Philips Semiconductors The I2C-bus and how to use it (including specifications) 1995 update 1.0 THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS 1.1 Designer benefits I2C-bus compatible ICs allow a system design to rapidly progress directly from a functional block diagram to a prototype. Moreover, since they `clip' directly onto the I2C-bus without any additional external interfacing, they allow a prototype system to be modified or upgraded simply by `clipping' or `unclipping' ICs to or from the bus. In consumer electronics, telecommunications and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes: * Some intelligent control, usually a single-chip microcontroller * General-purpose circuits like LCD drivers, remote I/O ports, RAM, Here are some of the features of I2C-bus compatible ICs which are particularly attractive to designers: * Functional blocks on the block diagram correspond with the actual EEPROM, or data converters * Application-oriented circuits such as digital tuning and signal ICs; designs proceed rapidly from block diagram to final schematic processing circuits for radio and video systems, or DTMF generators for telephones with tone dialling. * No need to design bus interfaces because the I2C-bus interface is To exploit these similarities to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the Inter IC or I2C-bus. At present, Philips' IC range includes more than 150 CMOS and bipolar I2C-bus compatible types for performing functions in all three of the previously mentioned categories. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus. This design concept solves the many interfacing problems encountered when designing digital control circuits. already integrated on-chip * Integrated addressing and data-transfer protocol allow systems to be completely software-defined * The same IC types can often be used in many different applications * Design-time reduces as designers quickly become familiar with the frequently used functional blocks represented by I2C-bus compatible ICs * ICs can be added to or removed from * Fault diagnosis and debugging are simple; malfunctions can be Here are some of the features of the I2C-bus: * Only two bus lines are required; a serial data line (SDA) and a immediately traced * Software development time can be reduced by assembling a serial clock line (SCL) * Each device connected to the bus is software addressable by a library of reusable software modules. unique address and simple master/ slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers In addition to these advantages,the CMOS ICs in the I2C-bus compatible range offer designers special features which are particularly attractive for portable equipment and battery-backed systems. * It's a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer They all have: * Extremely low current consumption * High noise immunity * Wide supply voltage range * Wide operating temperature range. * Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the standard mode or up to 400 kbit/s in the fast mode * On-chip filtering rejects spikes on the bus data line to preserve data integrity * The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400 pF. Figure 1 shows two examples of I2C-bus applications. April 1995 a system without affecting any other circuits on the bus 1 Philips Semiconductors The I2C-bus and how to use it (including specifications) SDA SCL MICROCONTROLLER PCB83C528 PLL SYNTHESIZER TSA5512 NON-VOLATILE MICROMEMORY CONTROLLER PCF8582E PCB83C528 M/S COLOUR DECODER TDA9160A MICROSTEREO/DUAL CONTROLLER SOUND DECODER PCB83C528 TDA9840 SDA SCL DTMF GENERATOR PICTURE SIGNAL IMPROVEMENT PCD3311 TDA4670 LINE INTERFACE MICROHI-FI CONTROLLER AUDIO PROCESSOR PCB83C528 TDA9860 PCA1070 ADPCM MICROCONTROLLER VIDEO PROCESSOR PCD5032 PCB83C528 TDA4685 BURST MODE CONTROLLER MICROSINGLE-CHIP CONTROLLER TEXT PCD5042 PCB83C528 SAA52XX MICROMICROCONTROLLER CONTROLLER ON-SCREEN DISPLAY PCB83C528 P80CLXXX PCA8510 (a) (b) SU00626 I2C-bus Figure 1. Two examples of applications (a) a high performance highly-integrated TV set; (b) DECT cordless phone base-station April 1995 2 Philips Semiconductors The I2C-bus and how to use it (including specifications) construction of equipment variants and easy upgrading to keep designs up-to-date. In this way, an entire family of equipment can be developed around a basic model. Upgrades for new equipment, or enhanced-feature models (i.e. extended memory, remote control, etc.) can then be produced simply by clipping the appropriate ICs onto the bus. If a larger ROM is needed, it's simply a matter of selecting a microcontroller with a larger ROM from our comprehensive range. As new ICs supersede older ones, it's easy to add new features to equipment or to increase its performance by simply unclipping the outdated IC from the bus and clipping on its successor. 1.2 Manufacturer benefits I2C-bus compatible ICs don't only assist designers, they also give a wide range of benefits to equipment manufacturers because: * The simple 2-wire serial I2C-bus minimizes interconnections so ICs have fewer pins and there are not so many PCB tracks; result -- smaller and less expensive PCBs * The completely integrated I2C-bus protocol eliminates the need for address decoders and other `glue logic' * The multi-master capability of the I2C-bus allows rapid testing and alignment of end-user equipment via external connections to an assembly-line computer * The availability of 1.3 The ACCESS.bus Another attractive feature of the I2C-bus for designers and manufacturers is that its simple 2-wire nature and capability of software addressing make it an ideal platform for the ACCESS.bus (Figure 2). This is a lower-cost alternative for an RS-232C interface for connecting peripherals to a host computer via a simple 4-pin connector (see Section 19.0). I2C-bus compatible ICs in SO (small outline), VSO (very small outline) as well as DIL packages reduces space requirements even more. These are just some of the benefits. In addition, I2C-bus compatible ICs increase system design flexibility by allowing simple SU00311A Figure 2. The ACCESS.bus -- a low-cost alternative to an RS-232C interface April 1995 3 Philips Semiconductors The I2C-bus and how to use it (including specifications) 2.0 INTRODUCTION TO THE I2C-BUS SPECIFICATION data loss and blockage of information. Fast devices must be able to communicate with slow devices. The system must not be dependent on the devices connected to it, otherwise modifications or improvements would be impossible. A procedure has also to be devised to decide which device will be in control of the bus and when. And, if different devices with different clock speeds are connected to the bus, the bus clock source must be defined. All these criteria are involved in the specification of the I2C-bus. For 8-bit digital control applications, such as those requiring microcontrollers, certain design criteria can be established: * A complete system usually consists of at least one microcontroller and other peripheral devices such as memories and I/O expanders * The cost of connecting the various devices within the system must be minimized 3.0 THE I2C-BUS CONCEPT * A system that performs a control function doesn't require The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognised by a unique address -- whether it's a microcontroller, LCD driver, memory or keyboard interface -- and can operate as either a transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table 1). A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave. high-speed data transfer * Overall efficiency depends on the devices chosen and the nature of the interconnecting bus structure. In order to produce a system to satisfy these criteria, a serial bus structure is needed. Although serial buses don't have the throughput capability of parallel buses, they do require less wiring and fewer IC connecting pins. However, a bus is not merely an interconnecting wire, it embodies all the formats and procedures for communication within the system. Devices communicating with each other on a serial bus must have some form of protocol which avoids all possibilities of confusion, Table 1. Definition of I2C-bus terminology TERM DESCRIPTION Transmitter The device which sends the data to the bus Receiver The device which receives the data from the bus Master The device which initiates a transfer, generates clock signals and terminates a transfer Slave The device addressed by a master Multi-master More than one master can attempt to control the bus at the same time without corrupting the message Arbitration Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted Synchronization Procedure to synchronize the clock signals of two or more devices MICROCONTROLLER A LCD DRIVER STATIC RAM OR EEPROM SDA SCL GATE ARRAY ADC MICROCONTROLLER B SU00385 Figure 3. Example of an I2C-bus configuration using two microcontrollers April 1995 4 Philips Semiconductors The I2C-bus and how to use it (including specifications) The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually micro-controllers, let's consider the case of a data transfer between two microcontrollers connected to the I2C-bus (Figure 3). This highlights the master-slave and receiver-transmitter relationships to be found on the I2C-bus. It should be noted that these relationships are not permanent, but only depend on the direction of data transfer at that time. The transfer of data would proceed as follows: transfer at the same time. To avoid the chaos that might ensue from such an event -- an arbitration procedure has been developed. This procedure relies on the wired-AND connection of all I2C interfaces to the I2C-bus. If two or more masters try to put information onto the bus, the first to produce a `one' when the other produces a `zero' will lose the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired-AND connection to the SCL line (for more detailed information concerning arbitration see Section 7.0). 1. Suppose microcontroller A wants to send information to microcontroller B: - microcontroller A (master), addresses microcontroller B (slave) - microcontroller A (master-transmitter), sends data to microcontroller B (slave-receiver) - microcontroller A terminates the transfer. Generation of clock signals on the I2C-bus is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding-down the clock line, or by another master when arbitration occurs. 2. If microcontroller A wants to receive information from microcontroller B: - microcontroller A (master) addresses microcontroller B (slave) - microcontroller A (master-receiver) receives data from microcontroller B (slave-transmitter) - microcontroller A terminates the transfer. 4.0 GENERAL CHARACTERISTICS Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull-up resistor (see Figure 4). When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector in order to perform the wired-AND function. Data on the I2C-bus can be transferred at a rate up to 100 kbit/s in the standard-mode, or up to 400 kbit/s in the fast-mode. The number of interfaces connected to the bus is solely dependent on the bus capacitance limit of 400pF. Even in this case, the master (microcontroller A) generates the timing and terminates the transfer. The possibility of connecting more than one microcontroller to the I2C-bus means that more than one master could try to initiate a data +VDD PULL-UP RESISTORS RP RP SDA (SERIAL DATA LINE) SCL (SERIAL CLOCK LINE SCLK SCLK SCLKN1 OUT DATAN1 OUT SCLK IN SCLKN2 OUT DATA IN DATAN2 OUT SCLK IN DEVICE 1 DATA IN DEVICE 2 Figure 4. Connection of I2C-bus devices to the I2C-bus April 1995 5 SU00386 Philips Semiconductors The I2C-bus and how to use it (including specifications) 5.0 BIT TRANSFER Due to the variety of different technology devices (CMOS, NMOS, bipolar) which can be connected to the I2C-bus, the levels of the logical `0' (LOW) and `1' (HIGH) are not fixed and depend on the associated level of VDD (see Section 15.0 for Electrical Specifications). One clock pulse is generated for each data bit transferred. SDA SCL DATA LINE STABLE: DATA VALID CHANGE OF DATA ALLOWED 5.1 Data validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see Figure 5). SU00361 Figure 5. Bit transfer on the I2C-bus 5.2 START and STOP conditions Within the procedure of the I2C-bus, unique situations arise which are defined as START and STOP conditions (see Figure 6). SDA SDA A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. SCL SCL S P START CONDITION START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. This bus free situation is specified in Section 15.0. STOP CONDITION SU00362 Figure 6. START and STOP conditions Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period in order to sense the transition. April 1995 6 Philips Semiconductors The I2C-bus and how to use it (including specifications) The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse (Figure 8). Of course, set-up and hold times (specified in Section 15.0) must also be taken into account. 6.0 TRANSFERRING DATA 6.1 Byte format Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (Figure 7). If a receiver can't receive another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the transmitter into a wait state. Data transfer then continues when the receiver is ready for another byte of data and releases clock line SCL. Usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte has been received, except when the message starts with a CBUS address (see Section 9.1.3). When a slave-receiver doesn't acknowledge the slave address (for example, it's unable to receive because it's performing some real-time function), the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. In some cases, it's permitted to use a different format from the I2C-bus format (for CBUS compatible devices for example). A message which starts with such an address can be terminated by generation of a STOP condition, even during the transmission of a byte. In this case, no acknowledge is generated (see Section 9.1.3). If a slave-receiver does acknowledge the slave address but, some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition. 6.2 Acknowledge If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition. Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. SDA MSB SCL S 1 ACKNOWLEDGEMENT SIGNAL FROM RECEIVER 2 7 8 ACKNOWLEDGEMENT SIGNAL FROM RECEIVER 9 1 2 3-8 9 ACK START CONDITION P ACK BYTE COMPLETE, INTERRUPT WITHIN RECEIVER CLOCK LINE HELD LOW WHILE INTERRUPTS ARE SERVICED STOP CONDITION SU00363 Figure 7. Data transfer on the I2C-bus DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S 1 2 7 8 9 START CONDITION CLOCK PULSE FOR ACKNOWLEDGMENT Figure 8. Acknowledge on the I2C-bus April 1995 7 SU00387 Philips Semiconductors The I2C-bus and how to use it (including specifications) WAIT STATE START COUNTING HIGH PERIOD CLK 1 COUNTER RESET CLK 2 SCL SU00388 Figure 9. Clock synchronization during the arbitration procedure Transmitter 1 Loses Arbitration DATA 1 SDA DATA 1 DATA 2 SDA SCL S SU00389 Figure 10. Arbitration procedure of two masters 7.0 ARBITRATION AND CLOCK GENERATION 7.2 Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time (tHD;STA) of the START condition which results in a defined START condition to the bus. 7.1 Synchronization All masters generate their own clock on the SCL line to transfer messages on the I2C-bus. Data is only valid during the HIGH period of the clock. A defined clock is therefore needed for the bit-by-bit arbitration procedure to take place. Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output stage because the level on the bus doesn't correspond to its own level. Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and, once a device clock has gone LOW, it will hold the SCL line in that state until the clock HIGH state is reached (Figure 9). However, the LOW to HIGH transition of this clock may not change the state of the SCL line if another clock is still within its LOW period. The SCL line will therefore be held LOW by the device with the longest LOW period. Devices with shorter LOW periods enter a HIGH wait-state during this time. Arbitration can continue for many bits. Its first stage is comparison of the address bits (addressing information is in Sections 9.0 and 13.0). If the masters are each trying to address the same device, arbitration continues with comparison of the data. Because address and data information on the I2C-bus is used for arbitration, no information is lost during this process. A master which loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration. When all devices concerned have counted off their LOW period, the clock line will be released and go HIGH. There will then be no difference between the device clocks and the state of the SCL line, and all the devices will start counting their HIGH periods. The first device to complete its HIGH period will again pull the SCL line LOW. If a master also incorporates a slave function and it losesarbitration during the addressing stage, it's possible that the winning master is trying to address it. The losing master must therefore switch over immediately to its slave-receiver mode. In this way, a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period. April 1995 Figure 10 shows the arbitration procedure for two masters. Of course, more may be involved (depending on how many masters are connected to the bus). The moment there is a difference 8 Philips Semiconductors The I2C-bus and how to use it (including specifications) On the bit level, a device such as a microcontroller without, or with only a limited hardware I2C interface on-chip can slow down the bus clock by extending each clock LOW period. The speed of any master is thereby adapted to the internal operating rate of this device. between the internal data level of the master generating DATA 1 and the actual level on the SDA line, its data output is switched off, which means that a HIGH output level is then connected to the bus. This will not affect the data transfer initiated by the winning master. Since control of the I2C-bus is decided solely on the address and data sent by competing masters, there is no central master, nor any order of priority on the bus. 8.0 FORMATS WITH 7-BIT ADDRESSES Special attention must be paid if, during a serial transfer, the arbitration procedure is still in progress at the moment when a repeated START condition or a STOP condition is transmitted to the I2C-bus. If it's possible for such a situation to occur, the masters involved must send this repeated START condition or STOP condition at the same position in the format frame. In other words, arbitration isn't allowed between: - A repeated START condition and a data bit - A STOP condition and a data bit - A repeated START condition and a STOP condition. Data transfers follow the format shown in Figure 11. After the START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) -- a `zero' indicates a transmission (WRITE), a `one' indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer. Possible data transfer formats are: - Master-transmitter transmits to slave-receiver. The transfer direction is not changed (Figure 12) - Master reads slave immediately after first byte (Figure 13). At the moment of the first acknowledge, the master-transmitter becomes a master-receiver and the slave-receiver becomes a slave-transmitter. This acknowledge is still generated by the slave. The STOP condition is generated by the master - Combined format (Figure 14). During a change of direction within a transfer, the START condition and the slave address are both repeated, but with the R/W bit reversed. If a master receiver sends a repeated START condition, it has previously sent a not acknowledge (A). 7.3 Use of the clock synchronizing mechanism as a handshake In addition to being used during the arbitration procedure, the clock synchronization mechanism can be used to enable receivers to cope with fast data transfers, on either a byte level or a bit level. On the byte level, a device may be able to receive bytes of data at a fast rate, but needs more time to store a received byte or prepare another byte to be transmitted. Slaves can then hold the SCL line LOW after reception and acknowledgement of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure. SDA SCL 1-7 8 9 ADDRESS R/W ACK 1-7 8 9 1-7 8 9 S P DATA ACK START CONDITION DATA ACK STOP CONDITION SU00365 Figure 11. A complete data transfer April 1995 9 Philips Semiconductors The I2C-bus and how to use it (including specifications) II IIIII IIIIIIII II II IIIII IIIIIIII II IIIII IIIIIIII II II II S SLAVE ADDRESS R/W A DATA A DATA A/A P DATA TRANSFERRED (n BYTES + ACKNOWLEDGE) `0' (WRITE) FROM MASTER TO SLAVE A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) S = START CONDITION P = STOP CONDITION FROM SLAVE TO MASTER SU00627 Figure 12. A master-transmitter addresses a slave receiver with a 7-bit address. The transfer direction is not changed II IIIII II II II II II IIIII II II II II 1 S SLAVE ADDRESS R/W A DATA A DATA A P DATA TRANSFERRED (n BYTES + ACKNOWLEDGE) (READ) SU00628 Figure 13. A master reads a slave immediately after the first byte III IIIII II III IIIII II S SLAVE ADDRESS R/W A READ OR WRITE DATA A/A (n BYTES + ACK.) * II IIIII II II IIIII II Sr SLAVE ADDRESS READ OR WRITE Sr = REPEATED START CONDITION R/W A DATA A/A (n BYTES + ACK.) * II II P DIRECTION OF TRANSFER MAY CHANGE AT THIS POINT * TRANSFER DIRECTION OF DATA AND ACKNOWLEDGE BITS DEPENDS ON R/W BITS. SU00629 Figure 14. Combined format NOTES: 1. Combined formats can be used, for example, to control a serial memory. During the first data byte, the internal memory location has to be written. After the START condition and slave address is repeated, data can be transferred. 2. All decisions on auto-increment or decrement of previously accessed memory locations etc. are taken by the designer of the device. 3. Each byte is followed by an acknowledgement bit as indicated by the A or A blocks in the sequence. 4. I2C-bus compatible devices must reset their bus logic on receipt of a START or repeated START condition such that they all anticipate the sending of a slave address. April 1995 10 Philips Semiconductors The I2C-bus and how to use it (including specifications) 9.0 7-BIT ADDRESSING (SEE SECTION 13.0 FOR 10-BIT ADDRESSING) Table 2. Definition of bits in the first byte SLAVE ADDRESS R/ bit 0000 000 0 General call address 0000 000 1 START byte 0000 001 X CBUS address 0000 010 X Address reserved for different bus format 9.1 Definition of bits in the first byte 0000 011 X Reserved for future purposes The first seven bits of the first byte make up the slave address (Figure15). The eighth bit is the LSB (least significant bit). It determines the direction of the message. A `zero' in the least significant position of the first byte means that the master will write information to a selected slave. A `one' in this position means that the master will read information from the slave. 0000 1XX X 1111 1XX X 1111 0XX X The addressing procedure for the I2C-bus is such that the first byte after the START condition usually determines which slave will be selected by the master. The exception is the `general call' address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. However, devices can be made to ignore this address. The second byte of the general call address then defines the action to be taken. This procedure is explained in more detail in Section 9.1.1. MSB DESCRIPTION 10-bit slave addressing NOTES: 1. No device is allowed to acknowledge at the reception of the START byte. 2. The CBUS address has been reserved to enable the inter-mixing of CBUS compatible and I2C-bus compatible devices in the same system. I2C-bus compatible devices are not allowed to respond on reception of this address. 3. The address reserved for a different bus format is included to enable I2C and other protocols to be mixed. Only I2C-bus compatible devices that can work with such formats and protocols are allowed to respond to this address. LSB R/W SLAVE ADDRESS SU00630 9.1.1 General call address The general call address is for addressing every device connected to the I2C-bus. However, if a device doesn't need any of the data supplied within the general call structure, it can ignore this address by not issuing an acknowledgement. If a device does require data from a general call address, it will acknowledge this address and behave as a slave-receiver. The second and following bytes will be acknowledged by every slave-receiver capable of handling this data. A slave which cannot process one of these bytes must ignore it by not acknowledging. The meaning of the general call address is always specified in the second byte (Figure 16). Figure 15. The first byte after the START procedure When an address is sent, each device in a system compares the first seven bits after the START condition with its address. If they match, the device considers itself addressed by the master as a slave-receiver or slave-transmitter, depending on the R/W bit. A slave address can be made-up of a fixed and a programmable part. Since it's likely that there will be several identical devices in a system, the programmable part of the slave address enables the maximum possible number of such devices to be connected to the I2C-bus. The number of programmable address bits of a device depends on the number of pins available. For example, if a device has 4 fixed and 3 programmable address bits, a total of 8 identical devices can be connected to the same bus. There are two cases to consider: * When the least significant bit B is a `zero' * When the least significant bit B is a `one'. When bit B is a `zero'; the second byte has the following definition: - 00000110 (H`06'). Reset and write programmable part of slave address by hardware. On receiving this 2-byte sequence, all devices designed to respond to the general call address will reset and take in the programmable part of their address. Precautions have to be taken to ensure that a device is not pulling down the SDA or SCL line after applying the supply voltage, since these low levels would block the bus - 00000100 (H`04'). Write programmable part of slave address by hardware. All devices which define the programmable part of their address by hardware (and which respond to the general call address) will latch this programmable part at the reception of this two byte sequence. The device will not reset. - 00000000 (H`00'). This code is not allowed to be used as the second byte. The I2C-bus committee coordinates allocation of I2C addresses. Further information can be obtained from the Philips representatives listed on the back cover. Two groups of eight addresses (0000XXX and 1111XXX) are reserved for the purposes shown in Table 2. The bit combination 11110XX of the slave address is reserved for 10-bit addressing (see Section 13.0). Sequences of programming procedure are published in the appropriate device data sheets. The remaining codes have not been fixed and devices must ignore them. April 1995 11 Philips Semiconductors The I2C-bus and how to use it (including specifications) direct the information from the hardware master. If the hardware master can also act as a slave, the slave address is identical to the master address. When bit B is a `one'; the 2-byte sequence is a `hardware general call'. This means that the sequence is transmitted by a hardware master device, such as a keyboard scanner, which cannot be programmed to transmit a desired slave address. Since a hardware master doesn't know in advance to which device the message has to be transferred, it can only generate this hardware general call and its own address -- identifying itself to the system (Figure 17). In some systems, an alternative could be that the hardware master transmitter is set in the slave-receiver mode after the system reset. In this way, a system configuring master can tell the hardware master-transmitter (which is now in slave-receiver mode) to which address data must be sent (Figure 18). After this programming procedure, the hardware master remains in the master-transmitter mode. The seven bits remaining in the second byte contain the address of the hardware master. This address is recognised by an intelligent device (e.g. a microcontroller) connected to the bus which will then LSB 0 0 0 0 0 0 0 0 A X X X X X X X B A SECOND BYTE FIRST BYTE (GENERAL CALL ADDRESS SU00631 Figure 16. General call address format II IIIIIIIIII IIIIIIIIII II IIIIIIIIII IIIIIIIIII S 00000000 A MASTER ADDRESS 1 A DATA A DATA A P (B) GENERAL CALL ADDRESS SECOND BYTE (n BYTES + ACK.) SU00632 Figure 17. Data transfer from a hardware master-transmitter II IIIIIII IIIIIIIIIII IIII II IIIIIII IIIIIIIIIII IIII II IIIIIIIII IIIIIIIIII II IIIIIIIII IIIIIIIIII S SLAVE ADDR. H/W MASTER R/W DUMP ADDR. FOR H/W MASTER A X A P WRITE (a) S DUMP ADDR. FROM H/W MASTER R/W A WRITE DATA A DATA A/A P (n BYTES + ACK.) (b) SU00633 Figure 18. Data transfer by a hardware-transmitter capable of dumping data directly to slave devices (a) Configuring master sends dump address to hardware master (b) Hardware master dumps data to selected slave April 1995 12 Philips Semiconductors The I2C-bus and how to use it (including specifications) A hardware receiver will reset on receipt of the repeated START condition Sr and will therefore ignore the START byte. 9.1.2 START byte Microcontrollers can be connected to the I2C-bus in two ways. A microcontroller with an on-chip hardware I2C-bus interface can be programmed to be only interrupted by requests from the bus. When the device doesn't have such an interface, it must constantly monitor the bus via software. Obviously, the more times the microcontroller monitors, or polls the bus, the less time it can spend carrying out its intended function. There is therefore a speed difference between fast hardware devices and a relatively slow microcontroller which relies on software polling. An acknowledge-related clock pulse is generated after the START byte. This is present only to conform with the byte handling format used on the bus. No device is allowed to acknowledge the START byte. 9.1.3 CBUS compatibility CBUS receivers can be connected to the I2C-bus. However, a third bus line called DLEN must then be connected and the acknowledge bit omitted. Normally, I2C transmissions are sequences of 8-bit bytes; CBUS compatible devices have different formats. In this case, data transfer can be preceded by a start procedure which is much longer than normal (Figure 19). The start procedure consists of: - A START condition (S) - A START byte (00000001) - An acknowledge clock pulse (ACK) - A repeated START condition (Sr). In a mixed bus structure, I2C-bus devices must not respond to the CBUS message. For this reason, a special CBUS address (0000001X) to which no I2C-bus compatible device will respond, has been reserved. After transmission of the CBUS address, the DLEN line can be made active and a CBUS-format transmission (Figure 20) sent. After the STOP condition, all devices are again ready to accept data. After the START condition S has been transmitted by a master which requires bus access, the START byte (00000001) is transmitted. Another microcontroller can therefore sample the SDA line at a low sampling rate until one of the seven zeros in the START byte is detected. After detection of this LOW level on the SDA line, the microcontroller can switch to a higher sampling rate to find the repeated START condition Sr which is then used for synchronization. Master-transmitters can send CBUS formats after sending the CBUS address. The transmission is ended by a STOP condition, recognised by all devices. NOTE: If the CBUS configuration is known, and expansion with CBUS compatible devices isn't foreseen, the designer is allowed to adapt the hold time to the specific requirements of the device(s) used. DUMMY ACKNOWLEDGE (HIGH) SDA SCL S 1 2 7 8 9 Sr ACK START BYTE 00000001 SU00634 Figure 19. START byte procedure SDA SCL DLEN S START condition P CBUS address R/W bit ACK related clock pulse n - data bits CBUS address SU00635 Figure 20. Data format of transmissions with CBUS transmitter/receiver April 1995 13 Philips Semiconductors The I2C-bus and how to use it (including specifications) When devices with fixed input levels are mixed with devices with input levels related to VDD, the latter devices must be connected to one common supply line of 5 V 10% and must have pull-up resistors connected to their SDA and SCL pins as shown in Figure 23. 10.0 ELECTRICAL CHARACTERISTICS FOR I2C-BUS DEVICES The electrical specifications for the I/Os of I2C-bus devices and the characteristics of the bus lines connected to them are given in Tables 3 and 4 in Section 15.0. Input levels are defined in such a way that: - The noise margin on the LOW level is 0.1 VDD - The noise margin on the HIGH level is 0.2 VDD - As shown in Figure 24, series resistors (RS) of, e.g., 300 can be used for protection against high-voltage spikes on the SDA and SCL lines (due to flash-over of a TV picture tube, for example). I2C-bus devices with fixed input levels of 1.5 V and 3 V can each have their own appropriate supply voltage. Pull-up resistors must be connected to a 5V 10% supply (Figure 21). I2C-bus devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also connected (Figure 22). VDD2 - 4 ARE DEVICE DEPENDENT (e.g., 12V) RP VDD1 = 5V 10% VDD2 NMOS BiCMOS RP VDD3 CMOS VDD4 BIPOLAR SDA SCL SU00636 Figure 21. Fixed input level devices connected to the I2C-bus VDD = e.g., 3V RP CMOS RP CMOS CMOS CMOS SDA SCL SU00637 Figure 22. Devices with wide supply voltage range connected to the I2C-bus VDD2, 3 ARE DEVICE DEPENDENT (e.g., 12V) VDD1 = 5V 10% RP RP CMOS CMOS VDD2 VDD3 NMOS BIPOLAR SDA SCL SU00638 Figure 23. Devices with input levels related to VDD (supply VDD1) mixed with fixed input level devices (supply VDD2, 3) on the I2C-bus RS VDD VDD I2C DEVICE I2C DEVICE RS RS RP RP RS SDA SCL SU00639 Figure 24. Series resistors (RS) for protection against high-voltage spikes April 1995 14 Philips Semiconductors The I2C-bus and how to use it (including specifications) limits the maximum value of Rs. Rs max as a function of Rp is shown in Figure 26. 10.1 Maximum and minimum values of resistors Rp and Rs For standard-mode I2C-bus devices, the values of resistors Rp and Rs in Figure 24 depend on the following parameters: - Supply voltage - Bus capacitance - Number of connected devices (input current + leakage current). The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of Rp due to the specified rise time. Figure 27 shows Rp max as a function of bus capacitance. The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 A. Due to the desired noise margin of 0.2VDD for the HIGH level, this input current limits the maximum value of Rp. This limit depends on VDD. The total HIGH level input current is shown as a function of Rp max in Figure 28. The supply voltage limits the minimum value of resistor Rp due to the specified minimum sink current of 3 mA at VOLmax = 0.4 V for the output stages. VDD as a function of Rp min is shown in Figure 25. The desired noise margin of 0.1VDD for the LOW level, minimum value RP (k) 6 10 RP (k) 5 VDD = 2.5V 5V 8 RS = 0 4 6 15V 3 4 max. RS 2 2 1 0 10V 0 4 8 12 0 16 0 400 VDD(V) 800 1200 1600 maximum value RS () SU00651 SU00652 Figure 25. Minimum value of RP as a function of supply voltage with the value of RS as a parameter Figure 26. Maximum value of RS as a function of the value of RP with supply voltage as a parameter maximum 20 value RP (k) maximum 20 value RP (k) 16 16 12 12 RS = 0 VDD = 15V 8 8 10V max. RS @ VDD = 5V 4 0 0 100 200 0 300 400 bus capacitance (pF) SU00653 2.5V 0 40 80 120 160 200 total high level input current (A) SU00654 Figure 27. Maximum value of RP as a function of bus capacitance for a standard-mode I2C-bus April 1995 5V 4 Figure 28. Total HIGH level input current as a function of the maximum value of RP with supply voltage as a parameter 15 Philips Semiconductors The I2C-bus and how to use it (including specifications) 11.0 EXTENSIONS TO THE I2C-BUS SPECIFICATION previous I2C-bus specification are unchanged. Changes to the previous I2C-bus specification are: - The maximum bit rate is increased to 400 kbit/s - Timing of the serial data (SDA) and serial clock (SCL) signals has been adapted. There is no need for compatibility with other bus systems such as CBUS because they cannot operate at the increased bit rate - The inputs of fast-mode devices must incorporate spike suppression and a Schmitt trigger at the SDA and SCL inputs - The output buffers of fast-mode devices must incorporate slope control of the falling edges of the SDA and SCL signals - If the power supply to a fast-mode device is switched off, the SDA and SCL I/O pins must be floating so that they don't obstruct the bus lines - The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter maximum permissible rise time for the fast-mode I2C-bus. For bus loads up to 200pF, the pull-up device for each bus line can be a resistor; for bus loads between 200pF and 400pF, the pull-up device can be a current source (3mA max.) or a switched resistor circuit as shown in Figure 37. The I2C-bus with a data transfer rate of up to 100 kbit/s and 7-bit addressing has now been in existence for more than ten years with an unchanged specification. The concept is accepted world-wide as a de facto standard and hundreds of different types of I2C-bus compatible ICs are available from Philips and other suppliers. The I2C-bus specification is now extended with the following two features: * A fast-mode which allows a fourfold increase of the bit rate to 0 to 400 kbit/s * 10-bit addressing which allows the use of up to 1024 additional addresses. There are two reasons for these extensions to the I2C-bus specification: - New applications will need to transfer a larger amount of serial data and will therefore demand a higher bit rate than 100 kbit/s. Improved IC manufacturing technology now allows a fourfold speed increase without increasing the manufacturing cost of the interface circuitry - Most of the 112 addresses available with the 7-bit addressing scheme have been issued more than once. To prevent problems with the allocation of slave addresses for new devices, it is desirable to have more address combinations. About a tenfold increase of the number of available addresses is obtained with the new 10-bit addressing. 13.0 10-BIT ADDRESSING The 10-bit addressing does not change the format in the I2C-bus specification. Using 10 bits for addressing exploits the reserved combination 1111XXX for the first seven bits of the first byte following a START (S) or repeated START (Sr) condition as explained in Section 9.1. The 10-bit addressing does not affect the existing 7-bit addressing. Devices with 7-bit and 10-bit addresses can be connected to the same I2C-bus, and both 7-bit and 10-bit addressing can be used in a standard-mode system (up to 100 kbit/s) or a fast-mode system (up to 400 kbit/s). All new devices with an I2C-bus interface are provided with the fast-mode. Preferably, they should be able to receive and/or transmit at 400 kbit/s. The minimum requirement is that they can synchronize with a 400 kbit/s transfer; they can then prolong the LOW period of the SCL signal to slow down the transfer. Fast-mode devices must be downward-compatible which means that they must still be able to communicate with 0 to 100 kbit/s devices in a 0 to 100 kbit/s I2C-bus system. Although there are eight possible combinations of the reserved address bits 1111XXX, only the four combinations 11110XX are used for 10-bit addressing. The remaining four combinations 11111XX are reserved for future I2C-bus enhancements. Obviously, devices with a 0 to 100 kbit/s I2C-bus interface cannot be incorporated in a fast-mode I2C-bus system because, since they cannot follow the higher transfer rate, unpredictable states of these devices would occur. 13.1 Definition of bits in the first two bytes The 10-bit slave address is formed from the first two bytes following a START condition (S) or a repeated START condition (Sr). Slave devices with a fast-mode I2C-bus interface can have a 7-bit or a 10-bit slave address. However, a 7-bit address is preferred because it is the cheapest solution in hardware and it results in the shortest message length. Devices with 7-bit and 10-bit addresses can be mixed in the same I2C-bus system regardless of whether it is a 0 to 100 kbit/s standard-mode system or a 0 to 400 kbit/s fast-mode system. Both existing and future masters can generate either 7-bit or 10-bit addresses. The first seven bits of the first byte are the combination 11110XX of which the last two bits (XX) are the two most-significant bits (MSBs) of the 10-bit address; the eighth bit of the first byte is the R/W bit that determines the direction of the message. A `zero' in the least significant position of the first byte means that the master will write information to a selected slave. A `one' in this position means that the master will read information from the slave. If the R/W bit is `zero', then the second byte contains the remaining 8 bits (XXXXXXXX) of the 10-bit address. If the R/W bit is `one', then the next byte contains data transmitted from a slave to a master. 12.0 FAST-MODE In the fast-mode of the I2C-bus, the protocol, format, logic levels and maximum capacitive load for the SDA and SCL lines quoted in the April 1995 16 Philips Semiconductors The I2C-bus and how to use it (including specifications) is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or until it receives another repeated START condition (Sr) followed by a different slave address. After a repeated START condition (Sr), all the other slave devices will also compare the first seven bits of the first byte of the slave address (11110XX) with their own addresses and test the eighth (R/W) bit. However, none of them will be addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit devices) does not match) - Combined format. A master transmits data to a slave and then reads data from the same slave (Figure 31). The same master occupies the bus all the time. The transfer direction is changed after the second R/W bit - Combined format. A master transmits data to one slave and then transmits data to another slave (Figure 32). The same master occupies the bus all the time - Combined format. 10-bit and 7-bit addressing combined in one serial transfer (Figure 33). After each START condition (S), or each repeated START condition (Sr), a 10-bit or 7-bit slave address can be transmitted. Figure 33 shows how a master-transmits data to a slave with a 7-bit address and then transmits data to a second slave with a 10-bit address. The same master occupies the bus all the time. 13.2 Formats with 10-bit addresses Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. Possible data transfer formats are: - Master-transmitter transmits to slave-receiver with a 10-bit slave address. The transfer direction is not changed (Figure 29). When a 10-bit address follows a START condition, each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own address and tests if the eighth bit (R/W direction bit) is 0. It is possible that more than one device will find a match and generate an acknowledge (A1). All slaves that found a match will compare the eight bits of the second byte of the slave address (XXXXXXXX) with their own addresses, but only one slave will find a match and generate an acknowledge (A2). The matching slave will remain addressed by the master until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address - Master-receiver reads slave- transmitter with a 10-bit slave address. The transfer direction is changed after the second R/W bit (Figure 30). Up to and including acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. After the repeated START condition (Sr), a matching slave remembers that it was addressed before. This slave then checks if the first seven bits of the first byte of the slave address following Sr are the same as they were after the START condition (S), and tests if the eighth (R/W) bit is 1. If there III IIIII IIIIIIIIIII III II III IIIII IIIIIIIIIII III II 1 1 1 1 0 X X SLAVE ADDRESS 1st 7 BITS S 0 R/W A1 SLAVE ADDRESS 2nd BYTE A2 DATA A DATA A/A P (WRITE) SU00640 Figure 29. A master-transmitter addresses a slave-receiver with a 10-bit address II IIIIII IIIIIIIIII IIIIII II II II II II IIIIII IIIIIIIIII IIIIII II II II II 1 1 1 1 0 X X SLAVE ADDRESS 1st 7 BITS S 0 R/W 1 A1 SLAVE ADDRESS 2nd BYTE A2 1 1 1 0 X X SLAVE ADDRESS 1st 7 BITS Sr 1 R/W (WRITE) A3 DATA A DATA A P (READ) SU00641 Figure 30. A master-receiver addresses a lave-transmitter with a 10-bit address II IIIIII IIIIIIIIIII III II IIIIII IIIIIIIIIII III II IIIIII II II II II II IIIIII II II II II 1 S 1 1 1 0 X SLAVE ADDRESS 1st 7 BITS X 0 R/W A SLAVE ADDRESS 2nd BYTE A DATA A 1 (WRITE) 1 DATA 1 1 0 X SLAVE ADDRESS 1st 7 BITS Sr X A/A 1 R/W A DATA A DATA A P (READ) SU00642 Figure 31. Combined format. A master addresses a lave with a 10-bit address, then transmits data to this slave and reads data from this slave April 1995 17 Philips Semiconductors The I2C-bus and how to use it (including specifications) II IIIIII IIIIIIIIIII III II IIIIII IIIIIIII III III II IIIII IIIIIIII II III II II IIIII IIIIIIII II III II 1 S 1 1 1 0 X SLAVE ADDRESS 1st 7 BITS X 0 R/W A SLAVE ADDRESS 2nd BYTE 1 (WRITE) 1 1 1 0 A X DATA X DATA A/A 0 SLAVE ADDRESS 1st 7 BITS Sr A R/W A SLAVE ADDRESS 2nd BYTE A DATA A DATA A/A P (WRITE) SU00643 Figure 32. Combined format. A master transmits data to two slaves, both with 10-bit addresses II IIIIII IIIII II II IIIIII IIIII II II IIIIII IIIII II II IIIII IIIIIIII II III II II IIIII IIIIIIII II III II 0 S 7-BIT SLAVE ADDRESS R/W A DATA A 1 (WRITE) Sr 1 DATA 1 1 0 X A/A X 0 1st 7 BITS OF 10-BIT SLAVE ADDRESS R/W A 2nd BYTE OF 10-BIT SLAVE ADDRESS A DATA A DATA A/A P (WRITE) SU00644 Figure 33. Combined format. A master transmits data to two slaves, one with a 7-bit address, and one with a 10-bit address NOTES: 1. Combined formats can be used, for example, to control a serial memory. During the first data byte, the internal memory location has to be written. After the START condition and slave address is repeated, data can be transferred. 2. All decisions on auto-increment or decrement of previously accessed memory locations etc. are taken by the designer of the device. 3. Each byte is followed by an acknowledgement bit as indicated by the A or A blocks in the sequence. 4. I2C-bus compatible devices must reset their bus logic on receipt of a START or repeated START condition such that they all anticipate the sending of a slave address. Hardware masters can transmit their 10-bit address after a `general call'. In this case, the `general call' address byte is followed by two successive bytes containing the 10-bit address of the master-transmitter. The format is as shown in Figure 17 where the first DATA byte contains the eight least-significant bits of the master address. 14.0 GENERAL CALL ADDRESS AND START BYTE The 10-bit addressing procedure for the I2C-bus is such that the first two bytes after the START condition (S) usually determine which slave will be selected by the master. The exception is the `general call' address 00000000 (H`00'). Slave devices with 10-bit addressing will react to a `general call' in the same way as slave devices with 7-bit addressing (see Section 9.1.1). April 1995 The START byte 00000001 (H`01') can precede the 10-bit addressing in the same way as for 7-bit addressing (see Section 9.1.2). 18 Philips Semiconductors The I2C-bus and how to use it (including specifications) The minimum HIGH and LOW periods of the SCL clock specified in Table 4 determine the maximum bit transfer rates of 100 kbit/s for standard-mode devices and 400 kbit/s for fast mode devices. Standard-mode and fast-mode I2C-bus devices must be able to follow transfers at their own maximum bit rates, either by being able to transmit or receive at that speed or by applying the clock synchronization procedure described in Section 7.0 which will force the master into a wait state and stretch the LOW period of the SCL signal. Of course, in the latter case the bit transfer rate is reduced. 15.0 ELECTRICAL SPECIFICATIONS AND TIMING FOR I/O STAGES AND BUS LINES The I/O levels, I/O current, spike suppression, output slope control and pin capacitance for I2C-bus devices are given in Table 3. The I2C-bus timing is given in Table 4. Figure 34 shows the timing definitions for the I2C-bus. The noise margin for HIGH and LOW levels on the bus lines for fast-mode devices are the same as those specified in Section 10.0 for standard-mode I2C-bus devices. Table 3. Characteristics of the SDA and SCL I/O stages for I2C-bus devices PARAMETER SYMBOL LOW level input voltage: fixed input levels VDD-related input levels VIL HIGH level input voltage: fixed input levels VDD-related input levels VIH Hysteresis of Schmitt trigger inputs: fixed input levels VDD-related input levels Vhys Pulse width of spikes which must be suppressed by the input filter tSP LOW level output voltage (open drain or open collector): at 3 mA sink current at 6 mA sink current STANDARD-MODE DEVICES FAST-MODE DEVICES UNIT Min. Max. Min. Max. -0.5 -0.5 1.5 0.3VDD -0.5 -0.5 1.5 0.3VDD 3.0 0.7VDD *1) *1) 3.0 0.7VDD *1) *1) n/a n/a n/a n/a 0.2 0.05VDD - - n/a n/a 0 50 V V V ns V VOL1 VOL2 Output fall time from VIHmin to VILmax with a bus capacitance from 10 pF to 400 pF: with up to 3 mA sink current at VOL1 with up to 6 mA sink current at VOL2 tof Input current each I/O pin with an input voltage between 0.4 V and 0.9VDDmax Capacitance for each I/O pin 0 n/a 0.4 n/a 0 0 0.4 0.6 ns - n/a 2503) n/a 20 + 0.1Cb2) 20 + 0.1Cb2) 250 2503) Ii -10 10 -104) 104) A Ci - 10 - 10 pF n/a = not applicable 1. Maximum VIH = VDDmax + 0.5 V 2. Cb = capacitance of one bus line in pF. 3. The maximum tf for the SDA and SCL bus lines quoted in Table 4 (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This allows series protection resistors (Rs)to be connected between the SDA/SCL pins and the SDA/SCL bus lines as shown in Figure 37 without exceeding the maximum specified tf. 4. I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VDD is switched off. April 1995 19 Philips Semiconductors The I2C-bus and how to use it (including specifications) Table 4. Characteristics of the SDA and SCL bus lines for I2C-bus devices PARAMETER STANDARD-MODE I2C-BUS SYMBOL Min. Max. FAST-MODE I2C-BUS UNIT Min. Max. SCL clock frequency fSCL 0 100 0 400 kHz Bus free time between a STOP and START condition tBUF 4.7 - 1.3 - s Hold time (repeated) START condition. After this period, the first clock pulse is generated tHD;STA 4.0 - 0.6 - s LOW period of the SCL clock tLOW 4.7 - 1.3 - s HIGH period of the SCL clock tHIGH 4.0 - 0.6 - s Set-up time for a repeated START condition tSU;STA 4.7 - 0.6 - s Data hold time: for CBUS compatible masters (see NOTE, Section 9.1.3) for I2C-bus devices tHD;DAT 5.0 - - - s 01) - 01) 0.92) s Data set-up time tSU;DAT 250 - 1003) Rise time of both SDA and SCL signals tr Fall time of both SDA and SCL signals tf Set-up time for STOP condition tSU;STO Capacitive load for each bus line Cb - 1000 - ns 20 + 0.1Cb 4) 300 ns 20 + 0.1Cb 4) 300 ns - 300 4.0 - 0.6 - s - 400 - 400 pF All values referred to VIHmin and VILmax levels (see Table 3). 1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 2. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 3. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT w250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. 4. Cb = total capacitance of one bus line in pF. SDA tBUF tLOW tR tF tHD;STA tSP SCL tHD;STA P S tSU;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STO P SU00645 Figure 34. Definition of timing on the I2C-bus April 1995 20 Philips Semiconductors The I2C-bus and how to use it (including specifications) 16.0 APPLICATION INFORMATION VP 16.1 Slope-controlled output stages of fast-mode I2C-bus devices The electrical specifications for the I/Os of I2C-bus devices and the characteristics of the bus lines connected to them are given in Tables 3 and 4 in Section 15.0. TO INPUT CIRCUIT R1 20k RP C1 Figures 35 and 36 show examples of output stages with slope control in CMOS and bipolar technology. The slope of the falling edge is defined by a Miller capacitor (C1) and a resistor (R1). The typical values for C1 and R1 are indicated on the diagrams. The wide tolerance for output fall time tof given in Table 3 means that the design is not critical. The fall time is only slightly influenced by the external bus load (Cb) and external pull-up resistor (Rp). However, the rise time (tr) specified in Table 4 is mainly determined by the bus load capacitance and the value of the pull-up resistor. VDD I/O SDA OR SCL BUS LINE 5pF T2 T1 Cb GND VSS SU00647 Figure 36. Slope-controlled output stage in bipolar technology 16.2 Switched pull-up circuit for fast-mode I2C-bus devices 1/4 HCT4066 The supply voltage (VDD) and the maximum output LOW level determine the minimum value of pull-up resistor Rp (see Section 10.1). For example, with a supply voltage of VDD = 5V 10% and VOLmax = 0.4V at 3mA, Rp min (5.5 - 0.4)/0.003 = 1.7 kW. As shown in Figure 38, this value of Rp limits the maximum bus capacitance to about 200pF to meet the maximum tr requirement of 300 ns. If the bus has a higher capacitance than this, a switched pull-up circuit as shown in Figure 37 can be used. VDD 5V 10% VCC nE P N GND nZ 1.3k RP2 1.7k RP1 SDA OR SCL BUS LINE 100 The switched pull-up circuit in Figure 37 is for a supply voltage of VDD = 5V 10% and a maximum capacitive load of 400pF. Since it is controlled by the bus levels, it needs no additional switching control signals. During the rising/falling edges, the bilateral switch in the HCT4066 switches pull-up resistor Rp2 on/off at bus levels between 0.8 V and 2.0 V. Combined resistors Rp1 and Rp2 can pull-up the bus line within the maximum specified rise time (tr) of 300 ns. The maximum sink current for the driving I2C-bus device will not exceed 6 mA at VOL2 = 0.6 V, or 3 mA at VOL1 = 0.4 V. RS 100 I/O N RS I/O Cb 400pF max. N VSS SU00648 Figure 37. Switched pull-up circuit Series resistors Rs are optional. They protect the I/O stages of the I2C-bus devices from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus line signals. The maximum value of Rs is determined by the maximum permitted voltage drop across this resistor when the bus line is switched to the LOW level in order to switch off Rp2. 7.5 maximum value Rp (k) 6.0 4.5 RS = 0 VDD P1 TO INPUT CIRCUIT R1 50k C1 N1 2pF VDD 3.0 RP I/O SDA OR SCL BUS LINE 0 N2 Cb VSS 0 100 200 300 400 bus capacitance (pF) VSS SU00649 Figure 38. Maximum value of RP as a function of bus capacitance for meeting the tR MAX requirement for a fast-mode I2C-bus SU00646 Figure 35. Slope-controlled output stage in CMOS technology April 1995 max. RS @ VDD = 5V 1.5 21 Philips Semiconductors The I2C-bus and how to use it (including specifications) If the bus lines are twisted-pairs, each bus line must be twisted with a VSS return. Alternatively, the SCL line can be twisted with a VSS return, and the SDA line twisted with a VDD return. In the latter case, capacitors must be used to decouple the VDD line to the VSS line at both ends of the twisted pairs. 16.3 Wiring pattern of the bus lines In general, the wiring must be so chosen that crosstalk and interference to/from the bus lines is minimized. The bus lines are most susceptible to crosstalk and interference at the HIGH level because of the relatively high impedance of the pull-up devices. If the bus lines are shielded (shield connected to VSS), interference will be minimized. However, the shielded cable must have low capacitive coupling between the SDA and SCL lines to minimize crosstalk. If the length of the bus lines on a PCB or ribbon cable exceeds 10cm and includes the VDD and VSS lines, the wiring pattern must be: SDA 16.4 Maximum and minimum values of resistors Rp and Rs for fast-mode I2C-bus devices VDD VSS The maximum and minimum values for resistors Rp and Rs connected to a fast-mode I2C-bus can be determined from Figure 25, 26 and 28 in Section 10.1. Because a fast-mode I2C-bus has faster rise times (tr) the maximum value of Rp as a function of bus capacitance is less than that shown in Figure 27. The replacement graph for Figure 27 showing the maximum value of Rp as a function of bus capacitance (Cb) for a fast mode I2C-bus is given in Figure 38. SCL If only the VSS line is included, the wiring pattern must be: SDA VSS SCL These wiring patterns also result in identical capacitive loads for the SDA and SCL lines. The VSS and VDD lines can be omitted if a PCB with a VSS and/or VDD layer is used. 17.0 DEVELOPMENT TOOLS 17.1 Development tools for 8048 and 8051-based systems PRODUCT DESCRIPTION OM1016 I2C-bus OM1018 manual for OM1016 OM1020 LCD and driver demonstration board OM4151 I2C-bus evaluation board (similar to OM1016 above but without infrared link). OM5027 I2C-bus evaluation board for low-voltage, low-power ICs & software demonstration board with microcontroller, LCD, LED, Par. I/O, SRAM, EEPROM, Clock, DTMF generator, AD/DA conversion, infrared link. 17.2 Development tools for 68000-based systems PRODUCT OM4160 OM4160/3 OM4160/3QFP DESCRIPTION Microcore-1 demonstration/evaluation board: SCC68070, 128K EPROM, 512K DRAM, I2C, RS-232C, VSC SCC66470, resident monitor Microcore-3 demonstration/evaluation board: 128K EPROM, 64K SRAM, I2C, RS-232C, 40 I/O (inc. 8051-compatible bus), resident monitor Microcore-3 demonstration/evaluation board for 9XC101 (QFP80 package) 17.3 17.3 Development tools for all systems PRODUCT OM1022 April 1995 DESCRIPTION I2C-bus analyzer. Hardware and software (runs on IBM or compatible PC) to experiment with and analyze the behaviour of the I2C-bus (includes documentation) 22 Philips Semiconductors The I2C-bus and how to use it (including specifications) 18.0 SUPPORT LITERATURE DATA HANDBOOKS Semiconductors for radio and audio systems IC01a 1995 IC01b 1995 Semiconductors for television and video systems IC02a 1995 IC02b 1995 IC02c 1995 Semiconductors for telecom systems IC03 1995 I2C Peripherals IC12 8048-based 8-bit microcontrollers IC14 1994 Wireless communications IC17 1995 Semiconductors for in-car electronics IC18 80C51-based 8-bit microcontrollers IC20 1995 68000-based 16-bit microcontrollers IC21 Desktop video IC22 1995 Brochures/leaflets/lab. reports I2C-bus compatible ICs and support overview I2C-bus control programs for consumer applications Microcontrollers, microprocessors and support overview Application notes for 80C51-based 8-bit microcontrollers OM5027 I2C-bus evaluation board for low-voltage, low-power ICs & software P90CL301 I2C driver routines User manual of Microsoft Pascal I2C-bus driver (MICDRV4.OBJ) User's guide to I2C-bus control programs April 1995 23 Philips Semiconductors The I2C-bus and how to use it (including specifications) 19.0 APPLICATION OF THE I2C-BUS IN THE ACCESS.bus SYSTEM As shown in Figure 39, the ACCESS.bus protocol comprises three levels: the I2C-bus protocol, the base protocol, and the application protocol. The ACCESS.bus (bus for connecting ACCESSory devices to a host system) is an I2C-bus based open-standard serial interconnect system jointly developed and defined by Philips and Digital Equipment Corporation. It is a lower-cost alternative to an RS-232C interface for connecting up to 14 inputs/outputs from peripheral equipment to a desk-top computer or workstation over a distance of up to eight metres. The peripheral equipment can be relatively low speed items such as keyboards, hand-held image scanners, cursor positioners, bar-code readers, digitizing tablets, card readers or modems. The base protocol is common to all ACCESS.bus devices and defines the format of the ACCESS.bus message. Unlike the I2C-bus protocol, it restricts masters to sending and slaves to receiving data. One item of appended information is a checksum for reliability control. The base protocol also specifies seven types of control and status messages which are used in the system configuration which assigns unique addresses to the peripherals without the need for setting jumpers or switches on the devices. The application protocol defines the message semantics that are specific to the three categories of peripheral device (keyboards, cursor locators, and text devices which generate character streams, e.g., card readers) which are at present envisaged. All that's required to implement an ACCESS.bus is an 8051-family microcontroller with an I2C-bus interface, and a 4-wire cable carrying a serial data (SDA) line, a serial clock (SCL) line, a ground wire and a 12V supply line (500mA max.) for powering the peripherals. Philips offers computer peripheral equipment manufacturers technical support, a wide range of I2C-bus devices and development kits for the ACCESS.bus. Hardware, software and marketing support is also offered by DEC. Important features of the ACCESS.bus are that the bit rate is only about 20% less than the maximum bit rate of the I2C-bus, and the peripherals don't need separate device drivers. Also, the protocol allows the peripherals to be changed by `hot-plugging' without re-booting. KEYBOARD PROTOCOL LOCATOR PROTOCOL TEXT PROTOCOL REAL-TIME CONTROL PROTOCOL SOFTWARE PROTOCOLS BASE PROTOCOL HARDWARE PROTOCOLS I2C PROTOCOL SU00650 Figure 39. ACCESS.bus protocol hierarchy April 1995 24