Product Folder Order Now Support & Community Tools & Software Technical Documents TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 TPS54540 4.5-V to 42-V Input, 5 A, Step Down DC-DC Converter with Eco-modeTM 1 Features 3 Description * The TPS54540 is a 42 V, 5 A, step down regulator with an integrated high side MOSFET. The device survives load dump pulses up to 45V per ISO 7637. Current mode control provides simple external compensation and flexible component selection. A low ripple pulse skip mode reduces the no load supply current to 146 A. Shutdown supply current is reduced to 2 A when the enable pin is pulled low. 1 * * * * * * * * * * High Efficiency at Light Loads with Pulse Skipping Eco-modeTM 92-m High-Side MOSFET 146 A Operating Quiescent Current and 2 A Shutdown Current 100 kHz to 2.5 MHz Fixed Switching Frequency Synchronizes to External Clock Low Dropout at Light Loads with Integrated BOOT Recharge FET Adjustable UVLO Voltage and Hysteresis 0.8 V 1% Internal Voltage Reference 8-Terminal HSOP with PowerPADTM Package -40C to 150C TJ Operating Range Create a Custom Design using the TPS54540 with the WEBENCH(R) Power Designer * A wide switching frequency range allows either efficiency or external component size to be optimized. Output current is limited cycle-by-cycle. Frequency foldback and thermal shutdown protects internal and external components during an overload condition. The TPS54540 is available in an 8-terminal thermally enhanced HSOP PowerPADTM package. 2 Applications * * * Undervoltage lockout is internally set at 4.3 V but can be increased using the enable pin. The output voltage start up ramp is internally controlled to provide a controlled start up and eliminate overshoot. Industrial Automation and Motor Control Vehicle Accessories: GPS, Entertainment USB Dedicated Charging Ports and Battery Chargers 12 V and 24 V Industrial, Automotive and Communications Power Systems Device Information PART NUMBER PACKAGE BODY SIZE TPS54540 HSOP (8) 4,89mm x 3,9mm spacer Simplified Schematic VIN Efficiency vs Load Current BOOT VIN 100 36 V to 12 V 95 TPS54540 SW COMP RT/CLK 90 VOUT FB Efficiency (%) EN 85 12 V to 3.3 V 80 12 V to 5 V 75 70 GND VOUT = 12 V, fsw = 800 kHz VOUT = 5 V and 3.3 V, fsw = 400 kHz 65 Copyright (c) 2017, Texas Instruments Incorporated 60 0 0.5 1 1.5 2 2.5 3 3.5 IO - Output Current (A) 4 4.5 5 C024 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 5 5 5 5 6 7 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 23 8 Application and Implementation ........................ 25 8.1 Application Information............................................ 25 8.2 Typical Application .................................................. 25 9 Power Supply Recommendations...................... 36 10 Layout................................................................... 37 10.1 Safe Operating Area ............................................. 37 10.2 Layout Guidelines ................................................. 38 10.3 Layout Example .................................................... 38 11 Device and Documentation Support ................. 39 11.1 11.2 11.3 11.4 11.5 11.6 Custom Design with WEBENCH(R) Tools .............. Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 39 39 39 39 39 39 12 Mechanical, Packaging, and Orderable Information ........................................................... 39 4 Revision History Changes from Revision A (March 2014) to Revision B Page * Added the WEBENCH information in the Features, Detailed Design Procedure, and Device Support sections .................. 1 * Changed the Handling Ratings table To ESD Ratings table.................................................................................................. 5 * Changed VIN MIN Value From: 4.5 V To: VO + VDO, and added Note 1 in the Recommended Operating Conditions .......... 5 * Deleted last graph: "5 V Start and Stop Voltage" from the Typical Characteristics ............................................................. 10 * Updated text and added Equation 1 in the Low Dropout Operation and Bootstrap Voltage (BOOT) ................................. 13 * Deleted text: "The start and stop voltage for a typical 5 V..." from the Low Dropout Operation and Bootstrap Voltage (BOOT) section..................................................................................................................................................................... 13 * Changed Equation 7 and Equation 8. ................................................................................................................................. 15 * Changed Equation 27 .......................................................................................................................................................... 26 * Added new section: Minimum VIN ......................................................................................................................................... 31 * Deleted 2 graphs named "Low Dropout Operation" from the Application Curves section .................................................. 33 Changes from Original (May 2013) to Revision A Page * Added Device Information table, Recommended Operating Conditions table, Pin Configuration and Functions section, Handling Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1 * Changed the Electrical Characteristics Conditions From: VIN = 4.5 to 60 V To: VIN = 4.5 to 42 V...................................... 6 * Changed the Operating: nonswitching supply current TEST CONDITIONS From: FB = 0.83 V To: FB = 0.9 V .................. 6 * Changed RT/CLK high threshold MAX value From: 1.7 V To: 2 V ....................................................................................... 6 * Changed the title of graph "5 V Start and Stop Voltage" to include a link to the Low Dropout Operation section. ............ 10 * Changed the FBD, removed the Logic block and Shutdown signal from the OV comparator ............................................. 12 * Changed VF = Forward Drop of the Catch Diode To: VD = Forward Drop of the Catch Diode .......................................... 14 * Deleted value TSW = 1 / Fsw from the list following Equation 2 ......................................................................................... 14 * Changed VB2SW = VBOOT + VF To: VB2SW = VBOOT + VD ........................................................................................... 14 * Changed VBOOT = (1.41 x VIN - 0.554 - VF / TSW - 1.847 x 103 x IB2SW) / (1.41 + 1 / Tsw) To: VBOOT = (1.41 x 2 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 VIN - 0.554 - VD x SW - 1.847 x 103 x IB2SW) / (1.41 + SW)............................................................................................... 14 * Deleted figure: "5V Start/Stop Voltage" ................................................................................................................................ 14 * Added a title to Figure 23 ..................................................................................................................................................... 14 * Changed the section title From: Selecting the Switching Frequency To: Accurate Current Limit Operation and Maximum Switching Frequency............................................................................................................................................ 16 * Changed text in the Synchronization to RT/CLK terminal section From: "0.5 V and higher than 1.7 V" To: "0.5 V and higher than 2 V" ................................................................................................................................................................... 17 * Changed Equation 33 From: (5.13V2 - 5 V2) To: 3.43 V2 - 3.3 V2) ...................................................................................... 28 * Changed Figure 36, VOUT From: 200 mV/div To 100 mV/div ............................................................................................ 33 * Changed Figure 38 , EN From: 1 V/div To: 2 V/div, VOUT From: 4 V/div To: 2 V/div, and Time = 2 ms/div To: Time = 20 ms/div ........................................................................................................................................................................... 33 * Changed Figure 39 , VOUT From: 4 V/div To: 2 V/div......................................................................................................... 33 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 3 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com 5 Pin Configuration and Functions HSOIC Package (Top View) BOOT 1 VIN 2 8 SW 7 GND PowerPAD 9 EN 3 6 COMP RT/CLK 4 5 FB Pin Functions TERMINAL NAME NO. I/O DESCRIPTION BOOT 1 O A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum required to operate the high side MOSFET, the output is switched off until the capacitor is refreshed. VIN 2 I Input supply voltage with 4.5 V to 42 V operating range. EN 3 I Enable terminal, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section. RT/CLK 4 I Resistor Timing and External Clock. An internal amplifier holds this terminal at a fixed voltage when using an external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming. FB 5 I Inverting input of the transconductance (gm) error amplifier. COMP 6 O Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components to this terminal. GND 7 - Ground SW 8 I The source of the internal high-side power MOSFET and switching node of the converter. Thermal Pad 9 - GND terminal must be electrically connected to the exposed pad on the printed circuit board for proper operation. 4 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VALUE MIN VIN -0.3 45 EN -0.3 8.4 BOOT Input voltage UNIT MAX 53 V FB -0.3 3 COMP -0.3 3 RT/CLK -0.3 3.6 -0.6 45 -2 45 Operating junction temperature, TJ -40 150 C Storage temperature, TSTG -65 150 C BOOT-SW Output voltage 8 SW SW, 10-ns Transient (1) V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VESD (1) (2) (3) (1) Human Body Model (HBM) ESD Stress Voltage (2) Charged Device Model (HBM) ESD Stress Voltage (3) VALUE UNIT 2000 V 500 V Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device. Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. terminals listed as 1000V may actually have higher performance. Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. terminals listed as 250V may actually have higher performance. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VIN Supply input voltage VO Output voltage IO Output current TJ Junction Temperature (1) MIN MAX VO + VDO 42 UNIT V 0.8 41.1 V 0 5 A -40 150 C See Equation 1 6.4 Thermal Information THERMAL METRIC (1) (2) TPS54540 DDA (8 PINS) UNIT JA Junction-to-ambient thermal resistance (standard board) 42.0 C/W JT Junction-to-top characterization parameter 5.9 C/W JB Junction-to-board characterization parameter 23.4 C/W JCtop Junction-to-case(top) thermal resistance 45.8 C/W JCbot Junction-to-case(bottom) thermal resistance 3.6 C/W JB Junction-to-board thermal resistance 23.4 v (1) (2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information. Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 5 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com 6.5 Electrical Characteristics TJ = -40C to 150C, VIN = 4.5 to 42 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 42 V 4.3 4.48 V SUPPLY VOLTAGE (VIN TERMINAL) Operating input voltage Internal undervoltage lockout threshold 4.5 Rising 4.1 Internal undervoltage lockout threshold hysteresis 325 mV Shutdown supply current EN = 0 V, 25C, 4.5 V VIN 42 V 2.25 4.5 Operating: nonswitching supply current FB = 0.9 V, TA = 25C 146 175 1.2 1.3 A ENABLE AND UVLO (EN TERMINAL) Enable threshold voltage Input current No voltage hysteresis, rising and falling 1.1 Enable threshold +50 mV -4.6 Enable threshold -50 mV Hysteresis current V A -0.58 -1.2 -1.8 -2.2 -3.4 -4.5 A 0.792 0.8 0.808 V 92 190 VOLTAGE REFERENCE Voltage reference HIGH-SIDE MOSFET On-resistance VIN = 12 V, BOOT-SW = 6 V m ERROR AMPLIFIER Input current Error amplifier transconductance (gM) -2 A < ICOMP < 2 A, VCOMP = 1 V Error amplifier transconductance (gM) during -2 A < ICOMP < 2 A, VCOMP = 1 V, VFB = 0.4 V soft-start Error amplifier dc gain VFB = 0.8 V Min unity gain bandwidth Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive COMP to SW current transconductance 50 nA 350 Mhos 77 Mhos 10,000 V/V 2500 kHz 30 A 17 A/V CURRENT LIMIT Current limit threshold All VIN and temperatures, Open Loop (1) 6.3 7.5 8.8 All temperatures, VIN = 12 V, Open Loop (1) 6.3 7.5 8.3 VIN = 12 V, TA = 25C, Open Loop (1) 7.1 7.5 7.9 A THERMAL SHUTDOWN Thermal shutdown Thermal shutdown hysteresis 176 C 12 C TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL) Switching frequency range using RT mode fSW Switching frequency 100 RT = 200 k Switching frequency range using CLK mode 450 160 RT/CLK high threshold 1.55 RT/CLK low threshold (1) 6 500 0.5 2500 kHz 550 kHz 2300 kHz 2 1.2 V V Open Loop current limit measured directly at the SW terminal and is independent of the inductor value and slope compensation. Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 6.6 Timing Requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENABLE AND UVLO (EN TERMINAL) Enable to COMP active VIN = 12 V, TA = 25C 540 s INTERNAL SOFT-START TIME Soft-Start Time fSW = 500 kHz, 10% to 90% 2.1 ms Soft-Start Time fSW = 2.5 MHz, 10% to 90% 0.42 ms HIGH-SIDE MOSFET On-resistance VIN = 12 V, BOOT-SW = 6 V 92 190 m TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL) Minimum CLK input pulse width RT/CLK falling edge to SW rising edge delay PLL lock in time 15 ns Measured at 500 kHz with RT resistor in series 55 ns Measured at 500 kHz 78 s 6.7 Typical Characteristics 0.814 VFB - Voltage Referance ( V) RDSON - On-State Resistance ( ) 0.25 0.2 0.15 0.1 0.05 BOOT-SW = 3 V 0.809 0.804 0.799 0.794 0.789 BOOT-SW = 6 V 0 0.784 50 25 0 25 50 75 100 125 TJ - Junction Temperature (C) 50 150 0 8.5 8.5 High Side Switch Current (A) 9 7.5 7 50 75 100 125 150 C026 Figure 2. Voltage Reference vs Junction Temperature 9 8 25 TJ - Junction Temperature (C) Figure 1. On Resistance vs Junction Temperature High Side Switch Current (A) 25 C025 40 C Series1 25 C Series2 150 C Series4 8 7.5 7 6.5 6.5 6 6 -50 0 -25 0 25 50 75 100 TJ - Junction Temperature (qC) 125 150 Figure 3. Switch Current Limit vs Junction Temperature 7 14 21 28 35 VI - Input Voltage (V) 42 C028 Figure 4. Switch Current Limit vs Input Voltage Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 7 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com 550 500 540 450 FSW - Switching Frequency (kHz) FS - Switching Frequency (kHz) Typical Characteristics (continued) 530 520 510 500 490 480 470 460 450 25 0 25 50 75 100 125 TJ - Junction Temperature (C) 300 250 200 150 100 50 150 200 300 400 500 600 700 800 900 RT/CLK - Resistance (k ) C029 1000 C030 Figure 5. Switching Frequency vs Junction Temperature Figure 6. Switching Frequency vs RT/CLK Resistance Low Frequency Range 2500 500 2300 450 2100 1900 400 gm (A/V) FSW - Switching Frequency (kHz) 350 0 50 1700 1500 1300 900 250 700 200 0 50 100 150 50 200 RT/CLK - Resistance (k ) EN - Threshold (V) 100 80 70 60 50 40 30 20 25 0 25 50 75 100 TJ - Junction Temperature (C) 125 150 50 75 100 125 150 C032 1.3 1.29 1.28 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.2 1.19 1.18 1.17 1.16 1.15 50 25 0 25 50 75 100 TJ - Junction Temperature (C) C033 Figure 9. EA Transconductance During Soft-Start vs Junction Temperature 25 Figure 8. EA Transconductance vs Junction Temperature 110 90 0 TJ - Junction Temperature (C) 120 50 25 C031 Figure 7. Switching Frequency vs RT/CLK Resistance High Frequency Range gm (A/V) 350 300 1100 500 8 400 125 150 C034 Figure 10. EN Terminal Voltage vs Junction Temperature Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 3.5 0.5 3.7 0.7 3.9 0.9 4.1 1.1 4.3 1.3 IEN (A) IEN (uA) Typical Characteristics (continued) 4.5 4.7 1.7 4.9 1.9 5.1 2.1 5.3 2.3 5.5 2.5 50 25 0 25 50 75 100 125 50 150 TJ - Junction Temperature (C) 25 0 100 % of Nominal Switching Frequency 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 50 75 100 125 150 C036 Figure 12. EN Terminal Current vs Junction Temperature 2.5 2.7 25 TJ - Junction Temperature (C) C035 Figure 11. EN Terminal Current vs Junction Temperature IEN - Hysteresis (A) 1.5 Series2 VSENSE Falling VSENSE Rising Series4 75 50 25 0 4.5 50 25 0 25 50 75 100 125 0.0 150 TJ - Junction Temperature (C) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VSENSE (V) C037 Figure 13. EN Terminal Current Hysteresis vs Junction Temperature 0.8 C038 Figure 14. Switching Frequency vs VSENSE 3 3 2.5 2.5 2 2 IVIN (A) IVIN (A) TJ =Series2 25C 1.5 1.5 1 1 0.5 0.5 0 0 50 25 0 25 50 75 100 125 150 TJ - Junction Temperature (C) 0 Figure 15. Shutdown Supply Current vs Junction Temperature 7 14 21 28 35 VIN - Input Voltage (V) C039 42 C040 Figure 16. Shutdown Supply Current vs Input Voltage (VIN) Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 9 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com Typical Characteristics (continued) 210 210 190 190 170 170 IVIN (A) IVIN (A) TJSeries2 = 25C 150 130 150 130 110 110 90 90 70 70 50 25 0 25 50 75 100 125 TJ - Junction Temperature (C) 0 150 28 35 42 C042 UVLO Start Switching UVLO Stop Switching 4.4 2.4 4.3 2.3 4.2 VIN (V) VI - BOOT-PH (V) 4.5 2.2 21 Figure 18. VIN Supply Current vs Input Voltage BOOT-PH UVLO Falling BOOT-PH UVLO Rising 2.5 14 VIN - Input Voltage (V) Figure 17. VIN Supply Current vs Junction Temperature 2.6 7 C041 4.1 2.1 4.0 2.0 3.9 1.9 3.8 3.7 1.8 50 25 0 25 50 75 100 TJ - Junction Temperature (C) 125 150 50 Figure 19. BOOT-SW UVLO vs Junction Temperature 25 0 25 50 75 100 TJ - Junction Temperature (C) C043 125 150 C044 Figure 20. Input Voltage UVLO vs Junction Temperature 10 12 12V,V,25C 25 C 9 Soft-Start Time (ms) 8 7 6 5 4 3 2 1 0 100 1500 1700 1900 2100 2300 2500 100 300 300 500 500700 700900 9001100 11001300 1300 1500 1700 1900 2100 2300 2500 Switching Frequency (kHz) C045 Figure 21. Soft-Start Time vs Switching Frequency 10 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 7 Detailed Description 7.1 Overview The TPS54540 is a 42 V, 5 A, step-down (buck) regulator with an integrated high side n-channel MOSFET. The device implements constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows either efficiency or size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground connected to the RT/CLK terminal. The device has an internal phase-locked loop (PLL) connected to the RT/CLK terminal that will synchronize the power switch turn on to a falling edge of an external clock signal. The TPS54540 has a default input start-up voltage of approximately 4.3 V. The EN terminal can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up current source enables operation when the EN terminal is floating. The operating current is 146 A under no load condition (not switching). When the device is disabled, the supply current is 2 A. The integrated 92 m high side MOSFET supports high efficiency power supply designs capable of delivering 5 amperes of continuous current to a load. The gate drive bias voltage for the integrated high side MOSFET is supplied by a bootstrap capacitor connected from the BOOT to SW terminals. The TPS54540 reduces the external component count by integrating the bootstrap recharge diode. The BOOT terminal capacitor voltage is monitored by a UVLO circuit which turns off the high side MOSFET when the BOOT to SW voltage falls below a preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54540 to operate at high duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the application. The minimum output voltage is the internal 0.8 V feedback reference. Output overvoltage transients are minimized by an Overvoltage Transient Protection (OVP) comparator. When the OVP comparator is activated, the high side MOSFET is turned off and remains off until the output voltage is less than 106% of the desired output voltage. The TPS54540 includes an internal soft-start circuit that slows the output rise time during start-up to reduce inrush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help maintain control of the inductor current. Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 11 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com 7.2 Functional Block Diagram EN VIN Thermal Shutdown UVLO Enable Comparator OV Shutdown Shutdown Logic Enable Threshold Boot Charge Voltage Reference Boot UVLO Minimum Clamp Pulse Skip Error Amplifier Current Sense PWM Comparator FB BOOT Logic Shutdown 6 Slope Compensation SW COMP Frequency Foldback Reference DAC for Soft- Start Maximum Clamp Oscillator with PLL 8/8/ 2012 A 0192789 GND POWERPAD RT/ CLK Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Fixed Frequency PWM Control The TPS54540 uses fixed frequency, peak current mode control with adjustable switching frequency. The output voltage is compared through external resistors connected to the FB terminal to an internal voltage reference by an error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output at the COMP terminal controls the high side power switch current. When the high side MOSFET switch current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP terminal voltage will increase and decrease as the output current increases and decreases. The device implements current limiting by clamping the COMP terminal voltage to a maximum level. The pulse skipping Eco-mode is implemented with a minimum voltage clamp on the COMP terminal. 7.3.2 Slope Compensation Output Current The TPS54540 adds a compensating ramp to the MOSFET switch current sense signal. This slope compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the high side switch is not affected by the slope compensation and remains constant over the full duty cycle range. 12 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 Feature Description (continued) 7.3.3 Pulse Skip Eco-mode The TPS54540 operates in a pulse skipping Eco-mode at light load currents to improve efficiency by reducing switching and gate drive losses. If the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV. When in Eco-mode, the COMP terminal voltage is clamped at 600 mV and the high side MOSFET is inhibited. Since the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the COMP terminal voltage. The high side MOSFET is enabled and switching resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to the regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal. During Eco-mode operation, the TPS54540 senses and controls peak switch current, not the average load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor value. The circuit in Figure 35 enters Eco-mode at about 18 mA output current. As the load current approaches zero, the device enters a pulse skip mode during which it draws only 146 A input quiescent current. 7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT) The TPS54540 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW terminals provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT capacitor is 0.1 F. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended for stable performance over temperature and voltage. When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54540 will operate at 100% duty cycle as long as the BOOT to SW terminal voltage is greater than 2.1V. When the voltage from BOOT to SW drops below 2.1V, the high side MOSFET is turned off and an integrated low side MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at high output voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V. Since the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode voltage and the printed circuit board resistance. Equation 1 calculates the minimum input voltage required to regulate the output voltage and ensure normal operation of the device. This calculation must include tolerance of the component specifications and the variation of these specifications at their maximum operating temperature in the application VIN min VOUT VF Rdc u IOUT 0.99 RDS on u IOUT VF where * * * VF = Schottky diode forward voltage Rdc = DC resistance of inductor and PCB RDS(on) = High-side MOSFET RDS(on) (1) During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time required to recharge the BOOT capacitor is longer than the high side off time associated with cycle by cycle PWM control. At heavy loads, the minimum input voltage must be increased to insure a monotonic startup. Equation 2 can be used to calculate the minimum input voltage for this condition. Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 13 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com Feature Description (continued) VOUT(max) = D(max) x (VIN(min) - IOUT(max) x RDS(on) + VD) - VD + IOUT(max) x Rdc where * * * * * * D(max) 0.9 IB2SW = 100 A VD = Forward Drop of the Catch Diode VB2SW = VBOOT + VD VBOOT = (1.41 x VIN - 0.554 - VD x fSW - 1.847 x 103 x IB2SW) / (1.41 + fSW) RDS(on) = 1 / (-0.3 x VB2SW2 + 3.577 x VB2SW - 4.246) (2) 7.3.5 Error Amplifier The TPS54540 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier compares the FB terminal voltage to the lower of the internal soft-start voltage or the internal 0.8 V voltage reference. The transconductance (gm) of the error amplifier is 350 A/V during normal operation. During softstart operation, the transconductance is reduced to 78 A/V and the error amplifier is referenced to the internal soft-start voltage. The frequency compensation components (capacitor, series resistor and capacitor) are connected between the error amplifier output COMP terminal and GND terminal. 7.3.6 Adjusting the Output Voltage The internal voltage reference produces a precise 0.8 V 1% voltage reference over the operating temperature and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor divider from the output node to the FB terminal. It is recommended to use 1% tolerance or better divider resistors. Select the low side resistor RLS for the desired divider current and use Equation 3 to calculate RHS. To improve efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator will be more susceptible to noise and voltage errors from the FB input current may become noticeable. ae Vout - 0.8V o RHS = RLS c / 0.8 V e o (3) 7.3.7 Enable and Adjusting Undervoltage Lockout The TPS54540 is enabled when the VIN terminal voltage rises above 4.3 V and the EN terminal voltage exceeds the enable threshold of 1.2 V. The TPS54540 is disabled when the VIN terminal voltage falls below 4 V or when the EN terminal voltage is below 1.2 V. The EN terminal has an internal pull-up current source, I1, of 1.2 A that enables operation of the TPS54540 when the EN terminal floats. If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 22 to adjust the input voltage UVLO with two external resistors. When the EN terminal voltage exceeds 1.2 V, an additional 3.4 A of hysteresis current, IHYS, is sourced out of the EN terminal. When the EN terminal is pulled below 1.2 V, the 3.4 A Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use Equation 4 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 5 to calculate RUVLO2 for the desired VIN start voltage. In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high input voltages (that is, up to 42 V), the EN terminal may experience a voltage greater than the absolute maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using the EN resistors, the EN terminal is clamped internally with a 5.8 V zener diode that will sink up to 150 A. 14 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 Feature Description (continued) VIN TPS54540 i1 VIN ihys RUVLO1 RUVLO1 EN EN 10 kW Node V EN 5.8 V RUVLO2 RUVLO2 Copyright (c) 2017, Texas Instruments Incorporated Figure 22. Adjustable Undervoltage Lockout (UVLO) Copyright (c) 2016, Texas Instruments Incorporated Figure 23. Internal EN Terminal Clamp - VSTOP V RUVLO1 = START IHYS RUVLO2 = (4) VENA VSTART - VENA + I1 RUVLO1 (5) 7.3.8 Internal Soft-Start The TPS54540 has an internal digital soft-start that ramps the reference voltage from zero volts to its final value in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 6. 1024 tSS (ms) = fSW (kHz) (6) If the EN terminal is pulled below the stop threshold of 1.2 V, switching stops and the internal soft-start resets. The soft-start also resets in thermal shutdown. 7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) Terminal) The switching frequency of the TPS54540 is adjustable over a wide range from 100 kHz to 2500 kHz by placing a resistor between the RT/CLK terminal and GND terminal. The RT/CLK terminal voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 7 or Equation 8 or the curves in Figure 5 and Figure 6. To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum controllable on time is typically 135 ns which limits the maximum operating frequency in applications with high input to output step down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A more detailed discussion of the maximum switching frequency is provided in the next section. 101756 RT (kW) = f sw (kHz)1.008 (7) f sw (kHz) = 92417 RT (kW)0.991 (8) Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 15 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com Feature Description (continued) 7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency The TPS54540 implements peak current mode control in which the COMP terminal voltage controls the peak current of the high side MOSFET. A signal proportional to the high side switch current and the COMP terminal voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch current by driving the COMP terminal high. The error amplifier output is clamped internally at a level which sets the peak switch current limit. The TPS54540 provides an accurate current limit threshold with a typical current limit delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor current. The relationship between the inductor value and the peak inductor current is shown in Figure 24. Inductor Current (A) Peak Inductor Current CLPeak Open Loop Current Limit CLPeak = VIN/L x tCLdelay tCLdelay tON Figure 24. Current Limit Delay To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54540 implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB terminal voltage falls from 0.8 V to 0 V. The TPS54540 uses a digital frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the inductor current can exceed the peak current limit because of the high input voltage and the minimum controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the period of the switching cycle providing more time for the inductor current to ramp down. With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can be controlled by frequency foldback protection. Equation 10 calculates the maximum switching frequency at which the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating frequency should not exceed the calculated value. Equation 9 calculates the maximum switching frequency limitation set by the minimum controllable on time and the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to skip switching pulses to achieve the low duty cycle required at maximum input voltage. fSW (max skip ) = 16 1 tON ae I R + V dc OUT + Vd c O c VIN - IO RDS(on ) + Vd e o / / o Submit Documentation Feedback (9) Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 Feature Description (continued) fSW(shift) = fDIV aec ICL Rdc + VOUT(sc ) + Vd tON c VIN - ICL RDS(on ) + Vd e o / / o IO Output current ICL Current limit Rdc inductor resistance VIN maximum input voltage VOUT output voltage VOUTSC output voltage during short Vd diode voltage drop RDS(on) switch on resistance tON controllable on time DIV frequency divide equals (1, 2, 4, or 8) (10) 7.3.11 Synchronization to RT/CLK Terminal The RT/CLK terminal can receive a frequency synchronization signal from an external system clock. To implement this synchronization feature connect a square wave to the RT/CLK terminal through either circuit network shown in Figure 25. The square wave applied to the RT/CLK terminal must switch lower than 0.5 V and higher than 2 V and have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising edge of the SW will be synchronized to the falling edge of RT/CLK terminal signal. The external synchronization circuit should be designed such that the default frequency set resistor is connected from the RT/CLK terminal to ground when the synchronization signal is off. When using a low impedance signal source, the frequency set resistor is connected in parallel with an ac coupling capacitor to a termination resistor (that is, 50 ) as shown in Figure 25. The two resistors in series provide the default frequency setting resistance when the signal source is turned off. The sum of the resistance should set the switching frequency close to the external CLK frequency. It is recommended to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK terminal. The first time the RT/CLK is pulled above the PLL threshold the TPS54540 switches from the RT resistor freerunning frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and the RT/CLK terminal becomes high impedance as the PLL starts to lock onto the external signal. The switching frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During the transition from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz and then increase or decrease to the resistor programmed frequency when the 0.5 V bias voltage is reapplied to the RT/CLK resistor. The switching frequency is divided by 8, 4, 2, and 1 as the FB terminal voltage ramps from 0 to 0.8 volts. The device implements a digital frequency foldback to enable synchronizing to an external clock during normal startup and fault conditions. Figure 26, Figure 27 and Figure 28 show the device synchronized to an external system clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode). TPS54540 TPS54540 RT /CLK RT /CLK PLL PLL RT Clock Source Hi -Z Clock Source RT Copyright (c) 2017, Texas Instruments Incorporated Figure 25. Synchronizing to a System Clock Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 17 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com Feature Description (continued) SW SW EXT EXT IL IL Figure 26. Plot of Synchronizing in CCM Figure 27. Plot of Synchronizing in DCM SW EXT IL Figure 28. Plot of Synchronizing in Eco-mode 7.3.12 Overvoltage Protection The TPS54540 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients in designs with low output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the FB terminal voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier output transitions to the normal operating level. In some applications, the power supply output voltage can increase faster than the response of the error amplifier output resulting in an output overshoot. 18 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 Feature Description (continued) The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB terminal voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB terminal voltage is greater than the rising OVP threshold, the high side MOSFET is immediately disabled to minimize output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the internal voltage reference, the high side MOSFET resumes normal operation. 7.3.13 Thermal Shutdown The TPS54540 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 176C. The high side MOSFET stops switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature falls below 164C, the device reinitiates the power up sequence controlled by the internal soft-start circuitry. 7.3.14 Small Signal Model for Loop Response Figure 29 shows an equivalent model for the TPS54540 control loop which can be simulated to check the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA of 350 A/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor RO and capacitor CO model the open loop gain and frequency response of the amplifier. The 1mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is only valid for continuous conduction mode (CCM) operation. SW VO Power Stage gmps 17 A/V a b RESR R1 RL COMP c 0.8 V R3 CO C2 RO FB COUT gmea R2 350 mA/V C1 Copyright (c) 2016, Texas Instruments Incorporated Figure 29. Small Signal Model for Loop Response 7.3.15 Simple Small Signal Model for Peak Current Mode Control Figure 30 describes a simple small signal model that can be used to design the frequency compensation. The TPS54540 power stage can be approximated by a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 11 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP terminal voltage (node c in Figure 29) is the power stage transconductance, gmPS. The gmPS for the TPS54540 is 17 A/V. The low-frequency gain of the power stage is the product of the transconductance and the load resistance as shown in Equation 12. Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 19 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com Feature Description (continued) As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 13). The combined effect is highlighted by the dashed line in the right half of Figure 30. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same with varying load conditions. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 14). VO Adc VC RESR fp RL gmps COUT fz Copyright (c) 2017, Texas Instruments Incorporated Figure 30. Simple Small Signal Model and Frequency Response for Peak Current Mode Control 20 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 Feature Description (continued) ae s c1 + 2p fZ VOUT = Adc e VC ae s c1 + 2p fP e Adc = gmps RL fP = o / o o / o (11) (12) 1 COUT RL 2p (13) 1 fZ = COUT RESR 2p (14) 7.3.16 Small Signal Model for Frequency Compensation The TPS54540 uses a transconductance amplifier for the error amplifier and supports three of the commonlyused frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 31. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors. Equation 15 and Equation 16 relate the frequency response of the amplifier to the small signal model in Figure 31. The open-loop gain and bandwidth are modeled using the RO and CO shown in Figure 31. See the application section for a design example using a Type 2A network with a low ESR output capacitor. Equation 15 through Equation 24 are provided as a reference. An alternative is to use WEBENCH software tools to create a design based on the power supply requirements. VO R1 FB gmea COMP Type 2A Type 2B Type 1 Vref R2 RO CO R3 C2 R3 C2 C1 C1 Copyright (c) 2016, Texas Instruments Incorporated Figure 31. Types of Frequency Compensation Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 21 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com Feature Description (continued) Aol A0 P1 Z1 P2 A1 BW Figure 32. Frequency Response of the Type 2A and Type 2B Frequency Compensation Aol(V/V) gmea gmea = 2p BW (Hz) Ro = CO (15) (16) ae o s c1 + / 2p fZ1 o e EA = A0 ae o ae o s s c1 + / c1 + / 2p fP1 o e 2p fP2 o e A0 = gmea A1 = gmea P1 = Z1 = P2 = R2 Ro R1 + R2 R2 Ro| | R3 R1 + R2 (18) (19) 1 2p Ro C1 (20) 1 2p R3 C1 (21) 1 2p R3 | | RO (C2 + CO ) type 2a (22) 1 P2 = type 2b 2p R3 | | RO CO P2 = 22 2p R O (17) (23) 1 type 1 (C2 + C O ) (24) Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 7.4 Device Functional Modes 7.4.1 Operation with VIN = < 4.5 V (Minimum VIN) The device is recommended to operate with input voltages above 4.5 V. The typical VIN UVLO threshold is 4.3 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device will not switch. If EN is externally pulled up to VIN or left floating, when VIN passes the UVLO threshold the device will become active. Switching is enabled, and the soft start sequence is initiated. The TPS54540 will start at the soft start time determined by the internal soft start time. 7.4.2 Operation with EN Control The enable threshold voltage is 1.2 V typical. With EN held below that voltage the device is disabled and switching is inhibited even if VIN is above its UVLO threshold. The IC quiescent current is reduced in this state. If the EN voltage is increased above the threshold while VIN is above its UVLO threshold, the device becomes active. Switching is enabled, and the soft start sequence is initiated. The TPS54540 will start at the soft start time determined by the internal soft start time. 7.4.3 Alternate Power Supply Topologies 7.4.3.1 Inverting Power The TPS54540 can be used to convert a positive input voltage to a negative output voltage. Idea applications are amplifiers requiring a negative power supply. For a more detailed example see SLVA317. VIN + Cin Cboot Lo VIN BOOT SW GND Cd R1 + GND TPS54540 R2 Co FB VOUT EN COMP Rcomp RT /CLK Czero Cpole RT Copyright (c) 2017, Texas Instruments Incorporated Figure 33. TPS54540 Inverting Power Supply Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 23 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com Device Functional Modes (continued) 7.4.3.2 Split Rail Power Supply The TPS54540 can be used to convert a positive input voltage to a split rail positive and negative output voltage by using a coupled inductor. Idea applications are amplifiers requiring a split rail positive and negative voltage power supply. For a more detailed example see SLVA369. VOPOS + VIN Copos + Cin VIN Cboot BOOT GND SW Lo Cd R1 GND + Coneg R2 TPS54540 VONEG FB EN COMP Rcomp RT /CLK RT Czero Cpole Copyright (c) 2017, Texas Instruments Incorporated Figure 34. TPS54540 Split Rail Power Supply 24 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS54540 is a 42 V, 5 A, step down regulator with an integrated high side MOSFET. Idea applications are: 12 V and 24 V Industrial, Automotive and Communications Power Systems. 8.2 Typical Application L1 5.5uH 0.1uF C4 3.3V, 5A U1 TPS54540DDA 6 V to 42 V 2 3 C10 C3 C1 4.7uF 4.7uF 4.7uF C2 4.7uF R1 365k 4 SW BOOT VIN GND EN COMP RT/CLK PWRPD 1 VIN FB 8 C7 100uF PDS760 R5 31.6k 7 6 5 FB FB R4 16 .9k 9 R2 88.7k C6 100uF D1 VOUT R3 243 k C8 R6 10 .2k 47 pF C5 4700 pF Copyright (c) 2017, Texas Instruments Incorporated Figure 35. 3.3 V Output TPS54540 Design Example 8.2.1 Design Requirements This guide illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few parameters must be known in order to start the design process. These requirements are typically determined at the system level. Calculations can be done with the aid of WEBENCH or the excel spreadsheet (SLVC452) located on the product page. For this example, start with the following known parameters: Table 1. Design Parameters PARAMETER VALUE Output Voltage 3.3 V Transient Response 1.25 A to 3.75 A load step VOUT = 4 % Maximum Output Current 5A Input Voltage 12 V nom. 6 V to 42 V Output Voltage Ripple 0.5% of VOUT Start Input Voltage (rising VIN) 5.75 V Stop Input Voltage (falling VIN) 4.5 V Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 25 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com 8.2.2 Detailed Design Procedure 8.2.2.1 Custom Design with WEBENCH(R) Tools Click here to create a custom design using the TPS54540 device with the WEBENCH(R) Power Designer. 1. Start by entering your VIN, VOUT, and IOUT requirements. 2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments. 3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability. 4. In most cases, you will also be able to: - Run electrical simulations to see important waveforms and circuit performance - Run thermal simulations to understand the thermal performance of your board - Export your customized schematic and layout into popular CAD formats - Print PDF reports for the design, and share your design with colleagues 5. Get more information about WEBENCH tools at www.ti.com/WEBENCH. 8.2.2.2 Selecting the Switching Frequency The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest switching frequency possible since this produces the smallest solution size. High switching frequency allows for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage and the frequency foldback protection. Equation 9 and Equation 10 should be used to calculate the upper limit of the switching frequency for the regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values results in pulse skipping or the lack of overcurrent protection during a short circuit. The typical minimum on time, tonmin, is 135 ns for the TPS54540. For this example, the output voltage is 3.3 V and the maximum input voltage is 42 V. Assuming a diode voltage of 0.52 V, inductor DC resistance of 10.3 m, typical switch resistance of 92 m and 5 A load, from Equation 25 the maximum switch frequency to avoid pulse skipping is 680 kHz. To ensure overcurrent runaway is not a concern during short circuits use Equation 26 to determine the maximum switching frequency for frequency foldback protection. With a current limit value of 6.3 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 960 kHz. For this design, a lower switching frequency of 400 kHz is chosen to operate comfortably below the calculated maximums. To determine the timing resistance for a given switching frequency, use Equation 27 or the curve in Figure 6. The switching frequency is set by resistor R3 shown in Figure 35. For 400 kHz operation, the closest standard value resistor is 243 k. 1 ae 5 A x 10.3 mW + 3.3 V + 0.52 V o fSW(max skip) = c / = 680 kHz 135ns e 42 V - 5 A x 92 mW + 0.52 V o (25) 8 ae 6.3 A x 10.3 mW + 0.1 V + 0.52 V o c / = 960 kHz 135 ns e 42 V - 6.3 A x 92 mW + 0.52 V o 101756 RT (kW) = = 242 kW 400 (kHz)1.008 fSW(shift) = 26 Submit Documentation Feedback (26) (27) Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 8.2.2.3 Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer, however, the following guidelines may be used. For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable. When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple current. This provides sufficienct ripple current with the input voltage at the minimum. For this design example, KIND = 0.3 and the inductor value is calculated to be 5.1 H. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation 30 and Equation 31. For this design, the RMS inductor current is 5 A and the peak inductor current is 5.79 A. The chosen inductor is a WE 744325550, which has a saturation current rating of 12 A and an RMS current rating of 10 A. This also has a typical inductance of 5.5 H at no load and 4.8 H at 5 A load. Lastly it has a DCR of 10.3 m. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative design approach is to choose an inductor with a saturation current rating equal to or greater than the switch current limit of the TPS54540 which is nominally 7.5 A. VIN(max ) - VOUT VOUT 42 V - 3.3 V 3.3 V = = 5.1 mH LO(min ) = IOUT KIND VIN(max ) fSW 5 A x 0.3 42 V 400 kHz (28) spacer IRIPPLE = VOUT (VIN(max ) - VOUT ) VIN(max ) LO fSW = 3.3 V x (42 V - 3.3 V) = 1.58 A 42 V x 4.8 mH x 400 kHz (29) spacer IL(rms ) = (IOUT ) 2 ( ae 1 c VOUT VIN(max ) - VOUT + 12 cc VIN(max ) LO fSW e )/o 2 / = / o 2 (5 A ) 2 ae 3.3 V (42 V - 3.3 V ) o 1 + c / =5A c / 12 e 42 V 4.8 mH 400 kHz o (30) spacer IL(peak ) = IOUT + IRIPPLE 1.58 A = 5A + = 5.79 A 2 2 (31) 8.2.2.4 Output Capacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the most stringent of these three criteria. Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 27 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the increased load current until the regulator responds to the load step. A regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range. Equation 32 shows the minimum output capacitance necessary, where IOUT is the change in output current, sw is the regulators switching frequency and VOUT is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75 A. Therefore, IOUT is 3.75 A - 1.25 A = 2.5 A and VOUT = 0.04 x 3.3 V = 0.13 V. Using these numbers gives a minimum capacitance of 95 F. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is shown in Figure 36. The excess energy absorbed in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the peak output voltage, and Vi is the initial voltage. For this example, the worst case load step will be from 3.75 A to 1.25 A. The output voltage increases during this load transition and the stated maximum in our specification is 4 % of the output voltage. This makes Vf = 1.04 x 3.3 V = 3.43 V. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum capacitance of 68 F. Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where sw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the inductor ripple current. Equation 34 yields 30 F. Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 35 indicates the equivalent ESR should be less than 10 m. The most stringent criteria for the output capacitor is 95 F required to maintain the output voltage within regulation tolerance during a load transient. Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 2 x 100 F, 6.3 V type X5R ceramic capacitors with 2 m of ESR will be used. The derated capacitance is 130 F, well above the minimum required capacitance of 95 F. Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor reliability, especially non ceramic capacitors. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current that the output capacitor must support. For this example, Equation 36 yields 460 mA. 2 DIOUT 2 2.5 A COUT > = = 95 mF fSW DVOUT 400 kHz x 0.13 V (32) ((I ) - (I ) ) = 4.8 mH x (3.75 A - 1.25 A ) = 68 mF x (3.43 V - 3.3 V ) ((V ) - (V ) ) 2 OH COUT > LO 2 2 f 2 2 2 2 OL 2 I 1 1 1 1 COUT > x = = 30 mF 8 fSW ae VORIPPLE o 8 x 400 kHz ae 16 mV o c 1.58 A / c / e o e IRIPPLE o V 16 mV RESR < ORIPPLE = = 10 mW IRIPPLE 1.58 A 28 Submit Documentation Feedback (33) (34) (35) Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 ICOUT(rms) = ( VOUT VIN(max ) - VOUT )= 12 VIN(max ) LO fSW 3.3 V (42 V - 3.3 V ) 12 42 V 4.8 mH 400 kHz = 460 mA (36) 8.2.2.5 Catch Diode The TPS54540 requires an external catch diode between the SW terminal and GND. The selected diode must have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator. Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of 42 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54540. For the example design, the PDS760-13 Schottky diode is selected for its lower forward voltage and good thermal characteristics compared to smaller devices. The typical forward voltage of the PDS760-13 is 0.52 volts at 5 A and 25C. The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 37 is used to calculate the total power dissipation, including conduction losses and ac losses of the diode. The PDS760-13 diode has a junction capacitance of 300 pF. Using Equation 37, the total loss in the diode at the nominal input voltage is 1.9 W. If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode which has a low leakage current and slightly higher forward voltage drop. PD (V = IN(max ) - VOUT (12 V ) I OUT 2 Vf d VIN - 3.3 V ) 5 A x 0.52 V 12 V + C j fSW (VIN + Vf d) + 2 = 300 pF x 400 kHz x (12 V + 0.52 V)2 = 1.9 W 2 (37) 8.2.2.6 Input Capacitor The TPS54540 requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 F of effective capacitance. Some applications will benefit from additional bulk capacitance. The effective capacitance includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54540. The input ripple current can be calculated using Equation 38. The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 42 V voltage rating is required to support transients up to the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or 100 V. For this example, four 4.7 F, 50 V capacitors in parallel are used. Table 2 shows several choices of high voltage capacitors. The input capacitance value determines the input ripple voltage of the regulator. The maximum input voltage ripple occurs at 50% duty cycle and can be calculated using Equation 39. Using the design example values, IOUT = 5 A, CIN = 18.8 F, sw = 400 kHz, yields an input voltage ripple of 170 mV and a rms input ripple current of 2.5 A. Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 29 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 ICI(rms ) = IOUT x VOUT x VIN(min ) www.ti.com (V IN(min ) - VOUT VIN(min ) ) = 5A 3.3 V 6V (6 V - 3.3 V ) 6V = 2.5 A (38) I 0.25 5 A 0.25 DVIN = OUT = = 170 mV CIN fSW 18.8 mF 400 kHz (39) Table 2. Capacitor Types VALUE (F) 1 to 2.2 1 to 4.7 1 1 to 2.2 1 to 1.8 1 to 1.2 1 to 3.9 1 to 1.8 1 to 2.2 1.5 to 6.8 1 to 2.2 1 to 3.3 1 to 4.7 1 1 to 4.7 1 to 2.2 EIA Size 1210 1206 2220 2225 1812 1210 1210 1812 VOLTAGE DIALECTRIC 100 V COMMENTS GRM32 series 50 V 100 V GRM31 series 50 V 50 V 100 V VJ X7R series 50 V 100 V 100 V X7R C series C4532 50 V 100 V C series C3225 50 V 50 V 100 V X7R dielectric series 50 V 100 V 8.2.2.7 Bootstrap Capacitor Selection A 0.1-F ceramic capacitor must be connected between the BOOT and SW terminals for proper operation. A ceramic capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10 V or higher voltage rating. 8.2.2.8 Undervoltage Lockout Set Point The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN terminal of the TPS54540. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it should continue to do so until the input voltage falls below 4.5 V (UVLO stop). Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between Vin and ground connected to the EN terminal. Equation 4 and Equation 5 calculate the resistance values necessary. For the example application, a 365 k between VIN and EN (RUVLO1) and a 88.7 k between EN and ground (RUVLO2) are required to produce the 5.75 V and 4.5 V start and stop voltages. V - VSTOP 5.75 V - 4.5 V RUVLO1 = START = = 368 kW IHYS 3.4 mA (40) RUVLO2 = 30 VENA 1.2 V = = 88.7 kW VSTART - VENA 5.75 V - 1.2 V + 1.2 mA + I1 365 kW RUVLO1 Submit Documentation Feedback (41) Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 8.2.2.9 Output Voltage and Feedback Resistors Selection The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 k was selected for R6. Using Equation 3, R5 is calculated as 31.9 k. The nearest standard 1% resistor is 31.6 k. Due to the input current of the FB terminal, the current flowing through the feedback network should be greater than 1 A to maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 k. Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but may also introduce noise immunity problems. V - 0.8 V ae 3.3 V - 0.8 V o RHS = RLS x OUT = 10.2 kW x c / = 31.9 kW 0.8 V 0.8 V e o (42) 8.2.2.10 Minimum VIN To ensure proper operation of the device and to keep the output voltage in regulation, the input voltage at the device must be above the value calculated with Equation 43. Using the typical values for the RHS, RDC and VF in this application example, the minimum input voltage is 5.56 V. The BOOT-SW = 3 V curve in Figure 1 was used for RDS(on) = 0.12 because the device operates with low drop out. When operating with low dropout, the BOOTSW voltage is regulated at a lower voltage because the BOOT-SW capacitor is not refreshed every switching cycle. In the final application, the values of RDS(on), Rdc and VF used in this equation must include tolerance of the component specifications and the variation of these specifications at their maximum operating temperature in the application. In this application example, the calculated minimum input voltage is near the input voltage UVLO for the TPS54540 so the device may turn off before going into drop out. VOUT VIN min VF Rdc u IOUT RDS on u I OUT VF 0.99 3.3 V 0.5 V 0.0103 : u 5 A 0.12 : u 5 A 0.5 V 0.99 VIN min 3.99 V (43) 8.2.2.11 Compensation There are several methods to design compensation for DC-DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. To get started, the modulator pole, p(mod), and the ESR zero, z1 must be calculated using Equation 44 and Equation 45. For COUT, use a derated value of 130 F. Use equations Equation 46 and Equation 47 to estimate a starting point for the crossover frequency, co. For the example design, p(mod) is 1850 Hz and z(mod) is 610 kHz. Equation 45 is the geometric mean of the modulator pole and the ESR zero and Equation 47 is the mean of modulator pole and half of the switching frequency. Equation 46 yields 34 kHz and Equation 47 gives 19 kHz. Use the geometric mean value of Equation 46 and Equation 47 for an initial crossover frequency. For this example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved transient response. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. IOUT(max ) 5A fP(mod) = = = 1850 Hz 2 p VOUT COUT 2 p 3.3 V 130 mF (44) f Z(mod) = 1 2 p RESR COUT fco1 = fp(mod) x f z(mod) = fco2 = fp(mod) x fSW 2 = = 1 = 610 kHz 2 p 1 mW 130 mF 1850 Hz x 610 kHz = 34 kHz 400 kHz 2 = 19 kHz 1850 Hz x (45) (46) (47) Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 31 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com To determine the compensation resistor, R4, use Equation 48. The typical power stage transconductance, gmps, is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 350 A/V, respectively. R4 is calculated to be 17 k and a standard value of 16.9 k is selected. Use Equation 49 to set the compensation zero to the modulator pole frequency. Equation 49 yields 5100 pF for compensating capacitor C5. 4700 pF is used for this design. o VOUT ae 2 p fco COUT o ae o 3.3V ae 2 p 30 kHz 130 mF o ae R4 = c xc / = c / x c / = 17 kW / gmps 17 A / V e o e 0.8 V x 350 mA / V o e o e VREF x gmea o (48) 1 1 C5 = = = 5100 pF 2 p R4 x fp(mod) 2 p 16.9 kW x 1850 Hz (49) A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value calculated from Equation 50 and Equation 51 for C8 to set the compensation pole. The selected value of C8 is 47 pF for this design example. C x RESR 130 mF x 1 mW = = 15 pF C8 = OUT R4 16.9 kW (50) 1 1 C8 = = = 47 pF R4 x f sw x p 16.9 kW x 400 kHz x p (51) 8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current is less than 560 mA. The power supply enters Eco-mode when the output current is lower than 18 mA. The input current draw is 241 A with no load. 8.2.2.13 Power Dissipation Estimate The following formulas show how to estimate the TPS54540 power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is operating in discontinuous conduction mode (DCM). The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and supply current (PQ). Example calculations are shown with the 12 V typical input voltage of the design example. aeV o 3.3 V 2 PCOND = (IOUT ) RDS(on ) c OUT / = 5 A 2 92 mW = 0.633 W 12 V e VIN o (52) spacer PSW = VIN fSW IOUT trise = 12 V 400 kHz 5 A 4.9 ns = 0.118 W (53) spacer PGD = VIN QG fSW = 12 V 3nC 400 kHz = 0.014 W (54) spacer PQ = VIN IQ = 12 V 146 mA = 0.0018 W (55) Where: IOUT is the output current (A). RDS(on) is the on-resistance of the high-side MOSFET (). VOUT is the output voltage (V). VIN is the input voltage (V). fsw is the switching frequency (Hz). trise is the SW terminal voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns QG is the total gate charge of the internal MOSFET 32 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com IQ SLVSBX7B - MAY 2013 - REVISED MARCH 2017 is the operating nonswitching supply current Therefore, PTOT = PCOND + PSW + PGD + PQ = 0.633 W + 0.118 W + 0.014 W + 0.0018 W = 0.77 W (56) For given TA, TJ = TA + RTH PTOT (57) For given TJMAX = 150C TA (max ) = TJ(max ) - RTH PTOT (58) Where: Ptot is the total device power dissipation (W). TA is the ambient temperature (C). TJ is the junction temperature (C). RTH is the thermal resistance of the package (C/W) TJMAX is maximum junction temperature (C). TAMAX is maximum ambient temperature (C). There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and PCB trace resistance impacting the overall efficiency of the regulator. 8.2.3 Application Curves 10 V/div 1 A/div Measurements are taken with standard EVM using a 12 V input, 3.3 V output, and 5 A load unless otherwise noted. IOUT VIN 100 mV/div 10 mV/div VOUT 3.3V offset VOUT 3.3V offset Time = 4 ms/div Time = 100 Ps/div Figure 37. Line Transient (8 V to 40 V) Figure 36. Load Transient Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 33 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com 5 V/div VIN VOUT 2 V/div EN EN 2 V/div 2 V/div 2 V/div 5 V/div VIN VOUT Time = 2 ms/div Time = 20 ms/div Figure 39. Start-up With EN Figure 38. Start-up With VIN 10 V/div SW 500 mA/div IL 10 mV/div IL 10 mV/div 1 A/div 10 V/div SW VOUT AC Coupled VOUT AC Coupled IOUT = 100 mA Time = 4 Ps/div Time = 4 Ps/div Figure 41. Output Ripple DCM Figure 40. Output Ripple CCM 10 V/div 1 A/div 10 V/div IL IL 200 mV/div 10 mV/div 200 mA/div SW SW VOUT AC Coupled No Load VIN AC Coupled Time = 1 ms/div Time = 4 Ps/div Figure 42. Output Ripple PSM 34 Figure 43. Input Ripple CCM Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 10 V/div 2 V/div SW SW VIN AC Coupled IOUT = 100 mA IL VOUT = 5 V 20 mV/div 10 mV/div 200 mA/div 500 mA/div IL No Load EN Floating VIN = 5.5 V Time = 4 Ps/div Time = 40 Ps/div Figure 44. Input Ripple DCM Figure 45. Low Dropout Operation 100 100 90 95 80 70 Efficiency (%) Efficiency (%) 90 85 80 75 VOUT = 5 V, fsw = 400 kHz 70 65 60 0 0.5 1 1.5 Series4 VIN = 7 V 12V VIN = 12 V VIN = 24 V 24V VIN = 36 V 36V 2 2.5 3 3.5 4 4.5 IO - Output Current (A) 60 50 30 V VIN=12V IN = 12 V 20 VIN=24V V IN = 24 V 10 0 0.001 5 VIN=24V V IN = 36 V VOUT = 5 V, fsw = 400 kHz 0.01 0.1 1 IO - Output Current (A) C024 C024 Figure 47. Light Load Efficiency Figure 46. Efficiency vs Load Current 100 100 95 90 80 90 70 Efficiency (%) Efficiency (%) VIN=6V V IN = 7 V 40 85 80 75 65 VOUT = 3.3 V, fsw = 400 kHz 60 0 0.5 1 1.5 2 2.5 3 3.5 4 Load Current (A) 4.5 50 40 30 VIN V IN ==66VV V VIN 12VV IN ==12 V VIN 24VV IN ==24 V VIN 36VV IN ==36 70 60 VIN V IN ==66VV V VIN 12VV IN ==12 V VIN 24VV IN ==24 V VIN 36VV IN ==36 20 10 5 0 0.001 C050 Figure 48. Efficiency vs Load Current VOUT = 3.3 V, fsw = 400 kHz 0.01 0.1 Load Current (A) Figure 49. Light Load Efficiency Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 1 C051 35 TPS54540 www.ti.com 100 95 85 Gain (dB) Efficiency (%) 90 80 75 V 18in IN = 18 V 60 180 50 150 40 120 30 90 20 60 10 30 0 0 10 30 20 60 30 70 Series1 V IN = 24 V 65 VOUT = 12 V, fsw = 800 kHz 0 0.5 1 1.5 2 2.5 50 Series3 V IN = 36 V 3 3.5 4 4.5 IO - Output Current (A) 90 40 VIN = 12 V, VOUT = 3.3 V, IOUT = 5 A 100 1k 150 10k 100k 1M Frequency (Hz) C024 C053 Figure 51. Overall Loop Frequency Response 0.5 0.20 0.4 0.15 Output Voltage Normalized (%) Output Voltage Normalized (%) 120 Phase 180 10 5 Figure 50. Efficiency vs Output Current 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 Gain 60 60 Phase () SLVSBX7B - MAY 2013 - REVISED MARCH 2017 VIN = 12 V, VOUT = 3.3 V, fsw = 400 kHz -0.4 VIN = 12 V, IOUT = 5 A, fsw = 400 kHz 0.10 0.05 0.00 0.05 0.10 0.15 0.20 0 0.5 1 1.5 2 2.5 3 3.5 4 Output Current (A) 4.5 5 0 C054 Figure 52. Regulation vs Load Current 5 10 15 20 25 30 35 40 Input Voltage (V) 45 C055 Figure 53. Regulation vs Input Voltage 9 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 4.5 V and42 V. This input supply should be well regulated. If the input supply is located more than a few inches from the TPS54540 converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 F is a typical choice. 36 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 10 Layout 10.1 Safe Operating Area 90 90 80 80 70 70 60 60 TA (C) TA (C) The safe operating area (SOA) of the device is shown in Figure 54, through Figure 57 for 3.3 V, 5 V and 12 V outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at which the internal and external components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a double-sided PCB with 2 oz. copper, similar to the EVM. Careful attention must be paid to the other components chosen for the design, especially the catch diode. In most of these test conditions, the thermal performance is limited by the catch diode. When operating at high duty cycles or at higher switching frequency the TPS54540's thermal performance can become the limiting factor. 50 50 6V 40 8V 40 12 V 24 V 30 36 V 20 0.0 0.5 1.0 12 V 24 V 30 36 V 20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 IOUT (Amps) 5.0 0.0 0.5 1.0 90 80 80 70 70 60 TA (C) TA (C) 2.5 3.0 3.5 4.0 4.5 5.0 C057 Figure 55. 5V Outputs 90 fsw = 800 kHz 18 V 40 2.0 IOUT (Amps) Figure 54. 3.3V Outputs 50 1.5 C056 60 50 400 LFM 40 200 LFM 30 100 LFM 24 V 30 36 V Nat Conv 20 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 IOUT (Amps) 4.0 4.5 5.0 0.0 C058 Figure 56. 12V Outputs 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 IOUT (Amps) 5.0 C048 Figure 57. Air Flow Conditions VIN = 36 V, VO = 12 V Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 37 TPS54540 SLVSBX7B - MAY 2013 - REVISED MARCH 2017 www.ti.com 10.2 Layout Guidelines Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. * * * * * * * * * * To reduce parasitic effects, the VIN terminal should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN terminal, and the anode of the catch diode. The GND terminal should be tied directly to the power pad under the IC and the PowerPADTM. The power pad should be connected to internal PCB ground planes using multiple vias directly under the IC. The SW terminal should be routed to the cathode of the catch diode and to the output inductor. Since the SW connection is the switching node, the catch diode and output inductor should be located close to the SW terminals, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK terminal is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline. 10.3 Layout Example Vout Output Capacitor Topside Ground Area Input Bypass Capacitor Vin UVLO Adjust Resistors Output Inductor Route Boot Capacitor Trace on another layer to provide wide path for topside ground BOOT Catch Diode SW VIN GND EN COMP RT/CLK FB Frequency Set Resistor Compensation Network Resistor Divider Thermal VIA Signal VIA Figure 58. PCB Layout Example 10.3.1 Estimated Circuit Area Boxing in the components in the design of Figure 35 the estimated printed circuit board area is 1.025 in2 (661 mm2). This area does not include test points or connectors. 38 Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 TPS54540 www.ti.com SLVSBX7B - MAY 2013 - REVISED MARCH 2017 11 Device and Documentation Support 11.1 Custom Design with WEBENCH(R) Tools Click here to create a custom design using the TPS54540 device with the WEBENCH(R) Power Designer. 1. Start by entering your VIN, VOUT, and IOUT requirements. 2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments. 3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability. 4. In most cases, you will also be able to: - Run electrical simulations to see important waveforms and circuit performance - Run thermal simulations to understand the thermal performance of your board - Export your customized schematic and layout into popular CAD formats - Print PDF reports for the design, and share your design with colleagues 5. Get more information about WEBENCH tools at www.ti.com/WEBENCH. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks Eco-mode, PowerPAD, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2013-2017, Texas Instruments Incorporated Product Folder Links: TPS54540 39 PACKAGE OPTION ADDENDUM www.ti.com 20-Jun-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS54540DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54540 TPS54540DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54540 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 20-Jun-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS54540 : * Automotive: TPS54540-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54540DDAR Package Package Pins Type Drawing SO Power PAD DDA 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.8 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54540DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0 Pack Materials-Page 2 GENERIC PACKAGE VIEW DDA 8 PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE Images above are just a representation of the package family, actual package may vary. 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