SLOS157B − JUNE1996 − REVISED APRIL 2005
3−1
WWW.TI.COM
DOutput Swing Includes Both Supply Rails
DLow Noise . . . 19 nV/√Hz Typ at f = 1 kHz
DLow Input Bias Current ...1 pA Typ
DFully Specified for Single-Supply 3-V and
5-V Operation
DVery Low Power ...110 µA Typ
DCommon-Mode Input Voltage Range
Includes Negative Rail
DWide Supply Voltage Range
2.7 V to 10 V
DMacromodel Included
description
The TLV2221 is a single low-voltage operational amplifier available in the SOT-23 package. It offers a
compromise between the ac performance and output drive of the TLV2231 and the micropower TLV2211.
It consumes only 150 µA (max) of supply current and is ideal for battery-powered applications. The device
exhibits rail-to-rail output performance for increased dynamic range in single- or split-supply applications. The
TLV2221 is fully characterized at 3 V and 5 V and is optimized for low-voltage applications.
The TLV2221, exhibiting high input impedance and low noise, is excellent for small-signal conditioning for
high-impedance sources, such as piezoelectric transducers. Because of the micropower dissipation levels
combined with 3-V operation, these devices work well in hand-held monitoring and remote-sensing
applications. In addition, the rail-to-rail output feature with single or split supplies makes this family a great
choice when interfacing with analog-to-digital converters (ADCs).
With a total area of 5.6mm2, the S OT-23 package only requires one third the board space of the standard 8-pin
SOIC package. This ultra-small package allows designers to place single amplifiers very close to the signal
source, minimizing noise pick-up from long PCB traces. TI has also taken special care to provide a pinout that
is optimized for board layout (see Figure 1). Both inputs are separated by GND to prevent coupling or leakage
paths. The OUT and IN− terminals are on the same end of the board to provide negative feedback. Finally, gain
setting resistors and decoupling capacitor are easily placed around the package.
VIVDD+
OUTIN−
VDD/GND
IN+ C
RI
RF
GND
V+
VO
1
2
3
4
5
Figure 1. Typical Surface Mount Layout for a Fixed-Gain Noninverting Amplifier
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DBV PACKAGE
(TOP VIEW)
5
43
1
2
IN−
VDD−/GND
IN+ VDD+
OUT
!"#$! % &""$ % ! '&()$! $*
"!&$% !!"# $! %'$!% '" $+ $"#% ! ,% %$"&#$%
%$" -""$.* "!&$! '"!%%/ !% !$ %%"). )&
$%$/ ! )) '"#$"%*
Copyright 1997 −2005, Texas Instruments Incorporated
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
SLOS157B − JUNE1996 − REVISED APRIL 2005
3−2 WWW.TI.COM
AVAILABLE OPTIONS
TA
VIOmax AT 25°C
PACKAGED DEVICES
SYMBOL
CHIP
FORM‡
T
A
V
IO
max AT 25
°
C
SOT-23 (DBV)†
SYMBOL
FORM
‡
(Y)
0°C to 70°C3 mV TLV2221CDBV VADC
TLV2221Y
−40°C to 85°C3 mV TLV2221IDBV VADI
TLV2221Y
†The DBV package available in tape and reel only.
‡Chip forms are tested at TA = 25°C only.
TLV2221Y chip information
This chip, when properly assembled, displays characteristics similar to the TLV2221C. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 10 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (2) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
+
−OUT
IN+
IN−
VDD+
(5)
(1)
(3) (4)
(2)
VDD−/GND
40
(3)
(2)
(1) (5)
(4)
32
0
0000
SLOS157B − JUNE 1997 − REVISED APRIL 2005
0
WWW.TI.COM
•6−3
equivalent schematic
Q3 Q6 Q9 Q12 Q14 Q16
Q2 Q5 Q7 Q8 Q10 Q11
D1
Q17Q15Q13
Q4Q1
R5
C1
VDD+
IN+
IN−
R3
R7
R1
R2
OUT
VDD−/GND
COMPONENT COUNT†
Transistors
Diodes
Resistors
Capacitors
23
5
11
2
†Includes both amplifiers and all
ESD, bias, and trim circuitry
R6
C2
R4
SLOS157B − JUNE 1996 − REVISED APRIL 2005
4WWW.TI.COM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input, see Note 1) −0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (each input) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current into VDD+ ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of VDD− ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current (at or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV2221C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV2221I −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DBV package 260°C. . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to VDD −.
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below VDD− − 0.3 V.
3. The output can be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA
≤
25
°
C
DERATING FACTOR
TA = 70
°
C
TA = 85
°
C
PACKAGE
TA ≤ 25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70 C
POWER RATING
TA = 85 C
POWER RATING
DBV 150 mW 1.2 mW/°C96 mW 78 mW
recommended operating conditions
TLV2221C TLV2221I
UNIT
MIN MAX MIN MAX
UNIT
Supply voltage, VDD 2.7 10 2.7 10 V
Input voltage range, VIVDD− VDD+ −1.3 VDD− VDD+ −1.3 V
Common-mode input voltage, VIC VDD− VDD+ −1.3 VDD− VDD+ −1.3 V
Operating free-air temperature, TA0 70 −40 85 °C
NOTE 1: All voltage values, except differential voltages, are with respect to VDD −.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLV2221C TLV2221I
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO Input offset voltage 0.62 3 0.62 3 mV
VIO
Temperature
coefficient of input
Full range
1
1
V/°C
αVIO
coefficient of input
offset voltage
Full range
1 1 µV/°C
Input offset voltage
long-term drift
(see Note 4) VDD± = ±1.5 V
,
VO = 0, VIC = 0,
RS = 50 Ω25°C0.003 0.003 µV/mo
IIO
Input offset current
O
S
25°C 0.5 0.5
pA
IIO Input offset current Full range 150 150 pA
IIB
Input bias current
25°C 1 1
pA
IIB Input bias current Full range 150 150 pA
0
−0.3
0
−0.3
25
°
C
0
to
−0.3
to
0
to
−0.3
to
VICR
Common-mode input
RS = 50 Ω
|VIO|≤5 mV
25 C
to
2
to
2.2
to
2
to
2.2
V
VICR
Common-mode input
voltage range RS = 50 Ω, |VIO| ≤5 mV
0
0
V
voltage range
Full range
0
to
0
to
Full range
to
1.7
to
1.7
High-level output
IOH = −100 µA 25°C 2.97 2.97
V
OH
High-level output
voltage
IOH = −400 A
25°C 2.88 2.88 V
VOH
voltage
IOH = −400 µAFull range 2.5 2.5
V
Low-level output
VIC = 1.5 V, IOL = 50 µA 25°C 15 15
V
OL
Low-level output
voltage
VIC = 1.5 V,
IOL = 500 A
25°C 150 150 mV
VOL
voltage
VIC = 1.5 V, IOL = 500 µAFull range 500 500
mV
Large-signal
V = 1.5 V,
RL = 2 kه
25°C 2 3 2 3
A
VD
Large-signal
differential voltage VIC = 1.5 V,
VO = 1 V to 2 V
RL = 2 kΩ
‡
Full range 1 1 V/mV
AVD
differential voltage
amplification
V
O
= 1 V to 2 V
RL = 1 MΩ‡25°C 250 250
V/mV
rid Differential input
resistance 25°C 1012 1012 Ω
ric Common-mode input
resistance 25°C 1012 1012 Ω
cic Common-mode input
capacitance f = 10 kHz 25°C 6 6 pF
zoClosed-loop output
impedance f = 10 kHz, AV = 10 25°C 90 90 Ω
CMRR
Common-mode
VIC = 0 to 1.7 V,
25°C 70 82 70 82
dB
CMRR
Common-mode
rejection ratio
VIC = 0 to 1.7 V,
VO = 1.5 V, RS = 50 ΩFull range 65 65 dB
kSVR
Supply voltage
rejection ratio
VDD = 2.7 V to 8 V,
25°C 80 95 80 95
dB
kSVR
rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 8 V,
VIC = VDD/2, No load Full range 80 80 dB
IDD
Supply current
VO = 1.5 V,
No load
25°C 100 150 100 150
µA
I
DD
Supply current
V
O
= 1.5 V,
No load
Full range 200 200 µ
A
†Full range for the TLV2221C is 0°C to 70°C. Full range for the TLV2221I is − 40°C to 85°C.
‡Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
6WWW.TI.COM
operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA†
TLV2221C TLV2221I
UNIT
PARAMETER
TEST CONDITIONS
TA
†
MIN TYP MAX MIN TYP MAX
UNIT
Slew rate at unity
VO = 1.1 V to 1.9 V,
RL = 2 kه,
25°C0.1 0.18 0.1 0.18
SR Slew rate at unity
gain VO = 1.1 V to 1.9 V
,
CL = 100 pF‡RL = 2 kΩ
‡
,Full
range 0.05 0.05 V/µs
Vn
Equivalent input
f = 10 Hz 25°C 120 120
nV/√Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 20 20
nV/√Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 680 680
nV
VN(PP
)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 860 860 nV
InEquivalent input
noise current 25°C 0.6 0.6 fA/√Hz
VO = 1 V to 2 V,
f = 20 kHz,
AV = 1
25°C
2.52% 2.52%
THD+N
Total harmonic
O
f = 20 kHz,
RL = 2 kΩ‡AV = 10 25°C7.01% 7.01%
THD+N
Total harmonic
distortion plus noise VO = 1 V to 2 V,
f = 20 kHz,
AV = 1
25°C
0.076% 0.076%
O
f = 20 kHz,
RL = 2 kΩ§AV = 10 25°C0.147% 0.147%
Gain-bandwidth
product f = 1 kHz,
CL = 100 pF‡RL = 2 kΩ‡,25°C 480 480 kHz
BOM Maximum
output-swing
bandwidth
VO(PP) = 1 V,
RL = 2 kه,AV = 1,
CL = 100 pF‡25°C 30 30 kHz
ts
Settling time
AV = −1,
Step = 1 V to 2 V,
‡
To 0.1% 25°C 4.5 4.5 µs
tsSettling time
Step = 1 V to 2 V,
RL = 2 kه,
C
L
= 100 pF‡To 0.01% 25°C 6.8 6.8 µs
φmPhase margin at
unity gain R
L
= 2 kه,
CL = 100 pF
‡25°C 51°51°
Gain margin
RL = 2 kه,
CL = 100 pF‡
25°C 12 12 dB
†Full range is −40°C to 85°C.
‡Referenced to 1.5 V
§Referenced to 0 V
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLV2221C TLV2221I
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO Input offset voltage 0.61 3 0.61 3 mV
VIO
Temperature
coefficient of input
Full range
1
1
V/°C
αVIO
coefficient of input
offset voltage
Full range
1 1 µV/°C
Input offset voltage
long-term drift
(see Note 4) VDD± = ±2.5 V
,
VO = 0, VIC = 0,
RS = 50 Ω25°C0.003 0.003 µV/mo
IIO
Input offset current
O
S
25°C 0.5 0.5
pA
IIO Input offset current Full range 150 150 pA
IIB
Input bias current
25°C 1 1
pA
IIB Input bias current Full range 150 150 pA
VICR
Common-mode input
RS = 50 Ω
|VIO|≤5 mV
25°C0
to
4
−0.3
to
4.2
0
to
4
−0.3
to
4.2
V
VICR
Common-mode input
voltage range RS = 50 Ω, |VIO| ≤5 mV
Full range 0
to
3.5
0
to
3.5
V
VOH
High-level output
IOH = −500 µA
25°C
4.75 4.88 4.75 4.88
V
VOH
High-level output
voltage IOH = −1 mA 25°C4.5 4.76 4.5 4.76 V
Low-level output
VIC = 2.5 V, IOL = 50 µA 25°C 12 12
V
OL
Low-level output
voltage
VIC = 2.5 V,
IOL = 500 A
25°C 120 120 mV
VOL
voltage
VIC = 2.5 V, IOL = 500 µAFull range 500 500
mV
Large-signal
V = 2.5 V,
RL = 2 kه
25°C 3 5 3 5
A
VD
Large-signal
differential voltage VIC = 2.5 V,
VO = 1 V to 4 V
RL = 2 kΩ
‡
Full range 1 1 V/mV
AVD
differential voltage
amplification
V
O
= 1 V to 4 V
RL = 1 MΩ‡25°C 800 800
V/mV
rid Differential input
resistance 25°C 1012 1012 Ω
ric Common-mode
input resistance 25°C 1012 1012 Ω
cic Common-mode
input capacitance f = 10 kHz 25°C 6 6 pF
zoClosed-loop
output impedance f = 10 kHz, AV = 10 25°C 70 70 Ω
CMRR
Common-mode
VIC = 0 to 2.7 V,
VO = 1.5 V,
25°C 70 85 70 85
dB
CMRR
Common-mode
rejection ratio
VIC = 0 to 2.7 V,
RS = 50 Ω
VO = 1.5 V,
Full range 65 65 dB
kSVR
Supply voltage
rejection ratio
VDD = 4.4 V to 8 V,
25°C 80 95 80 95
dB
kSVR
rejection ratio
(∆VDD /∆VIO)
VDD = 4.4 V to 8 V,
VIC = VDD/2, No load Full range 80 80 dB
IDD
Supply current
VO = 2.5 V,
No load
25°C110 150 110 150
µA
I
DD
Supply current
V
O
= 2.5 V,
No load
Full range 200 200 µ
A
†Full range for the TLV2221C is 0°C to 70°C. Full range for the TLV2221I is − 40°C to 85°C.
‡Referenced to 2.5 V
NOTE 5: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
8WWW.TI.COM
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA†
TLV2221C TLV2221I
UNIT
PARAMETER
TEST CONDITIONS
TA
†
MIN TYP MAX MIN TYP MAX
UNIT
Slew rate at unity
VO = 1.5 V to 3.5 V,
RL = 2 kه,
25°C0.1 0.18 0.1 0.18
SR Slew rate at unity
gain VO = 1.5 V to 3.5 V,
CL = 100 pF‡RL = 2 kΩ
‡
,Full
range 0.05 0.05 V/µs
Vn
Equivalent input
f = 10 Hz 25°C 90 90
nV/√Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 19 19
nV/√Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 800 800
nV
VN(PP
)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 960 960 nV
InEquivalent input
noise current 25°C 0.6 0.6 fA/√Hz
VO = 1.5 V to 3.5 V,
f = 20 kHz,
AV = 1
25°C
2.45% 2.45%
THD+N
Total harmonic
O
f = 20 kHz,
RL = 2 kΩ‡AV = 10 25°C5.54% 5.54%
THD+N
Total harmonic
distortion plus noise VO = 1.5 V to 3.5 V,
f = 20 kHz,
AV = 1
25°C
0.142% 0.142%
O
f = 20 kHz,
RL = 2 kΩ§AV = 10 25°C0.257% 0.257%
Gain-bandwidth
product f = 1 kHz,
CL = 100 pF‡RL = 2 kΩ‡,25°C 510 510 kHz
BOM Maximum output-
swing bandwidth VO(PP) = 1 V,
RL = 2 kه,AV = 1,
CL = 100 pF‡25°C 40 40 kHz
ts
Settling time
AV = −1,
Step = 1.5 V to 3.5 V,
‡
To 0.1% 25°C 6.8 6.8
s
tsSettling time
Step = 1.5 V to 3.5 V,
RL = 2 kه,
C
L
= 100 pF‡To 0.01% 25°C 9.2 9.2 µs
φmPhase margin at
unity gain
RL = 2 k
Ω‡
,
CL = 100 pF
‡25°C 52°52°
Gain margin
RL = 2 kه,
CL = 100 pF‡
25°C 12 12 dB
†Full range is −40°C to 85°C.
‡Referenced to 2.5 V
§Referenced to 0 V
SLOS157B − JUNE 1996 − REVISED APRIL 2005
9
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electrical characteristics at VDD = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLV2221Y
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VIO Input offset voltage
VDD± = ±1.5 V,
VIC = 0,
VO = 0,
620 µV
IIO Input offset current VDD± = ±1.5 V,
RS = 50 Ω
VIC = 0, VO = 0, 0.5 pA
IIB Input bias current
RS = 50 Ω
1 pA
−0.3
VICR
Common-mode input voltage range
|
VIO|
≤
5 mV,
RS = 50
Ω
−0.3
to
V
VICR
Common-mode input voltage range
|
VIO|
≤5 mV,
RS = 50 Ω
to
2.2
V
VOH High-level output voltage IOH = −100 µA 2.97 V
VOL
Low-level output voltage
VIC = 1.5 V, IOL = 50 µA 15
mV
VOL Low-level output voltage VIC = 1.5 V, IOL = 500 µA 150 mV
AVD
Large-signal differential
VO = 1 V to 2 V
RL = 2 kن3
V/mV
AVD
Large-signal differential
voltage amplification VO = 1 V to 2 V RL = 1 Mن250 V/mV
rid Differential input resistance 1012 Ω
ric Common-mode input resistance 1012 Ω
cic Common-mode input capacitance f = 10 kHz 6 pF
zoClosed-loop output impedance f = 10 kHz, AV = 10 90 Ω
CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, VO = 0, RS = 50 Ω82 dB
kSVR Supply voltage rejection ratio (∆VDD/∆VIO) VDD = 2.7 V to 8 V, VIC = 0, No load 95 dB
IDD Supply current VO = 0, No load 100 µA
†Referenced to 1.5 V
electrical characteristics at VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLV2221Y
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VIO Input offset voltage
VDD± = ±1.5 V,
VIC = 0,
VO = 0,
610 µV
IIO Input offset current VDD± = ±1.5 V,
RS = 50 Ω
VIC = 0, VO = 0, 0.5 pA
IIB Input bias current
RS = 50 Ω
1 pA
−0.3
VICR
Common-mode input voltage range
|
VIO|
≤
5 mV,
RS = 50
Ω
−0.3
to
V
VICR
Common-mode input voltage range
|
VIO|
≤5 mV,
RS = 50 Ω
to
4.2
V
VOH High-level output voltage IOH = −500 µA 4.88 V
VOL
Low-level output voltage
VIC = 2.5 V, IOL = 50 µA 12
mV
VOL Low-level output voltage VIC = 2.5 V, IOL = 500 µA 120 mV
AVD
Large-signal differential
VO = 1 V to 4 V
RL = 2 kن5
V/mV
AVD
Large-signal differential
voltage amplification VO = 1 V to 4 V RL = 1 Mن800 V/mV
rid Differential input resistance 1012 Ω
ric Common-mode input resistance 1012 Ω
cic Common-mode input capacitance f = 10 kHz 6 pF
zoClosed-loop output impedance f = 10 kHz, AV = 10 70 Ω
CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, VO = 0, RS = 50 Ω85 dB
kSVR Supply voltage rejection ratio (∆VDD/∆VIO) VDD = 2.7 V to 8 V, VIC = 0, No load 95 dB
IDD Supply current VO = 0, No load 110 µA
†Referenced to 2.5 V
SLOS157B − JUNE 1996 − REVISED APRIL 2005
10 WWW.TI.COM
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution
vs Common-mode input voltage 2, 3
4, 5
αVIO Input offset voltage temperature coefficient Distribution 6, 7
IIB/IIO Input bias and input offset currents vs Free-air temperature 8
VIInput voltage vs Supply voltage
vs Free-air temperature 9
10
VOH High-level output voltage vs High-level output current 11, 14
VOL Low-level output voltage vs Low-level output current 12, 13, 15
VO(PP) Maximum peak-to-peak output voltage vs Frequency 16
IOS Short-circuit output current vs Supply voltage
vs Free-air temperature 17
18
VOOutput voltage vs Differential input voltage 19, 20
AVD Differential voltage amplification vs Load resistance 21
AVD Large signal differential voltage amplification vs Frequency
vs Free-air temperature 22, 23
24, 25
zoOutput impedance vs Frequency 26, 27
CMRR Common-mode rejection ratio vs Frequency
vs Free-air temperature 28
29
kSVR Supply-voltage rejection ratio vs Frequency
vs Free-air temperature 30, 31
32
IDD Supply current vs Supply voltage 33
SR Slew rate vs Load capacitance
vs Free-air temperature 34
35
VOInverting large-signal pulse response vs Time 36, 37
VOVoltage-follower large-signal pulse response vs Time 38, 39
VOInverting small-signal pulse response vs Time 40, 41
VOVoltage-follower small-signal pulse response vs Time 42, 43
VnEquivalent input noise voltage vs Frequency 44, 45
Input noise voltage (referred to input) Over a 10-second period 46
THD + N Total harmonic distortion plus noise vs Frequency 47
Gain-bandwidth product vs Free-air temperature
vs Supply voltage 48
49
φmPhase margin vs Frequency
vs Load capacitance 22, 23
52, 53
Gain margin vs Load capacitance 50, 51
B1Unity-gain bandwidth vs Load capacitance 54, 55
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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TYPICAL CHARACTERISTICS
Figure 2
Precentage of Amplifiers − %
DISTRIBUTION OF TLV2211
INPUT OFFSET VOLTAGE
VIO − Input Offset Voltage − mV
15
10
5
0
20
25
−1.5 −1 −0.5 0 0.5 1 1.5
385 Amplifiers From 1 Wafer Lot
VDD = ±1.5 V
TA = 25°C
Figure 3
Precentage of Amplifiers − %
DISTRIBUTION OF TLV2211
INPUT OFFSET VOLTAGE
VIO − Input Offset Voltage − mV
15
10
5
0
20
25
−1.5 −1 −0.5 0 0.5 1 1.5
VDD = ±2.5 V
TA = 25°C
385 Amplifiers From 1 Wafer Lot
Figure 4
− Input Offset Voltage − mV
INPUT OFFSET VOLTAGE†
vs
COMMON-MODE INPUT VOLTAGE
ÁÁ
ÁÁ
ÁÁ
VIO
VIC − Common-Mode Input Voltage − V
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1−1 0 1 2
VDD = 3 V
RS = 50 Ω
TA = 25°C
3
Figure 5
− Input Offset Voltage − mV
INPUT OFFSET VOLTAGE†
vs
COMMON-MODE INPUT VOLTAGE
ÁÁ
ÁÁ
VIO
VIC − Common-Mode Input Voltage − V
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1−1 0 1 2
VDD = 5 V
RS = 50 Ω
TA = 25°C
345
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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TYPICAL CHARACTERISTICS
Figure 6
DISTRIBUTION OF TLV2221 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT†
Percentage of Amplifiers − %
αVIO − Input Offset Voltage
Temperature Coefficient − µV/°C
15
10
5
0
20
25
−4 −3 −2 0 1 2 3
VDD = ±1.5 V
P Package
TA = 25°C to 125°C
−1 4
32 Amplifiers From 1 Wafer Lot
Figure 7
DISTRIBUTION OF TLV2221 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT†
Percentage of Amplifiers − %
αVIO − Input Offset Voltage
Temperature Coefficient − µV/°C
15
10
5
0
20
25
−4 −3 −2 0 1 2 3
VDD = ±2.5 V
P Package
TA = 25°C to 125°C
−1 4
32 Amplifiers From 1 Wafer Lot
Figure 8
IIB and IIO − Input Bias and Input Offset Currents − pA
INPUT BIAS AND INPUT OFFSET CURRENTS
vs
FREE-AIR TEMPERATURE
IIB IIO
TA − Free-Air Temperature − °C
50
40
20
10
0
90
30
25 45 65 85
70
60
80
100
105 125
VDD± = ±2.5 V
VIC = 0
VO = 0
RS = 50 Ω
IIB
IIO
Figure 9
0
4
1 1.5 2 2.5
− Input Voltage − V
2
1
3
INPUT VOLTAGE
vs
SUPPLY VOLTAGE
5
3 3.5 4
−1
−2
−3
−4
−5
RS = 50 Ω
TA = 25°C
|VIO| ≤5 mV
ÁÁ
ÁÁ
VI
|VDD±| − Supply Voltage − V
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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TYPICAL CHARACTERISTICS
Figure 10
− Input Voltage − V
INPUT VOLTAGE†‡
vs
FREE-AIR TEMPERATURE
ÁÁ
VI
TA − Free-Air Temperature − °C
2
1
0
3
4
5
−1
−55 −35 −15 5 25 45 65 85
|VIO| ≤5 mV
VDD = 5 V
105 125
Figure 11
− High-Level Output Voltage − V
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
VOH
|IOH| − High-Level Output Current − mA
1.5
1
0.5
00 0.5 1 1.5 2 2.5 3
2
2.5
3
3.5 4 4.5 5
VDD = 3 V
TA = −40°C
TA = 25°C
TA = 85°C
TA = 125°C
Figure 12
0.6
0.4
0.2
00123
− Low-Level Output Voltage − V
0.8
1
LOW-LEVEL OUTPUT VOLTAGE‡
vs
LOW-LEVEL OUTPUT CURRENT
1.2
45
ÁÁ
ÁÁ
VOL
IOL − Low-Level Output Current − mA
VDD = 3 V
TA = 25°C
VIC = 0
VIC = 0.75 V
VIC = 1.5 V
Figure 13
− Low-Level Output Voltage − V
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
VOL
IOL − Low-Level Output Current − mA
0.4
0.2
1.2
0012 3
0.8
0.6
1
1.4
45
TA = 85°C
TA = − 40°C
TA = 25°C
TA = 125°C
VDD = 3 V
VIC = 1.5 V
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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TYPICAL CHARACTERISTICS
Figure 14
− High-Level Output Voltage − V
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
VOH
|IOH| − High-Level Output Current − mA
2
1
00123 4
3
4
5
5678
VDD = 5 V
VIC = 2.5 V
TA = −40°C
TA = 25°C
TA = 85°C
TA = 125°C
Figure 15
− Low-Level Output Voltage − V
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
VOL
IOL − Low-Level Output Current − mA
0.6
0.4
0.2
001 2 3
1
1.2
1.4
456
0.8
VDD = 5 V
VIC = 2.5 V
TA = −40°C
TA = 85°C
TA = 25°C
TA = 125°C
Figure 16
− Maximum Peak-to-Peak Output Voltage − V
f − Frequency − Hz
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE‡
vs
FREQUENCY
ÁÁ
ÁÁ
ÁÁ
VO(PP)
4
2
1
5
3
0102103104105
RL = 2 kΩ
TA = 25°C
VDD = 5 V
VDD = 3 V
Figure 17
− Short-Circuit Output Current − mA
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
IOS
VDD − Supply Voltage − V
2
−8
−4
0
4
8
12
16
20
345678
VO = VDD/2
TA = 25°C
VIC = VDD/2
VID = −100 mV
VID = 100 mV
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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TYPICAL CHARACTERISTICS
Figure 18
− Short-Circuit Output Current − mA
SHORT-CIRCUIT OUTPUT CURRENT†‡
vs
FREE-AIR TEMPERATURE
IOS
TA − Free-Air Temperature − °C
20
16
12
8
4
0
−4
−8
−75 −50 −25 0 25 50 75 100 125
VDD = 5 V
VIC = 2.5 V
VO = 2.5 V
VID = −100 mV
VID = 100 mV
Figure 19
543210−1−2−3−4−5
0
0.5
1
1.5
2
2.5
3VDD = 3 V
RI = 2 kΩ
VIC = 1.5 V
TA = 25°C
OUTPUT VOLTAGE‡
vs
DIFFERENTIAL INPUT VOLTAGE
VID − Differential Input Voltage − V
− Output Voltage − V
VO
Figure 20
543210−1−2−3−4−5
0
1
2
3
4
5
VDD = 5 V
VIC = 2.5 V
RL = 2 kΩ
TA = 25°C
OUTPUT VOLTAGE‡
vs
DIFFERENTIAL INPUT VOLTAGE
VID − Differential Input Voltage − V
− Output Voltage − V
VO
Figure 21
DIFFERENTIAL VOLTAGE AMPLIFICATION‡
vs
LOAD RESISTANCE
RL − Load Resistance − kΩ
− Differential Voltage Amplification − V/mV
ÁÁ
ÁÁ
ÁÁ
AVD
110
1102103
102
101
1
103
VDD = 5 V
VDD = 3 V
VO(PP) = 2 V
TA = 25°C
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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TYPICAL CHARACTERISTICS
om − Phase Margin
φm
f − Frequency − Hz
LARGE-SIGNAL DIFFERENTIAL VOLTAGE†
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
AVD − Large-Signal Differential
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
104
Gain
Phase Margin
20
80
60
40
0
−20
−40
180°
135°
90°
45°
0°
−45°
−90°
105106107
VDD = 5 V
RL = 2 kΩ
CL= 100 pF
TA = 25°C
Figure 22
om − Phase Margin
φm
f − Frequency − Hz
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN†
vs
FREQUENCY
AVD − Large-Signal Differential
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
Gain
Phase Margin
VDD = 3 V
RL = 2 kΩ
CL= 100 pF
TA = 25°C
104
20
80
60
40
0
−20
−40
180°
135°
90°
45°
0°
−45°
−90°
105106107
Figure 23
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
17
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TYPICAL CHARACTERISTICS
Figure 24
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†‡
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
− Large-Signal Differential Voltage AVD Amplification − V/mV
−50 −25 0 25 50 75 100
RL = 2 kΩ
RL = 1 MΩ
103
102
1
VDD = 3 V
VIC = 1.5 V
VO = 0.5 V to 2.5 V
−75 125
101
Figure 25
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†‡
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
− Large-Signal Differential Voltage
AVD Amplification − V/mV
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
RL = 2 kΩ
RL = 1 MΩ
−50 −25 0 25 50 75 100 125
104
103
102
1
−75
101
Figure 26
− Output Impedance −
f− Frequency − Hz
OUTPUT IMPEDANCE‡
vs
FREQUENCY
Ω
zo
1
101103104105
102
VDD = 3 V
TA = 25°C
AV = 100
AV = 10
AV = 1
10
100
1000
Figure 27
− Output Impedance −
f− Frequency − Hz
OUTPUT IMPEDANCE‡
vs
FREQUENCY
Ω
zo
VDD = 5 V
TA = 25°C
AV = 100
AV = 10
AV = 1
10
1
0.1
1000
100
101103104105
102
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
18 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 28
CMRR − Common-Mode Rejection Ratio − dB
f − Frequency − Hz
COMMON-MODE REJECTION RATIO†
vs
FREQUENCY
80
40
20
0
100
60
101102103104105106
VDD = 5 V
VIC = 2.5 V
TA = 25°C
VDD = 3 V
VIC = 1.5 V
Figure 29
CMMR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO†‡
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
88
86
84
82
80
78
−75 −50 −25 0 25 50 75 100 125
VDD = 5 V
VDD = 3 V
Figure 30
− Supply-Voltage Rejection Ratio − dB
f − Frequency − Hz
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREQUENCY
ÁÁ
ÁÁ
ÁÁ
kSVR
60
40
20
100
80
0
−20
101102103104105106
kSVR+
kSVR−
VDD = 3 V
TA = 25°C
Figure 31
− Supply-Voltage Rejection Ratio − dB
f − Frequency − Hz
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREQUENCY
ÁÁ
ÁÁ
ÁÁ
kSVR
VDD = 5 V
TA = 25°C
kSVR−
kSVR+
100
80
60
40
20
0
−20
101102103104105106
‡Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
19
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TYPICAL CHARACTERISTICS
Figure 32
− Supply-Voltage Rejection Ratio − dB
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREE-AIR TEMPERATURE
ÁÁ
ÁÁ
ÁÁ
kSVR
TA − Free-Air Temperature − °C
−50 −25 0 25 50 75 100 125−75
VDD = 2.7 V to 8 V
VIC = VO = VDD /2
100
98
96
94
92
90
Figure 33
− Supply Current − Aµ
ÁÁ
ÁÁ
ÁÁ
IDD
VDD − Supply Voltage − V
SUPPLY CURRENT†
vs
SUPPLY VOLTAGE
TA = 25°CTA = 85°C
TA = −40°C
VO = 0
No Load
200
175
150
125
100
75
50
25
00246810
Figure 34
SR − Slew Rate −
SLEW RATE‡
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
sµ
V/
0.5
101
0.4
0.3
0.2
0.1
0102103104105
VDD = 5 V
AV = −1
TA = 25°C
SR−
SR+
Figure 35
SR − Slew Rate −
SLEW RATE†‡
vs
FREE-AIR TEMPERATURE
sµ
V/
TA − Free-Air Temperature − °C
0.2
0.1
0
0.3
0.4
0.5
−50 −25 0 25 50 75 100
VDD = 5 V
RL = 2 kΩ
CL = 100 pF
AV = 1
−75 125
SR−
SR+
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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TYPICAL CHARACTERISTICS
Figure 36
− Output Voltage − V
INVERTING LARGE-SIGNAL PULSE
RESPONSE†
VO
t − Time − µs
AV = −1
TA = 25°C
VDD = 3 V
RL = 2 kΩ
CL = 100 pF
1.5
1
0.5
0
2
2.5
3
0 5 10 15 20 25 30 35 40 45 50
Figure 37
INVERTING LARGE-SIGNAL PULSE
RESPONSE†
t − Time − µs
− Output Voltage − V
VO
2
1
00 5 10 15 20 25 30
3
4
5
35 40 45 50
VDD = 5 V
RL = 2 kΩ
CL = 100 pF
AV = −1
TA = 25°C
Figure 38
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE†
− Output Voltage − V
VO
t − Time − µs
1
00 5 10 15 20 25 30
2
3
35 40 45 50
AV = 1
TA = 25°C
VDD = 5 V
RL = 2 kΩ
CL = 100 pF
4
5
Figure 39
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE†
− Output Voltage − V
VO
t − Time − µs
2
1
00 5 10 15 20 25 30
3
4
5
35 40 45 50
VDD = 5 V
CL = 100 pF
AV = 1
TA = 25°CRL = 100 kΩ
Tied to 2.5 V
RL = 2 kΩ
Tied to 2.5 V RL = 2 kΩ
Tied to 0 V
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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TYPICAL CHARACTERISTICS
Figure 40
INVERTING SMALL-SIGNAL
PULSE RESPONSE†
− Output Voltage − V
VO
t − Time − µs
0.82
0
0.8
0.78
0.76
0.74
0.72
0.7 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VDD = 3 V
RL = 2 kΩ
CL = 100 pF
AV = −1
TA = 25°C
Figure 41
VO − Output Voltage − V
INVERTING SMALL-SIGNAL
PULSE RESPONSE†
VO
t − Time − µs
VDD = 5 V
RL = 2 kΩ
CL = 100 pF
AV = −1
TA = 25°C
2.58
0
2.56
2.54
2.52
2.5
2.48
2.46
2.44 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 42
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE†
VO − Output Voltage − V
VO
t − Time − µs
0.82
0
0.8
0.78
0.76
0.74
0.72
0.7 12345678910
VDD = 3 V
RL = 2 kΩ
CL = 100 pF
AV = 1
TA = 25°C
Figure 43
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE†
VO − Output Voltage − V
VO
t − Time − µs
2.58
0
2.56
2.54
2.52
2.5
2.48
2.46
2.44 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VDD = 5 V
RL = 2 kΩ
CL = 100 pF
AV = 1
TA = 25°C
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
22 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 44
− Equivalent Input Noise Voltage −
f − Frequency − Hz
EQUIVALENT INPUT NOISE VOLTAGE†
vs
FREQUENCY
VnnV/ Hz
101102103104
120 VDD = 3 V
RS = 20 Ω
TA = 25°C
100
80
60
40
20
0
Figure 45
− Equivalent Input Noise Voltage −
f − Frequency − Hz
EQUIVALENT INPUT NOISE VOLTAGE†
vs
FREQUENCY
VnnV/ Hz
VDD = 5 V
RS = 20 Ω
TA = 25°C
101102103104
120
100
80
60
40
20
0
Figure 46
Input Noise Voltage − nV
t − Time − s
INPUT NOISE VOLTAGE OVER
A 10-SECOND PERIOD†
0246
750
1000
810
500
−250
−500
−750
−1000
250
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
0
Figure 47
THD + N − Total Harmonic Distortion Plus Noise − %
f − Frequency − Hz
TOTAL HARMONIC DISTORTION PLUS NOISE†
vs
FREQUENCY
10110210310410
5
0.1
10
0.01
1
AV = 1
AV = 10
AV = 1
AV = 10
VDD = 5 V
TA = 25°C
RL = 2 kΩ Tied to 2.5 V
RL = 2 kΩ Tied to 0 V
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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TYPICAL CHARACTERISTICS
Figure 48
Gain-Bandwidth Product − kHz
GAIN-BANDWIDTH PRODUCT†‡
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
500
400
300
200
600
700
800
−50 −25 0 25 50 10075
VDD = 5 V
f = 10 kHz
RL = 2 kHz
CL = 100 pF
125−75
Figure 49
Gain-Bandwidth Product − kHz
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
500
450
425
400
550
575
600
525
475
0235 78146
RL = 2k
CL = 100 pF
TA = 25°C
Figure 50
Gain Margin − dB
GAIN MARGIN
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
Rnull = 500 Ω
Rnull = 200 Ω
Rnull = 0
20
10
5
0
15
101102103105
104
Rnull = 1 kΩ
TA = 25°C
RL = ∞
Figure 51
CL − Load Capacitance − pF
101102103105
104
Rnull = 1 kΩ
Rnull = 500 Ω
Rnull = 100 Ω
Rnull = 0
TA = 25°C
RL = 2 kΩ
20
15
10
5
0
Gain Margin − dB
GAIN MARGIN
vs
LOAD CAPACITANCE
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
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TYPICAL CHARACTERISTICS
Figure 52
om − Phase Margin
PHASE MARGIN
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
m
φ
101102103105
75°
60°
45°
30°
15°
0°
Rnull = 200 Ω
Rnull = 500 Ω
Rnull = 0
Rnull = 1 kΩ
104
TA = 25°C
RL = ∞
Figure 53
CL − Load Capacitance − pF
101102103105
75°
60°
45°
30°
15°
0°104
Rnull = 1 kΩ
Rnull = 500 Ω
Rnull = 100 Ω
Rnull = 0
TA = 25°C
RL = 2 kΩ
om − Phase Margin
PHASE MARGIN
vs
LOAD CAPACITANCE
m
φ
Figure 54
− Unity-Gain Bandwidth − kHz
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
ÁÁ
ÁÁ
B1
600
101102103104105
500
400
300
200
100
0
TA = 25°C
RL = ∞
Figure 55
CL − Load Capacitance − pF
101102103105
104
TA = 25°C
RL = 2 kΩ
600
500
400
300
200
100
0
− Unity-Gain Bandwidth − kHz
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
ÁÁ
ÁÁ
ÁÁ
B1
SLOS157B − JUNE 1996 − REVISED APRIL 2005
25
WWW.TI.COM
APPLICATION INFORMATION
driving large capacitive loads
The TLV2221 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 50
through Figure 55 illustrate its ability to drive loads greater than 100 pF while maintaining good gain and phase
margins (Rnull = 0).
A small series resistor (Rnull) at the output of the device (Figure 56) improves the gain and phase margins when
driving large capacitive loads. Figure 50 through Figure 53 show the effects of adding series resistances of
100 Ω, 200 Ω, 500 Ω, and 1 kΩ. The addition of this series resistor has two ef fects: the first ef fect is that it adds
a zero to the transfer function and the second effect is that it reduces the frequency of the pole associated with
the output load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the approximate improvement in phase margin, equation 1 can be used.
∆φm1 +tan–1 ǒ2×π×UGBW×Rnull ×CLǓ
∆φm1 +improvement in phase margin
UGBW +unity-gain bandwidth frequency
Rnull +output series resistance
CL+load capacitance
(1)
where :
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (Figure 54 and Figure
55). To use equation 1, UGBW must be approximated from Figure 54 and Figure 55.
VDD−/GND
VDD+
Rnull
CL
VI+
−
RL
Figure 56. Series-Resistance Circuit
The TLV2221 is designed to provide better sinking and sourcing output currents than earlier CMOS rail-to-rail
output devices. This device is specified to sink 500 µA and source 1 mA at VDD = 5 V at a maximum quiescent
IDD of 200 µA. This provides a greater than 80% power efficiency.
When driving heavy dc loads, such as 2 kΩ, the positive edge under slewing conditions can experience some
distortion. This condition can be seen in Figure 38. This condition is affected by three factors:
DWhere the load is referenced. When the load is referenced to either rail, this condition does not occur. The
distortion occurs only when the output signal swings through the point where the load is referenced.
Figure 39 illustrates two 2-kΩ load conditions. The first load condition shows the distortion seen for a 2-kΩ
load tied to 2.5 V. The third load condition in Figure 39 shows no distortion for a 2-kΩ load tied to 0 V.
DLoad resistance. As the load resistance increases, the distortion seen on the output decreases. Figure 39
illustrates the difference seen on the output for a 2-kΩ load and a 100-kΩ load with both tied to 2.5 V.
DInput signal edge rate. Faster input edge rates for a step input result in more distortion than with slower input
edge rates.
SLOS157B − JUNE 1996 − REVISED APRIL 2005
26 WWW.TI.COM
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 6) and subcircuit in Figure 57 are generated using
the TLV2221 typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
−
+
−
+
−
+
−
+
−
+
−
+
−+
−
+−
.SUBCKT TLV2221 1 2 3 4 5
C1 11 12 12.53E−12
C2 6 7 50.00E−12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY (5) VB VC VE VLP
+ VLN 0 893.6E3 −90E3 90E3 90E3 −90E3
GA 6 0 11 12 94.25E−6
GCM 0 6 10 99 9.300E−9
ISS 3 10 DC 9.000E−6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100.0E3
RD1 60 11 10.61E3
RD2 60 12 10.61E3
R01 8 5 35
R02 7 99 35
RP 3 4 49.50E3
RSS 10 99 22.22E6
VAD 60 4 −.5
VB 9 0 DC 0
VC 3 53 DC .666
VE 54 4 DC .666
VLIM 7 8 DC 0
VLP 91 0 DC 3.4
VLN 0 92 DC 11.4
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=500.0E−15 BETA=1.527E−3
+ VTO=−.001)
.ENDS
VDD+
RP
IN − 2
IN+ 1
VDD−
VAD
RD1
11
J1 J2
10
RSS ISS
3
12
RD2
60
VE
54 DE
DP
VC
DC
4
C1
53
R2 6
9
EGND
VB
FB
C2
GCM GA VLIM
8
5RO1
RO2
HLIM
90 DLP
91
DLN
92
VLNVLP
99
7
Figure 57. Boyle Macromodel and Subcircuit
PSpice and Parts are trademark of MicroSim Corporation.
"!#!)% %#&)$! #!)% !" !$+" #!)% '"! (.
"$). !" "$). " !$ -""$ (. % &)). "'"%$/ ))
! $+ %'$! !'"$/ +"$"%$% ! $+
%#!&$!" '"!&$ $! -++ $+ #!) ")$%*
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV2221CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2221CDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2221CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2221CDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2221IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2221IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2221IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2221IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2221CDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2221CDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2221IDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2221IDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2221CDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
TLV2221CDBVT SOT-23 DBV 5 250 182.0 182.0 20.0
TLV2221IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
TLV2221IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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