1
®
FN7436.8
EL8176
Micropower Single Supply Rail-to-Rail
Input-Output Precision Op Amp
The EL8176 is a precision low power, operational amplifier.
The device is optimized for single supply operation between
2.4V to 5.5V.
The EL8176 draws minimal supply current while meeting
excellent DC-accuracy noise and output drive specifications.
Competing devices seriously degrade these parameters to
achieve micropower supply current.
The EL8176 can be operated from one lithium cell or two
Ni-Cd batteries. The input range includes both positive and
negative rail. The output swings to both rails.
Features
55µA supply current
100µV max offset voltage (8 Ld SO)
2nA input bias current
400kHz gain-bandwidth product
Single supply operation down to 2.4V
Rail-to-rail input and output
Output sources 31 mA an d sinks 26mA load curr ent
Pb-free plus (RoHS compliant)
Applications
Battery- or solar-powered systems
4mA to 20mA current loops
Handheld consumer products
Medical devices
Thermocouple amplifiers
Photodiode pre amps
pH probe amplifiers
Ordering Information
PART
NUMBER PART
MARKING PACKAGE
(Pb-Free) PKG.
DWG. #
EL8176FWZ-T7*
(Note 1) BBVA 6 Ld SOT-23 MDP0038
EL8176FWZ-T7A*
(Note 1) BBVA 6 Ld SOT-23 MDP0038
EL8176FSZ
(Note 1) 8176FSZ 8 Ld SO MDP0027
EL8176FSZ-T7*
(Note 1) 8176FSZ 8 Ld SO MDP0027
EL8176FIZ-T7*
(Note 2) 176Z 6 Ld WLCSP
(1.5mmx1.0mm) W3x2.6C
*Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temper atures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. These Intersil Pb-free WLCSP and BGA packaged product s
products employ special Pb-free material sets; molding
compounds/die attach materials and SnAgCu - e1 solder ball
terminals, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP
and BGA packaged products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Data Sheet April 3, 2009
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2006, 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN7436.8
April 3, 2009
Pinouts
EL8176
(6 LD SOT-23)
TOP VIEW
EL8176
(8 LD SO)
TOP VIEW
EL8176
(6 LD WLCSP)
TOP VIEW
1
2
3
6
4
5
+-
OUT
V-
IN+
V+
EN
IN-
1
2
3
4
8
7
6
5
-
+
NC
IN-
IN+
EN
V+
OUT
V- NC
21
A
B
C
OUT
V-
IN+
DNC*
V+
IN-
*DO NOT CONNECT
EL8176
3FN7436.8
April 3, 2009
Absolute Maximum Ratings (TA = +25°C) Thermal Information
Supply Voltage (VS) and Pwr-up Ramp Rate . . . . . . . 5.75V, 1V/µs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Current into IN+, IN-, and EN. . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Tolerance
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance (Typical, Note 3) θJA (°C/W)
6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230
6 Ld WLCSP Package . . . . . . . . . . . . . . . . . . . . . . . 130
8 Ld SO Package. . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Ambient Operating Temperature Range . . . . . . . . -40°C to +125°C
Storage Temperature R ange . . . . . . . . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, VEN = 0V, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
PARAMETER DESCRIPTION CONDITIONS MIN
(Note 4) TYP MAX
(Note 4) UNIT
DC SPECIFICAT IONS
VOS Input Offset Voltage 8 Ld SO -100 ±25 100 µV
-220 220 µV
6 Ld SOT-23 -350 ±80 350 µV
-350 350 µV
WLCSP -500 -75 500 µV
Long Term Input Offset Voltage Stability 2.4 µV/Mo
Input Offset Drift vs Temperature 0.7 µV/°C
IOS Input Offset Current -1 ±0.4 1 nA
-4 4 nA
IBInput Bias Current -2 ±0.5 2 nA
-5 5 nA
CMIR Input Voltage Range Guaranteed by CMRR test 0 5 V
CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 90 110 dB
90 dB
PSRR Power Supply Rejection Ratio VS = 2.4V to 5.5V 90 110 dB
90 dB
AVOL Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ200 500 V/mV
200 V/mV
VO = 0.5V to 4.5V, RL = 1kΩ25 V/mV
ΔVOS
ΔTime
------------------
ΔVOS
ΔT
----------------
EL8176
4FN7436.8
April 3, 2009
VOUT Maximum Output Voltage Swing
SOT-23/SO-8 VOL; Output low, RL = 100kΩ38mV
10 mV
VOL; Output low, RL = 1kΩ130 200 mV
300 mV
VOH; Output high, RL = 100kΩ4.994 4.997 V
4.992 V
VOH; Output high, RL = 1kΩ4.750 4.867 V
4.7 V
Maximum Output Voltage Swing
WLCSP VOL; Output low, RL = 100kΩ38mV
10 mV
VOL; Output low, RL = 1kΩ130 200 mV
300 mV
VOH; Output high, RL = 100kΩ4.991 4.997 V
VOH; Output high, RL = 1kΩ4.750 4.867 V
4.7 V
IS,ON Supply Current, Enabled VEN = 5V, SOT-23/SO-8 35 55 75 µA
30 90 µA
VEN = 5V, WLCSP 60 85 110 µA
55 120 µA
IS,OFF Supply Current, Disabled VEN = 0V, SOT-23/SO-8 only 3 10 µA
10 µA
IO+ Short Circuit Output Sourcing Current RL = 10Ω18 31 mA
18 mA
IO- Short Circuit Output Sinking Current RL = 10Ω17 26 mA
15 mA
VSSupply Voltage Guaranteed by PSRR test 2.4 5.5 V
2.4 5.5 V
VINH Enable Pin High Level SOT-23 and SO packages only 2 V
VINL Enable Pin Low Level SOT-23 and SO packages only 0.8 V
IENH Enable Pin Input Current VEN = 5V,
SOT-23 and SO packages only 0.25 0.7 2.0 µA
2.5 µA
IENL Enable Pin Input Current VEN = 0V,
SOT-23 and SO packages only -0.5 0 +0.5 µA
-1 +1 µA
AC SPECIFICAT IONS
GBW Gain Bandwidth Product AV = 100, RF = 100kΩ, RL = 10kΩ,
RG=1kΩ to VCM 400 kHz
Unity Gain
Bandwidth -3dB Bandwidth AV = 1, RF = 0Ω, RL = 100kΩ to VCM,
VOUT = 10mVP-P 1MHz
Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, VEN = 0V, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN
(Note 4) TYP MAX
(Note 4) UNIT
EL8176
5FN7436.8
April 3, 2009
eNInput Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz, RL = 10kΩ to VCM 1.5 µVP-P
Input Noise Voltage Density fO = 1kHz 28 nV/Hz
iNInput Noise Current Density fO = 1kHz 0.16 pA/Hz
ISO Off-State Input to Output Isolation VEN = 5V, fO = 1kHz, AV = +1, VIN = 1VP-P
SOT-23 and SO packages only -73 dB
CMRR Input Common Mode Rejection Ratio fO = 120Hz; VCM = 1VP-P, -70 dB
PSRR+ Power Supply Rejection Ratio (V+)f
O = 120Hz; V+, V- = ±2.5V,
VSOURCE =1V
P-P -90 dB
PSRR- Power Supply Rejection Ratio (V-)f
O = 120Hz; V+, V- = ±2.5V,
VSOURCE =1V
P-P -70 dB
TRANSIENT RESPONSE
SR Slew Rate ±0.065 ±0.13 ±0.3 V/µs
tr, tf, Large
Signal Rise Time, 10% to 90%, VOUT AV
= +2,
VOUT = 2VP-P, Rg = Rf = R
L
=
10kΩ
to VCM 18 µs
Fall Time, 90% to 10%, VOUT AV
= +2,
VOUT = 2VP-P, Rg = Rf = R
L
=
10kΩ
to VCM 19 µs
tr, tf, Small
Signal Rise Time, 10% to 90%, VOUT AV
= +2,
VOUT = 10mVP-P,
Rg = Rf = R
L
=
10kΩ to VCM 2.4 µs
Fall Time, 90% to 10%, VOUT AV
= +2,
VOUT = 10mVP-P,
Rg = Rf = R
L
=
10kΩ to VCM 2.4 µs
tEN Enable to Output Turn-on Delay T ime, 10%
EN to 10% VOUT (SOT-23, SO packages) VEN = 5V to 0V, AV
= +2,
Rg = Rf = R
L
=
10kΩ to VCM s
Enable to Output Turn-of f Delay Time, 10%
EN to 10% VOUT (SOT-23, SO packages) VEN = 0V to 5V, AV
= +2,
Rg = Rf = R
L
=
10kΩ to VCM 0.1 µs
NOTE:
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization
and are not production tested.
Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, VEN = 0V, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN
(Note 4) TYP MAX
(Note 4) UNIT
Typical Performance Curves
FIGURE 1. AVOL vs FREQUENCY @ 1kΩ LOAD FIGURE 2. AVOL vs FREQUENCY @ 100kΩ LOAD
-20
GAIN (dB)
0
20
80
100
40
60
10 10k 1M
FREQUENCY (Hz)
100 -150
PHASE (°)
200
150
100
50
0
-50
-100
100k1k
PHASE
GAIN
-80
GAIN (dB)
40
120
80
-40
0
1 1k 100k 10M
FREQUENCY (Hz)
10 -120
PHASE (°)
80
40
0
-40
-80
10k 1M100
EL8176
6FN7436.8
April 3, 2009
FIGURE 3. GAIN vs FREQUENCY vs FEEDBACK RESISTOR
VALUES Rf/Rg
FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 1k
FIGURE 5. GAIN vs FREQUENCY vs VOUT, RL = 10k FIGURE 6. GAIN vs FREQUENCY vs VOUT, RL = 100k
FIGURE 7. GAIN vs FREQUENCY vs RLFIGURE 8. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
Typical Performance Curves (Continued)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100 1k 10k 100k 1M
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
Rf = Rg = 1k
Rf = Rg = 10k
Rf = Rg = 100k
V+ = 5V
RL = 10k
AV = +2
VOUT = 10mVP-P
CL = 8.3pF
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
100 1k 10k 100k 1M 10M
10 FREQUENCY (Hz)
NORMALIZED GAIN (dB)
VOUT = 100mV
VOUT = 10mV
VOUT = 50mV
VOUT = 1V
V+ = 5V
RL = 1k
AV = +1
CL = 8.3pF
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
100 1k 10k 100k 1M 10M
10 FREQUENCY (Hz)
NORMALIZED GAIN (dB)
-8
VOUT = 50mV
VOUT = 100mV
VOUT = 10mV
VOUT = 1V
V+ = 5V
RL = 10k
AV = +1
CL = 8.3pF -7
-6
-5
-4
-3
-2
-1
0
1
2
3
100 1k 10k 100k 1M 10M
10 FREQUENCY (Hz)
NORMALIZED GAIN (dB)
-8
VOUT = 50mV
VOUT = 100mV
VOUT = 10mV
VOUT = 1V
V+ = 5V
RL = 100k
AV = +1
CL = 8.3pF
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
100 1k 10k 100k 1M 10M
10 FREQUENCY (Hz)
NORMALIZED GAIN (dB)
-8
R
L
= 100k
RL = 10k
R
L
= 1k
V+ = 5V
AV = +1
VOUT = 10mVP-P
CL = 8.3pF
100 1k 10k 100k 1M 10M
10
-10
0
10
20
30
40
50
60
70
AV = 1
AV = 101
AV = 1001
FREQUENCY
(Hz)
GAIN (dB)
A
V
= 1001, R
g
= 1k, R
f
= 1M
AV = 1, Rg = INF, Rf = 0
A
V
= 101, R
g
= 1k, R
f
= 100k
AV = 10
AV = 10, Rg = 1k, Rf = 9.09k
V+ = 5V
VOUT = 10mVP-P
CL = 8.3pF
RL = 10k
EL8176
7FN7436.8
April 3, 2009
FIGURE 9. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FIGURE 10. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 11. GAIN vs FREQUENCY vs CLFIGURE 12. CMRR vs FREQUENCY; V+, V- = ±2.5V
FIGURE 13. PSRR vs FREQUENCY, V+, V- = ±2.5V FIGURE 14. OFF ISOLATION vs FREQUENCY; V+, V- = ±2.5V
Typical Performance Curves (Continued)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
1k 10k 100k 1M 10M
FREQUENCY
(Hz)
GAIN (dB)
V+ = 2V
V+ = 2.5V
V+ = 5V
RL = 10k
AV = +1
V
OUT
= 10mV
P-P
CL = 8.3pF
RL = 10k
CL = 8.3pF
AV = 100
VOUT = 10mVP-P
RF = 221kΩ
RG = 2.23kΩ
0
5
10
15
20
25
30
35
40
45
100 1k 10k 100k 1M
FREQUENCY (Hz)
GAIN (dB)
V+ = 2V
V+ = 2.5V
V+ = 5V
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
CL = 64.3pF
CL = 47.3pF
CL = 35.3pF
CL = 26.3pF
CL = 8.3pF
V+ = 5V
RL = 10k
AV = +1
VOUT = 10mVP-P
1k 10k 100k 1M 10M -120
-100
-80
-60
-40
-20
0
20
1 10 100 1k 10k 100k 1M
CMRR (dB)
FREQUENCY (Hz)
V+ = 5V
RL = OPEN
AV = +1
VCM = 1VP-P
CL = 8.3pF
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
1 10 100 1k 10k 100k 1M
PSRR (dB )
FREQUENCY (Hz)
V+ = 5V
RL = OPEN
AV = +1
VCM = 1VP-P
CL = 8.3pF PSRR-
PSRR+
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1 10 100 1k 10k 100k 1M
OFF ISOLATION (dB)
FREQUENCY (Hz)
V+ = 5V
RL = OPEN
AV = +1
VIN = 1VP-P
CL = 8.3pF
10M
EL8176
8FN7436.8
April 3, 2009
FIGURE 15. INPUT VOLT AGE NOISE DENSITY vs FREQUENCY FIGURE 16. INPUT CURRENT NOISE DENSITY vs FREQUENCY
FIGURE 17. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz FIGURE 18. LARGE SIGNAL STEP RESPONSE
FIGURE 19. SMALL SIGNAL STEP RESPONSE FIGURE 20. ENABLE TO OUTPUT RESPONSE
Typical Performance Curves (Continued)
10
100
1000
0.1 1 10 100 1k 10k
FREQUENCY (Hz)
INPUT VOLTAGE NOISE (nVHz)
V+ = 5V
RL = OPEN
AV = +1
CL = 8.3pF
0.1
1
10
0.1 1 10 100 1k 10k
FREQUENCY (Hz)
INPUT CURRENT NOISE (pAHz)
V+ = 5V
RL = OPEN
AV = +1
CL = 8.3pF
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
012345678910
TIME (s)
V+ = 5V
RL = OPEN
Rg = 10, Rf = 10k
AV = 1000
CL = 8.3pF
INPUT NOISE (µV)
-2.5
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
2.5
0 50 100 150 200 250 300 350 400
TIME (µs)
LARGE SIGNAL (V)
V+, V- = ±2.5V
RL = 10k
Rg = 10k
AV = 4
CL = 8.3pF
VOUT = 4VP-P
Rf = 30k
-2
0
2
4
6
8
10
12
0 50 100 150 200 250 300 350 400
TIME (µs)
SMALL SIGNAL (mV)
V+, V- = ±2.5V
RL = 10k
Rg = Rf = 10k
AV = 2
CL = 8.3pF
VOUT = 10mVP-P
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
0 20 40 60 80 100 120 140 160 180 200
TIME (µs)
V-ENABLE (V)
OUTPUT (V)
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
V+, V- = ±2.5V
Rg = Rf = RL = 10k
AV = +2
VOUT = 2VP-P
CL = 8.3pF
VENABLE
VOUT
EL8176
9FN7436.8
April 3, 2009
FIGURE 21 . INPUT OF FSET VOLT AGE v s COMMON-MOD E
INPUT VOLTAGE FIGURE 22. INPUT OFFSET CURRENT vs COMMON-MODE
INPUT VOLTAGE
FIGURE 23. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE FIGURE 24. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 25. SUPPL Y CURRENT vs TEMPERA TURE
VS = ±2.5V ENABLED. RL = INF FIGURE 26. SUPPL Y CURRENT vs TEMPERA TURE
VS = ±2.5V ENABLED. RL = INF
Typical Performance Curves (Continued)
-100
-80
-60
-40
-20
0
20
40
60
80
100
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCM (V)
VIO (µV)
V+, V- = ±2.5V
Rg = 100
AV = +11
VOUT = 2VP-P
CL = 8.3pF
Rf = 10k
RL = INF
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
IBIAS (µA)
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCM (V)
V+, V- = ±2.5V
Rg = 100
AV = +11
VOUT = 2VP-P
CL = 8.3pF
Rf = 10k
RL = INF
-200
INPUT OFFSET VOLTAGE (µV)
-100
0
150
200
50
100
05
OUTPUT VOLTAGE (V)
1324
VCM = VDD/2
AV = -1
-150
-50 VDD = 2.5V
VDD = 5V
2.0 3.5 4.0 5.5
SUPPLY VOLTAGE (V)
2.5 5.04.53.0
0
SUPPLY CURRENT (µA)
20
50
60
30
40
10
45
50
55
60
65
70
75
-40-200 20406080100120
TEMPERATURE (°C)
n = 12
MAX
MEDIAN
MIN
SO, SOT-23 PACKAGE
SUPPLY CURRENT (µA)
60
65
70
75
80
85
90
95
100
SUPPLY CURRENT (µA)
n = 12
MAX
MEDIAN
MIN
WLCSP
-40-200 20406080100120
TEMPERATURE (°C)
EL8176
10 FN7436.8
April 3, 2009
FIGURE 27. DISABLED SUPPL Y CURRENT vs
TEMPERATURE VS = ±2.5V RL= INF FIGURE 28. IBIAS (+) vs TEMPERATURE VS = ±2.5V
FIGURE 29. IBIAS (+) vs TEMPERATURE VS = ±1.2V FIGURE 30. IBIAS (-) vs TEMPERATURE VS = ±2.5V
FIGURE 31. IBIAS (-) vs TEMPERATURE VS = ±1.2V FIGURE 32. INPUT OFFSET CURRENT vs TEMPERA TURE
VS = ±2.5V
Typical Performance Curves (Continued)
0
1
2
3
4
5
6
7
-40-200 20406080100120
TEMPERATURE (°C)
n = 12
MAX
MEDIAN
MIN
DISABLED SUPPLY CURRENT (µA)
-0.5
0
0.5
1.0
1.5
2.0
2.5
-40-200 20406080100120
TEMPERATURE (°C)
CURRENT (nA)
n = 12
MAX
MEDIAN
MIN
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
CURRENT (nA)
n = 12
MEDIAN
MIN
MAX
-0.5
0
0.5
1.0
1.5
2.0
2.5
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
CURRENT (nA)
n = 12
MIN
MEDIAN
MAX
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
CURRENT (nA)
n = 12
MAX
MEDIAN
MIN
-0.5
0
0.5
1.0
1.5
2.0
2.5
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
CURRENT (nA)
n = 12
MAX
MEDIAN
MIN
EL8176
11 FN7436.8
April 3, 2009
FIGURE 33. INPUT OFFSET CURRENT vs TEMPERA TURE
VS = ±1.2V FIGURE 34. INPUT OFFSET VOLT AGE vs TEMPERATURE
VS = ±2.5V
FIGURE 35. INPUT OFFSET VOL TAGE vs TEMPERA TURE
VS = ±1.2V FIGURE 36. INPUT OFFSET VOLT AGE vs TEMPERATURE
VS = ±2.5V
FIGURE 37. INPUT OFFSET VOL TAGE vs TEMPERA TURE
VS = ±1.2V FIGURE 38. INPUT OFFSET VOLT AGE vs TEMPERATURE
VS = ±2.5V
Typical Performance Curves (Continued)
-0.5
0
0.5
1.0
1.5
2.0
2.5
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
CURRENT (nA)
n = 12
MAX
MEDIAN
MIN
-50
50
100
150
200
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
VOS (µV)
SO PACKAGE
n = 12
MAX
MEDIAN
0MIN
-50
0
50
100
150
200
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
VOS (µV)
SO PACKAGE
n = 12
MAX
MIN
MEDIAN
-200
-100
0
100
200
300
400
-40-200 20406080100120
TEMPERATURE (°C)
VOS (µV)
n = 12 SOT-23 PACKAGE
MAX
MEDIAN
MIN
-200
-150
-100
-50
0
50
100
150
200
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
VOS (µV)
n = 12 SOT-23 PACKAGE
MAX
MEDIAN
MIN
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
VOS (µV)
150
100
50
0
50
100
150
n = 12
MAX
MEDIAN
MIN
WLCSP
EL8176
12 FN7436.8
April 3, 2009
FIGURE 39. INPUT OFFSET VOL TAGE vs TEMPERA TURE
VS = ±1.2V FIGURE 40. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V
FIGURE 41. PSRR vs TEMPERATURE VS = ±1.2V TO ±2.5V FIGURE 42. POSITIVE VOUT vs TEMPERA TURE RL = 1k
VS = ±2.5V
FIGURE 43. NEGA TIVE VOUT vs TEMPERATURE RL = 1k
VS = ±2.5V FIGURE 44. POSITIVE VOUT vs TEMPERA TURE RL = 100k
VS = ±2.5V
Typical Performance Curves (Continued)
-150
-100
-50
0
50
100
150 n = 12
MAX
MEDIAN
MIN
WLCSP
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
VOS (µV)
95
100
105
110
115
120
125
-40 -20 0 20 40 60 80 100 120
TEMPERAT URE (°C)
CMRR (dB)
n = 12
MAX
MEDIAN
MIN
95
100
105
110
115
120
125
130
135
140
-40 -20 0 20 40 60 80 100 120
TEMPERAT URE (°C)
PSRR (dB)
n = 12
MAX
MEDIAN
MIN
4.82
4.83
4.84
4.85
4.86
4.87
4.88
4.89
4.90
4.91
-40 -20 0 20 40 60 80 100 120
VOUT (V)
n = 12
TEMPERATURE (°C)
MAX
MEDIAN
MIN
80
100
120
140
160
180
200
220
240
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
VOUT (mV)
n = 12
MAX MEDIAN
MIN
4.9962
4.9964
4.9966
4.9968
4.9970
4.9972
4.9974
4.9976
4.9978
4.9980
4.9982
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
VOUT (V)
n = 12
MAX
MIN
MAX
MEDIAN
EL8176
13 FN7436.8
April 3, 2009
FIGURE 45. NEGA TIVE VOUT vs TEMPERATURE RL = 100k
VS = ±2.5V FIGURE 46. +SLEW RA TE vs TEMPERATURE VS = ±2.5V
INPUT = ±0.75V, AV = 2
FIGURE 47. -SLEW RA TE vs TEMPERATURE VS = ±2.5V
INPUT = ±0.75V, AV = 2 FIGURE 48. AVOL, RL = 100k, VS ±2.5V, VO = ±2V
Pin Descriptions
SO PIN
NUMBER SOT-23 PIN
NUMBER 6 Ld WLCSP
PIN NUMBER PIN NAME EQUIVALENT
CIRCUIT DESCRIPTION
1, 5 NC No internal connection
2 4 C1 IN- Circuit 1 Amplifier’s inverting input
3 3 C2 IN+ Circuit 1 Amplifier’s non-inverting input
4 2 B2 V- Circuit 4 Negative power supply
A1 DNC Do not connect. Pin must be left floating.
6 1 A2 OUT Circuit 3 Amplifier’s output
7 6 B1 V+ Circuit 4 Positive power supply
85 EN
Circuit 2 Amplifier’s enable pin with internal pull-down; Logic “1” selects the
disabled state; Logic “0” selects the enabled state.
Typical Performance Curves (Continued)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
VOUT (mV)
n = 12
MAX
MEDIAN MIN
0.09
0.11
0.13
0.15
0.17
0.19
0.21
0.23
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
SLEW RATE (V/µs)
n = 12
MIN
MAX MEDIAN
0.10
0.11
0.12
0.13
0.14
0.15
0.16
0.17
-40-200 20406080100120
TEMPERATURE (°C)
CURRENT (pA)
n = 12
MEDIAN
MIN
MAX
0
100
200
300
400
500
600
700
800
900
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
AVOL (V/mV)
n = 12
MEDIAN
MAX
MIN
EN OUT
CIRCUIT 3CIRCUIT 2
CAPACITIVELY
COUPLED
ESD CLAMP
CIRCUIT 4
V+V+V+
V- V- V-
IN+IN-
V+
V-
CIRCUIT 1
EL8176
14 FN7436.8
April 3, 2009
Applications Information
Introduction
The EL8176 is a rail-to-rail inp ut and output micro-power
precision single supply operational ampl ifier with an enable
feature. The device achieves rail-to-rail input and output
operation and eliminates the concerns introduced by a
conventional rail-to-rail I/O operational amplifier as
discussed below.
Rail-to-Rail Input
The input common-mode voltage range of the EL8176 goes
from negative supply to positive supply without introducing
offset errors or degrading performance associated with a
conventional rail-to-rail input operational amplifier. Many
rail-to-rail input st ag es use two differential input pairs, a
long-tail PNP (or PFET) and an NPN (or NFET). Seve re
penalties have to be p aid fo r this circuit top olog y. As the input
signal moves from one su pply rail to anothe r, the operational
amplifier switches from one input p air to the other ca using
drastic changes in input offset volt age an d an undesi red
change in magnitude and polarity of input of fset curren t.
The EL8176 achieves input rail-to-rail without sacrificing
important precision specifications and without degrading
distortion performance. The EL8176's input offset voltage
exhibits a smooth behavior throughout the entire
common-mode input range. The input bias current versus
the common-mode voltage range for the EL8176 gives us an
undistorted behavior from typically 10mV above the negative
rail all the way up to the positi ve rail.
Input Bias Current Compensation
The input bias currents as low as 500pA are achieved while
maintaining an excellent bandwidth for a micro-power
operational amplifier. Inside the EL8176 is an input bias
canceling circuit. The input stage transistors are still biased
with an adequate current for speed but the canceling circuit
sinks most of the base current, leaving a small fraction as
input bias current. The input bias curre nt
compensation/cancellation is stable from -40°C to +125°C
and operates from typically 10mV to the positive supply rail.
Rail-to-Rail Output
A pair of complement ary MOSFET devices achieves rail-to-rail
output swing. The NMOS sinks current to swing the output in
the negative direction. The PMOS sources current to swing the
output in the positive direction. The EL8176 with a 100kΩ load
will swing to within 3mV of the supply rails.
Enable/Disable Feature
The EL8176, in the SOT-23 and SO packages, offers an EN
pin. The active low EN pin disables the device when pulled
up to at least 2.0V. When disabled, the output is in a high
impedance state and the part consumes typically 3µA. When
disabled, the high impedance output allo ws multi ple parts to
be MUXed together . When configured as a MUX, the outputs
are tied together in parallel and a channel can be selected by
pulling the EN pin to 0.8V or lower.T he EN pin has an
internal pull-down. If left open or floating, the EN pin will
internally be pulled low, enabling the part by default.
Proper Layout Maximizes Performance
To achieve th e maximum performance of the high input
impedance and low offset voltage of the EL8176, care
should be taken in the circuit board layout. The PC board
surface must remain clean and free of moisture to avoid
leakage currents between adjacent traces. Surface coating
of the circuit board will reduce surface moisture and provide
a humidity barrier, reducing parasitic resistance on the
board. The use of guard rings around the amplifier inputs will
further reduce leakage currents. Figure 49 shows how the
guard ring should be configured and Figure 50 shows the top
view of how a surface mount layout can be arranged. The
guard ring does not need to be a specific width, but it should
form a continuous loop around both inputs. By setting the
guard ring voltage equal to the voltage at the non-inverting
input, parasitic capacitance is minimized as well. For further
reduction of leakage currents, components can be mounted
to the PC board using Teflon standoff insulators.
4
3
1
EL8176
IN
V+
FIGURE 49.
HIGH IMPEDANCE INPUT
6
52
FIGURE 50.
EL8176
15 FN7436.8
April 3, 2009
Typical Applications
Thermocouples are the most popular temperature-sensing
device because of their low cost, interchangeability, and
ability to measure a wide range of temperatures. The
EL8176 is used to convert the differential thermocouple
voltage into single-ended signal with 10X gain . T he
EL8176's rail-to-rail input characteristic allows the
thermocouple to be biased at ground and the converter to
run from a single 5V supply.
-
+
5V
+
V+
V-
EL8176
K TYPE
THERMOCOUPLE
10kΩR3
10kΩR2
R4
100kΩ
R1
100kΩ
410µV/°C
FIGURE 51. THERMOCOUPLE AMPLIFIER
EL8176
16 FN7436.8
April 3, 2009
EL8176
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1 L
L1
DETAIL X 4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
INCHES
TOLERANCE NOTESSO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
17 FN7436.8
April 3, 2009
EL8176
SOT-23 Package Family
e1
N
A
D
E
4
321
E1
0.15 DC
2X 0.20 C
2X
e
B0.20 MDC A-B
b
NX
6
2 3
5
SEATING
PLANE
0.10 C
NX
1 3
C
D
0.15 A-BC
2X
A2
A1
H
c
(L1)
L
0.25
+3°
-0°
GAUGE
PLANE
A
MDP0038
SOT-23 PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCESOT23-5 SOT23-6
A 1.45 1.45 MAX
A1 0.10 0.10 ±0.05
A2 1.14 1.14 ±0.15
b 0.40 0.40 ±0.05
c 0.14 0.14 ±0.06
D 2.90 2.90 Basic
E 2.80 2.80 Basic
E1 1.60 1.60 Basic
e 0.95 0.95 Basic
e1 1.90 1.90 Basic
L 0.45 0.45 ±0.10
L1 0.60 0.60 Reference
N 5 6 Reference
Rev. F 2/07
NOTES:
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
6. SOT23-5 version has no center lead (shown as a dashed line).
18
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Inter sil or it s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7436.8
April 3, 2009
EL8176
Wafer Level Chip Scale Package (WLCSP)
PIN 1 ID
A
E1
BOTTOM VIEW
CBAb
D1
SIDE VIEW
A1
A2
TOP VIEW
D
E
SD 2
1
e
SE
b
W3x2.6C
3x2 ARRAY 6 BALL WAFER LEVEL CHIP SCALE PACKAGE
SYMBOL MILLIMETERS
A 0.51 Min, 0.55 Max
A10.225 ±0.015
A20.305 ±0.013
bΦ0.323 ±0.025
D 0.955 ±0.020
D10.50 BASIC
E 1.455 ±0.020
E11.00 BASIC
e 0.50 BASIC
SD 0.25 BASIC
SE 0.00 BASIC
Rev. 3 03/08
NOTES:
1. All dimensions are in millimeters.