EBU WAN PLL
IDT82V32021
Version 3
April 24, 2015
6024 Silver Creek Valley Road, San Jose, CA 95138
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775
Printed in U.S.A.
© 2009 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos-
sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is exe-
cuted between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents 3 April 24, 2015
FEATURES.............................................................................................................................................................................. 8
HIGHLIGHTS....................................................................................................................................................................................................8
MAIN FEATURES............................................................................................................................................................................................8
OTHER FEATURES.........................................................................................................................................................................................8
APPLICATIONS....................................................................................................................................................................... 8
DESCRIPTION......................................................................................................................................................................... 9
FUNCTIONAL BLOCK DIAGRAM........................................................................................................................................ 10
1 PIN ASSIGNMENT ...........................................................................................................................................................11
2 PIN DESCRIPTION ..........................................................................................................................................................12
3 FUNCTIONAL DESCRIPTION .........................................................................................................................................16
3.1 RESET ...........................................................................................................................................................................................................16
3.2 MASTER CLOCK ....................................................... .................................................... .... ...........................................................................16
3.3 INPUT CLOCKS & FRAME SYNC SIGNALS ...............................................................................................................................................17
3.3.1 Input Clocks .................................................................................................................................................................................... 17
3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 17
3.4 INPUT CLOCK PRE-DIVIDER ......................................................................................................................................................................18
3.5 INPUT CLOCK QUALITY MONITORING .....................................................................................................................................................19
3.5.1 Activity Monitoring ......................................................................................................................................................................... 19
3.5.2 Frequency Monitoring ................................................................................................................................................................... 20
3.6 DPLL INPUT CLOCK SELECTION ..............................................................................................................................................................21
3.6.1 External Fast Selection .................................................................................................................................................................. 21
3.6.2 Forced Selection ............................................................................................................................................................................ 22
3.6.3 Automatic Selection ....................................................................................................................................................................... 22
3.7 SELECTED INPUT CLOCK MONITORING ..................................................................................................................................................23
3.7.1 DPLL Locking Detection ................................................................................................................................................................ 23
3.7.1.1 Fast Loss .......................................................................................................................................................................... 23
3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 23
3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 23
3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 23
3.7.2 Locking Status ............................................................................................................................................................................... 23
3.7.3 Phase Lock Alarm .......................................................................................................................................................................... 23
3.8 SELECTED INPUT CLOCK SWITCH ...........................................................................................................................................................25
3.8.1 Input Clock Validity ........................................................................................................................................................................ 25
3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 25
3.8.2.1 Revertive Switch ............................................................................................................................................................... 25
3.8.2.2 Non-Revertive Switch ....................................................................................................................................................... 25
3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 25
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE .......................................................................................................27
3.10 DPLL OPERATING MODE ...........................................................................................................................................................................29
3.10.1 Six Operating Modes ..................................................................................................................................................................... 29
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 29
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 29
3.10.1.3 Locked Mode .................................................................................................................................................................... 29
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 29
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 29
3.10.1.5 Holdover Mode ................................................................................................................................................................. 29
Table of Contents
Table of Contents 4 April 24, 2015
IDT82V32021 EBU WAN PLL
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 30
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 30
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 30
3.10.1.5.4 Manual ........................................................................................................................................................... 30
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 30
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 30
3.11 DPLL OUTPUT ..............................................................................................................................................................................................32
3.11.1 PFD Output Limit ............................................................................................................................................................................ 32
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 32
3.11.3 PBO ................................................................................................................................................................................................. 32
3.11.4 Four Paths of T0 DPLL Output ...................................................................................................................................................... 32
3.12 T0 APLL ........................................................................................................................................................................................................34
3.13 OUTPUT CLOCK & FRAME SYNC SIGNALS .............................................................................................................................................34
3.13.1 Output Clock ................................................................................................................................................................................... 34
3.13.2 Frame SYNC Output Signal ........................................................................................................................................................... 36
3.14 INTERRUPT SUMMARY ...............................................................................................................................................................................38
3.15 T0 SUMMARY ...............................................................................................................................................................................................38
3.16 LINE CARD APPLICATION ..........................................................................................................................................................................39
4 I2C PROGRAMMING INTERFACE ..................................................................................................................................40
4.1 FUNCTION DESCRIPTION ...........................................................................................................................................................................40
4.1.1 Data Transfer Format ..................................................................................................................................................................... 41
4.1.1.1 Slave-receiver Mode (Write) ............................................................................................................................................. 41
4.1.1.2 Slave-transmitter Mode (Read) ........................................................................................................................................ 41
4.1.2 Address Assignment ..................................................................................................................................................................... 42
4.2 TIMING DEFINITION .....................................................................................................................................................................................42
5 JTAG ................................................................................................................................................................................44
6 PROGRAMMING INFORMATION ....................................................................................................................................45
6.1 REGISTER MAP ............................................................................................................................................................................................45
6.2 REGISTER DESCRIPTION ...........................................................................................................................................................................49
6.2.1 Global Control Registers ............................................................................................................................................................... 49
6.2.2 Interrupt Registers ......................................................................................................................................................................... 56
6.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 60
6.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 65
6.2.5 T0 DPLL Input Clock Selection Registers .................................................................................................................................... 73
6.2.6 T0 DPLL State Machine Control Registers .................................................................................................................................. 75
6.2.7 T0 DPLL & T0 APLL Configuration Registers .............................................................................................................................. 77
6.2.8 Output Configuration Registers .................................................................................................................................................... 88
6.2.9 PBO & Phase Offset Control Registers ........................................................................................................................................ 90
6.2.10 Synchronization Configuration Registers ................................................................................................................................... 91
7 THERMAL MANAGEMENT .............................................................................................................................................92
7.1 JUNCTION TEMPERATURE ........................................................................................................................................................................92
7.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION .....................................................................................................................92
7.3 HEATSINK EVALUATION ............................................................................................................................................................................92
7.4 VFQFPN EPAD THERMAL RELEASE PATH ..............................................................................................................................................93
8 ELECTRICAL SPECIFICATIONS ....................................................................................................................................94
8.1 ABSOLUTE MAXIMUM RATING ..................................................................................................................................................................94
8.2 RECOMMENDED OPERATION CONDITIONS ............................................................................................................................................94
8.3 I/O SPECIFICATIONS ...................................................................................................................................................................................95
8.3.1 CMOS Input / Output Port .............................................................................................................................................................. 95
8.4 JITTER & WANDER PERFORMANCE .........................................................................................................................................................97
8.5 OUTPUT WANDER GENERATION ..............................................................................................................................................................99
8.6 INPUT / OUTPUT CLOCK TIMING .............................................................................................................................................................100
IDT82V32021 EBU WAN PLL
5 April 24, 2015
8.7 OUTPUT CLOCK TIMING ...........................................................................................................................................................................101
PACKAGE DIMENSIONS - 68-PIN NL ............................................................................................................................... 106
ORDERING INFORMATION................................................................................................................................................ 108
DATASHEET DOCUMENT HISTORY ................................................................................................................................. 108
List of Tables 6 April 24, 2015
Table 1: Pin Description ............................................................................................................................................................................................. 12
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 16
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 17
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 18
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 20
Table 6: Input Clock Selection ................................................................................................................................................................................... 21
Table 7: External Fast Selection ................................................................................................................................................................................ 21
Table 8: ‘n’ Assigned to the Input Clock ..................................................................................................................................................................... 22
Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 22
Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 23
Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 23
Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 24
Table 13: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 26
Table 14: T0 DPLL Operating Mode Control ............................................................................................................................................................... 27
Table 15: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 28
Table 16: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 29
Table 17: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 30
Table 18: Holdover Frequency Offset Read ................................................................................................................................................................ 30
Table 19: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 31
Table 20: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 33
Table 21: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 34
Table 22: Output on OUT1 if Derived from T0 DPLL Output ....................................................................................................................................... 34
Table 23: Output on OUT1 if Derived from T0 APLL ................................................................................................................................................... 35
Table 24: Frame Sync Input Signal Selection .............................................................................................................................................................. 36
Table 25: Synchronization Control ............................................................................................................................................................................... 36
Table 26: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 37
Table 27: Related Bit / Register in Chapter 3.14 ......................................................................................................................................................... 38
Table 28: Definition of S/Sr and P Conditions ............................................................................................................................................................. 40
Table 29: Timing Definition for Standard Mode and Fast Mode(1) .............................................................................................................................. 43
Table 30: JTAG Timing Characteristics ....................................................................................................................................................................... 44
Table 31: Register List and Map .................................................................................................................................................................................. 45
Table 32: Power Consumption and Maximum Junction Temperature ......................................................................................................................... 92
Table 33: Thermal Data ............................................................................................................................................................................................... 92
Table 34: Absolute Maximum Rating ........................................................................................................................................................................... 94
Table 35: Recommended Operation Conditions .......................................................................................................................................................... 94
Table 36: CMOS Input Port Electrical Characteristics ................................................................................................................................................. 95
Table 37: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics .................................................................................................. 95
Table 38: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ............................................................................................. 95
Table 39: CMOS Output Port Electrical Characteristics .............................................................................................................................................. 96
Table 40: Output Clock Jitter Generation .................................................................................................................................................................... 97
Table 41: Output Clock Phase Noise ........................................................................................................................................................................... 97
Table 42: Input Jitter Tolerance (155.52 MHz) ............................................................................................................................................................ 98
Table 43: Input Jitter Tolerance (1.544 MHz) .............................................................................................................................................................. 98
Table 44: Input Jitter Tolerance (2.048 MHz) .............................................................................................................................................................. 98
Table 45: Input Jitter Tolerance (8 kHz) ...................................................................................................................................................................... 98
Table 46: T0 DPLL Jitter Transfer & Damping Factor ................................................................................................................................................. 98
Table 47: Input/Output Clock Timing ......................................................................................................................................................................... 100
Table 48: Output Clock Timing .................................................................................................................................................................................. 101
List of Tables
List of Figures 7 April 24, 2015
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 10
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 11
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 18
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 19
Figure 5. External Fast Selection ................................................................................................................................................................................ 21
Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 27
Figure 7. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 36
Figure 8. 0.5 UI Early Frame Sync Input Signal Timing .............................................................................................................................................. 36
Figure 9. 0.5 UI Late Frame Sync Input Signal Timing ............................................................................................................................................... 37
Figure 10. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 37
Figure 11. Line Card Application ................................................................................................................................................................................. 39
Figure 12. Data Transfer on the I2C-bus ..................................................................................................................................................................... 40
Figure 13. Slave-receiver Mode ................................................................................................................................................................................... 41
Figure 14. Slave-transmitter Mode .............................................................................................................................................................................. 41
Figure 15. Address Assignment ................................................................................................................................................................................... 42
Figure 16. Timing Definition of I2C-bus ....................................................................................................................................................................... 42
Figure 17. JTAG Interface Timing Diagram ................................................................................................................................................................. 44
Figure 18. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................... 93
Figure 19. Output Wander Generation ........................................................................................................................................................................ 99
Figure 20. Input / Output Clock Timing ...................................................................................................................................................................... 100
Figure 21. 68-Pin NL Package Dimensions (a) (in Millimeters) ................................................................................................................................. 106
Figure 22. 68-Pin NL Package Dimensions (b) (in Millimeters) ................................................................................................................................. 107
List of Figures
8 April 24, 2015
IDT82V32021
2009 Integrated Device Technology, Inc. DSC-7071/3
EBU WAN PLL
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
FEATURES
HIGHLIGHTS
• The first single PLL chip:
-Features 1.2 Hz to 560 Hz bandwidth
-Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/
Option I) jitter generation requirements
-Provides node clocks for Cellular and WLL base-station (GSM
and 3G networks)
-Provides clocks for DSL access concentrators (DSLAM), espe-
cially for Japan TCM-ISDN network timing based ADSL equip-
ments
MAIN FEATURES
• Provides an integrated single-chip solution for Synchronous Equip-
ment Timing Source, including 4E and 4 clocks
• Employs DPLL and APLL to feature excellent jitter performance
and minimize the number of the external components
• Supports Forced or Automatic operating mode switch controlled by
an internal state machine; the primary operating modes are Free-
Run, Locked and Holdover
• Supports programmable DPLL bandwidth (1.2 Hz to 560 Hz in 8
steps) and damping factor (1.2 to 20 in 5 steps)
• Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8
ppm instantaneous holdover accuracy
• Supports PBO to minimize phase transients on T0 DPLL output to
be no more than 0.61 ns
• Supports phase absorption when phase-time changes on T0
selected input clock are greater than a programmable limit over an
interval of less than 0.1 seconds
• Limits the phase and frequency offset of the output
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock fail-
ure
• Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
• Provides two 2 kHz, 4 kHz or 8 kHz frame sync input signals, and
an 8 kHz frame sync output signal
• Provides two input clocks whose frequency cover from 2 kHz to
155.52 MHz
• Provides one output clock whose frequency covers from 1Hz to
155.52 MHz
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Supports CMOS input/output
• Supports master clock calibration
• Supports Line Card application
• Meets Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812,
ITU-T G.813 and ITU-T G.783 criteria
OTHER FEATURES
•I
2C programming interface
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 68-pin VFQFPN package, Green package options available
APPLICATIONS
• BITS / SSU
• SMC / SEC (SONET / SDH)
• DWDM cross-connect and transmission equipments
• Central Office Timing Source and Distribution
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• IP and ATM core switches and access equipments
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipments
• Any other telecom equipments that need synchronous equipment
system timing
IDT82V32021 EBU WAN PLL
Description 9 April 24, 2015
DESCRIPTION
The IDT82V32021 is an integrated, single-chip solution for the Syn-
chronous Equipment Timing Source for 4E and 4 clocks in SONET /
SDH equipments, DWDM and Wireless base station, such as GSM, 3G,
DSL concentrator, Router and Access Network applications.
The device supports three types of input clock sources: recovered
clock from STM-N or OC-n, PDH network synchronization timing and
external synchronization reference timing.
An input clock is automatically or manually selected for DPLL lock-
ing. The DPLL supports three primary operating modes: Free-Run,
Locked and Holdover. In Free-Run mode, the DPLL refers to the master
clock. In Locked mode, the DPLL locks to the selected input clock. In
Holdover mode, the DPLL resorts to the frequency data acquired in
Locked mode. Whatever the operating mode is, the DPLL gives a stable
performance without being affected by operating conditions or silicon
process variations.
If the DPLL outputs are processed by T0 APLL, the outputs of the
device will be in a better jitter/wander performance.
A high stable input is required for the master clock in different appli-
cations. The master clock is used as a reference clock for all t he in ternal
circuits in the device. It can be calibrated within ±741 ppm.
All the read/write registers are accessed only through an I2C pro-
gramming interface.
The device can be used typically in Line Card application.
IDT82V32021 EBU WAN PLL
Functional Block Diagram 10 April 24, 2015
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
Monitors
T0 PFD
& LPF
Divider
APLL Microprocessor Interf ace JTAG
PBO
Phase O ff set
T0
APLL
OUT1
OUT1
MUX
T0
APLL
MUX
T0 Input
Selector
OSCI
77.76 MHz
16E1/16T1
12E1/24T1/E3/T3
Auto
Divider
6
T0 DPLL
Input
IN1_CMOS
EX_SYNC1
IN2_CMOS
EX_SYNC2
FRSYNC_8K
Output
GSM/OBSAI/16E1/16T1
Input Pre-Divider Priority
Input Pre-Divider Priority Divider
EX_SYNC1
EX_SYNC2
FRSYN
C_8K
MUX
IDT82V32021 EBU WAN PLL
Pin Assignment 11 April 24, 2015
1 PIN ASSIGNMENT
Figure 2. Pin Assignment (Top View)
IDT82V32021
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
RST
SCL
AD2
AD1
AD0
IC10
NC
IC9
TMS
DGND5
VDDD5
VDDD5
TRST
VDDD5
IC8
IC7
EX_SYNC2
AGND
IC1
AGND1
VDDA1
NC
INT_REQ
OSCI
DGND1
VDDD1
VDDD3
DGND3
DGND2
VDDD2
FF_SRCSW
VDDA2
AGND2
IC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
SONET/SDH
IC16
IC15
IC14
IC13
IC12
NC
AGND3
VDDA3
OUT1
IC11
VDDD6
DGND6
SDA
TDI
TDO
TCK
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
FRSYNC_8K
IC17
IC18
IC19
GND_DIFF
VDD_DIFF
IC3
IC4
IC5
IC6
NC
NC
EX_SYNC1
IN1_CMOS
IN2_CMOS
DGND4
VDDD4
IDT82V32021 EBU WAN PLL
Pin Description 12 April 24, 2015
2 PIN DESCRIPTION
Table 1: Pin Description
Name Pin No. I/O Type Description 1
Global Control Signal
OSCI 7 I CMOS OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
FF_SRCSW 14 I
pull-down CMOS
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH) 2. The
EXT_SW bit determines whether the External Fast Selection is enabled.
High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is
enabled);
Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is dis-
abled).
After reset, this pin selects an input clock for the T0 DPLL if the External Fast selection is
enabled:
High: IN1_CMOS is selected.
Low: IN2_CMOS is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
SONET/SDH 68 I
pull-down CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST 51 I
pull-up CMOS RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will
still be held in reset state for 500 ms (typical).
Frame Synchronization Input Signal
EX_SYNC1 30 I
pull-down CMOS EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
EX_SYNC2 35 I
pull-down CMOS EX_SYNC2: External Sync Input 2
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
Input Clock
IN1_CMOS 31 I
pull-down CMOS IN1_CMOS: Input Clock 1
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN2_CMOS 32 I
pull-down CMOS IN2_CMOS: Input Clock 2
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
Output Frame Synchronization Signal
FRSYNC_8K 18 O CMOS FRSYNC_8K: 8 kHz Frame Sync Output
An 8 kHz signal is output on this pin.
Output Clock
OUT1 59 O CMOS
OUT1: Output Clock 1
A 1 Hz, 400 Hz, 2 kHz, 8 k Hz, 64 kHz, N x E1 (i ncludes 65.536 MHz) 4, N x T1 5, N x 13.0
MHz 6, N x 3.84 MHz 7, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz , 38.88 MHz, 51 .84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
IDT82V32021 EBU WAN PLL
Pin Description 13 April 24, 2015
I2C Programming Interface
INT_REQ 6 O CMOS INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the
HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
AD0
AD1
AD2
47
48
49
ICMOS
AD[2:0]: Address Input 2 to 0
The address is input on these pins.
SCL 50 I CMOS
SCL: Serial Clock Line
The serial clock is input on this pin. The clock is 100 kbit/s in Standard mode and 400 kbit/s in
Fast mode.
Should be pulled high via a 10 kresistor.
SDA 55 I/O CMOS SDA: Serial Data Input/Output
This pin is used as the input/output for the serial data.
Should be pulled high via a 10 kresistor.
JTAG (per IEEE 1149.1)
TRST 39 I
pull-down CMOS TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS 43 I
pull-up CMOS TMS: JTAG Test Mode Select
The signal on this pin control s the JTAG test performanc e and is sampled on the rising edg e
of TCK.
TCK 52 I
pull-down CMOS
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all s tored -sta te de vic es c on tain ed in the test logic will indefinitely
retain their state.
TDI 54 I
pull-up CMOS TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
TDO 53 O CMOS
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the LOS_-
FLAG_ON_TDO bit (b6, 0BH). Refer to Chapter 3.8.1 Input Clock Validity for details.
Power & Ground
VDDD1
VDDD2
VDDD3
VDDD4
VDDD5
VDDD6
9
13
10
34
38, 40, 41
57
Power -
VDDDn: 3.3 V Digital Power Supply
Each VDDDn should be paralleled with ground through a 0.1 µF capacitor.
VDDA1
VDDA2
VDDA3
4
15
60
Power -
VDDAn: 3.3 V Analog Power Supply
Each VDDAn should be paralleled with ground through a 0.1 µF capacitor.
Table 1: Pin Description (Continued)
Name Pin No. I/O Type Description 1
IDT82V32021 EBU WAN PLL
Pin Description 14 April 24, 2015
VDD_DIFF 23 Power - VDD_DIFF: 3.3 V Power Supply
DGND1
DGND2
DGND3
DGND4
DGND5
DGND6
8
12
11
33
42
56
Ground -
DGNDn: Digital Ground
AGND1
AGND2
AGND3
3
16
61
Ground -
AGNDn: Analog Ground
GND_DIFF 22 Ground - GND_DIFF: Ground
AGND 1 Ground - AGND: Analog Ground
Table 1: Pin Description (Continued)
Name Pin No. I/O Type Description 1
IDT82V32021 EBU WAN PLL
Pin Description 15 April 24, 2015
Others
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
IC10
IC11
IC12
IC13
IC14
IC15
IC16
IC17
IC18
IC19
2
17
24
25
26
27
36
37
44
46
58
63
64
65
66
67
19
20
21
--
IC: internally connected
Internal Use. These pins should be left open for normal operation.
NC 5, 28, 29, 45, 62 - - NC: Not Connected
Note:
1. All the unused input pins should be connected to ground; the output of all the unused output pins are don’t-care.
2. The contents in the bra ckets indicate the position of the register bit/bits.
3. N x 8 kHz: 1 < N < 19440.
4. N x E1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64.
5. N x T1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96.
6. N x 13.0 MHz: N = 1, 2, 4.
7. N x 3.84 MHz: N = 1, 2, 4, 8, 16, 10, 20, 40.
Table 1: Pin Description (Continued)
Name Pin No. I/O Type Description 1
IDT82V32021 EBU WAN PLL
Functional Des cription 16 April 24, 2015
3 FUNCTIONAL DESCRIPTION
3.1 RESET
The reset operation resets all registers and state machines to their
default value or status.
After power on, the device must be reset for normal operation.
For a complete reset, the RST pin must be asserted low for at least
50 µs. After the RST pin is pulled high, the device will still be in reset
state for 500 ms (typical). If the RST pin is held low continuously, the
device remains in reset state.
3.2 MASTER CLOCK
A nominal 12.8000 MHz clock, provided by a crystal oscillator, is
input on the OSCI pin. This clock is provided for the device as a master
clock. The master clock is used as a reference clock for all the internal
circuits. A better active edge of the master clock is selected by the
OSC_EDGE bit to improve jitter and wander performance.
In fact, an offset from the nominal frequency may input on the OSCI
pin. This offset can be compensated by setting the NOMINAL_FRE-
Q_VALUE[23:0] bits. The calibration range is within ±741 ppm.
The performance of the master clock should meet GR-1244-CORE,
GR-253-CORE, ITU-T G.812 and G.813 criteria.
Table 2: Related Bit / Register in Chapter 3.2
Bit Register Address (Hex)
NOMINAL_FREQ_VALUE[23:0] NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG 06, 05, 04
OSC_EDGE OSCI_CNFG 0A
IDT82V32021 EBU WAN PLL
Functional Des cription 17 April 24, 2015
3.3 INPUT CLOCKS & FRAME SYNC SIGNALS
Altogether two clocks and two frame sync signals are input to the
device.
3.3.1 INPUT CLOCKS
The device provides two CMOS input clock ports: IN1_CMOS and
IN2_CMOS.
According to the input clock source, the following clock sources are
supported:
•T1: Recovered clock from STM-N or OC-n
•T2: PDH network synchronization timing
•T3: External synchronization reference timing
The clock sources can be from T1, T2 or T3.
For SDH and SONET networks, the default frequency is different.
SONET / SDH frequency selection is controlled by the IN_SONET_SDH
bit. During reset, the default value of the IN_SONET_SDH bit is deter-
mined by the SONET/SDH pin: high for SONET and low for SDH. After
reset, the input signal on the SONET/SDH pin takes no effect.
3.3.2 FRAME SYNC INPUT SIGNALS
Two 2 kHz, 4 kHz or 8 kHz frame sync signals are input on the
EX_SYNC1 and EX_SYNC2 pins respectively. They are CMOS inputs.
The input frequency should match the setting in the SYNC_FREQ[1:0]
bits. The frame sync signals are only valid for the OC-n clock (6.48 MHz,
19.44 MHz, 38.88 MHz and 77.76 MHz) input.
Only one of the two frame sync input signals is used for frame sync
output signal synchronization. Refer to Chapter 3.13.2 Frame SYNC
Output Signal for details.
Table 3: Related Bit / Register in Chapter 3.3
Bit Register Address (Hex)
IN_SONET_SDH INPUT_MODE_CNFG 09
SYNC_FREQ[1:0]
IDT82V32021 EBU WAN PLL
Functional Des cription 18 April 24, 2015
3.4 I NPUT CLOCK PRE-DIVIDER
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
is used to divide the clock frequency down to the DPLL required fre-
quency, which is no more than 38.88 MHz. For each input clock, the
DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits.
If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is
bypassed automatically and the corresponding IN_FREQ[3:0] bits
should be set to match the input frequency; the input clock can be
inverted, as determined by the IN_2K_4K_8K_INV bit.
Each Pre-Divider consists of a DivN Divider and a Lock 8k Divider, as
shown in Figure 3.
Either the DivN Divider or the Lock 8k Divider can be used or both
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
When the DivN Divider is used, the division factor setting should
observe the following order:
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
3. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
Once the division factor is set for the input clock selected by the
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as fol-
lows: Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the IN_-
FREQ[3:0] bits) - 1
The DivN Divider can only divide the input clock whose frequency is
lower than () 155.52 MHz.
When the Lock 8k Divider is used, the input clock is divided down to
8 kHz automatically.
The Pre-Divider configuration and the division factor setting depend
on the input clock on one of the clock input pin and the DPLL required
clock. Here is an example:
The input clock on the IN2_CMOS pin is 155.52 MHz; the DPLL
required clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of
register IN2_CMOS_CNFG to ‘0010’. Do the following to divide the input
clock: Use the DivN Divider to divide the clock down to 6.48 MHz:
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0011’;
Set the DIRECT_DIV bit in Register IN2_CMOS_CNFG to ‘1’
and the LOCK_8K bit in Register IN2_CMOS_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
Figure 3. Pre-Divider for An Input Clock
Table 4: Related Bit / Register in Chapter 3.4
Bit Register Address (Hex)
IN_FREQ[3:0] IN1_CMOS_CNFG, IN2_CMOS_CNFG 16, 17DIRECT_DIV
LOCK_8K
IN_2K_4K_8K_INV FR_SYNC_CNFG 74
PRE_DIV_CH_VALUE[3:0] PRE_DIV_CH_CNFG 23
PRE_DIVN_VALUE[14:0] PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG 25, 24
input clock DivN Divider Lock 8k Divider
Pre-Divider DIRECT_DIV bit LOCK_8K bit
DPLL required clock
IDT82V32021 EBU WAN PLL
Functional Des cription 19 April 24, 2015
3.5 INPUT CLOCK QUALITY MONITORING
The qualities of the input clocks are always monitored in the following
aspects:
•Activity
•Frequency
The qualified clocks are available for T0 DPLL selection. The T0
selected input clock has to be monitored further. Refer to Chapter 3.7
Selected Input Clock Monitoring for details.
3.5.1 ACTIVITY MONITORING
Activity is monitored by using an internal leaky bucket accumulator,
as shown in Figure 4.
Each input clock is assigned an internal leaky bucket accumulator.
The input clock is monitored for each period of 128 ms and the internal
leaky bucket accumulator increases by 1 when an event is detected; it
decreases by 1 if no event is detected within the period set by the decay
rate. The event is that an input clock drifts outside (>) ±500 ppm with
respect to the master clock within a 128 ms period.
There are four configurations (0 - 3) for a leaky bucket accumulator.
The leaky bucket configuration for an input clock is selected by the cor-
responding BUCKET_SEL[1:0] bits. Each leaky bucket configuration
consists of four elements: upper threshold, lower threshold, bucket size
and decay rate.
The bucket size is the capability of the accumulator. If the number of
the accumulated events reach the bucket size, the accumulator will stop
increasing even if further events are detected. The upper threshold is a
point above which a no-activity alarm is raised. The lower threshold is a
point below which the no-activity alarm is cleared. The decay rate is a
certain period during which the accumulator decreases by 1 if no event
is detected.
The leaky bucket configuration is programmed by one of four groups
of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_
THRESHOLD_n_DATA[7:0] bits, the LOWER_THRESHOLD_n_
DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’
is 0 ~ 3.
The no-activity alarm status of the input clock is indicated by the
INn_CMOS_NO_ACTIVITY_ALARM bit (n = 1 or 2).
The input clock with a no-activity alarm is disqualified for clock selec-
tion for T0 DPLL.
Figure 4. Input Clock Activity Monitoring
Input Clock
Leaky Bucket Accumulator
No-activity Alarm Indication
Decay
Rate Bucket S i ze
Upper Threshold
Lower Threshold
0
clock signal with no event clock signal with events
IDT82V32021 EBU WAN PLL
Functional Des cription 20 April 24, 2015
3.5.2 FREQUENCY MONITORING
Frequency is monitored by comparing the input clock with a refer-
ence clock. The reference clock can be derived from the master clock or
the output of T0 DPLL, as determined by the FREQ_MON_CLK bit.
A frequency hard alarm threshold is set for frequency monitoring. If
the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised
when the frequency of the input clock with respect to the reference clock
is above the threshold; the alarm is cleared when the frequency is below
the threshold.
The frequency hard alarm threshold can be calculated as follows:
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_
THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0]
If the FREQ_MON_HARD_EN bit is ‘1’, the frequency hard alarm
status of the input clock is indicated by the INn_CMOS_FRE-
Q_HARD_ALARM bit (n = 1 or 2). When the FREQ_MON_HARD_EN
bit is ‘0’, no frequency hard alarm is raised even if the input clock is
above the frequency hard alarm threshold.
The input clock with a frequency hard alarm is disqualified for clock
selection for T0 DPLL.
In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges
with respect to the reference clock are monitored. If any edge drifts out-
side ±5%, the input clock is disqualified for clock selection for T0 DPLL.
The input clock is qualified if any edge drifts inside ±5%. This function is
supported only when the IN_NOISE_WINDOW bit is ‘1’.
The frequency of each input clock with respect to the reference clock
can be read by doing the following step by step:
1. Select an input clock by setting the IN_FREQ_READ_CH[3:0]
bits;
2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate
as follows:
Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] X FRE-
Q_MON_FACTOR[3:0]
Note that the value set by the FREQ_MON_FACTOR[3:0] bits
depends on the application.
Table 5: Related Bit / Register in Chapter 3.5
Bit Register Address (Hex)
BUCKET_SIZE_n_DATA[7:0] (3 n 0) BUCKET_SIZE_0_CNFG ~ BUCKET_SIZE_3_CNFG 33, 37, 3B, 3F
UPPER_THRESHOLD_n_DATA[7:0] (3 n 0) UPPER_THRESHOLD_0_CNFG ~ UPPER_THRESHOLD_3_CNFG 31, 35, 39, 3D
LOWER_THRESHOLD_n_DATA[7:0] (3 n 0) LOWER_THRESHOLD_0_CNFG ~ LOWER_THRESHOLD_3_CNFG 32, 36, 3A, 3E
DECAY_RATE_n_DATA[1:0] (3 n 0) DECAY_RATE_0_CNFG ~ DECAY_RATE_3_CNFG 34, 38, 3C, 40
BUCKET_SEL[1:0] IN1_CMOS_CNFG, IN2_CMOS_CNFG 16, 17
INn_CMOS_NO_ACTIVITY_ALARM (n = 1 or 2) IN1_IN2_CMOS_STS 44
INn_CMOS_FREQ_HARD_ALARM (n = 1 or 2)
FREQ_MON_CLK MON_SW_PBO_CNFG 0B
FREQ_MON_HARD_EN
ALL_FREQ_HARD_THRESHOLD[3:0] ALL_FREQ_MON_THRESHOLD_CNFG 2F
FREQ_MON_FACTOR[3:0] FREQ_MON_FACTOR_CNFG 2E
IN_NOISE_WINDOW PHASE_MON_PBO_CNFG 78
IN_FREQ_READ_CH[3:0] IN_FREQ_READ_CH_CNFG 41
IN_FREQ_VALUE[7:0] IN_FREQ_READ_STS 42
IDT82V32021 EBU WAN PLL
Functional Des cription 21 April 24, 2015
3.6 DPLL INPUT CLOCK SELECTION
The EXT_SW bit and the T0_INPUT_SEL[3:0] bits determine the
input clock selection, as shown in Table 6:
External Fast selection is done between IN1_CMOS and IN2_C-
MOS.
Forced selection is done by setting the related registers.
Automatic selection is done based on the results of input clocks qual-
ity monitoring and the related registers configuration.
The selected input clock is attempted to be locked by T0 DPLL.
3.6.1 EXTERNAL FAST SELECTION
In External Fast selection, only IN1_CMOS and IN2_CMOS are
available for selection. Refer to Figure 5. The results of input clocks
quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring)
do not affect input clock selection.
The T0 input clock selection is determined by the FF_SRCSW pin
after reset (this pin determines the default value of the EXT_SW bit
during reset, refer to Chapter 2 Pin Description), the IN1_C-
MOS_SEL_PRIORITY[3:0] bits and the IN2_CMOS_SEL_PRIOR-
ITY[3:0] bits, as shown in Figure 5 and Table 7:
Figure 5. External Fast Selection
Table 6: Input Clock Selection
Control Bits Input Clock Selection
EXT_SW T0_INPUT_SEL[3:0]
1 don’t-care External Fast selection
0other than 0000 Forced selection
0000 Automatic selection
FF_SRCSW pin
IN1_CMOS
IN2_CMOS
IN1_CMOS_SEL_PRIORITY[3:0] bits
IN2_CMOS_SEL_PRIORITY[3:0] bits
attempted to be
locked in T0 DPL L
Table 7: External Fast Selection
Control Pin & Bits the Selected Input Clock
FF_SRCSW (after reset) IN1_CMOS_SEL_PRIORITY[3:0] IN2_CMOS_SEL_PRIORITY[3:0]
high other than 0000 don’t-care IN1_CMOS
low don’t-care other than 0000 IN2_CMOS
IDT82V32021 EBU WAN PLL
Functional Des cription 22 April 24, 2015
3.6.2 F OR CED SEL ECT ION
In Forced selection, the selected input clock is set by the T0_IN-
PUT_SEL[3:0] bits. The results of input clocks quality monitoring (refer
to Chapter 3.5 Input Clock Quality Monitoring) do not affect the input
clock selection.
3.6.3 AUTOMATIC SELECTION
In Automatic selection, the input clock selection is determined by its
validity and priority. The validity depends on the results of input clock
quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring).
In the qualified input clocks, the one with the higher priority is selected.
The priority is configured by the corresponding INn_CMOS_SEL_PRI-
ORITY[3:0] bits (n = 1 or 2). If more than one qualified input clock is
available and has the same priority, the input clock with the smaller ‘n’ is
selected. See Table 8 for the ‘n’ assigned to the input clock.
Table 8: ‘n’ Assigned to the Input Clock
Input Clock ‘n’ Assigned to the Input Clock
IN1_CMOS 1
IN2_CMOS 3
Table 9: Related Bit / Register in Chapter 3.6
Bit Register Address (Hex)
EXT_SW MON_SW_PBO_CNFG 0B
T0_INPUT_SEL[3:0] T0_INPUT_SEL_CNFG 50
INn_CMOS_SEL_PRIORITY[3:0] (n = 1 or 2) IN1_IN2_CMOS_SEL_PRIORITY_CNFG 27
IDT82V32021 EBU WAN PLL
Functional Des cription 23 April 24, 2015
3.7 SELECTED INPUT CLOCK MONITORING
The quality of the selected input clock is always monitored (refer to
Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status
is always monitored.
3.7.1 DPLL LOCKING DETECTION
The following events is always monitored:
•Fast Loss;
•Coarse Phase Loss;
•Fine Phase Loss;
•Hard Limit Exceeding.
3.7.1.1 Fast Loss
A fast loss is triggered when the selected input clock misses 2 con-
secutive clock cycles. It is cleared once an active clock edge is detected.
The occurrence of the fast loss will result in T0 DPLL unlocked if the
FAST_LOS_SW bit is ‘1’.
3.7.1.2 Coarse Phase Loss
The T0 DPLL compares the selected input clock with the feedback
signal. If the phase-compared result exceeds the coarse phase limit, a
coarse phase loss is triggered. It is cleared once the phase-compared
result is within the coarse phase limit.
When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse
phase limit depends on the MULTI_PH_8K_4K_2K_EN bit, the
WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to
Table 10. When the selected input clock is of other frequencies but 2
kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN
bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 11.
The occurrence of the coarse phase loss will result in T0 DPLL
unlocked if the COARSE_PH_LOS_LIMT_EN bit is ‘1’.
3.7.1.3 Fine Phase Loss
The T0 DPLL compares the selected input clock with the feedback
signal. If the phase-compared result exceeds the fine phase limit pro-
grammed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is trig-
gered. It is cleared once the phase-compared result is within the fine
phase limit.
The occurrence of the fine phase loss will result in T0 DPLL unlocked
if the FINE_PH_LOS_LIMT_EN bit is ‘1’.
3.7.1.4 Hard Limit Exceeding
Two limits are available for this monitoring. They are DPLL soft limit
and DPLL hard limit. When the frequency of the DPLL output with
respect to the master clock exceeds the DPLL soft / hard limit, a DPLL
soft / hard alarm will be raised; the alarm is cleared once the frequency
is within the corresponding limit. The occurrence of the DPLL soft alarm
does not affect the T0 DPLL locking status. The DPLL soft alarm is indi-
cated by the corresponding T0_DPLL_SOFT_FREQ_ALARM bit. The
occurrence of the DPLL hard alarm will result in T0 DPLL unlocked if the
FREQ_LIMT_PH_LOS bit is ‘1’.
The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits
and can be calculated as follows:
DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724
The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0]
bits and can be calculated as follows:
DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014
3.7.2 LOCKING STATUS
The DPLL locking status depends on the locking monitoring results.
The DPLL is in locked state if none of the following events is triggered
during 2 seconds; otherwise, the DPLL is unlocked.
•Fast Loss (the FAST_LOS_SW bit is ‘1’);
•Coarse Phase Loss (the COARSE_PH_LOS_LIMT_EN bit is
‘1’);
•Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);
•DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’).
If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the
FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is ‘0’, the
DPLL locking status will not be affected even if the corresponding event
is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2
seconds.
The DPLL locking status is indicated by the T0_DPLL_LOCK bit.
3.7.3 PHASE LOCK ALARM
A phase lock alarm will be raised when the selected input clock can
not be locked in T0 DPLL within a certain period. This period can be cal-
culated as follows:
Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0]
The phase lock alarm is indicated by the corresponding INn_C-
MOS_PH_LOCK_ALARM bit (n = 1 or 2).
Table 10: Coarse Phase Limit Programming (the selected input
clock of 2 kHz, 4 kHz or 8 kHz)
MULTI_PH_8K_4K
_2K_EN WIDE_EN Coarse Phase Limit
0 don’t-care ±1 UI
10±1 UI
1 set by the PH_LOS_COARSE_LIMT[3:0] bits
Table 11: Coarse Phase Limit Programming (the selected input
clock of other than 2 kHz, 4 kHz and 8 kHz)
WIDE_EN Coarse Phase Limit
0±1 UI
1 set by the PH_LOS_COARSE_LIMT[3:0] bits
IDT82V32021 EBU WAN PLL
Functional Des cription 24 April 24, 2015
The phase lock alarm can be cleared by the following two ways, as
selected by the PH_ALARM_TIMEOUT bit:
•Be cleared when a ‘1’ is written to the corresponding INn_C-
MOS_PH_LOCK_ALARM bit;
•Be cleared after the period (= TIME_OUT_VALUE[5:0] X MUL-
TI_FACTOR[1:0] in second) which starts from when the alarm is
raised.
The selected input clock with a phase lock alarm is disqualified for T0
DPLL locking.
Table 12: Related Bit / Register in Chapter 3.7
Bit Register Address (Hex)
FAST_LOS_SW PHASE_LOSS_FINE_LIMIT_CNFG 5BPH_LOS_FINE_LIMT[2:0]
FINE_PH_LOS_LIMT_EN
MULTI_PH_8K_4K_2K_EN
PHASE_LOSS_COARSE_LIMIT_CNFG 5A
WIDE_EN
PH_LOS_COARSE_LIMT[3:0]
COARSE_PH_LOS_LIMT_EN
T0_DPLL_SOFT_FREQ_ALARM OPERATING_STS 52
T0_DPLL_LOCK
DPLL_FREQ_SOFT_LIMT[6:0] DPLL_FREQ_SOFT_LIMIT_CNFG 65
FREQ_LIMT_PH_LOS
DPLL_FREQ_HARD_LIMT[15:0] DPLL_FREQ_HARD_LIMIT[15:8]_CNFG, DPLL_FRE-
Q_HARD_LIMIT[7:0]_CNFG 67, 66
TIME_OUT_VALUE[5:0] PHASE_ALARM_TIME_OUT_CNFG 08
MULTI_FACTOR[1:0]
INn_CMOS_PH_LOCK_ALARM (n = 1 or 2) IN1_IN2_CMOS_STS 44
PH_ALARM_TIMEOUT INPUT_MODE_CNFG 09
IDT82V32021 EBU WAN PLL
Functional Des cription 25 April 24, 2015
3.8 SELECTED INPUT CLOCK SWITCH
If the input clock is selected by External Fast selection or by Forced
selection, it can be switched by setting the related registers (refer to
Chapter 3.6.1 External Fast Selection & Chapter 3.6.2 Forced Selection)
any time. In this case, whether the input clock is qualified for DPLL lock-
ing does not affect the clock switch.
When the input clock is selected by Automatic selection, the input
clock switch depends on its validity and priority. If the current selected
input clock is disqualified, a new qualified input clock may be switched
to.
3.8.1 INPUT CLOCK VALIDITY
For the input clocks, the validity depends on the results of input clock
quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring).
When all of the following conditions are satisfied, the input clock is valid;
otherwise, it is invalid.
•No no-activity alarm (the INn_CMOS_NO_ACTIVITY_ALARM
bit is ‘0’);
•No frequency hard alarm (the INn_CMOS_FREQ_HARD_
ALARM bit is ‘0’);
•If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input
clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the
IN_NOISE_WINDOW bit is ‘0’, this condition is ignored.
•No phase lock alarm, i.e., the INn_CMOS_PH_LOCK_ALARM
bit is ‘0’;
•If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock
misses less than (<) 2 consecutive clock cycles; if the ULTR_-
FAST_SW bit is ‘0’, this condition is ignored.
The validities of the input clocks are indicated by the INn_CMOS 1 bit
(n = 1 or 2). When the input clock validity changes (from ‘valid’ to ‘invalid’
or from ‘invalid’ to ‘valid’), the INn_CMOS 2 bit will be set. If the INn_C-
MOS 3 bit is ‘1’, an interrupt will be generated.
When the T0 selected input clock has failed, i.e., the validity of the T0
selected input clock changes from ‘valid’ to ‘invalid’, the T0_-
MAIN_REF_FAILED 1 bit w ill be set. If the T0_MAIN_REF _FAILED 2 bit
is ‘1’, an interrupt will be generated. This interrupt can also be indicated
by hardware - the TDO pin, as determined by the LOS_FLAG_TO_TDO
bit. When the TDO pin is used to indicate this interrupt, it will be set high
when this interrupt is generated and will remain high until this interrupt is
cleared.
3.8.2 SELECTED INPUT CLOCK SWITCH
Revertive and Non-Revertive switches are supported, as selected by
the REVERTIVE_MODE bit.
The difference between Revertive and Non-Revertive switches is
that whether the selected input clock is switched when another qualified
input clock with a higher priority than the current selected input clock is
available for selection. In Non-Revertive switch, input clock switch is
minimized.
Conditions of the qualified input clocks available for T0 selection are
as the following:
•Valid, i.e., the INn_CMOS 1 bit is ‘1’;
•Priority enabled, i.e., the corresponding INn_CMOS_SEL _PRI-
ORITY[3:0] bits are not ‘0000’.
The input clock is disqualified if any of the above conditions is not
satisfied.
In summary, the selected input clock can be switched by:
•External Fast selection;
•Forced selection;
•Revertive switch;
•Non-Revertive switch.
3.8.2.1 Revertive Switch
In Revertive switch, the selected input clock is switched when
another qualified input clock with a higher priority than the current
selected input clock is available.
The selected input clock is switched if any of the following is satis-
fied: •The selected input clock is disqualified;
•Another qualified input clock with a higher priority than the
selected input clock is available.
A qualified input clock with the higher priority is selected by revertive
switch. If more than one qualified input clock is available and has the
same priority, the input clock with the smaller ‘n’ is selected. See Table 8
for the ‘n’ assigned to each input clock.
3.8.2.2 Non-Revertive Switch
In Non-Revertive switch, the T0 selected input clock is not switched
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the higher priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smaller ‘n’ is selected. See Table 8 for the ‘n’ assigned to
each input clock.
3.8.3 SELECTED / QUALIFIED INPUT CLOCKS INDICATION
The selected input clock is indicated by the CURRENTLY_SELECT-
ED_INPUT[3:0] bits.
The qualified input clocks with the two highest priorities are indicated
by the HIGHEST_PRIORITY_VALIDATED[3:0] bits and the SEC-
OND_HIGHEST_PRIORITY_VALIDATED[3:0] bits respectively. If more
than one input clock has the same priority, the input clock with the
smaller ‘n’ is indicated by the HIGHEST_PRIORITY_VALIDATED[3:0]
bits. See Table 8 for the ‘n’ assigned to the input clock.
When the device is configured in Automatic selection and Revertive
switch is enabled, the input clock indicated by the CURRENTLY_SE-
LECTED_INPUT[3:0] bits is the same as the one indicated by the HIGH-
EST_PRIORITY_VALIDATED[3:0] bits; otherwise, they are not the
same.
IDT82V32021 EBU WAN PLL
Functional Des cription 26 April 24, 2015
Table 13: Related Bit / Register in Chapter 3.8
Bit Register Address (Hex)
INn_CMOS 1 (n = 1 or 2) INPUT_VALID1_STS 4A
INn_CMOS 2 (n = 1 or 2) INTERRUPTS1_STS, INTERRUPTS2_STS 0D, 0E
INn_CMOS 3 (n = 1 or 2) INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG 10, 11
INn_CMOS_NO_ACTIVITY_ALARM (n = 1 or 2) IN1_IN2_CMOS_STS 44INn_CMOS_FREQ_HARD_ALARM (n = 1 or 2)
INn_CMOS_PH_LOCK_ALARM (n = 1 or 2)
IN_NOISE_WINDOW PHASE_MON_PBO_CNFG 78
ULTR_FAST_SW MON_SW_PBO_CNFG 0B
LOS_FLAG_TO_TDO
T0_MAIN_REF_FAILED 1INTERRUPTS2_STS 0E
T0_MAIN_REF_FAILED 2INTERRUPTS2_ENABLE_CNFG 11
REVERTIVE_MODE INPUT_MODE_CNFG 09
INn_CMOS_SEL_PRIORITY[3:0] (n = 1 or 2) IN1_IN2_CMOS_SEL_PRIORITY_CNFG 27
CURRENTLY_SELECTED_INPUT[3:0] PRIORITY_TABLE1_STS 4E
HIGHEST_PRIORITY_VALIDATED[3:0]
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] PRIORITY_TABLE2_STS 4F
IDT82V32021 EBU WAN PLL
Functional Des cription 27 April 24, 2015
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL
OPERATING MODE
T0 DPLL supports three primary operating modes: Free-Run, Locked
and Holdover, and three secondary, temporary operating modes: Pre-
Locked, Pre-Locked2 and Lost-Phase. The operating mode of T0 DPLL
can be switched automatically or by force, as controlled by the T0_OP-
ERATING_MODE[2:0] bits.
When the operating mode is switched by force, the operating mode
switch is under external control and t he status of the selected input clock
takes no effect to the operating mode selection. The forced operating
mode switch is applicable for special cases, such as testing.
When the operating mode is switched automatically, the internal
state machine for T0 automatically determine the operating mode.
The T0 DPLL operating mode is controlled by the T0_OPERATING_-
MODE[2:0] bits, as shown in Table 14:
When the operating mode is switched automatically, the operation of
the internal state machine is shown in Figure 6.
Whether the operating mode is under external control or is switched
automatically, the current operating mode is always indicated by the
T0_DPLL_OPERATING_MODE[2:0] bits. When the operating mode
switches, the T0_OPERATING_MODE 1 bit will be set. If the T0_OPER-
ATING_MODE 2 bit is ‘1’, an interrupt will be generated.
Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode
Table 14: T0 DPLL Operating Mode Control
T0_OPERATING_MODE[2:0] T0 DPLL Operating Mode
000 Automatic
001 Forced - Free-Run
010 Forced - Ho ldov er
100 Forced - Locked
101 Forced - Pre-Locked2
110 Forced - Pre-Locked
111 Forced - Lost-Phase
Free-Run mode
1
Pre-Locked
mode
2
3
4
Locked
mode
5
Lost-Phase
mode
Holdover
mode
78
Pre-Locked2
mode
13
14
15
6
12 11
9
10
IDT82V32021 EBU WAN PLL
Functional Des cription 28 April 24, 2015
Notes to Figure 6:
1. Reset.
2. An input clock is selected.
3. The T0 selected input clock is disqualified AND No qualified input clock is available.
4. The T0 selected input clock is switched to another one.
5. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
6. The T0 selected input clock is disqualified AND No qualified input clock is available.
7. The T0 selected input clock is unlocked (the T0_DPLL_LOCK bit is ‘0’).
8. The T0 selected input clock is locked again (the T0_DPLL_LOCK bit is ‘1’).
9. The T0 selected input clock is switched to another one.
10. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
11. The T0 selected input clock is disqualified AND No qualified input clock is available.
12. The T0 selected input clock is switched to another one.
13. The T0 selected input clock is disqualified AND No qualified input clock is available.
14. An input clock is selected.
15. The T0 selected input clock is switched to another one.
The causes of Item 4, 9, 12, 15 - ‘the T0 selected input clock is
switched to another one’ - are: (The T0 selected input clock is disquali-
fied AND Another input clock is switched to) OR (In Revertive switch, a
qualified input clock with a higher priority is switched to) OR (The T0
selected input clock is switched to another one by External Fast selec-
tion or Forced selection).
Refer to Chapter 3.8.2 Selected Input Clock Switch for details about
T0 input clock qualification.
Table 15: Related Bit / Register in Chapter 3.9
Bit Register Address (Hex)
T0_OPERATING_MODE[2:0] T0_OPERATING_MODE_CNFG 53
T0_DPLL_OPERATING_MODE[2:0] OPERATING_STS 52
T0_DPLL_LOCK
T0_OPERATING_MODE 1INTERRUPTS2_STS 0E
T0_OPERATING_MODE 2INTERRUPTS2_ENABLE_CNFG 11
IDT82V32021 EBU WAN PLL
Functional Des cription 29 April 24, 2015
3.10 DPLL OPERATING MODE
The T0 DPLL gives a stable performance in different applications
without being affected by operating conditions or silicon process varia-
tions. It integrates a PFD (Phase & Frequency Detector), a LPF (Low
Pass Filter) and a DCO (Digital Controlled Oscillator), which forms a
closed loop. If no input clock is selected, the loop is not closed, and the
PFD and LPF do not function.
The PFD detects the phase error, including the fast loss, coarse
phase loss and fine phase loss (refer to Chapter3.7.1.1 Fast Loss to
Chapter 3.7.1.3 Fine Phase Loss). The averaged phase error of the T0
DPLL feedback with respect to the selected input clock is indicated by
the CURRENT_PH_DATA[15:0] bits. It can be calculated as follows:
Averaged Phase Error (ns) = CURRENT_PH_DATA[15:0] X 0.61
The LPF filters jitters. Its 3 dB bandwidth and damping factor are pro-
grammable. A range of bandwidths and damping factors can be set to
meet different application requirements. Generally, the lower the damp-
ing factor is, the longer the locking time is and the more the gain is.
The DCO controls the DPLL output. The frequency of the DPLL out-
put is always multiplied on the basis of the master clock. The phase and
frequency offset of the DPLL output may be locked to those of the
selected input clock. The current frequency offset with respect to the
master clock is indicated by the CURRENT_DPLL_FREQ[23:0] bits, and
can be calculated as follows:
Current Frequency Offset (ppm) = CURRENT_DPLL_FREQ[23:0] X
0.000011
3.10.1 SIX OPERATING MODES
The T0 DPLL loop is closed except in Free-Run mode and Holdover
mode.
For a closed loop, different bandwidths and damping factors can be
used depending on DPLL locking stages: starting, acquisition and
locked.
In the first two seconds when the T0 DPLL attempts to lock to the
selected input clock, the starting bandwidth and damping factor are
used. They are set by the T0_DPLL_START_BW[4:0] bits and the
T0_DPLL_START_DAMPING[2:0] bits respectively.
During the acquisition, the acquisition bandwidth and damping factor
are used. They are set by the T0_DPLL_ACQ_BW[4:0] bits and the
T0_DPLL_ACQ_DAMPING[2:0] bits respectively.
When the T0 selected input clock is locked, the locked bandwidth
and damping factor are used. They are set by the T0_D-
PLL_LOCKED_BW[4:0] bits and the T0_DPLL_LOCKED_DAMP-
ING[2:0] bits respectively.
The corresponding bandwidth and damping factor are used when the
T0 DPLL operates in different DPLL locking stages: starting, acquisition
and locked, as controlled by the device automatically.
Only the locked bandwidth and damping factor can be used regard-
less of the T0 DPLL locking stage, as controlled by the AUTO_BW_SEL
bit.
3.10.1.1 Free-Run Mode
In Free-Run mode, the T0 DPLL output refers to the master clock
and is not affected by any input clock. The accuracy of the T0 DPLL out-
put is equal to that of the master clock.
3.10.1.2 Pre-Locked Mode
In Pre-Locked mode, the T0 DPLL output attempts to track the
selected input clock.
The Pre-Locked mode is a secondary, temporary mode.
3.10.1.3 Locked Mode
In Locked mode, the T0 selected input clock is locked. The phase
and frequency offset of the T0 DPLL output track those of the T0
selected input clock.
In this mode, if the T0 selected input clock is in fast loss status and
the FAST_LOS_SW bit is ‘1’, the T0 DPLL is unlocked (refer to
Chapter 3.7.1.1 Fast Loss) and will enter Lost-Phase mode when the
operating mode is switched automatically; if the T0 selected input clock
is in fast loss status and the FAST_LOS_SW bit is ‘0’, the T0 DPLL lock-
ing status is not affected and the T0 DPLL will enter Temp-Holdover
mode automatically.
3.10.1.3.1 Temp-Holdover Mode
The T0 DPLL will automatically enter Temp-Holdover mode with a
selected input clock switch or no qualified input clock available when the
operating mode switch is under external control.
In Temp-Holdover mode, the T0 DPLL has temporarily lost the
selected input clock. The T0 DPLL operation in Temp-Holdover mode
and that in Holdover mode are alike (refer to Chapter3.10.1.5 Holdover
Mode) except the frequency offset acquiring methods. See
Chapter 3.10.1.5 Holdover Mode for details about the methods. The
method is selected by the TEMP_HOLDOVER_MODE[1:0] bits, as
shown in Table 16:
The device automatically controls the T0 DPLL to exit from Temp-
Holdover mode.
3.10.1.4 Lost-Phase Mode
In Lost-Phase mode, the T0 DPLL output attempts to track the
selected input clock.
The Lost-Phase mode is a secondary, temporary mode.
3.10.1.5 Holdover Mode
In Holdover mode, the T0 DPLL resorts to the stored frequency data
acquired in Locked mode to control its output. The T0 DPLL output is not
Table 16: Frequency Offset Control in Temp-Holdover Mode
TEMP_HOLDOVER_MODE[1:0] Frequency Offset Acquiring Method
00 the same as that used in Holdover mode
01 Automatic Instantaneous
10 Automatic Fast Averaged
11 Automatic Slow Averaged
IDT82V32021 EBU WAN PLL
Functional Des cription 30 April 24, 2015
phase locked to any input clock. The frequency offset acquiring method
is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the
FAST_AVG bit, as shown in Table 17:
3.10.1.5.1 Automatic Instantaneous
By this method, the T0 DPLL freezes at the operating frequency
when it enters Holdover mode. The accuracy is 4.4X10-8 ppm.
3.10.1.5.2 Automatic Slow Averaged
By this method, an internal IIR (Infinite Impulse Response) filter is
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 110 minutes. The accuracy is
1.1X10-5 ppm.
3.10.1.5.3 Automatic Fast Averaged
By this method, an internal IIR (Infinite Impulse Response) filter is
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 8 minutes. The accuracy is
1.1X10-5 ppm.
3.10.1.5.4 Manual
By this method, the frequency offset is set by the T0_HOLDOVER_-
FREQ[23:0] bits. The accuracy is 1.1X10-5 ppm.
The frequency offset of the T0 DPLL output is indicated by the CUR-
RENT_DPLL_FREQ[23:0] bits.
The device provides a reference for the value to be written to the
T0_HOLDOVER_FREQ[23:0] bits. The value to be written can refer to
the value read from the CURRENT_DPLL_FREQ[23:0] bits or the
T0_HOLDOVER_FREQ[23:0] bits (refer to Chapter 3.10.1.5.5 Holdover
Frequency Offset Read); or then be processed by external software fil-
tering.
3.10.1.5.5 Holdover Frequency Offset Read
The offset value, which is acquired by Automatic Slow Averaged,
Automatic Fast Averaged and is set by related register bits, can be read
from the T0_HOLDOVER_FREQ[23:0] bits by setting the READ_AVG
bit and the FAST_AVG bit, as shown in Table 18.
The frequency offset in ppm is calculated as follows:
Holdover Frequency Offset (ppm) = T0_HOLDOVER_FREQ[23:0] X
0.000011
3.10.1.6 Pre-Locked2 Mode
In Pre-Locked2 mode, the T0 DPLL output attempts to track the
selected input clock.
The Pre-Locked2 mode is a secondary, temporary mode.
Table 17: Frequency Offset Control in Holdover Mode
MAN_HOLDOVER AUTO_AVG FAST_AVG Frequency Offset Acquiring Method
00 don’t-care Automatic Instantaneous
10 Automatic Slow Averaged
1 Automatic Fast Averaged
1 don’t-care Manual
Table 18: Holdover Frequency Offset Read
READ_AVG FAST_AVG Offset Value Read from
T0_HOLDOVER_FREQ[23:0]
0 don’t-care The value is equal to the one written to.
10The value is acquired by Autom atic Slow Averaged
method, not equal to the one written to.
1The value is acquired by Automatic Fast Averaged
method, not equal to the one written to.
IDT82V32021 EBU WAN PLL
Functional Des cription 31 April 24, 2015
Table 19: Related Bit / Register in Chapter 3.10
Bit Register Address (Hex)
CURRENT_PH_DATA[15:0] CURRENT_DPLL_PHASE[15:8]_STS, CURRENT_DPLL_PHASE[7:0]_STS 69, 68
CURRENT_DPLL_FREQ[23:0] CURRENT_DPLL_FREQ[23:16]_STS, CURRENT_DPLL_FREQ[1 5:8]_STS, CURRENT_DPLL_-
FREQ[7:0]_STS 64, 63, 62
T0_DPLL_START_BW[4:0] T0_DPLL_START_BW_DAMPING_CNFG 56
T0_DPLL_START_DAMPING[2:0]
T0_DPLL_ACQ_BW[4:0] T0_DPLL_ACQ_BW_DAMPING_CNFG 57
T0_DPLL_ACQ_DAMPING[2:0]
T0_DPLL_LOCKED_BW[4:0] T0_DPLL_LOCKED_BW_DAMPING_CNFG 58
T0_DPLL_LOCKED_DAMPING[2:0]
AUTO_BW_SEL T0_BW_OVERSHOOT_CNFG 59
FAST_LOS_SW PHASE_LOSS_FINE_LIMIT_CNFG 5B
TEMP_HOLDOVER_MODE[1:0]
T0_HOLDOVER_MODE_CNFG 5C
MAN_HOLDOVER
AUTO_AVG
FAST_AVG
READ_AVG
T0_HOLDOVER_FREQ[23:0] T0_HOLDOVER_FREQ[23:16]_CNFG, T0_HOLDOVER_FREQ[15:8]_CNFG, T0_HOLDOVER_-
FREQ[7:0]_CNFG 5F, 5E, 5D
IDT82V32021 EBU WAN PLL
Functional Des cription 32 April 24, 2015
3.11 DPLL OUTPUT
The DPLL output is locked to the selected input clock. According to
the phase-compared result of the feedback and the selected input clock,
and the DPLL output frequency offset, the PFD output is limited and the
DPLL output is frequency offset limited.
3.11.1 PFD OUTPUT LIMIT
The PFD output is limited to be within ±1 UI or within the coarse
phase limit (refer to Chapter 3.7.1.2 Coarse Phase Loss), as determined
by the MULTI_PH_APP bit.
3.11 .2 FREQUENCY OFFSET LIMIT
The DPLL output is limited to be within the DPLL hard limit (refer to
Chapter 3.7.1.4 Hard Limit Exceeding).
The integral path value can be frozen when the DPLL hard limit is
reached. This function, enabled by the T0_LIMT bit, will minimize the
subsequent overshoot when T0 DPLL is pulling in.
3.11.3 PBO
When a PBO event is triggered, the phase of fset of the selected input
clock with respect to the T0 DPLL output is measured. The device then
automatically accounts for the measured phase offset and compensates
an appropriate phase offset into the DPLL output so that the phase tran-
sients on the T0 DPLL output are minimized.
A PBO event is triggered if any one of the following conditions
occurs:
•T0 selected input clock switches (the PBO_EN bit is ‘1’);
•T0 DPLL exits from Holdover mode or Free-Run mode (the
PBO_EN bit is ‘1’);
•Phase-time changes on the T0 selected input clock are greater
than a programmable limit over an interval of less than 0.1 sec-
onds (the PH_MON_PBO_EN bit is ‘1’).
For the first two conditions, the phase transients on the T0 DPLL out-
put are minimized to be no more than 0.61 ns with PBO. The PBO can
also be frozen at the current phase offset by setting the PBO_FREZ bit.
When the PBO is frozen, the device will ignore any further PBO events
triggered by the above two conditions, and maintain the current phase
offset. When the PBO is disabled, there may be a phase shift on the T0
DPLL output and the T0 DPLL output tracks back to 0 degree phase off-
set with respect to the T0 selected input clock.
The last condition is specially for stratum 2 and 3E clocks. The PBO
requirement specified in the Telcordia GR-1244-CORE is: ‘Input phase-
time changes of 3.5 µs or greater over an interval of less than 0.1 sec-
onds or less shall be built-out by stratum 2 and 3E clocks to reduce the
resulting clock phase-time change to less than 50 ns. Phase-time
changes of 1.0 µs or less over an interval of 0.1 seconds shall not be
built-out.’ Based on this requirement, phase-time changes of more than
1.0 µs but less than 3.5 µs that occur over an interval of less than 0.1
seconds may or may not be built-out.
An integrated Phase Transient Monitor can be enabled by the
PH_MON_EN bit to monitor the phase-time changes on the T0 selected
input clock. When the phase-time changes are greater than a limit over
an interval of less than 0.1 seconds, a PBO event is triggered and the
phase transients on the DPLL output are absorbed. The limit is pro-
grammed by the PH_TR_MON_LIMT[3:0] bits, and can be calculated as
follows:Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156
The phase offset induced by PBO will never result in a coarse or fine
phase loss.
3.11.4 FOUR PATHS OF T0 DPLL OUTPUT
The T0 DPLL output is phase aligned with the T0 selected input clock
every 125 µs period. T0 DPLL has four output paths as follows:
•77.76 MHz path - outputs a 77.76 MHz clock;
•16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by
the IN_SONET_SDH bit;
•GSM/OBSAI/16E1/16T1 path - outputs a GSM, OBSAI, 16E1 or
16T1 clock, as selected by the T0_GSM_OBSAI_16E1_16T1_
SEL[1:0] bits;
•12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock,
as selected by the T0_12E1_24T1_E3_T3_SEL[1:0] bits.
T0 selected input clock is compared with a T0 DPLL output for DPLL
locking. The output can only be derived from the 77.76 MHz path or the
16E1/16T1 path. The output path is automatically selected and the out-
put is automatically divided to get the same frequency as the T0
selected input clock.
T0 DPLL outputs are provided for T0 APLL or device output process.
IDT82V32021 EBU WAN PLL
Functional Des cription 33 April 24, 2015
Table 20: Related Bit / Register in Chapter 3.11
Bit Register Address (Hex)
MULTI_PH_APP PHASE_LOSS_COARSE_LIMIT_CNFG 5A
T0_LIMT T0_BW_OVERSHOOT_CNFG 59
PBO_EN MON_SW_PBO_CNFG 0B
PBO_FREZ
PH_MON_PBO_EN PHASE_MON_PBO_CNFG 78PH_MON_EN
PH_TR_MON_LIMT[3:0]
PH_OFFSET_EN PHASE_OFFSET[9:8]_CNFG 7B
IN_SONET_SDH INPUT_MODE_CNFG 09
T0_GSM_OBSAI_16E1_16T1_SEL[1:0] T0_DPLL_APLL_PATH_CNFG 55
T0_12E1_24T1_E3_T3_SEL[1:0]
IDT82V32021 EBU WAN PLL
Functional Des cription 34 April 24, 2015
3.12 T0 APLL
A T0 APLL is provided for a better jitter and wander performance of
the device output clock.
The bandwidth of the T0 APLL is set by the T0_APLL_BW[1:0] bits.
The lower the bandwidth is, the better the jitter and wander performance
of the T0 APLL output are.
The input of the T0 APLL can be derived from T0 DPLL output, as
selected by the T0_APLL_PATH[3:0] bits.
Both the APLL and DPLL outputs are provided for selection for the
device output.
3.13 OUTPUT CLOCK & FRAME SYNC SIGNALS
The device supports 1 output clock and 1 frame sync output signal
altogether.
3.13.1 OUTPUT CLOCK
The device provides 1 output clock.
The output on OUT1 is variable, depending on the signals derived
from the T0 DPLL and T0 APLL outputs, and the corresponding OUT-
1_PATH_SEL[3:0] bits. The derived signal can be from the T0 DPLL and
T0 APLL outputs, as selected by the corresponding OUT1_PATH_-
SEL[3:0] bits. If the signal is derived from the T0 DPLL output, please
refer to Table 22 for the output frequency. If the signal is derived from the
T0 APLL output, please refer to Table 23 for the output frequency.
The output on OUT1 can be inverted, as determined by the corre-
sponding OUT1_INV bit.
The output clock derived from T0 selected input clock is aligned with
the T0 selected input clock every 125 µs period.
Table 21: Related Bit / Register in Chapter 3.12
Bit Register Address (Hex)
T0_APLL_BW[1:0] T0_APLL_BW_CNFG 6A
T0_APLL_PATH[3:0] T0_DPLL_APLL_PATH_CNFG 55
Table 22: Output on OUT1 if Derived from T0 DPLL Output
OUT1_DIVIDER[3:0]
(Output Divider) output on OUT1 if derived from T0 DPLL output 1
77.76 MHz 12E1 16E1 24T1 16T1 E3 T3 GSM (26 MHz) OBSAI (30.72 MHz)
0000 Output is disabled (output low).
0001
0010 12E1 16E1 24T1 16T1 E3 T3
0011 6E1 8E1 12T1 8T1 13 MHz 15.36 MHz
0100 3E1 4E1 6T1 4T1
0101 2E1 4T1
0110 2E1 3T1 2T1
0111 E1 2T1
1000 E1 T1
1001 T1
1010 64 kHz
1011 8 kHz
1100 2 kHz
1101 400 Hz
1110 1Hz
1111 Output is disabled (output high).
Note:
1. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved.
IDT82V32021 EBU WAN PLL
Functional Des cription 35 April 24, 2015
Table 23: Output on OUT1 if Derived from T0 APLL
OUT1_DIVIDER[3:0]
(Output Divider) output on OUT1 if derived from T0 APLL output 1
77.76 MHz X 4 12E1 X 4 16E1 X 4 24T1 X 4 16T1 X 4 E3 T3 GSM (26 MHz X 2) OBSAI (30.72 MHz X 10)
0000 Output is disabled (output low).
0001
0010 48E1 64E1 96T1 64T1 E3 T3 52 MHz
0011 155.52 MHz 24E1 32E1 48T1 32T1 26 MHz 153.6 MHz
0100 77.76 MHz 12E1 16E1 24T1 16T1 13 MHz 76.8 MHz
0101 51.84 MHz 8E1 16T1
0110 38.88 MHz 6E1 8E1 12T1 8T1 38.4 MHz
0111 25.92 MHz 4E1 8T1
1000 19.44 MHz 3E1 4E1 6T1 4T1
1001 2E1 4T1 61.44 MHz 2
1010 2E1 3T1 2T1 30.72 MHz 2
1011 6.48 MHz E1 2T1 15.36 MHz 2
1100 E1 T1 7.68 MHz 2
1101 T1 3.84 MHz 2
1110
1111 Output is disabled (output high).
Note:
1. In the APLL, the selec ted T0 DPLL out put may be multiplied. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.36 8 MHz, T3 = 44.7 36 MHz. The blank cell means the conf iguration is re served.
2. The 61.44 MHz, 30.72 MHz, 15.36 MHz, 7.68 MHz and 3.84 MHz outputs are only derived from T0 APLL.
IDT82V32021 EBU WAN PLL
Functional Des cription 36 April 24, 2015
3.13.2 FRAME SYNC OUTPUT SIGNAL
An 8 kHz frame sync signal is output on the FRSYNC_8K pin if
enabled by the 8K_EN bit. It is a CMOS output.
The frame sync signal is derived from the T0 APLL output and are
aligned with the output clock. It can be synchronized to one of the two
frame sync input signals.
One of the two frame sync input signals is selected, as determined
by the SYNC_BYPASS bit and the T0 selected input clock, as shown in
Table 24:
If the selected frame sync input signal with respect to the T0 selected
input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an
external sync alarm will be raised and the selected frame sync input sig-
nal is disabled to synchronize the frame sync output signal. The external
sync alarm is cleared once the selected frame sync input signal with
respect to the T0 selected input clock is within the limit. If it is within the
limit, whether the selected frame sync input signal is enabled to synchro-
nize the frame sync output signal is determined by the SYNC_BYPASS
bit, the AUTO_EXT_SYNC_EN bit and the EXT_SYNC_EN bit. Refer to
Table 25 for details.
When the selected frame sync input signal is enabled to synchronize
the frame sync output signal, it should be adjusted to align itself with the
T0 selected input clock. Nominally, the falling edge of the selected frame
sync input signal is aligned with the rising edge of the T0 selected input
clock. The selected frame sync input signal may be 0.5 UI early/late or 1
UI late due to the circuit and board wiring delays. Setting th e sampling of
the selected frame sync input signal by the SYNC_PHn[1:0] bits (n = 1
or 2 corresponding to EX_SYNC1 or EX_SYNC2 respectively) will com-
pensate this early/late. Refer to Figure 7 to Figure 10.
The EX_SYNC_ALARM_MON bit indicates whether the selected
frame sync input signal is in external sync alarm status. The external
sync alarm is indicated by the EX_SYNC_ALARM 1 bit. If the EX_SYN-
C_ALARM 2 bit is ‘1’, the occurrence of the external sync alarm will trig-
ger an interrupt.
The 8 kHz frame sync output signal can be inverted by setting the
8K_INV bit. The frame sync output can be 50:50 duty cycle or pulsed, as
determined by the 8K_PUL bit. When they are pulsed, the pulse width is
defined by the period of OUT1; and they are pulsed on the position of
the falling or rising edge of the standard 50:50 duty cycle, as selected by
the 8K_PUL_POSITION bit.
Figure 7. On Target Frame Sync Input Signal Timing Figure 8. 0.5 UI Early Frame Sync Input Signal Timing
Table 24: Frame Sync Input Signal Selection
SYNC_BYPASS T0 Selected Input Clock Selected Frame Sync Input
Signal
0 don’t-care EX_SYNC1
1IN1_CMOS EX_SYNC1
IN2_CMOS EX_SYNC2
none none
Table 25: Synchronization Control
SYNC_BYPASS AUTO_EXT_SYNC_EN EXT_SYNC_EN Synchronization
0don’t-care 0 Disabled
01 Enabled
1 1 Disabled
1 don’t-care Enabled
IDT82V32021 EBU WAN PLL
Functional Des cription 37 April 24, 2015
Figure 9. 0.5 UI Late Frame Sync Input Signal Timing Figure 10. 1 UI Late Frame Sync Input Signal Timing
Table 26: Related Bit / Register in Chapter 3.13
Bit Register Address (Hex)
OUT1_PATH_SEL[3:0] OUT1_FREQ_CNFG 6D
OUT1_DIVIDER[3:0]
IN_SONET_SDH INPUT_MODE_CNFG 09AUTO_EXT_SYNC_EN
EXT_SYNC_EN
OUT1_INV OUT1_INV_CNFG 73
8K_EN
FR_SYNC_CNFG 74
8K_INV
8K_PUL
8K_PUL_POSITION
SYNC_BYPASS SYNC_MONITOR_CNFG 7C
SYNC_MON_LIMT[2:0]
SYNC_PHn[1:0] (n = 1 or 2) SYNC_PHASE_CNFG 7D
EX_SYNC_ALARM_MON OPERATING_STS 52
EX_SYNC_ALARM 1INTERRUPTS3_STS 0F
EX_SYNC_ALARM 2INTERRUPTS3_ENABLE_CNFG 12
IDT82V32021 EBU WAN PLL
Functional Des cription 38 April 24, 2015
3.14 INTERRUPT SUMMARY
The interrupt sources of the device are as follows:
•T0 Input clocks validity change
•T0 selected input clock fail
•T0 DPLL operating mode switch
•External sync alarm
All of the above interrupt events are indicated by the corresponding
interrupt status bit. If the corresponding interrupt enable bit is set, any of
the interrupts can be reported by the INT_REQ pin. The output charac-
teristics on the INT_REQ pin are determined by the HZ_EN bit and the
INT_POL bit.
Interrupt events are cleared by writing a ‘1’ to the corresponding
interrupt status bit. The INT_REQ pin will be inactive only when all the
pending enabled interrupts are cleared.
In addition, the interrupt of T0 selected input clock fail can be
reported by the TDO pin, as determined by the LOS_FLAG_TO_TDO
bit.
3.15 T0 SUMMARY
The main features supported by the T0 path are as follows:
•Phase lock alarm;
•Forced or Automatic input clock selection/switch;
•3 primary and 3 secondary, temporary DPLL operating modes,
switched automatically or under external control;
•Automatic switch between starting, acquisition and locked band-
widths/damping factors;
•Programmable DPLL bandwidths from 1.2 Hz to 560 Hz in 8
steps;
•Programmable damping factors: 1.2, 2.5, 5, 10 and 20;
•Fast loss, coarse phase loss, fine phase loss and hard limit
exceeding monitoring;
•Output phase and frequency offset limited;
•Automatic Instantaneous, Automatic Slow Averaged, Automatic
Fast Averaged or Manual holdover frequency offset acquiring;
•PBO to minimize output phase transients;
•Programmable output phase offset;
•Low jitter multiple clock outputs with programmable polarity;
•Low jitter 8 kHz frame sync signal output with programmable
pulse width and polarity;
Table 27: Related Bit / Register in Chapter 3.14
Bit Register Address (Hex)
HZ_EN INTERRUPT_CNFG 0C
INT_POL
LOS_FLAG_TO_TDO MON_SW_PBO_CNFG 0B
IDT82V32021 EBU WAN PLL
Functional Des cription 39 April 24, 2015
3.16 LINE CARD APPLICATION
Figure 11. Line Card Application
Master Clock
Board
Slave Clock
Board
IDT82V32021
Backplane
SDH/SONET
System
Chip
e.g.
Transciever
TSE
......
OC-n Line Card Board
OC-n Clock
Clock
Clock
Sync
Sync
Optical signal
155 M, 622 M, 2.5 G,
or 10 Gbit/s
Sync
IDT82V32021 EBU WAN PLL
I2C Programm ing Interface 40 April 24, 2015
4I
2C PROGRAMMING
INTERFACE
The I2C bus interface provides access to read and write the registers
in the IDT82V32021.
4.1 FUNCTION DESCRIPTION
The timing of a complete data transfer is shown in Figure 12.
The transfer process can be divided into three phases:
•START (S) or repeated START (Sr) condition;
•Byte data transfer condition;
•STOP (P) condition.
The definitions of S/Sr and P conditions are shown in Table 28:
Every byte put on the SDA line must be 8-bit long. The number of
bytes that can be transmitted per transfer is unrestricted in theory. Each
byte has to be followed by an acknowledge bit (ACK). So the whole data
transfer needs a period of 9 clock cycles. The data is transferred with the
most significant bit (MSB) first. The input SCL signal for the
IDT82V32021 is from the master device.
Figure 12. Data Transfer on the I2C-bus
Table 28: Definition of S/Sr and P Conditions
Condition Definition
S/Sr A high to low transition on the SDA pin while the SCL pin is high.
P A low to high transition on the SDA pin while the SCL pin is high.
SDA
SCL S
or
Sr
START or
repeated START
condition
MSB acknowledgement
signal from the slave device
byte complete,
interrupt within the Slave device
clock line held low while
interrupts are serviced
acknowledgement
signal from receiver
P
Sr
Sr
or
P
12789123-8 9
ACK ACK
STOP or
repeated START
condition
IDT82V32021 EBU WAN PLL
I2C Programm ing Interface 41 April 24, 2015
4.1.1 DATA TRANSFER FORMAT
Two kinds of data transfer formats are supported by the
IDT82V32021:
•Slave-receiver mode (Write);
•Slave-transmitter mode (Read);
4.1.1.1 Slave-receiver Mode (Write)
The Slave-receiver mode is as shown in Figure 13.
The Master device asserts the slave address followed by the Write
bit. The Slave device acknowledges and the Master device delivers the
address byte. The Slave device again acknowledges before the Master
device sends the data byte. The Slave device acknowledges each byte,
and the entire transaction is finished with a STOP condition.
Figure 13. Slave-receiver Mode
4.1.1.2 Slave-transmitter Mode (Read)
The Slave-transmitter mode is as shown in Figure 14.
First the Master device must write an address byte to the slave
device. Then it must follow that address byte with a repeated START
condition to denote a read from that device’s address. The Slave device
then returns one byte data corresponding the address. Note that there is
no STOP condition before the repeated STRAT condition, and that a no-
acknowledge (NACK) signifies the end of the read transfer.
Figure 14. Slave-transmitter Mode
A AAS
17 1181811
Slave Address Wr Address Byte Data Byte P
S Start Condition
Wr Write (bit value of 0)
Master-to-Slave
Slave-to-Master
Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK)A
Stop Condition
P
S Slave Address Wr Address Byte AASSlave Address Rd A Data Byte A P
1181171181171
S Start Condition
Rd Read (bit value of 1) Wr Write (bit value of 0)
Stop Condition
Master-to-Slave Slave-to-Master
P
Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK)A
IDT82V32021 EBU WAN PLL
I2C Programm ing Interface 42 April 24, 2015
4.1.2 ADDRESS ASSIG NMENT
Figure 15. Address Assignment
Each device is recognized by a unique slave address. The slave
addressing procedure for the I2C-bus is such that the first byte after the
START condition usually determines which slave device will be selected
by the Master device. In this specification, the 4 MSB bits of the address
byte are fixed and the 3 LSB bits are decided by address input pins
AD[2:0], as shown in Figure 15.
The R/W bit is used as a data transfer direction bit which is deter-
mined by the Master device. A ‘0’ on this bit indicates a transmission
(Write) to registers and a ‘1’ indicates a request for data (Read) from the
registers.
The device will acknowledge (ACK) the first byte which is received
after the Start Condition even though it is other device’s address. If the
slave address of the device matches the address input pins AD[2:0], the
device will process the normal read/write operation; otherwise the
device will release the data line with the right pin address for other chip
operation.
4.2 TIMING DEFINITION
The timing of I2C-bus is as shown in Figure 16.
Figure 16. Timing Definition of I2C-bus
A6 A5 A4 A3 A2 A1 A0 R/W
AD2 AD1 AD0 1/01100
SDA
SCL tLOW
tf
tHD: STA tHD: DA T tHIGH
tSU: DAT tf
tSU: STA
tHD: STA tSP
tSU: STO
tBUF
SSr PS
tr
tr
IDT82V32021 EBU WAN PLL
I2C Programm ing Interface 43 April 24, 2015
Table 29: Timing Definition for Standard Mode and Fast Mode(1)
Symbol Parameter Standard Mode Fast Mode Unit
Min Max Min Max
SCL Serial clock frequency 0 100 0 400 KHz
tHD; STA Hold time (repeated) START condition. After this period, the
first clock pulse is generated 4.0 - 0.5 - s
tLOW LOW period of the SCL clock 4.7 - 1.3 - s
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s
tSU; STA Set-up time for a repeated START condition 4.7 - 0.6 - s
tHD; DAT Data hold time: for CBUS compatible masters for I2C-bus
devices 5.0
0(2) -
3.45(3) -
0(2) -
0.9(3) s
tSU; DAT Data set-up time 250 - 100(4) -ns
trRise time of both SDA and SCL signals - 1000 20 + 0.1Cb(5) 300 ns
tfFall time of both SDA and SCL signals - 300 20 + 0.1Cb(5) 300 ns
tSU; STO Set-up time for STOP condition 4.0 - 0.6 - s
tBUF Bus free time between a STOP and START condition 4.7 - 1.3 - s
CbCapacitive load for each bus line - 400 - 400 pF
VnL Noise margin at the LOW level for each connected device
(Including hysteresis) 0.1VDD - 0.1VDD - V
VnH Noise margin at the HIGH level for each connected device
(Including hysteresis) 0.2VDD - 0.2VDD - V
tsp Pulse width of spikes whic h must be suppressed by the input
filter 050050ns
Note:
1. All values referred to VIHmin and VILmax levels (see Table 37)
2. A device must Internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the fall-
ing edge of SCL.
3. The maximum tHD; DAT has only to be met if the device does not strech the LOW period (tLOW) of the SCL signal.
4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU; DA T ≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal , it must ou tput th e next dat a
bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released.
5. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode device, faster fall-times according to Table 39 allowed.
n/a = not applicable
IDT82V32021 EBU WAN PLL
JTAG 44 April 24, 2015
5JTAG
This device is compliant with the IEEE 1149.1 Boundary Scan stan-
dard except the following:
•The output boundary scan cells do not capture data from the
core and the device does not support EXTEST instruction;
•The TRST pin is set low by default and JTAG is disabled in order
to be consistent with other manufacturers.
The JTAG interface timing diagram is shown in Figure 17.
Figure 17. JTAG Interface Timing Diagram
Table 30: JTAG Timing Characteristics
Symbol Parameter Min Typ Max Unit
tTCK TCK period 100 ns
tSTMS / TDI to TCK setup time 25 ns
tHTCK to TMS / TDI Hold Time 25 ns
tDTCK to TDO delay time 50 ns
TCK
TDO
TMS
TDI
tTCK
tStH
tD
IDT82V32021 EBU WAN PLL
Programming Informatio n 45 Ap ril 24, 2015
6 PROGRAMMING INFORMATION
After reset, all the registers are set to their default values. The regis-
ters are read or written via the microprocessor interface.
Before any write operation, the value in register PROTEC-
TION_CNFG is recommended to be confirmed to make sure whether
the write operation is enabled. The device provides 3 register protection
modes:
•Protected mode: no other registers can be written except register
PROTECTION_CNFG itself;
•Fully Unprotected mode: all the writable registers can be written;
•Single Unprotected mode: one more register can be written
besides register PROTECTION_CNFG. After write operation
(not including writing a ‘1’ to clear a bit to ‘0’), the device auto-
matically switches to Protected mode.
Writing ‘0’ to the registers will take no effect if the registers are
cleared by writing ‘1’.
The access of the Multi-word Registers is different from that of the
Single-word Registers. Take the registers (04H, 05H and 06H) for an
example, the write operation for the Multi-word Registers follows a fixed
sequence. The register (04H) is configured first and the register (06H) is
configured last. The three registers are configured continuously and
should not be interrupted by any operation. The crystal calibration con-
figuration will take effect after all the three registers are configured.
During read operation, the register (04H) is read first and the register
(06H) is read last. The crystal calibration reading should be continuous
and not be interrupted by any operation.
Certain bit locations within the device register map are designated as
Reserved. To ensure proper and predictable operation, bits designated
as Reserved should not be written by the users. In addition, their value
should be masked out from any testing or error detection methods that
are implemented.
6.1 REGISTER MAP
Table 31 is the map of all the registers, sorted in an ascending order
of their addresses.
Table 31: Register List and Map
Address
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
Global Control Registers
00 ID[7:0] - Device ID 1 ID[7:0] P 49
01 ID[15:8] - Device ID 2 ID[15:8] P 49
04 NOMINAL_FREQ[7:0]_CNFG - Crys-
tal Oscillator Frequency Offset Calibra-
tion Configuration 1 NOMINAL_FREQ_VALUE[7:0] P 50
05 NOMINAL_FREQ[15:8]_CNFG - Crys-
tal Oscillator Frequency Offset Calibra-
tion Configuration 2 NOMINAL_FREQ_VALUE[15:8] P 50
06 NOMINAL_FREQ[23:16]_CNFG -
Crystal Oscillator Frequency Offset
Calibration Configuration 3 NOMINAL_FREQ_VALUE[23:16] P 50
08 PHASE_ALARM_TIME_OUT_CNFG -
Phase Lock Alarm Time-Out Configu-
ration MULTI_FACTOR[1:0] TIME_OUT_VALUE[5:0] P 51
09 INPUT_MODE_CNFG - Input Mode
Configuration
AUTO_EX-
T_SYN-
C_EN
EXT_SYN-
C_EN
PH_ALAR
M_TIME-
OUT SYNC_FREQ[1:0] IN_SON-
ET_SDH -REVER-
TIVE_-
MODE P52
0A OSCI_CNFG - Master Clock Configu-
ration -----
OSC_EDG
E--P53
0B MON_SW_PBO_CNFG - Frequency
Monitor, Input Clock Selection & PBO
Control
FRE-
Q_MON_-
CLK
LOS_-
FLAG_TO_
TDO
ULTR_-
FAST_SW EXT_SW PBO_-
FREZ PBO_EN - FRE-
Q_MON_H
ARD_EN P54
7E PROTECTION_CNFG - Register Pro-
tection Mode Configuration PROTECTION_DATA[7:0] P 55
Interrupt Registers
0C INTERRUPT_CNFG - Interrupt Con-
figuration ------HZ_ENINT_POLP56
IDT82V32021 EBU WAN PLL
Programming Informatio n 46 Ap ril 24, 2015
0D INTERRUPTS1_STS - Interrupt Status
1- - - - IN2_CMOS IN1_CMOS - - P 56
0E INTERRUPTS2_STS - Interrupt Status
2
T0_OPER-
ATING_-
MODE
T0_-
MAIN_REF
_FAILED ------P57
0F INTERRUPTS3_STS - Interrupt Status
3EX_SYN-
C_ALARM -------P57
10 INTERRUPTS1_ENABLE_CNFG -
Interrupt Control 1 - - - - IN2_CMOS IN1_CMOS - - P 58
11 INTERRUPTS2_ENABLE_CNFG -
Interrupt Control 2
T0_OPER-
ATING_-
MODE
T0_-
MAIN_REF
_FAILED ------P58
12 INTERRUPTS3_ENABLE_CNFG -
Interrupt Control 3 EX_SYN-
C_ALARM -------P59
Input Clock Frequency & Priority Configuration Registers
16 IN1_CMOS_CNFG - CMOS Input
Clock 1 Configuration DIRECT_D
IV LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] P 60
17 IN2_CMOS_CNFG - CMOS Input
Clock 2 Configuration DIRECT_D
IV LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] P 61
23 PRE_DIV_CH_CNFG - DivN Divider
Channel Selection - - - - PRE_DIV_CH_VALUE[3:0] P 62
24 PRE_DIVN[7:0]_CNFG - DivN Divider
Division Factor Configuration 1 PRE_DIVN_VALUE[7:0] P 62
25 PRE_DIVN[14:8]_CNFG - DivN
Divider Division Factor Configuration 2 - PRE_DIVN_VALUE[14:8] P 63
27 IN1_IN2_CMOS_SEL_PRIORI-
TY_CNFG - CMOS Input Clock 1 & 2
Priority Configuration IN2_CMOS_SEL_PRIORITY[3:0] IN1_CMOS_SEL_PRIORITY[3:0] P 64
Input Clock Quality Monitoring Configuration & Status Registers
2E FREQ_MON_FACTOR_CNFG - Fac-
tor of Frequency Monitor Configuration - - - - FREQ_MON_FACTOR[3:0] P 65
2F
ALL_FREQ_MON_THRESH-
OLD_CNFG - Frequency Monitor
Threshold for All Input Clocks Configu-
ration
- - - - ALL_FREQ_HARD_THRESHOLD[3:0] P 65
31 UPPER_THRESHOLD_0_CNFG -
Upper Threshold for Leaky Bucket
Configuration 0 UPPER_THRESHOLD_0_DATA[7:0] P 66
32 LOWER_THRESHOLD_0_CNFG -
Lower Threshold for Leaky Bucket
Configuration 0 LOWER_THRESHOLD_0_DATA[7:0] P 66
33 BUCKET_SIZE_0_CNFG - Bucket
Size for Leaky Bucket Configuration 0 BUCKET_SIZE_0_DATA[7:0] P 66
34 DECAY_RATE_0_CNFG - Decay Rate
for Leaky Bucket Configuration 0 ------
DECAY_RATE_0_-
DATA[1:0] P67
35 UPPER_THRESHOLD_1_CNFG -
Upper Threshold for Leaky Bucket
Configuration 1 UPPER_THRESHOLD_1_DATA[7:0] P 67
Table 31: Register List and Map (Continued)
Address
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
IDT82V32021 EBU WAN PLL
Programming Informatio n 47 Ap ril 24, 2015
36 LOWER_THRESHOLD_1_CNFG -
Lower Threshold for Leaky Bucket
Configuration 1 LOWER_THRESHOLD_1_DATA[7:0] P 67
37 BUCKET_SIZE_1_CNFG - Bucket
Size for Leaky Bucket Configuration 1 BUCKET_SIZE_1_DATA[7:0] P 68
38 DECAY_RATE_1_CNFG - Decay Rate
for Leaky Bucket Configuration 1 ------
DECAY_RATE_1_-
DATA[1:0] P68
39 UPPER_THRESHOLD_2_CNFG -
Upper Threshold for Leaky Bucket
Configuration 2 UPPER_THRESHOLD_2_DATA[7:0] P 68
3A LOWER_THRESHOLD_2_CNFG -
Lower Threshold for Leaky Bucket
Configuration 2 LOWER_THRESHOLD_2_DATA[7:0] P 69
3B BUCKET_SIZE_2_CNFG - Bucket
Size for Leaky Bucket Configuration 2 BUCKET_SIZE_2_DATA[7:0] P 69
3C DECAY_RATE_2_CNFG - Decay Rate
for Leaky Bucket Configuration 2 ------
DECAY_RATE_2_-
DATA[1:0] P69
3D UPPER_THRESHOLD_3_CNFG -
Upper Threshold for Leaky Bucket
Configuration 3 UPPER_THRESHOLD_3_DATA[7:0] P 70
3E LOWER_THRESHOLD_3_CNFG -
Lower Threshold for Leaky Bucket
Configuration 3 LOWER_THRESHOLD_3_DATA[7:0] P 70
3F BUCKET_SIZE_3_CNFG - Bucket
Size for Leaky Bucket Configuration 3 BUCKET_SIZE_3_DATA[7:0] P 70
40 DECAY_RATE_3_CNFG - Decay Rate
for Leaky Bucket Configuration 3 ------
DECAY_RATE_3_-
DATA[1:0] P71
41 IN_FREQ_READ_CH_CNFG - Input
Clock Frequency Read Channel
Selection - - - - IN_FREQ_READ_CH[3:0] P 71
42 IN_FREQ_READ_STS - Input Clock
Frequency Read Value IN_FREQ_VALUE[7:0] P 71
44 IN1_IN2_CMOS_STS - CMOS Input
Clock 1 & 2 Status -
IN2_C-
MOS_-
FREQ_HA
RD_ALAR
M
IN2_C-
MOS_NO_
ACTIVI-
TY_ALAR
M
IN2_C-
MOS_PH_
LOCK_AL
ARM
-
IN1_C-
MOS_-
FREQ_HA
RD_ALAR
M
IN1_C-
MOS_NO_
ACTIVI-
TY_ALAR
M
IN1_C-
MOS_PH_
LOCK_AL
ARM
P72
T0 DPLL Input Clock Selection Registers
4A INPUT_VALID1_STS - Input Clocks
Validity 1 - - - - IN2_CMOS IN1_CMOS - - P 73
4E PRIORITY_TABLE1_STS - Priority
Status 1 HIGHEST_PRIORITY_VALIDATED[3:0] CURRENTLY_SELECTED_INPUT[3:0] P 73
4F PRIORITY_TABLE2_STS - Priority
Status 2 ----SECOND_HIGHEST_PRIORITY_VALI-
DATED[3:0] P74
50 T0_INPUT_SEL_CNFG - T0 Selected
Input Clo ck Configuratio n - - - - T0_INPUT_SEL[3:0] P74
T0 DPLL State Machine Control Registers
52 OPERATING_STS - DPLL Operating
Status
EX_SYN-
C_ALARM
_MON -
T0_DPLL_-
SOFT_-
FREQ_AL
ARM
-T0_D-
PLL_LOCK T0_DPLL_OPERATING_MODE[2:0] P 75
Table 31: Register List and Map (Continued)
Address
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
IDT82V32021 EBU WAN PLL
Programming Informatio n 48 Ap ril 24, 2015
53 T0_OPERATING_MODE_CNFG - T0
DPLL Operating Mode Configuration - - - - - T0_OPERATING_MODE[2:0] P 76
T0 DPLL & T0 APLL Configuration Registers
55 T0_DPLL_APLL_PATH_CNFG - T0
DPLL & APLL Path Configuration T0_APLL_PATH[3:0] T0_GSM_OBSA-
I_16E1_16T1_SEL[1:0] T0_12E1_24T1_E3_T3
_SEL[1:0] P77
56 T0_DPLL_START_BW_DAMP-
ING_CNFG - T0 DPLL Start Band-
width & Damping Factor Configuration T0_DPLL_START_DAMPING[2:0] T0_DPLL_START_BW[4:0] P 78
57
T0_DPLL_ACQ_BW_DAMP-
ING_CNFG - T0 DPLL Acquisition
Bandwidth & Damping Factor Configu -
ration
T0_DPLL_ACQ_DAMPING[2:0] T0_DPLL_ACQ_BW[4:0] P 79
58 T0_DPLL_LOCKED_BW_DAMP-
ING_CNFG - T0 DPLL Locked Band-
width & Damping Factor Configuration T0_DPLL_LOCKED_DAMPING[2:0] T0_DPLL_LOCKED_BW[4:0] P 80
59 T0_BW_OVERSHOOT_CNFG - T0
DPLL Bandwidth Overshoot Configu-
ration
AUTO_B-
W_SEL - - - T0_LIMT - - - P 80
5A PHASE_LOSS_COARSE_LIM-
IT_CNFG - Phase Loss Coarse Detec-
tor Limit Configuration
COARSE_
PH_LOS_L
IMT_EN WIDE_EN MUL-
TI_PH_AP
P
MUL-
TI_PH_8K
_4K_2K_E
N
PH_LOS_COARSE_LIMT[3:0] P 81
5B PHASE_LOSS_FINE_LIMIT_CNFG -
Phase Loss Fine Detector Limit Con-
figuration
FINE_PH_
LOS_LIMT
_EN
FAST_LOS
_SW - - - PH_LOS_FINE_LIMT[2:0] P 82
5C T0_HOLDOVER_MODE_CNFG - T0
DPLL Holdover Mode Configuration MAN_HOL
DOVER AUTO_AV
GFAST_AVG READ_AV
GTEMP_HOLDOVER_-
MODE[1:0] --P83
5D T0_HOLDOVER_FREQ[7:0]_CNFG -
T0 DPLL Holdover Frequency Config-
uration 1 T0_HOLDOVER_FREQ[7:0] P 83
5E T0_HOLDOVER_FREQ[15:8]_CNFG
- T0 DPLL Holdover Frequency Con-
figuration 2 T0_HOLDOVER_FREQ[15:8] P 84
5F T0_HOLDOVER_-
FREQ[23:16]_CNFG - T0 DPLL Hold-
over Frequency Configuration 3 T0_HOLDOVER_FREQ[23:16] P 84
62 CURRENT_DPLL_FREQ[7:0]_STS -
DPLL Current Frequency Status 1 CURRENT_DPLL_FREQ[7:0] P 84
63 CURRENT_DPLL_FREQ[15:8]_STS -
DPLL Current Frequency Status 2 CURRENT_DPLL_FREQ[15:8] P 85
64 CURRENT_DPLL_FREQ[23:16]_STS
- DPLL Current Frequency Status 3 CURRENT_DPLL_FREQ[23:16] P 85
65 DPLL_FREQ_SOFT_LIMIT_CNFG -
DPLL Soft Limit Configuration
FRE-
Q_LIMT_P
H_LOS DPLL_FREQ_SOFT_LIMT[6:0] P 85
66 DPLL_FRE-
Q_HARD_LIMIT[7:0]_CNFG - DPLL
Hard Limit Configuration 1 DPLL_FREQ_HARD_LIMT[7:0] P 86
67 DPLL_FRE-
Q_HARD_LIMIT[15:8]_CNFG - DPLL
Hard Limit Configuration 2 DPLL_FREQ_HARD_LIMT[15:8] P 86
Table 31: Register List and Map (Continued)
Address
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
IDT82V32021 EBU WAN PLL
Programming Informatio n 49 Ap ril 24, 2015
6.2 REGISTER DESCRIPTION
6.2.1 GLOBAL CONTROL REGISTERS
ID[7:0] - Device ID 1
68 CURRENT_DPLL_PHASE[7:0]_STS -
DPLL Current Phase Status 1 CURRENT_PH_DATA[7:0] P 86
69 CURRENT_D-
PLL_PHASE[15:8]_STS - DPLL Cur-
rent Phase Status 2 CURRENT_PH_DATA[15:8] P 87
6A T0_APLL_BW_CNFG - T0 APLL
Bandwidth Configuration - - T0_APLL_BW[1:0] - - - - P 87
Output Configuration Registers
6D OUT1_FREQ_CNFG - Output Cloc k 1
Frequency Configuration OUT1_PATH_SEL[3:0] OUT1_DIVIDER[3:0] P 88
73 OUT1_INV_CNFG - Output Clock 1
Invert Configuration -----OUT1_INV--P88
74 FR_SYNC_CNFG - Frame Sync Out-
put Configuration IN_2K_4K_
8K_INV 8K_EN - 8K_PUL_P
OSITION 8K_INV 8K_PUL - - P 89
PBO & Phase Offset Control Registers
78 PHASE_MON_PBO_CNFG - Phase
Transient Monitor & PBO Configura-
tion
IN_NOISE
_WINDOW -PH_MON_
EN PH_MON_
PBO_EN PH_TR_MON_LIMT[3:0] P 90
Synchronization Configuration Registers
7C SYNC_MONITOR_CNFG - Sync Mon-
itor Configuration SYNC_BY-
PASS SYNC_MON_LIMT[2:0] - - - - P 91
7D SYNC_PHASE_CNFG - Sync Phase
Configuration - - - SYNC_PH2[1:0] SYNC_PH1[1:0] P 91
Table 31: Register List and Map (Continued)
Address
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
Address: 00H
Type: Read
Default Value: 10001000
Bit Name Description
7 - 0 ID[7:0] Refer to the description of the ID[15:8] bits (b7~0, 01H).
76543210
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
IDT82V32021 EBU WAN PLL
Programming Informatio n 50 Ap ril 24, 2015
ID[15:8] - Device ID 2
NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1
NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2
Address: 01H
Type: Read
Default Value: 00010001
Bit Name Description
7 - 0 ID[15:8] The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V32021.
Address: 04H
Type: Read / Write
Default Value: 00000000
Bit Name Description
7 - 0 NOMINAL_FREQ_VALUE[7:0] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H).
Address: 05H
Type: Read / Write
Default Value: 00000000
Bit Name Description
7 - 0 NOMINAL_FREQ_VALUE[15:8] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H).
76543210
ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
76543210
NOMINAL_-
FREQ_VALUE7 NOMINAL_-
FREQ_VALUE6 NOMINAL_-
FREQ_VALUE5 NOMINAL_-
FREQ_VALUE4 NOMINAL_-
FREQ_VALUE3 NOMINAL_-
FREQ_VALUE2 NOMINAL_-
FREQ_VALUE1 NOMINAL_-
FREQ_VALUE0
76543210
NOMINAL_-
FREQ_VAL-
UE15
NOMINAL_-
FREQ_VAL-
UE14
NOMINAL_-
FREQ_VAL-
UE13
NOMINAL_-
FREQ_VAL-
UE12
NOMINAL_-
FREQ_VAL-
UE11
NOMINAL_-
FREQ_VAL-
UE10
NOMINAL_-
FREQ_VALUE9 NOMINAL_-
FREQ_VALUE8
IDT82V32021 EBU WAN PLL
Programming Informatio n 51 Ap ril 24, 2015
NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3
PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration
Address: 06H
Type: Read / Write
Default Value: 00000000
Bit Name Description
7 - 0 NOMINAL_FREQ_VALUE[23:16]
The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is multiplied by
0.0000884, the calibration value for the master clock in ppm will be gotten.
For example, the fre quency offset on OSCI is +3 ppm. Though -3 ppm should be comp ensated, the calibration valu e is
calcula ted as +3 ppm:
3 ÷ 0.0000884 = 33937 (Dec.) = 8490 (Hex);
So ‘008490’ should be written into these bits.
The calibration range is within ±741 ppm.
Address: 08H
Type: Read / Write
Default Value: 00110010
Bit Name Description
7 - 6 MULTI_FACTOR[1:0]
These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0
selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the
phase lock ala rm will be cleared after this period (starting from wh en the alarm is raised). Refer t o the descri ption of the
TIME_OUT_VALUE[5:0] bits (b5~0, 08H).
00: 2 (default)
01: 4
10: 8
11: 16
5 - 0 TIME_OUT_VALUE[5:0]
These bits represent an un signed integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0]
bits (b7~6, 08H), a period in seconds will be gotten.
A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’ , the phase lock alarm will be cleared after this p eriod (starting from when the
alarm is raised).
76543210
NOMINAL_-
FREQ_VAL-
UE23
NOMINAL_-
FREQ_VAL-
UE22
NOMINAL_-
FREQ_VAL-
UE21
NOMINAL_-
FREQ_VAL-
UE20
NOMINAL_-
FREQ_VAL-
UE19
NOMINAL_-
FREQ_VAL-
UE18
NOMINAL_-
FREQ_VAL-
UE17
NOMINAL_-
FREQ_VAL-
UE16
7654321 0
MULTI_FAC-
TOR1 MULTI_FAC-
TOR0 TIME_OUT_VA
LUE5 TIME_OUT_VA
LUE4 TIME_OUT_VA
LUE3 TIME_OUT_VA
LUE2 TIME_OUT_VA
LUE1 TIME_OUT_VAL
UE0
IDT82V32021 EBU WAN PLL
Programming Informatio n 52 Ap ril 24, 2015
INPUT_MODE_CNFG - Input Mode Configuration
Address: 09H
Type: Read / Write
Default Value: 10100X10
Bit Name Description
7 AUTO_EXT_SYNC_EN This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’.
Refer to the description of the EXT_SYNC_EN bit (b6, 09H).
6 EXT_SYNC_EN
This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’.
This bit, together with the AUTO_EXT_SYNC_EN bit (b 7, 09H), deter mines whe ther the s elected frame sy nc input s ignal is
enabled to synchronize the frame sync output signals.
5 PH_ALARM_TIMEOUT
This bit determines how to clear the phase lock alarm.
0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_CMOS_PH_LOCK_ALARM bit (n = 1
or 2) (b4/0, 44H).
1: The phase lock alarm will be cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0]
(b7~6, 08H) in second) which starts from when the alarm is raised. (default)
4 - 3 SYNC_FREQ[1:0]
These bits set the frequency of the frame sync signals input on the EX_SYNC1 ~ EX_SYNC2 pins.
00: 8 kHz (default)
01: 8 kHz.
10: 4 kHz.
11: 2 kHz.
2 IN_SONET_SDH
This bit selects the SDH or SONET network type.
0: SDH. The DPLL required clock is 2.048 MHz when the IN_ FRE Q[3:0] bits (b3~0, 1 6H, 17H) are ‘0001’ and the T0 DPL L
output from the 16E1/16T1 path is 16E1.
1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 16H, 17H) are ‘0001’ and the T0
DPLL output from the 16E1/16T1 path is 16T1.
The default value of this bit is determined by the SONET/SDH pin during reset.
1-Reserved.
0 REVERTIVE_MODE This bit selects Revertive or Non-Revertive switch.
0: Non-Revertive switch. (default)
1: Revertive switch.
76543210
AUTO_EX-
T_SYNC_EN EXT_SYNC_EN PH_ALARM_-
TIMEOUT SYNC_FREQ1 SYNC_FREQ0 IN_SON-
ET_SDH -REVERTIVE_-
MODE
AUTO_EXT_SYNC_EN EXT_SYNC_EN Synchronization
don’t-care 0 Disabled (default)
01 Enabled
11 Disabled
IDT82V32021 EBU WAN PLL
Programming Informatio n 53 Ap ril 24, 2015
OSCI_CNFG - Master Clock Configuration
Address: 0AH
Type: Read / Write
Default Value: XXXXX00X
Bit Name Description
7 - 3 - Reserved.
2OSC_EDGE
This bit selects a better active edge of the master clock.
0: The rising edge. (default)
1: The falling edge.
1 - 0 - Reserved
7654 3 2 1 0
---- -OSC_EDGE- -
IDT82V32021 EBU WAN PLL
Programming Informatio n 54 Ap ril 24, 2015
MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control
Address: 0BH
Type: Read / Write
Default Value: 100X01X1
Bit Name Description
7 FREQ_MON_CLK The bit selects a reference clock for input clock frequency monitoring.
0: The output of T0 DPLL.
1: The master clock. (default)
6 LOS_FLAG_TO_TDO
The bit determines whether the interrupt of T0 selected input clock fail - is reported by the TDO pin.
0: Not reported. TDO pin is used as JTAG test data output which complies with IEEE 1149.1. (default)
1: Reported. TDO pin mim ics the state of th e T0_MAI N_REF_FAILED bit (b6, 0EH) and does no t strictly comply with IEEE
1149.1.
5 ULTR_FAST_SW This bit determines whether the T0 selected input clock is valid when missing 2 consecutive clock cycles or more.
0: Valid. (default)
1: Invalid.
4EXT_SW
This bit determines the T0 input clock selection.
0: Forced selection or Automatic selection, as controlled by the T0_INPUT_SEL[3:0] bits (b3~0, 50H).
1: External Fast selection.
The default value of this bit is determined by the FF_SRCSW pin during reset.
3 PBO_FREZ
This bit is valid only when the PBO is enabled by the PBO_EN bit (b2, 0BH). It determines whether PBO is frozen at the cur-
rent phase offset when a PBO event is triggered.
0: Not frozen. (default)
1: Frozen. Further PBO events are ignored and the current phase offset is maintained.
2 PBO_EN
This bit determines whet her PBO is enable d when the T0 select ed input c lock swi tch or th e T0 DPL L exiti ng f rom Holdov er
mode or Free-Run mode occurs.
0: Disabled.
1: Enabled. (default)
1-Reserved.
0 FREQ_MON_HARD_EN
This bit determines whe ther the frequency hard al arm is enabled when th e frequency of the inpu t clock with respec t to the
reference clock is above the frequency hard alarm threshold. The reference clock can be the output of T0 DPLL or the mas-
ter clock, as determined by the FREQ_MON_CLK bit (b7, 0BH).
0: Disabled.
1: Enabled. (default)
76 5 43210
FREQ_MON_-
CLK LOS_-
FLAG_TO_TDO ULTR_FAST_SW EXT_SW PBO_FREZ PBO_EN - FRE-
Q_MON_HARD
_EN
IDT82V32021 EBU WAN PLL
Programming Informatio n 55 Ap ril 24, 2015
PROTECTION_CNFG - Register Protection Mode Configuration
Address: 7EH
Type: Read / Write
Default Value: 10000101
Bit Name Description
7 - 0 PROTECTION_DATA[7:0]
These bits select a register write protection mode.
00000000 - 10000100, 10000111 - 11111111: Protected mode. No other registers can be written except this register.
10000101: Fully Unprotected mode. All the writable registers can be written. (default)
10000110: Single Unprotected mode. One more register can be written besides this register. After write operation (not
including writing a ‘1’ to clear the bit to ‘0’), the device automatically switches to Protected mode.
76543210
PROTEC-
TION_DATA7 PROTEC-
TION_DATA6 PROTEC-
TION_DATA5 PROTEC-
TION_DATA4 PROTEC-
TION_DATA3 PROTEC-
TION_DATA2 PROTEC-
TION_DATA1 PROTEC-
TION_DATA0
IDT82V32021 EBU WAN PLL
Programming Informatio n 56 Ap ril 24, 2015
6.2.2 INTERRUPT REGISTERS
INTERRUPT_CNFG - Interrupt Configuration
INTERRUPTS1_STS - Interrupt Status 1
Address: 0CH
Type: Read / Write
Default Value: XXXXXX10
Bit Name Description
7 - 2 - Reserved.
1HZ_EN
This bit determines the output characteristics of the INT_REQ pin.
0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive.
1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance st ate when the inte rrupt
is inactive. (default)
0INT_POL
This bit determines the active level on the INT_REQ pin for an active interrupt indication.
0: Active l ow. (default)
1: Active h igh.
Address: 0DH
Type: Read / Write
Default Value: XXXX11XX
Bit Name Description
7 - 4 - Reserved.
3 - 2 INn_CMOS
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn_CMOS; i.e.,
whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn_CMOS bit (b3/2, 4AH). Here n is 2 or 1.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
1 - 0 - Reserved.
76543210
------HZ_ENINT_POL
76543210
----IN2_CMOSIN1_CMOS--
IDT82V32021 EBU WAN PLL
Programming Informatio n 57 Ap ril 24, 2015
INTERRUPTS2_STS - Interrupt Status 2
INTERRUPTS3_STS - Interrupt Status 3
Address: 0EH
Type: Read / Write
Default Value: 00XXXXXX
Bit Name Description
7 T0_OPERATING_MODE
This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the T0_DPLL_OPERATING_-
MODE[2:0] bits (b2~0, 52H) changes.
0: Has not switched. (default)
1: Has switched.
This bit is cleared by writing a ‘1’.
6 T0_MAIN_REF_FAILED
This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity
changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn_CMOS bit (4AH).
0: Has not failed. (default)
1: Has failed.
This bit is cleared by writing a ‘1’.
5 - 0 - Reserved.
Address: 0FH
Type: Read / Write
Default Value: 1XXXXXXX
Bit Name Description
7 EX_SYNC_ALARM
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the EX_SYN-
C_ALARM_MON bit (b7, 52H).
0: Has not occurred.
1: Has occurred. (default)
This bit is cleared by writing a ‘1’.
6 - 0 - Reserved.
7 6 543210
T0_OPERAT-
ING_MODE T0_MAIN_REF_-
FAILED ------
7 6543210
EX_SYNC_ALARM - - - - - - -
IDT82V32021 EBU WAN PLL
Programming Informatio n 58 Ap ril 24, 2015
INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1
INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2
Address: 10H
Type: Read / Write
Default Value: XXXX00XX
Bit Name Description
7 - 4 - Reserved.
3 - 2 INn_CMOS
This bit controls whether the interrupt is enabled to be reported on the I NT_REQ pin when the inp ut clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn_CMOS bit (b3/2, 0DH) is ‘1’. Here n is 2 or 1.
0: Disabled. (default)
1: Enabled.
1 - 0 - Reserved.
Address: 11H
Type: Read / Write
Default Value: 00XXXXXX
Bit Name Description
7 T0_OPERATING_MODE
This bit controls whethe r the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode
switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
6 T0_MAIN_REF_FAILED
This bit controls whether the interrup t is enabled to be reported on the INT_REQ pin when the T0 selected in put clock
has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
5 - 0 - Reserved.
76543210
----IN2_CMOSIN1_CMOS--
7 6 543210
T0_OPERAT-
ING_MODE T0_MAIN_REF_-
FAILED ------
IDT82V32021 EBU WAN PLL
Programming Informatio n 59 Ap ril 24, 2015
INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3
Address: 12H
Type: Read / Write
Default Value: 0XXXXXXX
Bit Name Description
7 EX_SYNC_ALARM
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has
occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
6 - 0 - Reserved.
7 6543210
EX_SYNC_ALARM - - - - - - -
IDT82V32021 EBU WAN PLL
Programming Informatio n 60 Ap ril 24, 2015
6.2.3 INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS
IN1_CMOS_CNFG - CMOS Input Clock 1 Configuration
Address: 16H
Type: Read / Write
Default Value: 00000000
Bit Name Description
7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 16H).
6LOCK_8K
This bit, together with th e DIRECT_DIV bit (b7, 16H), determines whether th e DivN Divider or the Lock 8k Divider i s used for
IN1_CMOS:
5 - 4 BUCKET_SEL[1:0]
These bits select one of the four groups of leaky bucket configuration registers for IN1_CMOS:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
3 - 0 IN_FREQ[3:0]
These bits set the DPLL required frequency for IN1_CMOS:
0000: 8 kHz. (default)
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.4 4 MHz.
0100: 25.92 MHz.
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN1_CMOS, the required frequency should not be set higher than that of the input clock.
76543210
DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0
DIRECT_DIV bit LOCK_8K bit Used Divider
0 0 Both bypassed (default)
0 1 Lock 8k Divider
10 DivN Divider
11 Reserved
IDT82V32021 EBU WAN PLL
Programming Informatio n 61 Ap ril 24, 2015
IN2_CMOS_CNFG - CMOS Input Clock 2 Configuration
Address: 17H
Type: Read / Write
Default Value: 00000000
Bit Name Description
7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 17H).
6LOCK_8K
This bit, together with the DIRECT_DIV bit (b7, 17H), determi nes whether the DivN Divider or the Lock 8k Divider is used for
IN2_CMOS:
5 - 4 BUCKET_SEL[1:0]
These bits select one of the four groups of leaky bucket configuration registers for IN2_CMOS:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
3 - 0 IN_FREQ[3:0]
These bits set the DPLL required frequency for IN2_CMOS:
0000: 8 kHz. (default)
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.4 4 MHz.
0100: 25.92 MHz.
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For the IN2_CMOS, the required frequency should not be set higher than that of the input clock.
76543210
DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0
DIRECT_DIV bit LOCK_8K bit Used Divider
0 0 Both bypassed (default)
0 1 Lock 8k Divider
10 DivN Divider
11 Reserved
IDT82V32021 EBU WAN PLL
Programming Informatio n 62 Ap ril 24, 2015
PRE_DIV_CH_CNFG - DivN Divider Channel Selection
PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1
Address: 23H
Type: Read / Write
Default Value: XXXX0000
Bit Name Description
7 - 4 - Reserved.
3 - 0 PRE_DIV_CH_VALUE[3:0]
This register is an indirect address register for Register 24H and 25H.
These bits select an input clock. The value set in the PRE_DIVN_VALUE[14:0] bits (25H, 24H) is available for the
selected input clock.
0000: Reserved. (defa ult)
0001, 0010: Reserved.
0011: IN1 _CMOS.
0100: IN2_CMOS.
0101 ~ 1111: Reserved.
Address: 24H
Type: Read / Write
Default Value: 00000000
Bit Name Description
7 - 0 PRE_DIVN_VALUE[7:0] Refer to the description of the PRE_DIVN_VALUE[14:8] bits (b6~0, 25H).
7654 3 2 1 0
- - - - PRE_DIV_CH_VALUE3 PRE_DIV_CH_VALUE2 PRE_DIV_CH_VALUE1 PRE_DIV_CH_VALUE0
76543210
PRE_DIVN_VA
LUE7 PRE_DIVN_VA
LUE6 PRE_DIVN_VA
LUE5 PRE_DIVN_VA
LUE4 PRE_DIVN_VA
LUE3 PRE_DIVN_VA
LUE2 PRE_DIVN_VA
LUE1 PRE_DIVN_VA
LUE0
IDT82V32021 EBU WAN PLL
Programming Informatio n 63 Ap ril 24, 2015
PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2
Address: 25H
Type: Read / Write
Default Value: X0000000
Bit Name Description
7-Reserved.
6 - 0 PRE_DIVN_VALUE[14:8]
If the value in the PRE_DIVN_VALUE[14:0] bits is pl us 1, the division factor for an input c lock will be gotten. The input
clock is selected by the PRE_DIV_CH_VALUE[3:0] bits (b3~0, 23H).
A value from ‘0’ to ‘4BEF’ (Hex) can be wri tten into, corresponding to a division fac tor from 1 to 19440. The others are
reserved. So the DivN Divider only supports an input clock whose frequency is lower than () 155.52 MHz.
The division factor setting should observe the following order:
1. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits;
2. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits.
76543210
-PRE_DIVN_VAL
UE14 PRE_DIVN_VAL
UE13 PRE_DIVN_VAL
UE12 PRE_DIVN_VAL
UE11 PRE_DIVN_VAL
UE10 PRE_DIVN_VAL
UE9 PRE_DIVN_VAL
UE8
IDT82V32021 EBU WAN PLL
Programming Informatio n 64 Ap ril 24, 2015
IN1_IN2_CMOS_SEL_PRIORITY_CNFG - CMOS Input Clock 1 & 2 Priority Configuration
Address: 27H
Type: Read / Write
Default Value: 00110010
Bit Name Description
7 - 4 IN2_CMOS_SEL_PRIORITY[3:0]
These bits set the priority of the corresponding IN2_CMOS.
0000: Disable IN2_CMOS for automatic selection.
0001: Priority 1.
0010: Priority 2.
0011: Priority 3. (default)
0100: Priority 4.
0101: Priority 5.
0110: Priority 6.
0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
3 - 0 IN1_CMOS_SEL_PRIORITY[3:0]
These bits set the priority of the corresponding IN1_CMOS.
0000: Disable IN1_CMOS for automatic selection.
0001: Priority 1.
0010: Priority 2. (default)
0011: Priority 3.
0100: Priority 4.
0101: Priority 5.
0110: Priority 6.
0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
76543210
IN2_C-
MOS_SEL_PRI-
ORITY3
IN2_C-
MOS_SEL_PRI-
ORITY2
IN2_C-
MOS_SEL_PRI-
ORITY1
IN2_C-
MOS_SEL_PRI-
ORITY0
IN1_C-
MOS_SEL_PRI-
ORITY3
IN1_C-
MOS_SEL_PRI-
ORITY2
IN1_C-
MOS_SEL_PRI-
ORITY1
IN1_C-
MOS_SEL_PRI-
ORITY0
IDT82V32021 EBU WAN PLL
Programming Informatio n 65 Ap ril 24, 2015
6.2.4 INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS
FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration
ALL_FREQ_MON_THRESHOLD_CNFG - Frequency Monitor Threshold for All Input Clocks Configuration
Address: 2EH
Type: Read / Write
Default Value: XXXX101 1
Bit Name Description
7 - 4 - Reserved.
3 - 0 FREQ_MON_FACTOR[3:0]
These bits determine a factor. The factor ha s a relationship with the fre quency hard alarm threshold in ppm (refer to
the description of the ALL_FREQ_HARD_THRESHOLD[3:0] bits (b3~0, 2FH)) and with the frequency of the input
clock with respect to the ma ste r cl ock in pp m (refe r to the description of the IN_FREQ_VALUE[7:0] bits (b 7~0, 42H)).
The factor represents the accuracy of the frequency monitor and should be set according to the requirements of differ-
ent applications.
0000: 0.0032.
0001: 0.0064.
0010: 0.0127.
0011: 0.02 57.
0100: 0.0514.
0101: 0.103.
0110: 0.206.
0111: 0.412.
1000: 0.823.
1001: 1.646.
1010: 3.292.
1011: 3.81 . (defaul t)
1100 - 1111: 4.6.
Address: 2FH
Type: Read / Write
Default Value: XXXX001 1
Bit Name Description
7 - 4 - Reserved.
3 - 0 ALL_FREQ_HARD_THRESHOLD[3:0]
These bits represent an unsigned integer . The frequency hard alarm threshold in ppm can be calculated as
follows:
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_THRESHOLD[3:0] + 1) X FRE-
Q_MON_FACTOR[3:0] (b3~0, 2EH)
This threshold is symmetrical about zero.
76543210
----
FREQ_MON_-
FACTOR3 FREQ_MON_-
FACTOR2 FREQ_MON_-
FACTOR1 FREQ_MON_-
FACTOR0
7654 3210
----
ALL_FRE-
Q_HARD_-
THRESHOLD3
ALL_FRE-
Q_HARD_-
THRESHOLD2
ALL_FRE-
Q_HARD_-
THRESHOLD1
ALL_FRE-
Q_HARD_-
THRESHOLD0
IDT82V32021 EBU WAN PLL
Programming Informatio n 66 Ap ril 24, 2015
UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0
LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket Configuration 0
BUCKET_SIZE_0_CNFG - Bucket Size for Leaky Bucket Configuration 0
Address: 31H
Type: Read / Write
Default Value: 00000110
Bit Name Description
7 - 0 UPPER_THRESHOLD_0_DATA[7:0] These bits set an upper threshold for the internal leaky bu cket accumulator. When the number of the accumu-
lated events is above this threshold, a no-activity alarm is raised.
Address: 32H
Type: Read / Write
Default Value: 00000100
Bit Name Description
7 - 0 LOWER_THRESHOLD_0_DATA[7:0] These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated
events is below this threshold, the no-activity alarm is cleared.
Address: 33H
Type: Read / Write
Default Value: 00001000
Bit Name Description
7 - 0 BUCKET_SIZE_0_DATA[7:0] These bits set a bucket size for the interna l leaky bucket accumul ator. If the number of the accumulated events reach
the bucket size, the accumulator will stop increasing even if further events are detected.
76543210
UPPER_-
THRESH-
OLD_0_DATA7
UPPER_-
THRESH-
OLD_0_DATA6
UPPER_-
THRESH-
OLD_0_DATA5
UPPER_-
THRESH-
OLD_0_DATA4
UPPER_-
THRESH-
OLD_0_DATA3
UPPER_-
THRESH-
OLD_0_DATA2
UPPER_-
THRESH-
OLD_0_DATA1
UPPER_-
THRESH-
OLD_0_DATA0
76543210
LOWER_-
THRESH-
OLD_0_DATA7
LOWER_-
THRESH-
OLD_0_DATA6
LOWER_-
THRESH-
OLD_0_DATA5
LOWER_-
THRESH-
OLD_0_DATA4
LOWER_-
THRESH-
OLD_0_DATA3
LOWER_-
THRESH-
OLD_0_DATA2
LOWER_-
THRESH-
OLD_0_DATA1
LOWER_-
THRESH-
OLD_0_DATA0
76543210
BUCKET_-
SIZE_0_DATA7 BUCKET_-
SIZE_0_DATA6 BUCKET_-
SIZE_0_DATA5 BUCKET_-
SIZE_0_DATA4 BUCKET_-
SIZE_0_DATA3 BUCKET_-
SIZE_0_DATA2 BUCKET_-
SIZE_0_DATA1 BUCKET_-
SIZE_0_DATA0
IDT82V32021 EBU WAN PLL
Programming Informatio n 67 Ap ril 24, 2015
DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0
UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket Configuration 1
LOWER_THRESHOLD_1_CNFG - Lower Threshold for Leaky Bucket Configuration 1
Address: 34H
Type: Read / Write
Default Value: XXXXXX01
Bit Name Description
7 - 2 - Reserved.
1 - 0 DECAY_RATE_0_DATA[1:0]
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
Address: 35H
Type: Read / Write
Default Value: 00000110
Bit Name Description
7 - 0 UPPER_THRESHOLD_1_DATA[7:0] These bits set an upper thre shold for the internal leaky buc ket accumulator. When the num ber of the accumu-
lated events is above this threshold, a no-activity alarm is raised.
Address: 36H
Type: Read / Write
Default Value: 00000100
Bit Name Description
7 - 0 LOWER_THRESHOLD_1_DATA[7:0] These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated
events is below this threshold, the no-activity alarm is cleared.
76543210
------
DECAY_RATE_
0_DATA1 DECAY_RATE_
0_DATA0
76543210
UPPER_-
THRESH-
OLD_1_DATA7
UPPER_-
THRESH-
OLD_1_DATA6
UPPER_-
THRESH-
OLD_1_DATA5
UPPER_-
THRESH-
OLD_1_DATA4
UPPER_-
THRESH-
OLD_1_DATA3
UPPER_-
THRESH-
OLD_1_DATA2
UPPER_-
THRESH-
OLD_1_DATA1
UPPER_-
THRESH-
OLD_1_DATA0
76543210
LOWER_-
THRESH-
OLD_1_DATA7
LOWER_-
THRESH-
OLD_1_DATA6
LOWER_-
THRESH-
OLD_1_DATA5
LOWER_-
THRESH-
OLD_1_DATA4
LOWER_-
THRESH-
OLD_1_DATA3
LOWER_-
THRESH-
OLD_1_DATA2
LOWER_-
THRESH-
OLD_1_DATA1
LOWER_-
THRESH-
OLD_1_DATA0
IDT82V32021 EBU WAN PLL
Programming Informatio n 68 Ap ril 24, 2015
BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1
DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration 1
UPPER_THRESHOLD_2_CNFG - Upper Threshold for Leaky Bucket Configuration 2
Address: 37H
Type: Read / Write
Default Value: 00001000
Bit Name Description
7 - 0 BUCKET_SIZE_1_DATA[7:0] These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach
the bucket size, the accumulator will stop increasing even if further events are detected.
Address: 38H
Type: Read / Write
Default Value: XXXXXX01
Bit Name Description
7 - 2 - Reserved.
1 - 0 DECAY_RATE_1_DATA[1:0]
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
Address: 39H
Type: Read / Write
Default Value: 00000110
Bit Name Description
7 - 0 UPPER_THRESHOLD_2_DATA[7:0] The se bits set an u pper thresho ld for the int ernal leak y bucket acc umulator. When the number of the accumu-
lated events is above this threshold, a no-activity alarm is raised.
76543210
BUCKET_-
SIZE_1_DATA7 BUCKET_-
SIZE_1_DATA6 BUCKET_-
SIZE_1_DATA5 BUCKET_-
SIZE_1_DATA4 BUCKET_-
SIZE_1_DATA3 BUCKET_-
SIZE_1_DATA2 BUCKET_-
SIZE_1_DATA1 BUCKET_-
SIZE_1_DATA0
76543210
------
DECAY_RATE_
1_DATA1 DECAY_RATE_
1_DATA0
76543210
UPPER_-
THRESH-
OLD_2_DATA7
UPPER_-
THRESH-
OLD_2_DATA6
UPPER_-
THRESH-
OLD_2_DATA5
UPPER_-
THRESH-
OLD_2_DATA4
UPPER_-
THRESH-
OLD_2_DATA3
UPPER_-
THRESH-
OLD_2_DATA2
UPPER_-
THRESH-
OLD_2_DATA1
UPPER_-
THRESH-
OLD_2_DATA0
IDT82V32021 EBU WAN PLL
Programming Informatio n 69 Ap ril 24, 2015
LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2
BUCKET_SIZE_2_CNFG - Bucket Size for Leaky Bucket Configuration 2
DECAY_RATE_2_CNFG - Decay Rate for Leaky Bucket Configuration 2
Address: 3AH
Type: Read / Write
Default Value: 00000100
Bit Name Description
7 - 0 LOWER_THRESHOLD_2_DATA[7:0] The se bits set a lower threshold for the intern al leaky bucket accumulator. When the number of the accumu-
lated events is below this threshold, the no-activity alarm is cleared.
Address: 3BH
Type: Read / Write
Default Value: 00001000
Bit Name Description
7 - 0 BUCKET_SIZE_2_DATA[7:0] These bits set a bucket size for th e internal leaky bucket a ccumulator. If the number of the accumul ated events reach
the bucket size, the accumulator will stop increasing even if further events are detected.
Address: 3CH
Type: Read / Write
Default Value: XXXXXX01
Bit Name Description
7 - 2 - Reserved.
1 - 0 DECAY_RATE_2_DATA[1:0]
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
76543210
LOWER_-
THRESH-
OLD_2_DATA7
LOWER_-
THRESH-
OLD_2_DATA6
LOWER_-
THRESH-
OLD_2_DATA5
LOWER_-
THRESH-
OLD_2_DATA4
LOWER_-
THRESH-
OLD_2_DATA3
LOWER_-
THRESH-
OLD_2_DATA2
LOWER_-
THRESH-
OLD_2_DATA1
LOWER_-
THRESH-
OLD_2_DATA0
76543210
BUCKET_-
SIZE_2_DATA7 BUCKET_-
SIZE_2_DATA6 BUCKET_-
SIZE_2_DATA5 BUCKET_-
SIZE_2_DATA4 BUCKET_-
SIZE_2_DATA3 BUCKET_-
SIZE_2_DATA2 BUCKET_-
SIZE_2_DATA1 BUCKET_-
SIZE_2_DATA0
76543210
------
DECAY_RATE_
2_DATA1 DECAY_RATE_
2_DATA0
IDT82V32021 EBU WAN PLL
Programming Informatio n 70 Ap ril 24, 2015
UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3
LOWER_THRESHOLD_3_CNFG - Lower Threshold for Leaky Bucket Configuration 3
BUCKET_SIZE_3_CNFG - Bucket Size for Leaky Bucket Configuration 3
Address: 3DH
Type: Read / Write
Default Value: 00000110
Bit Name Description
7 - 0 UPPER_THRESHOLD_3_DATA[7:0] The se bits set an upper th reshold for the in ternal le aky bu cket ac cumula tor. When the number of the accumu-
lated events is above this threshold, a no-activity alarm is raised.
Address: 3EH
Type: Read / Write
Default Value: 00000100
Bit Name Description
7 - 0 LOWER_THRESHOLD_3_DATA[7:0] These bits set a lower threshold for the internal leaky b ucket accumulator. When the nu mber of the accumu-
lated events is below this threshold, the no-activity alarm is cleared.
Address: 3FH
Type: Read / Write
Default Value: 00001000
Bit Name Description
7 - 0 BUCKET_SIZE_3_DATA[7:0] These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach
the bucket size, the accumulator will stop increasing even if further events are detected.
76543210
UPPER_-
THRESH-
OLD_3_DATA7
UPPER_-
THRESH-
OLD_3_DATA6
UPPER_-
THRESH-
OLD_3_DATA5
UPPER_-
THRESH-
OLD_3_DATA4
UPPER_-
THRESH-
OLD_3_DATA3
UPPER_-
THRESH-
OLD_3_DATA2
UPPER_-
THRESH-
OLD_3_DATA1
UPPER_-
THRESH-
OLD_3_DATA0
76543210
LOWER_-
THRESH-
OLD_3_DATA7
LOWER_-
THRESH-
OLD_3_DATA6
LOWER_-
THRESH-
OLD_3_DATA5
LOWER_-
THRESH-
OLD_3_DATA4
LOWER_-
THRESH-
OLD_3_DATA3
LOWER_-
THRESH-
OLD_3_DATA2
LOWER_-
THRESH-
OLD_3_DATA1
LOWER_-
THRESH-
OLD_3_DATA0
76543210
BUCKET_-
SIZE_3_DATA7 BUCKET_-
SIZE_3_DATA6 BUCKET_-
SIZE_3_DATA5 BUCKET_-
SIZE_3_DATA4 BUCKET_-
SIZE_3_DATA3 BUCKET_-
SIZE_3_DATA2 BUCKET_-
SIZE_3_DATA1 BUCKET_-
SIZE_3_DATA0
IDT82V32021 EBU WAN PLL
Programming Informatio n 71 Ap ril 24, 2015
DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3
IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection
IN_FREQ_READ_STS - Input Clock Frequency Read Value
Address: 40H
Type: Read / Write
Default Value: XXXXXX01
Bit Name Description
7 - 2 - Reserved.
1 - 0 DECAY_RATE_3_DATA[1:0]
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
Address: 41H
Type: Read / Write
Default Value: XXXX0000
Bit Name Description
7 - 4 - Reserved.
3 - 0 IN_FREQ_READ_CH[3:0]
These bits select an input clock, the frequency of which with respect to the reference clock can be read.
0000: Reserved. (defa ult)
0001, 0010: Reserved.
0011: IN1 _CMOS.
0100: IN2_CMOS.
0101 ~ 1111: Reserved.
Address: 42H
Type: Read
Default Value: 00000000
Bit Name Description
7 - 0 IN_FREQ_VALUE[7:0]
These bits represent a 2’s complement signed integer. If the value is multiplied by the value in the FREQ_MON_FAC-
TOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the referen ce clock in ppm will be gotten. The
input clock is selected by the IN_FREQ_READ_CH[3:0] bits (b3~0, 41H).
The value in these bits is updated every 16 seconds, starting when an input clock is selected.
76543210
------
DECAY_RATE_
3_DATA1 DECAY_RATE_
3_DATA0
7654 3 2 1 0
----
IN_FRE-
Q_READ_CH3 IN_FRE-
Q_READ_CH2 IN_FRE-
Q_READ_CH1 IN_FRE-
Q_READ_CH0
76543210
IN_FREQ_VAL-
UE7 IN_FREQ_VAL-
UE6 IN_FREQ_VAL-
UE5 IN_FREQ_VAL-
UE4 IN_FREQ_VAL-
UE3 IN_FREQ_VAL-
UE2 IN_FREQ_VAL-
UE1 IN_FREQ_VAL-
UE0
IDT82V32021 EBU WAN PLL
Programming Informatio n 72 Ap ril 24, 2015
IN1_IN2_CMOS_STS - CMOS Input Clock 1 & 2 Status
Address: 44H
Type: Read
Default Value: X110X110
Bit Name Description
7 - Reserved.
6 IN2_CMOS_FREQ_HARD_ALARM This bit indicates whether IN2_CMOS is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
5 IN2_CMOS_NO_ACTIVITY_ALARM This bit indicates whether IN2_CMOS is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
4 IN2_CMOS_PH_LOCK_ALARM
This bit indicates whether IN2_CMOS is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleare d by wri t ing ‘1’ to this bit; if the PH_ ALARM_-
TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0 ] (b5~0, 08H) X MUL-
TI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
3 - Reserved.
2 IN1_CMOS_FREQ_HARD_ALARM This bit indicates whether IN1_CMOS is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
1 IN1_CMOS_NO_ACTIVITY_ALARM This bit indicates whether IN1_CMOS is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
0 IN1_CMOS_PH_LOCK_ALARM
This bit indicates whether IN1_CMOS is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleare d by wri t ing ‘1’ to this bit; if the PH_ ALARM_-
TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0 ] (b5~0, 08H) X MUL-
TI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
76543210
-
IN2_CMOS_-
FRE-
Q_HARD_ALAR
M
IN2_C-
MOS_NO_AC-
TIVITY_ALARM
IN2_C-
MOS_PH_LOCK
_ALARM -
IN1_CMOS_-
FRE-
Q_HARD_ALAR
M
IN1_C-
MOS_NO_AC-
TIVITY_ALARM
IN1_C-
MOS_PH_LOCK
_ALARM
IDT82V32021 EBU WAN PLL
Programming Informatio n 73 Ap ril 24, 2015
6.2.5 T0 DPLL INPUT CLOCK SELECTION REGISTERS
INPUT_VALID1_STS - Input Clocks Validity 1
PRIORITY_TABLE1_STS - Priority Status 1
Address: 4AH
Type: Read
Default Value: XXXX00XX
Bit Name Description
7 - 4 - Reserved.
3 - 2 INn_CMOS This bit indicates the validity of the corresponding INn_CMOS. Here n is 2 or 1.
0: Invalid. (default)
1: Valid.
1 - 0 - Reserved.
Address: 4EH
Type: Read
Default Value: 00000000
Bit Name Description
7 - 4 HIGHEST_PRIORITY_VALIDATED[3:0]
These bits indicate a qualified input clock with the highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101 ~ 1111: Reserved.
3 - 0 CURRENTLY_SELECTED_INPUT[3:0]
These bits indicate the T0 selected input clock.
0000: No input clock is selected. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101 ~ 1111: Reserved.
76543210
----IN2_CMOSIN1_CMOS--
76543210
HIGHEST_PRI-
ORITY_VALI-
DATED3
HIGHEST_PRI-
ORITY_VALI-
DATED2
HIGHEST_PRI-
ORITY_VALI-
DATED1
HIGHEST_PRI-
ORITY_VALI-
DATED0
CURRENT-
LY_SELECT-
ED_INPUT3
CURRENT-
LY_SELECT-
ED_INPUT2
CURRENT-
LY_SELECT-
ED_INPUT1
CURRENT-
LY_SELECT-
ED_INPUT0
IDT82V32021 EBU WAN PLL
Programming Informatio n 74 Ap ril 24, 2015
PRIORITY_TABLE2_STS - Priority Status 2
T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration
Address: 4FH
Type: Read
Default Value: XXXX0000
Bit Name Description
7 - 4 - Reserved.
3 - 0 SECOND_HIGHEST_PRIORITY_VALIDATED[3:0]
These bits indicate a qualified input clock with the second highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101 ~ 1111: Reserved.
Address: 50H
Type: Read / Write
Default Value: XXXX0000
Bit Name Description
7 - 4 - Reserved.
3 - 0 T0_INPUT_SEL[3:0]
This bit determines T0 input clock selection. It is valid only when the EXT_SW bit (b4, 0BH) is ‘0’.
0000: Automatic selection. (default)
0001, 0010: Reserved.
0011: Forced selection - IN1_CMOS is selected.
0100: Forced selection - IN2_CMOS is selected.
0101 ~ 1111: Reserved.
76543210
----
SEC-
OND_HIGH-
EST_PRIORITY
_VALIDATED3
SEC-
OND_HIGH-
EST_PRIORITY
_VALIDATED2
SEC-
OND_HIGH-
EST_PRIORITY
_VALIDATED1
SEC-
OND_HIGH-
EST_PRIORITY
_VALIDATED0
7654 3 2 1 0
- - - - T0_INPUT_SEL3 T0_INPUT_SEL2 T0_INPUT_SEL1 T0_INPUT_SEL0
IDT82V32021 EBU WAN PLL
Programming Informatio n 75 Ap ril 24, 2015
6.2.6 T0 DPLL STATE MACHINE CONTROL REGISTERS
OPERATING_STS - DPLL Operating Status
Address: 52H
Type: Read
Default Value: 1X0X0001
Bit Name Description
7 EX_SYNC_ALARM_MON This bit indicates whether the selected frame sync input signal is in external sync alarm status.
0: No external sync alarm.
1: In external sync alarm status. (default)
6 - Reserved.
5 T0_DPLL_SOFT_FREQ_ALARM This bit indicates whether the T0 DPLL is in soft alarm status.
0: No T0 DPLL soft alarm. (default)
1: In T0 DPLL soft alarm status.
4 - Reserved.
3 T0_DPLL_LOCK This bit indicates the T0 DPLL locking status.
0: Unlocked. (default)
1: Locked.
2 - 0 T0_DPLL_OPERATING_MODE[2:0]
These bits indicate the current operating mode of T0 DPLL.
000: Reserved.
001: Free-Run. (default)
010: Holdover.
011: Reserved.
100: Locked.
101: Pre-Locked2.
110: Pre-Locked.
111: Lost-Phase.
76543210
EX_SYN-
C_ALARM_MO
N-T0_DPLL_-
SOFT_FRE-
Q_ALARM -T0_D-
PLL_LOCK
T0_DPLL_OP-
ERATING_-
MODE2
T0_DPLL_OP-
ERATING_-
MODE1
T0_DPLL_OP-
ERATING_-
MODE0
IDT82V32021 EBU WAN PLL
Programming Informatio n 76 Ap ril 24, 2015
T0_OPERATING_MODE_CNFG - T0 DPLL Operating Mode Configuration
Address: 53H
Type: Read / Write
Default Value: XXXXX000
Bit Name Description
7 - 3 - Reserved.
2 - 0 T0_OPERATING_MODE[2:0]
These bits control the T0 DPLL operating mode.
000: Automatic. (default)
001: Forced - Free-Run.
010: Forced - Holdover.
011: Reserved.
100: Forced - Locked.
101: Forced - Pre-Locked2.
110: Forced - Pre-Locked.
111: Forced - Lost-Phase.
76543 2 1 0
-----T0_OPERATING_MODE2 T0_OPERATING_MODE1 T0_OPERATING_MODE0
IDT82V32021 EBU WAN PLL
Programming Informatio n 77 Ap ril 24, 2015
6.2.7 T0 DPLL & T0 APLL CONFIGURATION REGISTERS
T0_DPLL_APLL_PATH_CNFG - T0 DPLL & APLL Path Configuration
Address: 55H
Type: Read / Write
Default Value: 00000X0X
Bit Name Description
7 - 4 T0_APLL_PATH[3:0]
These bits select an input to the T0 APLL.
0000: The output of T0 DPLL 77.76 MHz path. (default)
0001: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0010: The output of T0 DPLL 16E1/16T1 path.
0011: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
0100 ~ 1111: Reserved.
3 - 2 T0_GSM_OBSAI_16E1_16T1_SEL[1:0]
These bits select an output clock from the T0 DPLL GSM/OBSAI/16E1/16T1 path.
00: 16E1.
01: 16T1.
10: GSM.
11: OBSAI.
The default value of the T0_GSM_OBSAI_16E1_16T1_SEL0 bit is determined by the SONET/SDH pin
during reset.
1 - 0 T0_12E1_24T1_E3_T3_SEL[1:0]
These bits select an output clock from the T0 DPLL 12E1/24T1/E3/T3 path.
00: 12E1.
01: 24T1.
10: E3.
11: T3.
The default value of the T0_12E1_24T1_E3_T3_SEL0 bit is determined by the SONET/SDH pin during
reset.
7654 3 2 1 0
T0_APLL_-
PATH3 T0_APLL_-
PATH2 T0_APLL_-
PATH1 T0_APLL_-
PATH0
T0_GSM_OBSA-
I_16E1_16T1_-
SEL1
T0_GSM_OBSA-
I_16E1_16T1_-
SEL0
T0_12E1_24T1_
E3_T3_SEL1 T0_12E1_24T1_
E3_T3_SEL0
IDT82V32021 EBU WAN PLL
Programming Informatio n 78 Ap ril 24, 2015
T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Bandwidth & Damping Factor Configuration
Address: 56H
Type: Read / Write
Default Value: 01101111
Bit Name Description
7 - 5 T0_DPLL_START_DAMPING[2:0]
These bits set the starting damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
011: 5. (default)
100: 10.
101: 20.
110, 111: Reserved.
4 - 0 T0_DPLL_START_BW[4:0]
These bits set the starting bandwidth for T0 DPLL.
00XXX: Reserved.
01000 ~ 01010 : Reserved.
01011: 1.2 Hz.
01100: 2.5 Hz.
01101: 4 Hz.
01110: 8 Hz.
01111: 18 Hz. (default)
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 111 11: Reserved.
76543210
T0_D-
PLL_START_D
AMPING2
T0_D-
PLL_START_D
AMPING1
T0_D-
PLL_START_D
AMPING0
T0_D-
PLL_START_B
W4
T0_D-
PLL_START_B
W3
T0_D-
PLL_START_B
W2
T0_D-
PLL_START_B
W1
T0_D-
PLL_START_B
W0
IDT82V32021 EBU WAN PLL
Programming Informatio n 79 Ap ril 24, 2015
T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration
Address: 57H
Type: Read / Write
Default Value: 01101111
Bit Name Description
7 - 5 T0_DPLL_ACQ_DAMPING[2:0]
These bits set the acquisition damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
011: 5. (default)
100: 10.
101: 20.
110, 111: Reserved.
4 - 0 T0_DPLL_ACQ_BW[4:0]
These bits set the acquisition bandwidth for T0 DPLL.
00XXX ~ 01010 : Reserved.
01011: 1.2 Hz.
01100: 2.5 Hz.
01101: 4 Hz.
01110: 8 Hz.
01111: 18 Hz. (default)
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 111 11: Reserved.
76543210
T0_DPLL_AC-
Q_DAMPING2 T0_DPLL_AC-
Q_DAMPING1 T0_DPLL_AC-
Q_DAMPING0 T0_DPLL_AC-
Q_BW4 T0_DPLL_AC-
Q_BW3 T0_DPLL_AC-
Q_BW2 T0_DPLL_AC-
Q_BW1 T0_DPLL_AC-
Q_BW0
IDT82V32021 EBU WAN PLL
Programming Informatio n 80 Ap ril 24, 2015
T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration
T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration
Address: 58H
Type: Read / Write
Default Value: 01101111
Bit Name Description
7 - 5 T0_DPLL_LOCKED_DAMPING[2:0]
These bits set the locked damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
011: 5. (default)
100: 10.
101: 20.
110, 111: Reserved.
4 - 0 T0_DPLL_LOCKED_BW[4:0]
These bits set the locked bandwidth for T0 DPLL.
00XXX ~ 01010 : Reserved.
01011: 1.2 Hz. (default)
01100: 2.5 Hz.
01101: 4 Hz.
01110: 8 Hz.
01111: 18 Hz.
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 111 11: Reserved.
Address: 59H
Type: Read / Write
Default Value: 1XXX1XXX
Bit Name Description
7 AUTO_BW_SEL
This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL.
0: The starting and acquisition bandwidths / damping factors are not used. Only the locked bandwidth / damping factor is used
regardless of the T0 DPLL locking stage.
1: The starting, acquisition or locked bandwidth / damping factor is used automatically depending on different T0 DPLL locking
stages. (default)
6 - 4 - Reserved.
3 T0_LIMT This bit determines whether the integral path value is frozen when the T0 DPLL hard limit is reached.
0: Not frozen.
1: Frozen. It will minimize the subsequent overshoot when T0 DPLL is pulling in. (default)
2 - 0 - Reserved.
7 6 543210
T0_D-
PLL_LOCKED_
DAMPING2
T0_D-
PLL_LOCKED_
DAMPING1
T0_D-
PLL_LOCKED_
DAMPING0
T0_D-
PLL_LOCKED_
BW4
T0_D-
PLL_LOCKED_
BW3
T0_D-
PLL_LOCKED_
BW2
T0_D-
PLL_LOCKED_
BW1
T0_D-
PLL_LOCKED_
BW0
7 6 543210
AUTO_BW_SEL - - - T0_LIMT - - -
IDT82V32021 EBU WAN PLL
Programming Informatio n 81 Ap ril 24, 2015
PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration
Address: 5AH
Type: Read / Write
Default Value: 10000101
Bit Name Description
7 COARSE_PH_LOS_LIMT_EN This bit controls whether the occurrence of the coarse phase loss will result in the T0 DPLL unlocked.
0: Disabled.
1: Enabled. (default)
6 WIDE_EN Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH).
5 MULTI_PH_APP
This bit determines whether the PFD output of T0 DPLL is limited to ±1 UI or is limited to the coarse phase limit.
0: Limited to ±1 UI. (default)
1: Limited to the coarse phase limit. When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse phase limit depends
on the MULTI_PH_8K_4K_2 K_EN bit, the WIDE_ EN bit an d the PH_LOS_COARSE_LIMT[3:0] bits; when the sel ected input
clock is of other frequencies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the
PH_LOS_COARSE_LIMT[3:0] bits. Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH) for details.
4 MULTI_PH_8K_4K_2K_EN
This bit, together with the WIDE_EN bit (b6, 5AH) and the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH), determines the
coarse phase limit when the selected input clock is of 2 kHz, 4 kHz or 8 kHz. When the selected input clock is of other frequen-
cies but 2 kHz, 4 kHz and 8 kHz , the coarse phase lim it de pends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0 ]
bits.
3 - 0 PH_LOS_COARSE_LIMT[3:0]
These bit set the coarse phase limit. The limit is used only in some cases. Refer to the description of the MUL-
TI_PH_8K_4K_2K_EN bit (b4, 5AH).
0000: ±1 UI.
0001: ±3 UI.
0010: ±7 UI.
0011: ±15 UI.
0100: ±31 UI.
0101: ±63 UI. (default)
0110: ±127 UI.
0111: ±255 UI.
1000: ±511 UI.
1001: ±1023 UI.
1010-1111: Reserved.
7 6 543210
COARSE_PH_L
OS_LIMT_EN WIDE_EN MULTI_PH_APP MUL-
TI_PH_8K_4K_
2K_EN
PH_LOS_-
COARSE_LIMT
3
PH_LOS_-
COARSE_LIMT
2
PH_LOS_-
COARSE_LIMT
1
PH_LOS_-
COARSE_LIMT
0
Selected Input Clock MULTI_PH_8K_4K_2K_EN WIDE_EN Coarse Phase Limit
2 kHz, 4 kHz or 8 kHz
0 don’t -care ±1 UI
10±1 UI
1set by the PH_LOS_COARSE_LIMT[3:0] bits
(b3~0, 5AH).
other than 2 kHz, 4
kHz and 8 kHz don’t-care 0±1 UI
1set by the PH_LOS_COARSE_LIMT[3:0] bits
(b3~0, 5AH).
IDT82V32021 EBU WAN PLL
Programming Informatio n 82 Ap ril 24, 2015
PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration
Address: 5BH
Type: Read / Write
Default Value: 10XXX010
Bit Name Description
7 FINE_PH_LOS_LIMT_EN This bit controls whether the occurrence of the fine phase loss will result in the T0 DPLL unlocked.
0: Disabled.
1: Enabled. (default)
6 FAST_LOS_SW
This bit controls whether the occurrence of the fast loss will result in the T0 DPLL unlocked.
0: Does not result in the T0 DPLL unlocked. T0 DPLL will enter Temp-Holdover mode automatically. (default)
1: Results in the T0 DPLL unl ocked. T0 DPLL will enter Lost-Phase m ode if the T0 DPLL operating mode is switc hed
automatically.
5 - 3 - Reserved.
2 - 0 PH_LOS_FINE_LIMT[2:0]
These bits set a fine phase limit.
000: 0.
001: ± (45 ° ~ 90 °).
010: ± (90 ° ~ 180 °). (default)
011: ± (180 ° ~ 360 °).
100: ± (20 ns ~ 25 ns).
101: ± (60 ns ~ 65 ns).
110: ± (120 ns ~ 125 ns).
111: ± (950 ns ~ 955 ns).
7 6 543210
FINE_PH_LOS_
LIMT_EN FAST_LOS_SW - - - PH_LOS_FINE
_LIMT2 PH_LOS_FINE
_LIMT1 PH_LOS_FINE
_LIMT0
IDT82V32021 EBU WAN PLL
Programming Informatio n 83 Ap ril 24, 2015
T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration
T0_HOLDOVER_FREQ[7:0]_CNFG - T0 DPLL Holdover Frequency Configuration 1
Address: 5CH
Type: Read / Write
Default Value: 010001XX
Bit Name Description
7 MAN_HOLDOVER Refer to the description of the FAST_AVG bit (b5, 5CH).
6 AUTO_AVG Refer to the description of the FAST_AVG bit (b5, 5CH).
5 FAST_AVG
This bit, together with the AUTO_AVG bit (b6, 5CH) and the MAN_HOLDOVER bit (b7, 5CH), determines a fre-
quency offset acquiring method in T0 DPLL Holdover Mode.
4 READ_AVG
This bit controls the holdover frequency offset reading, which is read from the T0_HOLDOVER_FREQ[23:0] bits
(5FH ~ 5DH).
0: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is equal to the one written to them.
(default)
1: The value rea d from t he T0_HOL DOVER_FREQ[23:0] bits (5 FH ~ 5DH) is not e qual to the one writ ten to them.
The value is acqui red by Automat ic Slow Averaged metho d if the FAST_AVG bit (b5, 5CH) i s ‘0’; or is acqui red by
Automatic Fast Averaged method if the FAST_AVG bit (b5, 5CH) is ‘1’.
3 - 2 TEMP_HOLDOVER_MODE[1:0]
These bits determine the frequency offset acquiring method in T0 DPLL Temp-Holdover Mode.
00: The method is the same as that used in T0 DPLL Holdover mode.
01: Automatic Instantaneous. (default)
10: Automatic Fast Averaged.
11: Automatic Slow Averaged.
1 - 0 - Reserved.
Address: 5DH
Type: Read / Write
Default Value: 00000000
Bit Name Description
7 - 0 T0_HOLDOVER_FREQ[7:0] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH).
7 6 543210
MAN_HOLD-
OVER AUTO_AVG FAST_AVG READ_AVG TEMP_HOLD-
OVER_MODE1 TEMP_HOLD-
OVER_MODE0 --
MAN_HOLDOVER AUTO_AVG FAST_AVG Frequency Offset Acquiring Method
00 don’t-care Automatic Instantaneous
10 Automatic Slow Averaged (default)
1 Automatic Fast Averaged
1 don’t-care Manual
7 6 543210
T0_HOLD-
OVER_FREQ7 T0_HOLD-
OVER_FREQ6 T0_HOLD-
OVER_FREQ5 T0_HOLD-
OVER_FREQ4 T0_HOLD-
OVER_FREQ3 T0_HOLD-
OVER_FREQ2 T0_HOLD-
OVER_FREQ1 T0_HOLD-
OVER_FREQ0
IDT82V32021 EBU WAN PLL
Programming Informatio n 84 Ap ril 24, 2015
T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2
T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Configuration 3
CURRENT_DPLL_FREQ[7:0]_STS - DPLL Current Frequency Status 1
Address: 5EH
Type: Read / Write
Default Value: 00000000
Bit Name Description
7 - 0 T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH).
Address: 5FH
Type: Read / Write
Default Value: 00000000
Bit Name Description
7 - 0 T0_HOLDOVER_FREQ[23:16]
The T0_HOLDOVER_FREQ[23:0] bits represent a 2’s complement signed integer.
In T0 DPLL Holdover mode, the value written to these bits multiplied by 0.000011 is the frequency offset set manu-
ally; the valu e read from these bits multiplied by 0.000011 is th e frequency offset automaticall y slow or fast aver-
aged or manually set, as determined by the READ_AVG bit (b4, 5CH) and the FAST_AVG bit (b5, 5CH).
Address: 62H
Type: Read
Default Value: 00000000
Bit Name Description
7 - 0 CURRENT_DPLL_FREQ[7:0] Refer to the descri ptio n of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H).
7 6 543210
T0_HOLD-
OVER_FREQ15 T0_HOLD-
OVER_FREQ14 T0_HOLD-
OVER_FREQ13
T0_HOLD-
OVER_-
FREQ12
T0_HOLD-
OVER_FREQ11
T0_HOLD-
OVER_-
FREQ10
T0_HOLD-
OVER_FREQ9 T0_HOLD-
OVER_FREQ8
7 6 543210
T0_HOLD-
OVER_FREQ23 T0_HOLD-
OVER_FREQ22 T0_HOLD-
OVER_FREQ21
T0_HOLD-
OVER_-
FREQ20
T0_HOLD-
OVER_-
FREQ19
T0_HOLD-
OVER_-
FREQ18
T0_HOLD-
OVER_-
FREQ17
T0_HOLD-
OVER_-
FREQ16
76543210
CURRENT_D-
PLL_FREQ7 CURRENT_D-
PLL_FREQ6 CURRENT_D-
PLL_FREQ5 CURRENT_D-
PLL_FREQ4 CURRENT_D-
PLL_FREQ3 CURRENT_D-
PLL_FREQ2 CURRENT_D-
PLL_FREQ1 CURRENT_D-
PLL_FREQ0
IDT82V32021 EBU WAN PLL
Programming Informatio n 85 Ap ril 24, 2015
CURRENT_DPLL_FREQ[15:8]_STS - DPLL Current Frequency Status 2
CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3
DPLL_FREQ_SOF T_LIMIT_CNFG - DPLL Soft Limit Configuration
Address: 63H
Type: Read
Default Value: 00000000
Bit Name Description
7 - 0 CURRENT_DPLL_FREQ[15:8] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H).
Address: 64H
Type: Read
Default Value: 00000000
Bit Name Description
7 - 0 CURRENT_DPLL_FREQ[23:16] The CURRENT_DPLL_FREQ[23:0] bits represent a 2’s complement signed integer . If the value in these bits is mul-
tiplied by 0.000011, the cu rrent fre quency offset of the T0 DPLL o utput in ppm wi th respe ct to the master c lock will
be gotten.
Address: 65H
Type: Read / Write
Default Value: 10001100
Bit Name Description
7 FREQ_LIMT_PH_LOS This bit determines whether the T0 DPLL in hard alarm status will result in it unlocked.
0: Disabled.
1: Enabled. (default)
6 - 0 DPLL_FREQ_SOFT_LIMT[6:0] These bits represent an unsigned integer . If the value is multiplied by 0.724, the DPLL soft limit for T0 path in ppm will
be gotten.
The DPLL soft limit is symmetrical about zero.
76543210
CURRENT_D-
PLL_FREQ15 CURRENT_D-
PLL_FREQ14 CURRENT_D-
PLL_FREQ13 CURRENT_D-
PLL_FREQ12 CURRENT_D-
PLL_FREQ11 CURRENT_D-
PLL_FREQ10 CURRENT_D-
PLL_FREQ9 CURRENT_D-
PLL_FREQ8
76543210
CURRENT_D-
PLL_FREQ23 CURRENT_D-
PLL_FREQ22 CURRENT_D-
PLL_FREQ21 CURRENT_D-
PLL_FREQ20 CURRENT_D-
PLL_FREQ19 CURRENT_D-
PLL_FREQ18 CURRENT_D-
PLL_FREQ17 CURRENT_D-
PLL_FREQ16
76543210
FRE-
Q_LIMT_PH_LO
S
DPLL_FREQ_-
SOFT_LIMT6 DPLL_FREQ_-
SOFT_LIMT5 DPLL_FREQ_-
SOFT_LIMT4 DPLL_FREQ_-
SOFT_LIMT3 DPLL_FREQ_-
SOFT_LIMT2 DPLL_FREQ_-
SOFT_LIMT1 DPLL_FREQ_-
SOFT_LIMT0
IDT82V32021 EBU WAN PLL
Programming Informatio n 86 Ap ril 24, 2015
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL Hard Limit Configuration 1
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2
CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1
Address: 66H
Type: Read / Write
Default Value: 10101011
Bit Name Description
7 - 0 DPLL_FREQ_HARD_LIMT[7:0] Refer to the description of the DPLL_FREQ_HARD_LIMT[15:8] bits (b7~0, 67H).
Address: 67H
Type: Read / Write
Default Value: 00011001
Bit Name Description
7 - 0 DPLL_FREQ_HARD_LIMT[15:8] The DPLL_FREQ_HARD_LIMT[15:0] bits repres ent an un sig ned i nteg er. If the value is multiplied by 0.0014 , the
DPLL hard limit for T0 path in ppm will be gotten.
The DPLL hard limit is symmetrical about zero.
Address: 68H
Type: Read
Default Value: 00000000
Bit Name Description
7 - 0 CURRENT_PH_DATA[7:0] Refer to the description of the CURRENT_PH_DATA[15:8] bits (b7~0, 69H).
76543210
DPLL_FRE-
Q_HARD_LIMT
7
DPLL_FRE-
Q_HARD_LIMT
6
DPLL_FRE-
Q_HARD_LIMT
5
DPLL_FRE-
Q_HARD_LIMT
4
DPLL_FRE-
Q_HARD_LIMT
3
DPLL_FRE-
Q_HARD_LIMT
2
DPLL_FRE-
Q_HARD_LIMT
1
DPLL_FRE-
Q_HARD_LIMT
0
76543210
DPLL_FRE-
Q_HARD_LIMT
15
DPLL_FRE-
Q_HARD_LIMT
14
DPLL_FRE-
Q_HARD_LIMT
13
DPLL_FRE-
Q_HARD_LIMT
12
DPLL_FRE-
Q_HARD_LIMT
11
DPLL_FRE-
Q_HARD_LIMT
10
DPLL_FRE-
Q_HARD_LIMT
9
DPLL_FRE-
Q_HARD_LIMT
8
76543210
CUR-
RENT_PH_DA-
TA7
CUR-
RENT_PH_DA-
TA6
CUR-
RENT_PH_DA-
TA5
CUR-
RENT_PH_DA-
TA4
CUR-
RENT_PH_DA-
TA3
CUR-
RENT_PH_DA-
TA2
CUR-
RENT_PH_DA-
TA1
CUR-
RENT_PH_DA-
TA0
IDT82V32021 EBU WAN PLL
Programming Informatio n 87 Ap ril 24, 2015
CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2
T0_APLL_BW_CNFG - T0 APLL Bandwidth Configuration
Address: 69H
Type: Read
Default Value: 00000000
Bit Name Description
7 - 0 CURRENT_PH_DATA[15:8] The CURRENT_PH_DATA[15:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the
averaged phase error of the T0 DPLL feedback with respect to the selected input clock in ns will be gotten.
Address: 6AH
Type: Read / Write
Default Value: XX01XX01
Bit Name Description
7 - 6 - Reserved.
5 - 4 T0_APLL_BW[1:0]
These bits set the bandwidth for T0 APLL.
00: 100 kHz.
01: 500 kHz. (default)
10: 1 MHz.
11: 2 MHz.
3 - 0 - Reserved.
76543210
CUR-
RENT_PH_DA-
TA15
CUR-
RENT_PH_DA-
TA14
CUR-
RENT_PH_DA-
TA13
CUR-
RENT_PH_DA-
TA12
CUR-
RENT_PH_DA-
TA11
CUR-
RENT_PH_DA-
TA10
CUR-
RENT_PH_DA-
TA9
CUR-
RENT_PH_DA-
TA8
76543210
--T0_APLL_BW1T0_APLL_BW0----
IDT82V32021 EBU WAN PLL
Programming Informatio n 88 Ap ril 24, 2015
6.2.8 OUTPUT CONFIGURATION REGISTERS
OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration
OUT1_INV_CNFG - Output Clock 1 Invert Configuration
Address: 6DH
Type: Read / Write
Default Value: 00001000
Bit Name Description
7 - 4 OUT1_PATH_SEL[3:0]
These bits select an input to OUT1.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1111: Reserved.
3 - 0 OUT1_DIVIDER[3:0]
These bits select a division factor of the divider for OUT1.
The output frequency is determined by the division factor and the signal derived from T0 DPLL or T0 APLL output
(selected by the OUT1_P ATH_SEL[3:0] bits (b7~4, 6DH)). If the signal is derived from one of the T0 DPLL outputs, please
refer to Table 22 for the division fac tor s ele ction. If the signal is derive d from th e T0 APLL output, please refer to Table 23
for the division factor sel ecti on.
Address:73H
Type: Read / Write
Default Value: XXXXX0XX
Bit Name Description
7 - 3 - Reserved.
2OUT1_INV
This bit determines whether the output on OUT1 is inverted.
0: Not inverted. (default)
1: Inverted.
1 - 0 - Reserved.
76543210
OUT1_PATH_-
SEL3 OUT1_PATH_-
SEL2 OUT1_PATH_-
SEL1 OUT1_PATH_-
SEL0 OUT1_DIVID-
ER3 OUT1_DIVID-
ER2 OUT1_DIVID-
ER1 OUT1_DIVID-
ER0
76543210
-----OUT1_INV--
IDT82V32021 EBU WAN PLL
Programming Informatio n 89 Ap ril 24, 2015
FR_SYNC_CNFG - Frame Sync Output Configuration
Address:74H
Type: Read / Write
Default Value : 01X000 XX
Bit Name Description
7 IN_2K_4K_8K_INV
This bit determines whether the input clock is inverted before locked by the T0 DPLL when the input clock is 2 kHz, 4 kHz
or 8 kHz.
0: Not inverted. (default)
1: Inverted.
6 8K_EN This bit determines whether an 8 kHz signal is enabled to be output on FRSYNC_8K.
0: Disabled. FRSYNC_8K outputs low.
1: Enabled. (default)
5 - Reserved.
4 8K_PUL_POSITION
This bit is valid only when FRSYNC_8K output pulse; i.e., when one of the 8K_PUL bit (b2, 74H) is ‘1’ or when the
8K_PUL bit (b2, 74H) is ‘1’. It determines the pulse position referring to the standard 50:50 duty cycle.
0: Pulsed on the falling edge of the standard 50:50 duty cycle position. (default)
1: Pulsed on the rising edge of the standard 50:50 duty cycle position.
38K_INV
This bit determines whether the output on FRSYNC_8K is inverted.
0: Not inverted. (default)
1: Inverted.
2 8K_PUL This bit determines whether the output on FRSYNC_8K is 50:50 duty cycle or pulsed.
0: 50:50 duty cycle. (default)
1: Pulsed. The pulse width is defined by the period of the output on OUT1.
1 - 0 - Reserved.
76543210
IN_2K_4K_8K_-
INV 8K_EN - 8K_PUL_POSI-
TION 8K_INV 8K_PUL - -
IDT82V32021 EBU WAN PLL
Programming Informatio n 90 Ap ril 24, 2015
6.2.9 PBO & P HASE OFFSET CONTROL REGISTERS
PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration
Address:78H
Type: Read / Write
Default Value: 0X000110
Bit Name Description
7 IN_NOISE_WINDOW
This bit determines whether the input clock whose edge respect to the reference clock is outside ±5% is enabl ed to be
selected for T0 DPLL.
0: Disabled. (default)
1: Enabled.
6-Reserved.
5PH_MON_EN
This bit is valid only when the PH_MON_PBO_EN bit (b4, 78H) is ‘1’. It determines whether the Phase Transient Monitor
is enabled to monitor the phase-time changes on the T0 selected input clock.
0: Disabled. (default)
1: Enabled.
4 PH_MON_PBO_EN
This bit determines whether a PBO eve nt is triggered when the phase-time chang es on the T0 selected input clock are
greater than a programmable limit over an interval of less than 0.1 seconds with the PH_MON_EN bit being ‘1’. The limit
is programmed by the PH_TR_MON_LIMT[3:0] bits (b3~0, 78H).
0: Disabled. (default)
1: Enabled.
3 - 0 PH_TR_MON_LIMT[3:0] These bits represent an unsigned integer. The Phase Transient Monitor limit in ns can be calculated as follows:
Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156.
76543210
IN_NOISE_WIN
DOW - PH_MON_EN PH_MON_P-
BO_EN PH_TR_MON_L
IMT3 PH_TR_MON_L
IMT2 PH_TR_MON_L
IMT1 PH_TR_MON_L
IMT0
IDT82V32021 EBU WAN PLL
Programming Informatio n 91 Ap ril 24, 2015
6.2.10 SYNCHRONIZATION CONFIGURATION REGISTERS
SYNC_MONITOR_CNFG - Sync Monitor Configuration
SYNC_PHASE_CNFG - Sync Phase Configuration
Address:7CH
Type: Read / Write
Default Value: 00101011
Bit Name Description
7 SYNC_BYPASS
This bit selects one frame sync input signal to synchronize the frame sync output signal.
0: EX_SYNC1 is selected. (default)
1: When the T0 s elected input clock is IN1_CMOS, EX_SYNC1 is selected; when t he T0 selected input clo ck is IN2_C-
MOS, EX_SYNC2 is selected;when there is no T0 selected input clock, no frame sync input signal is selected.
6 - 4 SYNC_MON_LIMT[2:0]
These bits set the limit for the external sync alarm.
000: ±1 UI.
001: ±2 UI.
010: ±3 UI. (default)
011: ±4 UI.
100: ±5 UI.
101: ±6 UI.
110: ±7 UI.
111: ±8 UI.
3 - 0 - These bits must be set to ‘1011’.
Address:7DH
Type: Read / Write
Default Value: XXXX0000
Bit Name Description
7 - 4 - Reserved.
3 - 2 SYNC_PH2[1:0]
These bits set the sampling of EX_SYNC2 whe n EX_SYNC2 is enabled to s ynchronize the frame sy nc output signal . Nomi-
nally, the falling edge of EX_SYNC2 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
1 - 0 SYNC_PH1[1:0]
These bits set the sampling of EX_SYNC1 whe n EX_SYNC1 is enabled to s ynchronize the frame sy nc output signal . Nomi-
nally, the falling edge of EX_SYNC1 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
7 6 5 4 3210
SYNC_BYPASSSYNC_MON_LIMT2SYNC_MON_LIMT1SYNC_MON_LIMT0----
76543210
----SYNC_PH21SYNC_PH20SYNC_PH11SYNC_PH10
IDT82V32021 EBU WAN PLL
Thermal Managemen t 92 April 24, 2015
7 THERMAL MANAGEMENT
The device operates over the industry temperature range -40°C ~
+85°C. To ensure the functionality and reliability of the device, the maxi-
mum junction temperature Tjmax should not exceed 125°C. In some
applications, the device will consume more power and a thermal solution
should be provided to ensure the junction temperature Tj does not
exceed the Tjmax.
7.1 JUNCTION TEMPERATURE
Junction temperature Tj is the temperature of package typically at the
geographical center of the chip where the device's electrical circuits are.
It can be calculated as follows:
Equation 1: Tj = TA + P X
JA
Where:
JA = Junction-to-Ambient Thermal Resistance of the Package
Tj = Junction Temperature
TA = Ambient Temperature
P = Device Power Consumption
In order to calculate junction temperature, an appropriate JA must
be used. The JA is shown in Table 32:
Power consumption is the core power excluding the power dissipated
in the loads. Table 33 provides power consumption in special environ-
ments.
7.2 EXAMPLE OF JUNCTION TEMPERATURE
CALCULATION
Assume:
TA = 85°C
JA = 20.9 °C/W (VFQFPN/NL68 Soldered & when airfow rate is 0 m/
s)
P = 1.57W
The junction temperature Tj can be calculated as follows:
Tj = TA + P X
JA = 85°C + 1.57W X 20.9°C/W = 117.8°C
The junction temperature of 117.8°C is below the maximum junction
temperature of 125°C so no extra heat enhancement is required.
In some operation environments, the calculated junction temperature
might exceed the maximum junction temperature of 125°C and an exter-
nal thermal solution such as a heatsink is required.
7.3 HEATSINK EVALUATION
A heatsink is expanding the surface area of the device to which it is
attached. JA is now a combination of device case and heat-sink thermal
resistance, as the heat flowing from the die junction to ambient goes
through the package and the heatsink. JA can be calculated as follows:
Equation 2:
JA =
JC +
CH+
HA
Where:
JC = Junction-to-Case Thermal Resistance
CH = Case-to-Heatsink Thermal Resistance
HA = Heatsink-to-Ambient Thermal Resistance
CH+ HA determines which heatsink and heatsink attachment can
be selected to ensure the junction temperature does not exceed the
maximum junction temperature. According to Equation 1 and 2,
CH+ HA can be calculated as follows:
Equation 3:
CH+
HA = (Tj - TA) / P -
JC
Assume:
Tj = 125°C (Tjmax)
TA = 85°C
P = 1.57W
JC = 12.6°C/W (VFQFPN/NL68)
CH+
HA can be calculated as follows:
CH+
HA = (125°C - 85°C ) / 1.57W - 12.6°C/W = 12.9°C/W
That is, if a heatsink and heatsink attachment whose
CH+
HA is
below or equal to 12.9°C/W is used in such operation environment, the
junction temperature will not exceed the maximum junction temperature.
Table 32: Power Consumption and Maximum Junction Temperature
Package Power
Consumption (W)
Operating
Voltage
(V) TA (°C) Maximum
Junction
Temperature (°C)
VFQFPN/NL68 1.57 3.6 85 125
Table 33: Thermal Data
Package Pin Count Thermal Pad JC (°C/W) JB (°C/W) JA (°C/W) Air Flow in m/s
012345
VFQFPN/NL68 68 Yes/Exposed 9.1 8.3 39.4 34.1 31.7 30.2 29.1 28.2
VFQFPN/NL68 68 Yes/Soldered* 9.1 1.2 20.9 16.2 15.2 14.6 14.1 13.8
*note: Simulated with 3 x 3 array of thermal vias.
IDT82V32021 EBU WAN PLL
Thermal Managemen t 93 April 24, 2015
7.4 V FQFPN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on the
Printed Circuit Board (PCB) within the footprint of the package corre-
sponding to the exposed metal pad or exposed heat slug on the pack-
age, as shown in Figure 18. The solderable area on the PCB, as defined
by the solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the thermal/electri-
cal performance. Sufficient clearance should be designed on the PCB
between the outer edges of the land pattern and the inner edges of pad
pattern for the leads to avoid any shorts.
Figure 18. Ass em b ly fo r Expos e Pad the rm al Re le as e Pa th (Sid e View)
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a solder
joint, thermal vias are necessary to effectively conduct from the surface
of the PCB to the ground plane(s). The land pattern must be connected
to ground through these vias. The vias act as ‘heat pipes’. The number
of vias (i.e. ‘heat pipes’) are application specific and dependent upon the
package power dissipation as well as electrical conductivity require-
ments. Thus, thermal and electrical analysis and/or testing are recom-
mended to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is incorpo-
rated in the land pattern. It is recommended to use as many vias con-
nected to ground as possible. It is also recommended that the via
diameter should be 12 to 13mils (0.30 to 0.33mm) with 1 oz copper via
barrel plating. This is desirable to avoid any solder wicking inside the via
during the soldering process which may result in voids in solder between
the exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern.
Note: These recommendations are to be used as a guideline only.
For further information, please refer to the Application Note on the Sur-
face Mount Assembly of Amkor's Thermally/Electrically Enhance Lead
fame Base Package, Amkor Technology.
THERMAL VIA LAND PATTERN
SOLDER PIN
SOLDER
PIN PADPIN PAD
PIN
GROUND PLANE
EXPOSED HEAT SLUG
(GROUND PAD)
IDT82V32021 EBU WAN PLL
Electrical Specifications 94 April 24, 2015
8 ELECTRICAL SPECIFICATIONS
8.1 ABSOLUTE MAXIMUM RATING
8.2 RECOMMENDED OPERATION CONDITIONS
Table 34: Absolute Maximum Rating
Symbol Parameter Min Max Unit
VDD Supply Voltage VDD -0.5 4.0 V
VIN Input Voltage (non-supply pins) 5.5 V
VOUT Output Voltage (non-supply pins) 5.5 V
TSTOR Storage Temperature -50 +150 °C
Table 35: Recommended Operation Conditions
Symbol Parameter Min Typ Max Unit Test Condition
VDD Power Supply (DC voltage) VDD 3.0 3.3 3.6 V
TAAmbient Temperature Range -40 +85 °C
IDD Supply Current 325 365 mA Exclude the loading
current an d power
PTOT Total Power Dissipation 1.08 1.30 W
IDT82V32021 EBU WAN PLL
Electrical Specifications 95 April 24, 2015
8.3 I/O SPECIFICATIONS
8.3.1 CMOS INPUT / OUTPUT PORT
Table 36: CMOS Input Port Electrical Characteristics
Parameter Description Min Typ Max Unit Test Condition
VIH Input Voltage High 2.0 V
VIL Input Voltage Low 0.8 V
IIN Input Current 10 A
VIN Input Voltage -0.5 5.5 V
Table 37: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics
Parameter Description Min Typ Max Unit Test Condition
VIH Input Voltage High 2.0 V
VIL Input Voltage Low 0.8 V
PUPull-Up Resistor 23 38 K
TDI, TMS pin
41 82 RST pin
82 165
IIN Input Current 85 140
ATDI, TMS pin
40 80 RST pin
20 40
VIN Input Voltage -0.5 5.5 V
Table 38: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics
Parameter Description Min Typ Max Unit Test Condition
VIH Input Voltage High 2.0 V
VIL Input Voltage Low 0.8 V
PDPull-Down Resistor 814
K
TRST and TCK pin
16 23 other CMOS input port with internal pull-down resistor
183 366 SDI, CLKE pin
IIN Input Current 390 640
A
TRST and TCK pin
180 340 other CMOS input port with internal pull-down resistor
15 30 SDI, CLKE pin
VIN Input Voltage -0.5 5.5 V
IDT82V32021 EBU WAN PLL
Electrical Specifications 96 April 24, 2015
Table 39: CMOS Output Port Electrical Characteristics
Application Pin Parameter Description Min Typ Max Unit Test Condition
Output Clock
VOH Output Voltage High 2.4 VDD VIOH = 8 mA
VOL Output Voltage Low 0 0.4 V IOL = 8 mA
tRRise time (20% to 80%) 3 4 ns 15 pF
tFFall time (20% to 80%) 3 4 ns 15 pF
Other Output
VOH Output Voltage High 2.4 VDD VIOH = 4 mA
VOL Output Voltage Low 0 0.4 V IOL= 4 mA
tRRise Time (20% to 80%) 10 ns 50 pF
tFFall Time (20% to 80%) 10 ns 50 pF
IDT82V32021 EBU WAN PLL
Electrical Specifications 97 April 24, 2015
8.4 JITTER & WANDER PERFORMANCE
Table 40: Output Clock Jitter Generation
Test Definition 1Peak to Peak
Typ RMS
Typ Note Test Filter
N x 2.048MHz without APLL <2 ns <200 ps 20 Hz - 100 kHz
N x 2.048MHz with T0 APLL <1 ns <100 ps See Table 41: Output Clock Phase Noise for details 20 Hz - 100 kHz
N x 1.544 MHz without APLL <2 ns <200 ps 10 Hz - 40 kHz
N x 1.544 MHz with T0 APLL <1 ns <100 ps See Table 41: Out put Clock Phase Noise for details 10 Hz - 40 kHz
44.736 MHz with T0 APLL <1 ns <100 ps See Table 41: Ou tput Clock Phase Noi se for details 100 Hz - 800 kHz
44.736 MHz without APLL <2 ns <200 ps 100 Hz - 800 kHz
34.368 MHz with T0 APLL <1 ns <100 ps See Table 41: Ou tput Clock Phase Noi se for details 10 Hz - 400 kHz
34.368 MHz without APLL <2 ns <200 ps 10 Hz - 400 kHz
OC-3
(Chip T0 DPLL + T0 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz out-
put
0.004 UI p-p 0.001 UI RMS GR-253, G.813 Option 2
limit 0.1 UI p-p
(1 UI-6430 ps) 12 kHz - 1.3 MHz
0.004 UI p-p 0.001 UI RMS G.813 Option 1, G.812
limit 0.5 UI p-p
(1 UI-6430 ps) 500 Hz - 1.3 MHz
0.001 UI p-p 0.001 UI RMS G.813 Option 1
limit 0.1 UI p-p
(1 UI-6430 ps) 65 kHz - 1.3 MHz
OC-12
(Chip T0 DPLL + T0 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz out-
put + Intel GD16523 + Optical transceiver)
0.018 UI p-p 0.007 UI RMS GR-253, G.813 Option 2
limit 0.1 UI p-p
(1 UI-1608 ps) 12 kHz - 5 MHz
0.028 UI p-p 0.009 UI RMS G.813 Option 1, G.812
limit 0.5 UI p-p
(1 UI-1608 ps) 1 kHz - 5 MHz
0.002 UI p-p 0.001 UI RMS G.813 Option 1, G.812
limit 0.1 UI p-p
(1 UI-160 8ps) 250 kHz - 5 MHz
STM-16
(Chip T0 DPLL + T0 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz out-
put + Intel GD16523 + Optical transceiver)
0.162 UI p-p 0.03 UI RMS G.813 Option 1, G.812
limit 0.5 UI p-p
(1 UI-402 ps) 5 kHz - 20 MHz
0.01 UI p-p 0.009 UI RMS G.813 Option 1, G.812
limit 0.1 UI p-p
(1 UI-402 ps) 1 MHz - 20 MHz
Note:
1. CMAC E2747 TCXO is used.
Table 41: Output Clock Phase Noise
Output Clock 1@100Hz Offset
Typ @1kHz Offset
Typ @10kHz Offset
Typ @100kHz Offset
Typ @1MHz Offset
Typ @5MHz Offset
Typ Unit
155.52 MHz (T0 DPLL + T0 APLL) -82 -98 -107 -112 -119 -140 dBC/Hz
38.88 MHz (T0 DPLL + T0 APLL) -94 -110 -118 -124 -131 -143 dBC/Hz
16E1 (T0 APLL) -94 -110 -1 1 8 -125 -131 -142 dBC/Hz
16T1 (T0 APLL) -95 -112 -120 -127 -132 -143 dBC/Hz
E3 (T0 APLL) -93 -109 -116 -124 -131 -138 dBC/Hz
T3 (T0 APLL) -92 -108 -116 -122 -126 -141 dBC/Hz
Note:
1. CMAC E2747 TCXO is used.
IDT82V32021 EBU WAN PLL
Electrical Specifications 98 April 24, 2015
Table 42: Input Jitter Tolerance (155.52 MHz)
Jitter Frequency Jitter T o lerance Amplitude (UI p-p)
12 Hz > 2800
178 Hz > 2800
1.6 mHz > 311
15.6 mHz > 311
0.125 Hz > 39
19.3 Hz > 39
500 Hz > 1.5
6.5 kHz > 1.5
65 kHz > 0.15
1.3 MHz > 0.15
Table 43: Input Jitter To lerance (1.544 MHz)
Jitter Frequency Jitter Tolerance Amplitude (UI p-p)
1 Hz 150
5 Hz 140
20 Hz 130
300 Hz 38
400 Hz 25
700 Hz 15
2400 Hz 5
10 kHz 1.2
40 kHz 0.5
Table 44: Input Jitter Tolerance (2.048 MHz)
Jitter Frequency Jitter Tolerance Amplitude (UI p-p)
1 Hz 150
5 Hz 140
20 Hz 130
300 Hz 40
400 Hz 33
700 Hz 18
2400 Hz 5.5
10 kHz 1.3
50 kHz 0.4
100 kHz 0.4
Table 45: Input Jitter Tolerance (8 kHz)
Jitter Frequency Jitter Tolerance Amplitude (UI p-p)
1 Hz 0.8
5 Hz 0.7
20 Hz 0.6
300 Hz 0.16
400 Hz 0.14
700 Hz 0.07
2400 Hz 0.02
3600 Hz 0.01
Table 46: T0 DPLL Jitter Transfer & Damping Factor
3 dB Bandwidth Programmable Damping Factor
1.2 Hz 1.2, 2.5, 5, 10, 20
2.5 Hz 1.2, 2.5, 5, 10, 20
4 Hz 1.2, 2.5, 5, 10, 20
8 Hz 1.2, 2.5, 5, 10, 20
18 Hz 1.2, 2.5, 5, 10, 20
35 Hz 1.2, 2.5, 5, 10, 20
70 Hz 1.2, 2.5, 5, 10, 20
560 Hz 1.2, 2.5, 5, 10, 20
IDT82V32021 EBU WAN PLL
Electrical Specifications 99 April 24, 2015
8.5 O UTPUT WANDER GENERATION
Figure 19. Output W ander Generation
template
tested result
template
tested result
IDT82V32021 EBU WAN PLL
Electrical Specifications 100 April 24, 2015
8.6 INPUT / OUTPUT CLOCK TIMING
The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs.
Figure 20. Input / Output Clock Timing
Table 47: Input/Output Clock Timing
Symbol Typical Delay 1 (ns) Peak to Peak Delay Variation (ns)
t141.6
t211.6
t311.6
t421.6
t51.4 1.6
t631.6
Note:
1. Typical delay provided as refere nce only.
8 kHz Input Clock
8 kHz Output Clock
6.48 MHz Input Clock
6.48 MHz Output Clock
19.44 MHz Input Clock
19.44 MHz Output Clock
25.92 MHz Input Cl ock
25.92 MHz Output Clock
38.88 MHz Input Cl ock
38.88 MHz Output Clock
51.84 MHz Input Clock
51.84 MHz Output Clock
t1
t2
t3
t4
t5
t6
IDT82V32021 EBU WAN PLL
Electrical Specifications 101 April 24, 2015
8.7 OUTPUT CLOCK TIMING
Table 48: Output Clock Timing
Symbol Typical Delay (ns) Peak to Peak Delay Variation (ns)
t102
t202
t302
t402
t502
t602
t702
t802
t902
t10 02
t11 01.5
N X T 1 (1.544 MH z ) t1
N X E1 (2.048 MHz)
E3 (34.368 M H z)
6.48 MH z
19.44 MH z
25.92 MH z
38.88 MHz
51.84 MH z
77.76 MH z
155.52 MH z
FRSYNC_8K
T3 (44.736 MHz)
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Glossary 102 April 24, 2015
3G --- Third Gene r ation
ADSL --- Asymmetric Digital Subscriber Line
AMI --- Alternate Mark Inversion
APLL --- Analog Phase Locked Loop
ATM --- Asynchronous Transfer Mode
BITS --- Building Integrated Timing Supply
CMOS --- Complementary Metal-Oxide Semiconductor
DCO --- Digital Controlled Oscillator
DPLL --- Digital Phase Locked Loop
DSL --- Digital Subscriber Line
DSLAM --- Digital Subscriber Line Access MUX
DWDM --- Dense Wavelength Division Multiplexing
EPROM --- Erasable Programmable Read Only Memory
GPS --- Global Positioning System
GSM --- Global System for Mobile Communications
IIR --- Infinite Impulse Response
IP --- Internet Protocol
ISDN --- Integrated Services Digital Network
JTAG --- Joint Test Action Group
LOS --- Loss Of Signal
LPF --- Low Pass Filter
MTIE --- Maximum Time Interval Error
MUX --- Multiplexer
OBSAI --- Open Base Station Architecture Initiative
OC-n --- Optical Carried rate, n = 1, 3, 12, 48, 192, 768; 51 Mbit/s, 155 Mbit/s, 622 Mbit/s, 2.5 Gbit/s, 10 Gbit/s, 40 Gbit/s.
PBO --- Phase Build-Out
Glossary
Glossary 103 April 24, 2015
IDT82V32021 EBU WAN PLL
PDH --- Plesiochronous Digital Hierarchy
PFD --- Phase & Frequency Detector
PLL --- Phase Locked Loop
RMS --- Root Mean Square
PRS --- Primary Reference Source
SDH --- Synchronous Digital Hierarchy
SEC --- SDH / SONET Equipment Clock
SMC --- SONET Minimum Clock
SONET --- Synchronous Optical Network
SSU --- Synchronization Supply Unit
STM --- Synchronous Transfer Mode
TCM-ISDN --- Time Compression Multiplexing Integrated Services Digital Network
TDEV --- T ime Deviation
UI --- Unit Interval
WLL --- Wireless Local Loop
Index 104 April 24, 2015
A
Averaged Phase Error ........................................................................29
B
Bandwidths and Damping Factors .....................................................29
Acquisition Bandwidth and Damping Factor ...............................29
Locked Bandwidth and Damping Factor .....................................29
Starting Bandwidth and Damping Factor ....................................29
C
Calibration ..........................................................................................16
Coarse Phase Loss ............................................................................23
Crystal Oscillator ................................................................................16
Current Frequency Offset ...................................................................29
D
DCO ...................................................................................................29
Division Factor ....................................................................................18
DPLL Hard Alarm ...............................................................................23
DPLL Hard Limit .................................................................................23
DPLL Operating Mode
Free-Run mode ..........................................................................29
Holdover mode ...........................................................................29
Automatic Fast Averaged ...................................................30
Automatic Instantaneous ....................................................30
Automatic Slow Averaged ..................................................30
Manual ................................................................................30
Locked mode ..............................................................................29
Temp-Holdover mode .........................................................29
Lost-Phase mode .......................................................................29
Pre-Locked mode .......................................................................29
Pre-Locked2 mode .....................................................................30
DPLL Soft Alarm .................................................................................23
DPLL Soft Limit ..................................................................................23
E
External Sync Alarm ...........................................................................36
F
Fast Loss ............................................................................................23
Fine Phase Loss .................................................................................23
Frequency Hard Alarm .................................................................20, 25
Frequency Hard Alarm Threshold ...................................................... 20
H
Hard Limit ........................................................................................... 23
Holdover Frequency Offset ................................................................ 30
I
IIR ...................................................................................................... 30
Input Clock Frequency ....................................................................... 20
Input Clock Selection ......................................................................... 21
Automatic selection ..............................................................22, 25
External Fast selection ............................................................... 25
Forced selection ...................................................................22, 25
Internal Leaky Bucket Accumulator ................................................... 19
Bucket Size ................................................................................ 19
Decay Rate ................................................................................ 19
Lower Threshold ........................................................................ 19
Upper Threshold ........................................................................ 19
L
Limit ................................................................................................... 32
LPF .................................................................................................... 29
M
Master Clock ...................................................................................... 16
N
No-activity Alarm ..........................................................................19, 25
P
PFD .................................................................................................... 29
Phase Lock Alarm ........................................................................23, 25
Phase-compared ..........................................................................23, 32
Phase-time ......................................................................................... 32
Pre-Divider ......................................................................................... 18
DivN Divider ............................................................................... 18
Lock 8k Divider .......................................................................... 18
R
Reference Clock ................................................................................ 20
Index
Index 105 April 24, 2015
IDT82V32021 EBU WAN PLL
S
Selected Input Clock Switch ...............................................................25
Non-Revertive switch ..................................................................25
Revertive switch .........................................................................25
State Machine .................................................................................... 27
V
Validity ............................................................................................... 25
IDT82V32021 EBU WAN PLL
106 April 24, 2015
PACKAGE DIMENSIONS - 68-PIN NL
Figure 21. 68-Pin NL Package Dimensions (a) (in Millimeters)
IDT82V32021 EBU WAN PLL
107 April 24, 2015
Figure 22. 68-Pin NL Package Dimensions (b) (in Millimeters)
SYM
BOL NL68 NOTE
MIN. NOM. MAX.
A 0.80 0.90 1.00
A1 0.00 0.02 0.05
A3 0.20 REF.
b 0.18 0.25 0.30 5
D 10.00 BSC
E 10.00 BSC
D2 7.60 7.70 7.80 8
E2 7.60 7.70 7.80 8
k 0.20 - -
L 0.45 0.50 0.55
e0.50 BSC
N68 6
Nd 17 6
Ne 17 6
IDT82V32021 EBU WAN PLL
CORPORATE HEADQUARTERS
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108
ORDERING INFORMATION
DATASHEET DOCUMENT HISTORY
09/11/2008 Page 103
03/20/2009 Pages 42, 43, 92, 93, 97
07/23/2009 Pages 12, 96
04/24/2015 Page 108 removed leaded device
XXXXXXX XX X
Device Type
Blank
Process/
Temperature
Range
82V32021
Industrial (-40 °C to +85 °C)
WAN PLL
NLG Green Thermally Enhanced Plastic Very Fine Pitch Quad
Flat N o Lead Package (VF Q F PN, NLG68)