CY62126EV30 MoBL
1-Mbit (64K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05486 Rev . *H Revised December 17, 2010
Features
■High speed: 45 ns
■Temperature ranges
❐Industrial: –40 °C to +85 °C
❐Automotive: –40 °C to +125 °C
■Wide voltage range: 2.2 V to 3.6 V
■Pin compatible with CY62126DV30
■Ultra low standby power
❐Typical standby current: 1 A
❐Maximum standby current: 4 A
■Ultra low active power
❐Typical active current: 1.3 mA at f = 1 MHz
■Easy memory expansion with CE and OE features
■Automati c power down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Offered in Pb-free 48-ball very fine pitch ball grid array (VFBGA)
and 44-pin thin small outline package (TSOP) II packages
Functional Description
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life(MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input an d
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), the outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disa b le d (BHE , BLE HIGH) or during a write
operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the “T ruth Table” on page 11 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
64K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BHE
A0
A1
A9
A10
BLE
Logic Block Diagram
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 2 of 16
Contents
Pin Configuration ............................................................. 3
Maximum Ratings............................................................. 4
Operating Range................ ... .............. ... .............. ............. 4
Electrical Characteristics................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance.......................................................... 5
Data Retention Characteristics ....................................... 6
Switching Characteristics................................... .. ........... 7
Switching Waveforms........................ ... .............. ............. 8
Truth Table...................................................................... 11
Ordering Information...................................................... 12
Ordering Code Definitions......................................... 12
Package Diagrams.......................................................... 13
Acronyms........................................................................ 14
Document History Page........ ... .............. ... .............. ....... 15
Sales, Solutions, and Legal Information...................... 16
Worldwide Sales and Design Support....................... 16
Products.................................................................... 16
PSoC Solutions........................ ... .............. ... ... .......... 16
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 3 of 16
Pin Configuration
Figure 1. 48-Ball VFBGA (Top View) Figure 2. 44-Pin TSOP II (Top View) [1]
Table 1. Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating, ICC (mA) Standby, ISB2 (A)
f = 1 MHz f = fmax
Min Typ[2] Max Typ[2] Max Typ[2] Max Typ[2] Max
CY62126EV30LL Industrial 2.2 3.0 3.6 45 1.3 2 11 16 1 4
CY62126EV30LL Automotive 2.2 3.0 3.6 55 1.3 4 11 35 1 30
WE
A
11
A
10
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
Vss
A
7
I/O
0
BHE
NC
NC
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
NC
NC
3
26
5
4
1
D
E
B
A
C
F
G
H
NC
NC
V
cc
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29
30
A
5
18
17
20
19 27
28
25
26
22
21 23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
NC
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Ty pical values are measured at VCC = VCC(typ), TA = 25 °C.
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 4 of 16
Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied........................................... –55 °C to +125 °C
Supply voltage to ground
potential..............................–0.3 V to 3.6 V (VCCmax + 0.3 V)
DC voltage applied to outputs
in High Z state[3, 4] ..............–0.3 V to 3.6 V (VCCmax + 0.3 V)
DC input voltage[3, 4] 0.3 V to 3.6 V (VCCmax + 0.3 V)
Output current into outputs (L OW) ..............................20 mA
Static discharge voltage.......................................... > 2001 V
(MIL-STD-883, Method 3015)
Latch up current..................................................... > 200 mA
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns.
4. VIH(max) = VCC+0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
7. Chip enable (CE) needs to be tied t o CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Operating Range
Device Range Ambient
Temperature VCC[5]
CY62126EV30LL Industrial –40 °C to +85 °C 2.2 V to
3.6 V
Automotive –40 °C to +125 °C
Electrical Characteristics
(Over the Operating Range)
Parameter Description Test Conditions 45 ns (Industrial) 55 ns (Automotive) Unit
Min Typ[6] Max Min Typ[6] Max
VOH Output high voltage IOH = –0.1 mA 2.0 – – 2.0 – – V
IOH = –1.0 mA, VCC > 2.70V 2.4 – – 2.4 – – V
VOL Output low voltage IOL = 0.1 mA – – 0. 4 – 0.4 V
IOL = 2.1mA, VCC > 2.70V – – 0.4 – – 0.4 V
VIH Input high voltage VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 1.8 – VCC + 0.3 V
VCC = 2.7 V to 3.6 V 2.2 – VCC + 0.3 2.2 – V CC + 0.3 V
VIL Input low voltage VCC = 2.2 V to 2.7 V –0.3 – 0.6 –0.3 – 0.6 V
VCC = 2.7 V to 3.6 V –0.3 – 0.8 –0.3 – 0.8 V
IIX Input leakage current GND < VI < VCC –1 – +1 –4 – +4 A
IOZ Output leakage current GND < VO < VCC, Output Disabled –1 – +1 –4 – +4 A
ICC VCC operating supply
current f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
11 16 – 11 35 mA
f = 1 MHz – 1.3 2.0 – 1.3 4.0
ISB1 Automatic CE power
down current —CMOS
inputs
CE > VCC 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V)
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60V
–1 4 –1 35 A
ISB2 [7] Automatic CE power
down current —CMOS
inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60V
–1 4 –1 30 A
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 5 of 16
Capacitance
For all packages. Tested initially and after any design or process cha nges that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resist ance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions VFBGA
Package TSOP II
Package Unit
JA Thermal resist ance
(Junction to ambient) Still Air, solde re d on a 4.25 × 1.125 inch,
two-layer printed circuit board 58.85 28.2 °C/W
JC Thermal resist ance
(Junction to case) 17.01 3.4 °C/W
Figure 3. AC Test Loads and Waveforms
Parameters 2.2 V - 2.7 V 2.7 V - 3.6 V Unit
R1 16600 1103
R2 15400 1554
RTH 8000 645
VTH 1.2 1.75 V
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT VTH
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 6 of 16
Notes
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. Tested initially and after any design or process changes that may affect these parameters.
10.Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s.
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ[8] Max Unit
VDR VCC for data retention 1.5 – – V
ICCDR[9] Data retention current VCC= VDR, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V Industrial – – 3 A
Automotive – – 30 A
tCDR[10] Chip deselect to data
retention time 0–– ns
tR[10] Operation recovery time tRC ––ns
Figure 4. Data Retention Waveform
VCC(min)
VCC(min)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
VCC
CE
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 7 of 16
Switching Characteristics
Over the Operating Range [1 1, 12]
Parameter Description 45 ns (Industrial) 55 ns (Automotive) Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 45 – 55 – ns
tAA Address to data valid – 45 – 55 ns
tOHA Data hold from address change 10 – 10 – ns
tACE CE LOW to data valid –45 –55 ns
tDOE OE LOW to data valid –22 –25 ns
tLZOE OE LOW to Low Z [13] 5–5–ns
tHZOE OE HIGH to High Z [13, 14] –18 –20 ns
tLZCE CE LOW to Low Z [13] 10 –10 –ns
tHZCE CE HIGH to High Z [13, 14] –18 –20 ns
tPU CE LOW to power up 0 –0–ns
tPD CE HIGH to power down –45 –55 ns
tDBE BHE / BLE LOW to data valid –22 –25 ns
tLZBE BHE / BLE LOW to Low Z [13] 5–5–ns
tHZBE BHE / BLE HIGH to High Z [13, 14] –18 –20 ns
Write Cycle [15]
tWC W rite cycle time 45 – 55 – ns
tSCE CE LOW to write end 35 –40 –ns
tAW Address setup to write end 35 – 40 – ns
tHA Address hold from write end 0 – 0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 35 –40 –ns
tBW BHE / BLE pulse width 35 –40 –ns
tSD Data setup to write end 25 – 25 – ns
tHD Data hold from write end 0 – 0 – ns
tHZWE WE LOW to High Z [13, 14] –18 –20 ns
tLZWE WE HIGH to Low Z [13] 10 –10 –ns
Notes
1 1. Test conditions assume signal transition time of 3 ns or less, timin g reference levels of V CC(typ)/2, input pulse leve ls of 0 to VCC(typ), and output loading of the specified
IOL/IOH and 30-pF load capacitance.
12.AC timing parameters are subject to byte enab le signals (BHE or BLE) not switching when chip is disabled. See application not e AN13842 for further clarification.
13.At any temperature and voltage conditi on, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
14.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
15.The internal write time of the memory is def ined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a writ e and any of these
signals can terminate a write by going inact i ve. The data inpu t setup and hold timing must refer to the edge of signal that terminates write.
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 8 of 16
Switching Waveforms
Figure 5. Read Cycle No. 1(Address transition controlled)[16, 17]
Figure 6. Read Cycle No. 2 (OE controlled)[17, 18]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
16.The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
17.WE is high for read cycle.
18.A dd re ss va l id be fo r e or similar to CE and BHE, BLE transition LOW.
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 9 of 16
Figure 7. Write Cycle No. 1 (WE controlled)[19, 20, 21]
Figure 8. Write Cycle No. 2 (CE controlled)[19, 20, 21]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 22
tBW
tSCE
DATA I/O
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
NOTE 22
Notes
19.The internal write time of the memory is defined by the over lap of WE , CE = VIL, BHE, BLE or both = VIL. All signals must be active to init iate a write and any of
these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
20.Data I/O is high impedance if OE = VIH.
21.If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state.
22.During this period, the I/Os are in output state. Do not apply input signals.
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 10 of 16
Figure 9. Write Cycle No. 3 (WE controlled, OE LOW [23]
Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)[23]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 24
CE
ADDRESS
WE
DATA I/O
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 24
DATA I/O
ADDRESS
CE
WE
BHE/BLE
Note
23.If CE goes high simultaneou sly with WE = VIH, the output remains in a high impedance state.
24.During this period, the I/Os are in output state. Do not apply input signals.
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 11 of 16
Note
25.Chip enable must be at CMOS levels (not floating). Intermedi ate voltage levels on this pi n is not permitted.
Truth Table
CE[25] WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/power down Standby (ISB)
L X X H H High Z Out pu t di sa b le d Active (ICC)
L H L L L Data out (I/O0–I/O15)Read Active (I
CC)
L H L H L Data out (I/O0–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data out (I/O8–I/O15);
I/O0–I/O7 in High Z Read Active (ICC)
L H H L L High Z O utput disabled Active (ICC)
L H H H L High Z Out pu t di sa bled Active (ICC)
L H H L H Hig h Z Output disabled Active (ICC)
L L X L L Data in (I/O0–I/O15) Write Active (ICC)
L L X H L Data in (I/O0–I/O7);
I/O8–I/O15 in High Z Write Active (ICC)
L L X L H Data in (I/O8–I/O15);
I/O0–I/O7 in High Z Write Active (ICC)
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 12 of 16
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62126EV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free) Industrial
CY62126EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free) Industrial
CY62126EV30LL-45ZSXA 51-85087 44-pin TSOP II (Pb-free) Automotive-A
55 CY62126EV30LL-55BVXE 51-85150 48-ball VFBGA (Pb-free) Automotive-E
CY62126EV30LL-55ZSXE 51-85087 44-pin TSOP II (Pb -free) Automotive-E
Contact your local Cypress sales representative for availability of other parts.
CY
621 = MoBL SRAM Family
621 2 6
Density = 1 Mbit
Company ID: CY = Cypress
E
Bus Width = x16
E = Process Technology 90 nm
V30
Voltage Range = 3 V Typical
LL
Low Power
45/55
Speed grade
XXX
Package type:
BVX: VFBGA (Pb-free)
ZSX: TSOP II (Pb-free)
XTemperature Grades:
I = Industrial
A = Auto-A
E = Auto-E
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 13 of 16
Package Diagrams
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
51-85150 *F
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 14 of 16
Figure 12. 44-Pin TSOP II, 51-85087
Acronyms
MAX
MIN.
DIMENSION IN MM (INCH)
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
EJECTOR MARK
Z
A
Z
Z
Z
Z
X
A
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
TOP VIEW BOTTOM VIEW
PLANE
SEATING
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
BASE PLANE
0.10 (.004)
11.938 (0.470)
PIN 1 I.D.
44
1
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
22
23
51-85087-*C
Acronym Description
BHE byte high enable
BLE byte low enable
CMOS complementary metal oxide semiconductor
CE chip enable
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
VFBGA very fine ball gird array
WE write enable
CY62126EV30 MoBL
Document #: 38-05486 Rev. *H Page 15 of 16
Document History Page
Document Title: CY62126EV30 MoBL ®, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05486
Rev. ECN No. Submission
Date Orig. of
Change Description of Cha ng e
** 202760 See ECN AJU New data sheet
*A 300835 See ECN SYT Converted from Advance Information to Preliminary
Specified T ypical standby power in the Features Section
Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA Package
and removed the footnote associated with it on page #2
Changed tOHA from 6 ns to 10 ns for both 35- and 45-ns speed bins, respectively
Changed tDOE, tSD from 15 to 18 ns for 35-ns speed bin
Changed tHZOE, tHZBE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35- and
45-ns speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed
bins, respectively
Changed tSCE,tBW from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns speed
bins, respectively
Changed tAW from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins respec-
tively
Changed tDBE from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed bins
respectively
Removed fo otnote that read “BHE.BLE is the AND of both BHE and BLE. Chip can
be deselected by either disabling the chip enable signals or by disabling both BHE
and BLE” on page # 4
Removed footnote that read “If both BHE and BLE are toggled together , then tLZBE
is 10 ns” on page # 5
Added Pb-free package information
*B 461631 See ECN NXR Conv erted from Preliminary to Final
Removed 35 ns Speed Bin
Removed “L” version of CY62126EV30
Changed ICC (T yp) from 8 mA to 1 1 mA and ICC (max) from 12 mA to 16 mA for f = fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz, ISB1, ISB2 (max) from 1 A
to 4 A, ISB1, ISB2 (T yp) from 0.5 A to 1 A, ICCDR (max) from 1.5 A to 3 A, AC Test
load Capacitance value from 50 pF to 30 pF, tLZOE from 3 to 5 ns , tLZCE from 6 to
10 ns, tHZCE fr om 22 to 18 ns , tLZBE from 6 to 5 ns, tPWE from 30 to 35 ns, tSD from
22 to 25 ns, tLZWE from 6 to 10 ns, and updated the Ordering Information table.
*C 925501 See ECN VKN Added footnote #7 related to ISB2 and ICCDR
Added footnote #11 related AC timing parameters
*D 1045260 See ECN VKN Added Automotive information
Updated Ordering Information table
*E 2631771 01/07/09 NXR/PYRS Changed CE condition from X to L in Truth table for Output Disable mode
Updated template
*F 2944332 06/04/2010 VKN Added Contents
Removed byte enable from footnote #2 in Electrical Characteristics
Added footnote related to chip enable in Truth Table
Updated Package Diagrams
Updated links in Sales, Solutions, and Legal Information
*G 2996166 07/29/2010 AJU Added CY62126EV30LL-45ZSXA part in Ordering Information.
Added Ordering Code Definitions.
Modified table footnote format.
*H 3113864 12/17/2010 PRAS Updated Figure 1 and Package Diagram, and fi xed Typo in Figure 3..
Document #: 38-05486 Rev. *H Revised December 17, 2010 Page 16 of 16
MoBL is a regi stered trademark, and More B attery Life is a trademark, of C ypress Semiconductor . All product s and company names me ntioned in this document ma y be the trademarks of their r espective
holders.
CY62126EV30 MoBL
© Cypress Semicondu ctor Corpor ation, 2008-2010. The informatio n contai ned herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other righ ts. Cy pre ss pro d ucts a re n ot war r ant ed nor int e nd ed to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or safety applicatio ns, unl ess pu r suan t to an express written agreement wit h Cy press. Fu rthermore, Cypress does not authorize its pro ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwid e patent prot ection (Uni ted States and foreign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conju nction with a Cypres s
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permis sion of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY A ND FITNESS FOR A PARTICULAR PURPOSE. C ypress reserves the right to make changes without further notice to the materials des cribed herei n. Cypress does not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
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Products
Automotive cypress.com/go/automotive
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Interface cypress.com/go/interface
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
Optical & Image Sensing cypress.com/go/image
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
