NT5SV16M16AT-8BL - Nanya Technology

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Features

•High Performance:

•Single Pulsed RAS Interface

•Fully Synchronous to Positive Clock Edge

•Four Banks controlled by BA0/BA1 (Bank Select)

•Programmable CAS Latency: 2, 3

•Programmable Burst Length: 1, 2, 4, 8

•Programmable Wrap: Sequential or Interleave

•Multiple Burst Read with Single Write Option

•Automatic and Controlled Precharge Command

•Data Mask for Read/Write control (x4, x8)

•Dual Data Mask for byte control (x16)

•Auto Refresh (CBR) and Self Refresh

•Suspend Mode and Power Down Mode

•Standard Power operation

•8192 refresh cycles/64ms

•Random Column Address every CK (1-N Rule)

•Single 3.3V ± 0.3V Power Supply

•LVTTL compatible

•Package: 54-pin 400 mil TSOP-Type II

•-7K parts for PC133 2-2-2 operation

-75B parts for PC133 3-3-3 operation

-8B parts for PC100 2-2-2 operation

Description

The NT5SV64M4AT, NT5SV32M8AT, and NT5SV16M16AT

are four-bank Synchronous DRAMs organized as 16Mbit x 4

I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4

Bank, respectively. These synchronous devices achieve

high-speed data transfer rates of up to 133MHz by employing

a pipeline chip architecture that synchronizes the output data

to a system clock. The chip is fabricated with NTC’s

advanced 256Mbit single transistor CMOS DRAM process

technology.

The device is designed to comply with all JEDEC standards

set for synchronous DRAM products, both electrically and

mechanically. All of the control, address, and data input/out-

put (I/O or DQ) circuits are synchronized with the positive

edge of an externally supplied clock.

RAS, CAS, WE, and CS are pulsed signals which are exam-

ined at the positive edge of each externally applied clock

(CK). Internal chip operating modes are defined by combina-

tions of these signals and a command decoder initiates the

necessary timings for each operation. A fifteen bit address

bus accepts address data in the conventional RAS/CAS mul-

tiplexing style. Thirteen row addresses (A0-A12) and two

bank select addresses (BA0, BA1) are strobed with RAS.

Eleven column addresses (A0-A9, A11) plus bank select

addresses and A10 are strobed with CAS. Column address

A11 is dropped on the x8 device, and column addresses A11

and A9 are dropped on the x16 device.

Prior to any access operation, the CAS latency, burst length,

and burst sequence must be programmed into the device by

address inputs A0-A12, BA0, BA1 during a mode register set

cycle. In addition, it is possible to program a multiple burst

sequence with single write cycle for write through cache

operation.

Operating the four memory banks in an interleave fashion

allows random access operation to occur at a higher rate

than is possible with standard DRAMs. A sequential and gap-

less data rate of up to 133MHz is possible depending on

burst length, CAS latency, and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are sup-

ported.

-7K3

CL=2 -75B,

CL=3 -8B,

CL=2 Units

fCK Clock Frequency 133 133 100 MHz

tCK Clock Cycle 7.5 7.5 10 ns

tAC Clock Access Time1———ns

tAC Clock Access Time25.4 5.4 6ns

1. Terminated load. See AC Characteristics on page 37.

2. Unterminated load. See AC Characteristics on page 37.

3. tRP = tRCD = 2 CKs

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 2

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Assignments for Planar Components (Top View)

54-pin Plastic TSOP(II) 400 mil

16Mbit x 4 I/O x 4 Bank

NT5SV64M4AT

VDD

VDDQ

DQ0

VSSQ

VDDQ

DQ1

VSSQ

VDD

CAS

RAS

BA0

BA1

VSS

VSSQ

DQ3

VDDQ

VSSQ

DQ2

VDDQ

VSS

DQM

CKE

A12

A11

A10/AP

27 29

VDD

VSS

VDD

DQ0

VDDQ

DQ1

VSSQ

VDDQ

DQ3

VSSQ

VDD

DQ2

CAS

RAS

BA0

BA1

A10/AP

VDD

VSS

DQ7

VSSQ

DQ6

VDDQ

VSSQ

DQ4

VDDQ

VSS

DQ5

DQM

CKE

A12

A11

VSS

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

DQ3

DQ4

LDQM

CAS

RAS

BA0

BA1

A10/AP

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

DQ12

DQ11

UDQM

CKE

A12

A11

VSS

4Mbit x 16 I/O x 4 Bank

NT5SV16M16AT

8Mbit x 8 I/O x 4 Bank

NT5SV32M8AT

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 3

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Description

CK Clock Input DQ0-DQ15 Data Input/Output

CKE (CKE0, CKE1) Clock Enable DQM, LDQM, UDQM Data Mask

CS Chip Select VDD Power (+3.3V)

RAS Row Address Strobe VSS Ground

CAS Column Address Strobe VDDQ Power for DQs (+3.3V)

WE Write Enable VSSQ Ground for DQs

BA1, BA0 Bank Select NC No Connection

A0 - A12Address Inputs — —

Input/Output Functional Description

Symbol Type Polarity Function

CK Input Positive

Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.

CKE, CKE0,

CKE1 Input Active High Activates the CK signal when high and deactivates the CK signal when low. By deactivating the

clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.

CS Input Active Low CS enables the command decoder when low and disables the command decoder when high. When

the command decoder is disabled, new commands are ignored but previous operations continue.

RAS, CAS, WE Input Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be

executed by the SDRAM.

BA1, BA0 Input —Selects which bank is to be active.

A0 - A12 Input —

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sam-

pled at the rising clock edge.

During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9,

CA11), when sampled at the rising clock edge. Assume the x4 organization.

A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is

high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low,

autoprecharge is disabled.

During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which

bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10

is low, then BA0 and BA1 are used to define which bank to precharge.

DQ0 - DQ15 Input-

Output —Data Input/Output pins operate in the same manner as on conventional DRAMs.

DQM

LDQM

UDQM Input Active High

The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In

x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In

Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output

enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has

a latency of zero and operates as a word mask by allowing input data to be written if it is low but

blocks the write operation if DQM is high.

VDD, VSS Supply —Power and ground for the input buffers and the core logic.

VDDQ VSSQ Supply —Isolated power supply and ground for the output buffers to provide improved noise immunity.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 4

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Ordering Information

Organization Part Number Speed Grade Package Self

Refresh

Clock Frequency@CAS Latency Note

64M x 4

NT5SV64M4AT-7K 143MHz@CL3 133MHz@CL2 PC133 , PC100

400mil 54-

TSOP II SP

NT5SV64M4AT-75B 133MHz@CL3 100MHz@CL2 PC133 , PC100

NT5SV64M4AT-8B 125MHz@CL3 100MHz@CL2 PC100

32M x 8

NT5SV32M8AT-7K 143MHz@CL3 133MHz@CL2 PC133 , PC100

NT5SV32M8AT-75B 133MHz@CL3 100MHz@CL2 PC133 , PC100

NT5SV32M8AT-8B 125MHz@CL3 100MHz@CL2 PC100

16M x 16

NT5SV16M16AT-7K 143MHz@CL3 133MHz@CL2 PC133 , PC100

NT5SV16M16AT-75B 133MHz@CL3 100MHz@CL2 PC133 , PC100

NT5SV16M16AT-8B 125MHz@CL3 100MHz@CL2 PC100

16M x 16

NT5SV16M16AT-7KL 143MHz@CL3 133MHz@CL2 PC133 , PC100

LPNT5SV16M16AT-75BL 133MHz@CL3 100MHz@CL2 PC133 , PC100

NT5SV16M16AT-8BL 125MHz@CL3 100MHz@CL2 PC100

SP : Standard Power ; LP : Low power

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 5

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram

DQ0

DQX

Data Input/Output Buffers

CKE Buffer

CK Buffer

CKE

RAS

CAS

DQM

Command Decoder

Mode Register

Counter

Column

Address

Counter

Refresh

A10

A11

Sense Amplifiers

Memory Bank 1

Cell Array

Row Decoder

Address Buffers (15)

Column Decoder

Sense Amplifiers

Memory Bank 3

Cell Array

Row Decoder

Column Decoder

Sense Amplifiers

Memory Bank 0

Cell Array

Row Decoder

Column Decoder

Sense Amplifiers

Memory Bank 2

Cell Array

Row Decoder

Column Decoder

Data Control Circuitry

BA0

BA1

Control Signal

Generator

Cell Array, per bank, for 16Mb x 4 DQ: 8192 Row x 2048 Col x 4 DQ (DQ0-DQ3).

Cell Array, per bank, for 8Mb x 8 DQ: 8192 Row x 1024 Col x 8 DQ (DQ0-DQ7).

Cell Array, per bank, for 4Mb x 16 DQ: 8192 Row x 512 Col x 16 DQ (DQ0-DQ15).

A12

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 6

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Power On and Initialization

The default power on state of the mode register is supplier specific and may be undefined. The following power on and initializa-

tion sequence guarantees the device is preconditioned to each users specific needs.

Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power

on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP”

state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CK signal must be started

at the same time. After power on, an initial pause of 200µs is required followed by a precharge of all banks using the precharge

command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high

during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to ini-

tialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after

programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.

Programming the Mode Register

For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be

programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can

be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register

variables, all four variables must be redefined when the Mode Register Set Command is issued.

After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must

be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The

Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The

address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new

command may be issued following the mode register set command once a delay equal to tRSC has elapsed.

CAS Latency

The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock

edge to when the data from that Read Command becomes available at the outputs. The CAS latency is expressed in terms of

clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the

device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed

grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS

latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure

see Programming the Mode Register in the previous section.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 7

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Mode Register Operation (Address Input For Mode Set)

A11 A3A4 A2 A1 A0A10 A9 A8 A7 A6 A5 Address

BT Burst LengthCAS Latency Mode

CAS Latency

M6 M5 M4 Latency

0 0 0 Reserved

0 0 1 Reserved

0 1 0 2

0 1 1 3

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

Burst Length

M2 M1 M0 Length

Sequential Interleave

0 0 0 1 1

0 0 1 2 2

0 1 0 4 4

0 1 1 8 8

1 0 0 Reserved Reserved

1 0 1 Reserved Reserved

1 1 0 Reserved Reserved

1 1 1 Reserved Reserved

Burst Type

M3 Type

0Sequential

1Interleave

Operation Mode

M14M13M12 M11 M10 M9 M8 M7 Mode

00000000 Normal

00000100Multiple Burst

with

Single Write

Operation Mode

BA0BA1 Bus (Ax)

A12

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations

(read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst

sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by

address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits

A7 - A12, BA0, and BA1.

The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst

sequences are supported, sequential and interleaved. See the table below.

The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a

Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 (actual page length is dependent on organi-

zation: x4, x8, or x16).

Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the

device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with

single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to

read cycles. All write cycles are single write operations when this mode is selected.

Note: Page length is a function of I/O organization and column addressing.

x4 organization (CA0-CA9, CA11); Page Length = 2048 bits

x8 organization (CA0-CA9); Page Length = 1024 bits

x16 organization (CA0-CA8); Page Length = 512 bits

Burst Length and Sequence

Burst Length Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal)

2x x 0 0, 1 0, 1

x x 1 1, 0 1, 0

x 0 0 0, 1, 2, 3 0, 1, 2, 3

x 0 1 1, 2, 3, 0 1, 0, 3, 2

x 1 0 2, 3, 0, 1 2, 3, 0, 1

x 1 1 3, 0, 1, 2 3, 2, 1, 0

0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6

0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5

0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4

1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2

1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1

1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 9

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Bank Activate Command

In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The Bank

Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The Bank Select

address BA0 - BA1 is used to select the desired bank. The row address A0 - A12 is used to determine which row to activate in

the selected bank.

The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the

Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS

delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be

applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is deter-

mined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands

(Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active

is specified as tRAS(max).

Bank Select

The Bank Select inputs, BA0 and BA1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write oper-

ation.

Bank Activate Command Cycle

Bank Selection Bits

BA0 BA1 Bank

0 0 Bank 0

1 0 Bank 1

0 1 Bank 2

1 1 Bank 3

ADDRESS

CK T0 T2T1 T3 Tn Tn+1 Tn+2 Tn+3

COMMAND NOP NOP NOP NOP

Bank A

Row Addr.

Bank A

Activate Write A

with Auto

Bank A

Col. Addr.

. . . . . . . . . .

. . . . . . . . . . Bank B

Activate

Bank A

Row Addr.

Bank A

Activate

RAS-CAS delay (tRCD)

: “H” or “L” RAS Cycle time (tRC)

Precharge

RAS - RAS delay time (tRRD)

Bank B

Row Addr.

(CAS Latency = 3, tRCD = 3)

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 10

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low

at the clock’s rising edge after the necessary RAS to CAS delay (tRCD). WE must also be defined at this time to determine

whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the start-

ing column address.

The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write

operation on successive clock cycles up to 133MHz. The number of serial data bits for each access is equal to the burst length,

which is programmed into the Mode Register.

Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected

row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank.

A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock

cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Com-

mand, the remaining addresses are overridden by the new address.

Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again.

To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Acti-

vate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations

are possible. By using the programmed burst length and alternating the access and precharge operations between multiple

banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are acti-

vated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be

issued to the same bank or between active banks on every clock cycle.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 11

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Read Command

The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock.

The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or

interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears

on the outputs is equal to the value of the CAS latency that is set in the Mode Register.

Read Interrupted by a Read

A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that

the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remain-

ing addresses are overridden by the new address with the full burst length. The data from the first Read Command continues to

appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the

interrupting Read Command appears.

Burst Read Operation

Read Interrupted by a Read

COMMAND READ A NOP NOP NOP NOP NOP NOP NOP

DOUT A0

CAS latency = 2

tCK3, DQs

CAS latency = 3

DOUT A1DOUT A2DOUT A3

NOP

CK T0 T2T1 T3 T4 T5 T6 T7 T8

tCK2, DQs

DOUT A0DOUT A1DOUT A2DOUT A3

(Burst Length = 4, CAS latency = 2, 3)

COMMAND READ A READ B NOP NOP NOP NOP NOP NOP

tCK2, DQs

CAS latency = 2

tCK3, DQs

CAS latency = 3

NOP

CK T0 T2T1 T3 T4 T5 T6 T7 T8

DOUT B0DOUT B1DOUT B 2DOUT B3

DOUT A0

DOUT B 0DOUT B1DOUT B 2DOUT B3

DOUT A 0

(Burst Length = 4, CAS latency = 2, 3)

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 12

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance

state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the

write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ

bus.

Minimum Read to Write Interval

COMMAND NOPNOP READ A WRITE A NOP NOP NOP

DQM

DIN A0DIN A 1DIN A2DIN A3

: “H” or “L”

DIN A0DIN A 1DIN A2DIN A3

tCK2, DQs

CAS latency = 2

tCK3, DQs

CAS latency = 3

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOP

(Burst Length = 4, CAS latency = 2, 3)

DQM high for CAS latency = 2 only.

Required to mask first bit of READ data.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 13

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Non-Minimum Read to Write Interval

COMMAND NOPNOPREAD A WRITE A NOP NOP NOP

DQM

DIN A0DIN A 1DIN A2DIN A3

tCK2, DQs

CAS latency = 2

tCK3, DQs

CAS latency = 3

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOP

CL = 3: DQM needed to

mask first bit of READ data.

CL = 2: DQM needed to mask

first, second bit of READ data.

(Burst Length = 4, CAS latency = 2, 3)

: DQM high for CAS latency = 2

: DQM high for CAS latency = 3

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 14

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Write Command

The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock.

The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the

first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining

data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has fin-

ished, any additional data supplied to the DQ pins will be ignored.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is inter-

rupted, the remaining addresses are overridden by the new address and data will be written into the device until the pro-

grammed burst length is satisfied.

Burst Write Operation

Write Interrupted by a Write

COMMAND NOP WRITE A NOP NOP NOP NOP NOP NOP

DQs DIN A0DIN A1DIN A2DIN A3

NOP

CK T0 T2T1 T3 T4 T5 T6 T7 T8

Extra data is masked.The first data element and the Write

are registered on the same clock edge.

(Burst Length = 4, CAS latency = 2, 3)

: “H” or “L”

COMMAND NOP WRITE A WRITE B NOP NOP NOP NOP NOP

DQs DIN A0DIN B0DIN B1DIN B 2

NOP

DIN B 3

CK T0 T2T1 T3 T4 T5 T6 T7 T8

1 CK Interval

(Burst Length = 4, CAS latency = 2, 3)

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

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Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs

must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data

contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is pre-

sented on the DQ pins before the Read Command is initiated will actually be written to the memory.

Minimum Write to Read Interval

COMMAND NOPWRITE A READ B NOP NOP NOP NOP NOP NOP

tCK2, DQs

CAS latency = 2 DIN A0

tCK3, DQs

CAS latency = 3 DIN A0

CK T0 T2T1 T3 T4 T5 T6 T7 T8

Input data for the Write is masked. Input data must be removed from the DQs at least one clock

cycle before the Read data appears on the outputs to avoid

data contention.

DOUT B0DOUT B1DOUT B2DOUT B3

(Burst Length = 4, CAS latency = 2, 3)

: “H” or “L”

NT5SV64M4AT(L)

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Non-Minimum Write to Read Interval

COMMAND WRITE A READ B NOP NOP NOP NOP NOP NOP

tCK2, DQs

CAS latency = 2 DIN A 0

tCK3, DQs

CAS latency = 3 DIN A0

CK T0 T2T1 T3 T4 T5 T6 T7 T8

Input data for the Write is masked. Input data must be removed from the DQs at least one clock

cycle before the Read data appears on the outputs to avoid

data contention.

DOUT B0DOUT B 1DOUT B2DOUT B 3

DOUT B0DOUT B1DOUT B2DOUT B 3

NOP

DIN A 1

(Burst Length = 4, CAS latency = 2, 3)

: “H” or “L”

NT5SV64M4AT(L)

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Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command

or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra

address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during

the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst opera-

tion is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write

Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as

normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed.

Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can

also be implemented during Write commands.

A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or

Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or

Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst oper-

ation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has

been satisfied.

When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal

precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended.

Burst Read with Auto-Precharge

COMMAND NOP NOP NOP NOP

READ A

Auto-Precharge

tRP‡

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOPNOP

tRP‡

tCK2, DQs

CAS latency = 2

tCK3, DQs

CAS latency = 3

Begin Auto-precharge *Bank can be reactivated at completion of tRP.

DOUT A0

NOP

‡ tRP is a function of clock cycle time and speed sort.

See the Clock Frequency and Latency table.

(Burst Length = 1, CAS Latency = 2, 3)

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Burst Read with Auto-Precharge

COMMAND NOP NOP NOP NOP

READ A

Auto-Precharge

tRP‡

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOP

NOP

tRP‡

tCK2, DQs

CAS latency = 2

tCK3, DQs

CAS latency = 3

Begin Auto-precharge

DOUT A0

NOP

DOUT A1

*Bank can be reactivated at completion of tRP

‡ tRP

is a function of clock cycle time and speed sort.

See the Clock Frequency and Latency table.

(Burst Length = 2, CAS Latency = 2, 3)

COMMAND NOP NOP NOP NOP

READ A

Auto-Precharge

tRP‡

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOPNOP

tRP‡

tCK2, DQs

CAS latency = 2

tCK3, DQs

CAS latency = 3

Begin Auto-precharge

DOUT A0DOUT A1DOUT A2DOUT A3

NOP

DOUT A0DOUT A1DOUT A2DOUT A 3

*Bank can be reactivated at completion of tRP.

‡ tRP is a function of clock cycle time and speed sort.

See the Clock Frequency and Latency table.

(Burst Length = 4, CAS Latency = 2, 3)

NT5SV64M4AT(L)

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Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted

by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge

function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP.

If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.

Burst Read with Auto-Precharge Interrupted by Read

Burst Read with Auto-Precharge Interrupted by Write

tRP‡

COMMAND NOP NOP NOP NOP

READ A

Auto-Precharge

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOP

tRP‡

tCK2, DQs

CAS latency = 2

tCK3, DQs

CAS latency = 3

*Bank can be reactivated at completion of tRP.

DOUT A0DOUT A 1

NOP

DOUT A 0DOUT A1DOUT B 0DOUT B 1

READ B

DOUT B2DOUT B 3

DOUT B 0DOUT B1DOUT B2DOUT B 3

‡ tRP is a function of clock cycle time and speed sort.

See the Clock Frequency and Latency table.

(Burst Length = 4, CAS Latency = 2, 3)

COMMAND NOP NOP NOP

READ A

Auto-Precharge

tRP‡

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOP

tCK2, DQs

CAS latency = 2

DQM

NOP

DOUT A 0DIN B0DIN B 1

WRITE B

DIN B2DIN B3

NOP

DIN B4

*Bank can be reactivated at completion of tRP.

‡ tRP is a function of clock cycle time and speed sort..

See the Clock Frequency and Latency table.

(Burst Length = 8, CAS Latency = 2)

NT5SV64M4AT(L)

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If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-

precharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied.

Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank.

It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the

write. The bank undergoing auto-precharge can not be reactivated until tDAL is satisfied.

Burst Write with Auto-Precharge

Burst Write with Auto-Precharge Interrupted by Write

DIN A0

COMMAND NOP NOP NOP NOP

WRITE A

Auto-Precharge

DIN A1

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP

DIN A0DIN A1

tCK2, DQs

CAS latency = 2

tCK3, DQs

CAS latency = 3

NOP NOPNOP

*Bank can be reactivated at completion of tDAL.

tDAL‡

tDAL‡*

(Burst Length = 2, CAS Latency = 2, 3)

See the Clock Frequency and Latency table.

‡ tDAL is a function of clock cycle time and speed sort.

DIN A 0

COMMAND NOP NOP NOP

WRITE A

Auto-Precharge

DIN A1

tDAL‡

T0 T1 T2 T3 T4 T5

NOP

tCK3, DQs

CAS latency = 3

WRITE B

DIN B 0DIN B 1DIN B2DIN B3

T6 T7 T8

NOP NOPNOP

*Bank can be reactivated at completion of tDAL.

(Burst Length = 4, CAS Latency = 3)

See the Clock Frequency and Latency table.

‡ tDAL is a function of clock cycle time and speed sort.

NT5SV64M4AT(L)

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NT5SV16M16AT(L)

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Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered

when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to pre-

charge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which

bank(s) is to be precharged when the command is issued.

For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a

delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is

known as tDPL, Data-in to Precharge delay.

After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be

executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Pre-

charge time (tRP).

Burst Write with Auto-Precharge Interrupted by Read

Bank Selection for Precharge by Address Bits

A10 Bank Select Precharged Bank(s)

LOW BA0, BA1 Single bank defined by BA0, BA1

HIGH DON’T CARE All Banks

DIN A0

COMMAND NOP NOP NOP

WRITE A

Auto-Precharge

DIN A1

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOPNOP *

tCK3, DQs

CAS latency = 3

Bank A can be reactivated at completion of tDAL.

READ B

DIN A2

NOP

DOUT B0DOUT B1DOUT B2

tDAL‡

(Burst Length = 4, CAS Latency = 3)

See the Clock Frequency and Latency table.

‡ tDAL is a function of clock cycle time and speed sort.

NT5SV64M4AT(L)

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Burst Read Followed by the Precharge Command

Burst Write Followed by the Precharge Command

COMMAND READ Ax0NOP NOP NOP NOP NOP NOP NOP

tCK2, DQs

CAS latency = 3

CK T0 T2T1 T3 T4 T5 T6 T7 T8

DOUT Ax0DOUT Ax1DOUT Ax2DOUT Ax3

Precharge A

tRP

Bank A can be reactivated at completion of tRP.

(Burst Length = 4, CAS Latency = 3)

‡

‡tRP

is a function of clock cycle and speed sort.

COMMAND NOP NOP NOP

WRITE Ax0

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOP

NOP

DIN Ax 0DIN Ax1

Bank can be reactivated at completion of tRP.

Activate

Bank Ax

tCK2, DQs

CAS latency = 2

tDPL‡*

tRP‡

Precharge A

‡ tDPL and tRP are functions of clock cycle and speed sort.

See the Clock Frequency and Latency table.

(Burst Length = 2, CAS Latency = 2)

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

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Precharge Termination

The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command

is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to

appear on the data bus as a function of CAS Latency.

Burst Read Interrupted by Precharge

COMMAND READ Ax0NOP NOP NOP NOP NOP NOP NOP

tCK2, DQs

CAS latency = 2

CK T0 T2T1 T3 T4 T5 T6 T7 T8

DOUT Ax0DOUT Ax1DOUT Ax2DOUT Ax3

Precharge A

tCK3, DQs

CAS latency = 3 DOUT Ax0DOUT Ax1DOUT Ax2DOUT Ax3

tRP‡

Bank A can be reactivated at completion of tRP.

*See the Clock Frequency and Latency table.

(Burst Length = 8, CAS Latency = 2, 3)

‡ tRP

is a function of clock cycle time and speed sort.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

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Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the

device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the

Data-in to Precharge delay, tDPL.

Precharge Termination of a Burst Write

COMMAND NOP NOP NOP

WRITE Ax0

CK T0 T2T1 T3 T4 T5 T6 T7 T8

NOP NOP

NOP

DIN Ax 1DIN Ax2

tDPL‡

DIN Ax0

tCK2, DQs

CAS latency = 2

NOP

DIN Ax 1DIN Ax2

DIN Ax0

tCK3, DQs

CAS latency = 3

DQM

Precharge A

‡ tDPL is an asynchronous timing and may be completed in one or two clock cycles

depending on clock cycle time.

(Burst Length = 8, CAS Latency = 2, 3)

tDPL‡

NT5SV64M4AT(L)

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Automatic Refresh Command (CAS before RAS Refresh)

When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic

Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before

the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the

refresh cycle. No control of the external address pins is required once this cycle has started.

When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto

Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or

equal to the RAS cycle time (tRC).

Self Refresh Command

The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by hav-

ing CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the

Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.

When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is

internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self

Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is

cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device

exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC) plus

the Self Refresh exit time (tSREX).

NT5SV64M4AT(L)

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Power Down Mode

In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down

mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must

occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation,

Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or

Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power

Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does

not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period

(tREF) of the device.

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect

Command) is required on the next rising clock edge.

Power Down Mode Exit Timing

COMMAND NOP COMMAND NOP NOP NOP NOP NOP

CKE

: “H” or “L”

Tm Tm+2Tm+1 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+ 8

tCES(min)

tCK

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Data Mask

The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is

activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is

activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent

of CAS latency.

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No

Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Com-

mand will not terminate a previous operation that is still executing, such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is

brought high, the RAS, CAS, and WE signals become don’t cares.

Data Mask Activated during a Read Cycle

COMMAND NOP READ A NOP NOP NOP NOP NOP NOP NOP

DQM

: “H” or “L”

A two-clock delay before

the DQs become Hi-Z

DQs

CK T0 T2T1 T3 T4 T5 T6 T7 T8

DOUT A0DOUT A 1

(Burst Length = 4, CAS Latency = 2)

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Clock Suspend Mode

During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks

is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes”

any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and

the time at which the SDRAM’s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands

that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE

returns high to when Clock Suspend mode is exited.

When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto

the DQ pins will be actively held valid until Clock Suspend mode is exited.

If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Sus-

pend mode is exited.

Clock Suspend during a Read Cycle

Clock Suspend during a Write Cycle

CK T0 T2T1 T3 T4 T5 T6 T7 T8

COMMAND NOP READ A NOP NOP NOP NOP

CKE

DQs DOUT A 0DOUT A2

DOUT A1

: “H” or “L”

A one clock delay before

suspend operation starts

A one clock delay to exit

the Suspend command

DOUT element at the DQs when the

suspend operation starts is held valid

(Burst Length = 4, CAS Latency = 2)

CK T0 T2T1 T3 T4 T5 T6 T7 T8

COMMAND NOP WRITE A NOP NOP NOP NOP

CKE

DQs DIN A2DIN A3

: “H” or “L”

A one clock delay before

suspend operation starts

A one clock delay to exit

the Suspend command

DIN is masked during the Clock Suspend Period

DIN A1

DIN A0

(Burst Length = 4, CAS Latency = 2)

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Command Truth Table (See note 1)

Function Device State CKE CS RAS CAS WE DQM BA0,

BA1 A10 A12,

A11,

A9-A0 Notes

Cycle Current

Cycle

Mode Register Set Idle HXL L L L XOP Code

Auto (CBR) Refresh Idle H H LLLHX X X X

Entry Self Refresh Idle HL LLLHX X X X

Exit Self Refresh Idle (Self-

Refresh) LHHX X X X X X X

LH H H

Single Bank Precharge See Current

State Table HXL L HLXBSLX2

Precharge all Banks See Current

State Table HXL L HLX X HX

Bank Activate Idle HXL L H H X BS Row Address 2

Write Active HXLHL L XBSLColumn 2

Write with Auto-Precharge Active HXLHL L X BS HColumn 2

Read Active HXLHLHXBSLColumn 2

Read with Auto-Precharge Active HXLHLHX BS HColumn 2

Reserved HXLH H LX X X X

No Operation Any HXLH H H X X X X

Device Deselect Any HXHX X X X X X X

Clock Suspend Mode Entry Active HLX X X X X X X X 4

Clock Suspend Mode Exit Active LHX X X X X X X X

Data Write/Output Enable Active HX X X X X LX X X 5

Data Mask/Output Disable Active HX X X X X HX X X

Power Down Mode Entry Idle/Active HLHX X X X X X X 6, 7

LH H H

Power Down Mode Exit Any (Power

Down) LHHX X X X X X X 6, 7

LH H H

1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the

Current State Truth Table.

2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1

selects bank 3.

3. Not applicable.

4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and

Write operations. One clock delay is required for mode entry and exit.

5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the

data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles.

When it activates, the Write operation at the clock is prohibited (zero clock latency).

6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device

state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in

this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.

7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.

NT5SV64M4AT(L)

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Clock Enable (CKE) Truth Table

Current State CKE Command Action Notes

Cycle Current

Cycle CS RAS CAS WE BA0,

BA1 A12 - A0

Self Refresh

HX X X X X X X INVALID 1

LH H X X X X X Exit Self Refresh with Device Deselect 2

LHLHHH X X Exit Self Refresh with No Operation 2

LHLH H LX X ILLEGAL 2

LHLHLX X X ILLEGAL 2

LHLLX X X X ILLEGAL 2

L L X X X X X X Maintain Self Refresh

Power Down

HX X X X X X X INVALID 1

LH H X X X X X Power Down mode exit, all banks idle 2

LHLX X X X X ILLEGAL 2

L L X X X X X X Maintain Power Down Mode

All Banks Idle

H H H XXX Refer to the Idle State section of the

Current State Truth Table

H H LHX X 3

H H L L HX3

H H LLLHX X CBR Refresh

H H LLLL OP Code Mode Register Set 4

HLHXXX Refer to the Idle State section of the

Current State Truth Table

HL L HX X 3

HL L L HX3

HL L L L HX X Entry Self Refresh 4

HL LLLL OP Code Mode Register Set

LX X X X X X X Power Down 4

Any State

other than

listed above

H H X X X X X X Refer to operations in the Current State

Truth Table

HLX X X X X X Begin Clock Suspend next cycle 5

LHX X X X X X Exit Clock Suspend next cycle

L L X X X X X X Maintain Clock Suspend

1. For the given Current State CKE must be low in the previous cycle.

2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE

(tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising

clock after CKE goes high (see page 26).

3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more informa-

tion.

4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.

5. Must be a legal command as defined in the Current State Truth Table.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 31

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Current State Truth Table (Part 1 of 3)(See note 1)

Current State Command Action Notes

CS RAS CAS WE BA0,BA1 A12 - A0 Description

Idle

LLLL OP Code Mode Register Set Set the Mode Register 2

LLLHX X Auto or Self Refresh Start Auto or Self Refresh 2, 3

L L HLBS X Precharge No Operation

L L H H BS Row Address Bank Activate Activate the specified bank and row

LHL L BS Column Write w/o Precharge ILLEGAL 4

LHLHBS Column Read w/o Precharge ILLEGAL 4

LH H H X X No Operation No Operation

HX X X X X Device Deselect No Operation or Power Down 5

Row Active

LLLL OP Code Mode Register Set ILLEGAL

LLLHX X Auto or Self Refresh ILLEGAL

L L HLBS X Precharge Precharge 6

L L H H BS Row Address Bank Activate ILLEGAL 4

LHL L BS Column Write Start Write; Determine if Auto Precharge 7, 8

LHLHBS Column Read Start Read; Determine if Auto Precharge 7, 8

LH H H X X No Operation No Operation

HX X X X X Device Deselect No Operation

Read

LLLL OP Code Mode Register Set ILLEGAL

LLLHX X Auto or Self Refresh ILLEGAL

L L HLBS X Precharge Terminate Burst; Start the Precharge

L L H H BS Row Address Bank Activate ILLEGAL 4

LHL L BS Column Write Terminate Burst; Start the Write cycle 8, 9

LHLHBS Column Read Terminate Burst; Start a new Read cycle 8, 9

LH H H X X No Operation Continue the Burst

HX X X X X Device Deselect Continue the Burst

Write

LLLL OP Code Mode Register Set ILLEGAL

LLLHX X Auto or Self Refresh ILLEGAL

L L HLBS X Precharge Terminate Burst; Start the Precharge

L L H H BS Row Address Bank Activate ILLEGAL 4

LHL L BS Column Write Terminate Burst; Start a new Write cycle 8, 9

LHLHBS Column Read Terminate Burst; Start the Read cycle 8, 9

LH H H X X No Operation Continue the Burst

HX X X X X Device Deselect Continue the Burst

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is

being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.

3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is

entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-

enced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.

6. The minimum and maximum Active time (tRAS) must be satisfied.

7. The RAS to CAS Delay (tRCD) must occur before the command is given.

8. Column address A10 is used to determine if the Auto Precharge function is activated.

9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001 32

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read with

Auto Pre-

charge

LLLL OP Code Mode Register Set ILLEGAL

LLLHX X Auto or Self Refresh ILLEGAL

L L HLBS X Precharge ILLEGAL 4

L L H H BS Row Address Bank Activate ILLEGAL 4

LHL L BS Column Write ILLEGAL 4

LHLHBS Column Read ILLEGAL 4

LH H H X X No Operation Continue the Burst

HX X X X X Device Deselect Continue the Burst

Write with Auto

Precharge

LLLL OP Code Mode Register Set ILLEGAL

LLLHX X Auto or Self Refresh ILLEGAL

L L HLBS X Precharge ILLEGAL 4

L L H H BS Row Address Bank Activate ILLEGAL 4

LHL L BS Column Write ILLEGAL 4

LHLHBS Column Read ILLEGAL 4

LH H H X X No Operation Continue the Burst

HX X X X X Device Deselect Continue the Burst

Precharging

LLLL OP Code Mode Register Set ILLEGAL

LLLHX X Auto or Self Refresh ILLEGAL

L L HLBS X Precharge No Operation; Bank(s) idle after tRP

L L H H BS Row Address Bank Activate ILLEGAL 4

LHL L BS Column Write ILLEGAL 4

LHLHBS Column Read ILLEGAL 4

LH H H X X No Operation No Operation; Bank(s) idle after tRP

HX X X X X Device Deselect No Operation; Bank(s) idle after tRP

Row

Activating

LLLL OP Code Mode Register Set ILLEGAL

LLLHX X Auto or Self Refresh ILLEGAL

L L HLBS X Precharge ILLEGAL 4

L L H H BS Row Address Bank Activate ILLEGAL 4, 10

LHL L BS Column Write ILLEGAL 4

LHLHBS Column Read ILLEGAL 4

LH H H X X No Operation No Operation; Row Active after tRCD

HX X X X X Device Deselect No Operation; Row Active after tRCD

Current State Truth Table (Part 2 of 3)(See note 1)