BURR-BROWN CORP .47 vel 7aiab5 0012909 3 I D T-51-/1 BURR-BROWNe oa HI-508A HI-509A Single-Ended 8-Channel/Differential 4-Channel CMOS ANALOG MULTIPLEXERS FEATURES e ANALOG OVERVOLTAGE PROTECTION: 70Vp-p e NO CHANNEL INTERACTION DURING OVERVOLTAGE e ESD RESISTANT e BREAK-BEFORE-MAKE SWITCHING e ANALOG SIGNAL RANGE: +15V e STANDBY POWER: 7.5mW typ e TRUE SECOND SOURCE DESCRIPTION The HI-508A is an 8-channel single-ended analog multiplexer and the HI-509A is a 4-channel differ- ential multiplexer. The HI-508A and HI-509A multiplexers have input overvoltage protection. Analog input voltages may exceed either power supply voltage without damaging the device or disturbing the signal path of other channels. The protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand 70Vp-p signal levels and standard ESD tests. Signal sources are protected from short circuits should multiplexer power loss occur; each input presents a 1k(Q resistance under this condition. Digital inputs can also sustain continuous faults up to 4V greater than either supply voltage. These features make the HI-508A and HI-509A ideal for use in systems where the analog signals originate from external equipment or separately powered sources. The HI-508A and HI-509A are fabricated with Burr- Browns dielectrically isolated CMOS technology. The multiplexers are available in a hermetic ceramic DIP or plastic DIP. Commercial (0C to +75C) and military (55C to +125C) versions are available. FUNCTIONAL DIAGRAMS In 1 O=AA 7 =O Out 1kQ In2O5 1kQ ~|Decoder/ Driver e e in8O- tat tt baa Overvoltage Clamp and { | 5V Level Signal Ref Shift lsofation *Digital Input Protection i tl i 6646 6 HI-808A Ao Ar Az En iniAdo= In4AO=s In1BO= tn 4BO lsolation * *Digital input Protection fl maa * ~oe+ Out A 1kQ \ 1kQ | A { itt | =O Out B 1kQ iz ! ' ' | Decoder/ 1kO HH { 4 Driver l 1 it b-~~-4 L i Ss > Overvoltage Clamp and 5V Level Signal Ref Shift 66 6 Hi-s09A AoA, En international Airport Industrial Park - P.O. Box 11400 - Tucson, Arizona 65734 - Tel. (602) 746-1161 - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491 1988 Burr-Brown Corporation PDS-775 Printed in U.S.A. February, 1988SPECIFICATIONS BURR-BROWN CORP 4? vel L7313b5 0012910 0 i T-sl-l/ ELECTRICAL Supplies = +15V, 15V; Van (Logic Level High) = +4.0V, Va (Logic Level Low) = +0.8V unless otherwise specified. - HI-508/HI-509A-2 HI-508/HI-509A-5 PARAMETER TEMP MIN TYP MAX MIN TYP MAX UNITS ANALOG CHANNEL CHARACTERISTICS Vs, Analog Signal Range Full 15 +15 15 +15 v Rox, On Resistance +25C - 1.2 1.5 1.6 1.8 kn Full 1.5 1.8 1.8 2.0 ka Is (OFF), Off input Leakage Current +25C 0.03 0.03 nA Full 50 50 nA Ip (OFF), Off Output Leakage Current +25C 0.1 0.1 nA HI-508A Full 200 200 nA HI-509A Full 100 100 nA lo (OFF) with Input Overvoltage Applied +25C 4.0 4.0 nA Full 2.0 : HA Ip (ON), On Channel! Leakage Current +25C 0.1 01 nA HI-508A Full 200 200 nA HI-509A Full 100 100 nA lower Differential Off Output Leakage Current (HI-509A Only) Full 50 50 nA DIGITAL INPUT CHARACTERISTICS Va, Input Low Threshold Full 0.8 0.8 Vv Van, Input High Threshold Full 4.0 4.0 Vv Ia, Input Leakage Current (High or Low) Full 1.0 1.0 pA SWITCHING CHARACTERISTICS ta, Access Time +25C 0.5 0.5 iT) Full 1.0 1.0 Bs toren, Break-Before-Make Delay +25C 25 80 25 80 ns ton (EN), Enable Delay (ON) +25C 300 500 300 ns Full 1000 1000 ns torr (EN), Enable Delay (OFF) +25C 300 500 300 ns Full 7000 7000 ns Settling Time: (0.1%) +25C 1.2 1.2 HS (0.01%) +25C 3.5 3.5 HS OFF Isolation +25C 50 68 50 68 dB Cs (OFF), Channel Input Capacitance +25C 5 5 pF Cp (OFF), Channel Output Capacitance: HI-508A +25C 25 25 pF HI-509A +25C 12 12 pF Ca, Digital Input Capacitance +25C 5 5 pF Cos (OFF), Input to Output Capacitance +25C 0.1 0.1 pF POWER REQUIREMENTS Pp, Power Dissipation Full 75 75 mw H+, Current Full 0.5 2.0 0.5 2.0 mA I-, Current Full 0.02 1.0 0.02 1.0 mA NOTES: (1) Vour =210V, lour=100nA. (2) Analog overvoltage = 33V. recommended. (4) Digital input leakage is primarily due to the clamp diodes. Typical leakage is less than 1nA at 25C. (3) To drive from DTL/TTL circuits, 1kQ pull-up resistors to +5.0V supply are (5) Ven = 0.8V, Ri = 1kQ, Ci. = 15pF, Ve = 7Vrms, f = 100kHz. Worst-case isolation occurs on channel 4 due to proximity of the output pins. (6) Ven, Va = OV or 4.0V. TRUTH TABLES HI-508A HI-509A ABSOLUTE MAXIMUM RATINGS ON : ON Voltage between supply pins..:......-+ cevgeeees deceeeee ween A4V Az | Ar | Ao | EN CHANNEL CHANNEL V+ tO QFOUN .... cece ee sere ett e cere ees eer enone 1ae 22V xilxixte None A: | Ao | EN PAIR - V to ground ....... sevens tieeeeeeees se eeeenes . a L L L IH 1 x | x L None Digital input overvoltage Ven, Va: Vsupriy (+)......- see Voeuppty () cccesereseneneeces 4V L}|tLH] 4H 2 L | LH 1 . . L H L H 3 L H H 2 or 20mA, whichever occurs first. Analog input overvoltage Vs: Vsurpty (+)..+++-sseceeeeeeeeres +20V LiH|H] A 4 H|L]H 3 Y : Vsurpty (). ++ 20V H]|L]L)]H 5 H|H|H 4 . HittlHIH 6 Continuous current, S OF D ......ces eee senseereseeceeee seeee 20MA HIH L H 7 Peak current, $ or D (pulsed at ims, 10% duty cycle max) ..... 40mA HiH|LHIH 8 Power dissipation .........cceeesceeesenesreeeees seeneeeene 1.28W Operating temperature range: HI-508A/509A-2 ... 55C to +125C HI-508A/509A-5 ...,... 0C to +75C Storage temperature range ......- eee eeeeeeseeeee 65C to +150C The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shail be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. *Derate 12.8mW/C above Ta = +75C. NOTE: (1). Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied.BURR-BROWN CORP 97 Def} 173135 OoOLeILL 1 pots PRICES ORDERING INFORMATION MODEL 1-24 . 25-99 100+ MODEL DESCRIPTION TEMP RANGE PACKAGE HI3-0508A-5 $10.45 $ 8.20 $ 7.35 HI3-0508A-5 8-Channel 0C to 16-Pin H11-0508A-5 11.15 9.20 8.25 Single-Ended +75C Plastic DIP HIN-0508A-2 25.15 20.85 17.35 HI1-0508A-5 8-Channel 0C to 16-Pin HI3-0509A-5 10.45 8.20 7.35 Single-Ended +75C CERDIP HI1-0509A-5 11.15 9.20 8.25 HI1-0509A-2 25.15 20.85 17.35 HI1-0508A-2 8-Channel 55C to 16-Pin Single-Ended +125C CERDIP HI3-0509A-5 4-Channel 0C to 16-Pin Differential! +75C Plastic DIP Hi1-0509A-5 4-Channel 0C to 16-Pin Differential +75C CERDIP HH-0509A-2 4-Channel 55C to 16-Pin Differential +125C CERDIP MECHANICAL Plastic DIP Package L DIM| MIN | MAX 800 785 woos > Fie i NOTE: Leads in true position within 0.010" (0.25mm) R at MMC at seating plane. PINS: Pin material and plating N composition conform to method Le F 2003 (solderability) of MIL-STD- D 883 (except paragraph 3.2). CASE: Plastic G Seating Plane Ceramic DIP Package A ~ INCHES Le DIM [MIN | _MAX ~~ # B _t 015 | 083 J 030 | _.070 Denotes Pin 1 -100 BASIC M.! 100 = ' NOTE: Leads in true position 300 BASIC within 0.010" (0.25mm) R at MMC =| 1 a N at seating plane. et Seating Plane PIN CONFIGURATIONS Top View Top View 4.01 160 A Ati 160 A En 2 15p) Az En 2 151) Ground Vsurew 3 140) Ground Vsurery (3 140) +Vsupety int 4 130 +Vsurpi IniA 4 180) In1B In2 5 127 Ins In2a 5 120 In2B Ind 6 1100 In6 In38A 6 110 In3B In4 7 100 In7 nda G7 100 in4B Out 8 9D In8 OutA 08 90 OutB HIH1-508A (ceramic) HI1-509A (ceramic) HI3-508A (plastic) HI3-509A (plastic)DISCUSSION OF PERFORMANCE DC CHARACTERISTICS The static or DC transfer accuracy of transmitting the multiplexer input voltage to the output depends on the channel ON resistance (Ron), the load impedance, the source impedance, the load bias current and the multi- plexer leakage current. Single-Ended Multiplexer Static Accuracy The major contributors to static transfer accuracy for single-ended multiplexers are: Source resistance loading error Multiplexer ON resistance error DC offset error caused by both load bias current and multiplexer leakage current. Resistive Loading Errors The source and load impedances will determine the input resistive loading errors. To minimize these errors: @ Keep loading impedance as high as possible. This minimizes the resisitive loading effects of the source resistance and multiplexer ON resistance. As a guide- line, load impedances of 10 or greater will keep resistive loading errors to 0.002% or less for 10000 source impedances. A 100 load impedance will increase source loading error to 0.2% or more. @ Use sources with impedances as low as possible. A 10002 source resistance will present less than 0.001% loading error and 10k source resistance will increase source loading error to 0.01% with a 10 load impe- dance. Input resistive loading errors are determined by the following relationship: (see Figure 1) Source and Multiplexer Resistive Loading Error _ __Rs+Ron (Rs + Ron) > Ret Ron + Ri 100% where Rs = source resistance Rx = load resistance Ron = multiplexer ON resistance Input Offset Voltage Bias current generates an input OFFSET voltage as result of the IR drop across the multiplexer ON resistance and source resistance. A load bias current of 10nA will generate an offset voltage of 20V if a 1kO source is used. In general, for the HI-508A, the OFFSET voltage at the output is determined by: Vorrset = (In + It) (Ron + Rs) where Ip = Bias current of device multiplexer is driving I, = Multiplexer leakage current Ron = Multiplexer ON resistance Rs = Source resistance BURR-BROWN CORP 47 pe 1731365 OOL2912 3 iy D-7- S/-// Differential Multiplexer Static Accuracy Static accuracy errors in a differential multiplexer are difficult to control, especially when it is used for multi- plexing low-level signals with full-scale ranges of 10mV to 100mV. The matching properties of the multiplexer, source and output load play a very important part in determining the transfer accuracy of the multiplexer. The source impedance unbalance, common-mode impedance, load bias current mismatch, load differenital impedance mis- match, and common-mode impedance of the load all contribute errors to the multiplexer. The multiplexer ON resistance mismatch, leakage current mismatch and ON resistance also contribute to differenital errors. The effects of these errors can be minimized by following the general guidelines described in this section, especially for low-level multiplexing applications. Refer to Figure 2. Load (Output Device) Characteristics @ Use devices with very low bias current. Generally, FET input amplifiers should be used for low-level signals less than 50mV FSR. Low bias current bipolar input amplifiers are acceptable for signal ranges higher than 50mV FSR. Bias current matching will determine the input offset. @ The system DC common-mode rejection (CMR) can never be better than the combined CMR of the multiplexer and driven load. System CMR will be less than the device which has the lower CMR figure. @ Load Impedances, differenital and common-mode, should be 10 or higher. Ret Ron @ Ibias -O- > 1) mo to4 Vea i . g = s !Measured | Rore i Voltage ! FG eds FIGURE |. HI-508A DC Accuracy Equivalent Circuit. Rona tas A Rsta Rsis ) g > Ronie Rsaa Roreaa r | | I | I | | | Lo Rorras Rsae FIGURE 2. HI-509A DC Accuracy Equivalent Circuit.BURR-BROWN CORP 97 DE} 1731ab5 OoLed2a 5 Jo tT? S/-// Source Characteristics The source impedance unbalance will produce offset, common-mode and channel-to-channel gain-scatter errors. Use sources which do not have large impedance unbalances if at all possible. @ Keep source impedances as low as possible to minimize resistive loading errors. @ Minimize ground loops. If signal lines are shielded, ground all shields to a common point at the system analog common. If the HI-509A is used for multiplexing high-level signals of +IV to +10V full-scale ranges, the foregoing pre- cautions should still be taken, but the parameters are not as critical as for low-level signal applications. DYNAMIC CHARACTERISTICS Settling Time The gate-to-source and gate-to-drain capacitance of the CMOS FET switches, the RC time constants of the source and the load determine the settling time of the multiplexer. Governed by the charge transfer relation i = C (dV/dt), the charge currents transferred to both load and source by the analog switches are determined by the amplitude and rise time of the signal driving the CMOS FET switches and the gate-to-drain and gate-to-source junction capacitances as shown in Figures 3 and 4. Using this relationship, one can see that the amplitude of the switching transients, seen at the source and load, decrease proportionally as the capacitance of the load and source increase. The tradeoff for reduced switching transient amplitude is increased settling time. In effect, the amp- litude of the transients seen at the source and load are: dVi = (i/C) dt where i= C (dV/dt) of the CMOS FET switches C = load or source capacitance The source must then redistribute this charge, and the effect of source resistance on settling time is shown in the Typical Performance Curves. This graph shows the settling time for a 20V step change on the input. The settling time for smaller step changes on the input will be less than that shown in the curve. HI-508A Channel Source -xX T %~ e Load Node A Ci Re FIGURE 3. Settling Time EffectsHI-508A. FIGURE 4. Settling and Common-Mode Effects HI-509A. Switching Time This is the time required for the CMOS FET to turn ON after a new digital code has been applied to the Channel Address inputs. It is measured from the 50 percent point of the address input signal to the 90 percent point of the analog signal seen at the output for a 10V signal change between channels. Crosstalk Crosstalk is the amount of signal feethrough from the three (HI-509A) or seven (HI-508A) OFF channels appearing at the multiplexer output. Crosstalk is caused by the voltage divider effect of the OFF channel OFF resistance and junction capacitances in series with the Ron and Rs impedances of the ON channel. Crosstalk is measured with a 20Vp-p 1kHz sine wave applied to all OFF channels. The crosstalk for these multiplexers is shown in the Typical Performance Curves. Common-Mode Rejection (HI-509A Only) The matching properties of the load, multiplexer and source affect the common-mode rejection (CMR) capa- bility of a differentially multiplexed system. CMR is the ability of the multiplexer and input amplifier to reject signals that are common to both inputs, and to pass on only the signal difference to the output. For the HI-509A, protection is provided for common-mode signals of +20V above the power supply voltages with no damage to the analog switches. The CMR of the HI-509A and Burr-Browns INAIIO Instrumentation Amplifier is 10dB at DC to 10Hz (G = 100) with a 6dB/octave rolloff to 70dB at 1000Hz. This measurement of CMR is shown in the Typical Perfor- mance Curves and is made with a Burr-Brown model INAHO Instrumentation Amplifier connected for gains of 10, 100, and 500. Factors which will degrade multiplexer and system DC CMR are:BURR-BROUN CORP 47 DEB 1732365 oo1esa4 7 ff T= SIH @ Amplifier bias current and differential impedance mismatch Load impedance mismatch @ Multiplexer impedance and leakage current mismatch Load and source common-mode impedance AC CMR orolloff is determined by the amount of common- mode capacitances (absolute and mismatch) from each TYPICAL DYNAMIC PERFORMANCE CURVES Typical at +25C unless otherwise noted. SETTLING TIME VS SOURCE RESISTANCE FOR 20V STEP CHANGE 1k 100 g To +0.01% E - 10 oD 8 _ 1 0.1 0.01 0.1 1 10 100 Source Resistance (kQ) signal line to ground. Larger capacitances will limit CMR at higher frequencies; thus, if good CMR is desired at higher frequencies, the common-mode capaci- tances and unbalance of signal lines and multiplexer-to- amplifier wiring must be minimized. Use twisted-shielded- pair signal lines wherever possible. CROSSTALK VS SIGNAL FREQUENCY 0.1 0.01 0.001 Crosstalk (% of Off Channel Signal) (ZL 10 100 1k 0.0001 1 10k Signal Frequency (Hz) COMBINED CMR VS FREQUENCY HI-509A AND INA1I0 120 100 80 40 Common-Mode Rejection (dB) 20 100 ik 10k Frequency (Hz)BURR-BROWN CORP 9? DE 1732365 OoLeq1s gor srl SWITCHING WAVEFORMS Typical at +25C unless otherwise noted. BREAK-BEFORE-MAKE DELAY (toren) Hl i = Va Input Van = 4.0V r 2V/Div | Address Drive *HI-508A +5V ov (Va) As int oO In2 Va A Thru In7FO7 HHH t ape Teveyp erty ee sane wee! Output A - 50% 50% soo! In8 Vour F. Output M out + 0.5V/Div [ it => = O- En GND =o es - 12.5pF + tore 44.0V 0 oh 1kO + * 100ns/Div *Similar connection for HI-509A. ENABLE DELAY (ton (EN), tore (EN)) ENABLE DRIVE Van = 4.0V *HI-508A iniPO +10V Aa SH A: In2 thru in8 -O-_ 7 Ao = En Out GND Pj ton (EN) I< | son = 1kQ 12.5pF ! [ Pl tor (EN) . . 100ns/Div *Similar connection for HI-509A. PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS Unless otherwise specified: Ts = +25, Vs = +16V, Van = +4V, Var = 0.8V and Vace = Open. ON RESISTANCE VS ANALOG INPUT VOLTAGE, SUPPLY VOLTAGE Ron = V2/100"A ON RESISTANCE VS ANALOG INPUT VOLTAGE NORMALIZED ON RESISTANCE VS SUPPLY VOLTAGE On Resistance (kQ) 10 -8 -6 -4 -2 0 2 4 6 8 10 Analog Input (V) +125C >T,2 Vin = Normalized On Resistance (Referred to Value at 15V) 0.8 +5 +6 +7 +8 ++9 +410 +11 412 +13 +414 +415 Supply Voltage (V)BURR-BROWN CORP 47 a 1732365 COIL O i T-S/-/) PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT) SUPPLY CURRENT VS TOGGLE FREQUENCY +15V/+10V A ) +isuppiy 10pA 25 50 75 100 125 Temperature (C) e +V < Aa *HI-50BA Inth= +10V/+5V b In2 Thru r Va 500 As in7 | 6 Ao info = 2 o En Out a a => OS sav GND Vistowy S$14pF on +5V 10MQ 0 = tsupriy = 100 1k 10k 100k 1M 10M = = tint . a Toggle Frequency (Hz) Similar connection for HI-S09A _45y/10V LEAKAGE CURRENT VS TEMPERATURE 100nA En +0.8V Out 10nA Is (OFF)(A A) lo (OFF) +10V HN < input = Fi0v Current In (OFF) L =r = Hv +0.8V 6 On Leakage = = @ Current lo ( = m ind 6 x oa a 4 ~ NOTE: (1) Two measurements per chan- Is (OFF nel: +10V/10V and 10V/+10V. (Two {00pA s( ) measurements per device for In(OFF): +10V/-10V and 10V/+10V). A) ln (ON) +10V Fi0V atHI| +4V0 Analog Input Current (mA) Analog Input Current (lin) Leakage Current Ip (OFF) H12 +15 418 421,424 +27 430 133 +31 ANALOG INPUT OVERVOLTAGE CHARACTERISTICS lo(OFF) 7 6 5 A 4 3 2 1 (yu) yueung aBeyxe07 HO nding 0 6BURR-BROWN CoRP 97 DEP} u7siaes oo1eqy7 a2 9ot-si- PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT) ACCESS TIME VS LOGIC LEVEL (High) *HI-508A 10V a Aa Inte g Va P In2 Thru In7 or . E Ay > 2 in8r--O - 3 502 Ao Probe 3 OTEn Out T > PF +4ov L_GND : 3.4 5 6 7 8 9 10 14 12 13 14 15 = Logic Level High (V) *Similar connection for HI-509A ACCESS TIME Van = 4.0V Address | ov HOV Output A je | 90% 7 | | 10V 5 | | 3 >| th 3 200ns/Div ON-CHANNEL CURRENT VS VOLTAGE +14 + => +12 <t , +125C < 2 8 L_o--o +6 S Vin +4 42 9 O +2 44 +46 +8 +10 412 414 +H6 Vin ~Voltage Across Switch (V)BURR-BROWN CORP 97 DE} 1731365 O022918 4 fo rs7-/ INSTALLATION AND OPERATING INSTRUCTIONS The ENABLE input, pin 2, is included for expansion of the number of channels on a single node as illustrated in Figure 5. With ENABLE line at a logic 1, the channel is selected by the 2-bit (HI-509A) or 3-bit (HI-508A) Channel Select Address (shown in the Truth Tables). If ENABLE is at logic 0, all channels are turned OFF, even if the Channel Adddress Lines are active. If the ENABLE line is not to be used, simply tie it to +Vsurpty. If the +15V and/or 15V supply voltage is absent or shorted to ground, the HI-509A and HI-508A multi- plexers will not be damaged; however, some signal feedthrough to the output will occur. Total package power dissipation must not be exceeded. For best settling speed, the input wiring and intercon- nections between multiplexer output and driven devices should be kept as short as possible. When driving the digital inputs from TTL, open collector output with pull- up resistors are recommended. To preserve common-mode rejection of the HI-509A, use twisted-shielded pair wire for signal lines and inter-tier connections and/or multiplexer output lines. This will help common-mode capacitance balance and reduce stray signal pickup. If shields are used, all shields should be connected as closely as possible to system analog common or to the common-mode guard driver. CHANNEL EXPANSION Single-Ended Multiplexer (H!-508A) Up to 32 channels (four multiplexers) can be connected to a single node, or up to 64 channels using nine HI- 508A multiplexers on a two-tiered structure as shown in Figures 5 and 6. 2 3 int 2 In2 Qa O-in3 Out >| HI-508A oI Group 1 Multiplexer < | Chi-8 Group 1 Output O7Ins AoA Enable 2 Ai Ao 5-Bit Direct _ Binary To #eO 3 ee 1 Counter |Group | ! 2 | tro o 4 42? I 2 | ! L RY t foal ~ | 3h | to oHt-o 2 4 } 20] 1084 | 7 2 L 1 Decoder-~) | Loa Buffered To OPA602 O51 A2 Ai Aa Group | 1/4 OPA404 a Qyinz Group 4 3 | = Oqin3 D | HI-s08A | Enable | 2 Group 4 | e | Ch25-32 < 1 al Out In Fins Settling Time to +0.01% for Rs = 1002 Two HI-508A units in parallel: 10s Four HI-509A units in parallel: 12us FIGURE 5. 32-Channel, Single-Tier Expansion. 10 oa 2 6 Out a 2 = En S -O Multiplexer g +V Int Outputs 1 s ! Out Direct ( {| HI-508A roct74 1 i lps! ~ ! En ( Slo To Other H!-508A Ch LOLS. in8 4V L bs Int Ao At Az Buffered 2 O7In2 Out OPA602 GO7FIn3 8 4/4 OPA404 211 tsoaa a | > En 804 In8 9 -O E Ao Ai Az 4y < TT 1 Seti T 3LSBs 3MSBs ettling Time to : . 6-Bit Channel +0.01% is 20us with Rs < 1000 Address Generator FIGURE 6. Channel Expansion Up to 64 Channels Using 8 X 8 Two-Tiered Expansion. Differential Multiplexer (HI-509A) Single or multitiered configurations can be used to expand multiplexer channel capacity up to 32 channels using a 32 X 1 or 16 channels using a 4 X 4 configuration. Single-Node Expansion The 32 X | configuration is simply eight (H1I-509A) units tied to a single node. Programming is accomplished with a 5-bit counter, using the 2LSBs of the counter to control Channel Address inputs Ao and A: and the 3MSBs of the counter to drive a I-of-8 decoder. The l-of-8 decoder then is used to drive the ENABLE inputs (pin 2) of the HI-509A multiplexers. Two-Tier Expansion Using a 4 X 4 two-tier structure for expansion to 16 channels, the programming is simplified. A 4-bit counter output does not require a I-of-8 decoder. The 2LSBs of the counter drive the Ao and A: inputs of the four first- tier multiplexers and the 2MSBs of the counter are applied to the Ao and A; inputs of the second-tier multiplexer. Single vs Multitiered Channel Expansion In addition to reducing programming complexity, two- tier configuration offers the added advantages over single-node expansion of reduced OFF channel current leakage (reduced OFFSET), better CMR, and a more reliable configuration if a channel should fail in the ON condition (short). Should a channel fail ON in the single-node configuration, data cannot be taken from any channel, whereas only one channel group is failed (4 or 8) in the multitiered configuration.