74VHC74M - STMICROELECTRONICS - Datasheet.Directory

September 1988

Revised March 2005

74AC574 • 74ACT574 Octal D-Type Flip-Flop wit h 3-STATE Outputs

74AC574 • 74ACT574

Octal D-Type Flip-Flop with 3-STATE Outputs

General Descript ion

The AC/ACT574 is a high-speed, low power octal flip-flop

with a buffered common Clock (CP) and a buffered com-

mon Output Enable (OE). The information presented to the

D-type inputs is stored in the flip-flops on the LOW-to-HIGH

Clock (CP) transition.

The AC/ACT574 is func tiona lly iden tical to the AC /ACT3 74

except for the pino uts.

Features

■ICC and IOZ reduced by 50%

■Inputs and outputs on oppos ite s ides of package

allowing easy interface with microprocessors

■Useful as input or output port for microprocessors

■Functionally identical to AC/ACT374

■3-STATE outputs for bus-oriented applications

■Outputs source/sink 24 mA

■ACT574 has TTL-compatible inputs

Ordering Code:

Device a l s o av ailable in Tape and R eel. Specify by appending su ffix le t te r “X” to the ordering co de.

Pb-Free package per JEDEC J-STD-020B.

FACT

is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74AC574SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74AC574PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74ACT574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74ACT574SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACT574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ACT574PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2

74AC574 • 74ACT574

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

Function Table

HIGH Voltage Level

LOW Voltage Level

Immaterial

High Impedance



LOW-to-HIGH Transition

No Change

Functional Description

The AC/ACT574 co nsists of eight edge- triggered flip-f lops

with individual D-type inputs and 3-STATE true outputs.

The buffered clock and buffered Output Enable are com-

mon to all flip-flops. The eight flip-flops will store the state

of their individual D-type inputs that meet the setup and

hold time requirements on the LOW-to-HIGH Clock (CP)

transition. Wi th th e Ou tpu t En able ( OE ) LOW, the contents

of the eight flip-flops are available at the outputs. When OE

is HIGH, the outputs go to the high impedance state. Oper-

ation of the OE input does not affect the state of the flip-

flops.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names Description

D0–D7Data Inputs

CP Clock Pulse Input

OE 3-STATE Output Enable Input

O0–O73-STATE Output s

Inputs Internal Outputs Function

OE CP D Q ON

HHL NC Z Hold

H HH NC Z Hold



L L Z Load



H H Z Load



L L L Data Available



H H H Data Available

L H L NC NC No Change in Data

L H H NC NC No Change in Data

3 www.fairchildsemi.com

74AC574 • 74ACT574

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absol ut e maximum ratings are those v alues beyond which damage

to the dev ice may occur. The databook specifi cations should be met, with-

out exception, to ensure that the system design is reliable over its power

supply, temperature, and output/input loading variables. Fairchild does not

recommend operation of FACT

circuits outside databook spec if ic at ions.

DC Electrical Characteristics for AC

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: IIN and ICC @ 3.0V are gu aranteed to be less t han or equa l t o th e respectiv e limit @ 5. 5V VCC.

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Diode Current (IIK)



0.5V



20 mA

VCC



0.5V



20 mA

DC Input Voltage (VI)



0.5V to VCC



0.5V

DC Output Diode Current (IOK)



0.5V



20 mA

VCC



0.5V



20 mA

DC O utput Voltage (VO)



0.5V to VCC



0.5V

DC Output Source

or Sink Current (IO)

50 mA

DC VCC or Ground Current

Per Output Pin (ICC or IGND)

50 mA

Storage Temperature (TSTG)



C to



150

Junction Temperature (TJ)

PDIP 140

Supply Voltage (VCC)

AC 2.0V to 6.0V

ACT 4.5V to 5.5V

Input Voltage (VI)0V to V

Output Voltage (VO)0V to V

Operating Temperature (TA)



C to



Minimum Input Edge Rate (

AC Devices

VIN from 30% to 70% of VCC

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (

ACT Devices

VIN from 0.8V to 2.0V

VCC @ 4.5V, 5.5V 125 mV/ns

Symbol Parameter VCC TA



C to



CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT

0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC



0.1V

5.5 2.75 3.85 3.85

VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT

0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC



0.1V

5.5 2.75 1.65 1.65

VOH Minimum HIGH Level 3.0 2.99 2.9 2.9

Output Voltage 4.5 4.49 4.4 4.4 V IOUT



5.5 5.49 5.4 5.4

3.0 2.56 2.46 VIN

VIL or VIH

4.5 3.86 3.76 V IOH



12 mA

5.5 4.86 4.76 IOH



24 mA IOH

IOH



24 mA (Note 2)

VOL Maximum LOW Level 3.0 0.002 0.1 0.1

Output Voltage 4.5 0.001 0.1 0.1 V IOUT

5.5 0.001 0.1 0.1 VIN

VILor VIH

3.0 0.36 0.44 IOL

12 mA

4.5 0.36 0.44 V IOL

24 mA

5.5 0.36 0.44 IOL

24 mA (Note 2)

IIN (Note 4) Maximum Input Leakage Current 5.5

0.1

1.0

VCC, GND

IOZ Maximum VI (OE)

VIL, VIH

3-STATE 5.5

0.25

2.5

VCC, VGND

Leakage Current VO

VCC, GND

IOLD Minimum Dynamic 5.5 75 mA VOLD

1.65V

IOHD Output Current (Note 3) 5.5



75 mA VOHD

3.85V

ICC (Note 4) Maximum Quiescent S upply Current 5.5 4.0 40.0

VCC or GND

www.fairchildsemi.com 4

74AC574 • 74ACT574

DC Electrical Characteristics for ACT

Note 5: All outputs loaded; thresholds on input associated with output under test.

Note 6: Maximum test du ration 2.0 m s, one output loaded at a time.

AC Electrical Characteristics for AC

Note 7: Voltage Ran ge 3.3 is 3. 3V

0.3V

Voltag e R ange 5.0 is 5.0V

0.5V

Symbol Parameter VCC TA



C to



CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 VVOUT

0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC



0.1V

VIL Maximum LOW Level 4.5 1.5 0.8 0.8 VVOUT

0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC



0.1V

VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI

OUT



5.5 5.49 5.4 5.4 VIN

VILor VIH

4.5 3.86 3.76 V IOH



24 mA

5.5 4.86 4.76 IOH



24 mA (Note 5)

VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI

OUT

Output Voltage 5.5 0.001 0.1 0.1 VIN

VILor VIH

4.5 0.36 0.44 V IOL

24 mA

5.5 0.36 0.44 IOL

24 mA (Note 5)

IIN Maximum Input 5.5

0.1

1.0

VCC, GND

Leakage Current

IOZ Maximum 3-STATE 5.5

0.25

2.5

AVI

VIL, VIH

Leakage Current VO

VCC, GND

ICCT Maximum ICC/Input 5.5 0.6 1.5 mA VI

VCC



2.1V

I]OLD Minimum Dynamic 5.5 75 mA VOLD

1.65V

IOHD Output Current (Note 6) 5.5



75 mA VOHD

3.85V

ICC Maximum Quiescent 5.5 4.0 40.0

AVIN

VCC

Supply Curre nt or GND

VCC TA





C to



Symbol Parameter (V) CL

50 pF CL

50 pF Units

(Note 7) Min Typ Max Min Max

fMAX Maximum Clock 3.3 75 112 60 MHz

Frequency 5.0 95 153 85

tPLH Propagation Delay 3.3 3.5 8.5 13.5 3.5 15.0 ns

CP to On5.0 2.0 6.0 9.5 2.0 11.0

tPHL Propagation Delay 3.3 3.5 7.5 12.0 3.5 13.5 ns

CP to On5.0 2.0 5.5 8.5 2.0 9.5

tPZH Output Enable Time 3.3 2.5 7.0 11.0 2.5 12.0 ns

5.0 2.0 5.0 8.5 2.0 9.0

tPZL Output Enable Time 3.3 3.0 6.5 10.5 3.0 11.5 ns

5.0 2.0 5.0 8.0 1.5 9.0

tPHZ Output Disable Time 3.3 3.5 7.5 12.0 2.5 13.0 ns

5.0 2.0 6.0 9.5 1.5 10.5

tPLZ Output Disable Time 3.3 2.0 5.5 9.0 1.5 10.0 ns

5.0 1.0 4.5 7.5 1.0 8.5

5 www.fairchildsemi.com

74AC574 • 74ACT574

AC Operating Requirements for AC

Note 8: Voltag e R ange 3.3 is 3.3V

0.3V

Voltage Range 5.0 is 5.0V

0.5V

AC Electrical Characteristics for ACT

Note 9: Volta ge Range 5. 0 is 5. 0V

0.5V

AC Operating Requirements for ACT

Note 10: Voltage Range 5.0 is 5.0V

0.5V

Capacitance

VCC TA





C to



Symbol Parameter (V) CL

50 pF CL

50 pF Units

(Note 8) Typ Guaran teed Minim um

tSSet-Up Time, HIGH or LOW 3.3 0.5 2.5 3.0 ns

Dn to CP 5.0 0 1.5 2.0

tHHold Time, HIGH or LOW 3.3



0.5 1.5 1.5 ns

Dn to CP 5.0 0 1.5 1.5

tWCP Pulse Width 3.3 3.5 6.0 7.0 ns

HIGH or LOW 5.0 2.0 4.0 5.0

VCC TA





C to



Symbol Parameter (V) CL

50 pF CL

50 pF Units

(Note 9) Min Typ Max Min Max

fMAX Maximum Clock Frequency 5.0 100 110 85 ns

tPLH Propagation Delay 5.0 2.5 7.0 11.0 2.0 12.0 ns

CP to On

tPHL Propagation Delay 5.0 2.0 6.5 10.0 1 .5 11.0 ns

CP to On

tPZH Output Enable Time 5.0 2.0 6.4 9.5 1.5 10.0 ns

tPZL Output Enable Time 5.0 2.0 6.0 9.0 1.5 10.0 ns

tPHZ Output Disable Time 5.0 2.0 7.0 10.5 1.5 11.5 ns

tPLZ Output Disable Time 5.0 2.0 5.5 8.5 1.5 9.0 ns

VCC TA





C to



Symbol Parameter (V) CL

50 pF CL

50 pF Units

(Note 10) Typ Guaranteed Minimum

tSSet-Up Time, HIGH or LOW 5.0 1.5 2.5 ns

Dn to CP

tHHold Time, HIGH or LOW 5.0



0.5 1.0 ns

Dn to CP

tWCP Pulse Width 5.0 2.5 4.0 ns

HIGH or LOW

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC

OPE N

CPD Power Dissipation Capacitance 40.0 pF VCC

5.0V

www.fairchildsemi.com 6

74AC574 • 74ACT574

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

7 www.fairchildsemi.com

74AC574 • 74ACT574

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

www.fairchildsemi.com 8

74AC574 • 74ACT574

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

9 www.fairchildsemi.com

74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does not assum e any responsibility for use of any circuitry described, no cir cuit patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

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which, (a) are intended for surgical implant into the

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to perform when properly used in accordance with

instruct ions fo r use provided in the l abe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.