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© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
FAN2106 — 3-24 V Input, 6 A, High-Efficiency,
Integrated Synchronous Buck Regulator
Features
6 A Output Current
Wide Input Range: 3 V - 24 V
Output Voltage Range: 0.8 V to 80% VIN
Over 95% Peak Efficiency
1% Reference Accuracy Over Temperature
Programmable Frequency Operation: 200 KHz to
600 KHz
Fully Synchronous Operation with Integrated
Schottky Diode on Low-Side MOSFET Boosts
Efficiency
Internal Bootstrap Diode
Internal Soft-Start
Power-Good Signal
Starts on Pre-Biased Outputs
Accepts Ceramic Capacitors on Output
External Compensation for Flexible Design
Programmable Current Limit
Under-Voltage, Over-Voltage, and Thermal
Protections
5x6 mm, 25-Pin, 3-Pad MLP Package
Applications
Servers & Telecom
Graphics Cards & Displays
Computing Systems
Point-of-Load Regulation
Set-Top Boxes & Game Consoles
Description
The FAN2106 is a highly efficient, small-footprint,
constant-frequency, 6 A, integrated synchronous
buck regulator.
The FAN2106 contains both synchronous MOSFETs
and a controller/driver with optimized interconnects in
one package, which enables designers to solve high-
current requirements in a small area with minimal
external components. Integration helps to minimize
critical inductances, making component layout simpler
and more efficient compared to discrete solutions.
The FAN2106 provides for external loop
compensation, programmable switching frequency,
and current limit. These features allow design
flexibility and optimization. High-frequency operation
allows for all-ceramic solutions.
The summing current-mode modulator uses lossless
current sensing for current feedback and over-current
protection. Voltage feedforward helps operation over
a wide input voltage range.
Fairchild’s advanced BiCMOS power process,
combined with low-RDS(ON) internal MOSFETs and a
thermally efficient MLP package, provide the ability to
dissipate high power in a small package.
Output over-voltage, under-voltage, over-current, and
thermal shutdown protections help protect the device
from damage during fault conditions. FAN2106
prevents pre-biased output discharge during startup
in point-of-load applications.
Related Resources
AN-8022 — TinyCalc™ Calculator User Guide
TinyCalc™ Calculator Design Tool
Ordering Information
Part Number
Operating
Temperature Range
Package
Packing Method
FAN2106MPX
-40°C to 85°C
Molded Leadless Package (MLP) 5 x 6 mm
Tape and Reel
FAN2106EMPX
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 2
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical Application Diagram
Figure 1. Typical Application
Block Diagram
Figure 2. Block Diagram
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 3
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Pin Configuration
1
2
3
4
5
6
7
8
12 11 10 9
24 25
20
19
18
17
16
15
14
13
COMP
FB
R(T)
ILIM
AGND
VCC
EN
PGOOD
RAMP
NC
PGND
PGND
PGND
BOOT
VIN
VIN
VIN
VIN
SW
SW
SW
SW
SW
SW
SW
2221 23
P3
GND
P1
SW
P2
VIN
Figure 3. MLP 5 x 6 mm Pin Configuration (Bottom View)
Pin Definitions
Name
Description
SW
Switching Node. Junction of high-side and low-side MOSFETs.
VIN
Power Input Voltage. Connect to the main input power source.
PGND
Power Ground. Power return and Q2 source.
BOOT
High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC
includes an internal synchronous bootstrap diode to recharge the capacitor on this pin to
VCC when SW is LOW.
PGOOD
Power-Good Flag. An open-drain output that pulls LOW when FB is outside the limits
specified in electrical specs. PGOOD does not assert HIGH until the fault latch is enabled.
EN
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched fault condition. This input has an internal pull-up when the IC is
functioning normally. When a latched fault occurs, EN is discharged by a current sink.
VCC
Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin.
This pin should be decoupled to AGND through a >1 µF X5R/X7R capacitor.
AGND
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
ILIM
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the current-
limit trip threshold lower than the default setting.
R(T)
Oscillator Frequency. A resistor (RT) from this pin to AGND sets the PWM switching
frequency.
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
COMP
Compensation. Error amplifier output. Connect the external compensation network
between this pin and FB.
NC
No Connect. This pin is not used.
RAMP
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the ramp
amplitude and provides voltage feedforward functionality.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 4
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Parameter
Conditions
Min.
Max.
Unit
VIN to PGND
28
V
VCC to AGND
AGND = PGND
6
V
BOOT to PGND
35
V
BOOT to SW
-0.3
6.0
V
SW to PGND
Continuous
-0.5
24.0
V
Transient (t < 20 ns, f < 600 KHz)
-5.0
30.0
All other pins
-0.3
VCC+0.3
V
ESD
Human Body Model, JEDEC JESD22-A114
2.0
kV
Charged Device Model, JEDEC JESD22-C101
2.5
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VCC
Bias Voltage
VCC to AGND
4.5
5.0
5.5
V
VIN
Supply Voltage
VIN to PGND
3
24
V
TA
Ambient Temperature
-40
+85
°C
TJ
Junction Temperature
+125
°C
fSW
Switching Frequency
200
600
KHz
Thermal Information
Symbol
Parameter
Min.
Typ.
Max.
Unit
TSTG
Storage Temperature
-65
+150
°C
TL
Lead Soldering Temperature, 10 Seconds
+300
°C
JC
Thermal Resistance: Junction-to-Case
P1 (Q2)
4
°C/W
P2 (Q1)
7
P3
4
J-PCB
Thermal Resistance: Junction-to-Mounting Surface
35(1)
°C/W
PD
Power Dissipation, TA = 25°C
2.8(1)
W
Note:
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 26. Actual results
are dependent on mounting method and surface related to the design.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 5
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Electrical Specifications
Electrical specifications are the result of using the circuit shown in Figure 1 with VIN = 12 V, unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power Supplies
VCC Current
SW = Open, FB = 0.7 V, VCC = 5 V,
fSW = 600 KHz
8
12
mA
Shutdown: EN = 0, VCC = 5 V
7
10
µA
VCC UVLO Threshold
Rising VCC
4.1
4.3
4.5
V
Hysteresis
300
mV
Oscillator
Frequency
RT = 50 K
255
300
345
KHz
RT = 24 K
540
600
660
KHz
Minimum On-Time(2)
50
65
ns
Ramp Amplitude, Peak-to-Peak
16 VIN, 1.8 VOUT, RT = 30 K,
RRAMP = 200 K
0.53
V
Minimum Off-Time(2)
100
150
ns
Reference
Reference Voltage (VFB)(3)
795
800
805
mV
Error Amplifier
DC Gain(2)
VCC = 5 V
80
85
dB
Gain Bandwidth Product(2)
12
15
MHz
Output Voltage (VCOMP)
0.4
3.2
V
Output Current, Sourcing
VCC = 5 V, VCOMP = 2.2 V
1.5
2.2
mA
Output Current, Sinking
VCC = 5 V, VCOMP = 1.2 V
0.8
1.2
mA
FB Bias Current
VFB = 0.8 V, TA = 25°C
-850
-650
-450
nA
Protection and Shutdown
Current Limit
RILIM Open, fSW = 500 KHz, VOUT =
1.8 V, RRAMP = 200 K16 Consecutive
Cycles
6
8
10
A
ILIM Current
VCC = 5 V, TA = 25°C
-11
-10
-9
µA
Over-Temperature Shutdown
Internal IC Temperature
+155
°C
Over-Temperature Hysteresis
+30
°C
Over-Voltage Threshold
2 Consecutive Clock Cycles
110
115
120
%VOUT
Under-Voltage Shutdown
16 Consecutive Clock Cycles
68
73
78
%VOUT
Fault Discharge Threshold
Measured at FB Pin
250
mV
Fault Discharge Hysteresis
Measured at FB Pin (VFB ~500 mV)
250
mV
Soft-Start
VOUT to Regulation (T0.8)
Frequency = 600 KHz
5.3
ms
Fault Enable/SSOK (T1.0)
6.7
ms
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 6
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Electrical Specifications (Continued)
Electrical specifications are the result of using the circuit shown in Figure 1 with VIN= 12 V, unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Unit
Control Functions
EN Threshold, Rising
VCC = 5 V
1.35
2.00
V
EN Hysteresis
VCC = 5 V
250
mV
EN Pull-Up Resistance
VCC = 5 V
800
K
EN Discharge Current
Auto-Restart Mode, VCC = 5 V
1
µA
FB OK Drive Resistance
800
PGOOD Threshold
(Compared to VREF)
FB < VREF, 2 Consecutive Clock Cycles
-14
-11
-8
%VREF
FB > VREF, 2 Consecutive Clock Cycles
+7
+10
+13
%VREF
PGOOD Output Low
IOUT < 2 mA
0.4
V
Notes:
2. Specifications guaranteed by design and characterization; not production tested.
3. See Figure 4 for Temperature Coefficient
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 7
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical Characteristics
0.990
0.995
1.000
1.005
1.010
-50 0 50 100 150
Temperature (oC)
V FB
0.80
0.90
1.00
1.10
1.20
-50 0 50 100 150
Temperature (oC)
I FB
Figure 4. Reference Voltage (VFB) vs. Temperature,
Normalized
Figure 5. Reference Bias Current (IFB) vs.
Temperature, Normalized
0
300
600
900
1200
1500
020 40 60 80 100 120 140
RT (K)
Frequency (KHz)
0.98
0.99
1.00
1.01
1.02
-50 0 50 100 150
Temperature (oC)
Frequency
Figure 6. Frequency vs. RT
Figure 7. Frequency vs. Temperature, Normalized
0.60
0.80
1.00
1.20
1.40
1.60
-50 0 50 100 150
Temperature (oC)
RDS
0.96
0.98
1.00
1.02
1.04
-50 0 50 100 150
Temperature (oC)
I ILIM
Figure 8. RDS vs. Temperature, Normalized
(VCC = VGS = 5 V)
Figure 9. ILIM Current (IILIM) vs. Temperature,
Normalized
Q1 ~0.32 %/oC
Q2 ~0.35 %/oC
300 kHz
600 kHz
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 8
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Application Circuit
SW
P1
PGND
P3
VOUT
P2 VIN
BOOT
1
COMP
VCC
PGOOD
8-20 VIN
EN
+5V
AGND
RAMP
20
15
25
13
14
16
18
R(T)
17
ILIM
24
19
FB
VOUT
2 x 4.7µ
* Inter-Technical
SC7232-2R2M
390p
1.5
4 x 22µ
3.3n
200K
200K
2.00K 30.1K
4.7n
1.0µ 10K
2.49K
2.49K
56p4.7n
62
4.7n 0.1µ
2.2µ *
X5R
X7R
X5R
NC
Figure 10. Application Circuit: 1.8 VOUT, 500 KHz
Typical Performance Characteristics
Typical operating characteristics using the circuit shown in Figure 10. VIN=12 V, VCC=5 V, unless otherwise specified.
70
75
80
85
90
95
100
0 1 2 3 4 5 6
Load (A)
Efficiency (%)
0
200
400
600
800
1000
1200
1400
0 1 2 3 4 5 6
Load (A)
Dissipation (mW)
Figure 11. 1.8 VOUT Efficiency Over VIN vs. Load
Figure 12. 1.8 VOUT Dissipation Over VIN vs. Load
70
75
80
85
90
95
100
0 1 2 3 4 5 6
Load (A)
Efficiency (%)
70
75
80
85
90
95
100
0 1 2 3 4 5 6
Load (A)
Efficiency (%)
Figure 13. 1.8 VOUT Efficiency Over Frequency vs.
Load (Circuit Value Changes)
Figure 14. 3.3 VOUT Efficiency vs. Load
(Circuit Value Changes)
8 VIN 12 VIN 18 VIN
300 kHz 500 kHz 700 kHz
8 VIN 12 VIN 18 VIN
VIN=12V
12VIN, 500 kHz
8VIN, 300 kHz
18VIN, 700 kHz
FAN2106
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 9
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
Typical operating characteristics using the circuit shown in Figure 10. VIN=12 V, VCC=5 V, unless otherwise specified.
Figure 15. SW and VOUT Ripple, 6 A Load
Figure 16. Startup with 1 V Pre-Bias on VOUT
Figure 17. Transient Response, 2-6 A Load
Figure 18. Re-Start on Fault
Figure 19. Startup, 3 A Load
Figure 20. Shutdown, 3 A Load
VOUT
SW
VOUT
SW
IOUT
SW
VOUT
EN
PGOOD
PGOOD
EN
EN
VOUT
VOUT
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 10
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Circuit Description
PWM Generation
Refer to Figure 2 for the PWM control mechanism.
FAN2106 uses the summing-mode method of control to
generate the PWM pulses. An amplified current-sense
signal is summed with an internally generated ramp and
the combined signal is compared with the output of the
error amplifier to generate the pulsewidth to drive the
high-side MOSFET. Sensed current from the previous
cycle is used to modulate the output of the summing
block. The output of the summing block is also
compared against a voltage threshold set by the RLIM
resistor to limit the inductor current on a cycle-by-cycle
basis. The RRAMP resistor helps set the charging current
for the internal ramp and provides input voltage feed-
forward function. The controller facilitates external
compensation for enhanced flexibility.
Initialization
Once VCC exceeds the UVLO threshold and EN is
HIGH, the IC checks for a shorted FB pin before
releasing the internal soft-start ramp (SS).
If the parallel combination of R1 and RBIAS is 1 K,
the internal SS ramp is not released and the regulator
does not start.
Enable
FAN2106 has an internal pull-up to the ENABLE (EN)
pin so that the IC is enabled once VCC exceeds the
UVLO threshold. Connecting a small capacitor across
EN and AGND delays the rate of voltage rise on the EN
pin. The EN pin also serves for the restart whenever a
fault occurs (refer to the Auto-Restart section). If the
regulator is enabled externally, the external EN signal
should go HIGH only after VCC is established. For
applications where such sequencing is required,
FAN2106 can be enabled (after the VCC comes up) with
external control, as shown in Figure 21.
14
FAN2106
EN
3.3n
Figure 21. Enabling with External Control
Soft-Start
Once internal SS ramp has charged to 0.8 V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0 V (T1.0), the fault latch is inhibited.
To avoid skipping the soft-start cycle, it is necessary to
apply VIN before VCC reaches its UVLO threshold. Normal
sequence for powering up would be VINVCCEN.
Soft-start time is a function of switching frequency.
SS
1.35V
FB
EN
0.8V
T0.8
T1.0
3200 CLKs
4000 CLKs
Fault
Latch
Enable
0.8V
1.0V
2400 CLKs
Figure 22. Soft-Start Timing Diagram
Cycling VCC or the EN pin discharges the internal SS
and resets the IC. In applications where external EN
signal is used, VIN and VCC should be established
before the EN signal comes up to prevent skipping the
soft-start function.
Startup on Pre-Bias
The regulator does not allow the low-side MOSFET to
operate in full synchronous rectification mode until
internal SS ramp reaches 95% of VREF (~0.76 V). This
helps the regulator start on a pre-biased output and
ensures that the pre-biased outputs are not discharged
during soft-start.
Protections
The converter output is monitored and protected
against extreme overload, short-circuit, over-voltage,
under-voltage, and over-temperature conditions.
Under-Voltage Shutdown
If the voltage on the FB pin remains below the under-
voltage threshold for 16 consecutive clock cycles, the
fault latch is set and the converter shuts down. This
protection is not active until the internal SS ramp
reaches 1.0 V during soft-start.
Over-Voltage Protection
If voltage on the FB pin exceeds 115% of VREF for two
consecutive clock cycles, the fault latch is set and
shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7 V while the low-side
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 11
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
The OV and high-side short fault protections are active
all the time, including during soft-start.
Over-Temperature Protection (OTP)
The chip incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 150°C is reached. The IC restarts when the die
temperature falls below 125°C.
Auto-Restart
After a fault, EN pin is discharged by a 1 µA current sink
to a 1.1 V threshold before the internal 800 K pull-up
is restored. A new soft-start cycle begins when EN
charges above 1.35 V.
Depending on the external circuit, the FAN2106 can be
configured to remain latched-off or to automatically
restart after a fault.
Table 1. Fault / Restart Configurations
EN Pin
Controller / Restart State
Pull to GND
OFF (Disabled)
Pull-up to VCC with
100 K
No Restart – Latched OFF
(After VCC Comes Up)
Open
Immediate Restart After Fault
Cap. to GND
New Soft-Start Cycle After:
tDELAY (ms)=3.9 • C(nf)
When EN is left open, restart is immediate.
If auto-restart is not desired, tie the EN pin to the VCC
pin or pull it HIGH after VCC comes up with a logic gate
to keep the 1 µA current sink from discharging EN to
1.1 V. Figure 23 shows one method to pull up EN to VCC
for a latch configuration.
14
FAN2106
15
100K
EN
VCC
3.3n
Figure 23. Enable Control with Latch Option
Power-Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW
when VOUT is out of regulation, as measured at the FB
pin. Thresholds are specified in the Electrical
Specifications section. PGOOD does not assert HIGH
until the fault latch is enabled (T1.0) (see Figure 22).
Application Information
Bias Supply
The FAN2106 requires a 5 V supply rail to bias the IC
and provide gate-drive energy. Connect a 1.0 µf X5R
or X7R decoupling capacitor between VCC and PGND.
Since VCC is used to drive the internal MOSFET gates,
supply current is frequency and voltage dependent.
Approximate VCC current (ICC) can be calculated using:
)]128f()013.0
2275V
[(58.4I CC
)mA(
CC
(1)
where frequency (f) is expressed in KHz.
Setting the Output Voltage
The output voltage of the regulator can be set from
0.8 V to 80% of VIN by an external resistor divider (R1
and RBIAS in Figure 1). For output voltages > 5 V, output
current rating may need to be de-rated depending upon
the ambient temperature, power dissipated in the
package and the PCB layout.
The external resistor divider is calculated using:
nA650
1R V8.0V
RV8.0 OUT
BIAS
(2)
Connect RBIAS between FB and AGND.
If R1 is open (see Figure 1), the output voltage is not
regulated eventually causing a latched fault after the
soft start is complete (T1.0)
If the parallel combination of R1 and RBIAS is 1K, the
internal SS ramp is not released and the regulator does
not start.
Setting the Switching Frequency
Switching frequency is determined by an external resistor,
RT, connected between the R(T) pin and AGND:
65 135)f/10(
R6
)K(
T
(3)
where RT is in K and frequency (f) is in KHz.
The regulator cannot start if RT is left open.
Calculating the Inductor Value
Typically the inductor value is chosen based on ripple
current (IL), which is chosen between 10 to 35% of the
maximum DC load. Regulator designs that require fast
transient response use a higher ripple-current setting,
while regulator designs that require higher efficiency
keep ripple current on the low side and operate at a
lower switching frequency. The inductor value is
calculated by the following formula:
fL D)-(1 V
I OUT
L
(4)
where f is the switching frequency.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 12
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Setting the Ramp Resistor Value
RRAMP resistor plays a critical role in the design by
providing charging current to the internal ramp capacitor
and also serving as a means to provide input voltage
feedforward.
RRAMP is calculated by the following formula:
2
10)18()8.1( 6
)(
fV VV
RIN
OUTIN
KRAMP
(5)
where frequency (f) is expressed in KHz.
For wide input operation, first calculate RRAMP for the
minimum and maximum input voltage conditions and
use larger of the two values calculated.
In all applications, current through the RRAMP pin must
be greater than 10 µA from the equation below for
proper operation:
A
R
V
RAMP
IN
10
2
8.1
(6)
If the calculated RRAMP values in Equation (5) result in a
current less than 10 µA, use the RRAMP value that
satisfies Equation (6). In applications with large input
ripple voltage, the RRAMP resistor should be adequately
decoupled from the input voltage to minimize ripple on
the RAMP pin.
Setting the Current Limit
The current limit system involves two comparators. The
MAX ILIMIT comparator is used with a VILIM fixed-voltage
reference and represents the maximum current limit
allowable. This reference voltage is temperature
compensated to reflect the RDSON variation of the low-
side MOSFET. The ADJUST ILIMIT comparator is used
where the current limit needs to be set lower than the
VILIM fixed reference. The 10 µA current source does not
track the RDSON changes over temperature, so change
is added into the equations for calculating the ADJUST
ILIMIT comparator reference voltage, as is shown below.
Figure 24 shows a simplified schematic of the over-
current system.
Figure 24. Current-Limit System Schematic
Since the ILIM voltage is set by a 10 µA current source
into the RILIM resistor, the basic equation for setting the
reference voltage is:
VRILIM = 10µA*RILIM
(7)
To calculate RILIM:
RILIM = VRILIM/ 10µA
(8)
The voltage VRILIM is made up of two components, VBOT
(which relates to the current through the low-side
MOSFET) and VRMPEAK (which relates to the peak
current through the inductor). Combining those two
voltage terms results in:
RILIM = (VBOT + VRMPEAK)/ 10µA
(9)
RILIM = {0.96 + (ILOAD * RDSON *KT*8)} +
{D*(VIN – 1.8)/(fSW*0.03*10^-3*RRAMP)}/10µA
(10)
where:
VBOT = 0.96 + (ILOAD * RDSON *KT*8);
VRMPEAK = D*(VIN – 1.8)/(fSW*0.03*10^-3*RRAMP);
ILOAD = the desired maximum load current;
RDSON = the nominal RDSON of the low-side MOSFET;
KT = the normalized temperature coefficient for the
low-side MOSFET (on datasheet graph);
D = VOUT/VIN duty cycle;
fSW = Clock frequency in kHz; and
RRAMP = chosen ramp resistor value in k.
After 16 consecutive, pulse-by-pulse, current-limit
cycles, the fault latch is set and the regulator shuts
down. Cycling VCC or EN restores operation after a
normal soft-start cycle (refer to the Auto-Restart
section).
The over-current protection fault latch is active during
the soft-start cycle. Use 1% resistor for RILIM.
+
_
VC
C
10µA
ILIMI
T
ILIM
RILI
M
+
_
ILIMI
T
ADJUST
MAX
+
_
COMP
PWM
VER
R
PWM
ILIMTRIP
VILIM
RAMP
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN2106 • Rev. 1.25 13
FAN2106 — 3-24V Input, 6A, High-Efficiency, Integrated Synchronous Buck Regulator
Loop Compensation
The loop is compensated using a feedback network
around the error amplifier. Figure 25 shows a complete
Type-3 compensation network. For Type-2
compensation, eliminate R3 and C3.
Figure 25. Compensation Network
Since the FAN2106 employs a summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
RRAMP also provides feedforward compensation for
changes in VIN. With a fixed RRAMP value, the modulator
gain increases as VIN is reduced; this could make it
difficult to compensate the loop. For low-input-voltage-
range designs (3 V to 8 V), RRAMP and the
compensation component values are different
compared to designs with VIN between 8 V and 24 V.
Application note AN-8022 (TinyCalc™) can be used to
calculate the compensation components.
Recommended PCB Layout
Good PCB layout and careful attention to temperature
rise is essential for reliable operation of the regulator.
Four-layer PCB with two-ounce copper on the top and
bottom sides and thermal vias connecting the layers are
recommended. Keep power traces wide and short to
minimize losses and ringing. Do not connect AGND to
PGND below the IC. Connect the AGND pin to PGND at
the output OR to the PGND plane.
VIN
GND
SW
VOUT
GND
Figure 26. Recommended PCB Layout
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