ADUM1200AR-RL7 - Analog Devices - Datasheet.Directory

Dual-Channel Digital Isolators

ADuM1200/ADuM1201

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Narrow body SOIC 8-lead package

Low power operation

5 V operation

1.1 mA per channel maximum @ 0 Mbps to 2 Mbps

3.7 mA per channel maximum @ 10 Mbps

8.2 mA per channel maximum @ 25 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps

2.2 mA per channel maximum @ 10 Mbps

4.8 mA per channel maximum @ 25 Mbps

Bidirectional communication

3 V/5 V level translation

High temperature operation: 105°C

High data rate: dc to 25 Mbps (NRZ)

Precise timing characteristics

3 ns maximum pulse-width distortion

3 ns maximum channel-to-channel matching

High common-mode transient immunity: > 25 kV/µs

Safety and regulatory approvals

UL recognition

2500 V rms for 1 minute per UL 1577

CSA component acceptance notice #5A

VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000

VIORM = 560 V peak

APPLICATIONS

Size-critical multichannel isolation

SPI® interface/data converter isolation

RS-232/RS-422/RS-485 transceiver isolation

Digital field bus isolation

GENERAL DESCRIPTION

The ADuM120x are dual-channel digital isolators based on

Analog Devices’ iCoupler® technology. Combining high speed

CMOS and monolithic transformer technology, these isolation

components provide outstanding performance characteristics

superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices

remove the design difficulties commonly associated with

optocouplers. The typical optocoupler concerns regarding

uncertain current transfer ratios, nonlinear transfer functions,

and temperature and lifetime effects are eliminated with the

simple iCoupler digital interfaces and stable performance

characteristics. The need for external drivers and other discrete

components is eliminated with these iCoupler products.

Furthermore, iCoupler devices consume one-tenth to one-sixth

the power of optocouplers at comparable signal data rates.

The ADuM120x isolators provide two independent isolation

channels in a variety of channel configurations and data rates

(see the Ordering Guide). Both parts operate with the supply

voltage on either side ranging from 2.7 V to 5.5 V, providing

compatibility with lower voltage systems as well as enabling a

voltage translation functionality across the isolation barrier. In

addition, the ADuM120x provide low pulse-width distortion

(< 3 ns for CR grade) and tight channel-to-channel matching

(< 3 ns for CR grade). Unlike other optocoupler alternatives, the

ADuM120x isolators have a patented refresh feature that

ensures dc correctness in the absence of input logic transitions

and during power-up/power-down conditions.

FUNCTIONAL BLOCK DIAGRAMS

ENCODE DECODE

V

DD1

V

IA

V

IB

G

ND

1

V

DD2

V

OA

V

OB

GND

2

1

2

3

4

8

7

6

5

04642-0-001

Figure 1. ADuM1200 Functional Block Diagram

ENCODE DECODE

DECODE ENCODE

V

DD1

V

OA

V

IB

G

ND

1

V

DD2

V

IA

V

OB

GND

2

1

2

3

4

8

7

6

5

04642-0-002

Figure 2. ADuM1201 Functional Block Diagram

ADuM1200/ADuM1201

Rev. B | Page 2 of 20

TABLE OF CONTENTS

Specifications..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3 V Operation................................ 5

Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V

Operation....................................................................................... 7

Package Characteristics ............................................................. 10

Regulatory Information............................................................. 10

Insulation and Safety-Related Specifications.......................... 10

DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics ............................................................................ 11

Recommended Operating Conditions .................................... 11

Absolute Maximum Ratings.......................................................... 12

ESD Caution................................................................................ 12

Pin Configurations and Function Descriptions......................... 13

Typical Performance Characteristics ........................................... 14

Application Information................................................................ 15

PC Board Layout ........................................................................ 15

Propagation Delay-Related Parameters................................... 15

DC Correctness and Magnetic Field Immunity........................... 15

Power Consumption .................................................................. 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

REVISION HISTORY

9/04—Data Sheet Changed from Rev. A to Rev. B

Changes to Table 5.......................................................................... 10

6/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Format .............................................................Universal

Changes to General Description .................................................... 1

Changes to Electrical Characteristics—5 V Operation ............... 3

Changes to Electrical Characteristics—3 V Operation ............... 5

Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation ............................................................................ 7

4/04—Revision 0: Initial Version

ADuM1200/ADuM1201

Rev. B | Page 3 of 20

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the

entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent IDDI (Q) 0.50 0.60 mA

Output Supply Current, per Channel, Quiescent IDDO (Q) 0.19 0.25 mA

ADuM1200, Total Supply Current, Two Channels1

DC to 2 Mbps

VDD1 Supply Current IDD1 (Q) 1.1 1.4 mA DC to 1 MHz logic signal freq.

VDD2 Supply Current IDD2 (Q) 0.5 0.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

VDD1 Supply Current IDD1 (10) 4.3 5.5 mA 5 MHz logic signal freq.

VDD2 Supply Current IDD2 (10) 1.3 2.0 mA 5 MHz logic signal freq.

25 Mbps (CR Grade Only)

VDD1 Supply Current IDD1 (25) 10 13 mA 12.5 MHz logic signal freq.

VDD2 Supply Current IDD2 (25) 2.8 3.4 mA 12.5 MHz logic signal freq.

ADuM1201, Total Supply Current, Two Channels1

DC to 2 Mbps

VDD1 Supply Current IDD1 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq.

VDD2 Supply Current IDD2 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

VDD1 Supply Current IDD1 (10) 2.8 3.5 mA 5 MHz logic signal freq.

VDD2 Supply Current IDD2 (10) 2.8 3.5 mA 5 MHz logic signal freq.

25 Mbps (CR Grade Only)

VDD1 Supply Current IDD1 (25) 6.3 8.0 mA 12.5 MHz logic signal freq.

VDD2 Supply Current IDD2 (25) 6.3 8.0 mA 12.5 MHz logic signal freq.

For All Models

Input Currents IIA, IIB −10 +0.01 +10 µA 0 ≤ VIA, VIB ≤ VDD1 or VDD2

Logic High Input Threshold VIH 0.7 VDD1, VDD2 V

Logic Low Input Threshold VIL 0.3 VDD1,

VDD2

V

Logic High Output Voltages VOAH VDD1,

VDD2 − 0.1

5.0 V IOx = −20 µA, VIx = VIxH

V

OBH VDD1,

VDD2 − 0.5

4.8 V IOx = −4 mA, VIx = VIxH

Logic Low Output Voltages VOAL 0.0 0.1 V IOx = 20 µA, VIx = VIxL

V

OBL 0.04 0.1 V IOx = 400 µA, VIx = VIxL

0.2 0.4 V IOx = 4 mA, VIx = VIxL

SWITCHING SPECIFICATIONS

ADuM120xAR

Minimum Pulse Width2PW 1000 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay4tPHL, tPLH 50 150 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5tPSK 100 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching6tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

ADuM1200/ADuM1201

Rev. B | Page 4 of 20

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM120xBR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay4 t

PHL, tPLH 20 50 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t

PSK 15 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels6

tPSKCD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Opposing Directional Channels6

tPSKOD 15 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

ADuM120xCR

Minimum Pulse Width2 PW 20 40 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 25 50 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay4 t

PHL, tPLH 20 45 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH – tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t

PSK 15 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels6

tPSKCD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Opposing Directional Channels6

tPSKOD 15 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

For All Models

Common-Mode Transient Immunity

at Logic High Output7

|CMH| 25 35 kV/µs VIx = VDD1, VDD2, VCM = 1000 V,

transient magnitude = 800 V

Common-Mode Transient Immunity

at Logic Low Output7

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

Refresh Rate fr 1.2 Mbps

Input Dynamic Supply Current, per Channel8IDDI (D) 0.19 mA/Mbps

Output Dynamic Supply Current, per Channel8 I

DDO (D) 0.05 mA/Mbps

1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See

Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Figure 11

for total I

Figure 8

Figure 9

DD1 and IDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.

2 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

3 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output

load within the recommended operating conditions.

6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with

inputs on opposing sides of the isolation barrier.

7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

magnitude is the range over which the common mode is slewed.

8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply

current for a given data rate.

Figure 6

Power Consumption

ADuM1200/ADuM1201

Rev. B | Page 5 of 20

ELECTRICAL CHARACTERISTICS—3 V OPERATION

All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V. All min/max specifications apply over the

entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent IDDI (Q) 0.26 0.35 mA

Output Supply Current, per Channel, Quiescent IDDO (Q) 0.11 0.20 mA

ADuM1200, Total Supply Current, Two Channels1

DC to 2 Mbps

VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq.

VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq.

VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq.

25 Mbps (CR Grade Only)

VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq.

VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq.

ADuM1201, Total Supply Current, Two Channels1

DC to 2 Mbps

VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq.

VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq.

VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq.

25 Mbps (CR Grade Only)

VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq.

VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq.

For All Models

Input Currents IIA, IIB −10 0.01 10 µA 0 ≤ VIA, VIB, ≤ VDD1 or VDD2

Logic High Input Threshold VIH 0.7 VDD1, VDD2 V

Logic Low Input Threshold VIL 0.3 VDD1, VDD2

Logic High Output Voltages VOAH VDD1,

VDD2 − 0.1

3.0 V IOx = −20 µA, VIx = VIxH

V

OBH VDD1,

VDD2 − 0.5

2.8 V IOx = −4 mA, VIx = VIxH

Logic Low Output Voltages VOAL 0.0 0.1 V IOx = 20 µA, VIx = VIxL

V

OBL 0.04 0.1 V IOx = 400 µA, VIx = VIxL

0.2 0.4 V IOx = 4 mA, VIx = VIxL

SWITCHING SPECIFICATIONS

ADuM120xAR

Minimum Pulse Width2PW 1000 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay4tPHL, tPLH 50 150 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5tPSK 100 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching6tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

ADuM1200/ADuM1201

Rev. B | Page 6 of 20

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM120xBR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay4 t

PHL, tPLH 20 60 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH −tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t

PSK 22 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels6

tPSKCD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Opposing Directional Channels6

tPSKOD 22 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels

ADuM120xCR

Minimum Pulse Width2 PW 20 40 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 25 50 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay4 t

PHL, tPLH 20 55 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t

PSK 16 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels6

tPSKCD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Opposing Directional Channels6

tPSKOD 16 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels

For All Models

Common Mode Transient Immunity

at Logic High Output7

|CMH| 25 35 kV/µs VIx = VDD1, VDD2, VCM = 1000 V,

transient magnitude = 800 V

Common Mode Transient Immunity

at Logic Low Output7

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

Refresh Rate fr 1.1 Mbps

Input Dynamic Supply Current, per Channel8IDDI (D) 0.10 mA/Mbps

Output Dynamic Supply Current, per Channel8 I

DDO (D) 0.03 mA/Mbps

1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See

Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through Figure 11

for total I

Figure 8

9

DD1 and IDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.

2 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

3 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output

load within the recommended operating conditions.

6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with

inputs on opposing sides of the isolation barrier.

7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

magnitude is the range over which the common mode is slewed.

8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply

current for a given data rate.

Figure 6

Power Consumption

ADuM1200/ADuM1201

Rev. B | Page 7 of 20

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤

VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the entire recommended operating range, unless otherwise noted.

All typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V.

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent IDDI (Q) mA

5 V/3 V Operation 0.50 0.6 mA

3 V/5 V Operation 0.26 0.35 mA

Output Supply Current, per Channel, Quiescent IDDO (Q) mA

5 V/3 V Operation 0.11 0.20 mA

3 V/5 V Operation 0.19 0.25 mA

ADuM1200, Total Supply Current, Two Channels1

DC to 2 Mbps

VDD1 Supply Current IDD1 (Q)

5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal freq.

VDD2 Supply Current IDD2 (Q)

5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

VDD1 Supply Current IDD1 (10)

5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal freq.

3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal freq.

VDD2 Supply Current IDD2 (10)

5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal freq.

3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal freq.

25 Mbps (CR Grade Only)

VDD1 Supply Current IDD1 (25)

5 V/3 V Operation 10 13 mA 12.5 MHz logic signal freq.

3 V/5 V Operation 5.2 7.7 mA 12.5 MHz logic signal freq.

VDD2 Supply Current IDD2 (25)

5 V/3 V Operation 1.5 2.0 mA 12.5 MHz logic signal freq.

3 V/5 V Operation 2.8 3.4 mA 12.5 MHz logic signal freq.

ADuM1201, Total Supply Current, Two Channels1

DC to 2 Mbps

VDD1 Supply Current IDD1 (Q)

5 V/3 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq.

VDD2 Supply Current IDD2 (Q)

5 V/3 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

VDD1 Supply Current IDD1 (10)

5 V/3 V Operation 2.8 3.5 mA 5 MHz logic signal freq.

3 V/5 V Operation 1.5 2.2 mA 5 MHz logic signal freq.

VDD2 Supply Current IDD2 (10)

5 V/3 V Operation 1.5 2.2 mA 5 MHz logic signal freq.

3 V/5 V Operation 2.8 3.5 mA 5 MHz logic signal freq.

ADuM1200/ADuM1201

Rev. B | Page 8 of 20

Parameter Symbol Min Typ Max Unit Test Conditions

25 Mbps (CR Grade Only)

VDD1 Supply Current IDD1 (25)

5 V/3 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq.

3 V/5 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq.

VDD2 Supply Current IDD2 (25)

5 V/3 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq.

3 V/5 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq.

For All Models

Input Currents IIA, IIB −10 0.01 10 µA 0 ≤ VIA, VIB ≤ VDD1 or VDD2

Logic High Input Threshold VIH 0.7 VDD1, VDD2 V

Logic Low Input Threshold VIL 0.3 VDD1, VDD2 V

5 V/3 V Operation 0.8 V

3 V/5 V Operation 0.4 V

Logic High Output Voltages VOAH,

VOBH

VDD1,

VDD2 − 0.1

VDD1,

VDD2

V IOx = −20 µA, VIx = VIxH

VDD1,

VDD2 − 0.5

VDD1,

VDD2 − 0.2

V IOx = −4 mA, VIx = VIxH

Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 µA, VIx = VIxL

0.04 0.1 V IOx = 400 µA, VIx = VIxL

0.2 0.4 V IOx = 4 mA, VIx = VIxL

SWITCHING SPECIFICATIONS

ADuM120xAR

Minimum Pulse Width2PW 1000 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay4tPHL, tPLH 50 150 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5tPSK 50 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching6tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

ADuM120xBR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay4 t

PHL, tPLH 15 55 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t

PSK 22 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels6

tPSKCD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Opposing Directional Channels6

tPSKOD 22 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR/tf C

L = 15 pF, CMOS signal levels

5 V/3 V Operation 3.0 ns

3 V/5 V Operation 2.5 ns

ADuM1200/ADuM1201

Rev. B | Page 9 of 20

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM120xCR

Minimum Pulse Width2 PW 20 40 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 25 50 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay4 t

PHL, tPLH 20 50 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH – tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t

PSK 15 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels6

tPSKCD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Opposing Directional Channels6

tPSKOD 15 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR/tf C

L = 15 pF, CMOS signal levels

5 V/3 V Operation 3.0 ns

3 V/5 V Operation 2.5 ns

For All Models

Common-Mode Transient Immunity

at Logic High Output7

|CMH| 25 35 kV/µs VIx = VDD1, VDD2, VCM = 1000 V,

transient magnitude = 800 V

Common-Mode Transient Immunity

at Logic Low Output7

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current, per Channel8IDDI (D)

5 V/3 V Operation 0.19 mA/Mbps

3 V/5 V Operation 0.10 mA/Mbps

Output Dynamic Supply Current, per Channel8 I

DDI (D)

5 V/3 V Operation 0.03 mA/Mbps

3 V/5 V Operation 0.05 mA/Mbps

1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See

Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Figure 11

for total I

Figure 8

Figure 9

DD1 and IDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.

2 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

3 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output

load within the recommended operating conditions.

6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with

inputs on opposing sides of the isolation barrier.

7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

magnitude is the range over which the common mode is slewed.

8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply

current for a given data rate.

Figure 6

Power Consumption

ADuM1200/ADuM1201

Rev. B | Page 10 of 20

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-Output)1RI-O 1012 Ω

Capacitance (Input-Output)1 C

I-O 1.0 pF f = 1 MHz

Input Capacitance CI 4.0 pF

IC Junction-to-Case Thermal Resistance, Side 1 θJCI 46 °C/W Thermocouple located at center of

package underside

IC Junction-to-Case Thermal Resistance, Side 2 θJCO 41 °C/W

1 The device is considered a 2-terminal device; Pins 1, 2, 3, and 4 are shorted together, and Pins 5, 6, 7, and 8 are shorted together.

REGULATORY INFORMATION

The ADuM1200/ADuM1201 have been approved by the following organizations:

Table 5.

UL CSA VDE

Recognized under 1577 Component

Recognition Program1

2500 V rms isolation voltage

File E214100

Approved under CSA Component

Acceptance Notice #5A

File 205078

Certified according to

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-012

Basic insulation, 560 V peak

Complies with DIN EN 60747-5-2 (VDE 0884

Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12;

EN 60950: 2000, Reinforced insulation, 560 V peak

File 2471900-4880-0001

1 In accordance with UL1577, each ADuM120x is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA).

2 In accordance with DIN EN 60747-5-2, each ADuM120x is proof-tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection

limit = 5 pC).

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration

Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest

distance through air

Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest

distance path along body

Minimum Internal Gap (Internal

Clearance)

0.017 min mm Insulation distance through insulation

Tracking Resistance (Comparative

Tracking Index)

CTI >175 V DIN IEC 112/VDE 0303 Part 1

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

ADuM1200/ADuM1201

Rev. B | Page 11 of 20

DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS

Table 7.

Description Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I−IV

For Rated Mains Voltage ≤ 300 V rms I−III

For Rated Mains Voltage ≤ 400 V rms I−II

Climatic Classification 40/105/21

Pollution Degree (DIN VDE 0110, Table 1) 2

Maximum Working Insulation Voltage VIORM 560 V peak

Input to Output Test Voltage, Method b1 VPR 1050 V peak

VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC

Input to Output Test Voltage, Method a VPR

After Environmental Tests Subgroup 1

VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC 896 V peak

After Input and/or Safety Test Subgroup 2/3 672

VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) VTR 4000 V peak

Safety-Limiting Values (maximum value allowed in the event of a failure; also see the thermal

derating curve, Figure 3)

Case Temperature TS 150 °C

Side 1 Current IS1 160 mA

Side 2 Current IS2 170 mA

Insulation Resistance at TS, VIO = 500 V RS >109 Ω

Note that the “*” marking on the package denotes DIN EN 60747-5-2 approval for a 560 V peak working voltage.

This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.

CASE TEMPERATURE (°C)

SAFETY-LIMITING CURRENT (mA)

0

200

180

100

80

60

40

20

50 100 150 200

SIDE #1 SIDE #2

04642-0-003

120

140

160

Figure 3. Thermal Derating Curve, Dependence of Safety-

Limiting Values on Case Temperature, per DIN EN 60747-5-2

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature TA −40 +105 °C

Supply Voltages1VDD1, VDD2 2.7 5.5 V

Input Signal Rise and Fall Times 1.0 ms

1 All voltages are relative to their respective ground. See the DC Correctness and

Magnetic Field Immunity section for information on immunity to external

magnetic fields.

ADuM1200/ADuM1201

Rev. B | Page 12 of 20

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 9.

Parameter Symbol Min Max Unit

Storage Temperature TST −55 150 °C

Ambient Operating Temperature TA −40 105 °C

Supply Voltages1VDD1, VDD2 −0.5 7.0 V

Input Voltage,1, 2VIA, VIB −0.5 VDDI + 0.5 V

Output Voltage1, 2 VOA, VOB −0.5 VDDO + 0.5 V

Average Output Current, per Pin3IO −35 35 mA

Common-Mode Transients4 −100 +100 kV/µs

1 All voltages are relative to their respective ground.

2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively.

3 See for maximum rated current values for various temperatures. Figure 3

4 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or

permanent damage.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Table 10. ADuM1200 Truth Table (Positive Logic)

VIA Input VIB Input VDD1 State VDD2 State VOA Output VOB Output Notes

H H Powered Powered H H

L L Powered Powered L L

H L Powered Powered H L

L H Powered Powered L H

X X Unpowered Powered H H Outputs return to the input state within 1 µs

of VDDI power restoration.

X X Powered Unpowered Indeterminate Indeterminate Outputs return to the input state within 1 µs

of VDDO power restoration.

Table 11. ADuM1201 Truth Table (Positive Logic)

VIA Input VIB Input VDD1 State VDD2 State VOA Output VOB Output Notes

H H Powered Powered H H

L L Powered Powered L L

H L Powered Powered H L

L H Powered Powered L H

X X Unpowered Powered Indeterminate H Outputs return to the input state within 1 µs

of VDD1 power restoration.

X X Powered Unpowered H Indeterminate Outputs return to the input state within 1 µs

of VDDO power restoration.

ADuM1200/ADuM1201

Rev. B | Page 13 of 20

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

18

27

36

45

ADuM1200

TOP VIEW

(Not to Scale)

04642-0-004

V

DD1

V

IA

V

IB

GND

1

V

DD2

V

OA

V

OB

GND

2

Figure 4. ADuM1200 Pin Configuration

18

27

36

45

ADuM1201

TOP VIEW

(Not to Scale)

04642-0-005

V

DD1

V

OA

V

IB

GND

1

V

DD2

V

IA

V

OB

GND

2

Figure 5. ADuM1201 Pin Configuration

Table 12. ADuM1200 Pin Function Descriptions

No. Mnemonic Function

1 VDD1 Supply Voltage for Isolator Side 1,

2.7 V to 5.5 V.

2 VIA Logic Input A.

3 VIB Logic Input B.

4 GND1 Ground 1. Ground reference for isolator

Side 1.

5 GND2 Ground 2. Ground reference for isolator

Side 2.

6 VOB Logic Output B.

7 VOA Logic Output A.

8 VDD2 Supply Voltage for Isolator Side 2,

2.7 V to 5.5 V.

Table 13. ADuM1201 Pin Function Descriptions

No. Mnemonic Function

1 VDD1 Supply Voltage for Isolator Side 1,

2.7 V to 5.5 V.

2 VOA Logic Output A.

3 VIB Logic Input B.

4 GND1 Ground 1. Ground reference for Isolator

Side 1.

5 GND2 Ground 2. Ground reference for Isolator

Side 2.

6 VOB Logic Output B.

7 VIA Logic Input A.

8 VDD2 Supply Voltage for Isolator Side 2,

2.7 V to 5.5 V.

ADuM1200/ADuM1201

Rev. B | Page 14 of 20

TYPICAL PERFORMANCE CHARACTERISTICS

04642-0-006

DATA RATE (Mbps)

CURRENT/CHANNEL (mA)

0

6

2

8

10

10 20 30

5V 3V

4

Figure 6. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation

04642-0-007

DATA RATE (Mbps)

CURRENT/CHANNEL (mA)

0

3

2

1

4

10 20 30

5V

3V

Figure 7. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

04642-0-008

DATA RATE (Mbps)

CURRENT/CHANNEL (mA)

0

3

2

1

4

10 20 30

5V

3V

Figure 8. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

04642-0-009

DATA RATE (Mbps)

CURRENT (mA)

0

15

10

5

20

10 20 30

5V

3V

Figure 9. Typical ADuM1200 VDD1 Supply Current vs. Data Rate

for 5 V and 3 V Operation

04642-0-010

DATA RATE (Mbps)

CURRENT (mA)

0

3

2

1

4

10 20 30

5V 3V

Figure 10. Typical ADuM1200 VDD2 Supply Current vs. Data Rate

for 5 V and 3 V Operation

04642-0-011

DATA RATE (Mbps)

CURRENT (mA)

0

6

2

8

10

10 20 30

5V

3V

4

Figure 11. Typical ADuM1201 VDD1 or VDD2 Supply Current vs. Data Rate

for 5 V and 3 V Operation

ADuM1200/ADuM1201

Rev. B | Page 15 of 20

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM120x digital isolators require no external interface

circuitry for the logic interfaces. Power supply bypassing is

strongly recommended at the input and output supply pins. The

capacitor value should be between 0.01 µF and 0.1 µF. The total

lead length between both ends of the capacitor and the input

power supply pin should not exceed 20 mm.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes

a logic signal to propagate through a component. The

propagation delay to a logic low output may differ from the

propagation delay to a logic high.

INPUT (

V

IX

)

OUTPUT (

V

OX

)

t

PLH

t

PHL

50%

04642-0-012

Figure 12. Propagation Delay Parameters

Pulse-width distortion is the maximum difference between

these two propagation delay values and is an indication of how

accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum amount

that the propagation delay differs between channels within a

single ADuM120x component.

Propagation delay skew refers to the maximum amount that the

propagation delay differs between multiple ADuM120x

components operating under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent to the decoder via the

transformer. The decoder is bistable and is therefore either set

or reset by the pulses, indicating input logic transitions. In the

absence of logic transitions of more than 2 µs at the input, a

periodic set of refresh pulses indicative of the correct input state

are sent to ensure dc correctness at the output. If the decoder

receives no internal pulses for more than about 5 µs, the input

side is assumed to be unpowered or nonfunctional, in which

case the isolator output is forced to a default state (see Table 8)

by the watchdog timer circuit.

The ADuM120x are extremely immune to external magnetic

fields. The limitation on the ADuM120x’s magnetic field

immunity is set by the condition in which induced voltage in

the transformer’s receiving coil is sufficiently large to either

falsely set or reset the decoder. The following analysis defines

the conditions under which this may occur. The 3 V operating

condition of the ADuM120x is examined because it represents

the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater

than 1.0 V. The decoder has a sensing threshold at about 0.5 V,

therefore establishing a 0.5 V margin in which induced voltages

can be tolerated. The voltage induced across the receiving coil is

given by

∑=Π−= NnrdtβdV n,...2,1;)/( 2

where:

β is the magnetic flux density (gauss).

N is the number of turns in the receiving coil.

rn is the radius of the nth turn in the receiving coil (cm).

Given the geometry of the receiving coil in the ADuM120x and

an imposed requirement that the induced voltage be at most

50% of the 0.5 V margin at the decoder, a maximum allowable

magnetic field is calculated, as shown in Figure 13.

MAGNETIC FIELD FREQUENCY (Hz)

100

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSITY (kgauss)

0.001 1M

10

0.01

1k 10k 10M

0.1

1

100M100k

04642-0-013

Figure 13. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the

maximum allowable magnetic field of 0.2 kgauss induces a

voltage of 0.25 V at the receiving coil. This is about 50% of the

sensing threshold and does not cause a faulty output transition.

Similarly, if such an event were to occur during a transmitted

pulse (and had the worst-case polarity), it would reduce the

received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V

sensing threshold of the decoder.

The preceding magnetic flux density values correspond to

specific current magnitudes at given distances away from the

ADuM120x transformers. Figure 14 expresses these allowable

current magnitudes as a function of frequency for selected

distances. As seen, the ADuM120x are extremely immune and

can be affected only by extremely large currents operated at

high frequency and very close to the component. For the 1 MHz

example, one would have to place a 0.5 kA current 5 mm away

from the ADuM120x to affect the component’s operation.

ADuM1200/ADuM1201

Rev. B | Page 16 of 20

MAGNETIC FIELD FREQUENCY (Hz)

MAXIMUM ALLOWABLE CURRENT (kA)

1000

100

10

1

0.1

0.011k 10k 100M100k 1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

04642-0-014

Figure 14. Maximum Allowable Current for Various

Current-to-ADuM120x Spacings

Note that at combinations of strong magnetic fields and high

frequencies, any loops formed by printed circuit board traces

could induce sufficiently large error voltages to trigger the

threshold of succeeding circuitry. Care should be taken in the

layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM120x

isolator is a function of the supply voltage, the channel’s data

rate, and the channel’s output load.

For each input channel, the supply current is given by

IDDI = IDDI (Q) f ≤ 0.5fr

IDDI = IDDI (D) × (2f – fr) + IDDI (Q) f > 0.5fr

for each output channel, the supply current is given by

IDDO = IDDO (Q) f ≤ 0.5fr

IDDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f – fr) + IDDO (Q)

f > 0.5fr

where:

IDDI (D), IDDO (D) are the input and output dynamic supply currents

per channel (mA/Mbps).

CL is the output load capacitance (pF).

VDDO is the output supply voltage (V).

f is the input logic signal frequency (MHz, half of the input data

rate, NRZ signaling).

fr is the input stage refresh rate (Mbps).

IDDI (Q), IDDO (Q) are the specified input and output quiescent

supply currents (mA).

To calculate the total IDD1 and IDD2 supply current, the supply

currents for each input and output channel corresponding to

IDD1 and IDD2 are calculated and totaled. Figure 6 and Figure 7

provide per-channel supply currents as a function of data rate

for an unloaded output condition. Figure 8 provides per-

channel supply current as a function of data rate for a 15 pF

output condition. Figure 9 through Figure 11 provide total IDD1

and IDD2 supply current as a function of data rate for

ADuM1200 and ADuM1201 channel configurations.

ADuM1200/ADuM1201

Rev. B | Page 17 of 20

OUTLINE DIMENSIONS

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)× 45°

8°

0°

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

41

85

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)

BSC

6.20 (0.2440)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012AA

Figure 15. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-8)

Dimensions shown in millimeters (inches)

ORDERING GUIDE

Model

Number

of Inputs,

VDD1 Side

Number

of Inputs,

VDD2 Side

Maximum

Data Rate

(Mbps)

Maximum

Propagation

Delay, 5 V (ns)

Maximum

Pulse-Width

Distortion

(ns)

Temperature

Range (°C)

Package

Option1

ADuM1200AR 2 0 1 100 40 −40 to +105 R-8

ADuM1200AR-RL7 2 0 1 100 40 −40 to +105 R-8

ADuM1200ARZ22 0 1 100 40 −40 to +105 R-8

ADuM1200ARZ-RL72 2 0 1 100 40 −40 to +105 R-8

ADuM1200BR 2 0 10 50 3 −40 to +105 R-8

ADuM1200BR-RL7 2 0 10 50 3 −40 to +105 R-8

ADuM1200BRZ2 2 0 10 50 3 −40 to +105 R-8

ADuM1200BRZ-RL72 2 0 10 50 3 −40 to +105 R-8

ADuM1200CR 2 0 25 45 3 −40 to +105 R-8

ADuM1200CR-RL7 2 0 25 45 3 −40 to +105 R-8

ADuM1200CRZ2 2 0 25 45 3 −40 to +105 R-8

ADuM1200CRZ-RL72 2 0 25 45 3 −40 to +105 R-8

ADuM1201AR 1 1 1 100 40 −40 to +105 R-8

ADuM1201AR-RL7 1 1 1 100 40 −40 to +105 R-8

ADuM1201ARZ2 1 1 1 100 40 −40 to +105 R-8

ADuM1201ARZ-RL72 1 1 1 100 40 −40 to +105 R-8

ADuM1201BR 1 1 10 50 3 −40 to +105 R-8

ADuM1201BR-RL7 1 1 10 50 3 −40 to +105 R-8

ADuM1201BRZ2 1 1 10 50 3 −40 to +105 R-8

ADuM1201BRZ-RL72 1 1 10 50 3 −40 to +105 R-8

ADuM1201CR 1 1 25 45 3 −40 to +105 R-8

ADuM1201CR-RL7 1 1 25 45 3 −40 to +105 R-8

ADuM1201CRZ2 1 1 25 45 3 −40 to +105 R-8

ADuM1201CRZ-RL72 1 1 25 45 3 −40 to +105 R-8

1 R-8 = 8-lead narrow body SOIC.

2 Z = Pb-free part.

ADuM1200/ADuM1201

Rev. B | Page 18 of 20

NOTES

ADuM1200/ADuM1201

Rev. B | Page 19 of 20

NOTES

ADuM1200/ADuM1201

Rev. B | Page 20 of 20

NOTES

registered trademarks are the property of their respective owners.

D04642–0–9/04(B)