1
FEATURES
20ns (3.3 volt supply) maximum address access time
Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
TTL compatible inputs and output levels, three-state
bidirectional data bus
Typical radiation performance
- Total dose: 50krads
- >100krads(Si), for any orbit, using Aeroflex UTMC
patented shielded package
- SEL Immune >80 MeV-cm2/mg
- LETTH(0.25) = >10 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 5.0E-9
- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
Packaging options:
- 36-lead ceramic flatpack (3.42 grams)
- 36-lead flatpack shielded (10.77 grams)
Standard Microcircuit Drawing 5962-99607
- QML T and Q compliant
INTRODUCTION
The QCOTSTM UT8Q512 Quantified Commercial Off-the-
Shelf product is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (E), an active LOW
Output Enable (G), and three-state drivers. This device has a
power-down feature that reduces power consumption by more
than 90% when deselected.
Writing to the device is accomplished by taking Chip Enable
one (E) input LOW and Write Enable (W) inputs LOW. Data on
the eight I/O pins (DQ0 through DQ7) is then written into the
location specified on the address pins (A0 through A18). Reading
from the device is accomplished by taking Chip Enable one (E)
and Output Enable (G) LOW while forcing Write Enable (W)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed in a
high impedance state when the device is deselected (E, HIGH),
the outputs are disabled (G HIGH), or during a write operation
(E LOWand W LOW).
Standard Products
QCOTSTM UT8Q512 512K x 8 SRAM
Data Sheet
August, 2003
Memory Array
1024 Rows
512x8 Columns
Pre-Charge Circuit
Clk. Gen.
Row Select
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O Circuit
Column Select
Data
Control
CLK
Gen.
A10
A11
A12
A13
A14
A15
A16
A17
A18
DQ
0
- DQ
7
W
G
E
Figure 1. UT8Q512 SRAM Block Diagram
2
PIN NAMES
DEVICE OPERATION
The UT8Q512 has three control inputs called Enable 1 (E), Write
Enable (W), and Output Enable (G); 19 address inputs, A(18:0);
and eight bidirectional data lines, DQ(7:0). E Device Enable
controls device selection, active, and standby modes. Asserting
E enables the device, causes IDD to rise to its active value, and
decodes the 19 address inputs to select one of 524,288 words in
the memory. W controls read and write operations. During a read
cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than VIH (min) and E less than VIL
(max) defines a read cycle. Read access time is measured from
the latter of Device Enable, Output Enable, or valid address to
valid data output.
SRAM Read Cycle 1, the Address Access in figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified tAV Q V is satisfied. Outputs
remain active throughout the entire cycle. As long as Device
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (tAVAV ).
SRAM read Cycle 2, the Chip Enable - Controlled Access in
figure 3b, is initiated by E going active while G remains asserted,
W remains deasserted, and the addresses remain stable for the
entire cycle. After the specified tETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable - Controlled Access in
figure 3c, is initiated by G going active while E is asserted, W
is deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
A(18:0) Address
DQ(7:0) Data Input/Output
EEnable
WWrite Enable
GOutput Enable
VDD Power
VSS Ground
136
235
334
433
532
631
730
829
928
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19
Figure 2. 25ns SRAM Pinout (36)
NC
A18
A17
A16
A15
G
DQ7
DQ6
VSS
VDD
DQ5
DQ4
A14
A13
A12
A11
A10
NC
A0
A1
A2
A3
A4
E
DQ0
DQ1
VDD
VSS
DQ2
DQ3
W
A5
A6
A7
A8
A9
G W E I/O Mode Mode
X1X 1 3-state Standby
X 0 0 Data in Write
1103-state Read2
010Data out Read
3
WRITE CYCLE
A combination of W less than VIL(max) and E less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when W is less
than VIL(max).
Write Cycle 1, the Write Enable - Controlled Access in figure
4a, is defined by a write terminated by W going high, with E
still active. The write pulse width is defined by tWLWH when the
write is initiated by W, and by tETWH when the write is initiated
by E. Unless the outputs have been previously placed in the high-
impedance state by G
, the user must wait tWLQZ before applying
data to the nine bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable - Controlled Access in figure
4b, is defined by a write terminated by the latter of E going
inactive. The write pulse width is defined by tWLEF when the
write is initiated by W, and by tETEF when the write is initiated
by the E going active. For the W initiated write, unless the
outputs have been previously placed in the high-impedance state
by G, the user must wait tWLQZ before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
Table 2. Typical Radiation Hardness
Design Specifications1
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Tota l D o se 50 krad(Si) nominal
Heavy Ion
Error Rate2
<1E-8 Errors/Bit-Day
4
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.5 to 4.6V
VI/O Voltage on any pin -0.5 to 4.6V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissipation 1.0W
TJMaximum junction temperature2+150°C
ΘJC Thermal resistance, junction-to-case310°C/W
IIDC input current ±10 mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 3.0 to 3.6V
TCCase temperature range (C) screening: -55° to +125°C
(E) screening: -40° to +125°C
VIN DC input voltage 0V to VDD
5
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(-55°C to +125°C for (C) screening and -40oC to +125oC for (W) screening) (VDD = 3.3V + 0.3)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (CMOS) 2.0 V
VIL Low-level input voltage (CMOS) 0.8 V
VOL1 Low-level output voltage IOL = 8mA, VDD =3.0V 0.4 V
VOL2 Low-level output voltage IOL = 200µA,VDD =3.0V 0.08 V
VOH1 High-level output voltage IOH = -4mA,VDD =3.0V 2.4 V
VOH2 High-level output voltage IOH = -200µA,VDD =3.0V VDD-0.10 V
CIN1Input capacitance ƒ = 1MHz @ 0V 10 pF
CIO1Bidirectional I/O capacitance ƒ = 1MHz @ 0V 12 pF
IIN Input leakage current VSS < VIN < VDD, VDD = VDD (max) -2 2µA
IOZ Three-state output leakage current 0V < VO < VDD
VDD = VDD (max)
G = VDD (max)
-2 2µA
IOS2, 3 Short-circuit output current 0V < VO < VDD -90 90 mA
IDD(OP) Supply current operating
@ 1MHz
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
125 mA
IDD1(OP) Supply current operating
@40MHz
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
180 mA
IDD2(SB) Nominal standby supply current
@0MHz
Inputs: VIL = VSS
IOUT = 0mA
E = VDD - 0.5
VDD = VDD (max)
VIH = VDD - 0.5V
6
6
15
mA
mA
mA
-55°C and 25°C
-40oC and 25oC
+125°C
6
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
(-55°C to +125°C for (C) screening and -40oC to +125oC for (W) screening) (VDD = 3.3V + 0.3)
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 300mV change from steady-state output voltage (see Figure 3).
3. The ET (enable true) notation refers to the falling edge of E. SEU immunity does not affect the read parameters.
4. The EF (enable false) notation refers to the rising edge of E. SEU immunity does not affect the read parameters.
SYMBOL PARAMETER MIN MAX UNIT
tAVAV 1Read cycle time 20 ns
tAV Q V Read access time 25 ns
tAXQX Output hold time 3 ns
tGLQX G-controlled Output Enable time 0 ns
tGLQV G-controlled Output Enable time (Read Cycle 3) 10 ns
tGHQZ2G-controlled output three-state time 10 ns
tETQX3E-controlled Output Enable time 3 ns
tETQV3E-controlled access time 25 ns
tEFQZ1,2,4 E-controlled output three-state time 10 ns
{
{
}
}
VLOAD + 300mV
VLOAD - 300mV
VLOAD
VH - 300mV
VL + 300mV
Active to High Z LevelsHigh Z to Active Levels
Figure 3. 3-Volt SRAM Loading
7
Assumptions:
1. E and G < VIL (max) and W > VIH (min)
A(18:0)
DQ(7:0)
Figure 4a. SRAM Read Cycle 1: Address Access
tAVAV
tAVQV
tAXQX
Previous Valid Data Valid Data
Assumptions:
1. G < VIL (max) and W > VIH (min)
A(18:0)
Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access
E
DATA VALID
tEFQZ
tETQX
tETQV
DQ(7:0)
Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access
A(18:0)
DQ(7:0)
G
tGHQZ
Assumptions:
1. E< VIL (max) and W > VIH (min)
tGLQV
tGLQX
tAVQV
DATA VALID
8
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*
(-55°C to +125°C for (C) screening and -40oC to +125oC for (E) screening) (VDD = 3.3V + 0.3)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test performed with outputs disabled (G high).
2. Three-state is defined as 300mV change from steady-state output voltage (see Figure 3).
SYMBOL PARAMETER MIN MAX UNIT
tAVAV 1Write cycle time 20 ns
tETWH Device Enable to end of write 20 ns
tAV E T Address setup time for write (E - controlled) 0 ns
tAV W L Address setup time for write (W - controlled) 0 ns
tWLWH Write pulse width 20 ns
tWHAX Address hold time for write (W - controlled) 2 ns
tEFAX Address hold time for Device Enable (E - controlled) 2 ns
tWLQZ2W - controlled three-state time 10 ns
tWHQX W - controlled Output Enable time 5 ns
tETEF Device Enable pulse width (E - controlled) 20 ns
tDVWH Data setup time 15 ns
tWHDX2Data hold time 2 ns
tWLEF Device Enable controlled write pulse width 20 ns
tDVEF2Data setup time 15 ns
tEFDX Data hold time 2 ns
tAV W H Address valid to end of write 20 ns
tWHWL1Write disable time 5 ns
9
Assumptions:
1. G < VIL (max). If G > VIH (min) then Q(8:0) will be
in three-state for the entire cycle.
2. G high for tAVAV cycle.
W
tAV W L
Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access
A(18:0)
Q(7:0)
E
tAVAV 2
D(7:0) APPLIED DATA
tDVWH tWHDX
tETWH
tWLWH tWHAX
tWHQX
tWLQZ
tAV W H
tWHWL
10
tEFDX
Assumptions & Notes:
1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle.
2. Either E scenario above can occur.
3. G high for tAVAV cycle.
A(18:0)
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
W
E
D(7:0) APPLIED DATA
E
Q(7:0)
tWLQZ
tETEF
tWLEF
tDVEF
tAVAV 3
tAV E T
tAV E T
tETEF
tEFAX
tEFAX
or
Notes:
1. 50pF including scope probe and test socket capacitance.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = VDD/2).
90%
Figure 6. AC Test Loads and Input Waveforms
Input Pulses
10%
< 5ns < 5ns
VLOAD = 1.55V
300 ohms
50pF
CMOS
0.5V
VDD-0.05V
10%
11
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(1 Second Data Retention Test)
Notes:
1. E = VDD - .2V, all other inputs = VDR or VSS.
2. Data retention current (IDDR) Tc = 25oC.
3. Not guaranteed or tested.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(10 Second Data Retention Test, Tc= -55oC to +125oC for (C) screening
Notes:
1. Performed at VDD (min) and VDD (max).
2. E = VSS, all other inputs = VDR or VSS.
3. Not guaranteed or tested.
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
VDR VDD for data retention 2.0 -- V
IDDR 1,2 Data retention current -- 2.0 mA
tEFR1,3 Chip select to data retention time 0 ns
tR1,3 Operation recovery time tAVAV ns
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
VDD1VDD for data retention 3.0 3.6 V
tEFR2, 3 Chip select to data retention time 0 ns
tR2, 3 Operation recovery time tAVAV ns
VDD
DATA RETENTION MODE
tR
50%
50% VDR > 2.0V
Figure 7. Low VDD Data Retention Waveform
tEFR
E
12
PACKAGING
Figure 8. 36-pin Ceramic FLATPACK
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance to MIL-PRF-38535.
4. Lead position and coplanarity are not measured.
5. ID mark is vendor option.
6. Total weight is approx. 3.42 grams
13
1. All package finishes are per MIL-PRF-38535.
2. Letter designations are for cross-reference to MIL-STD-1835.
3. All leads increase max. limit by 0.003 measured at the center of the flat, when lead finish A (solder) is applied.
4. Total weight is approx. 10.77 g.
5. X-rays are an ineffective test for shielded packages.
Figure 9. 36-lead flatpack shielded package
14
ORDERING INFORMATION
512K x 8 SRAM:
= 25ns access time, 3.3V operation
20 = 20ns access time, 3.3V operation
Package Type:
(I) = 36-lead flatpack shielded package (bottom brazed)
(U) = 36-lead flatpack package (bottom brazed)
Screening:
(C) = Military Temperature Range flow
(P) = Prototype flow
(W) = Extended Industrial Temperature Range Flow (-40oC to +125oC)
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither
tested nor guaranteed.
4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and +125°C.
Radiation neither tested nor guaranteed.
5. 36LBBFP Shielded Package for reduced high rel orders only.
6. Extended Industrial Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -40°C to +125°C.
Radiation neither tested nor guaranteed.
UT8Q512 - * * * *
-Aeroflex UTMC Core Part Number
15
512K x 8 SRAM: SMD
5962 -
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
Case Outline:
(X) = 36-lead flatpack shielded package (bottom-brazed)
(U) = 36-lead ceramic flatpack (bottom-brazed)
Class Designator:
(T) = QML Class T
(Q) = QML Class Q
Device Type
01 = 25ns access time, 3.3V operation, Mil-Temp
02 = 25ns access time, 3.3V operation, Extended Industrial Temp (-40oC to +125oC)
03 = 20ns access time, 3.3V operation, Mil-Temp
04 = 20ns access time, 3.3V operation, Extended Industrial Temp (-40oC to +125oC)
Drawing Number: 99607
Total Dose:
(D) = 1E4 (10krad)(Si))
(P) = 3E4 (30krad)(Si)) (contact factory)
(L) = 5E4 (50krad(Si)) (contact factory)
Federal Stock Class Designator: No options
** ***
Notes:
1.Lead finish (A,C, or X) must be specified.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering.
99607
