© 2010 Freescale Semiconductor, Inc. All rights reserved.
Freescale Semiconductor
Technical Data
This document contains detailed information on power
considerations, DC/AC electrical characteristics, and AC
timing specifications for the .29 μm (HiP3) devices of the
Power QUICC II family of communic ations proce ssors : the
MPC8260 and the MPC8255. Throughout this document,
the MPC8260 and the MPC 8255 ar e collectively r eferred to
as the MP C8260.
Document Number: MPC8260EC
Rev. 2, 05/2010
Contents
1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical and Thermal Characteristics . . . . . . . . . . . . 5
3. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 20
4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 37
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 39
7. Document Revision History . . . . . . . . . . . . . . . . . . . 39
MPC8260
PowerQUICC II Integrated
Communications Processor
Hardware Specifications
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
2Freescale Semiconductor
Features
Figure 1 shows the block diagram for the MPC8260.
Figure 1. MPC8260 Block Diagram
1 Features
The major features of the MPC8260 are as follow s:
• Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 133–200 MHz (150–200 MHz for the
MPC8255)
— Separate 16-Kbyte data and instruction caches:
– F our-way set asso ciat iv e
– P hysically addressed
– LRU replacement algorithm
— Power PC archite cture -compliant memory management unit (MMU)
16 Kbytes
G2 Core
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
24 Kbytes
32-bit RISC Microcontroller
and Program ROM
Serial
DMAs
2 Virtual
IDMAs
Bridge
Memory Controller
Clock Counter
System Functions
System Interface Unit
(SIU)
Local Bus
32 bits, up to 66 MHz
MCC11MCC2 FCC1 FCC2 FCC31SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C
Serial Interface
3 MII 2 UTOPIA
PortsPorts3
60x Bus
Dual-Port RAM
Interrupt
Controller
Time Slot Assigner
8 TDM Ports2Non-Multiplexed
I/O
60x-to-Local
Bus Interface Unit
Notes:
1 Not on MPC8255
2 4 on the MPC8255
3 2 on the MPC8255
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 3
Features
— Common on-chip processor (COP) test interface
— High- performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for da ta cache coherency
— Fl oati ng-point unit (FPU)
• Separate power supply for internal logic and for I/O
• Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at diff erent frequenci es for power/perfor manc e optimization
— I nternal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
• 64-bit data and 32-bit address 60x bus
— Bus supports multiple maste r designs
— Supports single- and four -beat burst transfers
— 64- , 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
• 32-bit data and 18-bit address local bus
— Si ngle-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
• System interf ace unit (SIU)
— Clock synthes izer
— Reset controller
— R e al-time cl ock (RTC) registe r
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IE EE Std 1149.1™ JTAG test access port
• Twelve-bank memory controller
— Glueless interf ace to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and sele ctable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selec ts for 64 bus width (60x) and byte selects for 32 bus width ( local)
— Dedicated interface logic for SDRAM
• CPU core can be dis abled and the device can be used in slave mode to an ext erna l core
• Communications proc essor module (CPM)
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
4Freescale Semiconductor
Features
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communic ations protocols
— Inter faces to G2 core through on-chip 24-Kbyte dual-port RAM and DMA controlle r
— Serial DMA channels for receive and transm it on all serial channels
— Par al lel I/O registe rs with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory a nd memory-to-I/O transfers
— Three fa st communications c ontrollers (two on the MPC8255) supporting the following
protocols:
– 10/100-Mbit Ethernet/IEEE Std 802.3™ CDM A/CS interface through media indepe ndent
inter fa ce (M II )
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,
AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traff ic types, up to 16 K external
connections
– Transparent
– HDLC—Up to T3 ra tes (clear channel)
— Two multichannel controlle rs (MCCs) (only MCC2 on the MPC82 55)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split
into four subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interf aces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA /CS
– HDLC /SDLC and HDLC bus
– Univer sal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management f or BRI devices as ge neral circuit interf ace (GCI) controllers in time -
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One inte r -integrated circuit (I2C) controller (identical to the MPC860 I2C controller)
– Microwire compa tible
– Multiple-master, single-master, and slave modes
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 5
Electrical and Thermal Characteristics
— Up to eight TDM interfaces (4 on the MPC8255)
– Supports two groups of four TDM channels for a total of eight TDMs
– 2,048 bytes of SI RAM
– Bit or b yte reso lution
– Independent transmit and receive routing, frame synchronization
– Supports T1, CEP T , T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate ge nerator s and 20 input clock pins for supplying clocks to F CCs,
SCCs, SM Cs, and serial channels
— Four independent 16-bit timers that can be intercon nected as two 32-bit timers
2 Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8260.
2.1 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MPC8260. Table 1 shows the maximum
electrical ratings.
Table 1. Absolute Maximum Ratings1
1Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
Rating Symbol Value Unit
Core supply voltage2
2Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset.
VDD -0.3 – 2.75 V
PLL supply voltage2VCCSYN -0.3 – 2.75 V
I/O supply voltage3
3Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should
not exceed VDD/VCCSYN by more than 2.0 V during normal operation.
VDDH -0.3 – 4.0 V
Input voltage4
4Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
VIN GND(-0.3) – 3.6 V
Junction temperature Tj120 °C
Storage temperature range TSTG (-55) – (+150) °C
Note:
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
6Freescale Semiconductor
Electrical and Thermal Characteristics
Table 2 lists recommended operational voltage conditions.
NOTE: Core, PLL, and I/O Supply Voltages
VDDH, VCCSYN, and VDD must track each other and both must vary in
the same direction—in the positive direction (+5% and +0.1 Vdc) or in the
negative direction (–5% and –0.1 Vdc).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltage s to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or VCC).
Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the
MPC8280. Note that in PCI mode the I/O interface is different.
Figure 2. Overshoot/Undershoot Voltage
Table 2. Recommended Operating Conditions1
1Caution: These are the recommended and tested operating conditions. Proper device operating outside of these
conditions is not guaranteed.
Rating Symbol 2.5-V Device2
2Parts labeled with an “-HVA” suffix are 2.6-V devices.
Unit
Core supply voltage VDD 2.4–2.7 V
PLL supply voltage VCCSYN 2.4–2.7 V
I/O supply voltage VDDH 3.135 – 3.465 V
Input voltage VIN GND (-0.3) – 3.465 V
Junction temperature (maximum) Tj105 °C
GND
GND – 0.3 V
GND – 1.0 V
Not to exceed 10%
GVDD
of tSDRAM_CLK
GVDD + 5%
4 V
VIH
VIL
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 7
Electrical and Thermal Characteristics
Table 3 shows DC electrical characteristics.
Table 3. DC Electrical Characteristics1
Characteristic Symbol Min Max Unit
Input high voltage, all inputs except CLKIN VIH 2.0 3.465 V
Input low voltage VIL GND 0.8 V
CLKIN input high voltage VIHC 2.4 3.465 V
CLKIN input low voltage VILC GND 0.4 V
Input leakage current, VIN = VDDH2IIN —10µA
Hi-Z (off state) leakage current, VIN = VDDH2IOZ —10µA
Signal low input current, VIL = 0.8 V IL—1µA
Signal high input current, VIH = 2.0 V IH—1µA
Output high voltage, IOH = –2 mA
except XFC, UTOPIA mode, and open drain pins
In UTOPIA mode: IOH = -8.0mA
PA [0 - 3 1]
PB[4-31]
PC[0-31]
PD[4-31]
VOH 2.4 — V
In UTOPIA mode: IOL = 8.0mA
PA [0 - 3 1]
PB[4-31]
PC[0-31]
PD[4-31]
VOL —0.5 V
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
8Freescale Semiconductor
Electrical and Thermal Characteristics
IOL = 7.0mA
BR
BG
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0-63]
DP(0)/RSRV/EXT_BR2
DP(1)/IRQ1/EXT_BG2
DP(2)/TLBISYNC/IRQ2/EXT_DBG2
DP(3)/IRQ3/EXT_BR3/CKSTP_OUT
DP(4)/IRQ4/EXT_BG3/CORE_SREST
DP(5)/TBEN/IRQ5/EXT_DBG3
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
HRESET
SRESET
RSTCONF
QREQ
VOL —0.4 V
Table 3. DC Electrical Characteristics1 (continued)
Characteristic Symbol Min Max Unit
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 9
Electrical and Thermal Characteristics
IOL = 5.3mA
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE(0:7)/PSDDQM(0:7)/PBS(0:7)
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM[0:3]/LBS[0–3]
LSDA10/LGPL0
LSDWE/LGPL1
LOE/LSDRAS/LGPL2
LSDCAS/LGPL3
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX3/LGPL5
LWR
MODCK1/AP(1)/TC(0)/BNKSEL(0)
MODCK2/AP(2)/TC(1)/BNKSEL(1)
MODCK3/AP(3)/TC(2)/BNKSEL(2)
IOL = 3.2mA
L_A14
L_A15/SMI
L_A16
L_A17/CKSTP_OUT
L_A18
L_A19
L_A20
L_A21
L_A22
L_A23
L_A24
L_A25
L_A26
L_A27
L_A28/CORE_SRESET
L_A29
L_A30
L_A31
LCL_D(0-31)
LCL_DP(0-3)
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
VOL —0.4 V
1The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive DC current,
it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
2The leakage current is measured for nominal VDD, VCCSYN, and VDD.
Table 3. DC Electrical Characteristics1 (continued)
Characteristic Symbol Min Max Unit
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
10 Freescale Semiconductor
Electrical and Thermal Characteristics
2.2 Thermal Characteristics
Table 4 describes thermal characteristics .
2.3 Power Considerations
The average chip-junction temper at ure , TJ, in °C can be obtained from the following:
TJ = TA + (PD x θJA) (1)
where
TA = ambi en t tem pe ratu re °C
θJA = package thermal resistance, junction to ambient, °C/W
PD = PINT + PI/O
PINT = IDD x VDD Watts (chip internal pow er)
PI/O = power dissipation on input and output pins (determi ned by user)
For most applications PI/O < 0.3 x PINT. If PI/O is neglected, an approximate relationship between PD and
TJ is the following:
PD = K/(TJ + 273° C) (2)
Solving equations (1) and (2) f or K gives :
K = PD x (TA + 273° C) + θJA x PD2 (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
PD (at equilibrium) for a known TA. Using this value of K, the va lues of PD and TJ can be obtained by
solving e quations (1) and (2) iteratively for any value of TA.
3Rev C.2 silicon only.
Table 4. Thermal Characteristics
Characteristics Symbol Value Unit Air Flow
Thermal resistance for TBGA θJA 13.071
1Assumes a single layer board with no thermal vias
°C/W NC2
2Natural convection
θJA 9.551°C/W 1 m/s
θJA 10.483
3Assumes a four layer board
°C/W NC
θJA 7.783°C/W 1 m/s
Note:
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 11
Electrical and Thermal Characteristics
2.3.1 Layout Practices
Each VCC pin should be provided with a low-impedance path to the board’s power supply. Each ground
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four
0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an
inch per capacitor lead. A f our-layer board is recommended, employi ng two inner layers as VCC and GND
planes.
All output pins on the MPC8260 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and reflections caused by these
fast output switching times. This recommendation particula rly applies to the addre ss and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capac itive loads because these loads create
higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be
inputs during reset. Special c are should be taken to minimize the noise levels on the PLL supply pins.
Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required for conditions above PD = 3W (when the ambient temperature is 70° C or
greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that
the I/O power should be included when determining whether to use a heat sink.
Table 5. Estimated Power Dissipation for Various Configurations1
1Test temperature = room temperature (25° C)
Bus
(MHz)
CPM
Multiplier
CPU
Multiplier
CPM
(MHz)
CPU
(MHz)
PINT (W)2
2PINT = IDD x VDD Watts
Vddl
2.4 2.5 2.6 2.7 2.83
32.8 Vddl does not apply to HiP3 Rev C silicon.
33.3 4 4 133.3 133.3 2.04 2.14 2.26 2.38 2.50
50.0 2 3 100 150.0 2.21 2.30 2.45 2.59 2.69
66.7 2 2.5 133.3 166.7 2.47 2.62 2.74 2.88 3.02
66.7 2.5 2.5 166.7 166.7 2.57 2.69 2.83 2.98 3.12
66.7 2 3 133.3 200.0 2.81 2.95 3.12 3.29 3.43
66.7 2.5 3 166.7 200.0 2.88 3.05 3.22 3.38 3.55
50.0 3 4 150 200.0 2.83 3.00 3.14 3.31 3.48
Note:
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
12 Freescale Semiconductor
Electrical and Thermal Characteristics
2.4 AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for the 66 MHz MPC8260 device. Note that AC timings are based on a 50-pf load. Typical output
buf fer impedances are shown in Table 6.
Table 7 lists CPM output characteristics.
Table 8 lists CPM input characteristics.
NOTE: Rise/Fall Time on CPM Input Pins
It is recommended that the rise/fall time on CPM input pins should not
exceed 5 ns. This should be enforced especially on clock signals. Rise time
refe rs to signal trans itions from 10% to 90% of VCC; fall time refers to
transitions from 90% to 10% of VCC.
Table 6. Output Buffer Impedances1
1These are typical values at 65° C. The impedance
may vary by ±25% with process and temperature.
Output Buffers Typical Impedance (Ω)
60x bus 40
Local bus 40
Memory controller 40
Parallel I/O 46
Note:
Table 7. AC Characteristics for CPM Outputs1
1Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
Spec Number
Characteristic
Max Delay (ns) Min Delay (ns)
Max Min 66 MHz 66 MHz
sp36a sp37a FCC outputs—internal clock (NMSI) 6 1
sp36b sp37b FCC outputs—external clock (NMSI) 14 2
sp40 sp41 TDM outputs/SI 25 5
sp38a sp39a SCC/SMC/SPI/I2C outputs—internal clock (NMSI) 19 1
sp38b sp39b Ex_SCC/SMC/SPI/I2C outputs—external clock (NMSI) 19 2
sp42 sp43 PIO/TIMER/IDMA outputs 14 1
Note:
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 13
Electrical and Thermal Characteristics
Note that although the specifications generally reference the rising edge of the clock, the following AC
timing diagrams also apply when the falling edge is the active edge.
Table 8. AC Characteristics for CPM Inputs1
1Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
Spec Number
Characteristic
Setup (ns) Hold (ns)
Setup Hold 66 MHz 66 MHz
sp16a sp17a FCC inputs—internal clock (NMSI) 10 0
sp16b sp17b FCC inputs—external clock (NMSI) 3 3
sp20 sp21 TDM inputs/SI 15 12
sp18a sp19a SCC/SMC/SPI/I2C inputs—internal clock (NMSI) 20 0
sp18b sp19b SCC/SMC/SPI/I2C inputs—external clock (NMSI) 5 5
sp22 sp23 PIO/TIMER/IDMA inputs 10 3
Note:
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
14 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 3 shows the FCC external clock.
Figure 3. FCC External Clock Diagram
Figure 4 shows the FCC internal clock.
Figure 4. FCC Internal Clock Diagram
Serial ClKin
FCC input signals
FCC output signals
FCC output signals
Note: When GFMR[TCI] = 1
Note: When GFMR[TCI] = 0
sp16b
sp17b
sp36b/sp37b
sp36b/sp37b
BRG_OUT
FCC input signals
FCC output signals
FCC output signals
Note: When GFMR.[TCI] = 1
Note: When GFMR[TCI] = 0 sp36a/sp37a
sp36a/sp37a
sp17a
sp16a
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 15
Electrical and Thermal Characteristics
Figure 5 shows the SCC/SMC/SPI/I2C externa l clock.
Figure 5. SCC/SMC/SPI/I2C External Clock Diagram
Figure 6 shows the SCC/SMC/SPI/I2C internal cl ock.
Figure 6. SCC/SMC/SPI/I2C Internal Clock Diagram
Serial CLKin
SCC/SMC/SPI/I2C input signals
SCC/SMC/SPI/I2C output signals
sp18b sp19b
sp38b/sp39b
(See note)
(See note)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
BRG_OUT
SCC/SMC/SPI/I2C input signals
SCC/SMC/SPI/I2C output signals
sp18a sp19a
sp38a/sp39a
(See note)
(See note)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
16 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 7 shows PIO, timer , and DMA signals.
Figure 7. PIO, Timer, and DMA Signal Diagram
Table 9 lists SIU input characteristics.
Table 9. AC Characteristics for SIU Inputs1
1Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
Spec Number
Characteristic
Setup (ns) Hold (ns)
Setup Hold 66 MHz 66 MHz
sp11 sp10 AACK/ARTRY/TA/TS/TEA/DBG/BG/BR 61
sp12 sp10 Data bus in normal mode 5 1
sp13 sp10 Data bus in ECC and PARITY modes 8 1
sp14 sp10 DP pins 8 1
sp14 sp10 All other pins 5 1
Note:
Sys clk
PIO/IDMA/TIMER[TGATE assertion] input signals
IDMA output signals
sp22
sp23
sp42/sp43
TIMER/PIO
output signals
sp42/sp43
TIMER input signal [TGATE deassertion]
sp22
sp23
Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
(See note)
(See note)
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 17
Electrical and Thermal Characteristics
Table 10 lists SIU output characteristics.
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when EC C or PARITY are used. Als o, sp33a
can be used a s the AC spe cification for DP signals .
Figure 8 shows TDM input and output signals.
Figure 8. TDM Signal Diagram
Table 10. AC Characteristics for SIU Outputs1
1Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
NOTE
Spec Number
Characteristic
Max Delay (ns) Min Delay (ns)
Max Min 66 MHz 66 MHz
sp31 sp30 PSDVAL/TEA/TA 10 0.5
sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT 8 0.5
sp33a sp30 Data bus 8 0.5
sp33b sp30 DP 12 0.5
sp34 sp30 memc signals/ALE 6 0.5
sp35 sp30 all other signals 7.5 0.5
Note:
Serial CLKin
TDM input signals
TDM output signals
sp20 sp21
sp40/sp41
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
18 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 9 shows the interaction of several bus signals.
Figure 9. Bus Signals
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
Figure 10. Parity Mode Diagram
CLKin
DATA bus, ECC, and PARITY mode input signals
DP mode input signal
DP mode output signal
sp13
sp10
sp14
sp10
sp33b/sp30
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 19
Electrical and Thermal Characteristics
Figure 11 shows signal behavior in MEMC mode.
Figure 11. MEMC Mode Diagram
NOTE
Generally, all MPC8260 bus and system output signals are driven from the
rising edge of the input clock (CLKin). Memory c ontroller signals,
however , trigger on four points within a CLKin cycle. Each cycle is divided
by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising
edge, and T3 at the falling edge, of CLKin. However , the spacing of T 2 and
T4 depends on the PLL clock ratio selected, as shown in Table 11.
Figure 12 is a graphical representation of Table 11.
Figure 12. Internal Tick Spacing for Memory Controller Signals
Table 11. Tick Spacing for Memory Controller Signals
PLL Clock Ratio
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2 T3 T4
1:2, 1:3, 1:4, 1:5, 1:6 1/4 CLKin 1/2 CLKin 3/4 CLKin
1:2.5 3/10 CLKin 1/2 CLKin 8/10 CLKin
1:3.5 4/14 CLKin 1/2 CLKin 11/14 CLKin
CLKin
V_CLK
Memory controller signals sp34/sp30
CLKin
T1 T2 T3 T4
CLKin
T1 T2 T3 T4
for 1:2.5
for 1:3.5
CLKin
T1 T2 T3 T4
for 1:2, 1:3, 1:4, 1:5, 1:6
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
20 Freescale Semiconductor
Clock Configuration Modes
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs ch ange on
CLKin’s rising edge.
3 Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Table 12 shows the eight basic configuration
modes. Another 49 modes are available by using the configuration pin (RSTCONF) and driving four pins
on the data bus.
NOTE
Clock configurations change only after POR is ass er t ed.
3.1 Local Bus Mode
Table 12 describes default clock modes for the MPC8260.
Table 13 describes all possible clock configurations when using the hard reset c onfiguration sequence.
Note also that basic modes are shown in boldface type.
Table 12. Clock Default Modes
MODCK[1–3] Input Clock
Frequency
CPM Multiplication
Factor
CPM
Frequency Core Multiplication Factor Core Frequency
000 33 MHz 3 100 MHz 4 133 MHz
001 33 MHz 3 100 MHz 5 166 MHz
010 33 MHz 4 133 MHz 4 133 MHz
011 33 MHz 4 133 MHz 5 166 MHz
100 66 MHz 2 133 MHz 2.5 166 MHz
101 66 MHz 2 133 MHz 3 200 MHz
110 66 MHz 2.5 166 MHz 2.5 166 MHz
111 66 MHz 2.5 166 MHz 3 200 MHz
Table 13. Clock Configuration Modes1
MODCK_H–MODCK[1–3] Input Clock
Frequency2,3,4
CPM Multiplication
Factor2, 5
CPM
Frequency2
Core Multiplication
Factor2, 6
Core
Frequency2
0001_000 33 MHz 2 66 MHz 4 133 MHz
0001_001 33 MHz 2 66 MHz 5 166 MHz
0001_010 33 MHz 2 66 MHz 6 200 MHz
0001_011 33 MHz 2 66 MHz 7 233 MHz
0001_100 33 MHz 2 66 MHz 8 266 MHz
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 21
Clock Configuration Modes
0001_101 33 MHz 3 100 MHz 4133 MHz
0001_110 33 MHz 3 100 MHz 5166 MHz
0001_111 33 MHz 3 100 MHz 6 200 MHz
0010_000 33 MHz 3 100 MHz 7 233 MHz
0010_001 33 MHz 3 100 MHz 8 266 MHz
0010_010 33 MHz 4 133 MHz 4 133 MHz
0010_011 33 MHz 4 133 MHz 5 166 MHz
0010_100 33 MHz 4 133 MHz 6 200 MHz
0010_101 33 MHz 4 133 MHz 7 233 MHz
0010_110 33 MHz 4 133 MHz 8 266 MHz
0010_111 33 MHz 5 166 MHz 4 133 MHz
0011_000 33 MHz 5 166 MHz 5 166 MHz
0011_001 33 MHz 5 166 MHz 6 200 MHz
0011_010 33 MHz 5 166 MHz 7 233 MHz
0011_011 33 MHz 5 166 MHz 8 266 MHz
0011_100 33 MHz 6 200 MHz 4 133 MHz
0011_101 33 MHz 6 200 MHz 5 166 MHz
0011_110 33 MHz 6 200 MHz 6 200 MHz
0011_111 33 MHz 6 200 MHz 7 233 MHz
0100_000 33 MHz 6 200 MHz 8 266 MHz
0100_001 Reserved
0100_010
0100_011
0100_100
0100_101
0100_110
Table 13. Clock Configuration Modes1 (continued)
MODCK_H–MODCK[1–3] Input Clock
Frequency2,3,4
CPM Multiplication
Factor2, 5
CPM
Frequency2
Core Multiplication
Factor2, 6
Core
Frequency2
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
22 Freescale Semiconductor
Clock Configuration Modes
0100_111 Reserved
0101_000
0101_001
0101_010
0101_011
0101_100
0101_101 66 MHz 2 133 MHz 2 133 MHz
0101_110 66 MHz 2 133 MHz 2.5 166 MHz
0101_111 66 MHz 2 133 MHz 3 200 MHz
0110_000 66 MHz 2 133 MHz 3.5 233 MHz
0110_001 66 MHz 2 133 MHz 4 266 MHz
0110_010 66 MHz 2 133 MHz 4.5 300 MHz
0110_011 66 MHz 2.5 166 MHz 2 133 MHz
0110_100 66 MHz 2.5 166 MHz 2.5 166 MHz
0110_101 66 MHz 2.5 166 MHz 3 200 MHz
0110_110 66 MHz 2.5 166 MHz 3.5 233 MHz
0110_111 66 MHz 2.5 166 MHz 4 266 MHz
0111_000 66 MHz 2.5 166 MHz 4.5 300 MHz
0111_001 66 MHz 3 200 MHz 2 133 MHz
0111_010 66 MHz 3 200 MHz 2.5 166 MHz
0111_011 66 MHz 3 200 MHz 3 200 MHz
0111_100 66 MHz 3 200 MHz 3.5 233 MHz
0111_101 66 MHz 3 200 MHz 4 266 MHz
0111_110 66 MHz 3 200 MHz 4.5 300 MHz
0111_111 66 MHz 3.5 233 MHz 2 133 MHz
1000_000 66 MHz 3.5 233 MHz 2.5 166 MHz
1000_001 66 MHz 3.5 233 MHz 3 200 MHz
1000_010 66 MHz 3.5 233 MHz 3.5 233 MHz
1000_011 66 MHz 3.5 233 MHz 4 266 MHz
1000_100 66 MHz 3.5 233 MHz 4.5 300 MHz
Note:
Table 13. Clock Configuration Modes1 (continued)
MODCK_H–MODCK[1–3] Input Clock
Frequency2,3,4
CPM Multiplication
Factor2, 5
CPM
Frequency2
Core Multiplication
Factor2, 6
Core
Frequency2
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 23
Pinout
4 Pinout
This section provides the pin assignments and pinout list for the MPC8260.
1Because of speed dependencies, not all of the possible configurations in Ta b l e 1 3 are applicable.
2The user should choose the input clock frequency and the multiplication factors such that the frequency of the CPU ranges
between 133–200 and the CPM ranges between 50–166 MHz.
3Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that the resulting
configuration does not exceed the frequency rating of the user’s part.
460x and local bus frequency. Identical to CLKIN.
5CPM multiplication factor = CPM clock/bus clock
6CPU multiplication factor = Core PLL multiplication factor
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
24 Freescale Semiconductor
Pinout
4.1 Pin Assignments
Figure 13 shows the pinout of the MPC8260 480 TBGA package as viewed from the top surface.
Figure 13. Pinout of the 480 TBGA Package as Viewed from the Top Surface
1 2 3 4 5 6 7 8 91011121314151617 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 25
Pinout
Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view.
Figure 14. Side View of the TBGA Package
Table 14 shows the pinout list of the MPC8260. Table 15 defines conventions and acronyms used in
Table 14.
Table 14. Pinout List
Pin Name Ball
BR W5
BG F4
ABB/IRQ2 E2
TS E3
A0 G1
A1 H5
A2 H2
A3 H1
A4 J5
A5 J4
A6 J3
A7 J2
A8 J1
A9 K4
A10 K3
A11 K2
A12 K1
A13 L5
A14 L4
A15 L3
A16 L2
A17 L1
Soldermask
Copper Traces
Die
Copper Heat Spreader
(Oxidized for Insulation)
1.27 mm Pitch
Glob-Top Dam
Wire Bonds
Etched
Pressure Sensitive
Die
Glob-Top Filled Area
Polymide Tape Cavity
Adhesive
Attach
View
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
26 Freescale Semiconductor
Pinout
A18 M5
A19 N5
A20 N4
A21 N3
A22 N2
A23 N1
A24 P4
A25 P3
A26 P2
A27 P1
A28 R1
A29 R3
A30 R5
A31 R4
TT0 F1
TT1 G4
TT2 G3
TT3 G2
TT4 F2
TBST D3
TSIZ0 C1
TSIZ1 E4
TSIZ2 D2
TSIZ3 F5
AACK F3
ARTRY E1
DBG V1
DBB/IRQ3 V2
D0 B20
D1 A18
D2 A16
D3 A13
D4 E12
D5 D9
D6 A6
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 27
Pinout
D7 B5
D8 A20
D9 E17
D10 B15
D11 B13
D12 A11
D13 E9
D14 B7
D15 B4
D16 D19
D17 D17
D18 D15
D19 C13
D20 B11
D21 A8
D22 A5
D23 C5
D24 C19
D25 C17
D26 C15
D27 D13
D28 C11
D29 B8
D30 A4
D31 E6
D32 E18
D33 B17
D34 A15
D35 A12
D36 D11
D37 C8
D38 E7
D39 A3
D40 D18
D41 A17
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
28 Freescale Semiconductor
Pinout
D42 A14
D43 B12
D44 A10
D45 D8
D46 B6
D47 C4
D48 C18
D49 E16
D50 B14
D51 C12
D52 B10
D53 A7
D54 C6
D55 D5
D56 B18
D57 B16
D58 E14
D59 D12
D60 C10
D61 E8
D62 D6
D63 C2
DP0/RSRV/EXT_BR2 B22
IRQ1/DP1/EXT_BG2 A22
IRQ2/DP2/TLBISYNC/EXT_DBG2 E21
IRQ3/DP3/CKSTP_OUT/EXT_BR3 D21
IRQ4/DP4/CORE_SRESET/EXT_BG3 C21
IRQ5/DP5/TBEN/EXT_DBG3 B21
IRQ6/DP6/CSE0 A21
IRQ7/DP7/CSE1 E20
PSDVAL V3
TA C22
TEA V5
GBL/IRQ1 W1
CI/BADDR29/IRQ2 U2
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 29
Pinout
WT/BADDR30/IRQ3 U3
L2_HIT/IRQ4 Y4
CPU_BG/BADDR31/IRQ5 U4
CPU_DBG R2
CPU_BR Y3
CS0 F25
CS1 C29
CS2 E27
CS3 E28
CS4 F26
CS5 F27
CS6 F28
CS7 G25
CS8 D29
CS9 E29
CS10/BCTL1 F29
CS11/AP0 G28
BADDR27 T5
BADDR28 U1
ALE T2
BCTL0 A27
PWE0/PSDDQM0/PBS0 C25
PWE1/PSDDQM1/PBS1 E24
PWE2/PSDDQM2/PBS2 D24
PWE3/PSDDQM3/PBS3 C24
PWE4/PSDDQM4/PBS4 B26
PWE5/PSDDQM5/PBS5 A26
PWE6/PSDDQM6/PBS6 B25
PWE7/PSDDQM7/PBS7 A25
PSDA10/PGPL0 E23
PSDWE/PGPL1 B24
POE/PSDRAS/PGPL2 A24
PSDCAS/PGPL3 B23
PGTA/PUPMWAIT/PGPL4/PPBS A23
PSDAMUX/PGPL5 D22
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
30 Freescale Semiconductor
Pinout
LWE0/LSDDQM0/LBS0 H28
LWE1/LSDDQM1/LBS1 H27
LWE2/LSDDQM2/LBS2 H26
LWE3/LSDDQM3/LBS3 G29
LSDA10/LGPL0 D27
LSDWE/LGPL1 C28
LOE/LSDRAS/LGPL2 E26
LSDCAS/LGPL3 D25
LGTA/LUPMWAIT/LGPL4/LPBS C26
LGPL5/LSDAMUX1B27
LWR D28
L_A14 N27
L_A15/SMI T29
L_A16 R27
L_A17/CKSTP_OUT R26
L_A18 R29
L_A19 R28
L_A20 W29
L_A21 P28
L_A22 N26
L_A23 AA27
L_A24 P29
L_A25 AA26
L_A26 N25
L_A27 AA25
L_A28/CORE_SRESET AB29
L_A29 AB28
L_A30 P25
L_A31 AB27
LCL_D0 H29
LCL_D1 J29
LCL_D2 J28
LCL_D3 J27
LCL_D4 J26
LCL_D5 J25
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 31
Pinout
LCL_D6 K25
LCL_D7 L29
LCL_D8 L27
LCL_D9 L26
LCL_D10 L25
LCL_D11 M29
LCL_D12 M28
LCL_D13 M27
LCL_D14 M26
LCL_D15 N29
LCL_D16 T25
LCL_D17 U27
LCL_D18 U26
LCL_D19 U25
LCL_D20 V29
LCL_D21 V28
LCL_D22 V27
LCL_D23 V26
LCL_D24 W27
LCL_D25 W26
LCL_D26 W25
LCL_D27 Y29
LCL_D28 Y28
LCL_D29 Y25
LCL_D30 AA29
LCL_D31 AA28
LCL_DP0 L28
LCL_DP1 N28
LCL_DP2 T28
LCL_DP3 W28
IRQ0/NMI_OUT T1
IRQ7/INT_OUT/APE D1
TRST AH3
TCK AG5
TMS AJ3
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
32 Freescale Semiconductor
Pinout
TDI AE6
TDO AF5
TRIS AB4
PORESET AG6
HRESET AH5
SRESET AF6
QREQ AA3
RSTCONF AJ4
MODCK1/AP1/TC0/BNKSEL0 W2
MODCK2/AP2/TC1/BNKSEL1 W3
MODCK3/AP3/TC2/BNKSEL2 W4
XFC AB2
CLKIN1 AH4
PA0/RESTART1/DREQ3/FCC2_UTM_TXADDR2 AC292
PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3 AC252
PA2/CLK20/FCC2_UTM_TXADDR0/DACK3 AE282
PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2 AG292
PA4/REJECT2/FCC2_UTM_RXADDR1/DONE4 AG282
PA5/RESTART2/DREQ4/FCC2_UTM_RXADDR2 AG262
PA6/L1RSYNCA1 AE242
PA7/SMSYN2/L1TSYNCA1/L1GNTA1 AH252
PA8/SMRXD2/L1RXD0A1/L1RXDA1 AF232
PA9/SMTXD2/L1TXD0A1 AH232
PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5 AE222
PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4 AH222
PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3 AJ212
PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2 AH202
PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3 AG192
PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2 AF182
PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1 AF172
PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD AE162
PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD AJ162
PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1 AG152
PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2 AJ132
PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3 AE132
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 33
Pinout
PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11 AF122
PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10 AG112
PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1 AH92
PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0 AJ82
PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER AH72
PA27/FCC1_UT_RXSOC/FCC1_MII_RX_DV AF72
PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN AD52
PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER AF12
PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/FCC1_RTS AD32
PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL AB52
PB4/FCC3_TXD3/FCC2_UT8_RXD0/L1RSYNCA2/FCC3_RTS AD282
PB5/FCC3_TXD2/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2 AD262
PB6/FCC3_TXD1/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2 AD252
PB7/FCC3_TXD0/FCC3_TXD/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2 AE262
PB8/FCC2_UT8_TXD3/FCC3_RXD0/FCC3_RXD/TXD3/L1RSYNCD1 AH272
PB9/FCC2_UT8_TXD2/FCC3_RXD1/L1TXD2A2/L1TSYNCD1/L1GNTD1 AG242
PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1 AH242
PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1 AJ242
PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2 AG222
PB13/FCC3_MII_COL/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2 AH212
PB14/FCC3_MII_TX_EN/RXD3/L1RXDC1 AG202
PB15/FCC3_MII_TX_ER/RXD2/L1TXDC1 AF192
PB16/FCC3_MII_RX_ER/L1CLKOA1/CLK18 AJ182
PB17/FCC3_MII_RX_DV/L1RQA1/CLK17 AJ172
PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2 AE142
PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2 AF132
PB20/FCC2_UT8_RXD6/FCC2_RXD1/L1RSYNCD2/L1TXD1A1 AG122
PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2/
L1TXD2A1
AH112
PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_TXD/L1RXD1A1/L1RXDD2 AH162
PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1TXDD2 AE152
PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2 AJ92
PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1 AE92
PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2 AJ72
PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2 AH62
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
34 Freescale Semiconductor
Pinout
PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1 AE32
PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/L1RSYNCB2/
FCC2_MII_TX_EN
AE22
PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/L1RXDB2 AC52
PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2 AC42
PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2 AB262
PC1/DREQ2/BRGO6/L1RQA2 AD292
PC2/FCC3_CD/FCC2_UT8_TXD3/DONE2 AE292
PC3/FCC3_CTS/FCC2_UT8_TXD2/DACK2/CTS4 AE272
PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD AF272
PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS AF242
PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTS_RXADDR2/
FCC1_UTM_RXCLAV1
AJ262
PC7/FCC1_CTS/L1RQC1/FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/
FCC1_UTM_TXCLAV1
AJ252
PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3 AF222
PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2 AE212
PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3 AF202
PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2 AE192
PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/FCC1_UTS_RXADDR1 AE182
PC13/CTS2/CLSN2/L1RQD1/FCC1_UTM_TXADDR1/FCC1_UTS_TXADDR1 AH182
PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0 AH172
PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/FCC1_UTS_TXADDR0 AG162
PC16/CLK16/TIN4 AF152
PC17/CLK15/TIN3/BRGO8 AJ152
PC18/CLK14/TGATE2 AH142
PC19/CLK13/BRGO7/SPICLK AG132
PC20/CLK12/TGATE1 AH122
PC21/CLK11/BRGO6 AJ112
PC22/CLK10/DONE1 AG102
PC23/CLK9/BRGO5/DACK1 AE102
PC24/FCC2_UT8_TXD3/CLK8/TOUT4 AF92
PC25/FCC2_UT8_TXD2/CLK7/BRGO4 AE82
PC26/CLK6/TOUT3/TMCLK AJ62
PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3 AG22
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 AF32
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 35
Pinout
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 AF22
PC30/FCC2_UT8_TXD3/CLK2/TOUT1 AE12
PC31/CLK1/BRGO1 AD12
PD4/BRGO8/L1TSYNCD1/L1GNTD1/FCC3_RTS/SMRXD2 AC282
PD5/FCC1_UT16_TXD3/DONE1 AD272
PD6/FCC1_UT16_TXD4/DACK1 AF292
PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/
FCC1_UTM_TXADDR4/FCC1_TXCLAV2
AF282
PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5 AG252
PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3 AH262
PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4 AJ272
PD11/L1RQB2/FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1 AJ232
PD12/SI1_L1ST2/L1RXDB1 AG232
PD13/SI1_L1ST1/L1TXDB1 AJ222
PD14/FCC1_UT16_RXD0/L1CLKOC2/I2CSCL AE202
PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA AJ202
PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO AG182
PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI AG172
PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM_RXCLAV3/
SPICLK/FCC2_UTM_RXADDR3/FCC2_UTS_RXADDR0
AF162
PD19/FCC1_UTM_TXADDR4/FCC1_UTS_TXADDR4/FCC1_UTM_TXCLAV3/
SPISEL/BRGO1/FCC2_UTM_TXADDR3/FCC2_UTS_TXADDR0
AH152
PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2 AJ142
PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2 AH132
PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2 AJ122
PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1 AE122
PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1 AF102
PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1 AG92
PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1 AH82
PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1 AG72
PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1 AE42
PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/
FCC1_UTM_RXCLAV2/FCC2_UTM_RXADDR4/FCC2_UTS_RXADDR1
AG12
PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1 AD42
PD31/RXD1 AD22
VCCSYN AB3
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
36 Freescale Semiconductor
Pinout
Symbols used in Table 14 are described in Table 15.
VCCSYN1 B9
GNDSYN AB1
SPARE13AE11
SPARE43U5
SPARE54AF25
SPARE63V4
THERMAL05AA1
THERMAL15AG4
I/O power AG21, AG14, AG8, AJ1, AJ2, AH1,
AH2, AG3, AF4, AE5, AC27, Y27,
T27, P27, K26, G27, AE25, AF26,
AG27, AH28, AH29, AJ28, AJ29, C7,
C14, C16, C20, C23, E10, A28, A29,
B28, B29, C27, D26, E25, H3, M4,
T3, AA4, A1, A2, B1, B2, C3, D4, E5
Core Power U28, U29, K28, K29, A9, A19, B19,
M1, M2, Y1, Y2, AC1, AC2, AH19,
AJ19, AH10, AJ10, AJ5
Ground AA5, AF21, AF14, AF8, AE7, AF11,
AE17, AE23, AC26, AB25, Y26, V25,
T26, R25, P26, M25, K27, H25, G26,
D7, D10, D14, D16, D20, D23, C9,
E11, E13, E15, E19, E22, B3, G5,
H4, K5, M3, P5, T4, Y5, AA2, AC3
Note:
1Only on Rev C.2 silicon.
2The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive DC current,
it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
3Must be pulled down or left floating.
4Must be pulled down or left floating. However, if compatibility with HiP4 silicon is required, this pin must be pulled up or left
floating.
5For information on how to use this pin, refer to
MPC8260 PowerQUICC II Thermal Resistor Guide
available at
www.freescale.com.
Table 15. Symbol Legend
Symbol Meaning
OVERBAR Signals with overbars, such as TA, are active low
UTM Indicates that a signal is part of the UTOPIA master interface
Table 14. Pinout List (continued)
Pin Name Ball
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 37
Package Description
5 Package Description
The following sections provide the package parameters and mechanical dimensions for the MPC8260.
5.1 Package Parameters
Package parameters are provided in Table 16. The package type is a 37.5 × 37.5 mm, 480-lead TB GA.
UTS Indicates that a signal is part of the UTOPIA slave interface
UT8 Indicates that a signal is part of the 8-bit UTOPIA interface
UT16 Indicates that a signal is part of the 16-bit UTOPIA interface
MII Indicates that a signal is part of the media independent interface
Table 16. Package Parameters
Parameter Value
Package Outline 37.5 x 37.5 mm
Interconnects 480 (29 x 29 ball array)
Pitch 1.27 mm
Nominal unmounted package height 1.55 mm
Table 15. Symbol Legend (continued)
Symbol Meaning
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
38 Freescale Semiconductor
Package Description
5.2 Mechanical Dimensions
Figure 15 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA
package.
Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature
Dim
Millimeters
Min Max
A 1.45 1.65
A1 0.60 0.70
A2 0.85 0.95
A3 0.25 —
b 0.65 0.85
D 37.50 BSC
D1 35.56 REF
e1.27 BSC
E 37.50 BSC
E1 35.56 REF
Notes:
1. Dimensions and Tolerancing per
ASME Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the
maximum solder ball diameter, parallel
to primary data A.
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 39
Ordering Information
6 Ordering Information
Figure 16 provides an example of the Freescale part numbering nomenclature for the MPC8260. In
addition to the processor frequency, the part numbering scheme also consists of a part modifier that
indicates any enhancement(s) in the part from the original production design. Each part number also
contains a revision code that refers to the die mask revision number and is specified in the part numbering
scheme for identification purposes only. For more information, contact your local Freescale sales of fice.
Figure 16. Freescale Part Number Key
7 Document Revision History
Table 17 lists significant changes in each revision of this document.
Table 17. Document Revision History
Rev.
Number Date Substantive Change(s)
2 05/2010 Added a note about rise/fall time on CPM input pins above Ta b le 8 , “AC Characteristics for CPM Inputs.”
1.3 9/2005 • Document template update.
1.2 8/2003 • Note: In revision 0.7, sp30 (Table 10) was changed. This change was not previously recorded in this
“Document Revision History” Table.
• Addition of MPC8255 description to Section 1, “Features”
• Addition of Figure 2
• Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following Table 2
• Addition of note 1 to Ta bl e 3
• Addition of notes or modifications to Figure 3 through Figure 8
• Addition of reference notes 4, 5, and 6 to Tab le 1 3
• Addition of note 2 to Ta bl e 1 4
• Addition of SPICLK to PC19 in Ta bl e 1 4 . It is documented correctly in the
MPC8260 PowerQUICC
II™ Family Reference Manual
but had previously been omitted from Table 14.
1.1 5/2002 • Section 1, “Features”: updated minimum supported core frequency to 133 MHz
• Addition of “Note” at bottom of page 5.
• Table 13: Note 3.
Product Code
Device Number
Package
(ZU = 480 TBGA)
Core Voltage
Processor Frequency
Die Revision Level
MPC 82XX C ZU XXX
(CPU/CPM/Bus)
X
(Nn = Major.minor)
XX
Temperature Range
Blank = 0 to 105 °C
C = -40 to 105 °C
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
40 Freescale Semiconductor
Document Revision History
1.0 3/2002 • Table 14: modified notes to pins AE11 and AF25.
• Table 14: added note to pins AA1 and AG4 (Therm0 and Therm1).
0.9 2/2002 • Ta ble 14: additional note added to AE11
0.8 2/2002 • Table 7, Ta bl e 8 , Ta ble 9, and Ta b le 1 0 : revision 0.7 of this document incorrectly included values for
83 MHz. 83 MHz is not supported on the MPC8260.
• Table 14: notes added to pins at AE11, AF25, U5, and V4.
0.7 11/2001 • Revision of Ta bl e 5 , “Power Dissipation”
• Modifications to Figure 9, Table 2,Table 10, Table 11
• Additional revisions to text and figures throughout
0.6 5/2001 Corrected the thermal values in Table 3, “Thermal Characteristics.”
0.2–0.5 — Temporary revisions
0.1 1/2000 —
0 — Initial version
Table 17. Document Revision History (continued)
Rev.
Number Date Substantive Change(s)
Document Number: MPC8260EC
Rev. 2
05/2010
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