Philips Semiconductors Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
2
1998 Jul 29 853-1863 19804
FEATURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•Inputs accept voltages up to 5.5V
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when VCC = 0V
•8-bit positive edge-triggered register
•Independent register and 3-State buffer operation
•Flow-through pin-out architecture
DESCRIPTION
The 74LVC574A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC574A is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs
that meet the setup and hold times requirements on the
LOW-to-HIGH CP transition.
When OE is LOW , the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The ’574A’ is functionally identical to the ’374A’, but the ’374A’ has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0V ; Tamb =25°C; tr = tf 2.5ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH Propagation delay
CP to QnCL = 50pF
VCC = 3.3V 4.8 ns
fmax maximum clock frequency 150 MHz
CIInput capacitance 5.0 pF
CPD Power dissipation capacitance per
flip-flop Notes 1 and 2 20 pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
(CL x VCC2 x fo) = sum of outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES TEMPERATURE
RANGE OUTSIDE
NORTH AMERICA NORTH AMERICA PKG. DWG. #
20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C74LVC574A D 74LVC574A D SOT163-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C74LVC574A DB 74LVC574A DB SOT339-1
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C74LVC574A PW 7LVC574APW DH SOT360-1