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74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger
(3-State)
Product specification 1998 Jul 29
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
2
1998 Jul 29 853-1863 19804
FEATURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•Inputs accept voltages up to 5.5V
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when VCC = 0V
•8-bit positive edge-triggered register
•Independent register and 3-State buffer operation
•Flow-through pin-out architecture
DESCRIPTION
The 74LVC574A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC574A is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs
that meet the setup and hold times requirements on the
LOW-to-HIGH CP transition.
When OE is LOW , the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The ’574A’ is functionally identical to the ’374A’, but the ’374A’ has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0V ; Tamb =25°C; tr = tf 2.5ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH Propagation delay
CP to QnCL = 50pF
VCC = 3.3V 4.8 ns
fmax maximum clock frequency 150 MHz
CIInput capacitance 5.0 pF
CPD Power dissipation capacitance per
flip-flop Notes 1 and 2 20 pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
(CL x VCC2 x fo) = sum of outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES TEMPERATURE
RANGE OUTSIDE
NORTH AMERICA NORTH AMERICA PKG. DWG. #
20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C74LVC574A D 74LVC574A D SOT163-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C74LVC574A DB 74LVC574A DB SOT339-1
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C74LVC574A PW 7LVC574APW DH SOT360-1
Philips Semiconductors Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
1998 Jul 29 3
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enable input (active-Low)
2, 3, 4, 5,
6, 7, 8, 9 D0-D7 Data inputs
19, 18, 17, 16,
15, 14, 13, 12 Q0-Q7 Data outputs
10 GND Ground (0V)
11 CP Clock input (LOW-to-HIGH,
edge-triggered)
20 VCC Positive supply voltage
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
10 11
9
8
7
6
5
4
3
2
1VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
SA00400
LOGIC SYMBOL
11
1
CP
OE
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SA00401
LOGIC SYMBOL (IEEE/IEC)
1
219
318
417
516
C1
11 EN
615
714
813
912
1D
SA00402
FUNCTIONAL DIAGRAM
1
19
2
318
174
516
11
15
6
714
138
912
OE
Q0
D0
D1 Q1
Q2D2
D3 Q3
Q4D4
D5 Q5
Q6D6
D7 Q7
CP
SA00403
3-State
OUTPUTS
FF!
to
FF8
Philips Semiconductors Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
1998 Jul 29 4
LOGIC DIAGRAM
Q
D
D0
Q0
D
D1
D
D2
D
D3
D
D4
D
D5
D
D6
D
D7
Q1 Q2 Q3 Q4 Q5 Q6 Q7
CP
OE
QQQ QQQQ
CP CP CP CP CP CP CP CP
SA00404
FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8
FUNCTION TABLE
OPERATING MODES
INPUTS
INTERNAL FLIP-FLOPS
OUTPUTS
OPERATING
MODES
OE LE Dn
INTERNAL
FLIP
-
FLOPS
Q0 to Q7
Load and read register L
L°
°l
hL
HL
H
Load register and
disable outputs H
H°
°l
hL
HZ
Z
H = HIGH voltage level
h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition
Z = High impedance OFF-state
°= LOW-to-HIGH clock transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN MAX
UNIT
VCC
DC supply voltage (for max. speed performance) 2.7 3.6
V
V
CC DC supply voltage (for low-voltage applications) 1.2 3.6
V
VIDC Input voltage range 0 5.5 V
V
O
DC output voltage range; output HIGH or LOW
state 0 VCC V
O
DC output voltage range; output 3-State 0 5.5
Tamb Operating ambient temperature range in free-air –40 +85 °C
tr, tfInput rise and fall times VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V 0
020
10 ns/V
Philips Semiconductors Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
1998 Jul 29 5
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +6.5 V
IIK DC input diode current VI t0 –50 mA
VIDC input voltage Note 2 –0.5 to +6.5 V
IOK DC output diode current VO uVCC or VO t 0 "50 mA
VO
DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5
V
V
ODC output voltage; output 3-State Note 2 –0.5 to 6.5
V
IODC output source or sink current VO = 0 to VCC "50 mA
IGND, ICC DC VCC or GND current "100 mA
Tstg Storage temperature range –65 to +150 °C
Power dissipation per package
PTOT – plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
mW
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
V
HIGH level In
p
ut voltage
VCC = 1.2V VCC
V
IH
HIGH
le
v
el
Inp
u
t
v
oltage
VCC = 2.7 to 3.6V 2.0
V
LOW level In
p
ut voltage
VCC = 1.2V GND
V
IL
LOW
le
v
el
Inp
u
t
v
oltage
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V ; VI = VIH or VIL;I
O = –12mA VCC*0.5
VO
HIGH level out
p
ut voltage
VCC = 3.0V ; VI = VIH or VIL;I
O = –100µA VCC*0.2 VCC
V
OH
HIGH
le
v
el
o
u
tp
u
t
v
oltage
VCC = 3.0V ; VI = VIH or VIL; IO = –18mA VCC*0.6
VCC = 3.0V ; VI = VIH or VIL; IO = –24mA VCC*0.8
VCC = 2.7V ; VI = VIH or VIL;I
O = 12mA 0.40
VOL LOW level output voltage VCC = 3.0V ; VI = VIH or VIL;I
O = 100µA GND 0.20 V
VCC = 3.0V ; VI = VIH or VIL; IO = 24mA 0.55
I
In
p
ut leakage current2
VCC =36V
;
V = 5 5V or GND
"01
"5
I
I
Inp
u
t
leakage
c
u
rrent2
V
CC =
3
.
6V
;
V
I =
5
.
5V
or
GND
"0
.
1
"5
µ
IOZ 3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL;V
O = 5.5V or GND 0.1 "10 µA
Ioff Power of f leakage supply VCC = 0.0V; VI or VO = 5.5V 0.1 "10 µA
ICC Quiescent supply current VCC = 3.6V ; VI = VCC or GND; IO = 0 0.1 10 µA
∆ICC Additional quiescent supply current
per input pin VCC = 2.7V to 3.6V ; VI = VCC –0.6V; IO = 0 5 500 µA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
Philips Semiconductors Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
1998 Jul 29 6
AC CHARACTERISTICS
GND = 0V ; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT
MIN TYP1MAX MIN MAX TYP
tPHL
tPLH Propagation delay
CP to Qn 1, 4 1.5 4.8 7.0 1.5 8.0 21 ns
tPZH
tPZL 3-State output enable time
OE to Qn 2, 4 1.5 4.0 7.5 1.5 8.5 17 ns
tPHZ
tPLZ 3-State output disable time
OE to Qn 2, 4 1.5 3.5 6.0 1.5 6.5 11 ns
tWClock pulse width HIGH or LOW 1 3.4 1.7 – 3.4 – – ns
tSU Setup time
Dn to CP 3 2.0 0.3 – 2.0 – – ns
thHold time
Dn to CP 3 1.5 –0.2 – 1.5 – – ns
fmax Maximum clock pulse frequency 1 100 – 80 – – MHz
NOTE:
1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C.
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V ; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V ; VX = VOL + 0.1 VCC at VCC t2.7V
VY = VOH –0.3V at VCC w2.7V; VY = VOH – 0.1 VCC at VCC t2.7V
tw
tPLH
CP INPUT
Qn OUTPUT
VMVMVM
VMVM
VI
GND
VOH
VOL
SA00394
tPHL
1/fmax
Waveform 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width, output transition times and the maximum
clock pulse frequency.
VM
SW00107
VI
GND
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
VM
Dn
INPUT
VI
GND
VM
VOH
Qn
OUTPUT
VOL
CP
INPUT
tsu
th
tsu
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
W aveform 2. Data setup and hold times for the Dn input to the
CP input.
tPLZ tPZL
VI
nOE INPUT
GND
VCC
Qn OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
Qn OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND outputs
enabled outputs
enabled
outputs
disabled
tPHZ
VM
VM
VM
tPZH
VX
VY
SW00207
W aveform 3. 3-State enable and disable times.
TEST CIRCUIT
PULSE
GENERATOR
VI
RT
D.U.T. VO
CL50pF
S12 x VCC
Open
GND
500Ω
500Ω
VCC VI
t 2.7V VCC
2.7V – 3.6V 2.7V
Test S1
GND
tPLZ/tPZL 2 x VCC
tPHZ/tPZH
tPLH/tPHL Open
SY00003
VCC
W aveform 4. Load circuitry for switching times.
Philips Semiconductors Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
1998 Jul 29 7
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Philips Semiconductors Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
1998 Jul 29 8
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
Philips Semiconductors Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
1998 Jul 29 9
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
Philips Semiconductors Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
yyyy mmm dd 10
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 08-98
Document order number: 9397-750-04514
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
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.