SY10E107JC - MICROCHIP TECHNOLOGY

March, 2006 − Rev. 4 1Publication Order Number:

SA571/D

SA571

Compandor

The SA571 is a versatile low cost dual gain control circuit in which

either channel may be used as a dynamic range compressor or

expandor. Each channel has a full−wave rectifier to detect the average

value of the signal, a linerarized temperature−compensated variable

gain cell, and an operational amplifier.

The SA571 is well suited for use in cellular radio and radio

communications systems, modems, telephone, and satellite

broadcast/receive audio systems.

Features

•Complete Compressor and Expandor in one IChip

•Temperature Compensated

•Greater than 110 dB Dynamic Range

•Operates Down to 6.0 VDC

•System Levels Adjustable with External Components

•Distortion may be Trimmed Out

•Dynamic Noise Reduction Systems

•Voltage Controlled Amplifier

•Pb−Free Packages are Available*

Applications

•Cellular Radio

•High Level Limiter

•Low Level Expandor − Noise Gate

•Dynamic Filters

•CD Player

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

http://onsemi.com

RECT CAP 1

RECT IN 1

DG CELL IN 1

GND

RECT CAP 2

DG CELL IN 2

RECT IN 2

VCC

D, and N Packages*

INV. IN 1

RES. R3 1

OUTPUT 1

THD TRIM 1

INV. IN 2

RES. R3 2

OUTPUT 2

THD TRIM 2

TOP VIEW

SOL − Released in Large SO Package Only.

PIN CONNECTIONS

ee detailed ordering and shipping information in the package

imensions section on page 9 of this data sheet.

ORDERING INFORMATION

PDIP−16

N SUFFIX

CASE 648

16 1

SOIC−16 WB

D SUFFIX

CASE 751G

MARKING

DIAGRAMS

SA571D

AWLYYWWG

SA571N

AWLYYWWG

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

SA571

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VARIABLE

GAIN

THD TRIM

RECT CAP

1.8V

INVERTER IN

OUTPUT

−

RECTIFIER

Figure 1. Block Diagram

DG IN

RECT IN

VREF

R2 20kW

R1 10kW

R3 20kW

R4 30kW

MAXIMUM RATINGS

Rating Symbol Value Unit

Maximum Operating Voltage VCC 18 VDC

Operating Ambient Temperature Range TA−40 to +85 °C

Operating Junction Temperature TJ150 °C

Power Dissipation PD400 mW

Thermal Resistance, Junction−to−Ambient N Package

D Package

RqJA 75

105

°C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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ELECTRICAL CHARACTERISTICS (VCC = +15 V, TA = 25°C, unless otherwise noted)

Characteristic Symbol Test Conditions Min Typ Max Unit

Supply Voltage VCC − 6.0 − 18 V

Supply Current ICC No Signal − 4.2 4.8 mA

Output Current Capability IOUT −±20 − − mA

Output Slew Rate SR − − ±.5 − V/ms

Gain Cell Distortion (Note 2) Untrimmed

Trimmed − 0.5

0.1 2.0 %

Resistor Tolerance − − ±5±15 %

Internal Reference Voltage − 1.65 1.8 1.95 V

Output DC Shift (Note 3) Untrimmed − ±90 ±150 mV

Expandor Output Noise No Signal, 15 Hz−20 kHz

(Note 1) − 20 60 mV

Unity Gain Level (Note 5) 1.0 kHz −1.5 0 +1.5 dBm

Gain Change (Notes 2 and 4) − − ±0.1 − dB

Reference Drift (Note 4) − − +2.0, −25 +20, −50 mV

Resistor Drift (Note 4) −40°C to +85°C − +10, −12 − %

Tracking Error

(Measured Relative to Value at Unity Gain)

Equals [VO − VO (unity gain)] dB − V2dBm

Rectifier Input,

VCC = +6.0 V

V2 = +6.0 dBm, V1 = 0 dB

V2 = −30 dBm, V1 = 0 dB

−

+0.2

+0.2 −1.0, +1.5

Channel Separation − − 60 − dB

1. Input to V1 and V2 grounded.

2. Measured at 0 dBm, 1.0 kHz.

3. Expandor AC input change from no signal to 0 dBm.

4. Relative to value at TA = 25°C.

5. 0 dBm = 775 mVRMS.

SA571

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Circuit Description

The SA571 compandor building blocks, as shown in the

block diagram, are a full−wave rectifier , a variable gain cell,

an operational amplifier and a bias system. The arrangement

of these blocks in the IC result in a circuit which can perform

well with few external components, yet can be adapted to

many diverse applications.

The full−wave rectifier rectifies the input current which

flows from the rectifier input, to an internal summing node

which is biased at VREF. The rectified current is averaged on

an external filter capacitor tied to the CRECT terminal, and

the average value of the input current controls the gain of t he

variable gain cell. The gain will thus be proportional to the

average value of the input signal for capacitively−coupled

voltage inputs as shown in the following equation. Note that

for capacitively−coupled inputs there is no offset voltage

capable of producing a gain error. The only error will come

from the bias current of the rectifier (supplied internally)

which is less than 0.1 mA.

GT|VIN *VREF |avg

GT|V

IN |avg

The speed with which gain changes to follow changes in

input signal levels is determined by the rectifier filter

capacitor. A small capacitor will yield rapid response but

will not fully filter low frequency signals. Any ripple on th e

gain control signal will modulate the signal passing through

the variable gain cell. In an expander or compressor

application, this would lead to third harmonic distortion, so

there i s a trade−off to be made between fast attack and decay

times and distortion. For step changes in amplitude, the

change in gain with time is shown by this equation.

t+10kW CRECT

G(t) +(Ginitial *Gfinal)e

t)Gfinal

The variable gain cell is a current−in, current−out device

with the ratio IOUT/IIN controlled by the rectifier. IIN is the

current which flows from the DG input to an internal

summing node biased at VREF. The following equation

applies for capacitively−coupled inputs. The output current,

IOUT, is fed to the summing node of the op amp.

IIN +VIN *VREF

R2+VIN

A compensation scheme built into the DG cell

compensates for temperature and cancels out odd harmonic

distortion. The only distortion which remains is even

harmonics, and they exist only because of internal offset

voltages. The THD trim terminal provides a means for

nulling the internal offsets for low distortion operation.

The operational amplifier (which is internally

compensated) has the non−inverting input tied to VREF, and

the inverting input connected to the DG cell output as well

as brought out externally. A resistor, R 3, is brought out from

the summing node and allows compressor or expander gain

to be determined only by internal components.

The output stage is capable of ±20 mA output current.

This allows a +13 dBm (3.5 VRMS) output into a 300 W load

which, with a series resistor and proper transformer, can

result in +13 dBm with a 600 W output impedance.

A bandgap reference provides the reference voltage for all

summing nodes, a regulated supply voltage for the rectifier

and DG cell, and a bias current for the DG cell. The low

tempco of this type of reference provides very stable biasing

over a wide temperature range.

The typical performance characteristics illustration

shows the basic input−output transfer curve for basic

compressor or expander circuits.

+20

+10

−10

−20

−30

−40

−50

−60

−70

−80

−40 −30 −20 −10 0 +10

COMPRESSOR OUTPUT LEVEL

EXPANDOR INPUT LEVEL (dBm)

COMPRESSOR INPUT LEVEL OR EXPANDOR

Figure 2. Basic Input−Output Transfer Curve

OUTPUT LEVEL (dBm)

3, 14

2, 15

4 1, 16

200pF

Figure 3. Typical Test Circuit

VCC = 15V

VREF

10mF

0.1mF

2.2mF

20kW

10kW

2.2mF

5, 12

8.2kW

8, 9

30kW

20kW

6, 11

7, 10

−

SA571

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INTRODUCTION

Much interest has been expressed in high performance

electronic gain control circuits. For non−critical

applications, an integrated circuit operational

transconductance amplifier can be used, but when

high−performance is required, one has to resort to complex

discrete circuitry with many expensive, well−matched

components. This paper describes an inexpensive integrated

circuit, the SA571 Compandor, which offers a pair of high

performance gain control circuits featuring low distortion

(<0.1%), high signal−to−noise ratio (90 dB), and wide

dynamic range (110 dB).

Circuit Background

The SA571 Compandor was originally designed to satisfy

the requirements of the telephone system. When several

telephone channels are multiplexed onto a common line, the

resulting signal−to−noise ratio is poor and companding is

used to allow a wider dynamic range to be passed through

the channel. Figure 4 graphically shows what a compandor

can do for the signal−to−noise ratio of a restricted dynamic

range channel. The input level range of +20 to −80 dB is

shown undergoing a 2−to−1 compression where a 2.0 dB

input level change is compressed into a 1.0 dB output level

change by the compressor. The original 100 dB of dynamic

range is thus compressed to a 50 dB range for transmission

through a restricted dynamic range channel. A

complementary expansion on the receiving end restores the

original signal levels and reduces the channel noise by as

much as 45 dB.

The significant circuits in a compressor or expander are

the rectifier and the gain control element. The phone system

requires a simple full−wave averaging rectifier with good

accuracy, since the rectifier accuracy determines the (input)

output level tracking accuracy. The gain cell determines the

distortion and noise characteristics, and the phone system

specifications here are very loose. These specs could have

been met with a simple Operational Transconductance

Multiplier, or OTA, but the gain of an OTA is proportional

to temperature and this is very undesirable. Therefore, a

linearized transconductance multiplier was designed which

is insensitive to temperature and offers low noise and low

distortion performance. These features make the circuit

useful in audio and data systems as well as in

telecommunications systems.

Basic Hook−up and Operation

Figure 5 shows the block diagram of one half of the chip,

(there are two identical channels on the IC). The full−wave

averaging rectifier provides a gain control current, IG, for the

variable gain (DG) cell. The output of the DG cell is a current

which is fed to the summing node of the operational

amplifier. Resistors are provided to establish circuit gain and

set the output DC bias.

The circuit is intended for use in single power supply

systems, so the internal summing nodes must be biased at

some voltage above ground. An internal band gap voltage

reference provides a very stable, low noise 1.8 V reference

denoted V REF. The non−inverting input of the op amp is tied

to V REF, and the summing nodes of the rectifier and DG cell

(located at the right of R1 and R2) have the same potential.

The THD trim pin is also at the VREF potential.

INPUT

LEVEL

COMPRESSION

EXPANSION

OUTPUT

LEVEL

NOISE

+20

0dB

−40

−80

−20

0dB

−40

−80

Figure 4. Restricted Dynamic Range Channel

VCC PIN 13

GND PIN 4

OUTPUT

7,10

VREF

1.8V

30kW

1,16

CRECT

10kW

2,15

RECTIN

GIN

3,14 20kW

R220kW

R36,11 5,12

INVIN

THD TRIM8,9

Figure 5. Chip Block Diagram (1 of 2 Channels)

−

SA571

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Figure 6 shows how the circuit is hooked up to realize an

expandor. The input signal, VIN, is applied to the inputs of

both the rectifier and the DG cell. When the input signal

drops by 6 . 0 d B , t h e g a i n control current will drop by a factor

of 2, and so the gain will drop 6.0 dB. The output level at

VOUT will thus drop 12 dB, giving us the desired 2−to−1

expansion.

−

GAIN +ǒ2R

3VIN (avg)

R1R2IBǓ2

NOTE:

IB = 140mA

*EXTERNAL COMPONENTS

VIN VOUT

VREF

*CIN1

*CIN2

*CRECT

Figure 6. Basic Expander

Figure 7 shows the hook−up for a compressor. This is

essentially a n expandor placed in the feedback loop of the op

amp. The DG cell is setup to provide AC feedback only, so

a separate DC feedback loop is provided by the two RDC and

CDC. The values of RDC will determine the DC bias at the

output of the op amp. The output will bias to:

VOUT DC +ǒ1)RDC1 )RDC2

R4ǓVREF

VOUT DC +ǒ1)RDCTOT

30kWǓ1.8V

The output of the expander will bias up to:

VOUT DC +ǒ1)R3

R4ǓVREF

VOUT DC +ǒ1)20kW

30kWǓ1.8V +3.0V

The output will bias to 3.0 V when the internal resistors are

used. External resistors may be placed in series with R3,

(which will af fect the gain), or in parallel with R4 to raise the

DC bias to any desired value.

NOTE: GAIN +ǒR1R2IB

2R3VINavgǓ1

IB = 140mA

*EXTERNAL COMPONENTS

VIN

CIN

R3VOUT

CRECT *

RDC *RDC *

CDC *

VREF

Figure 7. Basic Compressor

−

Circuit Details − Rectifier

Figure 8 shows the concept behind the full−wave

averaging rectifier. The input current to the summing node

of the op amp, VIN/R1, is supplied by the output of the op

amp. If we can mirror the op amp output current into a

unipolar current, we will have an ideal rectifier. The output

current is averaged by R5, CR, which set the averaging time

constant, and then mirrored with a gain of 2 to become IG,

the gain control current.

CRIG

VIN

V+

I = VIN / R1

Figure 8. Rectifier Concept

10kW

−

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Figure 9 shows the rectifier circuit in more detail. The op

amp is a one−stage op amp, biased so that only one output

device is on at a time. The non−inverting input, (the base of

Q1), which is shown grounded, is actually tied to the internal

1.8 V, VREF. The inverting input is tied to the op amp output,

(the emitters of Q5 and Q6), and the input summing resistor

R1. The single diode between the bases of Q5 and Q6 assures

that only one device is on at a time. To detect the output

current of the op amp, we simply use the collector currents

of the output devices Q5 and Q6. Q6 will conduct when the

input swings positive and Q5 conducts when the input

swings negative. The collector currents will be in error by

the a of Q5 or Q6 on negative or positive signal swings,

respectively. ICs such as this have typical NPN b’s of 200

and PNP b’s of 40. The a’s of 0.995 and 0.975 will produce

errors of 0.5% on negative swings and 2.5% on positive

swings. The 1.5% average of these errors yields a mere 0.13

dB gain error.

V+

Q1Q2

Q6Q8Q9

I1I2

VIN

V−

IG+2VIN avg

NOTE:

Figure 9. Simplified Rectifier Schematic

10kW

At very low input signal levels the bias current of Q2,

(typically 50 nA), will become significant as it must be

supplied b y Q 5. Another low level error can be caused by DC

coupling into the rectifier. If a n o ffset voltage exists between

the VIN input pin and the base of Q2, an error current of

VOS/R1 will be generated. A mere 1.0 mV of offset will

cause an input current of 100 nA which will produce twice

the error of the input bias current. For highest accuracy, the

rectifier should be coupled capacitively. At high input levels

the b of the PNP Q6 will begin to suffer, and there will be an

increasing error until the circuit saturates. Saturation can be

avoided by limiting the current into the rectifier input to

250 mA. If necessary, an external resistor may be placed in

series with R1 to limit the current to this value. Figure 10

shows the rectifier accuracy vs. input level at a frequency of

1.0 kHz.

ERROR GAIN dB

−1 −40 −20 0

RECTIFIER INPUT dBm

Figure 10. Rectifier Accuracy

At very high frequencies, the response of the rectifier will

fall off. The roll−off will be more pronounced at lower input

levels due to the increasing amount of gain required to

switch between Q5 or Q6 conducting. The rectifier

frequency response for input levels of 0 dBm, −20 dBm, and

−40 dBm is shown in Figure 11. The response at all three

levels is flat to well above the audio range.

10k 1MEG

INPUT = 0dBm

−20dBm

−40dBm

FREQUENCY (Hz)

GAIN ERROR (dB)

Figure 11. Rectifier Frequency Response vs.

Input Level

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Variable Gain Cell

Figure 12 is a diagram of the variable gain cell. This is a

linearized two−quadrant transconductance multiplier. Q1,

Q2 and the op amp provide a predistorted drive signal for the

gain control pair, Q3 and Q4. The gain is controlled by IG and

a current mirror provides the output current.

Q1Q2Q3Q4

NOTE:

I2 (= 2I1)

280mAIG

IIN

VIN

20k

140mA

V+

V−

IOUT +IG

I1IIN +IGVIN

I2R2

Figure 12. Simplified DG Cell Schematic

−

The op amp maintains the base and collector of Q1 at

ground potential (VREF) by controlling the base of Q2. The

input current IIN (= VIN/R2) is thus forced to flow through

Q1 along with the current I1, so IC1 = I1 + IIN. Since I2 has

been set at twice the value of I1, the current through Q2 is:

I2 − (I1 + IIN) = I1 − IIN = IC2.

The op amp has thus forced a linear current swing between

Q1 and Q2 by providing the proper drive to the base of Q2.

This drive signal will be linear for small signals, but very

non−linear for lar ge signals, since it is compensating for the

non−linearity o f the dif ferential pair, Q1 and Q2, under large

signal conditions.

The key to the circuit is that this same predistorted drive

signal is applied to the gain control pair, Q3 and Q4. When

two differential pairs of transistors have the same signal

applied, their collector current ratios will be identical

regardless of the magnitude of the currents. This gives us:

IC1

IC2 +IC4

IC3 +I1)IIN

I1*IIN

plus the relationships IG = I C3 + I C4 and IOUT = I C4 − IC3 will

yield the multiplier transfer function,

IOUT +IG

I1IIN +VIN

This equation is linear and temperature−insensitive, but it

assumes ideal transistors.

If the transistors are not perfectly matched, a parabolic,

non−linearity is generated, which results in second

harmonic distortion. Figure 13 gives an indication of the

magnitude of the distortion caused by a given input level and

offset voltage. The distortion is linearly proportional to the

magnitude of the offset and the input level. Saturation of the

gain cell occurs at a +8 dBm level. At a nominal operating

level of 0 dBm, a 1.0 mV offset will yield 0.34% of second

harmonic distortion. Most circuits are somewhat better than

this, which means our overall o ffsets are typically about mV.

The distortion is not affected by the magnitude of the gain

control current, and it does not increase as the gain is

changed. This second harmonic distortion could be

eliminated by making perfect transistors, but since that

would be difficult, we have had to resort to other methods.

A trim pin has been provided to allow trimming of the

internal offsets to zero, which effectively eliminated second

harmonic distortion. Figure 14 shows the simple trim

network required.

.34 −6 0 +6

4mV

3mV

2mV

1mV

INPUT LEVEL (dBm)

% THD

Figure 13. DG Cell Distortion vs. Offset Voltage

3.6V

6.2kW

To THD Trim

≈200pF

Figure 14. THD Trim Network

20kW

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Figure 15 shows the noise performance of the DG cell.

The maximum output level before clipping occurs in the

gain cell is plotted along with the output noise in a 20 kHz

bandwidth. Note that the noise drops as the gain is reduced

for the first 20 dB of gain reduction. At high gains, the signal

to noise ratio is 90 dB, and the total dynamic range from

maximum signal to minimum noise is 110 dB.

VCA GAIN (0dB)

+20

OUTPUT (dBm)

−20

−40

−60

−80

−100

−40 −20 0

MAXIMUM

SIGNAL LEVEL

NOISE IN

20kHz BW

90dB

110dB

Figure 15. Dynamic Range

Control signal feedthrough is generated in the gain cell by

imperfect device matching and mismatches in the current

sources, I 1 and I2. When no input signal is present, changing

IG will cause a small output signal. The distortion trim is

effective in nulling out any control signal feedthrough, but

in general, the null for minimum feedthrough will be

different than the null in distortion. The control signal

feedthrough can be trimmed independently of distortion by

tying a current source to the DG input pin. This effectively

trims I1. Figure 16 shows such a trim network.

Figure 16. Control Signal Feedthrough

R−SELECT FOR

3.6V

470kW

TO PIN 3 OR 14

100kW

VCC

Operation Amplifier

The main op amp shown in the chip block diagram is

equivalent to a 741 with a 1.0 MHz bandwidth. Figure 17

shows the basic circuit. Split collectors are used in the input

pair to reduce gM, so that a small compensation capacitor of

just 10 pF may be used. The output stage, although capable

of output currents in excess of 20 mA, is biased for a low

quiescent current to conserve power. When driving heavy

loads, this leads to a small amount of crossover distortion.

Q1Q2

I1I2Q6

+IN

−IN OUT

Figure 17. Operational Amplifier

ORDERING INFORMATION

Device Description Temperature Range Shipping†

SA571D 16−Pin Plastic Small Outline (SO−16 WB) Package −40 to +85°C47 Units / Rail

SA571DG 16−Pin Plastic Small Outline (SO−16 WB) Package

(Pb−Free) −40 to +85°C47 Units / Rail

SA571DR2 16−Pin Plastic Small Outline (SO−16 WB) Package −40 to +85°C1000 / Tape & Reel

SA571DR2G 16−Pin Plastic Small Outline (SO−16 WB) Package

(Pb−Free) −40 to +85°C1000 / Tape & Reel

SA571N 16−Pin Plastic Dual In−Line Package (PDIP−16) −40 to +85°C25 Units / Rail

SA571NG 16−Pin Plastic Dual In−Line Package (PDIP−16)

(Pb−Free) −40 to +85°C25 Units / Rail

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS5

SOIC−16 WB

D SUFFIX

CASE 751G−03

ISSUE C

14X

B16X

SEATING

PLANE

0.25 B S

16 9

hX 45_

0.25

H8X

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN

EXCESS OF THE B DIMENSION AT MAXIMUM

MATERIAL CONDITION.

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D10.15 10.45

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

PDIP−16

N SUFFIX

CASE 648−08

ISSUE T NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

HGD

16 PL

SEATING

916

PLANE

−T−

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

SA571/D

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