General Description
The MAX9179 is a quad low-voltage differential
signaling (LVDS) line receiver designed for applications
requiring high data rates, low power dissipation, and
noise immunity. The receiver accepts four LVDS input
signals and translates them to 3.3V LVCMOS output lev-
els at speeds up to 400Mbps. The receiver features
built-in hysteresis, which improves noise immunity and
prevents multiple switching on slow transitioning inputs.
The device supports a wide 0.038V to 2.362V common-
mode input voltage range, allowing for ground potential
differences and common-mode noise between the driver
and the receiver. A fail-safe circuit sets the output high
when the input is open, undriven and shorted, or undriven
and terminated. Common enable inputs control the high-
impedance outputs.
The MAX9179 has a flow-through pinout for easy PC
board layout, and is pin compatible with the MAX9121
and the DS90LV048A with the additional features of
high ESD tolerance and built-in hysteresis.
The MAX9179 operates from a single 3.3V supply, and is
specified for operation from -40°C to +85°C. The device
is offered in 16-pin TSSOP and thin QFN packages.
Applications
Laser Printers
Digital Copiers
Cell-Phone Base Stations
Telecom Switching Equipment
LCD Displays
Network Switches/Routers
Backplane Interconnect
Clock Distribution
Features
♦Guaranteed 400Mbps Data Rate
♦50mV (typ) Hysteresis
♦Overshoot/Undershoot Protection (-1.0V or VCC +
1.0V) on Enables
♦IEC61000-4-2 Level 4 ESD Tolerance
♦AC Specifications Guaranteed with |VID|= 100mV
♦Single 3.3V Supply
♦Fail-Safe Circuit
♦Flow-Through Pinout
Simplifies PC Board Layout
Reduces Crosstalk
♦Low-Power CMOS Design
♦Conforms to ANSI TIA/EIA-644 LVDS Standard
♦High-Impedance Inputs when Powered Off
♦Pin Compatible with the MAX9121 and the
DS90LV048A
♦Small Thin QFN Package Available
MAX9179
Quad LVDS Receiver with Hysteresis
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2752; Rev 0; 2/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX9179EUE -40°C to +85°C 16 TSSOP
MAX9179ETE* -40°C to +85°C 16 Thin QFN-EP**
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1- EN
OUT1
OUT2
VCC
GND
OUT3
OUT4
TOP VIEW
MAX9179
TSSOP
THIN QFN
(LEADS UNDER PACKAGE)
EN
IN1+
IN2+
IN3+
IN2-
IN3-
IN4+
IN4-
IN2+
IN2-
IN3-
IN3+
OUT4IN4-IN4+
OUT2
VCC
GND
OUT3
EN
OUT1IN1-IN1+ EN
MAX9179
EXPOSED PAD
1
2
3
4
5678
16 15 14 13
12
11
10
9
Pin Configurations
Functional Diagram appears at end of data sheet.
*Future product—contact factory for availability.
**EP = Exposed paddle.
MAX9179
Quad LVDS Receiver with Hysteresis
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, differential input voltage |VID| = 0.075V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|,
TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND...........................................................-0.3V to +4.0V
IN_+, IN_- to GND .................................................-0.3V to +4.0V
EN, EN to GND...........................................-1.4V to (VCC + 1.4V)
OUT_ to GND .............................................-0.3V to (VCC + 0.3V)
Continuous Power Dissipation (TA= +70°C)
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
16-Pin Thin QFN (derate 16.9mW/°C
above +70°C).............................................................1349mW
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (RD= 1.5kΩ, CS= 100pF)
(IN_+, IN_-) ................................................................±16kV
IEC61000-4-2 (RD= 330Ω, CS= 150pF) (IN_+, IN_-)
Contact Discharge .......................................................±8kV
Air-Gap Discharge .....................................................±15kV
Soldering Temperature (soldering, 10s) ..........................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INPUTS (IN_+, IN_-)
Differential Input High Threshold VTH Figure 1 25 75 mV
Differential Input Low Threshold VTL Figure 1 -75 -25 mV
Hysteresis VTH - VTL Figure 1 50 mV
Input Current IIN+
,
IIN- -20 +20 µA
Power-Off Input Current IOFF+,
IOFF- VCC = 0V -20 +20 µA
Fail-Safe Input Resistor 1 RIN1 VCC = 3.6V or 0V, Figure 2 40 65 kΩ
Fail-Safe Input Resistor 2 RIN2 VCC = 3.6V or 0V, Figure 2 280 455 kΩ
OUTPUTS (OUT_)
Open, undriven short, or
undriven parallel
termination
Output High Voltage VOH IOH = -4.0mA
VID = +50mV
VCC -
0.2
VCC -
0.1 V
Output Low Voltage VOL IOL = 4.0mA, VID = -50mV 0.1 0.25 V
Output Short-Circuit Current IOS Enabled, VID = +50mV, VOUT = 0 (Note 3) -40 -70 -120 mA
Output High-Impedance Current IOZ Disabled, VOUT = 0 or VCC -1.0 +1.0 µA
ENABLE INPUTS (EN, EN)
Input High Voltage VIH 2.0 VCC +
1.0 V
Input Low Voltage VIL -1.0 +0.8 V
-1.0V ≤ EN, EN ≤ 0V -1800 +10
0V ≤ EN, EN ≤ VCC -20 +20Input Current IIN
VCC ≤ EN, EN ≤ VCC + 1.0V -10 +1800
µA
POWER SUPPLY
Supply Current ICC Enabled, inputs open 10.4 15
Disabled Supply Current ICCZ Disabled, inputs open 0.6 1.0 mA
MAX9179
Quad LVDS Receiver with Hysteresis
_______________________________________________________________________________________ 3
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Parts are production
tested at TA= +25°C.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, and VID.
Note 3: Short one output at a time.
Note 4: AC parameters are guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 5: CLincludes scope probe and test jig capacitance.
Note 6: Pulse generator differential output for all tests (unless otherwise noted): tR= tF< 1ns (0% to 100%), frequency = 100MHz,
50% duty cycle.
Note 7: tSKD1 is the magnitude of the difference of the differential propagation delays in a channel. tSKD1 = | tPHLD - tPLHD |.
Note 8: tSKD2 is the magnitude of the difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of the other channel
on the same part.
Note 9: tSKD3 is the magnitude of the difference of any differential propagation delays between parts at the same VCC and within
5°C of each other.
Note 10: tSKD4 is the magnitude of the difference of any differential propagation delays between parts operating over the rated
supply and temperature ranges.
Note 11: Pulse generator output for tPHZ, tPLZ, tPZH, and tPZL tests: tR= tF= 1.5ns (0.2VCC to 0.8VCC), 50% duty cycle, VOH =
VCC + 1.0V settling to VCC, VOL = -1.0V settling to 0, frequency = 1MHz.
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, CL= 15pF, differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|,
TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA= +25°C.) (Notes 4, 5, 6)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Differential Propagation Delay
High to Low tPHLD Figures 3, 4 2.0 2.6 4.6 ns
Differential Propagation Delay
Low to High tPLHD Figures 3, 4 2.0 2.52 4.6 ns
|VID| = 0.1V to 0.15V 700
|VID| = 0.15V to 0.2V 400
Differential Pulse Skew
| tPHLD - tPLHD | (Note 7) tSKD1
|VID| = 0.2V to 1.2V 80 300
ps
|VID| = 0.1V to 0.15V 900
|VID| = 0.15V to 0.2V 600
Differential Channel-to-Channel
Skew, Same Part
(Note 8)
tSKD2
|VID| = 0.2V to 1.2V 120 400
ps
Differential Part-to-Part Skew
(Note 9) tSKD3 2.0 ns
Differential Part-to-Part Skew
(Note 10) tSKD4 2.6 ns
Rise Time tTLH 0.77 1.4 ns
Fall Time tTHL 0.74 1.4 ns
Disable Time High to Z tPHZ RL = 2kΩ, Figures 5, 6 (Note 11) 10.6 14 ns
Disable Time Low to Z tPLZ RL = 2kΩ, Figures 5, 6 (Note 11) 11 14 ns
Enable Time Z to High tPZH RL = 2kΩ, Figures 5, 6 (Note 11) 4.8 14 ns
Enable Time Z to Low tPZL RL = 2kΩ, Figures 5, 6 (Note 11) 4.8 14 ns
Maximum Operating Frequency fMAX
All channels switching, CL = 15pF, VOL
(max) = 0.25V, VOH (min) = VCC - 0.2V,
44% < duty cycle < 56%
200 250 MHz
MAX9179
Quad LVDS Receiver with Hysteresis
4 _______________________________________________________________________________________
Test Circuits/Timing Diagrams
VOUT
VOH
VTL
-VID +VID
VOL
VTH
HYSTERESIS
VID = 0
Figure 1. Input Thresholds and Hysteresis
VCC
VCC - 0.3V
RIN2
RIN1
RIN1
IN_+
OUT_
IN_-
Figure 2. Fail-Safe Input Circuit
OUT_
CL
50Ω50Ω
IN_-
IN_+
PULSE
GENERATOR
Figure 3. Propagation Delay and Transition Time Test Circuit
0.9VCC
0.5VCC
0.1VCC
0.9VCC
0.5VCC
0.1VCC
IN_-
IN_+
(0V DIFFERENTIAL) VID
tPHLD
tPLHD
tTLH tTHL
VCM = ((VIN_+) + (VIN_-))/2
OUT_
Figure 4. Propagation Delay and Transition Time Waveforms
50Ω
PULSE
GENERATOR
CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS.
S1 = 0 FOR tPZH AND tPHZ MEASUREMENTS.
DEVICE
UNDER
TEST
EN
EN
IN_+
VCC S1
RL
CL
OUT_
IN_-
Figure 5. High-Impedance Delay Test Circuit
VCC + 1.0V
VCC
0
-1.0V
VCC + 1.0V
VCC
0
-1.0V
VCC
VOL
VOH
0
EN WHEN EN = LOW OR OPEN
EN WHEN EN = HIGH
OUT_ WHEN VID = -75mV
OUT_ WHEN VID = +75mV
1.5V 1.5V
1.5V 1.5V
tPZL
tPLZ
tPHZ tPZH
0.5V
0.5V
50%
50%
Figure 6. High-Impedance Delay Waveforms
Typical Operating Characteristics
(VCC = 3.3V, VCM = 1.2V, |VID| = 0.15V, CL= 15pF, f = 100MHz, TA= +25°C, unless otherwise noted.)
MAX9179
Quad LVDS Receiver with Hysteresis
_______________________________________________________________________________________ 5
SUPPLY CURRENT vs. FREQUENCY
MAX9179 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
30025020015010050
30
50
70
90
110
10
0 350
ALL CHANNELS DRIVEN
SUPPLY CURRENT
vs. TEMPERATURE
MAX9179 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
6
8
10
12
14
16
4
-40 85
INPUTS OPEN
DC DIFFERENTIAL THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX9179 toc03
SUPPLY VOLTAGE (V)
DC DIFFERENTIAL THRESHOLD VOLTAGE (mV)
3.53.43.1 3.2 3.3
-30
-20
-10
0
10
20
30
40
-40
3.0 3.6
VTH
VTL
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
MAX9179 toc04
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
3.53.43.33.23.1
-40
-60
-80
-100
-20
3.0 3.6
DC INPUT
(VID = +150mV)
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
MAX9179 toc05
SUPPLY VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
3.53.43.33.23.1
2.8
3.0
3.2
3.4
3.6
2.6
3.0 3.6
DC INPUT
(VID = +150mV)
IOH = -4mA
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9179 toc07
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
3.53.43.33.23.1
2.2
2.4
2.6
2.8
3.0
3.2
2.0
3.0 3.6
tPHLD
tPLHD
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
MAX9179 toc06
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE (mV)
3.53.43.33.23.1
100
110
120
130
140
90
3.0 3.6
DC INPUT
(VID = -150mV)
IOL = 4mA
Typical Operating Characteristics (continued)
(VCC = 3.3V, VCM = 1.2V, |VID| = 0.15V, CL= 15pF, f = 100MHz, TA= +25°C, unless otherwise noted.)
MAX9179
Quad LVDS Receiver with Hysteresis
6 _______________________________________________________________________________________
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9179 toc08
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)
603510-15
2.2
2.4
2.6
2.8
3.0
3.2
3.4
2.0
-40 85
tPHLD
tPLHD
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
MAX9179 toc09
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
1.8751.4250.525 0.975
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
1.8
0.075 2.325
tPHLD
tPLHD
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
MAX9179 toc10
DIFFERENTIAL INPUT VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
0.930.650.38
2.0
2.2
2.4
2.6
2.8
3.0
1.8
0.10 1.20
tPHLD
tPLHD
DIFFERENTIAL PULSE SKEW
vs. SUPPLY VOLTAGE
MAX9179 toc11
SUPPLY VOLTAGE (V)
DIFFERENTIAL PULSE SKEW (ps)
3.53.43.33.23.1
-50
0
50
150
100
200
-100
3.0 3.6
TRANSITION TIME
vs. SUPPLY VOLTAGE
MAX9179 toc12
SUPPLY VOLTAGE (V)
TRANSITION TIME (ps)
3.53.43.33.23.1
600
700
800
900
1000
1100
500
3.0 3.6
tTLH
tTHL
TRANSITION TIME vs. TEMPERATURE
MAX9179 toc13
TEMPERATURE (°C)
TRANSITION TIME (ps)
603510-15
500
600
700
800
1100
1000
900
1200
400
-40 85
tTLH
tTHL
DIFFERENTIAL THRESHOLD VOLTAGE
vs. COMMON-MODE VOLTAGE
MAX9179 toc14
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL THRESHOLD VOLTAGE (mV)
1.8751.4250.9750.525
-30
-20
-10
0
10
20
30
40
-40
0.075 2.325
VTH
VTL
MAX9179
Quad LVDS Receiver with Hysteresis
__________________________________________________________________________
Pin Description
PIN
TSSOP QFN NAME FUNCTION
1 15 IN1- Inverting LVDS Input 1
2 16 IN1+ Noninverting LVDS Input 1
3 1 IN2+ Noninverting LVDS Input 2
4 2 IN2- Inverting LVDS Input 2
5 3 IN3- Inverting LVDS Input 3
6 4 IN3+ Noninverting LVDS Input 3
7 5 IN4+ Noninverting LVDS Input 4
8 6 IN4- Inverting LVDS Input 4
97EN Enable Complementary Input. The outputs are active when EN = high and EN = low or open. For
all other combinations of EN and EN, the outputs are disabled and in high impedance.
10 8 OUT4 LVCMOS/LVTTL Output 4
11 9 OUT3 LVCMOS/LVTTL Output 3
12 10 GND Ground
13 11 VCC Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
14 12 OUT2 LVCMOS/LVTTL Output 2
15 13 OUT1 LVCMOS/LVTTL Output 1
16 14 EN Enable Input. The outputs are active when EN = high and EN = low or open. For all other
combinations of EN and EN, the outputs are disabled and in high impedance.
—EP Exposed
Pad Exposed Pad. Connect to ground.
MAX9179
Quad LVDS Receiver with Hysteresis
8 _______________________________________________________________________________________
Detailed Description
The LVDS is a signaling method intended for point-to-
point communication over a controlled-impedance
medium as defined by the ANSI TIA/EIA-644 and IEEE
1596.3 standards.
The MAX9179 is a quad LVDS line receiver with built-in
hysteresis, intended for high-speed, point-to-point, low-
power applications. The receiver accepts four LVDS
input signals and translates them to 3.3V LVCMOS out-
put levels at speeds up to 400Mbps over controlled-
impedance media of 100Ω. The hysteresis improves
noise immunity and prevents multiple switching due to
noise on slow input transitions at the end of a long cable.
The receiver is capable of detecting differential signals
as low as 75mV and as high as 1.2V within a 0 to 2.4V
input voltage range. The 250mV to 450mV differential
output of an LVDS driver is nominally centered on a 1.2V
offset. This offset, coupled with the receiver’s 0 to 2.4V
input voltage range, allows an approximate ±1V shift in
the signal (as seen by the receiver). This allows for a dif-
ference in ground references of the transmitter and the
receiver, the common-mode effects of coupled noise, or
both. The LVDS standards specify an input voltage
range of 0 to 2.4V referenced to receiver ground.
Hysteresis
The MAX9179 incorporates hysteresis of 50mV (typ),
which rejects noise and prevents false switching during
low-slew-rate transitions at the end of a long cable. The
receiver typically switches at 25mV above or below VID
= 0V (Figure 1). The hysteresis is designed to be sym-
metrical around VID = 0V for low pulse distortion (see
the Typical Operating Characteristics).
Input Fail-Safe
The fail-safe feature of the MAX9179 sets the output
high when the differential input is:
•Open
•Undriven and shorted
•Undriven and terminated
Without a fail-safe circuit, when the input is undriven,
noise at the input may switch the output and it may
appear to the system that data is being sent. Open or
undriven terminated input conditions can occur when a
cable is disconnected or cut, or when a driver output is
in high impedance. A shorted input can occur because
of a cable failure.
When the input is driven with a differential signal of |VID|
= 75mV to 1.2V within a voltage range of 0 to 2.4V, the
fail-safe circuit is not activated. If the input is open,
undriven and shorted, or undriven and terminated, an
internal resistor in the fail-safe circuit pulls both inputs
above VCC - 0.3V, activating the fail-safe circuit and
forcing the output high (Figure 2).
Overshoot and Undershoot
Voltage Protection
The MAX9179 is designed to protect the enable inputs
(EN and EN) against latchup due to transient overshoot
and undershoot voltage. If the enable input voltage
goes above VCC or below GND by up to 1V, an internal
circuit clamps and limits input current to 1.8mA.
Applications Information
Power-Supply Bypassing
Bypass the VCC pin with high-frequency surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to VCC.
Differential Traces
Input trace characteristics affect the performance of the
MAX9179. Use controlled-impedance differential traces
(100Ωis typical). To reduce radiated noise and ensure
that noise couples as common mode, route the differ-
ential input signals within a pair close together. Reduce
skew by matching the electrical length of the signal
paths making up the differential pair. Excessive skew
can result in a degradation of magnetic field cancella-
tion. Maintain a constant distance between the differen-
tial traces to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
ENABLES INPUTS OUTPUT
EN EN (IN_+) - (IN_-) OUT_
≥ +75mV H
≤ -75mV L
H L or open
Open, undriven short,
or undriven terminated H
All other combinations
of enable inputs XZ
H= High logic level
L= Low logic level
X= Don't care
Z= High impedance
Table 1. Functional Table
MAX9179
Quad LVDS Receiver with Hysteresis
_______________________________________________________________________________________ 9
Cables and Connectors
Interconnect for LVDS typically has a controlled differ-
ential impedance of 100Ω. Use cables and connectors
that have matched differential impedance to minimize
impedance discontinuities. Avoid the use of unbal-
anced cables such as ribbon or simple coaxial cable.
Balanced cables such as twisted pair offer superior
signal quality and tend to generate less EMI due to
magnetic field canceling effects. Balanced cables pick
up noise as common mode, which is rejected by the
LVDS receiver.
Termination
The MAX9179 requires external termination resistors.
The input termination resistor used on each active
channel should match the differential impedance of the
transmission line. Place the termination resistor as
close to the MAX9179 receiver input as possible. Use
1% surface-mount resistors.
Board Layout
Keep the LVDS input and LVCMOS output signals sepa-
rated from each other to reduce crosstalk; 180 degrees of
separation between LVDS inputs and LVCMOS outputs is
recommended. Because there are leads on all sides, this
separation requires special attention when laying out
traces for the QFN package.
A four-layer printed circuit board with separate layers
for power, ground, LVDS inputs, and single-ended
logic signals is recommended. Separate the LVDS sig-
nals from the single-ended signals with power and
ground planes for best results.
IEC 61000-4-2 Level 4 ESD Protection
The IEC 61000-4-2 standard (Figure 7) specifies ESD
tolerance for electronic systems. The IEC61000-4-2
model specifies a 150pF capacitor that is discharged
into the device through a 330Ωresistor. The MAX9179
LVDS inputs are rated for IEC61000-4-2 level 4 (±8kV
Contact Discharge and ±15kV Air-Gap Discharge). The
Human Body Model (HBM) (Figure 8) specifies a 100pF
capacitor that is discharged into the device through a
1.5kΩresistor. The IEC 61000-4-2 discharges higher
peak current and more energy than the HBM due to the
lower series resistance and larger capacitor.
Chip Information
TRANSISTOR COUNT: 1173
PROCESS: CMOS
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1MΩ
RD
1.5kΩ
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 8. Human Body Test Model
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
IN4+
IN4-
EN
EN
OUT1
OUT2
OUT3
OUT4
Functional Diagram
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50Ω TO 100Ω
RD
330Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 7. IEC61000-4-2 Test Model
MAX9179
Quad LVDS Receiver with Hysteresis
10 ______________________________________________________________________________________
TSSOP4.40mm.EPS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9179
Quad LVDS Receiver with Hysteresis
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
24L QFN THIN.EPS
21-0139 A
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
A21-0139
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
