10/12/11
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HEXFET® Power MOSFET
VDSS = 55V
RDS(on) = 6.5mΩ
ID = 75A
This HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating. These features
combine to make this design an extremely efficient
and reliable device for use in a wide variety of
applications.
S
D
G
Description
l
Advanced Process Technology
l
Ultra Low On-Resistance
l
175°C Operating Temperature
l
Fast Switching
l
Repetitive Avalanche Allowed up to Tjmax
Features
IRF3205Z
IRF3205ZS
IRF3205ZL
D2Pak
IRF3205ZS
TO-220AB
IRF3205Z
TO-262
IRF3205ZL
Absolute Maximum Ratings
Parameter Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V
A
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
(Package Limited)
I
DM
Pulsed Drain Current
P
D
@T
C
= 25°C
Power Dissipation W
Linear Derating Factor W/°C
V
GS Gate-to-Source Voltage V
E
AS (Thermally limited)
Single Pulse Avalanche Energy
mJ
E
AS
(Tested )
Single Pulse Avalanche Energy Tested Value
I
AR
Avalanche Current
c
A
E
AR
Repetitive Avalanche Energy
mJ
T
J Operating Junction and
T
STG Storage Temperature Range °C
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
i
Thermal Resistance
Parameter Typ. Max. Units
R
θJC Junction-to-Case ––– 0.90 °C/W
R
θCS Case-to-Sink, Flat Greased Surface
i
0.50 –––
R
θJA Junction-to-Ambient
i
––– 62
RθJA Junction-to-Ambient (PCB Mount)
j
––– 40
250
180
See Fig.12a, 12b, 15, 16
170
1.1
± 20
Max.
110
78
440
75
-55 to + 175
300 (1.6mm from case )
10 lbf
y
in (1.1N
y
m)
PD - 94653C
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Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
V
(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V
Δ
V
(BR)DSS
/
Δ
T
J Breakdown Voltage Temp. Coefficient ––– 0.051 ––– V/°C
R
DS(on) Static Drain-to-Source On-Resistance ––– 4.9 6.5
m
Ω
V
GS(th) Gate Threshold Voltage 2.0 ––– 4.0 V
gfs Forward Transconductance 71 ––– ––– S
I
DSS Drain-to-Source Leakage Current ––– ––– 20 μA
––– ––– 250
I
GSS Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to-Source Reverse Leakage ––– ––– -200
Q
gTotal Gate Charge ––– 76 110
Q
gs Gate-to-Source Charge ––– 21 ––– nC
Q
gd Gate-to-Drain ("Miller") Charge ––– 30 –––
t
d(on) Turn-On Delay Time ––– 18 –––
t
rRise Time –––95–––
t
d(off) Turn-Off Delay Time ––– 45 ––– ns
t
fFall Time –––67–––
L
DInternal Drain Inductance ––– 4.5 ––– Between lead,
nH 6mm (0.25in.)
L
SInternal Source Inductance ––– 7.5 ––– from package
and center of die contact
C
iss Input Capacitance ––– 3450 –––
C
oss Output Capacitance ––– 550 –––
C
rss Reverse Transfer Capacitance ––– 310 ––– pF
C
oss Output Capacitance ––– 1940 –––
C
oss Output Capacitance ––– 430 –––
C
oss
eff.
Effective Output Capacitance ––– 640 –––
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units
I
SContinuous Source Current ––– ––– 75
(Body Diode) A
I
SM Pulsed Source Current ––– ––– 440
(Body Diode)
c
V
SD Diode Forward Voltage ––– ––– 1.3 V
t
rr Reverse Recovery Time ––– 28 42 ns
Qrr Reverse Recovery Charge ––– 25 38 nC
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 44V
f
VGS = 10V
e
VDD = 28V
ID = 66A
RG = 6.8 Ω
TJ = 25°C, IS = 66A, VGS = 0V
e
TJ = 25°C, IF = 66A, VDD = 25V
di/dt = 100A/μs
e
Conditions
VGS = 0V, ID = 250μA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 66A
e
VDS = VGS, ID = 250μA
VDS = 55V, VGS = 0V
VDS = 55V, VGS = 0V, TJ = 125°C
MOSFET symbol
showing the
integral reverse
p-n junction diode.
VDS = 25V, ID = 66A
ID = 66A
VDS = 44V
Conditions
VGS = 10V
e
VGS = 0V
VDS = 25V
ƒ = 1.0MHz
VGS = 20V
VGS = -20V
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance
Vs. Drain Current
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
4.5V 20μs PULSE WIDTH
Tj = 25°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
4.5V 20μs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0
VGS, Gate-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (
A)
TJ = 25°C
TJ = 175°C
VDS = 25V
20μs PULSE WIDTH
0 20406080100
ID, Drain-to-Source Current (A)
0
20
40
60
80
100
120
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 175°C
VDS = 10V
20μs PULSE WIDTH
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0.2 0.6 1.0 1.4 1.8 2.2
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
110 100
VDS, Drain-to-Source Voltage (V)
0
1000
2000
3000
4000
5000
6000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
1 10 100 1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100μsec
0 20 40 60 80 100 120
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 44V
VDS= 28V
VDS= 11V
ID= 66A
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Normalized On-Resistance
Vs. Temperature
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
20
40
60
80
100
120
ID , Drain Current (A)
LIMITED BY PACKAGE
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 66A
VGS = 10V
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Q
G
Q
GS
Q
GD
V
G
Charge
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage Vs. Temperature
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150 175
Starting TJ, Junction Temperature (°C)
0
50
100
150
200
250
300
350
EAS, Single Pulse Avalanche Energy (mJ)
ID
TOP 27A
47A
BOTTOM 66A
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
1.0
2.0
3.0
4.0
VGS(th) Gate threshold Voltage (V)
ID = 250μA
1K
VCC
DUT
0
L
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ΔTj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
40
80
120
160
200
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 66A
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
VDS
90%
10%
VGS
t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
- B -
1.32 (.052)
1.22 (.048)
3X 0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
4.69 (.185)
4.20 (.165)
3X 0.93 (.037)
0.69 (.027)
4.06 (.160)
3.55 (.140)
1.15 (.045)
MIN
6.47 (.255)
6.10 (.240)
3.78 (.149)
3.54 (.139)
- A -
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
15.24 (.600)
14.84 (.584)
14.09 (.555)
13.47 (.530)
3X 1.40 (.055)
1.15 (.045)
2.54 (.100)
2X
0.36 (.014) M B A M
4
1 2 3
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE:
IN T HE AS S E MB LY L INE "C"
T HIS IS AN IR F1010
LOT CODE 1789
AS SE MB LE D ON WW 19, 1997 PART NUMBER
AS S E MB L Y
LOT CODE
DAT E CODE
YEAR 7 = 1997
LINE C
WE E K 19
LOGO
RECTIFIER
INT ER NAT IONAL
E XAMPL E: THIS IS AN IRF1010
LOT CODE 1789
AS S E MBL ED ON WW 19, 1997
IN THE AS SEMBLY LINE "C"
INT ER NAT IONAL
RECT IF IE R
LOGO
LOT CODE
PART NUMBER
DAT E CODE
For GB Production
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF3205ZS/L
10 www.irf.com
D2Pak Part Marking Information
F 530S
T HIS IS AN IRF 530S WIT H
LOT CODE 8024
AS S EMB LED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
AS S E MB L Y
LOT CODE
INTERNATIONAL
RE CT IF IE R
LOGO
PART NUMB ER
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
DAT E CODE
IN THE ASSEMBLY LINE "L"
AS S E MBL E D ON WW 02, 2000
T HIS IS AN IRF 530S WIT H
LOT CODE 8024 INTERNATIONAL
LOGO
RECT IFIE R
LOT CODE
PART NUMBER
F530S
For GB Production
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF3205ZS/L
www.irf.com 11
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXA
MPLE:THIS IS A
N IRL3103L
LOT C
O
DE 1789
A
SSEMBLY
PA
RT NUMBER
DA
TE C
ODE
W
EEK 19
LINE C
LO
T C
O
DE
YEA
R 7 = 1997
A
SSEMBLED O
N W
W 19, 1997
IN THE A
SSEMBLY LINE "C
"LO
GO
REC
TIFIER
INTERNA
TIONA
L
IGBT
1- GATE
2- COLLEC-
TOR
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF3205ZS/L
12 www.irf.com
IR WORLD HEADQUARTERS: 101N.Sepulveda Blvd, El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/2011
TO-220AB package is not recommended for Surface Mount Application.
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.08mH
RG = 25Ω, IAS = 66A, VGS =10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the
same charging time as Coss while VDS is rising
from 0 to 80% VDSS .
Notes:
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is only applied to TO-220AB pakcage.
This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
D2Pak Tape & Reel Information
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24. 30 (.95 7)
23. 90 (.94 1)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.