2003 Microchip Technology Inc. DS21202D-page 1
24C02C
Features
• Single supply with operation from 4.5 to 5.5V
• Low-power CMOS technology
- 1 mA active current typical
-10 µA standby current typical at 5.5V
• Organiz ed as a s ingle bl ock of 256 bytes (256 x 8)
• Hardware write protection for upper half of array
• 2-wire serial interface bus, I2C compatible
• 100 kHz and 400 kHz compatibility
• Page write buffer for up to 16 bytes
• Self-timed write cycle (including auto-erase)
• Fast 1 mS write cycle time for Byte or Page mode
• Address lines allow up to eight devices on bus
• 1,000,000 erase/write cycles
• ESD protection > 4,000V
• Data retentio n > 200 years
• 8-pin PDIP, SOIC or TSSOP packages
• Available for extended temperature ranges
Description
The Microchip Technology Inc. 24C02C is a 2K bit
Serial El ectricall y Erasabl e PROM with a volt age rang e
of 4.5V to 5.5V. The device is organized as a single
block of 256 x 8-bit memory with a 2-wire serial
interface. Low current design permits operation with
typica l st andb y and ac tive cu rrent s of only 10 µA and 1
mA respe ctively. The dev ice has a page wri te capabi lity
for up to 16 b ytes of dat a and has f ast w rite c ycle time s
of only 1 mS for both byte and page writes. Functional
address lines allow the connection of up to eight
24C02C devices on the same bus for up to 16K bits of
contiguous EEPROM memory. The device is available
in the standard 8-pin PDIP, 8-pin SOIC (150 mil) and
TSSOP packages.
Package Types
Block Diagram
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +85°C
- Automotive (E) : -40°C to +125°C
PDIP/SOIC
TSSOP
A0
A1
A2
Vss
Vcc
WP
SCL
SDA
24C02C
24C02C
1
2
3
4
8
7
6
5
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
I/O
Control
Logic
Memory
Control
Logic XDEC
HV Generator
EEPROM
Array
Write-Protect
Circuitry
YDEC
Vcc
Vss
Sense Amp.
R/W Control
SDA SCL
A0 A1 A2 WP
2K 5.0V I2C™ Serial EEPROM
I2C is a trademark of Philips Corporation.
24C02C
DS21202D-page 2 2003 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
ESD protection on all pins...................................................................................................................................... ≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This i s a stres s ratin g only and functio nal ope ration of the device at thos e or any other co nditio ns abov e those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
All parameters apply across the
specified operating ranges unless
otherwise noted.
VCC = +4.5V to +5.5V
Commercial (C): TA = 0°C to +70°C
Industrial (I): TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pins:
High-level input voltage VIH 0.7 VCC —V
Low-level input voltage VIL — 0.3 VCC V
Hysteresis of Schmitt Trigger inputs VHYS 0 .05 V CC —V(Note)
Low-level output vo lt ag e VOL —0.40VIOL = 3.0 mA, Vcc = 4.5V
Input leakage current ILI —±1µAVIN = 0.1V to 5.5V, WP = Vss
Output lea kage curre nt ILO —±1µAVOUT = 0.1V to 5.5V
Pin capacitance (all inputs/outputs) CIN, COUT —10pFVCC = 5.0V (Note)
TA = 25°C, f = 1 MHz
Operati ng current ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz
ICC Write — 3 mA VCC = 5.5V
Standby current ICCS —50µAVCC = 5.5V, SDA = SCL = VCC
WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
2003 Microchip Technology Inc. DS21202D-page 3
24C02C
TABLE 1-2: AC CHARACTERISTICS
FIGURE 1-1: BUS TIMING DATA
All parameters apply across the
specified operating ranges unless
otherwise noted.
VCC = +4.5V to +5.5V
Commercial (C): TA = 0°C to +70°C
Industri al (I): TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
Parameter Symbol TA > +85°C -40°C ≤ TA ≤ +85°C Units Remarks
Min. Max. Min. Max.
Clock frequency FCLK —100 — 400kHz
Clock high time THIGH 4000 — 600 — ns
Clock low time TLOW 4700 — 1300 — ns
SDA and SCL rise time TR— 1000 — 300 ns (Note 1)
SDA and SCL fall time TF— 300 — 300 ns (Note 1)
Start condition hold time THD:STA 4000 — 600 — ns After this period the first
clock puls e is generated
Start condition setup time TSU:STA 4700 — 600 — ns Only relev ant for repeated
Start condition
Data input hold time THD:DAT 0— 0 —ns(Note 2)
Data input setup time TSU:DAT 250 — 100 — ns
Stop condition setup time TSU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns T ime the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum TOF — 250 20 + 0.1 CB250 ns (Note 1), CB ≤ 100 pF
Input fil ter sp ik e s upp res si on
(SDA and SCL pin s) TSP — 50 — 50 ns (Note 3)
Write cycle time TWR — 1.5 — 1 ms Byte or Page mode
Endurance 1M — 1M — cycles 25°C, VCC = 5.0V, Block
mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site.
SCL
SDA
IN
TSU:STA
SDA
OUT
THD:STA
TLOW
THIGH TR
TBUF
TAA
THD:DAT TSU:DAT TSU:STO
TSP
TF
24C02C
DS21202D-page 4 2003 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For norma l data trans fer SDA is all owed to change only
during SCL low. Changes during SCL high are
reserved for ind icating the Start and Stop conditions.
2.2 SCL Serial Clock
This i nput is u sed t o sy nchron ize the d ata trans fer fro m
and to the device.
2.3 A0, A1, A2
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C02C devices may be connected to the
same bus by using different Chip Select bit combina-
tions. T hese i nput s mu st be c onnec ted to e ither VCC or
VSS.
2.4 WP
This is the hardware write-p rotect pin. It must be tie d to
VCC or VSS. If tied to Vcc, the ha rdware write protectio n
is enabled. If the WP pin is tied to Vss the hardware
write protection is disabled.
2.5 Noise Protection
The 24C02C employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
3.0 FUNCTIONAL DESCRIPTION
The 24C02C supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receivi ng data as receiver . The bus has t o be controlle d
by a master device which generates the serial clock
(SCL), controls the bus access, and generat es the S tart
and S t op conditi ons, while the 24C02C works as slave.
Both master and slave can operate as transmitter or
receive r but th e mas ter devic e det ermine s whic h mod e
is activated.
Name Function
Vss Ground
SDA Serial Data
SCL Serial Clock
VCC +4.5V to 5.5V Power Supply
A0, A1, A2 Chip Selects
WP Hardware Write-Protect
2003 Microchip Technology Inc. DS21202D-page 5
24C02C
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stab le when ever th e clock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined ( Figure 4-1).
4.1 Bus not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 S top Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All opera-
tions must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the cloc k signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each dat a transf er is initiated w ith a S tart condition an d
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwri te d oes oc c ur it will repl ac e da t a i n a firs t in firs t
out fashion.
4.5 Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The mast er device mus t ge nera te a n ext ra c lock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line du ring the Acknow ledge cl ock pulse in s uch a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by no t g ene rati ng an Acknow led ge bi t o n th e las t
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the maste r to gen erat e the Stop conditi on (Fi gur e 4-2).
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
FIGURE 4-2: ACKNOWLEDGE TIMING
Note: The 24C02C does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
(A) (B) (C) (D) (A)(C)
SCL
SDA
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL 987654321 123
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitt er can continue sending data.
Data from transmitter Data from transmitter
SDA
Acknowledge
Bit
24C02C
DS21202D-page 6 2003 Microchip Technology Inc.
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four bit control code; for
the 24C02C this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the Chip Select bits (A2, A1, A0). The Chip Select bits
allow the use of up to eight 24C02C devices on the
same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
corresp ond to the logic lev els on the corresp onding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. Following the Start condition, the 24C02C
monitors the SDA bus checking the control byte being
transmi tted. U pon rece iving a 101 0 co de and ap propri-
ate Chip Select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24C02C will select a read or
write operation.
FIGURE 5-1: CONTROL BYTE FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 16K bits by
adding up to eight 24C02C devices on the same bus.
In this case, software can use A0 of the control byte
as address bit A8, A1 as address bit A9, and A2 as
address bit A10. It is not possible to write or read
across device boundaries.
1 0 1 0 A2 A1 A0SACKR/W
Control Code Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
2003 Microchip Technology Inc. DS21202D-page 7
24C02C
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start signal from the master, the device
code (4 bits), the Chip Select bits (3 bits) and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. The device will acknowledge this
control by te during the ninth clock pulse. The ne xt byte
tran smit ted by the ma ster is the word add res s and wi ll
be written into the address pointer of the 24C02C. After
receiving another Acknowledge signal from the
24C02C the master device will transmit the data word
to be written into the addressed memory location. The
24C02C acknowledges again and the master gener-
ates a Stop condition. This initiates the internal write
cycle, and during this time the 24C02C will not gener-
ate Acknowledge signals (Figure 6-1). If an attempt is
made to write to the protected portion of the array when
the hardware write protection has been enabled, the
device will acknowledge the command but no data will
be written. The write cycle time must be observed even
if the write protection is enabled.
6.2 Page Write
The write control byte, word address and the first data
byte are tr ansmitted to the 24 C02C in the same way a s
in a byte write. But instead of generating a Stop
conditi on, th e mas ter tran smit s u p to 15 addi tional dat a
bytes to the 24C02C which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a Stop
conditi on. After th e recei pt of each word , the four lo wer
order address pointer bit s are internally incremented by
one. The higher order four bits of the word address
remains constant. If the master should transmit more
than 1 6 bytes p rior to gen erating the S top cond ition, the
address counter will roll over and the previously
receive d dat a wil l be overwri tten. As w ith the byte write
operation, once the Stop condition is received an
internal write c ycle wil l begin (Figure 6-2). If an att empt
is made to write to the protected portion of the array
when the hardware write protection has been enabled,
the device will acknowledge the command but no data
will be written. The write cycle time must be observed
even if the write protection is enabled.
6.3 WRITE PROTECTION
The WP pin must be tied to VCC or VSS. If tied to VCC,
the upper half of the array (080-0FF) will be write-
protected. If the WP pin is tied to VSS, then write
operations t o all addr ess locations a re allowed.
FIGURE 6-1: BYTE WRITE
FIGURE 6-2: PAG E WR ITE
Note: Page write opera tions are l imited to wri ting
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buf fer size (or
‘page size’ ) an d end at addresses that are
integer multiples of [page size - 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being w ritte n to th e nex t page as mi ght be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S P
Bus Acti vity
Master
SDA Line
Bus Acti vity
S
T
A
R
T
S
T
O
P
Control
Byte Word
Address Data
A
C
K
A
C
K
A
C
K
S P
Bus Activit y
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte Word
Address (n) Data n Data n + 15
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data n +1
24C02C
DS21202D-page 8 2003 Microchip Technology Inc.
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no AC K is retu rned, then the S t art bit and cont rol byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then pro-
ceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
8.0 READ OPERATIONS
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There a re three basic types
of read operation s: curren t address re ad, ra ndom rea d,
and sequential read.
8.1 Current Address Read
The 24C02C contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operat ion woul d acc ess da ta f rom add ress n + 1. Upo n
receipt o f the slave a ddress with the R/W bit s et to one,
the 24C02C issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the tr ansfer but does ge nerate a Stop conditi on and th e
24C02C discontinues transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad o peration, first the word ad dres s m us t
be set. This is done b y sending the word address to the
24C02C as part of a write operation. After the word
address is sent, the master generat es a Start conditio n
following the acknowledge. This terminates the write
operatio n, but not bef ore the internal addre ss pointe r is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24C02C will then
issue an acknowledge and transmits the eight bit data
word. The m aster wil l not a cknowledg e the tra nsfer b ut
does generate a Stop condition and the 24C02C
discontinues transmission (Figure 8-2). After this
command, the interna l address counte r will po int to the
address location following the one that was just read.
8.3 Sequentia l Read
Sequential reads are initiated in the same way as a
random read except that after the 24C02C transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24C02C to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24C02C contains an
internal address poin ter which is inc remented by o ne at
the com ple tio n o f each ope rati on. Thi s a ddre ss po int er
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address FF to address 00.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
2003 Microchip Technology Inc. DS21202D-page 9
24C02C
FIGURE 8-1: CURRENT ADDRESS READ
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
Bus Acti vity
Master
SDA line
Bus Acti vity
P
S
S
T
O
P
Control
Byte
S
T
A
R
TData
A
C
K
N
O
A
C
K
S P
S
S
T
A
R
T
S
T
O
P
Control
Byte
A
C
K
Word
Address (n) Control
Byte
S
T
A
R
TData (n)
A
C
K
A
C
K
N
O
A
C
K
Bus Activity
Master
SDA line
Bus Activity
Control
Byte Data n Data n + 1 D ata n + 2 Data n + X
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
Bus Acti vity
Master
SDA line
Bus Acti vity
24C02C
DS21202D-page 10 2003 Microchip Technology Inc.
APPENDIX A: REVISION HIST ORY
Revision D
Corrections to Section 1.0, Electrical Characteristics.
2003 Microchip Technology Inc. DS21202D-page 11
24C02C
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24C02C
DS21202D-page 12 2003 Microchip Technology Inc.
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DS21202D24C02C
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2003 Microchip Technology Inc. DS21202D-page 13
24C02C
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PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device 24C02C 2K I2C™ Serial EEPROM
24C02CT 2K I2C™ Serial EEPROM (Tape and Reel)
Temp er atu re Rang e Blank = 0°C to +70°C
I= -40°C to +85°C
E= -40°C to +125°C
Packag e P = Plastic DIP (300 mil Bod y), 8-le ad
SN = Plastic SOIC, (150 mil Body), 8-lead
ST = TSSOP (4.4 mm Body), 8-lead
24C02C
DS21202D-page 14 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS21202D-page 15
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporat ed with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’ s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PIC m ic ro, PI C START,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor , SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorpora ted in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• Th ere are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the co de protect ion features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such ac t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and M ount ain View, Cali fornia in March 2 002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, micr operipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS21202D-page 16 2003 Microchip Technology Inc.
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