DATA SH EET
Product specification
File under Integrated Circuits, IC04 January 1995
INTEGRATED CIRCUITS
HEF4073B
gates
Triple 3-input AND gate
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Triple 3-input AND gate HEF4073B
gates
DESCRIPTION
The HEF4073B provides the positive triple 3-input AND
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.1 Functional diagram.
HEF4073BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4073BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4073BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
Fig.3 Logic diagram (one gate).
January 1995 3
Philips Semiconductors Product specification
Triple 3-input AND gate HEF4073B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb =25°C; CL= 50 pF; input transition times ≤20 ns
VDD
VSYMBOL TYP. MAX. TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
In→On5 55 110 ns 23 ns +(0,55 ns/pF) CL
HIGH to LOW 10 tPHL 25 50 ns 14 ns +(0,23 ns/pF) CL
15 20 40 ns 12 ns +(0,16 ns/pF) CL
5 45 90 ns 13 ns +(0,55 ns/pF) CL
LOW to HIGH 10 tPLH 20 40 ns 9 ns +(0,23 ns/pF) CL
15 15 30 ns 7 ns +(0,16 ns/pF) CL
Output transition times 5 60 120 ns 10 ns +(1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
5 60 120 ns 10 ns +(1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
VDD
VTYPICAL FORMULA FOR P (µW)
Dynamic power 5 600 fi+∑(foCL)×VDD2where
dissipation per 10 2700 fi+∑(foCL)×VDD2fi= input freq. (MHz)
package (P) 15 8400 fi+∑(foCL)×VDD2fo= output freq. (MHz)
CL= load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
