May 2000 1/15
AN1237
APPLICATION NOTE
Driving an M88x3Fxx FLASH+PSD Device
From an M 68HC 11
This document contains an example memory-map when using a FLASH+PSD device with an M68HC11.
It also includes an associated minimal connection schematic and a PSDabel file. The suggested memory
map is given for a M8813F1x part. Many other memory configurations are possible; however, this
example provide s the best utilization of th e FLASH+PSD Decode P LD (DPLD). (The mem ory map f or a
M8813F2x can look just like a m ap for t he M8813F1x with EEPRO M areas re placed by a secondar y Fl ash
memory). Figure 1 shows the priority level of the PSD me mory and I /O comp onent s. If a component on
a lower level overlaps one on a higher level, priority will be given to the item on the lower level. For
example, if the PSD’s SRAM is mapped to 8000h – 87FFh, and its Flash memory segment 3 (fs3) is
mapped to 8000h – BFFFh, any address in the 8000 to 87FFh range would access the SRAM, effectively
reducing the size of that Flash me mory segment by 2 Kbytes, from 8800h to BFFFh .
Figure 1. Priority Level Pyramid of Memory and I/O Components
Most of the Motorola 68HC11 family of microcontrollers have only 64 KBytes of address space. Because
of this, a simple paging scheme is required to utilize all of the memory in the FLASH+PSD and to allow In-
System-Programm ing (ISP). The PSDabel tem plate file provided uses 4 of the 8 PSD pag e register bits
in the follo win g w a y :
■2 of the page register bits are decoded to allow up to f our memory pages
■1 page bit is used for swappin g EEPROM segments with Flash memory segments (“swap” bit)
■1 page bit is used for EEPROM securi ty, l imi ting acces s to the boot code in the EEPRO M (“unl ock” b it)
For this example, at power-up, the MCU fetches a reset vector from high memory (FFFE – FFFF) which
is stored in PSD EEPROM . T his reset vector forces a jump to location 0xC000 (also in PSD EE PR OM),
which contains code for initialization (boot), UART download protocol, and access to Flash memory. The
very first instruction that the HC11 executes in the initialization routine is one which relocates the internal
HC11 SRAM and registers to a new location, 0x8000, from the default lo cation, 0x0000. The HC11 allows
this, which makes our mapping scheme easier to work with because we can create a contiguous
“common” memory area from 0x 8000 to 0xFFFF. This common area inclu des the reset vectors in h igh
memory (0xFFFE), and the HC11 registers and memory starting at 0x8000. This leaves the address range
0x0000 to 0x7FFF open for paged memo ry, as shown in Fi gure 3.
Level 3
Flash Memory
Level 2
EEPROM/Boot Flash
Memory
Level 1
SRAM, I /O, or
Peripheral I/O
AI03738
AN1237 - APPLICATION NOTE
2/15
After boot an d ini tialization, and whil e the HC11 is exec uting out of E E PROM, t he Flash mem ory can be
checke d for valid contents (using the checksum) o r it can be programmed with UART data from a host
computer if needed. After the Flash memory contents are validated, HC11 execution will jump to Flash
memory (fs0), then set the s wap bit in side the PSD page register to swap a portion of Flash memory (fs7)
with a portion of EEPROM (ees0 and ees1). After the swap, the HC11 is executing completely out of Flash
memory. If desired, the original boot code in EEPROM segments ees0 and ees1 can be modified with new
code received over the UART. For this to happen, the HC11 must first set the “unlock” bit in the PSD page
registe r before modifying the EEPROM boot c ode. The rem ainder of EEP ROM (ees2 and ees3) can be
treated as general data and is independent of the unlock bit.
At the next reset or power cycle, this sequence will be r epeated ( HC11 boot s from EEPRO M ).
Figure 2. Schema tic for the M68HC11 and M881 3F1x
Notes: 1. Connections are shown between the MC68HC11 MCU and the PLCC package for the M8813F1x, but only the necessary pins on
the MCU are show n.
M8813F1X
ADIO0
ADIO8
ADIO7
ADIO6
ADIO5
ADIO4
ADIO3
ADIO2
ADIO1
ADIO15
ADIO14
ADIO13
ADIO12
ADIO11
ADIO9
ADIO10
CNTL0
PD0-AS
CNTL1
RESET
PA0
PA1
PC0/TMS
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
PA2
PC1/TCK
PC2/VSTBY
PC7
PC6/TDO
PC5/TDI
PC4/TERR
PC3/TSTAT
PD2-CSI
PD1-CLKIN
CNTL2
30
39
37
36
35
34
33
32
31
45
44
43
42
41
40
49
47
46
9
10
50
48
8
12
11
52
51
20
19
17
14
13
6
5
4
3
2
7
21
22
23
24
25
27
28
29
18
Optional
JTAG Port
TMS
TDO
TDI
TERR|
TSTAT
TCK
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
A15
R/W
DS
AS
68HC11
RESET
RESET
Vcc Optional 3.6 V
lithium battery or cap
Vcc
MODB
MODA
AI03739
3/15
AN1237 - APPL ICATION NOTE
Figure 3. Memory M ap for the M68HC11 and M8 813F1 x
Not es : 1. If the MCU sets unlo ck=1, it can upda te the origi n al boot code in EES0 and EES1
FFFF
C000
8B00
8200
9000
4000
8000
0000
Power-up or Reset:
swap = 0
FFFF
C000
8B00
8200
9000
4000
8000
0000
After UART Flash Download and/or
good Flash Checksum:
Set swap = 1
Not to
Scale Not to
Scale
2000 2000
FS7 - Common to all pages
16 Kbytes Flash
FS6
Page 2
16 Kbytes
Flash
FS4
Page 1
16 Kbytes
Flash
FS2
Page 0
16 Kbytes
Flash
FS5
Page 2
16 Kbytes
Flash
FS3
Page 1
16 Kbytes
Flash
FS1
Page 0
16 Kbytes
Flash
EES2
Page 3
16 Kbytes
EEPROM
EES3
Page 3
16 Kbytes
EEPROM
FS0 - Common to all pages
12 Kbytes F lash
FS0 - Common to all pages
12 KBytes Flash
HC11
(512 Byte s Regist ers/ S R AM)
rs0/csiop - Common to all pages
2 Kbytes SR AM + 256 bytes I/O
CS_DEV0/1/2 - Common to all
pages
1.25 Kbyt es E xt ernal Device Chip Se lects
HC11
(512 Byt es Reg isters/SRAM)
rs0/csiop - Common to all pages
2 Kbytes SRAM + 256 bytes I/O
CS_DEV0/1/2 - Common to all
pages
1.25 Kbytes External Device Chip Selects
FS7
Page 3
16 Kbytes
Flash
FS4
Page 1
16 Kbytes
Flash
FS2
Page 0
16 Kbytes
Flash
FS5
Page 2
16 Kbytes
Flash
FS3
Page 1
16 Kbytes
Flash
FS1
Page 0
16 Kbytes
Flash
EES2
Page 3
16 Kbytes
EEPROM
EES3
Page 3
16 Kbytes
EEPROM
{
{
FS6
Page 2
16 Kbytes
Flash
EES0 - Common to all pages
8 Kbytes EEPROM
EES1 - Common to all pages
8 Kbytes EEPROM
EES0
Page 3
16 Kbytes
EEPROM
EES1
Page 3
16 Kbytes
EEPROM
AI03740
Boot
from
here
AN1237 - APPLICATION NOTE
4/15
TEMPLATE FOR THE M68HC11 AND M 8813F 1X
title ‘ST M88 FLASH+PSD design template for the 68HC11 fami ly
of microcontrollers (multiplexed bus versions)’;
“**** Important: 52 pin PQFP package users... regard all pi n
“**** numbers in this template as 52 pin PLCC package pin
“**** assignments.
“**** Template rev date 9/17/99
“**** This PSDabel file is used to:
“****
“**** 1. Define the chip select equations for internal PSD components.
“**** These equations are implemented on the DPLD to sel ect:
“**** * Main Flash memory
“**** * Secondary NVM programmable memory (EEPROM for
“**** M8813F1, Flash for M88X3F2)
“**** * SRAM
“**** * PSD control registers
“****
“**** 2. Define external chip select equations.
“****
“**** 3. Define equations for the CPLD application specific logic.
“****
“**** Refer to Application Note AN1171 - ‘PSD CPLD Primer’ for more
“**** information and examples. Also, see Application note AN1170 for
“**** memory map information.
“**** This template makes the following assumption about th e
“**** setting of the HC11:
“**** - The SRAM and registers internal to the HC11 are mov ed
“**** from their default location (address 0x0000) to add ress
“**** 0x8000. The HC11 allows this move within the first 64
“**** E clocks after reset is released.
“PIN DECLARATIONS
“**** Declare pin names for all I/O signals. Pin numbers ar e not
“**** necessary if it is desired to let the PSDsoft Fitter utility
“**** choose the best fit. If reserved signal names are use d,
“**** predetermined pin numbers are automatically assigned. Some
“**** signals must remain on certain pins (microcontroller addr, data,
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AN1237 - APPL ICATION NOTE
“**** control, etc.). See PSDsoft users manual for complete list of
“**** reserved names.
“****
“**** Delete any pin declaration that is not used in this t emplate.
“**** Remove the comment delimiter from any statements that will
“**** be included in this compilation.
“****
“**** Important: All pin numbers generated from this templa te
“**** (either from reserved signal names or from direct pin
“**** assignments) are for the 52 pin PLCC package.
“*********** MCU Bus Interface signal declarations ******** **********
“**** The following are HC11 bus input signals to the FLASH +PSD PLDs.
“psen pin 49; The PSEN pin is not used in Motorola MCU
r_w pin;“CNTL0 Input:(pin 47)- read/write indicator
e pin;“CNTL1 Input:(pin 50)- E clock
//name pin 49; “CNTL2 Input:(pin 49)- not used as contro l for HC11,
“this pin can be used for a general input t o PLD.
“Insert your signal name.
as pin;“PD0 Input:(pin 10)- address strobe
reset pin; “Input:(pin 48)- system reset
a15..a0 pin; “Input:(pins 46..39,37..30)- demuxed addres s
“**** In addition to making these declarations, use the PSD
“**** Configuration utility and make these selections:
“**** * 8-bit muxed data bus
“**** * R/W, E for control setting
“**** * Active high level for ALE/AS
“**** * Enable CSi if used in application
“******** Port A, B, C, D pin declaration ***************** ***********
“**** Pin or node names must be declared for all signals. R eplace
“**** reserved pin signal names in this template with your own names
“**** if desired. Remember, the PSDsoft Fitter utility will assign
“**** predetermined pin numbers to signals with reserved pi n signal
“**** names. See PSDsoft user’s manual for list of reserved names.
“****
“**** If a CPLD output is to be used as internal feedback, declare
AN1237 - APPLICATION NOTE
6/15
“**** the signal as a node instead of a pin, using your own signal
“**** name. You can specify a certain node number to force the node
“**** to a particular Output MicroCell, or you can let the Fitter
“**** utility choose a node. See PSDsoft users manual for n ode
“**** numbers.
“****
“**** If any Output MicroCell is used as a registered outpu t, or any
“**** Input MicroCell is used as a registered input, the as sociated
“**** pin or node must be declared as a register (istype ‘r eg’).
“****
“**** For MCU I/O mode and Address Out mode, no equations a re
“**** necessary. Just declare the pin names so the Fitter u tility
“**** will not use them. These modes must be configured at run-time
“**** by the microcontroller writing to PSD control registe rs, see
“**** data sheets for reg definition.
“****
“**** See the M8813F1 tutorial (app note AN1154) and the FL ASH+PSD CPLD
“**** Primer (App note AN1171) for details and examples rel ated to
“**** these issues.
“**** Port A pin assignments
“**** Use these reserved names or edit with your own names.
//pa0 pin; “I/O (pin 29)- Port A pin pa0
//pa1 pin; “I/O (pin 28)- Port A pin pa1
//pa2 pin; “I/O (pin 27)- Port A pin pa2
//pa3 pin; “I/O (pin 25)- Port A pin pa3
//pa4 pin; “I/O (pin 24)- Port A pin pa4
//pa5 pin; “I/O (pin 23)- Port A pin pa5
//pa6 pin; “I/O (pin 22)- Port A pin pa6
//pa7 pin; “I/O (pin 21)- Port A pin pa7
“**** Port B pin assignments
//pb0 pin; “I/O (pin 7)- Port B pin pb0
//pb1 pin; “I/O (pin 6)- Port B pin pb1
//pb2 pin; “I/O (pin 5)- Port B pin pb2
//pb3 pin; “I/O (pin 4)- Port B pin pb3
//pb4 pin; “I/O (pin 3)- Port B pin pb4
//pb5 pin; “I/O (pin 2)- Port B pin pb5
//pb6 pin; “I/O (pin 52)- Port B pin pb6
//pb7 pin; “I/O (pin 51)- Port B pin pb7
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AN1237 - APPL ICATION NOTE
“**** Port C pin assignments
“**** Port C pins can be used for I/O just like Port A or
“**** Port B. However, some of the pins on Port C can be us ed for
“**** special functions such as the IEEE 1149.1 JTAG interf ace.
“**** Declare these pins for desired special functions with your
“**** own signal names, then use the PSD Configuration util ity
“**** to enable the functions. See M88 tutorial.
//pc0 pin; “I/O (pin 20)- Port C pin pc0, or JTAG TMS
//pc1 pin; “I/O (pin 19)- Port C pin pc1, or JTAG TCK
//pc2 pin; “I/O (pin 18)- Port C pin pc2, or VSTBY
//pc3 pin; “I/O (pin 17)- Port C pin pc3, or JTAG TSTAT, or Stdby On
//pc4 pin; “I/O (pin 14)- Port C pin pc4, or JTAG TERR\, or Rdy/Busy
//pc5 pin; “I/O (pin 13)- Port C pin pc5, or JTAG TDI
//pc6 pin; “I/O (pin 12)- Port C pin pc6, or JTAG TDO
//pc7 pin; “I/O (pin 11)- Port C pin pc7
“**** Port D pin assignments
“pd0 (pin 10) is assigned above as the ALE signal from the MCU
“and is not available for use as general I/O.
clkin pin; “Port D pin pd1 (pin 9) can be used as a com mon
“clock (clkin) to the PLDs and the power dow n
“circuitry. If not used as a common clock, t his
“pin may be used as general I/O.
//pd2 pin; “Port D pin pd2 (pin 8) can be used as gener al I/O
“or the global PSD chip select (CSi). If CSi is
“desired, do not declare the pin, go to the PSD
“Configuration utility and enable CSi.
“**** Following are examples of pin and node assignments th at are
“**** not tied to any particular PSD pin or node. The Fitte r utility
“**** will choose. See the Fitter report (*.frp) for actual pin and
“**** node assignments.
device_cs pin; “Combinatorial outp ut pin.
term_cnt node; “Combinatorial outp ut node.
Latched_Input7..Latched_Input0 pin istype ‘reg’; “Regist ered pins.
half_clkin node istype ‘reg,buffer’; “R eg’rd nodes
AN1237 - APPLICATION NOTE
8/15
Down_Count3..Down_Count0 node istype ‘reg,buffer’;
Init_Count3..Init_Count0 node istype ‘reg,buffer’;
“**** Example of WSIPSD PROPERTY statement for Output Micro cells.
“**** A four bit self-reloading down-counter (Down_Count[3: 0])
“**** is used internally as buried nodes. The initial count
“**** (Init_Count[3:0]) is loaded by the microcontroller . This
“**** property statement aligns the individual bits of Init _Count
“**** with the desired microcontroller data bus bits.
WSIPSD PROPERTY ‘DataBus_OMC D[3:0]:Init_Count[3:0]’;
“**** Example of WSIPSD PROPERTY statement for Input Microc ells.
“**** Eight signals on Port B will be latched by a common c lock
“**** as they enter the PSD. Input Microcells will be used to
“**** implement this. This property statement will assign p ins on
“**** Port B to be aligned with the desired microcontroller data
“**** bus bits.
WSIPSD PROPERTY ‘DataBus_IMC D[7:0]:Latched_Input[7:0] Port B’;
“******** DPLD Outputs and other internal node declaration ********
“**** The following are DPLD outputs (chip selects) for the
“**** main FLASH, alternate programmable NVM, SRAM and PSD
“**** control registers. Include or comment out the appropr iate
“**** declarations depending on which M88 device you are us ing.
“**** Main Flash memory segments ************************
fs7..fs0 node; “This declaration is supported by all M88 d evices
“**** Alternate NVM programmable segments ***************
ees3..ees0 node; “EEPROM: This declaration is supported b y M8813F1
“devices only.
//csboot3..csboot0 node; “Flash: This declaration is suppor ted by M88X3F2
“devices.
“**** SRAM **********************************************
9/15
AN1237 - APPL ICATION NOTE
rs0 node; “This declaration is supported by all the M88 fa mily.
“**** PSD Control Registers *****************************
csiop node; “This declaration is needed for all M88 devic es.
“**** Internal PSD Page Register bits
pgr1..pgr0 node; “This declaration is supported by all M88
“devices. For this template example, only two page
“bits are used as address extension (four pages).
“Declare only the page bits needed for yo ur
“application. Up to eight bits are availa ble, (pgr7
“..pgr0). Always start with pgr0 and prog ress
“upward. The future mapping feature of PS Dsoft
“relies on this binary weighting.
“**** Important. If page register bits are not used as addr ess
“**** extension bits (such as pgr0, pgr1, etc), but are
“**** used to manipulate access of memory (i.e. swapping
“**** boot memory with main memory), then they s hould be
“**** declared as individual page bit node numbe rs to be
“**** compatible with the future mapping feature of
“**** PSDsoft. Do not use the reserved page bit names
“**** (such as pgr0 .. pgr7) so that the mapping feature
“**** will not count them as part of the address .
“**** It is recommended to use bits starting at the most
“**** significant end (node 117) and work downwa rds.
“**** Here are the node numbers associated with page
“**** register bits.
“****
“**** Page register bit Internal node n umber
“**** pgr7 node 117
“**** pgr6 node 116
“**** pgr5 node 115
“**** pgr4 node 114
“**** pgr3 node 113
“**** pgr2 node 112
“**** pgr1 node 111
“**** pgr0 node 110
“**** The following page register bit definitions are an ex ample of
“**** how to manipulate memory to facilitate In-System-Prog ramming.
“**** See App note AN1237.
AN1237 - APPLICATION NOTE
10/15
swap node 117; “ This page register bit, pgr7, will be u sed for
“ swapping memory segments after a firmwa re
“ download from the HC11 UART port has co mpleted.
“ swap = 0, secondary NVM occupies boot a rea for
“ ISP, swap = 1, primary NVM occupies boo t area.
unlock node 116; “ This page reg bit, pgr6, will allow acc ess (read
“ and write) to the secondary NVM (EEPROM or Boot
“ Flash) after it has been swapped out of the boot
“ address area (after swap = 1).
“ This protects this secondary NVM boot a rea from
“ unwanted writes while unlock = 0. The M CU must
“ set unlock = 1 before it can update the
“ secondary NVM boot code.
“**** JTAG port select *********************************
jtagsel node; “Selects JTAG port active using a product term
“*******************************************************************
“DEFINITIONS
DCOUNT = [Down_Count3..Down_Count0]; “buried down counter
INIT = [Init_Count3..Init_Count0]; “initial count value
LINPUTS = [Latched_Input7..Latched_Input0]; “latched input signals
X = .x.; “Don’t care symbol
page = [pgr1,pgr0]; “You can use up to eight bits for memor y paging.
“Here, only two bits are used to define four
“memory pages. The remaining six page r egister
“bits can be used for general registere d logic
“that the microcontroller can write to. All
“eight page register bits are inputs to the PLDs.
address = [a15..a0]; “De-muxed microcontroller address sig nals
EQUATIONS
“******** DPLD equations ********************************** *******
11/15
AN1237 - APPL ICATION NOTE
“**** The following DPLD equations are examples only. If de sired,
“**** change the address ranges and page definition to suit your
“**** design. Delete any equation that is not used.
“**** Generate active high chip selects for the main Flash segments.
“**** Each segment is 16K bytes for the M88X3FX devices.
“**** All M88 devices support fs7..fs0.
fs0 = (address >= ^h9000) & (address <= ^hBFFF) & (page == X);
fs1 = (address >= ^h0000) & (address <= ^h3FFF) & (page == 0);
fs2 = (address >= ^h4000) & (address <= ^h7FFF) & (page == 0);
fs3 = (address >= ^h0000) & (address <= ^h3FFF) & (page == 1);
fs4 = (address >= ^h4000) & (address <= ^h7FFF) & (page == 1);
fs5 = (address >= ^h0000) & (address <= ^h3FFF) & (page == 2);
fs6 = (address >= ^h4000) & (address <= ^h7FFF) & (page == 2);
fs7 = ((address >= ^h4000) & (address <= ^h7FFF) & (page == 3) & !swap)
# ((address >= ^hC000) & (address <= ^hFFFF) & (page == X) & swap);
“**** Generate active high chip selects for the EEPROM segm ents.
“**** Each segment is 8K bytes for the M88 devices.
“**** Only M8813F1 devices support ees3..ees0.
ees0 = ((address >= ^hC000) & (address <= ^hDFFF) & (page = = X) & !swap)
# ((address >= ^h4000) & (address <= ^h5FFF) & (page == 3) & swap & unlock);
ees1 = ((address >= ^hE000) & (address <= ^hFFFF) & (page = = X) & !swap)
# ((address >= ^h6000) & (address <= ^h7FFF) & (page == 3) & swap & unlock);
ees2 = (address >= ^h0000) & (address <= ^h1FFF) & (page == 3) ;
ees3 = (address >= ^h2000) & (address <= ^h3FFF) & (page == 3) ;
“**** Generate active high chip selects for the alternate F lash memory
“**** segments. Each segment is 8K bytes for the M8813F2x
“**** devices. Only M88X3F2 devices support
“**** csboot3..csboot0.
//csboot0 = ((address >= ^hC000) & (address <= ^hDFFF) & (p age == X) & !swap)
// # ((address >= ^h4000) & (address <= ^h5FFF) & (p age == 3) & swap &
unlock);
//csboot1 = ((address >= ^hE000) & (address <= ^hFFFF) & (p age == X) & !swap)
AN1237 - APPLICATION NOTE
12/15
// # ((address >= ^h6000) & (address <= ^h7FFF) & (p age == 3) & swap &
unlock);
//csboot2 = (address >= ^h0000) & (address <= ^h1FFF) & (pa ge == 3) ;
//csboot3 = (address >= ^h2000) & (address <= ^h3FFF) & (pa ge == 3) ;
“**** Generate active high chip select for the FLASH+PSD SR AM (2K bytes).
rs0 = (address >= ^h8200) & (address <= ^h89FF) & (page == X);
“***** Generate active high chip select for the PSD control registers.
“***** 256 contiguous bytes must be decoded for all M88 dev ices.
csiop= (address >= ^h8A00) & (address <= ^h8AFF) & (page = = X);
“******** CPLD/ECSPLD Equations *************************** *********
“**** The CPLD provides 16 Output MicroCells to implement
“**** combinatorial or sequential logic for signals, nodes, and
“**** state machines. Some examples:
“**** Active low chip select for an external I/O device:
!device_cs = (address >= ^h8C00) & (address <= ^h8FFF) & (p age == X);
“**** Simple clock divider:
half_clkin := !(half_clkin.fb); “Register input is negated reg output
half_clkin.clk = clkin; “Assign clock input.
half_clkin.re = !reset; “Node cleared by reset inp ut.
“**** This is a self-reloading down counter. The terminal c ount can
“**** be loaded by the microcontroller at runtime. Loading is achieved
“**** by writing to the ‘INIT’ bits that were created with the Output
“**** MicroCell registers. Once ‘INIT’ is loaded, the down- counter
“**** (‘DCOUNT’) will free run and reload each time termina l count is
“**** reached.
INIT.c = 0; “The clock for these four registers s hould
“be tied to an inactive source to pre vent
13/15
AN1237 - APPL ICATION NOTE
“PSDsoft Fitter from connecting these clocks
“to the common clock (CLKIN). If CLKI N is
“the source, the data loaded by the M CU will
“be over-written.
DCOUNT.c = half_clkin; “Assign clock input.
DCOUNT.re = !reset; “Counter value is cleared at reset.
term_cnt = (DCOUNT.fb == 0); “Terminal count occurs when D COUNT = 0.
WHEN (term_cnt) THEN DCOUNT := INIT; “Load/reload after te rminal cnt
ELSE DCOUNT := DCOUNT.fb - 1; “Implements the down count
“on rising edge of ha lf_clkin.
“**** There are 24 Input MicroCells available. Here is an e xample of
“**** how eight are used to latch input signals by a common clock as
“**** they enter the PSD at pins on Port B. The microcontro ller may
“**** read the state of these signals at any time, or the s ignals
“**** may be used as sampled PLD logic inputs. The WSIPSD P ROPERTY
“**** statement above has declared this function. Only need to assign
“**** source of Input MicroCell clock here.
LINPUTS.ld = !clkin; “Inputs are latched into Input MicroC ells on
“falling edge of clkin. This clock ca n be any
“signal available to PLD. Use ‘.le’ e xtension
“(LINPUTS.le) for transparent latch f unction.
“******** State Machine *********************************** ********
“**** If you have a state machine, define the ‘state value’ and
“**** ‘state registers’ in the definition section. Refer to the
“**** PSDabel manual for additional information on implemen ting
“**** State Machine.
“**** Enter ‘state_diagram’ and state descriptions here:
“******** Test Vectors ************************************ ********
“**** Write test vectors to verify PLD logic equations or s tate
“**** machine functions. The test vector format is:
“**** [input signals logic level] -> [output signals’ expec ted value];
“**** Enter ‘X’ for the expected values if you want to obse rve the
AN1237 - APPLICATION NOTE
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“**** simulation result instead of comparing it.
“**** Here’s an example:
test_vectors([address,page,swap]
-> [fs7,fs6,fs5,fs4,fs3,fs2,fs1,fs0,ees3,ees2,ees1,ees 0,rs0,csiop])
[^hFFFE,X,0] -> [0,0,0,0,0,0,0,0,0,0,1,0,0,0];
[^hFFFE,X,1] -> [1,0,0,0,0,0,0,0,0,0,0,0,0,0];
[^h2000,2,1] -> [0,0,1,0,0,0,0,0,0,0,0,0,0,0];
[^h8300,X,X] -> [0,0,0,0,0,0,0,0,0,0,0,0,1,0];
[^h8A00,X,X] -> [X,X,X,X,X,X,X,X,X,X,X,X,X,X];
end
15/15
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