T4-LDS-0249, Rev. 1 (120183) ©2011 Microsemi Corporation Page 1 of 6
2N682, 2N683, 2N685 – 2N692
and 2N5 20 6
Available on
commercial
versions
PNPN SILI CON, REVERSE-BLOCKING,
POWER TR IODE T HYRIS T ORS
Qualified per MIL-PRF-19500/108
Quali f i ed Levels:
JAN and JANTX
DESCRIPTION
This silicon c ontrolled rectifier device is m ilitary qu alified up to a JANTX l evel for high -reliability
applications. Microsemi al so offers numerous oth er products to meet higher and low er power
vol tage reg ulation ap plication s.
TO-208 / TO-48
Package
Important: For the latest information, visit our websi te http://www.microsemi.com.
FEATURES
• JEDEC registered 2N682, 2N 683, 2N685, 2N687 – 2N692 and 2N5206.
• JAN and JANTX qualifications are avail able per MIL-PRF-19500/108.
• RoHS compliant versions available (commercial grade only).
APPLICAT IONS / BENE FITS
• A general purpose, reverse-blocking thyristor.
MAXIMUM RATINGS
MSC – Lawrence
6 Lake Street,
Lawrence, MA 01841
Tel: 1-800-446-1158 or
(978) 620-2600
Fax: (978) 689-0803
MSC – Ireland
Gort Road Business Park,
Ennis, Co. Clare, Ireland
Tel: +353 (0) 65 6840044
Fax: +353 (0) 65 6822298
Website:
www.microsemi.com
Parameters/Test Conditions
Symbol
Value
Unit
Junction Temperature
TJ
-65 to +125
oC
Storage Temperature
TSTG
-65 to +150
oC
Gate Voltage
VGM
5
V(pk)
Maximum Average DC Output Current (1)
IO
16
A
Non-repetitive Peak On-State Current (2) @ t = 7 ms
ITSM
150
A
Notes: 1. This average forward current is for a maximum case temperature of +65 °C, and 180 electrical deg rees
of conduction.
2. Surge rating is non-recurrent and applies only with device in the con ducting state. The peak rate of surge
current must not exceed 100 amperes during the first 10 μs after switching from the off (blocking) state
to the on (conducting) state. This time is measured from the point where the thyristor voltage has
decayed to 90 percent of its initial blocking value.
T4-LDS-0249, Rev. 1 (120183) ©2011 Microsemi Corporation Page 2 of 6
2N682, 2N683, 2N685 – 2N692
and 2N5 20 6
• CASE: Nickel plated copper.
• TERMINALS: Nic kel plated steel, sol der dipped.
• MARKING: Manufacturer’s ID, part number, date code, polarity.
• POLARITY: Terminal 1: gate, terminal 2: cathode, terminal 3 (stud): anode.
• WEIGHT: 12.36 grams.
• See Package Dimensions on las t page.
JAN 2N682 (e3)
Reliability Level
JAN = Jan level
JANTX = JANTX level
CDS (reference JANS)
Blank = Commercial
JEDEC type number
(See Electrical Characteristics
table)
RoHS Compl iance
e3 = RoHS compliant (available
on commercial grade only)
Blank = non-RoHS compliant
SYMBOL S & DEFI NITIONS
Symbol
Definition
VAA
Anode power supply voltage (dc).
T4-LDS-0249, Rev. 1 (120183) ©2011 Microsemi Corporation Page 3 of 6
2N682, 2N683, 2N685 – 2N692
and 2N5 20 6
Parameters / Test Conditions
Symbol
Min.
Max.
Unit
Repet i tiv e Peak R everse Volt age
And
Repet i tiv e peak off-st ate vol tage
2N682
2N683
2N685
2N686
2N687
2N688
2N689
2N690
2N691
2N692
2N5206
V
RRM
(1)
and
VDRM
50
100
200
250
300
400
500
600
700
800
1,000
V (pk)
(1) Valu es ap pli cab le to z er o or negative g ate voltage (VGM).
Parameters / Test Conditions
Symbol
Min.
Max.
Unit
Holding current:
B ias c ondit ion D; VAA = 24 V maximum;
ITM = IF1 = 1 A
IT = IF2 = 100 mA
t r i gger volt age s ource = 10 V
trigger PW = 100 μs (minimum)
R
2
= 20 Ω
IH 50 mA
Rev er se b locking c urrent
A C method, bias cond i tion D;
f = 60 Hz, VRRM = rated
IRRM1 2 mA (pk)
Forward blocking current
A C method, bias cond i tion D;
f = 60 Hz; VDRM = rated IDRM1 2 mA (pk)
Gate trigger voltage and current
V2 = VD = 6 V; RL = 50 Ω;
Re = 20 Ω maximum
VGT1
IGT1
3
35
V
mA
Forward on v ol tage
ITM = 50 A(pk) (puls e);
pulse width = 8.5 ms; m aximum;
duty cycle = 2 percent m aximum VTM 2 V (pk)
Rev er se g ate current
VG = 5 V
IG 250 mA
T4-LDS-0249, Rev. 1 (120183) ©2011 Microsemi Corporation Page 4 of 6
2N682, 2N683, 2N685 – 2N692
and 2N5 20 6
Parameters / Test Conditions
Symbol
Min.
Max.
Unit
Rev er se b locking c urrent (
TC
= +1 20 ºC
)
A C method, bias cond i tion D;
f = 60 Hz; V
RRM
= rated IRRM2 5 mA (pk)
Forward blocking current (TC = +1 20 ºC)
A C method, bias cond i tion D;
f = 60 Hz; V
DRM
= rated IDRM2 5 mA (pk)
G ate t r i gger volt age (
TC
= +1 20 ºC; R
e
= 20 Ω
max)
V
2
= V
DM
= 50 V; R
L
= 140 Ω
V2 = VDM = 100 V; RL = 140 Ω
V2 = VDM = 200 V; RL = 140 Ω
V2 = VDM = 250 V; RL = 650 Ω
V2 = VDM = 300 V; RL = 650 Ω
V2 = VDM = 400 V; RL = 3 k Ω
V2 = VDM = 500 V; RL = 3 k Ω
V2 = VDM = 600 V; RL = 3 k Ω
V2 = VDM = 700 V; RL = 3 k Ω
V2 = VDM = 800 V; RL = 3 k Ω
V = V = 1 000 V; R = 3 k Ω
2N682
2N683
2N685
2N686
2N687
2N688
2N689
2N690
2N691
2N692
2N5206
VGT2 .25 V
Rev er se b locking c urrent (T
C
= -65 ºC)
A C method, bias cond i tion D;
f = 60 Hz; VRRM = rated
IRRM3 2 mA ( pk )
Forward blocking current (TC = -65 ºC)
A C method, bias cond i tion D;
f = 60 Hz; VDRM = rated IDRM3 2 mA (pk)
G ate t r i gger volt age and cur r ent (
TC
= -65 ºC
)
V2 = VD = 6 V; RL = 50 Ω;
R
e
= 20 Ω maximum VGT3
IGT2 3
80 V
mA
Exponenti al rate of vol tage ris e
B ias c ondit ion D; TC = +1 20°C mi nimum,
dv/dt = 25 v/μs; repetition rate = 60 pps;
t est duration = 15 s;
C = 1.0 μF; RL = 50 Ω
VAA = 50 V
VAA = 100 V
VAA = 200 V
VAA = 250 V
VAA = 300 V
VAA = 400 V
VAA = 500 V
VAA = 600 V
VAA = 700 V
VAA = 800 V
VAA = 1, 00 0 V
2N682
2N683
2N685
2N686
2N687
2N688
2N689
2N690
2N691
2N692
2N5206
VD
47
95
190
240
285
380
475
570
665
760
950
V
T4-LDS-0249, Rev. 1 (120183) ©2011 Microsemi Corporation Page 5 of 6
2N682, 2N683, 2N685 – 2N692
and 2N5 20 6
Parameters / Test Conditions Symbol Min. Max. Unit
Circuit-commutated t urn-off time
TC = +120°C minimum; ITM = 10 A;
ton = 100 ±50 μs; di/dt = 5 A/μs minimum;
di/dt = 8 A/μs maximum; reverse voltage at t1 = 1 5 V minimum;
repetition rate = 60 pps maximum; di/dt = 20 V/μs;
gate bias con ditions ; g ate sourc e voltage = 0 V;
gate source resistance = 100 Ω
V
DM
= V
DRM
= 50 V (p k); V
RRM
= 50 V maximum
VDM = VDRM = 100 V (pk); VRRM = 100 V maximum
VDM = VDRM = 200 V (pk); VRRM = 200 V maximum
VDM = VDRM = 250 V (pk); VRRM = 250 V maximum
VDM = VDRM = 300 V (pk); VRRM = 300 V maximum
VDM = VDRM = 400 V (pk); VRRM = 400 V maximum
VDM = VDRM = 500 V (pk); VRRM = 500 V maximum
VDM = VDRM = 600 V (pk); VRRM = 600 V maximum
VDM = VDRM = 700 V (pk); VRRM = 700 V maximum
VDM = VDRM = 800 V (pk); VRRM = 800 V maximum
VDM = VDRM = 1,000 V (pk ) ; VRRM = 1,00 0 V ma x.
2N682
2N683
2N685
2N686
2N687
2N688
2N689
2N690
2N691
2N692
2N5206
t
off
30
30
30
30
30
30
40
40
60
60
60
µs
G ate cont r olled turn-on time
VAA = 50 V for 2N682
VAA = 100 V for 2N683, 2N6 85 thr ou gh 2N692
and 2N5206
ITM = 10 A; VGG = 10 V; Re = 25 Ω
tp1 = 15 ±5 μs; 4 A/μs ≤ di/dt ≤ 200 A/μs.
2N682,
2N683,
2N685
through
2N692 and
2N5206
ton
5
µs
T4-LDS-0249, Rev. 1 (120183) ©2011 Microsemi Corporation Page 6 of 6
2N682, 2N683, 2N685 – 2N692
and 2N5 20 6
NOTES:
1. Dimensions are in inc hes. Millimeters are given for general information
only.
2. Device contour, except on hex head and noted terminal dimensions, is
optional within zone defined by CD and OAH, CD not to exceed actual
HF.
3. Contour and angular orientation of terminals 1 and 2 with respect to
hex portion and to each other are optional.
4. Chamfer or undercut on one or both ends of the hexagonal portion are
optional.
5. Square or radius on end of terminal is optional.
6. Minimum difference in termi nal lengths to establish datum line for
numbering terminals.
7. Dimension SD is pitch diameter of coated threads.
8. In accordance with ASME Y14.5M, diameters are equivalent to Φx
symbology.
Dimensions
Ltr
Inches
Millimeters
Notes
Min
Max
Min
Max
b
.115
.139
2.92
3.53
3
b1
.210
.300
5.33
7.62
3
CD
.543
13.8
2
CH
.550
14.00
e2
.125
3.17
6
HF
.544
.563
13.8
14.3
HT
.075
.200
1.9
5.08
4
OAH
1.193
30.3
2
S
.120
3.05
3
SD
¼ - 28 UNF 2A
SL
.422
.453
10.7
11.5
SU
.090
2.29
ΦT
.125
.165
3.17
4.19
ΦT1
.060
.075
1.52
1.9
UD
.220
.249
5.59
6.32
Termi nal 1
Gate
Termi nal 2
Cathode
5
Termi nal 3
Anode (Stud)
7