65540 / 545 High Performance Flat Panel / CRT VGA Controllers Data Sheet Revision 1.2 October 1995 (R) CopyrightNotice Copyright (c) 1995, Chips and Technologies, Inc. ALL RIGHTS RESERVED. This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, any part of this publication without the express written permission of Chips and Technologies, Inc. RestrictedRightsLegend Use, duplication, or disclosure by the Government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at 252.277-7013. Trademark Acknowledgement CHIPS Logotype, CHIPSlink, CHIPSPort, ELEAT, LeAPSet, NEAT, NEATsx, PEAK, PRINTGINE, SCAT, SuperMathDX, SuperState, and WINGINE are registered trademarks of Chips and Technologies, Incorporated. CHIPSet, Super Math, WinPC, and XRAM Video Cache are trademarks of Chips and Technologies,Incorporated. IBM(R) AT, XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter, Color Graphics Adapter, Video Graphics Adapter, IBM Color Display, and IBM Monochrome Display are trademarks of International Business Machines Corporation. Hercules is a trademark of Hercules Computer Technology. MS-DOS and Windows are trademarks of Microsoft Corporation. MultiSync is a trademark of Nippon Electric Company (NEC). Brooktree and RAMDAC are trademarks of Brooktree Corporation. Inmos is a trademark of Inmos Corporation. TRI-STATE(R) is a registered trademark of National Semiconductor Corporation. VESA(R) is a registered trademark of Video Electronics Standards Association. VL-Bus is a trademark of Video Electronics Standards Association. All other trademarks are the property of their respective holders. Disclaimer This document is provided for the general information of the customer. Chips and Technologies, Inc., reserves the right to modify the information contained herein as necessary and the customer should ensure that it has the most recent revision of the data sheet. CHIPS makes no warranty for the use of its products and bears no responsibility for any errors which may appear in this document. The customer should be on notice that the field of personal computers is the subject of many patents held by different parties. Customers should ensure that they take appropriate action so that their use of the products does not infringe upon any patents. It is the policy of Chips and Technologies, Inc. to respect the valid patent rights of third parties and not to infringe upon or assist others to infringe upon such rights. (R) n 65540 / 545 High Performance Flat Panel / CRT VGA Controller n n n n n n Highly integrated design (flat panel / CRT VGA controller, RAMDAC, clock synthesizer) Multiple Bus Architecture Integrated Interface * Local Bus (32-bit CPU Direct and VL) * EISA/ISA (PC/AT) 16-bit Bus * PCI Bus (65545) Flexible display memory configurations * One 256Kx16 DRAM (512KB) * Four 256Kx4 DRAMs (512KB) * Two 256Kx16 DRAMs (1MB) Advanced frame buffer architecture uses available display memory, maximizing integration and minimizing chip count Integrated programmable linear address feature accelerates GUI performance n n n n n Hardware windows acceleration (65545) * 32-bit graphics engine - System-to-screen and screen-to-screen BitBLT - 3 operand ROP's - Color expansion - Optimized for WindowsTM BitBLT format * Hardware line drawing * 64x64x2 hardware cursor Hardware pop-up icon (65545) * 64x64 pixels by 4 colors * 128x128 pixels by 2 colors High performance resulting from zero wait-state writes (write buffer) and minimum wait-state reads (internal asynchronous FIFO design) n n n Interface to CHIPS' PC Video to display "live" video on flat panel displays Supports panel resolutions up to 1280 x 1024 resolution including 800x600 and 1024x768 Supports non-interlaced CRT monitors with resolutions up to 1024 x 768 / 256 colors True-color and Hi-color display capability with flat panels and CRT monitors up to 640x480 resolution Direct interface to Color and Monochrome Dual Drive (DD) and Single Drive (SS) panels (supports 8, 9, 12, 15, 16, 18 and 24-bit data interfaces) n n EIAJ-standard 208-pin plastic flat pack n Advanced power management features minimize power consumption during: * Normal operation * Standby (Sleep) modes * Panel-Off Power-Saving Mode Flexible on-board Activity Timer facilitates ordered shut-down of the display system Power Sequencing control outputs regulate application of Bias voltage, +5V to the panel and +12 V to the inverter for backlight operation SMARTMAPTM intelligent color to gray scale conversion enhances text legibility Text enhancement feature improves white text contrast on flat panel displays Fully Compatible with IBMTM VGA n n n Mixed 3.3V 0.3V / 5.0V 10% Operation BIOS ROM 32-bit 386/486 CPU Direct or VL Local Bus, PCI Bus, or 16-bit ISA System Bus 28 32 Address Data Control 14.31818 MHz 65540 or 65545 RGB H/V Sync To CRT Display Panel Control Panel Data To Flat Panel Display 32 16/24 512KByte or 1MByte Video Memory Optional PCVideo Multi-Media Interface 24 System Diagram Revision 1.2 65540 / 545 (R) Revision History Revision History Revision Date By Comment 1.1 9/94 DH 1.2 7/95 BB/MP Added note: Refer to Electrical Specs for maximum clock frequencies in 'Supported Video Modes' table Added note: Not all above resolutions can be supported at 3.3V and/or 5V Changed Mode 50 in Supported Video Modes-Extended Resolution Table from 16 to 16M Reset column in Reset/Setup/Test/Standby/Panel-Off Mode table was incorrect. Now reads: "RESET#/Low/-/-/High/High" Changed note for Pin List-Bus Interface: from "Drive=5V low drive and 3V high drive" to "IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)" Changed pin description: pin 25 LDEV# pin type "Out/OC" to "Out" Changed Config Reg XR01 bits 2-1 VL-Bus description for pin 23=CRESET should read pin 23=RDYRTN# Changed Ext Reg XR2D and XR2E to (CMPR Enabled) and (CMPR Disabled) and added note: "For DD panels without frame acceleration, the programmed value should be doubled" Updated tables for "No FRC" and "2-Frame FRC" Updated Flat Panel Timing "CD: 010" should read "CD: 001" Updated Programming: FLM delay programmed in XR2C should be equal to: CRT blank time - FLM front porch - FLM width XR2D LP Delay (CMPR enabled) & XR2E LP Delay (CMPR disabled) Added note: "Can use external 14.31818 MHz oscillator into XTALI (203) with XTALO (204) as no connect" Updated Elec Specs: changed "Max" under "Normal Operating Conditions" from 90 to 100; "memory clock is assumed to be 68 MHz not 65 MHz;" and "VL-Bus timing is compatible with VL-Bus Specification 2.0" Added timing for VL-Bus LDEV#, 14.31818 MHz, DRAM R/M/W and PC-Video and modified timing for PCI Bus Frame Clarified function of ACTI output. Updated Supported Video Modes table Updated I/O Map section Added 64310 to CHIPS VGA Product Family in Register Summary Updated Extension Registers table Updated XR33, XR6C, XR6F in the Extension Registers section Added Rset formula to CRT Panel Interface Circuit Updated Interface-Optrex DMF-50351NC-FW (640x480 Color STN-DD) LCD Panel Interface example Updated 65540/545 DC Characteristics in timing section Updated Local Bus Input Setup & Hold, Local Bus Output Valid, Local Bus Output Float Delay, VL-Bus LDEV#, CRT Output, Panel Output Timing diagrams Added 65545B2 specifications Revision 1.2 2 65540 / 545 (R) Table of Contents Table of Contents Section Introduction / Overview .................................. Minimum Chip Count / Board Space .......... Display Memory Interface........................... CPU Bus Interface ....................................... High Performance Features ......................... 65545 Acceleration...................................... 65545 Hardware Cursor............................... PC Video / Overlay Support........................ Display Interface.......................................... Flat Panel Displays.................................. Panel Power Sequencing ............................. CRT Displays .......................................... Simultaneous Flat Panel / CRT Display.. Display Enhancement Features ................... "True-Gray" Gray Scale Algorithm ........ RGB Color to Gray Scale Reduction ...... SmartMapTM ............................................ Text Enhancement................................... Vertical and Horizontal Compensation ... Advanced Power Management.................... Normal Operating Mode ......................... Mixed 3.3V and 5V Operation................ Panel Off Mode ....................................... Standby Mode ......................................... CRT Power Management (DPMS) ......... CPU Activity Indicator / Timer ................... Full Compatibility ....................................... Write Protection ...................................... Extension Registers ................................. Panel Interface Registers......................... Alternate Panel Timing Registers ........... Context Switching ................................... Reset, Setup, and Test Modes...................... Reset Mode.............................................. Setup Mode ............................................. Tri-State Mode ........................................ ICT (In-Circuit-Test) Mode .................... Chip Architecture ........................................ Sequencer ................................................ CRT Controller........................................ Graphics Controller ................................. Attribute Controller ................................. VGA / Color Palette DAC....................... Clock Synthesizers .................................. Configuration Inputs.................................... Virtual Switch Register ............................... Light Pen Registers...................................... BIOS ROM Interface................................... Package........................................................ Application Schematics ............................... Revision 1.2 Section Page 7 8 8 10 10 10 10 10 11 11 11 11 14 14 14 14 14 15 15 16 16 16 16 16 16 17 17 17 17 17 17 17 18 18 18 18 18 19 19 19 19 19 19 20 21 21 21 21 21 22 3 Page Pinouts (65540) ............................................... Pinouts (65545) ............................................... Pin Diagram (65540) ................................... Pin Diagram (65545) ................................... Pin Lists ....................................................... Pin Descriptions - ISA/VL-Bus Interface.... Pin Descriptions - PCI Bus Interface (65545 only) ............................................ Pin Descriptions - Display Memory ............ Pin Descriptions - Flat Panel Interface ........ Pin Descriptions - CRT and Clock Interface Pin Descriptions - Power / Gnd / Standby... 23 24 23 24 25 31 Register and Port Address Summaries ............ I/O Map........................................................ CGA, MDA, and Hercules Registers........... EGA Registers ............................................. VGA Registers............................................. VGA Indexed Registers............................... Extension Registers ..................................... 32-Bit Registers (65545) ............................. PCI Configuration Registers (65545) .......... 43 43 44 44 44 45 46 49 50 Register Descriptions ...................................... Global Control (Setup) Registers ................ PCI Configuration Registers........................ General Control & Status Registers............. CGA / Hercules Registers............................ Sequencer Registers..................................... CRT Controller Registers ............................ Graphics Controller Registers ..................... Attribute Controller and VGA Color Palette Registers .................. Extension Registers ..................................... 32-Bit Registers (65545 only) ..................... 51 53 55 59 61 63 67 81 34 37 39 40 42 89 95 155 65540 / 545 (R) Table of Contents Table of Contents Section Page Section Functional Description .................................... System Interface .......................................... Functional Blocks ................................... Bus Interface .......................................... ISA Interface ..................................... VL-Bus Interface ............................... Direct Processor Interface ................. PCI Interface ..................................... Display Memory Interface .......................... Memory Architecture ............................. Memory Chip Requirements .................. Clock Synthesizer ....................................... MCLK Operation ................................... VCLK Operation .................................... Programming the Clock Synthesizer . Programming Constraints .................. Programming Example ...................... PCB Layout Considerations ................... VGA Color Palette DAC ............................ BitBLT Engine (65545 only) ...................... Bit Block Transfer .................................. Sample Screen-to-Screen Transfer ......... Compressed Screen-to-Screen Transfer . System-to-Screen BitBLTs .................... Hardware Cursor (65545 only) ................... Programming .......................................... Cursor Data Array Format & Layout Display Mem Base Addr Formation . VGA Controller Programming .......... Copying Cursor Data to Disp Mem ... Setting Position, Type, & Base Addr 165 165 165 165 165 165 165 165 166 166 166 167 167 168 168 168 169 169 170 171 171 172 173 175 177 177 177 178 178 178 178 Programming and Parameters ......................... General Programming Hints........................ Parameters for Initial Boot .......................... Parameters for Emulation Modes ................ Parameters for Monochrome LCD Panels (Panel Mode Only) .................................. Parameters for Monochrome LCD Panels (Simultaneous Mode Display)................. Parameters for Color TFT Panels (Panel Mode Only) .................................. Parameters for Color TFT Panels (Simultaneous Mode Display)................. Parameters for Color STN SS Panels (Panel & Simultaneous Mode Display)... Parameters for Color STN SS Panels (Extended 4-bit Pack).............................. Parameters for Color STN DD Panels (Panel & Simultaneous Mode Display)... Parameters for Plasma Panels...................... Parameters for EL Panels ............................ 195 195 197 198 Application Schematics................................... System Bus Interface ................................... VL-Bus / 486 CPU Local Bus Interface...... PCI Local Bus Interface .............................. Display Memory / PC Video Interface ........ CRT / Panel Interface .................................. 209 210 211 212 213 214 Flat Panel Timing ............................................ Overview ..................................................... Panel Size .................................................... Panel Type ................................................... TFT Panel Data Width................................. Display Quality Settings.............................. Frame Rate Control (FRC)...................... Dither....................................................... M Signal Timing ..................................... Gray / Color Levels ................................. Pixels Per Shift Clock.................................. Color STN Pixel Packing ............................ Output Signal Timing .................................. LP Signal Timing .................................... FLM Output Signal Timing..................... Blank#/DE Output Signal Timing........... Shift Clock Output Signal Timing .......... Pixel Timing Sequence Diagrams ............... 179 179 179 179 179 180 180 180 180 180 181 182 183 183 183 183 183 183 Revision 1.2 Page 199 200 201 202 203 204 205 206 207 Panel Interface Examples ................................ 215 Electrical Specifications.................................. Absolute Maximum Conditions................... Normal Operating Conditions ..................... DAC Characteristics .................................... DC Characteristics....................................... DC Drive Characteristics............................. AC Test Conditions ..................................... AC Characteristics Reference Clock Timing ......................... Clock Generator Timing.......................... Reset Timing ........................................... Bus Timing.............................................. DRAM Timing ........................................ CRT Output Timing ................................ PC Video Timing .................................... Panel Output Timing ............................... 241 241 241 241 242 242 243 243 244 245 246 254 258 258 259 Mechanical Specifications............................... 261 Plastic 208-PFP Package Dimensions ......... 261 4 65540 / 545 (R) List of Tables List of Tables Table Feature Differences ......................................... Display Capabilities ........................................ Supported Video Modes - VGA...................... Supported Video Modes - Extended ............... Supported Video Modes - High Refresh ......... Vcc Pin to Interface Pin Correspondence ....... Reset/Setup/Test/Standby/Panel-Off Modes... Configuration Pin Summary............................ Page 7 9 12 13 13 16 18 21 Pin List ............................................................ 25 Pin Descriptions .............................................. 31 Standby Mode Panel Output Signal Status ..... Standby Mode Memory Output Signal Status. Standby Mode Bus Output Signal Status ........ I/O Map ........................................................... Register Summary - CGA/MDA/Herc Modes Register Summary - EGA Mode ..................... Register Summary - VGA Mode..................... Register Summary - Indexed Registers........... Register Summary - Extension Registers........ Register Summary - 32-Bit Registers (65545) Register Summary - PCI Confg Regs (65545) 41 41 42 43 44 44 44 45 46 49 50 Register List - Setup Registers ........................ Register List - PCI Configuration ................... Register List - General Control & Status ........ Register List - CGA / Hercules Registers ....... Register List - Sequencer ................................ Register List - CRT Controller........................ Register List - Graphics Controller ................. Register List - Attribute Controller and VGA Color Palette................................ Register List - Extension Registers ................. Register List - 32-Bit Registers (65545) ......... 53 55 59 61 63 67 81 Page Parameters - Initial Boot ................................ Parameters - Emulation Modes ....................... Parameters - Monochrome LCD-DD Panel Mode Only ......................................... Simultaneous Mode Display........................ Parameters - Color TFT LCD Panel Mode Only ......................................... Simultaneous Mode Display........................ Parameters - Color STN-SS LCD Panel & Simultaneous Mode Display.......... Parameters - Color STN-DD LCD 8-bit Interface Extended 4-bit Pack ............. 16-bit Interface (with FA)............................ Parameters - Monochrome Plasma.................. Parameters - Monochrome EL ........................ 197 198 199 200 201 202 203 204 205 206 207 Panel Interface Examples Summary ............... 215 DK Board Connector Summary ...................... 216 Absolute Maximum Conditions ..................... Normal Operating Conditions ........................ DAC Characteristics ....................................... DC Characteristics .......................................... DC Drive Characteristics ............................... AC Test Conditions ........................................ AC Timing Characteristics ............................. Reference Clock .......................................... Clock Generator........................................... Reset ............................................................ Local Bus Clock .......................................... Local Bus Input Setup & Hold .................... Local Bus Output Valid............................... Local Bus Float Delay ................................. VL-Bus LDEV# .......................................... PCI Bus Frame............................................. PCI Bus Stop .............................................. ISA Bus........................................................ DRAM Read / Write.................................... DRAM Read / Modify / Write..................... DRAM CBR-Refresh .................................. DRAM Self-Refresh .................................... CRT Output ................................................ PC Video ..................................................... Panel Output ............................................... 89 95 155 DRAM Speed vs. Memory Clock Frequency . 166 Revision 1.2 Table 5 241 241 241 242 242 243 243 243 244 245 246 247 248 248 249 250 252 253 254 256 257 257 258 258 259 65540 / 545 (R) List of Figures List of Figures Figure Page Figure System Diagram .............................................. 1 Panel Power Sequencing ................................. 11 Color Palette / DAC Block Diagram............... 19 Clock Synthesizer Register Structure.............. 20 Pinouts (65540) ............................................... Pinouts (65545) ............................................... Pin List ............................................................ Pin Descriptions .............................................. 23 24 25 26 Functional Description Clock Synthesizer Register Structure .......... Clock Synthesizer PLL Block Diagram ...... Clock Filter Circuit...................................... Clock Power / Ground Layout Example...... VGA Color Palette DAC Data Flow ........... Possible BitBLT Orientations With Overlap Screen-to-Screen BitBLT ............................ BitBLT Data Transfer.................................. Differential Pitch BitBLT Data Transfer..... 167 167 169 169 170 171 172 173 174 Flat Panel Timing Monochrome 16 Gray-Level EL ................ Monochrome LCD DD 8-bit Interface ....... Monochrome LCD DD 16-bit Interface ..... Color LCD TFT 9/12/16-bit Interface ........ Color LCD TFT 18/24-bit Interface ........... Color LCD STN 8-bit Interface .................. Color LCD STN 16-bit Interface ................ Color LCD STN-DD 8-bit Interface (with Frame Acceleration) ...................... Color LCD STN-DD 8-bit Interface (without Frame Acceleration) ................ Color LCD STN-DD 16-bit Interface (with Frame Acceleration) ..................... Color LCD STN-DD 16-bit Interface (without Frame Acceleration) ................ Application Schematics ISA Bus Interface ....................................... VL-Bus / 486 Processor Direct Interface ... PCI Bus Interface ........................................ Display Memory Interface .......................... CRT / Panel Interface ................................. Revision 1.2 Page Flat Panel Interface Schematics Plasma-16 - Matsushita S804 ...................... EL-16 - Sharp LJ64ZU50 ............................ Mono DD - Epson EG9005F-LS ................. Mono DD - Citizen G6481L-FF.................. Mono DD - Sharp LM64P80 ....................... Mono DD - Sanyo LCM6494-24NTK ........ Mono DD - Hitachi LMG5364XUFC ......... Mono DD - Sanyo LCM-5491-24NAK....... Mono DD - Epson ECM-A9071.................. Color TFT - Hitachi TM26D50VC2AA...... Color TFT - Sharp LQ9D011 ...................... Color TFT - Toshiba LTM-09C015-1 ......... Color TFT - Sharp LQ10D311 .................... Color TFT - Sharp LQ10DX01 ................... Color STN SS - Sanyo LM-CK53-22NEZ.. Color STN SS - Sanyo LCM5327-24NAK . Color STN SS - Sharp LM64C031.............. Color STN DD - Kyocera KCL6448........... Color STN DD - Hitachi LMG9720XUFC . Color STN DD - Sharp LM64C08P ............ Color STN DD - Sanyo LCM5331-22NTK Color STN DD - Hitachi LMG9721XUFC . Color STN DD - Tosh. TLX-8062S-C3X ... Color STN DD - Opt DMF-50351NC-FW.. Electrical Specifications Reference Clock Timing.............................. Clock Generator Timing.............................. Reset Timing................................................ Local Bus Clock Timing.............................. Local Bus '2x' Clock Synch Timing ............ Local Bus Input Setup & Hold Timing ....... Local Bus Output Valid Timing .................. Local Output Float Delay Timing ............... VL-Bus LDEV# Timing ............................. PCI Bus Frame Timing................................ PCI Bus Stop Timing................................... ISA Bus Timing........................................... DRAM Page Mode Read Cycle Timing...... DRAM Page Mode Write Cycle Timing..... DRAM Read/Modify/Write Cycle Timing.. DRAM CAS-Before-RAS (CBR) Timing... DRAM 'Self-Refresh' Cycle Timing ........... CRT Output Signal Timing ......................... PC Video Timing......................................... Panel Output Signal Timing ........................ Mechanical Specifications Plastic 208-PFP Package Dimensions ......... 184 185 186 187 188 189 190 191 192 193 194 210 211 212 213 214 6 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 243 244 245 246 246 247 248 248 249 251 252 253 255 255 256 257 257 258 258 259 261 65540 / 545 (R) Introduction / Overview Introduction / Overview The 65540 / 545 High Performance Flat Panel / CRT Controllers initiate a family of 208-pin, high performance solutions for full-featured notebook / sub-notebook and other portable applications that require the highest graphics performance available. The 65545 is pin-to-pin compatible with the 65540 and adds a sophisticated graphics hardware engine for Bit Block Transfer (BitBLT), line drawing, hardware cursor, and other functions intensively used in Graphical User Interfaces (GUIs) such as Microsoft WindowsTM. The 65540 and 65545 also use the same video BIOS, offering the system manufacturer a wide range of price / performance points while minimizing overhead for system integration and improving time-to-market. The following table indicates feature differences between the 65540 and 65545: Features 65540 Support for all flat panels 3 VESA Local Bus / 16-bit ISA Bus 3 32-bit PCI Bus -- Linear Addressing 3 Hardware Accelerator -- Hardware Cursor -- Pin Compatible 3 BIOS Compatible 3 system can be implemented with a single 256Kx16 DRAM. The 32-bit local bus interface of the 65540 / 545 family eliminates external buffers. For maximum performance, the 65540 / 545 supports an additional 256Kx16 DRAM, which provides a 32-bit video memory bus and additional display memory to support resolutions up to 1024x768 with 256 colors, 800x600 with 256 colors, and 640x480 with 16M colors. In addition, the 65540 / 545 family can support PC Video multimedia features while interfacing to a 32-bit local bus and one MByte of video memory. The 65540 / 545 family supports a wide variety of monochrome and color Single-Panel, Single-Drive (SS) and Dual-Panel, Dual Drive (DD) passive STN and active matrix TFT / MIM LCD, EL, and plasma panels. The 65540 / 545 family supports panel resolutions of 800x600, 1024x768, and 1280x1024. For monochrome panels, up to 64 gray scales are supported. Up to 226,981 different colors can be displayed on passive STN LCDs and up to 16M colors on 24-bit active matrix LCDs using the 65540 / 545 controllers. 65545 3 3 3 3 3 3 3 3 The 65540 / 545 family offers a variety of programmable features to optimize display quality. For text modes which do not fill all 480 lines of a standard VGA panel, the 65540 / 545 provides tall font stretching in the hardware. Fast vertical centering and programmable vertical stretching in graphics modes offer more options for handling modes with less than 480 lines. Three selectable color-to-grayscale reduction techniques and SMARTMAPTM are available for improving the viewability of color applications on monochrome panels. CHIPS' polynomial FRC algorithm reduces panel flicker on a wider range of panel types with a single setting for a particular panel type. The 65540 / 545 family achieves superior performance through direct connection to system processor buses up to 32-bits in width. When combined with CHIPS' advanced linear acceleration software driver technology, these devices exhibit exceptional performance compared with devices of similar architecture. The 65540 / 545 architecture provides a fast throughput to video memory, maximizing the capability of today's powerful microprocessors to manipulate graphics operations. Based on the architecture of the 65540, the 65545 adds a powerful 32-bit graphics engine to offload graphics processing from the microprocessor for maximum performance. The 65540 / 545 employs a variety of advanced power management features to reduce power consumption of the display subsystem and extend battery life. The 65540 / 545's internal logic, memory interface, bus interface, and flat panel interfaces can be independently configured to operate at either 3.3 V or 5.0 V. The 65540 / 545 is optimized for minimum power consumption during normal operation and provides two power-saving modes - Panel Off and Standby. During Panel Off mode, the 65540 / 545 turns off the flat panel while Minimum chip-count, low-power graphics subsystem implementations are enabled through the high integration level of the 65540 / 545 family. These devices integrate the VGA-compatible graphics controller, true color RAMDAC, and dual PLL clock synthesizers. The entire graphics sub- Revision 1.2 7 65540 / 545 (R) Introduction / Overview the VGA subsystem remains active. The palette may also be automatically shut off during Panel Off mode to further reduce power consumption. During Standby mode, the 65540 / 545 suspends all CPU, memory and display activities. In this mode, the 65540 / 545 places the DRAM in self-refresh mode and the 65540 / 545 reference input clock can be turned off. The 65540 / 545 also provides a programmable activity timer which monitors VGA activity. After all display activity ceases, the timer will automatically shut down the panel by either disabling the backlight or putting the 65540 / 545 in Panel Off mode. interface. The 65540 / 545 employs separate address and data buses with sufficient drive capability such that the bus can be driven directly. The 65540 / 545 also provides up to 24 bits of panel data with sufficient drive capability such that virtually all flat panels can be driven directly. DISPLAY MEMORY INTERFACE The 65540 / 545 supports multiple display memory configurations, providing the OEM with the flexibility to use the same VGA controller in several designs with differing cost, power consumption and performance criteria. The 65540 / 545 supports the following display memory configurations: The 65540 / 545 is fully compatible with the VGA graphics standard at the register, gate, and BIOS levels. The 65540 / 545 provides full backwards compatibility with the EGA and CGA graphics standards without using NMIs. CHIPS and thirdparty vendors supply fully VGA-compatible BIOS, end-user utilities and drivers for common application programs (e.g., Microsoft WindowsTM, OS/2, WordPerfect, Lotus, etc.). CHIPS' drivers for Windows include a Big Cursor (to increase the cursor's legibility on monochrome flat panels) and panning / scrolling capability (to increase performance). n n n Performance is significantly improved when the 65540 / 545 is configured with a 32-bit data path to display memory, which is accomplished by using two 256Kx16 DRAMs. Two 256Kx16 DRAMs support all standard, Super, and Extended VGA resolutions up to 1024x768 256 colors as well as "high" 16bpp color and "true" 24bpp color modes. The table on the following page summarizes the display capabilities of the 65540 / 545. MINIMUM CHIP COUNT / BOARD SPACE The 65540 / 545 provides a minimum chip count / board space, yet highly flexible VGA subsystem. The 65540 / 545 integrates a high-performance VGA flat panel / CRT controller, industry-standard RAMDAC, clock synthesizer, monitor sense circuitry and an activity timer in a 208-pin plastic flat pack package. In its minimum configuration, the 65540 / 545 requires only a single 256Kx16 DRAM, such that a complete VGA subsystem for motherboard applications can be implemented with just two ICs. This configuration consumes less than 2 square inches (1290 sq mm) of board space and is capable of supporting simultaneous flat panel / CRT display requirements while directly interfacing to a 32-bit local bus. As an option, a second memory chip may be implemented to increase performance (via a 32-bit data path to display memory) and support graphics modes which require more than 512 KBytes of display memory. No external buffers or glue logic are required for the 65540 / 545's bus interface, memory interface, or panel Revision 1.2 One 256Kx16 DRAM (512 KBytes) Two 256Kx16 DRAMs (1 MBytes) Four 256Kx4 DRAMs (512 KBytes) Display memory control signals are derived from the integrated clock synthesizer's memory clock. The 65540 / 545 serves as a DRAM controller for the system's display memory. It handles DRAM refresh, fetches data from display memory for display refresh, interfaces the CPU to display memory, and supplies all necessary DRAM control signals. The 65540 / 545 supports 'two-CAS / one-WE' and 'one-CAS / two-WE' 256Kx16 DRAMs. The 65540 / 545 supports the self-refresh features of 256Kx16 DRAMs and certain 256Kx4 DRAMs during Standby mode, enabling the 65540 / 545 to be powered down completely during suspend/resume operation. 8 65540 / 545 (R) Introduction / Overview 65540 / 545 Display Capabilities CRT Mode Mono LCD 4 Resolution Color Gray Scales 4 320x200 256 / 256K 61 / 61 640x480 16 / 256K 16 / 61 640x480 256 / 256K 61 / 61 800x600 16 / 256K 16 / 61 800x600 256 / 256K 61 / 61 1024x768 16 / 256K 16 / 61 1024x768 256 / 256K 61 / 61 1280x1024 16 / 256K 16 / 61 DD STN LCD Colors 2, 3, 4 256 / 226,981 16 / 226,981 256 / 226,981 16 / 226,981 256 / 226,981 16 / 226,981 256 / 226,981 n/a 9-Bit TFT LCD Colors 1, 2, 3, 4 256 / 185,193 16 / 185,193 256 / 185,193 16 / 185,193 256 / 185,193 16 / 185,193 256 / 185,193 n/a Video Memory 512KB 512KB 512KB 512KB 512KB 512KB 1MB 1MB Simultaneous Display Yes Yes Yes Yes with 1MB Yes with 1MB Yes with 1MB Yes n/a Notes: 1 Larger color palettes and simultaneous colors can be displayed on 12-bit, 18-bit, and 24-bit TFT panels via the 65540 / 545 video input port 2 Includes dithering 3 Includes frame rate control 4 Colors are described as number of simultaneous on-screen colors and number of unique colors available in the color palette 256K colors assumes DAC output mode is set to 6 bits of R, G, & B. If DAC is set to 8-bit output mode, the number of available colors is 16M Revision 1.2 9 65540 / 545 (R) Introduction / Overview CPU BUS INTERFACE 65545 HARDWARE CURSOR The 65540 / 545 provides a direct interface to: A programmable-size hardware cursor frees software from continuously generating the cursor image on the display. The 65545 supports four types of cursors: n 32-bit VL-Bus 32-Bit 386/486 CPU local bus EISA/ISA (PC/AT) 16-bit bus PCI Bus (65545 only) n n n 32 x 32 64 x 64 64 x 64 128 x 128 Strap options allow the user to configure the chip for the type of interface desired. Control signals for all interface types are integrated on chip. All operations necessary to ensure proper functioning in these various environments are handled in a fashion transparent to the CPU. These include internal decoding of all memory and I/O addresses, bus width translations, and generation of necessary control signals. The 65540 / 545 includes a number of performance enhancement techniques including: n n n n Direct 32-bit local bus CPU support 32-bit interface to video memory Linearly addressable display memory 32-bit graphics hardware engine (65545 only) 64x64x2 hardware cursor (65545 only) The hardware cursor can overlay either graphics or video data on a pixel by pixel basis. It may be positioned anywhere within screen resolutions up to 2048x2048 pixels. 64x64 'and/xor' cursors may also be optionally doubled in size to 128 pixels either horizontally and/or vertically by pixel replication. The 65540 /545 provides an optimized 32-bit path from 32-bit CPUs direct to the video memory. Running the 32-bit local bus of the 65540 / 545 at CPU speeds up to 33 MHz maximizes data throughput and drawing speed for today's powerful CPU architectures. Addressing pixels linearly maximizes the efficiency of software drivers, enabling the CPU to make the most use of the full 32-bit path through the 65540 / 545 controller. Software drivers optimized for linear addressing are available from CHIPS and improve performance up to 80% over standard software methods. Hardware cursor screen position, type, color, and base address of the cursor data array in display memory may be controlled via the 32-bit 'DR' extension registers. PC VIDEO / OVERLAY SUPPORT The 65540 / 545 allows up to 24 bits of external RGB video data to be input and merged with the internal VGA data stream. The 65540 / 545 supports two forms of video windowing: (i) color key input and (ii) X-Y window keying. The X-Y window key input can be used to position the live video window coordinates. The 65540 / 545 can be used in conjunction with Chips and Technologies, Inc. PC Video products to provide portable multimedia solutions. 65545 ACCELERATION Several functions traditionally performed by software have been implemented in hardware in the 65545 to off load the CPU and further improve performance. Three-Operand BitBLT logic supports all 256 logical combinations of Source, Destination, and Pattern. All BitBLTs are executed up to 32-bits per cycle, maximizing the efficiency of memory accesses. A 32-bit color expansion engine allows the host CPU to transfer monochrome "maps" of color images over the system bus at high speeds to the 65545, which decodes the monochrome images into their color form. Line drawing is also accelerated with hardware assistance. Revision 1.2 (and/xor) (and/xor) (4-color) (2-color) The first two hardware cursor types indicated as 'and/xor' above follow the MS WindowsTM AND/XOR cursor data plane structure which provides for two colors plus 'transparent' (background color) and 'inverted' (background color inverted). The last two types in the list above are also referred to as 'Pop-Ups' because they are typically used to implement pop-up menu capabilities. Hardware cursor / pop-up data is stored in display memory, allowing multiple cursor values to be stored and selected rapidly. The two or four colors specified by the values in the hardware cursor data arrays are stored in on-chip registers as high-color (5-6-5) values independent of the onchip color lookup tables. HIGH PERFORMANCE FEATURES n x 2bpp x 2bpp x 2bpp x 1bpp 10 65540 / 545 (R) Introduction / Overview DISPLAY INTERFACE called ENAVEE, ENAVDD and ENABKL to regulate the LCD Bias Voltage (VEE), the driver electronics logic voltage (VDD), and the backlight voltage (BKL) to provide intelligent power sequencing to the panel. The timing diagram below illustrates the power sequencing cycle. In the 65540 / 545, the power on/off delay time (TPO) is programmable (with a default of 32 mS). The 65540 / 545 initiates a 'panel off' sequence if the STNDBY# input is asserted (low), or if XR52 bit-4 is set to a '1' putting the chip into STNDBY mode. The 65540 / 545 also initiates a 'panel off' sequence if the chip is programmed to enter 'panel off' mode (by setting extension register XR52 bit3=1), or if the 'Display Type' is programmed to 'CRT' (extension register XR51 bit-2 transitions from '1' to '0'). The 65540 / 545 initiates a 'panel on' sequence if the STNDBY# input is high and the chip is programmed to 'panel on' (XR52 bit-3 transitions from a '1' to '0') and 'flat panel display' (XR51 bit-2 is set to '1'). The 65540 / 545 is designed to support a wide range of flat panel and CRT displays of all different types and resolutions . Flat Panel Displays The 65540 / 545 supports all flat panel display technologies including plasma, electroluminescent (EL) and liquid crystal displays (LCD). LCD panel interfaces are provided for single panel-single drive (SS) and dual panel-dual drive (DD) configurations. A single panel sequences data similar to a CRT (i.e., sequentially from one area of video memory). In contrast, a dual panel requires video data to be provided alternating from two separate areas of video memory. In addition, a dual drive panel requires the data from the two areas to be provided to the panel simultaneously. Due to its integrated frame buffer and 24-data-line panel interface, the 65540 / 545 supports all panels directly. Support for LCD-DD panels does not require external hardware such as a frame buffer. Support for highresolution, 'high color' flat panels also does not require additional components. The 65540 / 545 handles display data sequencing transparently to applications software, providing full compatibility on both CRT and flat panel displays. 9-bit '512-Color' 512 (83) 3,375 (153) 24,389 (293) 185,193 (573) Panel On ENAVDD TPO 12-bit '4096-Color' Dither FRC 4096 (163) No No 29,791 (313) No Yes 226,981 (613) Yes No 1,771,561 (1213) Yes Yes TPO ENABKL Flat Panel Control & Data Signals Valid TPO There is currently no standard interface for flat panel displays. Interface signals and timing requirements vary between panel technologies and suppliers. The 65540 / 545 provides register programmable features to allow interfacing to the widest possible range of flat panel displays. The 65540 / 545 provides a direct interface to panels from vendors such as Sharp, Sanyo, Epson, Seiko Instruments, Oki, Toshiba, Hitachi, Fujitsu, NEC, Matsushita/Panasonic, and Planar. T PO ENAVEE Panel Power Sequencing CRT Displays The 65540 / 545 supports high resolution fixed frequency and variable frequency analog monitors in interlaced and non-interlaced modes of operation. Digital monitor support is also built in. PANEL POWER SEQUENCING Flat panel displays are extremely sensitive to conditions where full biasing voltage VEE is applied to the liquid crystal material without enabling the control and data signals to the panel. This results in severe damage to the panel and may disable the panel permanently. The 65540 / 545 provides a simple and elegant method to sequence power to the flat panel display during various modes of operation to conserve power and provide safe operation to the flat panel. The 65540 / 545 provides three pins Revision 1.2 Panel Off The 65540 / 545 supports resolutions up to 1024x768 256 colors, 800x600 256 colors or 640x480 16,777,216 colors in 1 MByte display memory configurations, 1024x768 16 colors, 800x600 256 colors in 512 KBytes display memory configurations. The tables starting on the following page list all 65540 / 545 CRT monitor video modes. 11 65540 / 545 (R) Introduction / Overview Supported Video Modes - VGA Standard Horizontal Vertical Mode# Display Text Font Pixel DotClock Frequency Frequency Video (Hex) Mode Colors Display Size Resolution (MHz) (KHz) (Hz) Memory 0, 1 Text 16 40 x 25 8x8 360x400 28.322 31.5 70 256 KB 0*, 1* 40 x 25 8x14 320x350 25.175 0+, 1+ 40 x 25 8x8 320x200 25.175 2, 3 Text 16 80 x 25 9x16 720x400 28.322 31.5 70 256 KB 2*, 3* 80 x 25 8x14 640x350 25.175 2+, 3+ 80 x 25 8x8 640x200 25.175 4 Graphics 4 40 x 25 8x8 320x200 25.175 31.5 70 256 KB 5 Graphics 4 40 x 25 8x8 320x200 25.175 31.5 70 256 KB 6 Graphics 2 80 x 25 8x8 640x200 25.175 31.5 70 256 KB 7 Text Mono 80 x 25 9x16 720x400 28.322 31.5 70 256 KB 7+ 80 x 25 9x14 720x350 D Planar 16 40 x 25 8x8 320x200 25.175 31.5 70 256 KB E Planar 16 80 x 25 8x8 640x200 25.175 31.5 70 256 KB F Planar Mono 80 x 25 8x14 640x350 25.175 31.5 70 256 KB 10 Planar 16 80 x 25 8x14 640x350 25.175 31.5 70 256 KB 11 Planar 2 80 x 30 8x16 640x480 25.175 31.5 60 256 KB 12 Planar 16 80 x 30 8x16 640x480 25.175 31.5 60 256 KB 13 Packed Pixel 256 40 x 25 8x8 320x200 25.175 31.5 70 256 KB Note: * All of the above VGA standard modes are supported directly in the 65548 BIOS (both 32K and 40K BIOS versions). * All of the above VGA standard modes are supported at both 3.3V and 5V. * All VGA modes using 25.175 MHz and 28.322 MHz can also be supported using 32 MHz and 36 MHz respectively. CRT A,B,C A,B,C A,B,C A,B,C A,B,C A,B,C A,B,C A,B,C A,B,C A,B,C A,B,C A,B,C A,B,C In this case, the horizontal frequency becomes 40.000 KHz and the vertical frequency becomes 89 Hz. (see XR33 bit-7 "ISO Mode Control" for selection of VGA dot clock frequencies) Note: Not all above resolutions can be supported at both 3.3V and 5V. Refer to Electrical Specifications section for maximum clock frequencies for 5V and 3.3V operation. CRT Codes: A PS/2 fixed frequency analog CRT monitor or equivalent (31.5 / 35.5 KHz Horizontal Frequency Specification) B Multi-Frequency CRT monitor (37.5 KHz Minimum Horizontal Frequency Specification) (NEC MultiSync 3D or equivalent) C Multi-Frequency High-Performance CRT Monitor (48.5 KHz Min H Freq Specification) (Nanao Flexscan 9070s, MultiSync 5D, or equivalent) Revision 1.2 12 65540 / 545 (R) Introduction / Overview Supported Video Modes - Extended Resolution Mode# Display (Hex) Mode 20 4 bit Linear 22 4 bit Linear 24 4 bit Linear 24 I 4 bit Linear 28I 4 bit Linear 30 8 bit Linear 32 8 bit Linear 34 8 bit Linear 34 I 8 bit Linear 40 15bit Linear 41 16bit Linear 50 24bit Linear 60 Text 61 Text 6A, 70 Planar 72,75 Planar 72, 75I Planar 78 Packed Pixel 79 Packed Pixel 7C Packed Pixel 7E Packed Pixel 7E I Packed Pixel 76 I 4 bit Planar Colors 16 16 16 16 16 256 256 256 256 32K 64K 16M 16 16 16 16 16 16 256 256 256 256 16 Text Display 80 x 30 100 x 37 128 x 48 128 x 48 128 x 48 80 x 30 100 x 37 128 x 48 128 x 48 80 x 30 80 x 30 80 x 30 132 x 25 132 x 50 100 x 37 128 x 48 128 x 48 80 x 25 80 x 30 100 x 37 128 x 48 128 x 48 128 x 48 Font Size 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 8x16 Pixel DotClock Resolution (MHz) 640x480 25.175 800x600 40.000 1024x768 65.000 1024x768 44.900 1280x1024 65.000 640x480 25.175 800x600 40.000 1024x768 65.000 1024x768 44.900 640x480 50.350 640x480 50.350 640x480 65.000 1056x400 40.000 1056x400 40.000 800x600 40.000 1024x768 65.000 1024x768 44.900 640x400 25.175 640x480 25.175 800x600 40.000 1024x768 65.000 1024x768 44.900 1280x1024 65.000 Horizontal Vertical Frequency Frequency Video (KHz) (Hz) Memory CRT 31.5 60 512 KB A,B,C 37.5 60 512 KB B,C 48.5 60 512 KB C 35.5 43 512 KB B,C 42.5 39 1 MB C 31.5 60 512 KB A,B,C 37.5 60 512 KB B,C 48.5 60 1 MB C 35.5 43 1 MB B,C 31.5 60 1 MB A,B,C 31.5 60 1 MB A,B,C 27.1 51.6 1 MB B,C 30.5 68 256 KB A,B,C 30.5 68 256 KB A,B,C 38.0 60 256 KB B,C 48.5 60 512 KB C 35.5 43 512 KB B,C 31.5 70 256 KB A,B,C 31.5 60 512 KB A,B,C 37.5 60 512 KB B,C 48.5 60 1 MB C 35.5 43 1 MB B,C 42.5 39 1 MB C Note: Support for the modes in the above table is included directly in the BIOS (both 32K and 40K versions). The "I" in the mode # column indicates "Interlaced". Supported Video Modes - High Refresh Mode# Display Text Font Pixel DotClock (Hex) Mode Colors Display Size Resolution (MHz) 12* Planar 16 80 x 30 8x16 640x480 31.500 30 8 bit Linear 256 80 x 30 8x16 640x480 31.500 79 Packed Pixel 256 80 x 30 8x16 640x480 31.500 6A, 70 Planar 16 100 x 37 8x16 800x600 49.500 32 8 bit Linear 256 100 x 37 8x16 800x600 49.500 7C Packed Pixel 256 100 x 37 8x16 800x600 49.500 Horizontal Vertical Frequency Frequency Video (KHz) (Hz) Memory CRT 37.5 75 256 KB B,C 37.5 75 256 KB C 37.5 75 512 KB C 46.9 75 512 KB C 46.9 75 1 MB C 46.9 75 1 MB C Note: Not all above resolutions can be supported at both 3.3V and 5V. Refer to Electrical Specifications section for maximum clock frequencies for 5V and 3.3V operation. CRT Codes: A PS/2 fixed frequency analog CRT monitor or equivalent (31.5 / 35.5 KHz Horizontal Frequency Specification) B Multi-Frequency CRT monitor (37.5 KHz Minimum Horizontal Frequency Specification) (NEC MultiSync 3D or equivalent) C Multi-Frequency High-Performance CRT Monitor (48.5 KHz Min H Freq Specification) (Nanao Flexscan 9070s, MultiSync 5D, or equivalent) Revision 1.2 13 65540 / 545 (R) Introduction / Overview Simultaneous Flat Panel / CRT Display refresh rate -- has several drawbacks. As the vertical refresh rate increases, panel power consumption increases, ghosting (cross-talk) increases, and contrast decreases. CHIPS' polynomial FRC gray scale algorithm reduces flicker without increasing the vertical refresh rate. The 65540 / 545 provides simultaneous display operation with Multi-Sync variable frequency or PS/2 fixed frequency CRT monitors and single panel-single drive LCDs (LCD-SS), dual panel-dual drive LCDs (LCD-DD), and plasma and EL panels (which employ single panel-single drive interfaces). Single drive panels sequence data in the same manner as CRTs, so the 65540 / 545 provides simultaneous CRT display with LCD-SS, Plasma, and EL panels by driving the panels with CRT timing. LCD-DD panels require video data alternating between two separate locations in memory. In addition, a dual drive panel requires data from both locations simultaneously. A framestore area, also called the frame buffer, is required to achieve this operation. The 65540 / 545 innovative architecture implements the frame buffer in an unused area of display memory, reducing chip count and subsystem cost. As an option, an extra 16-bit wide DRAM can be used as an external frame buffer, improving performance while in simultaneous flat panel/CRT modes. The 65540 / 545 provides simultaneous display with monochrome and color LCD-DD panels with a single 256Kx16 DRAM. RGB Color To Gray Scale Reduction The 24 bits of color palette data from the VGA standard color lookup table (CLUT) are reduced to 6 bits for 64 gray scales via one of three selectable RGB color to gray scale reduction techniques: 1) NTSC Weighting: 5/16 Red 9/16 Green 2/16 Blue 2) Equal Weighting: 5/16 Red 6/16 Green 5/16 Blue 3) Green Only: 6 bits of Green only NTSC is the most common weighting, which is used in television broadcasting. Equal weighting increases the weighting for Blue, which is useful for Applications such as Microsoft Windows 3.1 which often uses Blue for background colors. Green-Only is useful for replicating on a flat panel the display of software optimized for IBM's monochrome monitors which use the six green bits of palette data. DISPLAY ENHANCEMENT FEATURES SmartMapTM Display quality is one of the most important features for the success of any flat panel-based system. The 65540 / 545 provides many features to enhance the flat panel display quality. SmartMapTM is a proprietary feature that can be invoked to intelligently map colors to gray levels in text mode. SmartMapTM improves the legibility of flat panel displays by solving a common problem: "TRUE-GRAY" Gray Scale Algorithm Most application programs are optimized for color CRT monitors using multiple colors. For example, a word processor might use a blue background with white characters for normal text, underlined text could be displayed in green, italicized text in yellow, and so on. This variety of colors, which is quite distinct on a color CRT monitor, can be illegible on a monochrome flat panel display if the colors are mapped to adjacent gray scale values. In the example, underlined and italicized text would be illegible if yellow is mapped to gray scale 4, green to gray scale 6 with the blue background mapped to gray scale 5. A proprietary polynomial-based Frame Rate Control (FRC) and dithering algorithm in the 65540 / 545's hardware generates a maximum of 61 gray levels on monochrome panels. The FRC technique simulates a maximum of 16 gray levels on monochrome panels by turning the pixels on and off over several frames in time. The dithering technique increases the number of gray scales from 16 to 61 by altering the pattern of gray scales in adjacent pixels. The persistence (response time) of the pixels varies among panel manufacturers and models. By re-programming the polynomial (an 8bit value in Extension Register XR6E) while viewing the display, the FRC algorithm can be adjusted to match the persistence of the particular panel without increasing the panel's vertical refresh rate. With this technique, the 65540 / 545 produces up to 61 flicker-free gray scales on the latest fast response "mouse quick" film-compensated monochrome STN LCDs. The alternate method of reducing flicker -- increasing the panel's vertical Revision 1.2 SmartMapTM compares and adjusts foreground and background grayscale values to produce adequate display contrast on flat panel displays. The minimum contrast value and the foreground / background grayscale adjustment values are programmed in the 65540 / 545's Extension Registers. This feature can be disabled if desired. 14 65540 / 545 (R) Introduction / Overview Text Enhancement The 65540 / 545 implements the Tall FontTM scheme so that there are very few blank lines on the flat panel in text modes. For example, using an 8x19 Tall FontTM would fill 475 lines on a 480-line panel in VGA mode 3. Lines 1, 9, 12 of the 16 line font may be replicated to generate the 8x19 font. Alternately, line 0 may be replicated twice and line 15 replicated once. The Tall FontTM scheme is implemented in hardware thereby avoiding any compatibility issues. Text Enhancement is another feature of the 65540 / 545 that improves image quality on flat panel displays. When enabled, the Text Enhancement feature displays Dim White as Bright White, thereby optimizing the contrast level on flat panels. Text Enhancement can be enabled and disabled by changing a bit in one of the Extension Registers. Vertical & Horizontal Compensation Each of these Vertical Compensation techniques can be controlled by programming the Extension Registers. Each Vertical Compensation feature can be individually disabled, enabled, and adjusted. A combination of Vertical Compensation features can be used by adjusting the features' priority order. For example, text mode vertical compensation consists of four priority order options: Vertical & Horizontal Compensation are programmable features that adjust the display to completely fill the flat panel display. Vertical Compensation increases the useable display area when running lower resolution software on a higher resolution panel. Unlike CRT monitors, flat panels have a fixed number of scan lines (e.g., 200, 400, 480 or 768 lines). Lower resolution software displayed on a higher resolution panel only partially fills the useable display area. For instance, 350-line EGA software displayed on a 480-line panel would leave 130 blank lines at the bottom of the display and 400-line VGA text or Mode 13 images would leave 80 blank lines at the bottom. The 65540 / 545 offers the following Vertical Compensation techniques to increase the useable screen area: n n n n Vertical Centering displays text or graphics images in the center of the flat panel, with a border of unused area at the top and bottom of the display. Automatic Vertical Centering automatically adjusts the Display Start address such that the unused area at the top of the display equals the unused area at the bottom. Non-Automatic Vertical Centering enables the Display Start address to be set (by programming the Extension Registers) such that text or graphics images can be positioned anywhere on the display. Text and graphics modes offer two Line Replication priority order options: n n Double Scanning+ Line Replication, Double Scanning, Line Replication Double Scanning+ Line Replication, Line Replication, Double Scanning Horizontal Compensation techniques include Horizontal Compression, Horizontal Centering, and Horizontal Doubling. Horizontal Compression will compress 9-dot text to 8-dots such that 720-dot text in Hercules modes will fit on a 640-dot panel. Automatic Horizontal Centering automatically centers the display on a larger resolution panel such that the unused area at the left of the display equals the unused area at the right. Non-Automatic Horizontal Centering enables the left border to be set (by programming the Horizontal Centering Extension Register) such that the image can be positioned anywhere on the display. Automatic Horizontal Doubling will automatically double the display in the horizontal direction when the horizontal display width is equal to or less than half of the horizontal panel size. Line replication (referred to as "stretching") duplicates every Nth display line (where N is programmable), thus stretching text characters and graphic images an adjustable amount. The display can be stretched to completely fill the flat panel area. Double scanning, a form of line replication where every line is replicated, is useful for running 200-line software on a 400-line panel or 480-line software on a 1024-line panel. Blank line insertion, inserts N lines (where N is programmable) between each line of text characters. Thus text can be evenly spaced to fill the entire panel display area without altering the height and shape of the text characters. Blank line insertion can be used in text mode only. Revision 1.2 Double Scanning+Line Insertion, Double Scanning, Line Insertion Double Scanning+Line Insertion, Line Insertion, Double Scanning Double Scanning+Tall Fonts, Double Scanning, Tall Fonts Double Scanning+Tall Fonts, Tall Fonts, Double Scanning 15 65540 / 545 (R) Subject to change without notice Introduction / Overview ADVANCED POWER MANAGEMENT CRT Power Management (DPMS) Normal Operating Mode The 65540 / 545 supports the VESA DPMS (Display Power Management Signaling) protocol. This includes the ability to independently stop HSYNC and/or VSYNC and hold them at a static level to signal the CRT to enter various powersaving states. Additionally, the RAMDAC may be powered down and the clock frequencies lowered for further power savings. The 65540 / 545 is a full-custom, sub-micron CMOS integrated circuit optimized for low power consumption during normal operation. The 65540 / 545 provides CAS-before-RAS refresh cycles for the DRAM display memory. The 65540 / 545 provides "mixed" 3.3V and 5.0V operation by providing dedicated Vcc pins for the 65540 / 545's internal logic, bus interface, memory interface, and display interface. If the 65540 / 545 internal logic operates at 3.3V, the memory, bus, and panel interfaces can independently operate at either 3.3V or 5.0V. The clock Vcc must be the same as the Vcc of the internal logic. The 65540 / 545 provides direct interface to 386/486 local bus which conserves power when 3.3V microprocessors are used. A flexible clock synthesizer is used to generate independent memory and video clocks. The 65540 / 545's performance-enhancement features minimize the memory clock frequency (and thus power consumption) required to achieve a given performance level. The 65540 / 545's proprietary gray scaling algorithm produces a flicker-free display with a minimum video clock and panel vertical refresh rate. (Note: the power consumption of the controller increases linearly with video clock frequency). Mixed 3.3V and 5.0V Operation The 65540 supports operation at either 5.0V 10% or 3.3V 0.3V. The 65540 also provides "mixed" 5V and 3.3V operation by providing dedicated Vcc pins for the 65540's internal logic, bus interface, memory interface, and display interface. Each dedicated Vcc can be either 5V or 3.3V, such that the 65540 internal logic operates at 3.3V and the various interfaces at either 3.3V or 5V. The clock VCC must be the same as the Vcc of the internal logic. The following table shows the relationship between the VCC inputs to the 65540 and the interface pins controlled by each Vcc input. Vcc Pins Interface Pins Affected 80, 181 Internal Logic -9, 42 Bus 1-54, 178-201, 207 158 Memory A 145-177 142 Memory B 123-144 108 Memory C 90-122 66 Display 61-89 205, 206 Clock* 203, 204 59 DAC 55,57,58,60 * Must be same as the Vcc of the internal logic. Panel Off Mode In 'Panel Off' mode, the 65540 / 545 turns off both the flat panel and CRT interface logic. The VGA subsystem remains active, such that the CPU can read/write display memory and I/O registers. The 65540 / 545's video clock can be reduced significantly, saving power. Panel Off mode is activated by programming Extended Register XR52 bit-3=1. The 65545B1/B2 and 65545B1-5/B2-5 are the same part (die) that has been tested for operation at different voltage requirements. Standby Mode The 65545B1/B2 provides a dedicated Vcc (Voltage) pins for the internal logic, clock synthesizer, bus interface, memory interface and the display interface. Each dedicated Vcc can be either 5V or 3.3V independently except for the internal core and clock synthesizer which must be at the same voltage level. In 'Standby' mode, the 65540 / 545 suspends all CPU, memory and display activities. The 65540 / 545 places the DRAM in its self-refresh mode of operation, and the 65540 / 545's clock can be shut off. The VGA subsystem dissipates a minimum amount of power during Standby. Since the 65540 / 545 is a fully static device, the contents of the controller's registers and on-chip palette are maintained during Standby. Therefore, Standby mode provides fast Suspend / Resume modes. The Standby mode may be activated by forcing the STNDBY# pin low or programming XR52 bit-4 to '1'. The state of all 65540 / 545 pins during Standby mode is summarized in the tables on the following page. Revision 1.2 The 65545B1-5/B2-5 limits the internal core and clock synthesizer Vcc to 5V only operation and meets all 5V data sheet requirements. 16 65540 / 545 (R) Introduction / Overview CPU ACTIVITY INDICATOR / TIMER Panel Interface Registers The 65540 / 545 provides an output pin called ACTI (pin 53) to facilitate an orderly power-down sequence. The ACTI output is an active high signal which is driven high every time a valid VGA memory read/write operation or VGA I/O read/write operation is executed by the CPU. This signal may be used by power management circuitry to put the 65540 / 545 in Panel Off or Standby power down modes. The 65540 / 545 may also evoke its own low power operation by using the activity timer which monitors the ACTI signal. The activity timer will either disable the backlight or evoke Panel Off mode after a specified time interval. This time interval is programmed in 30 second intervals via Extension Register XR5C. Flat Panel Interface characteristics are controlled by a subset of the Extension Registers. These Registers select the panel type, data formatting, panel configuration, panel size, clock selection and video polarity. Since the 65540 / 545 is designed to support a wide range of panel types and sizes, the control of these features is fully programmable. The video polarity of text and graphics modes is independently selectable to allow black text on a white background and still provide normal graphics images. Alternate Panel Timing Registers Flat panel displays usually require sync signal timing that is different from a CRT. To provide full compatibility with the IBM VGA standard, alternate timing registers are used to allow independent timing of the sync signals for flat panel displays. Unlike the values programmed into the standard CRT timing registers, the value programmed into the alternate timing registers is dependent on the panel type used and is independent of the display mode. FULL COMPATIBILITY The 65540 / 545 is fully compatible with the IBMTM VGA standard at the hardware, register, and BIOS level. The 65540 / 545 also provides enhanced backward compatibility to EGATM and CGATM standards without using NMIs. These controllers include a variety of features to provide compatibility on flat panel displays in addition to CRT monitors. Internal compensation techniques ensure that industry-standard software designed for different displays can be executed on the single flat panel used in an implementation. Mode initialization is supported at the BIOS and register levels, ensuring compatibility with all application software. Context Switching For support of multi-tasking, windowing, and context switching, the entire state of the 65540 / 545 (internal registers) is readable and writable. This feature is fully compatible with IBM's VGA. Additional registers are provided to allow read back of internal latches not readable in the IBM VGA. Write Protection The 65540 / 545 has the ability to write protect most of the standard VGA registers. This feature is used to provide backwards compatibility with software written for older generation display types. The write protection is grouped into register sets and controlled by the Write Protect Register (XR15). Extension Registers The 65540 / 545 employs an "Extension" Register set to control its enhanced features. These Extension Registers provide control of the flat panel interface, flat panel timing, vertical compensation, SMARTMAPTM, and Backwards Compatibility. These registers are always accessible as an index/data register set at port addresses 3D6-3D7h. None of the unused bits in the regular VGA registers are used for extensions. Revision 1.2 17 65540 / 545 (R) Introduction / Overview RESET, SETUP, AND TEST MODES low (MAD0 pin 162). The 65540 / 545 will exit Tri-State mode with the enabling memory data pin (MAD0) high or RESET# low. Reset Mode When this mode is activated by pulling the RESET# pin low, the 65540 / 545 is forced to VGA-compatible mode and the CRT is selected as the active display. In addition, the 65540 / 545 is disabled; it must be enabled after deactivating the RESET# pin by writing to the Global Enable Register (102h in Setup Mode for ISA bus configurations or to port 3C3h or Local Bus configurations). Access to all Extension Registers is always enabled after reset (at 3D6/3D7h). The RESET# pin must be active for at least 64 clock cycles. ICT (In-Circuit Test) Mode In this mode, all digital pins of the 65540 / 545 chip may be tested individually to determine if they are properly connected (the analog RGB and RESET# pins cannot be tested in ICT mode). The 65540 / 545 will enter ICT mode if it sees a rising edge on XTALI during RESET with one of the display memory data pins pulled low (a different pin from the one used to enable Tri-state mode: MAD1). In ICT mode, all digital signal pins become inputs which are part of a long path starting at ENAVDD (pin 62) and proceeding to lower pin numbers around the chip to pin 1 (except analog pins 55, 57, 58, and 60) then to pin 208 and ending at VSYNC (pin 64). If all pins in the path are high, the VSYNC output will be high. If any pin is low, the VSYNC output will be low. Thus the chip can be checked in circuit to determine if all pins are connected properly by toggling all pins one at a time (XTALI last) and observing the effect on VSYNC. XTALI must be toggled last because rising edges on XTALI with either of the enabling memory data pins high or RESET# low will exit ICT mode. As a side effect, ICT mode effectively Tri-States all pins except VSYNC. Setup Mode In this mode, only the Global Enable register is accessible. In IBM-compatible PC implementations, setup mode is entered by writing a 1 to bit-4 of port 46E8h. This port is incorporated in the 65540 / 545. While in Setup mode, the video output is active if it was active prior to entering Setup mode and inactive if it was inactive prior to entering Setup mode. After power up, video BIOS can optionally disable the video 46E8 or 3C3 registers (via XR70) for compatibility in case other non-IBM-compatible peripheral devices use those ports. Tri-State Mode In this mode, all output pins of the 65540 / 545 chip may be disabled for testing of circuitry external to the chip. The 65540 / 545 will enter Tri-State mode if it sees a rising edge on XTALI during RESET with one of the display memory data pins pulled Mode of Operation Reset Setup Test Standby Panel-Off RESET# Pin Low --------High High STNDBY# Pin xxx --------Low High Display Memory Access ----No No No Yes Video Output ----Yes Yes No No It is illegal to go from Panel-Off Mode to Standby Mode. Panel-Off Mode must be exited first and a delay must occur of twice the value programmed into XR5B[7-4] prior to entering Standby Mode. In 65540 ES Silicon reset is active high (RESET); in all following revisions reset is active low (RESET#). Reset / Setup / Test / Standby / Panel-Off Mode Summary Revision 1.2 18 65540 / 545 (R) Introduction / Overview graphic modes the 4-bit pixel data acts as an index into a set of 16 internal color look-up registers which generate a 6-bit color value. Two additional bits of color data are added to provide an 8-bit address to the VGA color palette. In 256-color modes, two 4-bit values may be passed through the color look-up registers and assembled into one 8-bit video data value. In high-resolution 256-color modes, an 8-bit video data value may be provided directly, bypassing the attribute controller color lookup registers. Text and cursor blink, underline and horizontal scrolling are also the responsibility of the Attribute Controller. CHIP ARCHITECTURE The 65540 / 545 integrates six major internal modules: Sequencer The Sequencer generates all CPU and display memory timing. It controls CPU access of display memory by inserting cycles dedicated to CPU access. It also contains mask registers which can prevent writes to individual display memory planes. CRT Controller The CRT Controller generates all the sync and timing signals for the display and also generates the multiplexed row and column addresses used for both display refresh and CPU access of display memory. VGA / Color Palette DAC The 65540 / 545 integrates a VGA compatible triple 6-bit Color Lookup Table (sometimes referred to as a "CLUT" or just "LUT") and high speed 6/8-bit DACs. Additionally true color bypass modes are supported displaying color depths of up to 24bpp (8-red, 8-green, 8-blue). The palette DAC can switch between true color data and LUT data on a pixel by pixel basis. Thus, video overlays may be any arbitrary shape and can lie on any pixel boundary. The hardware cursor is also a true color bitmap which may overlay on any pixel boundary. Graphics Controller The Graphics Controller interfaces the 8, 16, or 32bit CPU data bus to the 32-bit internal data bus used by the four planes (Maps) of display memory. It also latches and supplies display memory data to the Attribute Controller for use in refreshing the screen image. For text modes this data is supplied in parallel form (character generator data and attribute code); for graphics modes it is converted to serial form (one bit from each of four bytes form a single pixel). The Graphics Controller can also perform any one of several types of logical operations on data while reading it from or writing it to display memory or the CPU data bus. The internal palette DAC register I/O addresses and functionality are 100% compatible with the VGA standard. In all bus interfaces the palette DAC automatically controls accesses to its registers to avoid data overrun. This is handled by holding RDY in the ISA configuration and by delaying RDY# for VL-Bus and local bus interfaces. Attribute Controller Extended RAMDAC display modes are selected in the Palette Control Register (XR06). Two 16bpp formats are supported: 5-red, 5-green, 5-blue Targa format and 5-red, 6-green, 5-blue XGA format. The internal Palette / DAC may also be disabled via the Palette Control Register (XR06). The Attribute Controller generates the 4-bit-wide video data stream used to refresh the display. This is created in text modes from a font pattern and an attribute code which pass through a parallel to serial conversion. In graphics modes, the display memory contains the 4-bit pixel data. In text and 16 color 24 RGB5-6-5ExternalVideo HighColorPixelData Red Green Blue LUTPixelData 8 Triple6-bit LUT 18 Color Palette / DAC Internal Block Diagram Revision 1.2 19 65540 / 545 (R) Introduction / Overview Clock Synthesizers Integrated clock synthesizers support all pixel clock (VCLK) and memory clock (MCLK) frequencies which may be required by the 65540 / 545. Each of the two clock synthesizers may be programmed to output frequencies ranging between 1MHz and the maximum specified operating frequency for that clock in increments not exceeding 0.5%. The frequencies are set via a programmable 18-bit divisor value which contains fields for Phase Lock Loop (PLL), Voltage Controlled Oscillator (VCO) and Pre/Post Divide Control. A block diagram showing the clock synthesizer registers is included below. Refer to the Functional Description section of this document for additional information. VCLKRegisterTable VGA CLK0 = 25.175MHz VGA CLK1 = 28.322MHz 21 VCLK Synthesizer CLK2 = Programmable XR32:30 MCLKRegisterTable MCLK = Programmable CLKSEL1:0 21 MCLK Synthesizer MISC Output Reg[3:2] Clock Synthesizer Register Diagram Revision 1.2 20 65540 / 545 (R) Introduction / Overview read a selected bit from the 'virtual switch register' (an extension register set up by BIOS at initialization time) instead of reading the state of the internal comparator output. CONFIGURATION INPUTS The 65540 / 545 can read up to nine configuration bits. These signals are sampled on memory address bus AA0-AA8 on the trailing edge of Reset. The 65540 / 545 implements pull-up resistors on-chip on all configuration input pins. If the user wishes to force a certain option, then a 4.7K ohm resistor may be used to pull-down the desired configuration pin. 65540 / 545 Pin # Signal Active 145 146 147 148 149 150 151 152 153 LIGHT PEN REGISTERS In the CGA and Hercules modes, the contents of the Display Address counter are saved at the end of the frame before being reset. The saved value can be read in the CRT Controller Register space at indices 10h and 11h. This allows simulation of a light pen hit in CGA and Hercules modes. Functionality LB# Low Bus Configuration ISA# Low Bus Configuration 2X# Low 2xCPU Clock Select -- Low Reserved -- Low Reserved (Do Not Use) OS# Low External Oscillator Select AD# Low ENABKL/ACTI=A26,A27 TS# Low Test Mode Enable LV# Low Low Voltage Select 2X# (AA2) Pin 147 ISA# (AA1) Pin 146 Low Low Low Low High High High High Low Low High High Low Low High High LB# (AA0) Pin 145 BIOS ROM INTERFACE In typical ISA bus and VL-Bus applications, the 65540 / 545 is placed on the motherboard and the video BIOS is integrated with the system BIOS (in PCI Bus, the video BIOS is always included in the system BIOS). A separate signal (ROMCS#) is generated on the A24 pin for ISA bus or may be created external to the 65540 / 545 for implementing a separate external ROM BIOS. Bus Functionality Typically, an 8-bit BIOS is implemented with one external ROM chip. A 16-bit dedicated video BIOS ROM could be implemented with the 65540 / 545 if required using two BIOS ROM chips, an external PAL, and a 74LS244 buffer. However, a higherperformance and lower-cost video system will result from implementation of the video BIOS as either an 8-bit dedicated video BIOS ROM or as part of the system BIOS and having the video BIOS be copied into system RAM by the system BIOS on startup. Low Reserved High Reserved Low Reserved High 32-bit CPU Bus (2x clk) Low Reserved High 16-bit ISA Bus Low PCI Bus (65545 only) High 32-bit VL-Bus (1x clk) AA2 determines the CPU clock rate for purposes of local bus implementation (0=2x CPU clock, 1=1x CPU clock). AA3 has no hardware function, but the status of the pin is latched in extension register 1 bit 3 on reset so it may be used to input systemspecific information. AA4 is reserved and should be sampled high on reset. AA5, if forced to 0, indicates that a reference frequency of 14.31818 MHz must be input on XTALI (pin 203). AA6 selects between ACTI/ENABKL and A26-27 on pins 53-54 (default is ENABKL and ACTI). AA7, when forced low, enables clock test mode (VCLK and MCLK are output on A24-25 (pins 29-30). AA8, when forced low, selects 3.3V level of operation for the internal logic and the clock core. Chips and Technologies, Inc. supplies a video BIOS that is optimized for the 65540 / 545 hardware. The BIOS supports the extended functions of the 65540 / 545, such as switching between the flat panel and the CRT, SMARTMAPTM, Vertical Compensation, and palette load/save. The BIOS Modification Program (BMP) enables OEMs to tailor their feature set by programming the extended functions. CHIPS offers the BIOS as a standard production version, a customized version, or as source code. PACKAGE The 65540 / 545 is available in a EIAJ-standard 208-pin plastic flat pack with a 28 x 28 mm body size and 0.5 mm (19.7 mil) lead pitch. VIRTUAL SWITCH REGISTER The 65540 / 545 implements a 'virtual switch register'. In 'EGA' mode, the sense bit of the Feature control register (3C2 bit 4) may be set up to Revision 1.2 21 65540 / 545 (R) Introduction / Overview APPLICATION SCHEMATIC EXAMPLES This document includes application schematic examples of the following: 1. Bus Interface - 16-bit EISA/ISA Bus Bus Interface - 32-bit 486 Local Bus (1x Clock) Bus Interface - 32-bit VL-Bus (1x Clock) Bus Interface - 32-bit PCI Bus 2. Display Memory Interface 3. CRT / Panel Interface 4. PC Video Interface Revision 1.2 22 65540 / 545 (R) DRAM"B" DisplayMemoryUpper512KB RASA# OEAB# AA9 (VR0) AA8 (CFG8) AA7 (CFG7) AA6 (CFG6) AA5 (CFG5) AA4 (CFG4) AA3 (CFG3) AA2 (CFG2) AA1 (CFG1) AA0 (CFG0) MBD15 MBD14 MVCCB MBD13 MBD12 MGNDB MBD11 MBD10 MBD9 MBD8 MBD7 MBD6 MBD5 MBD4 MBD3 MBD2 MBD1 MBD0 CASBL# CASBH# WEB# RASB# MCD15 (VR5) MCD14 (VR4) MCD13 (VR3) MCD12 (VR2) MCD11 (VG7) MCD10 (VG6) MCD9 (VG5) MCD8 (VG4) MCD7 (VG3) MCD6 (VG2) MCD5 (VB7) MCD4 (VB6) MCD3 (VB5) MCD2 (VB4) MVCCC MCD1 (VB3) MCD0 (VB2) MGNDC (LV#) (TS#) (AD#) (OS#) (2X#) (ISA#) (LB#) Pin Diagram DRAM"A" DisplayMemory Lower512KB DRAM"C" FrameBuffer or 24-Bit PC-Video Interface 156 155 (32KHZ) 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 (WEBL#) 126 (CASB#) 125 (WEBH#) 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 10/30/95 Panel 80 Interface 79 78 Group 77 76 Pin names shown indicate VL-Bus connections (Default) 75 Pin names in brackets <...> indicate ISA-Bus connections (ISA# = 0) 74 Pin names in parentheses indicate alternate functions 73 72 71 70 (DE)(BLANK#) 69 (DE)(BLANK#) 68 67 66 65 64 63 62 (ENABKL) 61 60 DAC 59 58 Group 57 56 55 54 53 Configuration Pins 2X# = 0 2X LCLK OS# = 0 External Oscillator (1=Xtal) AD# = 0 ENABKL & ACTI are A26,A27 TS# = 0 Enable Clock Test Mode LV# = 0 Input Threshold Level Control 65540 (WECL#) (VR6) (CASC#) (VR7) (WECH#) (PCLK) (KEY) (VR1) (VG0) (VG1) (P23) (P22) (P21) (P20) (P19) (P18) (P17) (P16) <A0> <D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0> <D9> <D8> <IORD#> <LA23> <ROMCS#> (VCLKOUT) <IRQ> (MCLKOUT) <AEN> <BHE#> <D15> <D14> <D13> <D12> <D11> <D10> <A6> <A7> <A8> <A9> <A10> <A11> <A12> <A13> <A14> <A15> <A16> <LA17> <LA18> <LA19> <LA20> <LA21> <LA22> <reserved> <reserved> <reserved> <reserved> <reserved> <IOCS16#> <MCS16#> <ZWS#> <A1> <ALE> <MEMW#> (CRESET) <RDY> <IOWR#> <A4> <A5> <RFSH#> <MEMR#> Flat Panel VGA Controller <A2> <A3> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 CASCL# CASCH# WEC# RASC# OEC# CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 DGND P15 P14 P13 P12 P11 P10 P9 P8 IVCC P7 P6 IGND P5 P4 P3 P2 P1 P0 SHFCLK M LP FLM DVCC HSYNC VSYNC DGND ENAVDD ENAVEE RED AVCC GREEN BLUE AGND RSET ENABKL ACTI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 WEA# MVCCA (CASA#) CASAH# (WEAL#) CASAL# MGNDA (TSENA#) MAD0 (ICTENA#) MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 STNDBY# A2 A3 IVCC A4 A5 IGND A6 A7 Bus A8 Interface A9 A10 Group A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 CGND0 XTALI Clock XTALO Group CVCC0 CVCC1 RESET# CGND1 [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] (WEAH#) [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] D31 D30 D29 D28 D27 D26 D25 D24 BVCC BE3# W/R# BGND D23 D22 D21 D20 D19 D18 D17 D16 BE2# ADS# RDYRTN# LRDY# LDEV# BGND LCLK A23 A24 A25 M/IO# BE1# D15 D14 D13 D12 D11 D10 BGND D9 D8 BVCC BE0# D7 D6 D5 D4 D3 D2 D1 D0 BGND [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] Bus Interface Group ENABKL = (GPIO) (A27) (VB1) ACTI = (GPIO) (A26) (VB0) In 2x clock mode, pin 23 becomes CRESET instead of RDYRTN# In Test mode, pin 29 becomes VCLKOUT and pin 30 becomes MCLKOUT In 65540 ES Silicon reset is active high (RESET); in all following revisions reset is active low (RESET#). Revision 1.2 23 65540 / 545 (R) DRAM"B" DisplayMemoryUpper512KB RASA# OEAB# AA9 (VR0) AA8 (CFG8) AA7 (CFG7) AA6 (CFG6) AA5 (CFG5) AA4 (CFG4) AA3 (CFG3) AA2 (CFG2) AA1 (CFG1) AA0 (CFG0) MBD15 MBD14 MVCCB MBD13 MBD12 MGNDB MBD11 MBD10 MBD9 MBD8 MBD7 MBD6 MBD5 MBD4 MBD3 MBD2 MBD1 MBD0 CASBL# CASBH# WEB# RASB# MCD15 (VR5) MCD14 (VR4) MCD13 (VR3) MCD12 (VR2) MCD11 (VG7) MCD10 (VG6) MCD9 (VG5) MCD8 (VG4) MCD7 (VG3) MCD6 (VG2) MCD5 (VB7) MCD4 (VB6) MCD3 (VB5) MCD2 (VB4) MVCCC MCD1 (VB3) MCD0 (VB2) MGNDC (LV#) (TS#) (AD#) (OS#) (2X#) (ISA#) (LB#) Pin Diagram DRAM"A" DisplayMemory Lower512KB DRAM"C" FrameBuffer or 24-Bit PC-Video Interface 156 155 (32KHZ) 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 (WEBL#) 126 (CASB#) 125 (WEBH#) 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 Panel 82 81 10/30/95 Interface 80 Group 79 78 77 shown indicate VL-Bus connections (Default) 76 in brackets <...> indicate ISA-Bus connections (ISA# = 0) 75 74 in quotes "..." indicate PCI-Bus connections (LB# = 0) 73 in parentheses indicate alternate functions 72 71 70 (DE)(BLANK#) 69 (DE)(BLANK#) 68 67 66 65 64 63 62 (ENABKL) 61 60 DAC 59 Group 58 57 56 55 54 53 Configuration Pins 2X# = 0 2X LCLK OS# = 0 External Oscillator (1=Xtal) AD# = 0 ENABKL & ACTI are A26,A27 TS# = 0 Enable Clock Test Mode LV# = 0 Input Threshold Level Control 65545 (WECL#) (VR6) (CASC#) (VR7) (WECH#) (PCLK) (KEY) (VR1) (VG0) (VG1) (P23) (P22) (P21) (P20) (P19) (P18) (P17) (P16) <A0> <D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0> <IORD#> <LA23> <ROMCS#> <IRQ> <AEN> <BHE#> <D15> <D14> <D13> <D12> <D11> <D10> (CRESET) names names names names <reserved> <reserved> <reserved> <reserved> <reserved> <IOCS16#> <MCS16#> <ZWS#> <A1> <ALE> <MEMW#> <RDY> <IOWR#> Pin Pin Pin Pin <RFSH#> <MEMR#> <A6> <A7> <A8> <A9> <A10> <A11> <A12> <A13> <A14> <A15> <A16> <LA17> <LA18> <LA19> <LA20> <LA21> <LA22> <D9> <D8> <A4> <A5> (VCLKOUT) (MCLKOUT) Flat Panel VGA Controller <A2> <A3> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 CASCL# CASCH# WEC# RASC# OEC# CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 DGND P15 P14 P13 P12 P11 P10 P9 P8 IVCC P7 P6 IGND P5 P4 P3 P2 P1 P0 SHFCLK M LP FLM DVCC HSYNC VSYNC DGND ENAVDD ENAVEE RED AVCC GREEN BLUE AGND RSET ENABKL ACTI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 WEA# MVCCA (CASA#) CASAH# (WEAL#) CASAL# MGNDA (TSENA#) MAD0 (ICTENA#) MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 STNDBY# "reserved" A2 "reserved" A3 IVCC "reserved" A4 "reserved" A5 IGND "reserved" A6 "reserved" A7 "reserved" A8 "reserved" A9 "reserved" A10 "reserved" A11 "reserved" A12 "reserved" A13 "reserved" A14 "reserved" A15 "reserved" A16 "reserved" A17 "reserved" A18 "reserved" A19 "reserved" A20 "reserved" A21 "CLK" A22 CGND0 Clock XTALI XTALO Group CVCC0 CVCC1 RESET# CGND1 [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] (WEAH#) [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] "AD31" "AD30" "AD29" "AD28" "AD27" "AD26" "AD25" "AD24" D31 D30 D29 D28 D27 D26 D25 D24 BVCC "C/BE3#" BE3# "IDSEL" W/R# BGND "AD23" D23 "AD22" D22 "AD21" D21 "AD20" D20 "AD19" D19 "AD18" D18 "AD17" D17 "AD16" D16 "C/BE2#" BE2# "FRAME#" ADS# "IRDY#" RDYRTN# "TRDY#" LRDY# "DEVSEL#" LDEV# BGND "STOP#" LCLK "reserved" A23 "PERR#" A24 "SERR#" A25 "PAR" M/IO# "C/BE1#" BE1# "AD15" D15 "AD14" D14 "AD13" D13 "AD12" D12 "AD11" D11 "AD10" D10 BGND "AD9" D9 "AD8" D8 BVCC "C/BE0#" BE0# "AD7" D7 "AD6" D6 "AD5" D5 "AD4" D4 "AD3" D3 "AD2" D2 "AD1" D1 "AD0" D0 BGND [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] Bus Interface Group ACTI = (GPIO) (A26) (VB0) ENABKL = (GPIO) (A27) (VB1) In 2x clock mode, pin 23 becomes CRESET instead of RDYRTN# In Test mode, pin 29 becomes VCLKOUT and pin 30 becomes MCLKOUT Revision 1.2 24 65540 / 545 (R) Pin List Pin Name A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 (LA17) A18 (LA18) A19 (LA19) A20 (LA20) A21 (LA21) A22 (LA22) "CLK" A23 (LA23) A24 (ROMCS#) "PERR#" A25 (IRQ) "SERR#" AA0 (CFG0) (LB#) AA1 (CFG1) (ISA#) AA2 (CFG2) (2X#) AA3 (CFG3) AA4 (CFG4) AA5 (CFG5) (OS#) AA6 (CFG6) (AD#) AA7 (CFG7) (TS#) AA8 (CFG8) (LV#) AA9 (32KHZ) (VR0) ACTI (A26) (VB0) ADS# (ALE) "FRAME#" AGND AVCC BE0# (A0) "C/BE0#" BE1# (BHE#) "C/BE1#" BE2# (A1) "C/BE2#" BE3# (RFSH#) "C/BE3#" BLUE BGND (Bus) BGND (Bus) BGND (Bus) BGND (Bus) BVCC (Bus) BVCC (Bus) CA0 (P16) CA1 (P17) CA2 (P18) CA3 (P19) CA4 (P20) CA5 (P21) CA6 (P22) CA7 (P23) CA8 (VG1) CA9 (VG0) CASAH# (CASA#) CASAL# (WEAL#) CASBH# (CASB#) CASBL# (WEBL#) CASCH# (CASC#) (VR7) CASCL# (WECL#) (VR6) CGND0 (Clock) CGND1 (Clock) CVCC0 (Clock) CVCC1 (Clock) Note: Drive = 5V low drive Revision 1.2 Pin # Dir Drive Pin Name Pin # 179 In -- D0 "AD0" 51 180 In -- D1 "AD1" 50 182 In -- D2 "AD2" 49 183 In -- D3 "AD3" 48 185 In -- D4 "AD4" 47 186 In -- D5 "AD5" 46 187 In -- D6 "AD6" 45 188 In -- D7 "AD7" 44 189 In -- D8 "AD8" 41 190 In -- D9 "AD9" 40 191 In -- D10 "AD10" 38 192 In -- D11 "AD11" 37 193 In -- D12 "AD12" 36 194 In -- D13 "AD13" 35 195 In -- D14 "AD14" 34 196 In -- D15 "AD15" 33 197 In -- D16 (ZWS#) "AD16" 20 198 In -- D17 (MCS16#) "AD17" 19 199 In -- D18 (IOCS16#) "AD18" 18 200 In -- D19 "AD19" 17 201 In -- D20 "AD20" 16 28 In -- D21 "AD21" 15 29 I/O 8mA D22 "AD22" 14 30 I/O 8mA D23 "AD23" 13 145 I/O 4mA D24 "AD24" 8 146 I/O 4mA D25 "AD25" 7 147 I/O 4mA D26 "AD26" 6 148 I/O 4mA D27 "AD27" 5 149 I/O 4mA D28 "AD28" 4 150 I/O 4mA D29 "AD29" 3 151 I/O 4mA D30 "AD30" 2 152 I/O 4mA D31 "AD31" 1 153 I/O 4mA DGND (Display) 63 154 I/O 4mA DGND (Display) 89 53 I/O 8mA DVCC (Display) 66 22 In -- ENABKL(A27) (VB1) 54 56 -- -- ENAVDD 62 59 -- -- ENAVEE(ENABKL) 61 43 In -- FLM 67 32 In -- GREEN 58 21 In -- HSYNC 65 10 In -- IGND (Internal Logic) 77 57 Out -- IGND (Internal Logic) 184 12 -- -- IVCC (Internal Logic) 80 26 -- -- IVCC (Internal Logic) 181 39 -- -- LCLK (IORD#) "STOP#" 27 52 -- -- LDEV# (IOWR#) "DEVSEL#" 25 9 -- -- LRDY# (RDY) "TRDY#" 24 42 -- -- LP (BLANK#) (DE) 68 90 Out 4mA M (BLANK#) (DE) 69 91 Out 4mA MAD0 (TSENA#) 162 92 Out 4mA MAD1 (ICTENA#) 163 93 Out 4mA MAD2 164 94 Out 4mA MAD3 165 95 Out 4mA MAD4 166 96 Out 4mA MAD5 167 97 Out 4mA MAD6 168 98 I/O 4mA MAD7 169 99 I/O 4mA MAD8 170 159 Out 4mA MAD9 171 160 Out 4mA MAD10 172 125 Out 4mA MAD11 173 126 Out 4mA MAD12 174 103 I/O 4mA MAD13 175 104 I/O 4mA MAD14 176 202 -- -- MAD15 177 208 -- -- MBD0 127 205 -- -- MBD1 128 206 -- -- MBD2 129 and 3V high drive.MBD3 130 25 Dir I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O -- -- -- I/O Out Out Out Out Out -- -- -- -- In I/O Out Out Out I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Drive 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA -- -- -- 8mA 8mA 8mA 8mA -- 12mA -- -- -- -- -- 12mA 12mA 8mA 8mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA Pin Name Pin # Dir Drive MBD4 131 I/O 2mA MBD5 132 I/O 2mA MBD6 133 I/O 2mA MBD7 134 I/O 2mA MBD8 135 I/O 2mA MBD9 136 I/O 2mA MBD10 137 I/O 2mA MBD11 138 I/O 2mA MBD12 140 I/O 2mA MBD13 141 I/O 2mA MBD14 143 I/O 2mA MBD15 144 I/O 2mA MCD0 (VB2) 106 I/O 2mA MCD1 (VB3) 107 I/O 2mA MCD2 (VB4) 109 I/O 2mA MCD3 (VB5) 110 I/O 2mA MCD4 (VB6) 111 I/O 2mA MCD5 (VB7) 112 I/O 2mA MCD6 (VG2) 113 I/O 2mA MCD7 (VG3) 114 I/O 2mA MCD8 (VG4) 115 I/O 2mA MCD9 (VG5) 116 I/O 2mA MCD10 (VG6) 117 I/O 2mA MCD11 (VG7) 118 I/O 2mA MCD12 (VR2) 119 I/O 2mA MCD13 (VR3) 120 I/O 2mA MCD14 (VR4) 121 I/O 2mA MCD15 (VR5) 122 I/O 2mA MGNDA (Memory A) 161 -- -- MGNDB (Memory B) 139 -- -- MGNDC (Memory C) 105 -- -- M/IO# (AEN) "PAR" 31 I/O 4mA MVCCA (Memory A) 158 -- -- MVCCB (Memory B) 142 -- -- MVCCC (Memory C) 108 -- -- OEAB# 155 Out 4mA OEC# (VR1) 100 I/O 4mA P0 71 Out 8mA P1 72 Out 8mA P2 73 Out 8mA P3 74 Out 8mA P4 75 Out 8mA P5 76 Out 8mA P6 78 Out 8mA P7 79 Out 8mA P8 81 Out 8mA P9 82 Out 8mA P10 83 Out 8mA P11 84 Out 8mA P12 85 Out 8mA P13 86 Out 8mA P14 87 Out 8mA P15 88 Out 8mA RASA# 156 Out 4mA RASB# 123 Out 4mA RASC# (KEY) 101 I/O 4mA RRTN#<MEMW#>"IRDY#" 23 In -- RED 60 Out -- RESET# (540 Rev 0=RESET) 207 In -- RSET 55 In -- SHFCLK 70 Out 8mA STNDBY# 178 In -- VSYNC 64 Out 12mA WEA# (WEAH#) 157 Out 4mA WEB# (WEBH#) 124 Out 4mA WEC# (WECH#)(PCLK) 102 Out 4mA W/R# (MEMR#) "IDSEL" 11 In -- XTALI 203 In -- XTALO 204 Out -- I/O in 65545 only for PCI, In for 65540 65540 / 545 (R) Pin Lists PIN LIST - BUS INTERFACE Pin # TypeVCC Plane IOH IOL Load 65545 PCI Bus 207 In Bus - - - RESET# VL-Bus RESET# CPUDirectLB RESET# ISA Bus RESET# 25 24 23 11 31 22 27 I/O Out In I/O I/O In In Bus Bus Bus Bus Bus Bus Bus -12 12 150 -12 12 150 - - - -4 4 150 -4 4 150 - - - - - - DEVSEL# TRDY# IRDY# IDSEL PAR FRAME# STOP# LDEV# LRDY# RDYRTN# W/R# M/IO# ADS# LCLK LDEV# LRDY# CRESET W/R# M/IO# ADS# CLK2X IOWR# RDY MEMW# MEMR# AEN ALE IORD# 32 10 43 21 179 180 182 183 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 28 29 30 53 54 In In In In In In In In In In In In In In In In In In In In In In In In In In I/O I/O I/O I/O Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus - - - - - - - - - - - - - - - - - - - - - - - - - - -8 -8 -8 -8 C/BE1# C/BE3# C/BE0# C/BE2# - - - - - - - - - - - - - - - - - - - - CLK - PERR# SERR# ACTI ENABKL BE1# BE3# BE0# BE2# A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 BE1# BE3# BE0# BE2# A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 BHE# RFSH# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 ROMCS# IRQ ACTI ENABKL - - - - - - - - - - - - - - - - - - - - - - - - - - 8 8 8 8 - - - - - - - - - - - - - - - - - - - - - - - - - - 150 150 150 150 These two pins usually function as ACTI and ENABKL, but can be reconfigured as additional address msbs (for 386/486/VL-Bus only) via configuration bit-6 (see other tables and pin descriptions for more details) In internal clock synthesizer test mode, MCLK is output on A25 and VCLK is output on A24. LB# ISA# 2X# BusConfiguration 1 1 1 VL-Bus (1x clock) Pin-23 = RDYRTN# 1 1 0 CPU-Direct (2x clock) Pin-23 = CRESET 1 0 1 ISA Bus 1 0 0 -reserved0 1 1 PCI Bus (65545 only) 0 1 0 -reserved0 0 1 -reserved0 0 0 -reservedNote: I OL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Note: I OL/IOH are specified in mA; Load is specified in pF Revision 1.2 26 65540 / 545 (R) Pin Lists PIN LIST - BUS INTERFACE Pin # 51 50 49 48 47 46 45 44 41 40 38 37 36 35 34 33 20 19 18 17 16 15 14 13 8 7 6 5 4 3 2 1 Type VCC Plane I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O Bus I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus Bus IOH IOL -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 Load 65545 PCI Bus 150 AD0 150 AD1 150 AD2 150 AD3 150 AD4 150 AD5 150 AD6 150 AD7 150 AD8 150 AD9 150 AD10 150 AD11 150 AD12 150 AD13 150 AD14 150 AD15 -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 VL-Bus D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CPUDirectLB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 ISA Bus D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 ZWS# MCS16# IOCS16# -- -- -- -- -- -- -- -- -- -- -- -- -- Note: I OL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Note: I OL/IOH are specified in mA; Load is specified in pF Revision 1.2 27 65540 / 545 (R) Pin Lists PIN LIST - DISPLAY MEMORY INTERFACE Pin # Type IOH IOL Load Function Alt Alt 145 I/O -4 4 50 AA0 CFG0 - 146 I/O -4 4 50 AA1 CFG1 - 147 I/O -4 4 50 AA2 CFG2 - 148 I/O -4 4 50 AA3 CFG3 - 149 I/O -4 4 50 AA4 CFG4 - 150 I/O -4 4 50 AA5 CFG5 - 151 I/O -4 4 50 AA6 CFG6 - 152 I/O -4 4 50 AA7 CFG7 - 153 I/O -4 4 50 AA8 CFG8 - 154 I/O -4 4 50 AA9 32KHZ VR0 90 91 92 93 94 95 96 97 98 99 Out Out Out Out Out Out Out Out I/O I/O -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 4 4 4 4 4 4 4 4 4 4 50 50 50 50 50 50 50 50 50 50 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 P16 P17 P18 P19 P20 P21 P22 P23 - - - - - - - - - - VG1 VG0 156 Out -4 123 Out -4 101 I/O -4 4 4 4 50 50 50 RASA# RASB# RASC# - - - - - KEY 160 159 126 125 104 103 -4 -4 -4 -4 -4 -4 4 4 4 4 4 4 50 50 50 50 50 50 CASAL# CASAH# CASBL# CASBH# CASCL# CASCH# 157 Out -4 124 Out -4 102 Out -4 4 4 4 50 50 50 WEA# WEAH# - WEB# WEBH# - WEC# WECH# PCLK 155 Out -4 100 I/O -4 4 4 50 50 OEAB# OEC# Out Out Out Out I/O I/O Pin # 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 127 128 129 130 131 132 133 134 135 136 137 138 140 141 143 144 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 106 107 109 110 111 112 113 114 115 116 117 118 119 120 121 122 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 WEAL# - CASA# - WEBL# - CASB# - WECL# VR6 CASC# VR7 - - - VR1 IOH IOL -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 Load 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 Function MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 MBD0 MBD1 MBD2 MBD3 MBD4 MBD5 MBD6 MBD7 MBD8 MBD9 MBD10 MBD11 MBD12 MBD13 MBD14 MBD15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 MCD0 MCD1 MCD2 MCD3 MCD4 MCD5 MCD6 MCD7 MCD8 MCD9 MCD10 MCD11 MCD12 MCD13 MCD14 MCD15 Alt Alt VB2 VB3 VB4 VB5 VB6 VB7 VG2 VG3 VG4 VG5 VG6 VG7 VR2 VR3 VR4 VR5 Note: I OL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Note: I OL/IOH are specified in mA; Load is specified in pF Revision 1.2 28 65540 / 545 (R) Pin Lists PIN PIST - CRT INTERFACE Pin # 65 64 55 60 58 57 59 56 Type Out Out - Out Out Out Vcc Gnd IOH IOL Load Function -12 12 150 HSYNC -12 12 150 VSYNC - - - RSET - - - RED - - - GREEN - - - BLUE - - - AVCC - - - AGND PIN LIST - POWER & GROUND Alt - - - - - - - - Pin # Type IOH IOL Load Function 80 Vcc - - - IVCC 181 Vcc - - - IVCC PIN PIST - PANEL INTERFACE Pin # 67 68 69 70 71 72 73 74 75 76 78 79 81 82 83 84 85 86 87 88 Type Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out IOH IOL -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 -8 8 Load Function Alt Alt 80 FLM - 80 LP BLANK# DE 80 M BLANK# DE 80 SHFCLK - 80 P0 - 80 P1 - 80 P2 - 80 P3 - 80 P4 - 80 P5 - 80 P6 - 80 P7 - 80 P8 - 80 P9 - 80 P10 - 80 P11 - 80 P12 - 80 P13 - 80 P14 - 80 P15 - 77 184 Gnd Gnd - - - - - - IGND IGND 9 42 Vcc Vcc - - - - - - BVCC BVCC 12 26 39 52 Gnd Gnd Gnd Gnd - - - - - - - - - - - - BGND BGND BGND BGND 158 142 108 Vcc Vcc Vcc - - - - - - - - - MVCCA MVCCB MVCCC 161 139 105 Gnd Gnd Gnd - - - - - - - - - MGNDA MGNDB MGNDC 66 Vcc - - - DVCC 63 89 Gnd Gnd - - - - - - DGND DGND Note: IVCC must equal CVCC PIN LIST - POWER MANAGEMENT Pin # Type IOH IOL 62 Out -8 8 61 Out -8 8 54 I/O -8 8 53 I/O -8 8 178 In - - Load Function Alt Alt 80 ENAVDD - - 80 ENAVEE ENABKL - 80 ENABKL A27 VB1 80 ACTI A26 VB0 - STNDBY# - - PIN LIST - CLOCK Pin # 203 204 205 206 202 208 Type In Out Vcc Vcc Gnd Gnd IOH IOL Load Function - - - XTALI -2 2 50 XTALO - - - CVCC0 - - - CVCC1 - - - CGND0 - - - CGND1 Alt - - - - - - Note: CVCC must equal IVCC Note: I OL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Note: I OL/IOH are specified in mA; Load is specified in pF Revision 1.2 29 65540 / 545 (R) Revision 1.2 30 65540 / 545 (R) Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name 207 RESET# 22 ADS# ISA / CPU Direct / VL-Bus Interface Type Active In Low Reset. For VL-Bus interfaces, connect to RESET#. For direct CPU local bus interfaces, connect to the system reset generated by the motherboard system logic for all peripherals (not the RESET# pin of the processor). For ISA bus interfaces, RESET must be inverted before connection to this pin. (ALE) In In Low High Address Strobe. In VL-Bus and CPU local bus interfaces indicates valid address and control signal information is present. It is used for all decodes and to indicate the start of a bus cycle. (AEN) In In Both High Memory / IO. In VL-Bus and CPU local bus interfaces indicates memory or I/O cycle: 1 = memory, 0 = I/O. (MEMR#) In In Both Low Write / Read. This control signal indicates a write (high) or read (low) operation. It is sampled on the rising edge of the (internal) 1x CPU clock when ADS# is active. 23 RDYRTN# for 1x clock config In CRESET for 2x clock config In (MEMW#) In Low High Low Ready Return. Handshaking signal in VL-Bus interface indicating synchronization of RDY# by the local bus master / controller to the processor. Upon receipt of this LCLK-synchronous signal the 65540 / 545 will stop driving the bus (if a read cycle was active) and terminate the current cycle. 24 LRDY# Out/OC Out/OC Low High Local Ready. Driven low during VL-Bus and CPU local bus cycles to indicate the current cycle should be completed. This signal is driven high at the end of the cycle, then tri-stated. In ISA bus interfaces, this signal is active high and may be connected directly to the ISA bus RDY pin. (IOWR#) Out In Low Low Local Device. In VL-Bus and CPU local bus interfaces, this pin indicates that the 65540 / 545 owns the current cycle based on the memory or I/O address which has been broadcast. For VL-Bus, it is a direct output reflecting a straight address decode. (IORD#) In In Both Low Local Clock. In VL-Bus this pin is connected to the CPU 1x clock. In CPU local bus interfaces it is connected to the CPU 1x or 2x clock. If the input is a 2x clock, the processor reset signal must be connected to CRESET (pin 23) for synchronization of the clock phase. 31 11 M/IO# W/R# (RDY) 25 27 LDEV# LCLK Description Note: Pin names in parentheses (...) indicate alternate functions (in this case, ISA bus control) Revision 1.2 31 65540 / 545 (R) Pin Descriptions PIN DESCRIPTIONS Pin # ISA / CPU Direct / VL-Bus Interface (continued) Pin Name Type Active Description 43 BE0# (A0) (BLE#) In Low Byte Enable 0. Indicates data transfer on D7:D0 for the current cycle. A0 address input in ISA interfaces. In 16-bit local bus interfaces indicates the low order byte at the current (16-bit) word address is being accessed. 32 BE1# (BHE#) In Low Byte Enable 1. Indicates data transfer on D15:D8 for the current cycle. In ISA, indicates high order byte at the current (16-bit) word address is being accessed. 21 BE2# (A1) In Low Byte Enable 2. Indicates data transfer on D23:D16 for the current cycle. A1 address in ISA & 16-bit local bus. 10 BE3# (RFSH#) In Low Byte Enable 3. BE3# indicates that data is to be transferred over the data bus on D31:24 during the current access. Refresh input in ISA interfaces. Disconnected in 16-bit local bus interfaces. 179 180 182 183 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 28 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 In In In In In In In In In In In In In In In In In In In In In In High High High High High High High High High High High High High High High High High High High High High High System Address Bus. In ISA, VL-Bus, and direct CPU interfaces, the address pins are connected directly to the bus. In 386 SX local bus interfaces BE2# is address input A1, BE0# is BLE#, and BE1# is BHE#. In ISA bus interfaces BE2# is address A1, BE0# is address A0, BE1# is BHE#, A17-23 are LA17-23, and A24 is ROMCS# (indicates valid ROM access to memory address range 0C0000-0C7FFFh). 29 30 A24 (ROMCS#) A25 (IRQ) 53 54 A26 (ACTI) (VB0) (GP0) A27 (ENBKL) (VB1) (GP1) (LA17) (LA18) (LA19) (LA20) (LA21) (LA22) (LA23) (VOUT) I/O (MOUT) I/O I/O I/O High High High High Address inputs through A23 are always available; A2427 may be optionally used for other functions: In internal clock synthesizer test mode (TS#=0 at Reset), A24 becomes VCLK out and A25 becomes MCLK out. A25 may alternately be used as a programmable polarity IRQ output. Set when interrupt on VSYNC is enabled. Cleared by reprogramming register 11h in the CRT Controller. See also XR14 bit-7. For 24-bit RGB Video input, A26-27 may be used as the two lsbs of the Blue Video. Otherwise, A26 and A27 may be used as General Purpose I/O pins or as Activity Indicator and Enable Backlight respectively (see panel interface pin descriptions and XR5C and XR72 for more details). Note: Pin names in parentheses (...) indicate alternate functions Revision 1.2 32 65540 / 545 (R) Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name ISA / CPU Direct / VL-Bus Interface (continued) Type Active Description System Data Bus. 51 50 49 48 47 46 45 44 D00 D01 D02 D03 D04 D05 D06 D07 I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High 41 40 38 37 36 35 34 33 D08 D09 D10 D11 D12 D13 D14 D15 I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High 20 19 18 17 16 15 14 13 D16 D17 D18 D19 D20 D21 D22 D23 I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High 8 7 6 5 4 3 2 1 D24 D25 D26 D27 D28 D29 D30 D31 I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High (ZWS#) (MCS16#) (IOCS16#) In 32-bit CPU Local Bus designs these data lines connect directly to the processor data lines. On the VLBus they connect to the corresponding buffered or unbuffered data signal. In ISA bus interfaces, D16-18 become outputs for the Zero Wait State, Memory Chip Select 16, and I/O Chip Select 16 respectively. In ISA bus interfaces D19-31 are unused and should be left disconnected. Note: Pin names in parentheses (...) indicate alternate functions Revision 1.2 33 65540 / 545 (R) Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name 207 PCI Bus Interface (65545 Only) Type Active Description RESET# In Low Reset. This input is used to bring signals and registers in the chip to a consistent state. All outputs from the chip are tri-stated or driven to an inactive state. 201 CLK In High Bus Clock. This input provides the timing reference for all bus transactions. All bus inputs except RESET# and INTA# are sampled on the rising edge of CLK. CLK may be any frequency from DC to 33MHz. 31 PAR I/O High Parity. This signal is used to maintain even parity across AD0-31 and C/BE0-3#. PAR is stable and valid one clock after the address phase. For data phases PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase (i.e., PAR has the same timing as AD0-31 but delayed by one clock). The bus master drives PAR for address and write data phases; the target drives PAR for read data phases. 22 FRAME# In Low Cycle Frame. Driven by the current master to indicate the beginning and duration of an access. Assertion indicates a bus transaction is beginning (while asserted, data transfers continue); de-assertion indicates the transaction is in the final data phase. 23 IRDY# In Low Initiator Ready. Indicates the bus master's ability to complete the current data phase of the transaction. During a write, IRDY# indicates valid data is present on AD0-31; during a read it indicates the master is prepared to accept data. A data phase is completed on any clock when both IRDY# and TRDY# are sampled asserted (wait cycles are inserted until this occurs). 24 TRDY# S/TS Low Target Ready. Indicates the target's ability to complete the current data phase of the transaction. During a read, TRDY# indicates that valid data is present on AD0-31; during a write it indicates the target is prepared to accept data. A data phase is completed on any clock when both IRDY# and TRDY# are sampled asserted (wait cycles are inserted until this occurs). 27 STOP# S/TS Low Stop. Indicates the current target is requesting the master to stop the current transaction. 25 DEVSEL# S/TS Low Device Select. Indicates the current target has decoded its address as the target of the current access. Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before being released, and are not driven for at least one cycle after being released by the previous device. A pull-up provided by the bus controller is used to maintain an inactive level between transactions. Revision 1.2 34 65540 / 545 (R) Pin Descriptions PIN DESCRIPTIONS Pin # PCI Bus Interface (65545 Only) Pin Name Type Active 29 PERR# (VCLKOUT) S/TS Low Parity Error. This signal is for the reporting of data parity errors (except for Special Cycles where SERR# is used). The PERR# pin is Sustained Tri-state and is driven active by the agent receiving the data for two clocks following the data when a data parity error is detected. PERR# will be driven high for one clock before being tri-stated as with all sustained tri-state signals. PERR# will not be reported until the 65545 has claimed the access by asserting DEVSEL# and completing the data phase. 30 SERR# (MCLKOUT) OD Low System Error. Used to report system errors where the result will be catastrophic (address parity error, data parity errors for Special Cycle commands, etc.). This output is actively driven for a single PCI clock cycle synchronous to CLK and meets the same setup and hold time requirements as all other bused signals. SERR# is not driven high by the 65545 after being asserted; it is pulled high only by a weak pull-up provided by the system, so SERR# on the PCI bus may take two or three clock periods to fully return to an inactive state. n/a n/a n/a n/a n/a n/a n/a n/a These pins are reserved for future use and should not be connected. All the pins in this group are tri-stated at all times in PCI interface mode. 28 179-180 182-183 185-200 Reserved Reserved Reserved Reserved Description Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before being released, and are not driven for at least one cycle after being released by the previous device. A central pull-up provided by the bus controller is used to maintain an inactive level between transactions. Revision 1.2 35 65540 / 545 (R) Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name PCI Bus Interface (65545 Only) Type Active Description PCI Address / Data Bus 51 50 49 48 47 46 45 44 AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High 41 40 38 37 36 35 34 33 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High 20 19 18 17 16 15 14 13 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High 8 7 6 5 4 3 2 1 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High 43 32 21 10 C/BE0# C/BE1# C/BE2# C/BE3# In In In In Low Low Low Low Bus Command / Byte Enables. During the address phase of a bus transaction, these pins define the bus command (see list above). During the data phase, these pins are byte enables that determine which byte lanes carry meaningful data: byte 0 corresponds to AD0-7, byte 1 to 8-15, byte 2 to 16-23, and byte 3 to 24-31. 11 IDSEL In High Initialization Device Select. Used as a chip select during configuration read and write transactions. Revision 1.2 Address and data are multiplexed on the same pins. A bus transaction consists of an address phase followed by one or more data phases (both read and write bursts are allowed by the bus definition). The address phase is the clock cycle in which FRAME# is asserted (AD0-31 contain a 32-bit physical address). For I/O, the address is a byte address, for memory and configuration, the address is a DWORD address. During data phases AD0-7 contain the LSB and 24-31 contain the MSB. Write data is stable and valid when IRDY# is asserted and read data is stable and valid when TRDY# is asserted. Data is transferred during those clocks when both IRDY# and TRDY# are asserted. C/BE3-0 CommandType 65545 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 4 0011 I/OWrite 4 0100 -reserved0101 -reserved0110 MemoryRead 4 0111 MemoryWrite 4 1000 -reserved1001 -reserved1010 ConfigurationRead 4 1011 ConfigurationWrite 4 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Read & Invalidate 36 65540 / 545 (R) Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name 145 146 147 148 149 150 151 152 153 154 AA0 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 90 91 92 93 94 95 96 97 98 99 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 156 123 101 RASA# RASB# RASC# Display Memory Interface Type Active (LB#) (CFG0) (ISA#) (CFG1) (2X#) (CFG2) (Reserved)(CFG3) (Reserved)(CFG4) (OS#) (CFG5) (AD#) (CFG6) (TS#) (CFG7) (LV#) (CFG8) (32KHz) (VR0) Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High High High Address bus for DRAMs A and B. (P16) (P17) (P18) (P19) (P20) (P21) (P22) (P23) (VG1) (VG0) Out Out Out Out Out Out Out Out I/O I/O High High High High High High High High High High Address bus for DRAM C. (KEY) Out Out Out In Low Low Low High Row address strobe for DRAM A Row address strobe for DRAM B Row address strobe for DRAM C or color key input from external video source 160 159 126 125 104 103 CASAL# (WEAL#) CASAH# (CASA#) CASBL# (WEBL#) CASBH# (CASB#) CASCL# (WECL#) (VR6) CASCH# (CASC#) (VR7) Out Out Out Out I/O I/O Low Low Low Low Both Both Column address strobe for the DRAM A lower byte Column address strobe for the DRAM A upper byte Column address strobe for the DRAM B lower byte Column address strobe for the DRAM B upper byte CAS for the DRAM C lower byte or video in red bit-6 CAS for the DRAM C upper byte or video in red bit-7 157 124 102 WEA# WEB# WEC# Out Out Out Low Low Both Write enable for DRAM A Write enable for DRAM B Write enable for DRAM C or video in port PCLK out 155 100 OEAB# OEC# Out I/O Low Both Output enable for DRAMs A and B Output enable for DRAM C or video in red bit-1 (WEAH#) (WEBH#) (WECH#) (PCLK) (VR1) Please see the configuration table in the Extended Register description section for complete details on the configuration options (XR01 and XR6C). AA9, alternately, becomes clock input for refresh of non-self-refresh DRAMs and panel power sequencing or video input red lsb. Note: Pin names in parentheses (...) indicate alternate functions Revision 1.2 37 65540 / 545 (R) Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 127 128 129 130 131 132 133 134 135 136 137 138 140 141 143 144 106 107 109 110 111 112 113 114 115 116 117 118 119 120 121 122 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 MBD0 MBD1 MBD2 MBD3 MBD4 MBD5 MBD6 MBD7 MBD8 MBD9 MBD10 MBD11 MBD12 MBD13 MBD14 MBD15 MCD0 MCD1 MCD2 MCD3 MCD4 MCD5 MCD6 MCD7 MCD8 MCD9 MCD10 MCD11 MCD12 MCD13 MCD14 MCD15 (TSENA#) (ICTENA#) (VB2) (VB3) (VB4) (VB5) (VB6) (VB7) (VG2) (VG3) (VG4) (VG5) (VG6) (VG7) (VR2) (VR3) (VR4) (VR5) Display Memory Interface (continued) Type Active Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High Memory data bus for DRAM A (lower 512KB of display memory) Memory data bus for DRAM B (upper 512KB) Memory data bus for DRAM C (Frame Buffer) When a frame buffer DRAM is not required, this bus may optionally be used to input up to 24 bits of RGB data from an external PC-Video subsystem. For the remaining pins of the 24-bit video input port see the pin descriptions of DRAM C address, DRAM C control, AA9, ACTI, and ENABKL. Note that this configuration also provides for additional panel outputs so that a full 24-bit video input port may be implemented along with a 24-bit true-color TFT panel (TFT panels never need DRAM C). Note: Pin names in parentheses (...) indicate alternate functions. Note: If ICTENA# is low with RESET# low, a rising edge on XTALI will put the chip into 'In Circuit Test' mode. In ICT mode, all digital signal pins become inputs which are part of a long path starting at ENAVDD (pin 62) and proceeding to lower pin numbers around the chip to pin 1 then to pin 208 and ending at VSYNC (pin 64). If all pins in the path are high, the VSYNC output will be high. If any pin is low, the VSYNC output will be low. Thus the chip can be checked in circuit to determine if all pins are connected properly by toggling all pins one at a time and observing the effect on VSYNC. XTALI must be toggled last because rising edges on XTALI with ICTENA# high or RESET# high will exit ICT mode. As a side effect, ICT mode effectively 3-states all pins except VSYNC. If TSENA# is low with RESET # low , a rising edge on XTALI will 3-state all pins. An XTALI rising edge without the enabling conditions exits 3-state. Revision 1.2 38 65540 / 545 (R) Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name Flat Panel Display Interface Type Active Description 8, 9, 12, or 16-bit flat panel data output. 18-bit and 24bit panel interfaces may also be supported (see CA0-7 for P16-23). Refer to the table below for configurations for various panel types. 71 72 73 74 75 76 78 79 81 82 83 84 85 86 87 88 70 67 68 69 P0 Out P1 Out P2 Out P3 Out P4 Out P5 Out P6 Out P7 Out P8 (SHFCLKU) Out P9 Out P10 Out P11 Out P12 Out P13 Out P14 Out P15 Out SHFCLK (CL2) (SHFCLKL) Out FLM Out LP (CL1) (DE) (BLANK#) Out M (DE) (BLANK#) Out High High High High High High High High High High High High High High High High High High High High 62 61 53 54 ENAVDD ENAVEE (ENABKL) ACTI (GP0)(VB0)(A26) ENABKL (GP1)(VB1)(A27) High High High High Out Out I/O I/O Shift Clock. Pixel clock for flat panel data. First Line Marker. Flat Panel equivalent of VSYNC. Latch Pulse. Flat Panel equivalent of HSYNC. M signal for panel AC drive control (may also be called ACDCLK). May also be configured as BLANK# or as Display Enable (DE) for TFT Panels (see XR4F bit-6). Power sequencing controls for panel driver electronics voltage VDD and panel LCD bias voltage VEE Activity Indicator and Enable Backlight outputs. May be configured for other functions (see Extension Registers XR5C and XR72 and pin descriptions of MCD0-15 and A26/A27 for more information). Mono Mono Mono Color Color Color 6554x 6554x SS DD DD TFT TFT TFT HR Pin# Pin Name 8-bit 8-bit 16-bit 9/12/16-bit 18/24-bit 18/24-bit 71 P0 - UD3 UD7 B0 B0 B00 72 P1 - UD2 UD6 B1 B1 B01 73 P2 - UD1 UD5 B2 B2 B02 74 P3 - UD0 UD4 B3 B3 B03 75 P4 - LD3 UD3 B4 B4 B10 76 P5 - LD2 UD2 G0 B5 B11 78 P6 - LD1 UD1 G1 B6 B12 79 P7 - LD0 UD0 G2 B7 B13 81 P8 P0 - LD7 G3 G0 G00 82 P9 P1 - LD6 G4 G1 G01 83 P10 P2 - LD5 G5 G2 G02 84 P11 P3 - LD4 R0 G3 G03 85 P12 P4 - LD3 R1 G4 G10 86 P13 P5 - LD2 R2 G5 G11 87 P14 P6 - LD1 R3 G6 G12 88 P15 P7 - LD0 R4 G7 G13 90 P16 - - - - R0 R00 91 P17 - - - - R1 R01 92 P18 - - - - R2 R02 93 P19 - - - - R3 R03 94 P20 - - - - R4 R10 95 P21 - - - - R5 R11 96 P22 - - - - R6 R12 97 P23 - - - - R7 R13 70 SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK Pixels / Clock: 8 8 16 1 1 2 Revision 1.2 39 Color STN Color Color Color STN SS STN SS STN DD STN DD 8-bit (X4bP) 16-bit (4bP) 8-bit (4bP) 16-bit (4bP) R1... R1... UR1... UR0... B1... G1... UG1... UG0... G2... B1... UB1... UB0... R3... R2... UR2... UR1... B3... G2... LR1... LR0... G4... B2... LG1... LG0... R5... R3... LB1... LB0... B5... G3... LR2... LR1... SHFCLKU B3... - UG1... - R4... - UB1... - G4... - UR2... - B4... - UG2... - R5... - LG1... - G5... - LB1... - B5... - LR2... - R6... - LG2... - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SHFCLKL SHFCLK SHFCLK SHFCLK 2-2/3 5-1/3 2-2/3 5-1/3 65540 / 545 (R) Pin Descriptions PINDESCRIPTIONS Pin # CRT and Clock Interface Pin Name Type Active Description 65 HSYNC Out Both CRT Horizontal Sync (polarity is programmable) 64 VSYNC Out Both CRT Vertical Sync (polarity is programmable) 60 58 57 RED GREEN BLUE Out Out Out High High High CRT analog video outputs from the internal color palette DAC. 55 RSET In n/a Set point resistor for the internal color palette DAC. A 270 1% resistor is required between RSET and AGND. 59 56 AVCC AGND VCC GND --- Analog power and ground pins for noise isolation for the internal color palette DAC. AVCC should be isolated from digital VCC as described in the Functional Description of the internal color palette DAC. AGND should be common with digital ground but must be tightly decoupled to AVCC. See the Functional Description of the internal color palette DAC for further information. 203 XTALI I/O High Crystal In. When the internal clock synthesizer is used, this pin serves as either the series resonant crystal input or as the input for an external reference oscillator (usually 14.31818 MHz). Note that in test mode for the internal clock synthesizer, MCLK is output on A25 (pin 30) and VCLK is output on A24 (pin 29). XTALO Out High Crystal Out. When the internal oscillator is used, this pin serves as the series resonant crystal output. When an external oscillator is used, this pin must be left disconnected. 205 202 CVCC0 CGND0 VCC GND --- 206 208 CVCC1 CGND1 VCC GND --- Analog power and ground pins for noise isolation for the internal clock synthesizer. Must be the same as VCC for internal logic. VCC/GND pair 0 and VCC/GND pair 1 pins must be carefully decoupled individually. Refer also to the section on clock ground layout in the Functional Description. Note that the CVCC voltage must be the same as the voltage for the internal logic (IVCC). 204 (MCLK) Note: Pin names in parentheses (...) indicate alternate functions Revision 1.2 40 65540 / 545 (R) Pin Descriptions CRT / Panel Output Signal Status During Standby Mode 6554x Pin # Signal Name Signal Status 67 FLM Forced Low 68 LP Forced Low 70 SHFCLK Forced Low 69 M Forced Low 71 P0 Forced Low 72 P1 Forced Low 73 P2 Forced Low 74 P3 Forced Low 75 P4 Forced Low 76 P5 Forced Low 78 P6 Forced Low 79 P7 Forced Low 81 P8 Forced Low 82 P9 Forced Low 83 P10 Forced Low 84 P11 Forced Low 85 P12 Forced Low 86 P13 Forced Low 87 P14 Forced Low 88 P15 Forced Low 90 P16/CA0 Forced Low 91 P17/CA1 Forced Low 92 P18/CA2 Forced Low 93 P19/CA3 Forced Low 94 P20/CA4 Forced Low 95 P21/CA5 Forced Low 96 P22/CA6 Forced Low 97 P23/CA7 Forced Low 62 ENAVDD Forced Low 61 ENAVEE Forced Low 54 ENABKL/A27 Forced Low 65 HSYNC Forced Low 64 VSYNC Forced Low 53 ACTI/A26 Forced Low 60,58,57 R,G,B Forced Low Signal Polarity XR54 bit 7 XR54 bit 6 N/A N/A XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) XR61 bit 7 (text); XR63 bit 7 (graphics) N/A N/A N/A N/A N/A N/A N/A Display Memory Output Signal Status During Standby Mode 6554x Pin # Signal Name Signal Status 156 RASA# Driven Low 123 RASB# Driven Low 101 RASC# Driven Low (see note 1) 157 WEA# Driven High 124 WEB# Driven High 102 WEC# Driven High (see note 1) 160 CASAL# Driven Low 159 CASAH# Driven Low 126 CASBL# Driven Low 125 CASBH# Driven Low 104 CASCL# Driven Low (see note 1) 103 CASCH# Driven Low (see note 1) 155 OEAB# Driven High 100 OEC# Driven High (see note 1) 154-145 AA9-0 Pulled low with weak resistor 99-90 CA9-0 Driven Low 177-162 MAD15-0 Pulled low with weak resistor 144-143,141-140,138-127 MBD15-0 Pulled low with weak resistor 122-109,107-66 MCD15-0 Pulled low with weak resistor (see note 1) Notes: 1 These pins are inputs when using the video input port. These pins are driven as outputs when using a frame buffer DRAM. Revision 1.2 41 65540 / 545 (R) Pin Descriptions PIN DESCRIPTIONS Power / Ground and Standby Control Pin # Pin Name Type Active Description 178 STNDBY# In Low Standby Control Pin. Pulling this pin to ground places the 65540 / 545 in Standby Mode. 80 77 IVCC IGND Vcc Gnd - - Power / Ground (Internal Logic). 5V10% or 3.3V 0.3V. Note that this voltage must be the same as CVCC (voltage for internal clock synthesizer). 181 184 IVCC IGND Vcc Gnd - - 9 12 26 BVCC BGND BGND Vcc Gnd Gnd - - - 42 39 52 BVCC BGND BGND Vcc Gnd Gnd - - - 66 63 89 DVCC DGND DGND Vcc Gnd Gnd - - - Power / Ground (Display Interface). 5V10% or 3.3V 0.3V. 158 161 MVCCA MGNDA Vcc Gnd - - Power / Ground (Memory Interface A). 5V10% or 3.3V 0.3V. 142 139 MVCCB MGNDB Vcc Gnd - - Power / Ground (Memory Interface B). 5V10% or 3.3V 0.3V. 108 105 MVCCC MGNDC Vcc Gnd - - Power / Ground (Memory Interface C). 5V10% or 3.3V 0.3V. Power / Ground (Bus Interface). 5V10% or 3.3V 0.3V. Bus/ClockOutputSignalStatusDuringStandbyMode 6554x Pin # 204 29 30 53 54 24 25 51-44, 41-40,38-33 20 19 18 17-13, 8-1 Signal Status Signal Name VL-Bus ISA Bus XTALO Driven (see note 1) Driven (see note 1) ROMCS# / A24 N/A Driven High IRQ / A25 N/A Tri-Stated ACTI / A26 (see previous page) N/A ENABKL / A27 (see previous page) N/A LRDY# / RDY Tri-Stated Tri-Stated LDEV# Driven High N/A D0-15 Tri-Stated Tri-Stated D16 / ZWS# Tri-Stated Tri-Stated D17 / MCS16# Tri-Stated Tri-Stated D18 / IOCS16# Tri-Stated Tri-Stated D19-31 Tri-Stated Tri-Stated Notes: 1 The XTALO pin will always be driven except when XR33 bit-2 is set to '1'. Revision 1.2 42 65540 / 545 (R) I/O Map I/O Map PortAddress Read 102 Global Enable (ISA Bus Only) Write Global Enable (ISA Bus Only) 3B0 3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8 3B9 3BA 3BB 3BC 3BD 3BE 3BF Reserved for MDA/Hercules Reserved for MDA/Hercules Reserved for MDA/Hercules Reserved for MDA/Hercules CRTC Index CRTC Data Reserved for MDA/Hercules Reserved for MDA/Hercules Hercules Mode Register (MODE) -Status Register (STAT) -- Reserved for MDA/Hercules Mono Reserved for MDA/Hercules Mode Reserved for MDA/Hercules Reserved for MDA/Hercules CRTC Index CRTC Data Reserved for MDA/Hercules Reserved for MDA/Hercules Hercules Mode Register (MODE) Set Light Pen FF (ignored) Feature Control Register (FCR) Clear Light Pen FF (ignored) Hercules Configuration Register (HCFG) Hercules Configuration Register (HCFG) 3C0 3C1 3C2 3C3 3C4 3C5 3C6 3C7 3C8 3C9 3CA 3CB 3CC 3CD 3CE 3CF Attribute Controller Index / Data Attribute Controller Index / Data Feature Read Register (FEAT) Video Subsystem Enable (VSE)(LB Only) Sequencer Index Sequencer Data Color Palette Mask Color Palette State Color Palette Write Mode Index Color Palette Data Feature Control Register (FCR) -Miscellaneous Output Register (MSR) -Graphics Controller Index Graphics Controller Data Attribute Controller Index / Data Attribute Controller Index / Data Miscellaneous Output Register (MSR) Video Subsystem Enable (VSE)(LB Only) Sequencer Index Sequencer Data Color Palette Mask Color Palette Read Mode Index Color Palette Write Mode Index Color Palette Data ----Graphics Controller Index Graphics Controller Data n3D0 n3D1 n3D2 n3D3 03D4 03D5 03D6 03D7 03D8 03D9 03DA 03DB 03DC 32-Bit DR Register Extensions (65545 only) 32-Bit DR Register Extensions (65545 only) 32-Bit DR Register Extensions (65545 only) 32-Bit DR Register Extensions (65545 only) CRTC Index CRTC Data CHIPSTM Extensions Index CHIPSTM Extensions Data CGA Mode Register (MODE) CGA Color Register (COLOR) Status Register (STAT) --- 32-Bit DR Register Extensions (65545 only) 32-Bit DR Register Extensions (65545 only) 32-Bit DR Register Extensions (65545 only) 32-Bit DR Register Extensions (65545 only) CRTC Index Color CRTC Data Mode CHIPSTM Extensions Index CHIPSTM Extensions Data CGA Mode Register (MODE) CGA Color Register (COLOR) Feature Control Register (FCR) Clear Light Pen FF (ignored) Set Light Pen FF (ignored) 46E8 -- Setup Control (ISA Bus Only) Reserved for system parallel port 32-Bit register addresses are of the form 'bnnn nn1b bbbb bb00' where 'bbbbbbbb' is specified by I/O base register XR07 and 'nnnnn' specifies 1 of 32 DRxx 32-bit registers Revision 1.2 43 65540 / 545 (R) Register Summary REGISTER SUMMARY - CGA, MDA, AND HERCULES MODEs Register ST00 (STAT) Register Name Display Status CLPEN SLPEN Clear Light Pen Flip Flop Set Light Pen Flip Flop 0 0 W(n/a) W(n/a) MODE COLOR HCFG CGA/MDA/Hercules Mode Control CGA Color Select Hercules Configuration 7 6 2 RX, R0-11 XRX, XR0-7F '6845' Registers Extension Registers Bits Access I/O Port - MDA/Herc 7 R 3BA 0-8 0-8 I/O Port - CGA 3DA Comment 3BB(ignored) 3B9(ignored) 3DB(ignored) 3DC (ignored) ref only: no light pen ref only: no light pen R/W R/W W R 3B8 n/a 3BF 3D6-3D7 index 14 3D8 3D9 n/a n/a R/W R/W 3B4-3B5 3D6-3D7 3D4-3D5 3D6-3D7 R/W at XR7E also XR14 REGISTER SUMMARY - EGA MODE Register MSR FCR Register Name Miscellaneous Output Feature Control Bits 7 3 Access I/O Port - Mono W 3C2 W 3BA I/O Port - Color 3C2 3DA ST00 (FEAT) ST01 (STAT) Feature Read (Input Status 0) Display Status (Input Status 1) 4 7 R R 3C2 3BA 3C2 3DA CLPEN SLPEN Clear Light Pen Flip Flop Set Light Pen Flip Flop 0 0 W(n/a) W(n/a) 3BB(ignored) 3B9(ignored) 3DB(ignored) 3DC (ignored) SRX, SR0-7 CRX, CR0-3F GRX, GR0-8 ARX, AR0-14 XRX, XR0-7F Sequencer CRT Controller Graphics Controller Attributes Controller Extension Registers 0-8 0-8 0-8 0-8 0-8 R/W R/W R/W R/W R/W 3C4-3C5 3B4-3B5 3CE-3CF 3C0-3C1 3D6-3D7 3C4-3C5 3D4-3D5 3CE-3CF 3C0-3C1 3D6-3D7 Comment ref only: no light pen ref only: no light pen REGISTER SUMMARY - VGA MODE Register VSE SETUP ENABLE PR0-17 Register Name Video Subsystem Enable Setup Control Global Enable PCI Configuration MSR Miscellaneous Output 7 W R 3C2 3CC 3C2 3CC FCR Feature Control 3 W R 3BA 3CA 3DA 3CA ST00 (FEAT) ST01 (STAT) Feature Read (Input Status 0) Display Status (Input Status 1) 4 6 R R 3C2 3BA 3C2 3DA CLPEN SLPEN Clear Light Pen Flip Flop Set Light Pen Flip Flop 0 0 W(n/a) W(n/a) 3BB(ignored) 3B9(ignored) 3DB(ignored) 3DC (ignored) DACMASK DACSTATE DACRX DACWX DACDATA Color Palette Pixel Mask Color Palette State Color Palette Read-Mode Index Color Palette Write-Mode Index Color Palette Data 0-FF 8 2 8 8 3x6 R/W R W R/W R/W 3C6 3C7 3C7 3C8 3C9 3C6 3C7 3C7 3C8 3C9 SRX, SR0-7 CRX, CR0-3F GRX, GR0-8 ARX, AR0-14 XRX, XR0-7F DR00-DR0C Sequencer CRT Controller Graphics Controller Attributes Controller Extension Registers 32-Bit Extension Registers 0-8 0-8 0-8 0-8 0-8 32 R/W R/W R/W R/W R/W R/W 3C4-3C5 3B4-3B5 3CE-3CF 3C0-3C1 3D6-3D7 n3D0-n3D3 3C4-3C5 3D4-3D5 3CE-3CF 3C0-3C1 3D6-3D7 n3D0-n3D3 Revision 1.2 Bits Access I/O Port - Mono I/O Port - Color Comment 1 W 3C3 if LB 3C3 if LB Disabled by XR70 bit-7 2 W 46E8 if ISA 46E8 if ISA Disabled by XR70 bit-7 1 R/W 102 if ISA 102 if ISA Setup Only in ISA Bus 8, 16, 32 R/W System Dependent System Dependent PCI Bus Only 44 Ref only: No light pen Ref only: No light pen Programmable I/O address 65540 / 545 (R) Register Summary REGISTER SUMMARY - INDEXED REGISTERS (VGA) Register SRX SR0 SR1 SR2 SR3 SR4 SR7 Register Name SequencerIndex Reset Clocking Mode Plane Mask Character Map Select Memory Mode Reset Horizontal Character Counter CRX CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CRA CRB CRC CRD CRE CRF LPENH LPENL CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR22 CR24 CRTC Index Horizontal Total Horizontal Display End Horizontal Blanking Start Horizontal Blanking End Horizontal Retrace Start Horizontal Retrace End Vertical Total Overflow Preset Row Scan Character Cell Height Cursor Start Cursor End Start Address High Start Address Low Cursor Location High Cursor Location Low Light Pen High Light Pen Low Vertical Retrace Start Vertical Retrace End Vertical Display End Offset Underline Row Scan Vertical Blanking Start Vertical Blanking End CRT Mode Control Line Compare Graphics Controller Data Latches Attribute Controller Index/Data Latch GRX GR0 GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 ARX AR0-F AR10 AR11 AR12 AR13 AR14 Bits 3 2 6 4 6 3 0 RegisterType VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA Access(VGA) R/W R/W R/W R/W R/W R/W W Access(EGA) R/W R/W R/W R/W R/W R/W n/a I/OPort 3C4 3C5 3C5 3C5 3C5 3C5 3C5 6 8 8 8 5+2+1 8 5+2+1 8 8 5+2 5+3 5+1 5+2 8 8 8 8 8 8 8 4+4 8 8 5+2 8 8 7 8 8 1 VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA VGA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W W R/W R/W R/W R/W R/W R/W R/W n/a n/a 3B4 Mono, 3D4 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color Graphics Controller Index Set/Reset Enable Set/Reset Color Compare Data Rotate Read Map Select Mode Miscellaneous Color Don't Care Bit Mask 4 4 4 4 5 2 6 4 4 8 VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 3CE 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF Attribute Controller Index Internal Palette Regs 0-15 Mode Control Overscan Color Color Plane Enable Horizontal Pixel Panning Color Select 6 6 7 6 6 4 4 VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W n/a 3C0 3C0 3C0 3C0 3C0 3C0 3C0 Revision 1.2 45 (3C1) (3C1) (3C1) (3C1) (3C1) (3C1) (3C1) 65540 / 545 (R) Register Summary EXTENSION REGISTER SUMMARY: 00-2F Reg XRX XR00 XR01 XR02 XR03 XR04 XR05 XR06 XR07 XR08 XR09 XR0A XR0B XR0C XR0D XR0E XR0F Register Name Bits Access Extension Index Register 7 R/W Chip Version (65540: v=0; 65545: v=1) 8 R/O Configuration 8 R/O CPU Interface Control 1 8 R/W CPUInterfaceControl2 (ROM Intfc) 2 R/W Memory Control 1 4 R/W Memory Control 2 (Clock Control) 8 R/W Palette Control (DRAM Intfc) 8 R/W I/O Base ( 65545 Only ) 8 R/W LinearAddressingBase (Linear Base L) 8 R/W -reserved(Linear Base H) ---reserved(XRAM Mode) --CPU Paging 5 R/W Start Address Top 2 R/W Auxiliary Offset 2 R/W Text Mode Control 6 R/W Software Flags 0 8 R/W Port 3D6 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 XR10 XR11 XR12 XR13 XR14 XR15 XR16 XR17 XR18 XR19 XR1A XR1B XR1C XR1D XR1E XR1F XR20 XR21 XR22 XR23 XR24 XR25 XR26 XR27 XR28 XR29 XR2A XR2B XR2C XR2D XR2E XR2F Single/Low Map High Map -reserved-reservedEmulation Mode WriteProtect Vertical Overflow Horizontal Overflow Alternate H Disp End AlternateHSyncStart (Half-line) Alternate H Sync End Alternate H Total Alternate Blank Start / H Panel Size Alternate H Blank End Alternate Offset Virtual EGA Switch Register -reserved-reserved-reserved-reservedFP AltMaxScanline FP AltTxtHVirtPanel Size Alt HSync Start -reservedVideo Interface Half Line Compare -reservedSoftware Flags 1 FLM Delay LP Delay LP Delay LP Width 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 Reset Codes: x d h r = = = = 8 8 --8 8 5 7 8 8 8 8 8 8 8 5 ----5 8 8 -5 8 -8 8 8 8 8 R/W R/W --R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ----R/W R/W R/W -R/W R/W -R/W R/W R/W R/W R/W Reset -xxxxxxx 1101v r r r dddddddd 00000000 - - - - - -0x - -0 - -000 00000000 00000000 11110100 xxxxxxxx 0 x -00 * - - - - - - 0000 xxxx 000 -xx -00 0 - xxx CHIPS' VGA Product Family 82C450 64300/310 65510 65530 65535 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 . 3 . . . 3 3 3 3 3 . 3 . . 3 . 3 3 3 3 . 3 . . . . 3 . . 3 . 3 . . . . 3 . . . 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 . 3 3 3 3 3 3 3 3 3 3 3 3 xxxxxxxx xxxxxxxx . . 0 0 * * x x x x x 0 x 0 000h 0000 0 *0 * 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx - - -x 3 3 3 3 3 3 3 . . 3 3 . . 3 . . 3 . . 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 . . . . . . . . 3 0 x x x x 3 Not changed by RESET (indeterminate on power-up) Set from the corresponding data bus pin on falling edge of RESET Read-only Hercules Configuration Register Readback bits Chip revision # (starting from 0000) . . 3 0000 - -0 xxxxxxxx 000 xxx xxx xxx xxx 3 . . 3 h00 000 000 000 xxx xxx xxx xxx xxx xxx xxx xxx * * *xxxxx xxxxxxxx xxxxxxxx 0000 xxxx xxxx xxxx xxxx . . 3 . . . . . . . . . . . . 3 3 3 3 3 . . . . 3 . . 3 . . 3 . . . . 3 . . 3 . . . . . . 3 3 3 . . . . . 3 . . . . 3 3 3 3 3 3 3 3 3 3 3 3 3 3 . - = Not implemented (always reads 0) * = Reserved (read/write, reset to 0) 0/1 = Reset to 0/1 by trailing edge of reset Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD) Revision 1.2 46 65540 / 545 (R) Register Summary EXTENSION REGISTER SUMMARY: 30-5F Reg XR30 XR31 XR32 XR33 XR34 XR35 XR36 XR37 XR38 XR39 XR3A XR3B XR3C XR3D XR3E XR3F Register Name Clock Divide Control Clock M-Divisor Clock N-Divisor Clock Control -reserved-reserved-reserved-reserved-reserved-reservedColor Key 0 Color Key 1 Color Key 2 Color Key Mask 0 Color Key Mask 1 Color Key Mask 2 XR40 XR41 XR42 XR43 XR44 XR45 XR46 XR47 XR48 XR49 XR4A XR4B XR4C XR4D XR4E XR4F BitBLT Configuration ( 65545 Only ) -reserved-reserved-reservedSoftware Flag Register 2 Software Flag Register 3 -reserved-reserved-reserved-reserved-reserved-reserved-reserved-reserved-reservedPanel Format 2 2 ---8 8 ---------5 XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5C XR5D XR5E XR5F Panel Format 1 Display Type Power Down Control Panel Format 3 PanelInterface H Compensation H Centering V Compensation V Centering V Line Insertion V Line Replication Power Sequencing Delay Activity Indicator Control FP Diagnostic ACDCLK (M) Control Power Down Mode Refresh 8 7 8 7 8 6 8 8 8 7 4 8 7 8 8 8 Reset Codes: x d h r = = = = Bits Access 4 R/W 7 R/W 7 R/W 7 R/W ------------8 R/W 8 R/W 8 R/W 8 R/W 8 R/W 8 R/W Port 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 Reset * * * *xxxx *xxxxxxx *xxxxxxx 0000 *000 R/W ---R/W R/W ---------R/W 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 - - - - - - xx R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx CHIPS' VGA Product Family 82C450 64300/310 65510 65530 65535 . 3 . . 3 . 3 . . 3 . 3 . . 3 . 3 . . 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . . 3 . 3 . . 3 . 3 . . 3 . 3 . . 3 . 3 . . 3 . 3 . . 3 xx * * *xxx . . . . . . . . . . . . . . . . xxxxxxxx 000 *0000 00000001 *00000x0 xxxxxxxx xxxx * *xx xxxxxxxx xxxxxxxx xxxxxxxx xxx *xxxx * * * *xxxx 10000001 0x *xxxxx 00000000 xxxxxxxx xxxxxxxx . . . . . . . . . . . . . . . . xxxxxxxx xxxxxxxx Not changed by RESET (indeterminate on power-up) Set from the corresponding data bus pin on falling edge of RESET Read-only Hercules Configuration Register Readback bits Chip revision # (starting from 0000) 3 . . . . . . . 3 3 . . . . . . . . . . . . . . . 3 3 . . . . . . . . . . . 3 . . . . . . . . . . . . . . . . . . . . 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 . . 3 . . . . . . . . . . . . . . . . . 3 . . 3 . 3 . . 3 3 3 3 3 - = Not implemented (always reads 0) * = Reserved (read/write, reset to 0) 0/1 = Reset to 0/1 by trailing edge of reset Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD) Revision 1.2 47 65540 / 545 (R) Register Summary EXTENSION REGISTER SUMMARY: 60-7F Reg XR60 XR61 XR62 XR63 XR64 XR65 XR66 XR67 XR68 XR69 XR6A XR6B XR6C XR6D XR6E XR6F Register Name Bits Access Blink Rate Control 8 R/W SmartMapTM Control 8 R/W SmartMapTM Shift Parameter 8 R/W SmartMapTMColorMappingControl 8 R/W FP Alternate Vertical Total 8 R/W FP Alternate Overflow 6 R/W FP Alternate Vertical Sync Start 8 R/W FP Alternate Vertical Sync End 4 R/W FP Vertical Panel Size 8 R/W -reserved---reserved---reserved--Programmable Output Drive 5 R/W -reserved--Polynomial FRC Control 8 R/W Frame Buffer Control 8 R/W Port 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 Reset 10000011 xxxxxxxx xxxxxxxx x1xxxxxx xxxxxxxx xxx * *xxx xxxxxxxx * * * *xxxx xxxxxxxx XR70 XR71 XR72 XR73 XR74 XR75 XR76 XR77 XR78 XR79 XR7A XR7B XR7C XR7D XR7E XR7F Setup / Disable Control -reserved(GPIO Control) ExternalDeviceI/O (GPIOData) Miscellaneous Control -reserved(Configuration 2) -reserved(Software Flags 3) -reserved-reserved-reserved-reserved-reserved-reserved-reservedDiagnostic CGA/Hercules Color Select Diagnostic 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 0------- Reset Codes: x d h r = = = = 1 -7 6 ---------1 6 8 R/W -R/W R/W ---------R/W R/W R/W * *0000d* 10111101 00000000 CHIPS' VGA Product Family 82C450 64300/310 65510 65530 65535 . 3 3 3 3 . . 3 3 3 . . 3 3 3 . . 3 3 3 . . 3 3 3 . . 3 3 3 . . 3 3 3 . . 3 3 3 . . 3 3 3 . . . . . . . . . . . . . . . . . 3 3 3 . . . . . . . 3 3 3 . . . 3 3 3 3 0000000 * 00 - - 0000 0------* - - xxxxxx 00xxxx00 Not changed by reset (indeterminate on power-up) Set from the corresponding data bus pin on trailing edge of reset Read-only Hercules Configuration Register Readback bits Chip revision # (starting from 0000) 3 3 3 . . . . . . . . . . . . . 3 3 . . . . . . . . . . . . 3 3 3 . . . . . . . . . . . . . . . . . . . . . 3 3 3 3 3 3 3 3 3 3 3 3 3 3 . . . . . . . . . . - = Not implemented (always reads 0) * = Reserved (read/write, reset to 0) 0/1 = Reset to 0/1 by trailing edge of reset Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD) Revision 1.2 48 65540 / 545 (R) Register Summary 32-BIT EXTENSION REGISTER SUMMARY Reg DR00 DR01 DR02 DR03 DR04 DR05 DR06 DR07 Group BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Register Name BitBLT Offset BitBLT Pattern ROP BitBLT BG Color BitBLT FG Color BitBLT Control BitBLT Source BitBLT Destination BitBLT Command Bits 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 Access R/W R/W R/W R/W R/W R/W R/W R/W Port 83D0-3 87D0-3 8BD0-3 8FD0-3 93D0-3 97D0-3 9BD0-3 9FD0-3 - - - - xxxx -------xxxxxxxx xxxxxxxx ---------------------- - - - 0000 DR08 DR09 DR0A DR0B DR0C Cursor Cursor Cursor Cursor Cursor Cursor Control Cursor Color 0-1 Cursor Color 2-3 Cursor Position Cursor Base Address 16/32 16/32 16/32 16/32 16/32 R/W R/W R/W R/W R/W A3D0-3 A7D0-3 ABD0-3 AFD0-3 B3D0-3 -------- -------xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx x - - - - xxx xxxxxxxx - - - - - - - - - - - - xxxx Reset Codes: x d h r Revision 1.2 = = = = Not changed by reset (indeterminate on power-up) Set from configuration pin on trailing edge of reset Read-only Hercules Configuration Register Readback bits Chip revision # (starting from 0000) 49 Reset xxxxxxxx - - - - xxxx - - - xxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx - - - 0xxxx xxxxxxxx - - - xxxxx xxxxxxxx - - - xxxxx xxxxxxxx 00000000 - - - - xxxx * * * *0000 xxxxxxxx xxxxxxxx x - - - - xxx xxxxxx - - xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000 * * *00 xxxxxxxx xxxxxxxx xxxxxxxx -------- - = Not implemented (always reads 0) * = Not implemented (read/write, reset to 0) 0/1 = Reset to 0/1 by trailing edge of reset 65540 / 545 (R) Register Summary PCI CONFIGURATION REGISTER SUMMARY Reg VENID DEVID DEVCTL DEVSTAT Register Name Vendor ID Device ID Device Control Device Status Bits Access 16 R 16 R 16 R/W 16 R/C Offset 00h 02h 04h 06h REV PRG SUB BASE Revision Programming Interface Sub Class Code Base Class Code 8 8 8 8 R R R R 08h 09h 0Ah 0Bh MBASE IOBASE Memory Base Address I/O Base Address 32 32 R/W R/W 10h 14h Reset 00010000 00000000 - - - - - - 10 00000000 00101100 11011000 10000000 0-----------rrr 00000000 00000000 00000011 xxxxxxxx xxx - - - - - - - - - - - - xxxxxxxx xxxxxxxx xxxxxx - - - - - - 0000 - - - - - - 01 Note: R = Read, W = Write, C = Clear (1s written to specific bits will clear those bits) Revision 1.2 50 65540 / 545 (R) Registers Registers GLOBAL CONTROL (SETUP) REGISTERS CGA / HERCULES REGISTERS The Setup Control Register and Video Subsystem Enable registers are used to enable or disable the VGA. The Setup Control register is also used to place the VGA in normal or setup mode (the Global Enable Register is accessible only during Setup mode). The Setup Control register is used only in ISA bus interfaces; the Video Subsystem Enable register is used only in Local Bus configurations. The various internal 'disable' bits 'OR' together to provide multiple ways of disabling the chip; all 'disable' bits must be off to enable access to the chip. When the chip is 'disabled' in this fashion, only bus access is disabled; other functions remain operational (memory refresh, display refresh, etc.). CGA Mode and Color Select registers are provided on-chip for emulation of CGA modes. Hercules Mode and Configuration registers are provided onchip for emulation of Hercules mode. SEQUENCER REGISTERS The Sequencer Index Register contains a 3-bit index to the Sequencer Data Registers. The Reset Register forces an asynchronous or synchronous reset of the sequencer. The Sequencer Clocking Mode Register controls master clocking functions, video enable/disable and selects either an 8 or 9 dot character clock. A Plane/Map Mask Register enables the color plane and write protect. The Character Font Select Register handles video intensity and character generation and controls the display memory plane through the character generator select. The Sequencer Memory Mode Register handles all memory, giving access by the CPU to 4 / 16 / 32 KBytes, Odd / Even addresses (planes) and writing of data to display memory. Note: In setup mode in the IBM VGA, the Global Setup Register (defined as port address 102) actually occupies the entire I/O space . Only the lower 3 bits are used to decode and select this register. To avoid bus conflicts with other peripherals, reads should only be performed at the 10xh port addresses while in setup mode. To eliminate potential compatibility problems in widely varying PC systems, CHIPS' VGA controllers decode the Global Setup register at I/O port 102h only. CRT CONTROLLER REGISTERS The CRT Controller Index Register contains a 6-bit index to the CRT Controller Registers. Twenty one registers control various display functions: horizontal and vertical blanking and sync timing, panning and scrolling, cursor size and location, light pen, and text-mode underline. PCI CONFIGURATION REGISTERS (65545) For PCI bus configuration in the 65545, ten 16-bit registers are implemented to allow identification of the chip, examination of various internal states, configuration of memory and I/O base addresses, and control of settings for various modes of operation. These registers are located at various offsets into the PCI configuration space which may be I/O or memory mapped depending on the system design. GRAPHICS CONTROLLER REGISTERS The Graphics Controller Index Register contains a 4bit index to the Graphics Controller Registers. The Set/Reset Register controls the format of the CPU data to display memory. It also works with the Enable Set/Reset Register. Reducing 32 bits of display data to 8 bits of CPU data is accomplished by the Color Compare Register. Data Rotate Registers specify the CPU data bits to be rotated and subjected to logical operations. The Read Map Select Register reduces memory data for the CPU in the four plane (16 color) graphics mode. The Graphics Mode Register controls the write, read, and shift register modes. The Miscellaneous Register handles graphics/text, chaining of odd/even planes, and display memory mapping. Additional registers include Color Don't Care and Bit Mask. GENERAL CONTROL REGISTERS Two Input Status Registers read the SENSE function (Virtual Switch Register or internal RGB comparator output), pending CRT interrupt, display enable / horizontal sync output, and vertical retrace / video output. The Feature Control Register selects the vertical sync function while the Miscellaneous Output Register controls I/O address selection, clock selection, CPU access to display memory, display memory page selection, and horizontal and vertical sync polarity. Revision 1.2 51 65540 / 545 (R) Registers ATTRIBUTE CONTROLLER AND COLOR PALETTE REGISTERS 4. Clock Registers control the operation of the onchip clock synthesizer The Attribute Controller Index Register contains a 5bit index to the Attribute Controller Registers which consist of a 16-entry color lookup table with 6 bits per entry plus five additional control registers. A sixth index register bit is used to enable video. The Attribute Controller Registers handle color lookup table mapping, text/graphics mode control, overscan color selection, and color plane enabling. One register allows the display to be shifted left up to 8 pixels. Another register provides default values to extend the 6-bit lookup table values to 8 bits for modes providing less than 8 bits per pixel. 5. MultimediaRegisters control the operation of the video input port color key and mask 6. BitBLT Registers control the operation of the BitBlock-Transfer (BitBLT) engine (65545 only) for graphics acceleration. 7. Backwards Compatibility Registers control Hercules, MDA, and CGA emulation modes. Write Protect functions are provided to increase flexibility in providing backwards compatibility. 8. Alternate Horizontal and Vertical Registers handle all horizontal and vertical timing, including sync, blank and offset. These are used for backwards compatibility. The color palette registers control the interface to the on-chip color palette. This on-chip palette fully implements the functions of the VGA-standard palette (Inmos IMSG176, Brooktree BT471/476, or equivalent functionality). The color palette primarily consists of a 256-entry color lookup table (also sometimes referred to as a CLUT), a mask register, index registers used to access the CLUT data, and triple 6 / 8-bit DACs used to drive analog RGB outputs to a CRT monitor. Each entry in the CLUT is 18 bits in length (6 bits each for red, green, and blue) so each CLUT data entry must be accessed sequentially as 3 separate bytes and each DAC output operates with 6 bits of resolution. In 24-bpp "TrueColor" modes, the CLUT is bypassed and each DAC operates with 8-bit resolution. 9. Flat Panel Registers handle all internal logic specific to driving of flat panel displays. 32-BIT REGISTERS The 65545 also implements a group of sixteen 32-bit doubleword extension registers (called "DR's"). These registers are used for control of the high performance BitBLT and Hardware Cursor subsystems and may be mapped anywhere in the I/O and/or memory address space. For ISA and VL-Bus configurations, the 32-bit registers take up 32 doubleword locations in the 16bit I/O address space (only the first 13 registers are defined; the remaining locations are reserved). An 8-bit extension register is provided to program the base address. The address is of the form "bnnn nn1b bbbb bbxx" (where b specifies the value programmed into the base register and 'n' selects one of the 32 register locations). The base register is typically programmed with '74h' to map the 32-bit registers to I/O addresses x3D0-x3D3h (unused ports in the standard VGA I/O address range). EXTENSION REGISTERS The 65540 / 545 defines a set of extension registers (called "XR's") which are addressed with the 7-bit Extension Register Index. The I/O port address is fixed at 3D6-3D7h and read/write access is always enabled to improve software performance. The extension registers handle a variety of interfacing, compatibility, and display functions as discussed below. They are grouped into the following logical groups for discussion purposes: For PCI bus configurations, the 32-bit registers are mapped to both the memory and I/O address spaces. The PCI configuration registers contain an I/O base register which defines a 1KB space (256 doublewords) which allows the 32-bit register space to start on any 1KB boundary in the I/O address space. In addition, the PCI memory base register specifies an 8MB memory address space; display memory is mapped into the lower 2 megabytes and the 32-bit registers are mapped into the upper 6 megabytes. 1. Miscellaneous Registers include the chip version/revision, configuration, and various interface control and diagnostic functions. 2. Mapping Registers include paging controls and base registers for relocation of I/O and memory blocks. 3. Software Flags Registers provide locations for BIOS and driver software to store various temporary variable values on-chip Note: The state of most of the standard VGA registers is undefined at reset. The state at Reset of all registers specific to the 65540 / 545 (extension registers and 32-bit registers) is summarized in the register summary tables. Revision 1.2 52 65540 / 545 (R) Global Control (Setup) Registers Global Control (Setup) Registers Register Mnemonic Register Name SETUP VSE ENAB Setup Control Video Subsystem Enable Global Enable Index Access I/O I/O Address Page - - - W W RW 46E8h (ISA Bus Only) 3C3h (Local Bus Only) 102h (ISA Bus / Setup Mode Only) 53 53 54 SETUP CONTROL REGISTER (SETUP) Write only at I/O Address 46E8h VIDEOSUBSYSTEMENABLEREGISTER(VSE) Write Only at I/O Address 3C3h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 VGA Sleep Reserved(0) VGA Enable VGA Setup Reserved(0) Reserved(0) This register is effective in ISA bus configuration only and is not used in local bus or PCI bus configurations. In ISA bus configuration, this register is ignored if XR70 bit-7 is set to 1 (the default is 0). This register is accessible in Local Bus configurations only. It is ignored in ISA bus configurations (registers 102h and 46E8h are used in ISA bus configurations to control VGA enable and disable). Access to this register may be disabled by setting XR70 bit-7 to 1 (the default is 0). In local bus configurations, the VGA may be enabled and disabled using register 3C3. In PCI bus configurations (65545), the VGA may be enabled and disabled via the PCI configuration registers. Setup mode is available only in ISA bus configuration via this register. This register is cleared by RESET to disable the VGA. In this state, only register 3C3 is accessible (the other registers in the VGA I/O address range will be inaccessible and read or write accesses to VGA I/O addresses other than 3C3 will be ignored) until bit-0 of this register is set to 1. This register is cleared by RESET. 2-0 3 4 7-5 In PCI bus configurations, VGA enable and disable are controlled via the PCI configuration registers and this register is ignored. Reserved (0) VGA Enable 0 VGA is disabled 1 VGA is enabled Setup Mode 0 VGA is in Normal Mode 1 VGA is in Setup Mode Reserved (0) Revision 1.2 0 7-1 53 VGA Sleep 0 VGA is disabled 1 VGA is enabled Reserved (0) 65540 / 545 (R) Global Control (Setup) Registers GLOBAL ENABLE REGISTER ( ENAB ) Read/Write at I/O Address 102h D7 D6 D5 D4 D3 D2 D1 D0 VGA Sleep Reserved(0) This register is accessible only in setup mode (46E8 bit-4 = 1). If the VGA is not in setup mode (46E8 bit-4 = 0), attempts to access this register are ignored. Bit-0 of this register is cleared by RESET in ISA bus configurations to disable the VGA (all VGA memory and I/O addresses except 102h and 46E8h are ignored). Bit-0 of this register is AND'ed with bit-3 of register 46E8: the VGA is enabled only if both bits are set. If the VGA is disabled, only register 46E8 is accessible. 0 7-1 VGA Sleep 0 VGA is disabled 1 VGA is enabled Reserved (0) Revision 1.2 54 65540 / 545 (R) PCI Configuration Registers PCI Configuration Registers Register Mnemonic Register Name VENID DEVID DEVCTL DEVSTAT REV PRG SUB BASE Vendor ID DeviceID DeviceControl Device Status Revision Programming Interface Sub Class Code Base Class Code 00h 02h 04h 06h 08h 09h 0Ah 0Bh R R R/W R/C R R R R MBASE IOBASE Memory Base Address I/O Base Address 10h 14h R/W xxxx xxxx xxx0 0000 0000 0000 0000 0000 58 R/W xxxx xxxx xxxx xxxx xxxx xx00 0000 0001 58 Offset Access Reset State Page 0001 0000 0010 1100 0000 0000 1101 1000 0000 0010 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0011 55 55 56 56 57 57 57 57 Note: 'Access' codes are R=Read, W=Write, and C=Clear (writing a 1 to a bit clears that bit) VENDOR ID REGISTER (VENID) Read/Only at PCI Configuration Offset 00h Byte or Word Accessible Accessible in PCI Bus Configuration Only DEVICE ID REGISTER (DEVID) Read/Only at PCI Configuration Offset 02h Byte or Word Accessible Accessible in PCI Bus Configuration Only 15 15 0 0 Vendor ID Device ID 15-0 Vendor ID 15-0 Device ID Read-Only. Always returns 102Ch (4140d) Revision 1.2 Read-Only. Always returns 00D8h 55 65540 / 545 (R) PCI Configuration Registers DEVICE CONTROL REGISTER ( DEVCTL ) DEVICE STATUS REGISTER ( DEVSTAT ) Read/Write at PCI Configuration Offset 04h Byte or Word Accessible Accessible in PCI Bus Configuration Only Read/Only at PCI Configuration Offset 06h Byte or Word Accessible Accessible in PCI Bus Configuration Only 15 15 0 0 I/O Access Ena Mem Access Ena Always Read 0 Undefined(0) Palette Snoop Ena PERR# Enable Always Reads 1 SERR# Enable Always Reads 1 Always Reads 1 Always Reads 0 DEVSEL# Timing (Always Reads 10) Target Abort Sig'd Always Reads 0 Always Reads 0 Sys Err Signaled Parity Err Detected Undefined(0) 0 1 2 3 4 5 6 7 8 I/O Access Enable When set, the chip will respond to I/O cycles for addresses within the range specified by the IOBASE register. 6-0 7 Fast Back-to-Back Capable ( 1 ) 8 Data Parity Error Detect (0) Implemented by bus masters only. Memory Access Enable When set, the chip will respond to memory cycles for addresses within the range specified by the MBASE register. 10-9 DEVSEL# Timing Always responds '10' (Slow) Bus Master ( Always Reads 0 ) Special Cycles ( Always Reads 0 ) Mem Write & Invalidate ( Always Reads 0 ) Palette Snoop Enable When set, the chip will not respond to VGA Palette Accesses. Reads will be ignored but writes will still update the internal palette. 11 PERR# Enable Set to enable PERR# response for detected data parity errors. 12 Target Abort Signaled Set whenever a Target Abort is generated on the bus. This can happen under the following conditions: 1) Command/Address cycle parity error 2) Invalid byte enables received 3) VGA core unable to complete a cycle Received Target Abort (0) Implemented by bus masters only. 13 Wait Cycle Control ( Always Reads 1 ) SERR# Enable Set to enable SERR# response for detected address / command parity errors. The chip will also generate a Target Abort. Master Abort (0) Implemented by bus masters only. 14 System Error Signaled Set whenever SERR# is asserted. 15 9 Fast Back-to-Back Enable for Masters (Always Reads 0) 15-10 Undefined / Reserved ( 0 ) Revision 1.2 Undefined / Reserved ( 0 ) Parity Error Detected Set when data parity error is detected even if PERR# response disabled (DEVCTL bit-6) 56 65540 / 545 (R) PCI Configuration Registers REVISION REGISTER ( REV ) SUB CLASS CODE REGISTER ( SUB ) Read/Only at PCI Configuration Offset 08h ByteAccessible Accessible in PCI Bus Configuration Only Read/Only at PCI Configuration Offset 0Ah ByteAccessible Accessable in PCI Bus Configuration Only D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Chip Revision Code 2-0 7-3 Sub-Class Code Chip Revision Code These bits match XR00 bits 2-0. Revision codes start at 0 and are incremented for each silicon revision. 7-0 Sub-Class Code This register always returns a value of 00h to indicate "VGA Compatible Controller". Reserved (0) These bits are defined by the PCI 2.0 specification as additional revision code bits. They always read zero. PROGRAMMINGINTERFACEREGISTER(PRG) Read/Only at PCI Configuration Offset 09h ByteAccessible Accessable in PCI Bus Configuration Only BASE CLASS CODE REGISTER ( BASE ) Read/Only at PCI Configuration Offset 0Bh ByteAccessible Accessable in PCI Bus Configuration Only D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Programming Interface Code 7-0 Base Class Code Programming Interface Code 7-0 This register always returns a value of 00h (no special register-level device-independent interface definition is defined). Revision 1.2 Base Class Code This register always returns a value of 03h to indicate base class "Display Controller". 57 65540 / 545 (R) PCI Configuration Registers MEMORY BASE REGISTER ( MBASE ) I/O BASE REGISTER ( IOBASE ) Read/Write at PCI Configuration Offset 10h Byte, Word, or DoubleWord Accessible Accessable in PCI Bus Configuration Only Read/Write at PCI Configuration Offset 14h Byte, Word, or DoubleWord Accessible Accessable in PCI Bus Configuration Only 31 31 2322 4 32 1 0 10 9 2 1 0 0 (Memory Space) 1 (I/O Space) 0(Reserved) 00 (32-bit Address) 0 (No Prefetching) 0 (Address Mask) (1KB Range) 0 (Address Mask) (8MB Range) I/O Base Address Memory BaseAddress 0 Memory / IO Space (0) 0 Always returns 0 to indicate memory space 2-1 Always returns 1 to indicate I/O space Memory Type (00) 1 Always return 0 to indicate 32-bit address 3 9-2 Prefetchable Memory (0) 22-4 Address Mask (0) R/W in bits 10 and above to indicate a 1KB address range for the 32-bit registers (DRxx registers). The actual value programmed in this field determines the start of the range in the 32-bit I/O address space. For example: 31-23 Memory Base Address R/W in bits 23 and above to indicate an 8MB address range. The lower 2MB is for video memory and the rest is for memory mapped IO. The actual value programmed in this field determines the start of the range in the 32-bit memory address space. For example: Note: Value Programmed 000000h 000001h 000002h 000003h 000004h ... Memory Address Range IllegalSetting 00800000h - 00FFFFFFh 01000000h - 017FFFFFh 01800000h - 01FFFFFFh 02000000h - 027FFFFFh 02800000h - 02FFFFFFh ... XR08 provides the same function for ISA/VL. It is ignored in PCI bus mode. Revision 1.2 Address Mask (0) 31-10 I/O Base Address Always returns 0 to indicate an 8MB range 0: 8MB: 16MB: 24MB: 32MB: 40MB: ... Undefined / Reserved (0) All bits in in this field return 0 to indicate a 1KB I/O address range Always return 0 to prevent prefetching Value Programmed 000000000b 000000001b 000000010b 000000011b 000000100b 000000101b ... Memory / IO Space (1) 58 I/O Address Range IllegalSetting 00000400h - 000007FFh 00000800h - 00000BFFh 00000C00h - 00000FFFh 00001000h - 000013FFh ... Note: XR07 provides the same function for ISA/VL. It is ignored in PCI bus mode. Note: In PCI bus configuration, the DR registers may also be memory mapped to the upper megabyte of the 2MB memory space (see MBASE). 65540 / 545 (R) General Control Registers General Control & Status Registers Register Mnemonic Register Name Index Access I/O Address Protect Group Page ST00 ST01 FCR Input Status 0 Input Status 1 Feature Control - - - 59 59 60 MiscellaneousOutput - 3C2h 3BAh/3DAh 3BAh/3DAh 3CAh 3C2h 3CCh - - 5 MSR R R W R W R 5 60 INPUT STATUS REGISTER 0 ( ST00 ) Read only at I/O Address at 3C2h INPUT STATUS REGISTER 1 ( ST01 ) Read only at I/O Address 3BAh/3DAh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DE/Hsync Output Reserved(0) Reserved(0) VerticalRetrace/Video RGB Comparator / Sense VideoFeedback Reserved(0) VSync Output Reserved(0) CRT Interrupt Pending 3-0 4 0 Reserved (0) The functionality of this bit is controlled by the Emulation Mode register (XR14 bit-4). RGB Comparator / Sense This bit returns the state of the output of the RGB output comparator or the output of the Virtual Switch Register (XR1F bit 0, 1, 2, or 3) if enabled by XR1F bit-7. 6-5 7 Display Enable/HSYNC Output 0 Indicates DE or HSYNC inactive 1 Indicates DE or HSYNC active 2-1 3 Reserved (0) Reserved (0) Vertical Retrace/Video The functionality of this bit is controlled by the Emulation Mode register (XR14 bit-5). 0 Indicates VSYNC or video inactive 1 Indicates VSYNC or video active CRT Interrupt Pending 0 Indicates no CRT interrupt is pending 1 Indicates a CRT interrupt is waiting to be serviced 5-4 Video Feedback 1, 0 These are diagnostic video bits which are selected via the Color Plane Enable Register. 6 7 Reserved (0) VSync Output The functionality of this bit is controlled by the Emulation Mode register (XR14 bit-6). It reflects the active status of the VSYNC output: 0=inactive, 1=active. Revision 1.2 59 65540 / 545 (R) General Control Registers FEATURE CONTROL REGISTER ( FCR ) Write at I/O Address 3BAh/3DAh Read at I/O Address 3CAh Group 5 Protection MISCELLANEOUSOUTPUTREGISTER(MSR) Write at I/O Address 3C2h Read at I/O Address 3CCh Group 5 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Feature Control I/O Address Select RAM Enable Reserved(0) VSync Control Clock Select Reserved(0) Page Select HSync Polarity VSync Polarity Reserved(0) 1-0 2 3 7-4 Feature Control These bits are used internal to the chip in conjunction with the Configuration Register (XR01). When enabled by XR01 bits 2-3 and Misc Output Register bits 3-2 = 10, these bits determine the pixel clock frequency typically as follows: FCR1:0 = 00 = 40.000 MHz FCR1:0 = 01 = 50.350 MHz FCR1:0 = 10 = User defined FCR1:0 = 11 = 44.900 MHz This preserves compatibility with drivers developed for earlier generation Chips and Technologies VGA controllers. Reserved (0) VSync Control This bit is cleared by RESET. 0 VSync output on the VSYNC pin 1 Logical 'OR' of VSync and Display Enable output on the VSYNC pin This capability is not typically very useful, but is provided for IBM compatibility. Reserved (0) This register is cleared by RESET. 0 I/O Address Select This bit selects 3Bxh or 3Dxh as the I/O address for the CRT Controller registers, the Feature Control Register (FCR), and Input Status Register 1 (ST01). 0 Select 3Bxh I/O address 1 Select 3Dxh I/O address 1 RAM Enable 0 Prevent CPU access to display memory 1 Allow CPU access to display memory 3-2 Clock Select. These bits usually select the dot clock source for the CRT interface: MSR3:2 = 00 = Select CLK0 MSR3:2 = 01 = Select CLK1 MSR3:2 = 10 = Select CLK2 MSR3:2 = 11 = Select CLK3 See extension register XR01 bits 2-3 (Configuration) and FCR bits 0-1 for variations of the above clock selection mapping. See also XR1F (Virtual Switch Register) for additional functionality potentially controlled by these bits. 4 Reserved (0) 5 Page Select. In Odd/Even Memory Map Mode 1 (GR6), this bit selects the upper or lower 64 KByte page in display memory for CPU access: 0=select upper page; 1=select lower page. 6 CRT HSync Polarity. 0=pos, 1=neg 7 CRT VSync Polarity. 0=pos, 1=neg (Blank pin polarity can be controlled via the Video Interface Register, XR28). XR55 bits 6-7 are used to control H/V sync polarity instead of these bits if XR51 bit-2 = 1 (display type = flat panel). CRT Display Sync Polarities V H Display HFreq VFreq P P >480 Line Variable Variable P P 200 Line 15.7 KHz 60 Hz N P 350 Line 21.8 KHz 60 Hz P N 400 Line 31.5 KHz 70 Hz N N 480 Line 31.5 KHz 60 Hz Revision 1.2 60 65540 / 545 (R) CGA / Hercules Registers CGA / Hercules Registers Register Mnemonic RegisterName MODE COLOR HCFG CGA/Hercules Mode CGA Color Select Hercules Configuration Index Access I/O Address Protect Group Page - - - R/W R/W R/W 3D8h 3D9h 3BFh - - - 61 62 62 CGA / HERCULES MODE CONTROL REGISTER ( MODE ) Read/Write at I/O Address 3B8h/3D8h 2 D7 D6 D5 D4 D3 D2 D1 D0 3 0 1 4 This register is effective only in CGA and Hercules modes. It is accessible if CGA or Hercules emulation mode is selected or the extension registers are enabled. If the extension registers are enabled, the address is determined by the address select in the Miscellaneous Outputs register. Otherwise the address is determined by the emulation mode. It is cleared by RESET. 1 CGA/Hercules Graphics/Text Mode Select 320x200 graphics mode Select 640x200 graphics mode CGA/Hercules Text Blink Enable 0 Disable character blink attribute (blink attribute bit-7 used to control background intensity) 1 Enable character blink attribute 6 Reserved (0) 7 Hercules Page Select 0 Select the lower part of memory (starting address B0000h) in Hercules Graphics Mode 1 Select the upper part of the memory (starting address B8000h) in Hercules Graphics Mode CGA 80/40 Column Text Mode 0 Select 40 column CGA text mode 1 Select 80 column CGA text mode Blank the screen Enable video output CGA High Resolution Mode 0 1 5 Select CGA color mode Select CGA monochrome mode CGA/Hercules Video Enable 0 1 HiRes Text (CGA only) Graphics Mode (0=Text) Monochrome (CGA only) Video Enable HiRes Graphics (CGA only) Text Blink Enable Reserved(0) Page Select (Herc only) 0 CGA Mono/Color Mode 0 Select text mode 1 Select graphics mode Revision 1.2 61 65540 / 545 (R) CGA / Hercules Registers CGA COLOR SELECT REGISTER (COLOR) Read/Write at I/O Address 3D9h HERCULES CONFIGURATION REGISTER ( HCFG ) Write only at I/O Address 3BFh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Enable Graphics Mode Enable Memory Page 1 Color bit-0 (Blue) Color bit-1 (Green) Color bit-2 (Red) Color bit-3 (Intensity) Intensity Enable Color Set Select Reserved(0) Reserved(0) This register is effective only in CGA modes. It is accessible if CGA emulation mode is selected or the extension registers are enabled. This register may also be read or written as an Extension Register (XR7E). It is cleared by Reset. 3-0 This register is effective only in Hercules mode. It is accessible in Hercules emulation mode or if the extension registers are enabled. It may be read back through XR14 bits 2 & 3. It is cleared by Reset. 0 Color Enable Graphics 0 Lock the chip in Hercules text mode. In this mode, the CPU has access only to memory address range B0000hB7FFFh (in text mode the same area of display memory wraps around 8 times within this range such that B0000 accesses the same display memory location as B1000, B2000, etc.). 1 Permit entry to Hercules Graphics mode 320x200 4-color: Background Color (color when the pixel value is 0) The foreground colors (colors when the pixel value is 1-3) are determined by bit-5 of this register. 640x200 2-color: Foreground Color (color when the pixel value is 1) The background color (color when the pixel value is 0) is black. 4 Text Mode: 320x200 4-color: 640x200 2-color: 5 1 Intensity Enable Enables intensified background colors Enables intensified colors 0-3 Don't care Color Set Select This bit selects one of two available CGA color palettes to be used in 320x200 graphics mode (it is ignored in all other modes) according to the following table: Pixel Value 0 0 1 1 7-6 0 1 0 1 Color Set 0 Color Set 1 Color per bits 0-3 Green Red Brown Color per bits 0-3 Cyan Magenta White 7-2 Mode Enable Memory Page 1 0 Prevent setting of the Page Select bit (bit 7 of the Hercules Mode Control Register). This function also restricts memory usage to addresses B0000hB7FFFh. 1 The Page Select bit can be set and the upper part of display memory (addresses B8000h - BFFFFh) is available. Reserved (0) Reserved(0) Revision 1.2 62 65540 / 545 (R) Sequencer Registers Sequencer Registers Register Mnemonic Register Name SRX SR00 SR01 SR02 SR03 SR04 SR07 Sequencer Index Reset Clocking Mode Plane/MapMask Character Font Memory Mode Horizontal Character Counter Reset Index Access I/O Address - 00h 01h 02h 03h 04h 07h R/W R/W R/W R/W R/W R/W W 3C4h 3C5h 3C5h 3C5h 3C5h 3C5h 3C5h Protect Group Page 1 1 1 1 1 1 - SEQUENCER INDEX REGISTER (SRX) Read/Write at I/O Address 3C4h SEQUENCER RESET REGISTER (SR00) Read/Write at I/O Address 3C5h Index 00h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SequencerIndex Async Reset Sync Reset Reserved(0) Reserved(0) 0 This register is cleared by reset. 2-0 Sequencer Index These bits contain a 3-bit Sequencer Index value used to access sequencer data registers at indices 0 through 7. 7-3 Asynchronous Reset 0 Force asynchronous reset 1 Normal operation Display memory data will be corrupted if this bit is set to zero. 1 Reserved (0) 7-2 Revision 1.2 63 63 64 64 65 66 66 63 Synchronous Reset 0 Force synchronous reset 1 Normal operation Display memory data is not corrupted if this bit is set to zero for a short period of time (a few tenths of a microsecond). See also XR0E. Reserved (0) 65540 / 545 (R) Sequencer Registers SEQUENCER CLOCKING MODE REGISTER (SR01) Read/Write at I/O Address 3C5h Index 01h Group 1 Protection SEQUENCER PLANE/MAP MASK REGISTER (SR02) Read/Write at I/O Address 3C5h Index 02h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 8/9 Dot Clocks Reserved(0) Shift Load Input Clock Divide Shift 4 Screen Off Color Plane Enable Reserved(0) Reserved(0) 0 8/9 Dot Clocks 3-0 This bit determines whether a character clock is 8 or 9 dot clocks long. 0 Select 9 dots/character clock 1 Select 8 dots/character clock 1 Reserved (0) 2 Shift Load 0 Load video data shift registers every characterclock 1 Load video data shift registers every other character clock Color Plane Enable 0 1 Write protect corresponding color plane Allow write to corresponding color plane. In Odd/Even and Quad modes, these bits still control access to the corresponding color plane. 7-4 Reserved (0) Bit-4 of this register must be 0 for this bit to be effective. 3 Input Clock Divide 0 Sequencer master clock output on the PCLK pin (used for 640 (720) pixel modes) 1 Master clock divided by 2 output on the PCLK pin (used for 320 (360) pixel modes) 4 Shift 4 0 Load video shift registers every 1 or 2 character clocks (depending on bit-2 of this register) 1 Load shift registers every 4th character clock. 5 Screen Off 0 Normal Operation 1 Disable video output and assign all display memory bandwidth for CPU accesses Reserved (0) 7-6 Revision 1.2 64 65540 / 545 (R) Sequencer Registers CHARACTER FONT SELECT REGISTER (SR03) Read/Write at I/O Address 3C5h Index 03h Group 1 Protection The following table shows the display memory plane selected by the Character Generator Select A and B bits. Code 0 1 2 3 4 5 6 7 D7 D6 D5 D4 D3 D2 D1 D0 Font Select B bit-1 Font Select B bit-2 Font Select A bit-1 Font Select A bit-2 Font Select B bit-0 Font Select A bit-0 Character Generator Table Location First 8K of Plane 2 Second 8K of Plane 2 Third 8K of Plane 2 Fourth 8K of Plane 2 Fifth 8K of Plane 2 Sixth 8K of Plane 2 Seventh 8K of Plane 2 Eighth 8K of Plane 2 where 'code' is: Character Generator Select A (bits 3, 2, 5) when bit-3 of the attribute byte is one. Character Generator Select B (bits 1, 0, 4) when bit-3 of the attribute byte is zero. Reserved(0) In text modes, bit-3 of the video data's attribute byte normally controls the foreground intensity. This bit may be redefined to control switching between character sets. This latter function is enabled whenever there is a difference in the values of the Character Font Select A and the Character Font Select B bits. If the two values are the same, the character select function is disabled and attribute bit-3 controls the foreground intensity. SR04 bit-1 must be 1 for the character font select function to be active. Otherwise, only character fonts 0 and 4 are available. 1-0 High order bits of Character Generator Select B 3-2 High order bits of Character Generator Select A 4 Low order bit of Character Generator Select B 5 Low order bit of Character Generator SelectA 7-6 Reserved (0) Revision 1.2 65 65540 / 545 (R) Sequencer Registers SEQUENCER MEMORY MODE REGISTER (SR04) Read/Write at I/O Address 3C5h Index 04h Group 1 Protection SEQUENCER HORIZONTAL CHARACTER COUNTER RESET (SR07) Read/Write at I/O Address 3C5h Index 07h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved(0) ExtendedMemory Odd/EvenMode Quad Four Mode Don't Care Reserved(0) 0 Reserved (0) 1 Extended Memory Writing to SR07 with any data will cause the horizontal character counter to be held reset (character counter output = 0) until a write to any other sequencer register with any data value. The write to any index in the range 0-6 clears the latch that is holding the reset condition on the character counter. 0 Restrict CPU access to 4 / 16 / 32 KBytes 1 Allow complete access to memory This bit should normally be 1. 2 The vertical line counter is clocked by a signal derived from horizontal display enable (which does not occur if the horizontal counter is held reset). Therefore, if the write to SR07 occurs during vertical retrace, the horizontal and vertical counters will both be set to zero. A write to any other sequencer register may then be used to start both counters with reasonable synchronization to an external event via software control. Odd/Even Mode 0 CPU accesses to Odd/Even addresses are directed to corresponding odd/even planes 1 All planes are accessed simultaneously (IRGB color) Bit-3 of this register must be 0 for this bit to be effective. This bit affects only CPU write accesses to display memory. 3 This is a standard VGA register which was not documented by IBM. Quad Four Mode 0 CPU addresses are mapped to display memory as defined by bit-2 of this register 1 CPU addresses are mapped to display memory modulo 4. The two low order CPU address bits select the display memory plane. This bit affects both CPU reads and writes to display memory. 7-4 Reserved (0) Revision 1.2 66 65540 / 545 (R) CRT Controller Registers CRT Controller Registers Register Mnemonic Register Name Index Access I/O Address CRX CR00 CR01 CR02 CR03 CR04 CR05 CR06 CR07 CR08 CR09 CR0A CR0B CR0C CR0D CR0E CR0F CR10 CR11 CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR22 CR24 CRTC Index HorizontalTotal Horizontal Display Enable End Horizontal Blank Start Horizontal Blank End Horizontal Sync Start Horizontal Sync End VerticalTotal Overflow Preset Row Scan Maximum Scan Line Cursor Start Scan Line Cursor End Scan Line Start Address High Start Address Low Cursor Location High Cursor Location Low Vertical Sync Start (See Note 2) Vertical Sync End (See Note 2) Lightpen High (See Note 2) Lightpen Low (See Note 2) Vertical Display Enable End Offset Underline Row Vertical Blank Start Vertical Blank End CRT Mode Control Line Compare Memory Data Latches Attribute Controller Toggle - 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 10h 11h 12h 13h 14h 15h 16h 17h 18h 22h 24h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W or R/W W or R/W R R R/W R/W R/W R/W R/W R/W R/W R R 3B4h/3D4h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h Protect Group Page - 0 0 0 0 0 0 0 0/3 3 2/4 2 2 - - - - 4 3/4 - - 4 3 3 4 4 3/4 3 - - 68 68 68 69 69 70 70 71 71 72 72 73 73 74 74 74 74 75 75 75 75 76 76 76 77 77 78 79 80 80 Note 1: When MDA or Hercules emulation is enabled, the CRTC I/O address should be set to 3B0h-3B7h by setting the I/O address select bit in the Miscellaneous Output register (3C2h/3CCh bit-0) to zero. When CGA emulation is enabled, the CRTC I/O address should be set to 3D0h-3D7h by setting Misc Output Register bit-0 to 1. Note 2: In the EGA, all CRTC registers except the cursor (CR0C-CR0F) and light pen (CR10 and CR11) registers are write-only (i.e., no read back). In both the EGA and VGA, the light pen registers are at index locations conflicting with the vertical sync registers. This would normally prevent reads and writes from occurring at the same index. Since the light pen registers are not normally useful, the VGA provides software control (CR03 bit-7) of whether the vertical sync or light pen registers are readable at indices 10-11. Revision 1.2 67 65540 / 545 (R) CRT Controller Registers CRTC INDEX REGISTER (CRX) Read/Write at I/O Address 3B4h/3D4h HORIZONTAL DISPLAY ENABLE END REGISTER (CR01) Read/Write at I/O Address 3B5h/3D5h Index 01h Group 0 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CRTC Index Horizontal Display Reserved(0) 5-0 CRTC Data Register Index 7-6 Reserved (0) This register is used for all VGA and EGA modes on CRTs. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. HORIZONTAL TOTAL REGISTER (CR00) Read/Write at I/O Address 3B5h/3D5h Index 00h Group 0 Protection 7-0 Horizontal Display Number of Characters displayed per scan line - 1. D7 D6 D5 D4 D3 D2 D1 D0 Horizontal Total This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 7-0 Horizontal Total Total number of character clocks per line = contents of this register + 5. This register determines the horizontal sweep rate. Revision 1.2 68 65540 / 545 (R) CRT Controller Registers HORIZONTAL BLANK START REGISTER (CR02) Read/Write at I/O Address 3B5h/3D5h Index 02h Group 0 Protection HORIZONTAL BLANK END REGISTER (CR03) Read/Write at I/O Address 3B5h/3D5h Index 03h Group 0 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 H Blank End H Blank Start DE Skew Control Light Pen Register Enable This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 7-0 This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. Horizontal Blank Start 4-0 These bits specify the beginning of horizontal blank in terms of character clocks from the beginning of the display scan. The period between Horizontal Display Enable End and Horizontal Blank Start is the right side border on screen. Horizontal Blank End These are the lower 5 bits of the character clock count used to define the end of horizontal blank. The interval between the end of horizontal blank and the beginning of the display (a count of 0) is the left side border on the screen. If the horizontal blank width desired is W clocks, the 5-bit value programmed in this register = [contents of CR02 + W] and 1Fh. The most significant bit is programmed in CR05 bit-7. This bit = [( CR02 + W) and 20h]/20h. 6-5 Display Enable Skew Control Defines the number of character clocks that the Display Enable signal is delayed to compensate for internal pipeline delays. 7 Light Pen Register Enable This bit must be 1 for normal operation; when this bit is 0, CRTC registers CR10 and CR11 function as lightpen readback registers. Revision 1.2 69 65540 / 545 (R) CRT Controller Registers HORIZONTAL SYNC START REGISTER (CR04) Read/Write at I/O Address 3B5h/3D5h Index 04h Group 0 Protection HORIZONTAL SYNC END REGISTER (CR05) Read/Write at I/O Address 3B5h/3D5h Index 05h Group 0 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Horizontal Sync End Horizontal Sync Start Horizontal Sync Delay H Blank End Bit 5 This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 7-0 This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. Horizontal Sync Start 4-0 These bits specify the beginning of HSync in terms of Character clocks from the beginning of the display scan. These bits also determine display centering on the screen. Horizontal Sync End Lower 5 bits of the character clock count which specifies the end of Horizontal Sync. If the horizontal sync width desired is N clocks, then these bits = (N + contents of CR04) and 1Fh. 6-5 Horizontal Sync Delay These bits specify the number of character clocks that the Horizontal Sync is delayed to compensate for internal pipeline delays. 7 Horizontal Blank End Bit 5 This bit is the sixth bit of the Horizontal Blank End Register (CR03). Revision 1.2 70 65540 / 545 (R) CRT Controller Registers VERTICAL TOTAL REGISTER (CR06) Read/Write at I/O Address 3B5h/3D5h Index 06h Group 0 Protection OVERFLOW REGISTER (CR07) Read/Write at I/O Address 3B5h/3D5h Index 07h Group 0 Protection on bits 0-3 and bits 5-7 Group 3 Protection on bit 4 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 V Total Bit 8 V DE End Bit 8 V Sync Start Bit 8 V Blank Start Bit 8 Line Compare Bit 8 V Total Bit 9 V DE End Bit 9 V Sync Start Bit 9 V Total (Scan Lines) (Lower 8 Bits) This register is used in all modes. 7-0 This register is used in all modes. Vertical Total 0 Vertical Total Bit 8 These are the 8 low order bits of a 10-bit register. The 9th and 10th bits are located in the CRT Controller Overflow Register. The Vertical Total value specifies the total number of scan lines (horizontal retrace periods) per frame. 1 Vertical Display Enable End Bit 8 2 Vertical Sync Start Bit 8 3 Vertical Blank Start Bit 8 4 Line Compare Bit 8 5 Vertical Total Bit 9 6 Vertical Display Enable End Bit 9 7 Vertical Sync Start Bit 9 Programmed Count = Actual Count - 2 Revision 1.2 71 65540 / 545 (R) CRT Controller Registers PRESET ROW SCAN REGISTER (CR08) Read/Write at I/O Address 3B5h/3D5h Index 08h Group 3 Protection MAXIMUM SCAN LINE REGISTER (CR09) Read/Write at I/O Address 3B5h/3D5h Index 09h Group 2 Protection on bits 0-4 Group 4 Protection on bits 5-7 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 4-0 Start Row Scan Count Scan Lines Per Row Byte Panning Control Reserved(0) V Blank Start Bit 9 Line Compare Bit 9 Double Scan Start Row Scan Count 4-0 These bits specify the starting row scan count after each vertical retrace. Every horizontal retrace increments the character row scan line counter. The horizontal row scan counter is cleared at maximum row scan count during active display. This register is used for soft scrolling in text modes. 6-5 These bits specify the number of scan lines in a row: Programmed Value = Actual Value - 1 Byte Panning Control Vertical Blank Start Register Bit 9 6 Line Compare Register Bit 9 7 Double Scan The vertical parameters in the CRT Controller (even for a split screen) are not affected, only the CRTC row scan counter (bits 0-4 of this register) and display memory addressing screen refresh are affected. Reserved (0) Revision 1.2 5 0 Normal Operation 1 Enable scan line doubling These bits specify the lower order bits for the display start address. They are used for horizontal panning in Odd/Even and Quad modes. 7 Scan Lines Per Row 72 65540 / 545 (R) CRT Controller Registers CURSOR START SCAN LINE REGISTER CR0A) Read/Write at I/O Address 3B5h/3D5h Index 0Ah Group 2 Protection CURSOR END SCAN LINE REGISTER (CR0B) Read/Write at I/O Address 3B5h/3D5h Index 0Bh Group 2 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Cursor Start Scan Line Cursor End Scan Line Cursor off Cursor Delay Reserved(0) Reserved(0) 4-0 Cursor Start Scan Line 4-0 These bits specify the scan line of the character row where the cursor display begins. 5 7-6 Cursor End Scan Line These bits specify the scan line of a character row where the cursor display ends (i.e., last scan line for the block cursor): Programmed Value = Actual Value + 1 Cursor Off 0 Text Cursor On 1 Text Cursor Off 6-5 Cursor Delay These bits define the number of character clocks that the cursor is delayed to compensate for internal pipeline delay. Reserved (0) 7 Reserved (0) Note: If the Cursor Start Line is greater than the Cursor End Line, then no cursor is generated. Revision 1.2 73 65540 / 545 (R) CRT Controller Registers START ADDRESS HIGH REGISTER (CR0C) Read/Write at I/O Address 3B5h/3D5h Index 0Ch CURSORLOCATIONHIGHREGISTER(CR0E) Read/Write at I/O Address 3B5h/3D5h Index 0Eh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Display Start Address High (Upper 8 bits) 7-0 Text Cursor Address (Upper 8 bits) Display Start Address High 7-0 This register contains the upper 8 bits of the display start address. In CGA / MDA / Hercules modes, this register wraps around at the 16K, 32K, and 64KByte boundaries respectively. Text Cursor Location High This register contains the upper 8 bits of the memory address where the text cursor is active. In CGA / MDA / Hercules modes, this register wraps around at 16K, 32K, and 64KByte boundaries respectively. START ADDRESS LOW REGISTER (CR0D) Read/Write at I/O Address 3B5h/3D5h Index 0Dh CURSORLOCATIONLOWREGISTER(CR0F) Read/Write at I/O Address 3B5h/3D5h Index 0Fh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Display Start Address Low (Lower 8 bits) 7-0 Text Cursor Address (Lower 8 bits) 7-0 Display Start Address Low This register contains the lower 8 bits of the memory address where the text cursor is active. In CGA / MDA / Hercules modes, this register wraps around at 16K, 32K, and 64KByte boundaries respectively. This register contains the lower 8 bits of the display start address. The display start address points to the memory address corresponding to the top left corner of the screen. Revision 1.2 Text Cursor Location Low 74 65540 / 545 (R) CRT Controller Registers VERTICAL SYNC END REGISTER (CR11) Read/Write at I/O Address 3B5h/3D5h Index 11h Group 3 Protection for bits 4 and 5 Group 4 Protection for bits 0-3, 6, and 7 LIGHTPEN HIGH REGISTER (CR10) Read only at I/O Address 3B5h/3D5h Index 10h Read-only Register loaded at line compare (the light pen flip-flop is not implemented). Effective only in MDA and Hercules modes or when CR03 bit-7 = 0. D7 D6 D5 D4 D3 D2 D1 D0 V Sync End LIGHTPEN LOW REGISTER (CR11) Read only at I/O Address 3B5h/3D5h Index 11h V Interrupt Clear V Interrupt Enable Select Refresh Type Protect CRTC (Group 0) Read-only Register loaded at line compare (the light pen flip-flop is not implemented). Effective only in MDA and Hercules modes or when CR03 bit-7 = 0. This register is used in all modes. This register is not readable in MDA/Hercules emulation or when CR03 bit-7=1. 3-0 Vertical Sync End The lower 4 bits of the scan line count that defines the end of vertical sync. If the vertical sync width desired is N lines, then bits 3-0 of this register = (CR10 + N) AND 0Fh. VERTICAL SYNC START REGISTER (CR10) Read/Write at I/O Address 3B5h/3D5h Index 10h Group 4 Protection 4 Vertical Interrupt Clear 0=Clear vertical interrupt generated on the IRQ output; 1=Normal operation. This bit is cleared by RESET. D7 D6 D5 D4 D3 D2 D1 D0 5 Vertical Interrupt Enable 0 Enable vertical interrupt (default) 1 Disable vertical interrupt V Sync Start (Lower 8 bits) This bit is cleared by RESET. 7 Group Protect 0 0 Enable writes to CR00-CR07 1 Disable writes to CR00-CR07 Vertical Sync Start The eight low order bits of a 10-bit register. The 9th and 10th bits are located in the CRTC Overflow Register. They define the scan line position at which Vertical Sync becomes active. Revision 1.2 Select Refresh Type ( Ignored ) This bit is logically ORed with XR15 bit-6 to determine the protection for group 0 registers. This bit is cleared by RESET. This register is used in all modes. This register is not readable in (Line Compare bit-9) MDA/Hercules emulation or when CR03 bit-7=1. 7-0 6 CR07 bit-4 (Line Compare bit-9) is not affected by this bit. 75 65540 / 545 (R) CRT Controller Registers VERTICAL DISPLAY ENABLE END REGISTER (CR12) Read/Write at I/O Address 3B5h/3D5h Index 12h Group 4 Protection UNDERLINE LOCATION REGISTER (CR14) Read/Write at I/O Address 3B5h/3D5h Index 14h Group 3 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Underline Position V Display Enable End (Lower 8 bits) 7-0 Count by 4 DoublewordMode Reserved(0) 4-0 Vertical Display Enable End Underline Position These bits specify the underline's scan line position within a character row. These are the eight low order bits of a 10-bit register. The 9th and 10th bits are located in the CRT Controller Overflow register. The actual count = Contents of this register + 1. Programmed Value = Actual scan line number - 1 5 OFFSET REGISTER (CR13) Read/Write at I/O Address 3B5h/3D5h Index 13h Group 3 Protection Count by 4 for Doubleword Mode 0 Frame Buffer Address is incremented by 1 or 2 1 Frame Buffer Address is incremented by 4 or 2 D7 D6 D5 D4 D3 D2 D1 D0 See CR17 bit-3 for further details. 6 Doubleword Mode 0 Frame Buffer Address is byte or word address 1 Frame Buffer Address is doubleword address Display Buffer Width This bit is used in conjunction with CR17 bit-6 to select the display memory addressing mode. 7-0 7 Display Buffer Width. The byte starting address of the next display row = Byte Start Address for current row + K* (CR13 + Z/2), where Z = bit defined in XR0D, K = 2 in byte mode, and K = 4 in word mode. Byte, word and double word mode is selected by bit-6 of CR17 and bit-6 of CR14. A less significant bit than bit-0 of this register is defined in the Auxiliary Offset register (XR0D). This allows finer resolution of the bit map width. Byte, word and doubleword mode affects the translation of the 'logical' display memory address to the 'physical' display memory address. Revision 1.2 76 Reserved (0) 65540 / 545 (R) CRT Controller Registers VERTICAL BLANK START REGISTER (CR15) Read/Write at I/O Address 3B5h/3D5h Index 15h Group 4 Protection VERTICAL BLANK END REGISTER (CR16) Read/Write at I/O Address 3B5h/3D5h Index 16h Group 4 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 V Blank Start (Lower 8 bits) V Blank End (Lower 8 bits) This register is used in all modes. 7-0 This register is used in all modes. Vertical Blank Start 7-0 These are the 8 low order bits of a 10-bit register. The 9th and 10th bits are located in the CRT Controller Overflow and Maximum Scan Line Registers respectively. Together these 10 bits define the scan line position where vertical blank begins. The interval between the end of the vertical display and the beginning of vertical blank is the bottom border on the screen. Revision 1.2 Vertical Blank End These are the 8 low order bits of the scan line count which specifies the end of Vertical Blank. If the vertical blank width desired is Z lines these bits = (Vertical Blank Start + Z) and 0FFh. 77 65540 / 545 (R) CRT Controller Registers CRT MODE CONTROL REGISTER (CR17) Read/Write at I/O Address 3B5h/3D5h Index 17h Group 3 Protection for bits 0, 1, and 3-7 Group 4 Protection for bit 2 3 D7 D6 D5 D4 D3 D2 D1 D0 Compatibility Mode Select Row Scan Counter VSync Select Count by 2 Reserved(0) AddressWrap Word/ByteMode CRTC Reset 0 Compatibility Mode Support This bit allows compatibility with the IBM CGA two-bank graphics mode. 1 4 0 Character row scan line counter bit 0 is substituted for memory address bit 13 during active display time 1 Normal operation, no substitution takes place Select Row Scan Counter Note: In Hercules graphics and Hi-res CGA modes, address increments every two clocks. Reserved (0) 5 AddressWrap (effective only in word mode) 0 Wrap display memory address at 16 KBytes. Used in IBM CGA mode. 1 Normal operation (extended mode). 6 Word Mode or Byte Mode 0 Select Word Mode. In this mode the display memory address counter bits are shifted down by one, causing the most-significant bit of the counter to appear on the least-significant bit of the display memory address output 1 Select byte mode This bit allows compatibility with Hercules graphics and with any other 4-bank graphics system. 2 Count By Two 0 Memory address counter is incremented every character clock 1 Memory address counter is incremented every two character clocks, used in conjunction with bit 5 of 0Fh. Note: This bit is used in conjunction with CR14 bit-5. The net effect is as follows: Increment CR14 CR17 Addressing Bit-5 Bit-3 Every 0 0 1 CCLK 0 1 2 CCLK 1 0 4 CCLK 1 1 2 CCLK 0 Character row scan line counter bit 1 is substituted for memory address bit 14 during active display time 1 Normal operation, no substitution takes place Vertical Sync Select Note: This bit is used in conjunction with CR14 bit-6 to select byte, word, or double word memory addressing as follows: CR14 Bit-6 0 0 1 1 This bit controls the vertical resolution of the CRT Controller by permitting selection of the clock rate input to the vertical counters. When set to 1, the vertical counters are clocked by the horizontal retrace clock divided by 2. CR17 Bit-6 0 1 0 1 Addressing Mode Word Mode Byte Mode Double Word Mode Double Word Mode Display memory addresses are affected as shown in the table on the following page. 7 CRTC Reset 0 Force HSYNC and VSYNC inactive. No other registers or outputs affected. 1 Normal Operation This bit is cleared by RESET. Revision 1.2 78 65540 / 545 (R) CRT Controller Registers Display memory addresses are affected by CR17 bit 6 as shown in the table below: Logical Memory Address MA00 MA01 MA02 MA03 MA04 MA05 MA06 MA07 MA08 MA09 MA10 MA11 MA12 MA13 MA14 MA15 LINE COMPARE REGISTER (CR18) Read/Write at I/O Address 3B5h/3D5h Index 18h Group 3 Protection Physical Memory Address Byte Word DoubleWord Mode Mode Mode A00 Note 1 Note 2 A01 A00 Note 3 A02 A01 A00 A03 A02 A01 A04 A03 A02 A05 A04 A03 A06 A05 A04 A07 A06 A05 A08 A07 A06 A09 A08 A07 A10 A09 A08 A11 A10 A09 A12 A11 A10 A13 A12 A11 A14 A13 A12 A15 A14 A13 D7 D6 D5 D4 D3 D2 D1 D0 Line Compare Target (Lower 8 bits) 7-0 These are the low order 8 bits of a 10-bit register. The 9th and 10th bits are located in the CRT Controller Overflow and Maximum Scan Line Registers, respectively. This register is used to implement a split screen function. When the scan line counter value is equal to the contents of this register, the memory address counter is cleared to 0. The display memory address counter then sequentially addresses the display memory starting at address 0. Each subsequent row address is generated by the addition of the Offset Register contents. This register is not affected by the double scanning bit (CR09 bit 7). Note 1 = A13 * NOT CR17 bit 5 + A15 * CR17 bit 5 Note 2 = A12 xor (A14 * XR04 bit 2) Note 3 = A13 xor (A15 * XR04 bit 2) Revision 1.2 Line Compare Target 79 65540 / 545 (R) CRT Controller Registers MEMORY DATA LATCH REGISTER (CR22) Read only at I/O Address 3B5h/3D5h Index 22h ATTRIBUTE CONTROLLER TOGGLE REGISTER (CR24) Read only at I/O Address 3B5h/3D5h Index 24h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Data Latch n Bit 7 Data Latch n Bit 6 Data Latch n Bit 5 Data Latch n Bit 4 Data Latch n Bit 3 Data Latch n Bit 2 Data Latch n Bit 1 Data Latch n Bit 0 Reserved(0) Index (0) / Data (1) This register may be used to read the state of Graphics Controller Memory Data Latch 'n', where 'n' is controlled by the Graphics Controller Read Map Select Register (GR04 bits 0-1) and is in the range 0-3. Writes to this register are not decoded and will be ignored. This is a standard VGA register which was not documented by IBM. 6-0 7 Reserved (0) Index/Data This bit may be used to read back the state of the attribute controller index/data latch. This latch indicates whether the next write to the attribute controller at 3C0h will be to the register index pointer or to an indexed register. 0 Next write is to the index 1 Next write is to an indexed register Writes to this register are not decoded and will be ignored. This is a standard VGA register which was not documented by IBM. Revision 1.2 80 65540 / 545 (R) Graphics Controller Registers Graphics Controller Registers Register Mnemonic Register Name GRX GR00 GR01 GR02 GR03 GR04 GR05 GR06 GR07 GR08 Graphics Index Set/Reset EnableSet/Reset Color Compare DataRotate Read Map Select Graphics mode Miscellaneous Color Don't Care Bit Mask Index Access I/O Address Protect Group Page - 00h 01h 02h 03h 04h 05h 06h 07h 08h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 3CEh 3CFh 3CFh 3CFh 3CFh 3CFh 3CFh 3CFh 3CFh 3CFh 1 1 1 1 1 1 1 1 1 1 81 81 82 82 83 83 84 86 86 87 GRAPHICSCONTROLLER INDEX REGISTER (GRX) Write only at I/O Address 3CEh Group 1 Protection SET/RESET REGISTER (GR00) Read/Write at I/O Address 3CFh Index 00h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Index to Graphics Controller Data Registers Set/Reset Bit 0 Set/Reset Bit 1 Set/Reset Bit 2 Set/Reset Bit 3 Reserved(0) Reserved(0) 3-0 4-bitIndextoGraphicsControllerRegisters 7-4 Reserved (0) The SET/RESET and ENABLE SET/RESET registers are used to 'expand' 8 bits of CPU data to 32 bits of display memory. 3-0 Set / Reset Planes 3-0 When the Graphics Mode register selects Write Mode 0, all 8 bits of each display memory plane are set as specified in the corresponding bit in this register. The Enable Set/Reset register (GR01) allows selection of some of the source of data to be written to individual planes. In Write Mode 3 (see GR05), these bits determine the color value. 7-4 Revision 1.2 81 Reserved (0) 65540 / 545 (R) Graphics Controller Registers ENABLE SET/RESET REGISTER (GR01) Read/Write at I/O Address 3CFh Index 01h Group 1 Protection COLOR COMPARE REGISTER (GR02) Read/Write at I/O Address 3CFh Index 02h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 3-0 Enable Set/Reset Bit 0 Enable Set/Reset Bit 1 Enable Set/Reset Bit 2 Enable Set/Reset Bit 3 Color Compare (Plane 0) Color Compare (Plane 1) Color Compare (Plane 2) Color Compare (Plane 3) Reserved(0) Reserved(0) Enable Set / Reset Planes 3-0 3-0 This register works in conjunction with the Set/Reset register (GR00). The Graphics Mode register must be programmed to Write Mode 0 in order for this register to have any effect. This register is used to 'reduce' 32 bits of memory data to 8 bits for the CPU in 4plane graphics mode. These bits provide a reference color value to compare to data read from display memory planes 0-3. The Color Don't Care register (GR07) is used to affect the result. This register is active only if the Graphics Mode register (GR05) is set to Read Mode 1. A match between the memory data and the Color Compare register (GR02) (for the bits specified in the Color Don't Care register) causes a logical 1 to be placed on the CPU data bus for the corresponding data bit; a mis-match returns a logical 0. 0 The corresponding plane is written with the data from the CPU data bus 1 The corresponding plane is set to 0 or 1 as specified in the Set/Reset Register 7-4 Reserved (0) 7-4 Revision 1.2 Color Compare Planes 3-0 82 Reserved (0) 65540 / 545 (R) Graphics Controller Registers DATA ROTATE REGISTER (GR03) Read/Write at I/O Address 3CFh Index 03h Group 1 Protection READ MAP SELECT REGISTER (GR04) Read/Write at I/O Address 3CFh Index 04h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Rotate Count 0 Rotate Count 1 Rotate Count 2 Read Map Select 0 Read Map Select 1 Function Select Reserved(0) Reserved(0) 2-0 Data Rotate Count 1-0 These bits specify the number of bits to rotate to the right the data being written by the CPU. The CPU data bits are first rotated, then subjected to the logical operation as specified in the Function Select bit field. The rotate function is active only if the Graphics Mode register is programmed for Write Mode 0. 4-3 This register is also used to 'reduce' 32 bits of memory data to 8 bits for the CPU in the 4-plane graphics mode. These bits select the memory plane from which the CPU reads data in Read Mode 0. In Odd/Even mode, bit-0 is ignored. In Quad mode, bits 0 and 1 are both ignored. The four memory maps are selected as follows: Function Select These Function Select bits specify the logical function performed on the contents of the processor latches (loaded on a previous CPU read cycle) before the data is written to display memory. These bits operate as follows: Bit 4 Bit 3 0 0 0 1 7-5 1 0 1 1 Read Map Select Bit 1 Bit 0 0 0 0 1 1 0 1 1 7-2 MapSelected Plane 0 Plane 1 Plane 2 Plane 3 Reserved (0) Result No change to the Data Logical 'AND' between Data and latched data Logical 'OR' between Data and latched data Logical 'XOR' between Data and latched data Reserved (0) Revision 1.2 83 65540 / 545 (R) Graphics Controller Registers corresponding pixel in the processor latches. The Set/Reset and Enable Set/Reset registers are ignored. The Function Select bits in the Data Rotate register are used. GRAPHICS MODE REGISTER (GR05) Read/Write at I/O Address 3CFh Index 05h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 1 Write Mode Reserved(0) ReadMode Odd/EvenMode Shift Register Mode Reserved(0) 1-0 For 16-bit writes, the operation is repeated on the lower and upper bytes of CPU data. 0 1 Revision 1.2 0 0 1 0 Write mode 3. The CPU data is rotated then logically ANDed with the contents of the Bit Mask register (GR08) and then treated as the addressed data's bit mask, while the contents of the Set/Reset register is treated as the color value. A '0' on the data bus (mask) causes the corresponding pixel in the addressed byte to be set to the corresponding pixel in the processor latches. Write Mode 1 0 1 A '1' on the data bus (mask) causes the corresponding pixel in the addressed byte to be set to the color value specified in the Set/Reset register. Write Mode Write mode 0. Each of the four display memory planes is written with the CPU data rotated by the number of counts in the Rotate Register, except when the Set/Reset Register is enabled for any of the four planes. When the Set/Reset Register is enabled, the corresponding plane is written with the data stored in the Set/Reset Register. The Enable Set/Reset register is ignored. The Data Rotate is used. This write mode can be used to fill an area with a single color and pattern. Write mode 1. Each of the four display memory planes is written with the data previously loaded in the processor latches. These latches are loaded during all read operations. Write mode 2. The CPU data bus data is treated as the color value for the addressed byte in planes 0-3. All eight pixels in the addressed byte are modified unless protected by the Bit Mask register setting. A logical 1 in the Bit Mask register sets the corresponding pixel in the addressed byte to the color specified on the data bus. A 0 in the Bit Mask register sets the corresponding pixel in the addressed byte to the 2 Reserved (0) 3 Read Mode 0 The CPU reads data from one of the planes as selected in the Read Map Select register. 1 The CPU reads the 8-bit result of the logical comparison between all eight pixels in the four display planes and the contents of the Color Compare and Color Don't Care registers. The CPU reads a logical 1 if a match occurs for each pixel and logical 0 if a mis-match occurs. In 16-bit read cycles, this operation is repeated on the lower and upper bytes. (Continued on following page) 84 65540 / 545 (R) Graphics Controller Registers 4 Odd/Even Mode 0 All CPU addresses sequentially access all planes 1 Even CPU addresses access planes 0 and 2, while odd CPU addresses access planes 1 and 3. This option is useful for compatibility with the IBM CGA memory organization. 6-5 Shift Register Mode These two bits select the data shift pattern used when passing data from the four memory planes through the four video shift registers. If data bits 0-7 in memory planes 0-3 are represented as M0D0-M0D7, M1D0-M1D7, M2D0-M2D7, and M3D0-M3D7 respectively, then the data in the serial shift registers is shifted out as follows: 65 Last Bit Shifted Out Shift Direction Output to: 00: M0D0 M1D0 M2D0 M3D0 M0D1 M1D1 M2D1 M3D1 M0D2 M1D2 M2D2 M3D2 M0D3 M1D3 M2D3 M3D3 M0D4 M1D4 M2D4 M3D4 M0D5 M1D5 M2D5 M3D5 M0D6 M1D6 M2D6 M3D6 M0D7 M1D7 M2D7 M3D7 Bit 0 Bit 1 Bit 2 Bit 3 01: M1D0 M1D1 M3D0 M3D1 M1D2 M1D3 M3D2 M3D3 M1D4 M1D5 M3D4 M3D5 M1D6 M1D7 M3D6 M3D7 M0D0 M0D1 M2D0 M2D1 M0D2 M0D3 M2D2 M2D3 M0D4 M0D5 M2D4 M2D5 M0D6 M0D7 M2D6 M2D7 Bit 0 Bit 1 Bit 2 Bit 3 1x: M3D0 M3D1 M3D2 M3D3 M3D4 M3D5 M3D6 M3D7 M2D0 M2D1 M2D2 M2D3 M2D4 M2D5 M2D6 M2D7 M1D0 M1D1 M1D2 M1D3 M1D4 M1D5 M1D6 M1D7 M0D0 M0D1 M0D2 M0D3 M0D4 M0D5 M0D6 M0D7 Bit 0 Bit 1 Bit 2 Bit 3 Note: If the Shift Register is not loaded every character clock (see SR01 bits 2&4) then the four 8-bit shift registers are effectively 'chained' with the output of shift register 1 becoming the input to shift register 0 and so on. This allows one to have a large monochrome (or 4 color) bit map and display one portion thereof. Note: If XR28 bit-4 is set (8-bit video path), GR05 bit-6 must be set to 0: 0x and XR28 bit-4=1: 7 1st Bit Shifted Out M3D0 M3D1 M3D2 M3D3 M3D4 M3D5 M3D6 M3D7 M2D0 M2D1 M2D2 M2D3 M2D4 M2D5 M2D6 M2D7 M1D0 M1D1 M1D2 M1D3 M1D4 M1D5 M1D6 M1D7 M0D0 M0D1 M0D2 M0D3 M0D4 M0D5 M0D6 M0D7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Reserved (0) Revision 1.2 85 65540 / 545 (R) Graphics Controller Registers MISCELLANEOUS REGISTER (GR06) Read/Write at I/O Address 3CFh Index 06h Group 1 Protection COLOR DON'T CARE REGISTER (GR07) Read/Write at I/O Address 3CFh Index 07h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Graphics/Text Mode Chain Odd/Even Planes 0 Memory Map Mode Ignore Color Plane 0 Ignore Color Plane 1 Ignore Color Plane 2 Ignore Color Plane 3 Reserved(0) Reserved(0) Graphics/Text Mode 3-0 0 Text Mode 1 Graphics mode 1 Ignore Color Plane (3-0) 0 This causes the corresponding bit of the Color Compare register to be a don't care during a comparison. 1 The corresponding bit of the Color Compare register is enabled for color comparison. This register is active in Read Mode 1 only. Chain Odd/Even Planes This mode can be used to double the address space into display memory. 1 CPU address bit A0 is replaced by a higher order address bit. The state of A0 determines which memory plane is to be selected: 7-4 Reserved (0) A0 = 0: select planes 0 and 2 A0 = 1: select planes 1 and 3 0 A0 not replaced 3-2 Memory Map Mode These bits control the mapping of the display memory into the CPU address space as follows (also used in extended modes): Bit 3 0 0 1 1 7-4 Bit 2 0 1 0 1 CPU Address A0000h-BFFFFh A0000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh Reserved (0) Revision 1.2 86 65540 / 545 (R) Graphics Controller Registers BIT MASK REGISTER (GR08) Read/Write at I/O Address 3CFh Index 08h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 Bit Mask 0=Immune to change 1=Change permitted 7-0 Bit Mask This bit mask is applicable to any data written by the CPU, including that subject to a rotate, logical function (AND, OR, XOR), Set/Reset, and No Change. In order to execute a proper read-modify-write cycle into displayed memory, each byte must first be read (and latched by the VGA), the Bit Mask register set, and the new data then written. The bit mask applies to all four planes simultaneously. 0 The corresponding bit in each of the four memory planes is written from the corresponding bit in the latches 1 Unrestricted manipulation of the corresponding data bit in each of the four memory planes is permitted Revision 1.2 87 65540 / 545 (R) Revision 1.2 88 65540 / 545 (R) Attribute Controller and Color Palette Registers Attribute Controller and VGA Color Palette Registers Register Mnemonic Register Name ARX AR00-AR0F AR10 AR11 AR12 AR13 AR14 DACMASK DACSTATE DACRX DACX DACDATA Attribute Index (for 3C0/3C1h) Attribute Controller Color Data Mode Control Overscan Color Color Plane Enable Horizontal Pixel Panning Pixel Pad Color Palette Pixel Mask Color Palette State Color Palette Read-Mode Index Color Palette Index (for 3C9h) Color Palette Data In regular VGA mode, all Attribute Controller registers are located at the same byte address (3C0h) in the CPU I/O space. An internal flip-flop controls the selection of either the Attribute Index or Data Registers. To select the Index Register, an I/O Read is executed to address 3BAh/3DAh (Input Status Register 1) to clear this flip-flop. After the Index Register has been loaded by an I/O Write to address 3C0h, this flip-flop toggles, and the Data Register is ready to be accessed. Every I/O Write to address 3C0h toggles this flip-flop. The flip-flop does not have any effect on the reading of the Attribute Controller registers. The Attribute Controller index register is always read back at address 3C0h, the data register is always read back at address 3C1h. Access - 00-0Fh 10h 11h 12h 13h 14h - - - - 00-FFh R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W I/O Protect Address Group Page 3C0h 3C0h/3C1h 3C0h/3C1h 3C0h/3C1h 3C0h/3C1h 3C0h/3C1h 3C0h/3C1h 3C6h 3C7h 3C7h 3C8h 3C9h 1 1 1 1 1 1 1 6 - 6 6 6 89 90 90 91 91 92 92 93 93 94 94 94 ATTRIBUTE INDEX REGISTER (ARX) Read/Write at I/O Address 3C0h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 Index to Attribute Controller Data Registers Enable Video Reserved(0) An option is provided to allow the Attribute Controller Index register to be mapped to 3C0h and the Data register to 3C1h to allow word I/O accesses. Another option allows the Attribute Controller to be both read and written at either 3C0h or 3C1h (EGA compatible mode). These optional mappings are selected by 'CPU Interface Register 1' (XR02[4-3]) and are not standard VGA capabilities. 4-0 Attribute Controller Index These bits point to one of the internal registers of the Attribute Controller. 5 The VGA color palette is used to further modify the video color output following the attribute controller color registers. The color palette logic is contained on-chip; extension register XR06 is provided to control various optional capabilities. DAC logic is provided on-chip to convert the final video output of the color palette to analog RGB outputs for use in driving a CRT display. Output comparator logic is also provided on-chip to duplicate the SENSE function (see Status Register 0 readable at 3C2h). Revision 1.2 Index 7-6 89 Enable Video 0 Disable video, allowing the Attribute Controller Color registers to be accessed by the CPU 1 Enable video, causing the Attribute Controller Color registers (AR00AR0F) to be inaccessible to the CPU Reserved (0) 65540 / 545 (R) Attribute Controller and Color Palette Registers ATTRIBUTE CONTROLLER COLOR REGISTERS (AR00-AR0F) Read at I/O Address 3C1h Write at I/O Address 3C0/1h Index 00-0Fh Group 1 Protection or XR63 bit-6 2 This bit is dependent on bit 0 of the Override register. 0 Make the ninth pixel appear the same as the background 1 For special line graphics character codes (0C0h-0DFh), make the ninth pixel identical to the eighth pixel of the character. For other characters, the ninth pixel is the same as the background. D7 D6 D5 D4 D3 D2 D1 D0 Blue Green Red SecondaryBlue SecondaryGreen SecondaryRed 3 Color Value 0 Disable Blinking and enable text mode background intensity These bits are the color value in the respective attribute controller color register as pointed to by the attribute index register. 7-6 1 Enable the blink attribute in text and graphics modes. Reserved (0) 4 Reserved (0) 5 Split Screen Horizontal Panning Mode 0 Scroll both screens horizontally as specified in the Pixel Panning register ATTRIBUTE CONTROLLER MODE CONTROL REGISTER (AR10) Read at I/O Address 3C1h Write at I/O Address 3C0/1h Index 10h Group 1 Protection 6 Text/Graphics Mode Mono/Color Display 1 Two 4-bit sets of video data are assembled to generate 8-bit video data at half the frequency of the internal dot clock (256 color mode). Enable Line Graphics Select Background Reserved(0) Horizontal Split Screen 256 Color Video Output 4-5 Select 1 7 Video Output 5-4 Select 0 Video bits 4 and 5 are generated by the internal Attribute Controller color palette registers Text/Graphics Mode 0 Select text mode 1 Select graphics mode Monochrome/Color Display 0 Select color display attributes 1 Select mono display attributes Revision 1.2 1 Scroll horizontally only the top screen as specified in the Pixel panning register 256 Color Output Assembler 0 6-bits of video (translated from 4-bits by the internal color palette) are output every dot clock D7 D6 D5 D4 D3 D2 D1 D0 0 Enable Blink/Select Background Intensity The blinking counter is clocked by the VSYNC signal. The Blink frequency is defined in the Blink Rate Control Register (XR60). Reserved(0) 5-0 Enable Line Graphics Character Codes 1 Video bits 4 and 5 are the same as bits 0 and 1 in the Pixel Pad register (AR14) 90 65540 / 545 (R) Attribute Controller and Color Palette Registers OVERSCAN COLOR REGISTER (AR11) Read at I/O Address 3C1h Write at I/O Address 3C0/1h Index 11H Group 1 Protection COLOR PLANE ENABLE REGISTER (AR12) Read at I/O Address 3C1h Write at I/O Address 3C0/1h Index 12h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Color Plane 0 Enable Color Plane 1 Enable Color Plane 2 Enable Color Plane 3 Enable Overscan Color Display Status Select Reserved(0) 7-0 Overscan Color 3-0 These 8 bits define the overscan (border) color value. For monochrome displays, these bits should be zero. Color Plane (3-0) Enable 0 Force the corresponding color plane pixel bit to 0 before it addresses the color palette 1 Enable the plane data bit of the corresponding color plane to pass The border color is displayed in the interval after Display Enable End and before Blank Start (end of display area; i.e. right side and bottom of screen) and between Blank End and Display Enable Start (beginning of display area; i.e. left side and top of screen). 5-4 Display Status Select These bits select two of the eight color outputs to be read back in the Input Status Register 1 (port 3BAh or 3DAh). The output color combinations available on the status bits are as follows: Bit 5 Bit 4 0 0 0 1 1 0 1 1 7-6 Revision 1.2 91 Status Register 1 Bit 5 Bit 4 P2 P0 P5 P4 P3 P1 P7 P6 Reserved (0) 65540 / 545 (R) Attribute Controller and Color Palette Registers ATTRIBUTE CONTROLLER HORIZONTAL PIXEL PANNING REGISTER (AR13) Read at I/O Address 3C1h Write At I/O Address 3C0/1h Index 13h Group 1 Protection ATTRIBUTE CONTROLLER PIXEL PAD REGISTER (AR14) Read at I/O Address 3C1h Write At I/O Address 3C0/1h Index 14h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 3-0 Horizontal Pixel Panning Video bit-4 if AR10 bit7=1 Video bit-5 if AR10 bit7=1 Video bit-6 if not 256-color Video bit-7 if not 256-color Reserved(0) Reserved(0) Horizontal Pixel Panning 1-0 These bits select the number of pixels to shift the display horizontally to the left. Pixel panning is available in both text and graphics modes. In 9 pixel/character text mode, the output can be shifted a maximum of 9 pixels. In 8 pixel/character text mode and all graphics modes a maximum shift of 8 pixels is possible. In 256-color mode (output assembler AR10 bit-6 = 1), bit 0 of this register must be 0 which results in only 4 panning positions per display byte. In Shift Load 2 and Shift Load 4 modes, register CR08 provides single pixel resolution for panning. Panning is controlled as follows: AR13 0 1 2 3 4 5 6 7 8 7-4 Video Bits 5-4 These bits are output as video bits 5 and 4 when AR10 bit-7 = 1. They are disabled in the 256 color mode. 3-2 Video Bits 7-6 These bits are output as video bits 7 and 6 in all modes except 256-color mode. 7-4 Reserved (0) Number of Pixels Shifted 9-dot 8-dot 256-color mode mode mode 1 0 0 2 1 -3 2 1 4 3 -5 4 2 6 5 -7 6 3 8 7 -0 --- Reserved (0) Revision 1.2 92 65540 / 545 (R) Attribute Controller and Color Palette Registers COLOR PALETTE PIXEL MASK REGISTER (DACMASK) Read/Write at I/O Address 3C6h Group 6 Protection COLOR PALETTE STATE REGISTER (DACSTATE) Read only at I/O Address 3C7h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Pixel Mask Bit-0 Pixel Mask Bit-1 Pixel Mask Bit-2 Pixel Mask Bit-3 Pixel Mask Bit-4 Pixel Mask Bit-5 Pixel Mask Bit-6 Pixel Mask Bit-7 Palette State 0 Palette State 1 Reserved(0) 1-0 The contents of this register are logically ANDed with the 8 bits of video data coming into the color palette. Zero bits in this register therefore cause the corresponding address input to the color palette to be zero. For example, if this register is programmed with 7, only color palette registers 0-7 would be accessible; video output bits 3-7 would be ignored and all color values would map into the lower 8 locations in the color palette. Palette State 1-0 Status bits indicate the I/O address of the last CPU write to the Color Palette: 00 11 7-2 The last write was to 3C8h (write mode) The last write was to 3C7h (read mode) Reserved (0) To allow saving and restoring the state of the video subsystem, this register is required since the color palette index register is automatically incremented differently depending on whether the index is written at 3C7h or 3C8h. Revision 1.2 93 65540 / 545 (R) Attribute Controller and Color Palette Registers COLOR PALETTE READ-MODE INDEX REGISTER (DACRX) Write only at I/O Address 3C7h Group 6 Protection COLOR PALETTE INDEX REGISTER (DACX) Read/Write at I/O Address 3C8h Group 6 Protection D7 D6 D5 D4 D3 D2 D1 D0 Color Palette Index 0 Color Palette Index 1 Color Palette Index 2 Color Palette Index 3 Color Palette Index 4 Color Palette Index 5 Color Palette Index 6 Color Palette Index 7 COLOR PALETTE DATA REGISTERS (DACDATA 00-FF) Read/Write at I/O Address 3C9h Index 00h-FFh Group 6 Protection D7 D6 D5 D4 D3 D2 D1 D0 register) is used by the palette logic to point at the current data register. When the index value is written to 3C7h (readmode), it is written to both the index register and the save register, then the index register is automatically incremented. When the index value is written to 3C8h (write mode), the automatic incrementing of the index register does not occur. After the third of the three sequential data reads from (or writes to) 3C9h is completed, the save and index registers are both automatically incremented by the palette logic. This allows the entire palette (or any subset) to be read (written) by writing the index of the first color in the set, then sequentially reading (writing) the values for each color, without having to reload the index every three bytes. The state of the RGB sequence is not saved; the user must access each three bytes in an uninterruptible sequence (or be assured that interrupt service routines will not access the palette index or data registers). When the index register is written (at either port), the RGB sequence is restarted. Data reads and writes may be intermixed; either reads or writes increment the palette logic's RGB sequence counter. The palette's save register always contains a value one less than the readable index value if the last index write was to the 'read mode' port. The state is saved of which port (3C7h or 3C8h) was last written; that information is returned on reads from 3C7h. Access 1st 2nd 3rd Red 0 Green 0 Blue 0 Red 1 Green 1 Blue 1 Red 2 Green 2 Blue 2 Red 3 Green 3 Blue 3 Red 4 Green 4 Blue 4 Red 5 Green 5 Blue 5 Reserved (0) The palette index register is used to point to one of 256 palette data registers. Each data register is 18 bits in length (6 bits each for red, green, and blue), so the data values must be read as a sequence of 3 bytes. After writing the index register (3C7h or 3C8h), data values may be read from or written to the color palette data register port (3C9h) in sequence: first red, then green, then blue, then repeat for the next location if desired (the index is incremented automatically by the palette logic). The index may be written at 3C7h and may be read or written at 3C8h. When the index value is written to either port, it is written to both the index register and a 'save' register. The save register (not the index Revision 1.2 94 65540 / 545 (R) Extension Registers Extension Registers Register Mnemonic XRX Register Group -- Extension Register Name Extension Index Index -- I/O Access R/W XR00 XR01 XR02 XR03 XR04 XR05 XR06 XR0E XR28 XR29 XR70 XR72 XR73 XR7D XR7F Misc Misc Misc Misc Misc Misc Misc Misc Misc Misc Misc Misc Misc Misc Misc Chip Version (65540: v=0; 65545: v=1) Configuration CPU Interface Control 1 CPU Interface Control 2 Memory Control 1 Memory Control 2 Palette Control Text Mode Control VideoInterface Half Line Compare Setup / Disable Control External Device I/O DPMS Control Diagnostic (65545 Only) Diagnostic 00h 01h 02h 03h 04h 05h 06h 0Eh 28h 29h 70h 72h 73h 7Dh 7Fh RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 1101v r r r dddddddd 00000000 - - - - - - 0x - - 0 - - 000 00000000 00000000 000000 - 0000 - - 0 xxxxxxxx 0------0000000 * 00 - - 0000 0------00xxxx00 97 98 99 100 101 102 103 106 117 117 150 151 152 152 153 XR07 XR08 XR0B XR0C XR10 XR11 Mapping Mapping Mapping Mapping Mapping Mapping I/O Base (65545 Only) Linear Addressing Base CPU Paging Start Address Top Single/Low Map High Map 07h 08h 0Bh 0Ch 10h 11h R/W R/W R/W R/W R/W R/W 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 11110100 xxxxxxxx - - 00 *000 - - - - - - xx xxxxxxxx xxxxxxxx 104 104 105 105 108 108 XR0F XR2B XR44 XR45 Software Flags Software Flags Software Flags Software Flags Software Flags 0 Software Flags 1 Software Flags 2 Software Flags 3 0Fh 2Bh 44h 45h R/W R/W R/W R/W 3D7h 3D7h 3D7h 3D7h xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 107 118 127 127 XR14 XR15 XR1F XR7E Compatibility Compatibility Compatibility Compatibility Emulation Mode Write Protect Virtual EGA Switch CGA/Hercules Color Select 14h 15h 1Fh 7Eh R/W R/W R/W R/W 3D7h 3D7h 3D7h 3D7h 0000hh00 00000000 0 - - - xxxx - - xxxxxx 109 110 115 153 XR30 XR31 XR32 XR33 Clock Clock Clock Clock Clock Divide Control Clock M-Divisor Clock N-Divisor Clock Control 30h 31h 32h 33h R/W R/W R/W R/W 3D7h 3D7h 3D7h 3D7h * * *x *x 00 xx xx xx 00 121 122 122 123 XR3A XR3B XR3C XR3D XR3E XR3F MultiMedia MultiMedia MultiMedia MultiMedia MultiMedia MultiMedia Color Key 0 Color Key 1 Color Key 2 Color Key Mask 0 Color Key Mask 1 Color Key Mask 2 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh R/W R/W R/W R/W R/W R/W 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 124 124 125 125 126 126 XR40 BitBLT BitBLT Configuration (65545 Only) 40h R/W 3D7h - - - - - - xx 127 Reset Codes: x d h r Revision 1.2 = = = = Not changed by reset (indeterminate on power-up) Set from the corresponding data bus pin on trailing edge of reset Read-only Hercules Configuration Register Readback bits Chip revision # (starting from 0000) 95 State After Address Reset 3D6h - x x x x x x x * *xx xxxx xxxx 00 *0 Page 97 - = Not implemented (always reads 0) * = Reserved (read/write, reset to 0) 0/1 = Reset to 0 or 1 by trailing edge of reset 65540 / 545 (R) Extension Registers Extension Registers (Continued) Register Mnemonic XR0D XR16 XR17 XR18 XR19 XR1A XR1B XR1C XR1D XR1E XR24 XR25 XR26 XR64 XR65 XR66 XR67 Register Group Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate Extension Register Name Auxiliary Offset Vertical Overflow Horizontal Overflow Alternate Horizontal Display End Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Alternate H Blank Start / H Panel Size Alternate Horizontal Blank End Alternate Offset Alternate Maximum Scan Line Alternate Text Mode / H Virtual Panel Size Alternate Horizontal Sync Start Register Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Index 0Dh 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 24h 25h 26h 64h 65h 66h 67h I/O Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5C XR5D XR5E XR5F XR60 XR61 XR62 XR63 XR68 XR6C XR6E XR6F Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel Flat Panel FLM Delay LP Delay (Comp Enabled) LP Delay (Comp Disabled) LP Width Panel Format 2 Panel Format 1 Display Type Power Down Control Panel Format 3 PanelInterface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Panel Power Sequencing Delay Activity Indicator Control FP Diagnostic M (ACDCLK) Control Power Down Mode Refresh Blink Rate Control SmartMapTM Control SmartMapTM Shift Parameter SmartMapTM Color Mapping Control Vertical Panel Size Programmable Output Drive Polynomial FRC Control Frame Buffer Control 2Ch 2Dh 2Eh 2Fh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 68h 6Ch 6Eh 6Fh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Codes: x d h r Revision 1.2 = = = = Not changed by reset (indeterminate on power-up) Set from the corresponding data bus pin on trailing edge of reset Read-only Hercules Configuration Register Readback bits Chip revision # (starting from 0000) 96 State After Address Reset 3D7h - - - - - - x x 3D7h * 0 * 0 * 0 0 0 3D7h * 0 0 0 0 0 0 0 3D7h x x x x x x x x 3D7h x x x x x x x x 3D7h x x x x x x x x 3D7h x x x x x x x x 3D7h x x x x x x x x 3D7h 0 x x x x x x x 3D7h x x x x x x x x 3D7h * * * x x x x x 3D7h x x x x x x x x 3D7h x x x x x x x x 3D7h x x x x x x x x 3D7h x x x * * x x x 3D7h x x x x x x x x 3D7h * * * * x x x x 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h 3D7h xx xx xx xx xx xx 00 00 *0 xx xx xx xx xx xx * * 10 0x 00 xx xx 10 xx xx x1 xx * * 10 00 xxxx xxxx xxxx xxxx * * *x xxxx 0 *00 0000 0000 xxxx x * *x xxxx xxxx xxxx x *xx * *xx 0000 *xxx 0000 xxxx xxxx 0000 xxxx xxxx xxxx xxxx 0000 1111 0000 xx xx xx xx xx xx 00 01 x0 xx xx xx xx xx xx xx 01 xx 00 xx xx 11 xx xx xx xx d* 01 00 Page 106 111 111 112 112 113 113 114 114 115 116 116 116 145 145 146 146 118 119 119 120 128 129 130 131 132 133 134 135 136 137 137 138 138 139 140 141 141 142 143 144 144 147 147 148 149 - = Not implemented (always reads 0) * = Reserved (read/write, reset to 0) 0/1 = Reset to 0 or 1 by trailing edge of reset 65540 / 545 (R) Extension Registers EXTENSION INDEX REGISTER (XRX) Read/Write at I/O Address 3D6h CHIPS VERSION REGISTER (XR00) Read only at I/O Address 3D7h Index 00h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Chip Revision Index to Extension Registers - 0=65540, 1=65545 Chip Type (1101) Reserved(0) 6-0 7 Index value used to access the extension registers 7-0 Reserved (0) Revision 1.2 97 Chip Version - 65540 Chip Versions start at D0h and are incremented for every silicon step. 65545 Chip Versions start at D8h and are incremented for every silicon step. 65540 / 545 (R) Extension Registers CONFIGURATION REGISTER (XR01) Read only at I/O Address 3D7h Index 01h 5 CFG5 - Oscillator Source Select 0 External Oscillator drives XTALI (pin 203) 1 Internal Oscillator (series resonant crystal connected to XTALI and XTALO) 6 CFG 6 - A26-A27 Enable D7 D6 D5 D4 D3 D2 D1 D0 CFG0 / LB#: Bus Type CFG1 / ISA#: Bus Type CFG2 / 2X#: Bus Type CFG3: Reserved CFG4: Reserved (do not use) CFG5 / OS#: Osc Src Select CFG6 / AD#: A26-27 Ena CFG7 / TS#: Clk Test Ena 0 Pin 53 is A26 (ignore for ISA & PCI) Pin 54 is A27 (ignore for ISA & PCI) 1 Pin 53 is ACTI Pin 54 is ENABKL 7 CFG7 - Internal Clock Test Mode 0 Enable internal clock test mode. Output MCLK on pin-30 (A25) and VCLK on pin 29 (A24) 1 Normal operation: ROMCS# generated in ISA bus mode These bits latch the state of memory address bus A (AA bus) bits 0-7 on the rising edge of RESET#. The state of bits 0-7 after RESET# effect chip internal logic as indicated below. During RESET#, internal pullups are enabled for AA[7:0] and hence the status of these bits will be high if no external pull-down resistors are present on these pins. This register is not related to the Virtual EGA Switch register (XR1F). 2-0 CFG2:0 - CPU Bus Type 2 1 0 2X# ISA# LB# L L L L L H L H L L H H H H H H L L H H L H L H Bus Type Reserved Reserved Reserved CPU Direct (2x LCLK) (pin-23=CRESET) Reserved ISA Bus PCI Bus (65545 only) VL-Bus (1x clk) (pin-23=RDYRTN#) 3 CFG3 - Reserved The pin corresponding to this bit has no internal hardware function so may be used for sampling external conditions at reset. 4 CFG4 - Reserved The pin corresponding to this bit must be sampled high on reset so this bit will always read back 1. Revision 1.2 98 65540 / 545 (R) Extension Registers CPU INTERFACE CTRL REGISTER 1 (XR02) Read/Write at I/O Address 3D7h Index 02h D7 D6 D5 D4 D3 D2 D1 D0 Enable 16-bit Mem Access Digital Monitor Mode Sim Disp CRT H Timing Attribute Controller Mapping 10-bit I/O Address Decode 83C6-83C9 Palette Decode Attribute FF Status (R/O) 0 1 2 4-3 5 6 7 8/16-bit CPU Memory Access 0 8-bit CPU memory access (default) 1 16-bit CPU memory access Digital Monitor Clock Mode 0 Normal (clk 0-1=25,28 MHz) (default) 1 Digital Monitor (clk 0-1=14,16MHz) 14MHz = 56MHz / 4 or 28MHz / 2 16MHz = 50MHz / 3 SimultaneousDisplayCRTHTimingSelect 0 Use XR19,1A,1B for H parameters 1 Use CR04,05,00 for H parameters AttributeControllerMapping 00 Write Index and Data at 3C0h. (8-bit access only) (default - VGA mapping) 01 Write Index at 3C0h and Data at 3C1h (8-bit or 16-bit access). Attribute flipflop (bit-7) is always reset in this mode (16-bit mapping) 10 Write Index and Data at 3C0h/3C1h (8-bit access only) (EGA mapping) 11 Reserved I/O Address Decoding 0 Decode all 16 bits of I/O address (default) 1 Decode only lower 10 bits of I/O address. This affects addresses 3B43B5h, 3B8h, 3BAh, 3BFh, 3C03C2h, 3C4-3C5h, 3CE-3CFh, 3D43D5h, and 3D8-3DAh. Palette Address Decoding 0 External palette registers can be accessed only at 3C6h-3C9h (default) 1 External palette regs can be accessed at 3C6h-3C9h & 83C6h-83C9h Attribute Flip-Flop Status (read only) 0 = Index, 1 = Data Revision 1.2 99 65540 / 545 (R) Extension Registers CPU INTERFACE CTRL REGISTER 2 (XR03) Read/Write at I/O Address 3D7h Index 03h This bit may be set to 0 to effectively create a CPU-transparent delay, however this is not compatible with some systems: some systems ignore RDY for palette accesses, so for those systems, this bit must be set to 1. D7 D6 D5 D4 D3 D2 D1 D0 5 Palette Write Shadow DR Access Ena (545 only) 7-6 Diagnostic ( R/W but should be set to 0 ) Reserved (0) Reserved(0) Palette RDY Response Diagnostic (Set to 0) Reserved(0) 0 Palette Write Shadow 0 1 1 3-2 4 Chip responds normally to Palette Write accesses (LDEV# is returned for VL-Bus and DEVSEL# is returned for PCI bus) Palette write commands are executed internally but the chip does not respond externally (LDEV# is not returned for VL-Bus and DEVSEL# is not returned for PCI bus). This conforms to both VL-Bus and PCI bus "Palette Shadowing" requirements as it forces the access to be passed on to the ISA bus where add-in cards may be shadowing the VGA color palette data. This bit should normally be set to 1. DR Register Access Enable 0 32-Bit DRxx register access Disabled (Default) 1 DRxx registers accessible at I/O port defined by XR07. Reserved (0) ISA Bus Palette Access RDY Response 0 1 Hold off the CPU using RDY for palette accesses (read or write to 3C63C9h). Do not hold off the CPU using RDY for palette accesses (read or write to 3C6-3C9h) The internal RAMDAC has a minimum specification for time between accesses. A faster CPU is more likely to violate this specification, so it is normally required to add delay between accesses in software. Revision 1.2 100 65540 / 545 (R) Extension Registers MEMORY CONTROL REGISTER 1 (XR04) Read/Write at I/O Address 3D7h Index 04h DRAMs as 1MB of display memory and set to 01 to use DRAM A as 512KB of display memory and DRAM C as an external frame buffer). D7 D6 D5 D4 D3 D2 D1 D0 2 Memory Configuration Memory Wraparound Ctrl Reserved(0) Write Buffer Enable 4-3 Reserved(0) 1-0 5 Memory Wraparound Control This bit enables bits 16-17 of the CRT Controller address counter (default = 0 on reset). 0 Disable CRTC addr counter bits 16-17 1 Enable CRTC addr counter bits 16-17 Reserved (0) CPU Memory Write Buffer 0 Memory Configuration 00 32-bit memory data path. Memory data bus is on MAD15-0 & MBD15-0 (DRAMs A and B). If frame acceleration is enabled and embedded frame buffer is selected, the data will be stored in both DRAMs A and B. An external frame buffer can be enabled on DRAM C with this setting. 01 16-bit data path (DRAM A only). The memory data bus is on MAD15-0. If frame acceleration is enabled and embedded frame buffer is selected, the data will be restricted to storage in DRAM A only. An external frame buffer can be enabled on DRAM C with this setting. 10 32-bit memory data path. Memory data bus is on MAD15-0 & MCD15-0 (DRAMs A & C). DRAM C cannot be used as an external frame buffer with this setting, but programming can select between this setting and '01' to switch the function of DRAM C between use as display memory and use as an external frame buffer. 11 Reserved 1 7-6 Disable CPU memory write buffer (default) Enable CPU memory write buffer Reserved (0) DRAM A must always be present and if that is the only DRAM present, setting 01 must be used. DRAM B may optionally be present and if it is, setting 00 may be used (either 00 or 01 may be programmed with DRAMs A & B physically present). If all three DRAMs are present, setting 00 would normally be used (00, 01, and 10 are all allowable). Setting 10 would be used where only two DRAMs (A and C) are physically present (this field is set to 10 to use both Revision 1.2 101 65540 / 545 (R) Extension Registers MEMORY CONTROL REGISTER 2 (XR05) Read/Write at I/O Address 3D7h Index 05h 4 CAS# / WE# Select for DRAMs A & B 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Disable Long CPU Cycles CPU Access CAS# Ctrl Display Access CAS# Ctrl DRAM CAS# Address Memory CAS/WE Select Frame Buffr CAS/WE Slct PC Video Interface Enable PC Video Interface Width 0 1 0 1 6 Enable long CPU cycles (default on RESET). This puts as many CPU cycles as possible into one RAS cycle. Disable long CPU cycles. CPU-Mem Access CAS# Cycle Ctrl (545) Display Mem Access CAS# Cycle Ctrl (545) 7 2 CAS# and 1 WE# configuration 256Kx16 DRAM is used (default) 1 CAS# and 2 WE# configuration 256Kx16 DRAM is used PC Video Interface Enable 0 1 Bit-1 affects accesses to display memory initiated by the 65545 for display refresh. Bit-2 affects CPU accesses to display memory in the 65545. Both bits are defined as follows: 0 3-MCLK CAS# cycle (2 low, 1 high) for all read or write accesses (default) 1 4-MCLK CAS# cycle (3 low, 1 high) for all read accesses and for the first CAS# cycle of page-mode write accesses (following cycles are 2L/1H) These bits may be set to create looser memory timing (e.g., for 3.3V operation, to allow use of cheaper DRAMs, etc.). 4MCLK CAS cycles are not supported in the 65540. 3 CAS# / WE# Select for DRAM C This bit is effective when XR6F[7]=1. Disable Long CPU Cycles 0 1 2 5 2-CAS# / 1-WE# 256Kx16 DRAM configuration is used (default) 1 CAS# and 2 WE# 256Kx16 DRAM configuration is used Disable PC Video Interface (default) Enable PC Video interface on DRAM 'C' pins (MCD15-0, RASC#, CASCH#, CASCL#, and WEC#). If bit-7 of this register is set to 1, OEC#, AA9, ACTI, ENABKL, and CA8-9 also serve as PC Video Interface pins. An external frame buffer cannot be used in this configuration. PC Video Interface Control 0 1 18-bit PC Video interface 24-bit PC Video interface Note: When this bit is set to 1, AA9, ENABKL, ACTI pins are used for video inputs therefore they lose their alternate functions. When this bit is set to 1, a 24-bit panel interface is also available (CA0-7 become P16-23). This bit should not be set to 1 if the AD# (A26-27 enable) or EC# (external clock) configuration bits are asserted low at reset (since this enables ACTI and ENABKL to perform alternate functions). Asymmetric Address for DRAMs A & B 0 Symmetric 256Kx16 DRAM is used (9-bit RAS/CAS addresses) (default) 1 Asymmetric 256Kx16 DRAM is used (10-bit RAS/8-bit CAS address) Asymmetric address DRAMs should not be used (and this bit should not be set to one) if AA9 is used as a 32KHz clock input (see XR33 bit-6) or if 24-bit PC-Video interface is enabled (see bit-7 of this register). See also XR6F bit-2 (address symmetry control for DRAM C). Revision 1.2 102 65540 / 545 (R) Extension Registers PALETTE CONTROL REGISTER (XR06) Read/Write at I/O Address 3D7h Index 06h 5 0 Use internal VGA palette (Default on reset). 1 Bypass internal VGA palette which will be powered down if DAC is disabled. D7 D6 D5 D4 D3 D2 D1 D0 Pixel Out Diagnostic Mode Internal DAC Disable 7-6 00 NTSC weighting algorithm (default on reset) 01 Equivalent weighting algorithm 10 Green only 11 Color (no reduction). This setting should be used when driving color panels. FP Color Reduction Select Pixel Data Pin Diagnostic Output Mode 0 1 1 Color Reduction Select These bits are effective in flat panel mode. These bits select the algorithm used to reduce 24-bit or 18-bit color data to 8-bit or 6-bit color data for monochrome panels. Display Mode Color Depth PC Video Color Key Enble Bypass Internal Palette 0 Bypass Internal VGA Palette Normal operation. Pixel data (P15:0) pins output flat panel pixel data (default on Reset). Output CRT pixel data on pixel data pins P0-7 and output various internal signals on pixel data pins P8-15 for diagnostic purposes. Internal DAC Disable This bit affects the DAC analog outputs. 0 Enable internal DAC (default on Reset). DAC analog outputs (R, G, B) will be active and HSYNC and VSYNC signals are driven (Default on reset). 1 Disable internal DAC. The DAC analog outputs (R, G, B) will be 3stated. Setting this bit forces power down of the internal DAC. HSYNC and VSYNC are forced inactive if XR5D[6] is 0 and will be driven if XR5D[6] is 1. 3-2 Display Mode Color Depth 00 01 10 11 4 4 or 8 bits-per-pixel (default on reset) 16 bpp (5-5-5) (Targa compatible) 24 bpp (true color) 16 bpp (5-6-5) (XGA compatible) PC Video Color Key Enable 0 Disable PC Video Overlay (default on reset) 1 Enable PC Video Overlay on color key Revision 1.2 103 65540 / 545 (R) Extension Registers I/O BASE REGISTER (XR07) Read/Write at I/O Address 3D7h Index 07h LINEARADDRESSINGBASEREGISTER(XR08) Read/Write at I/O Address 3B7h/3D7h Index 08h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 I/O Base for 32-Bit Regs (65545 only) 7-0 Linear Address Base I/O Base for 32-Bit Registers (65545 only) 7-0 In ISA and VL-Bus configuration, these bits determine the I/O range for the Doubleword Hardware Cursor & BitBLT registers (DRxx). The value programmed here is matched against CPU addresses A15 & A82. Address A9 must equal 1 and A14-10 select one of 32 DR registers. For example, a programmed value of 074h (011101 00b) would result in this DR register mapping: DRxx: nxxx xx1n nnnn nn00b DR00: 03D0h = 0000 0011 1101 0000b DR01: 07D0h = 0000 0111 1101 0000b DR02: 0BD0h = 0000 1011 1101 0000b DR03: 0FD0h = 0000 1111 1101 0000b DR04: 13D0h = 0001 0011 1101 0000b DR05: 17D0h = 0001 0111 1101 0000b DR06: 1BD0h = 0001 1011 1101 0000b DR07: 1FD0h = 0001 1111 1101 0000b DR08: 23D0h = 0010 0011 1101 0000b DR09: 27D0h = 0010 0111 1101 0000b DR0A: 2BD0h = 0010 1011 1101 0000b DR0B: 2FD0h = 0010 1111 1101 0000b DR0C: 33D0h = 0011 0011 1101 0000b In VL-Bus configuration, if linear addressing is enabled (XR0B[4]=1), these 8 bits are compared to A[27:20] to determine the base address of the 1MB of display memory in the 256MB VL-Bus address space (normally the VL address space is 4GB, but only 28 bits of address are decoded by the chip). For example, if the video memory is to be placed at 12MB (0C00000-0CFFFFFh), this register should be programmed to '00001100b'. Note that as a result, programming this register to 0 is typically not useful. If A26-27 are not available (used for ACTI and ENABKL if Configuration Register XR01 bit-6 = 1) then bits 6-7 of this register are ignored and only A20-25 are compared against bits 0-5 of this register to determine the base address for the linear frame buffer in the VL-Bus / 486 CPU memory space. Similarly, if A25 and/or A24 are not available (see configuration bits 3, 4, and 7), bits 5 and/or 4 are also ignored. In ISA bus configuration, address inputs A24-27 are never available, so bits 4-7 of this register are ignored and A20-23 are compared against bits 0-3 of this register to determine the base address for the linear frame buffer in the 16MB ISA memory space. The DRxx registers are enabled for access by setting XR03[1]. They are disabled following Reset. The programmer should write this register before enabling access to the DRxx registers. In PCI bus configuration, this register is ignored. The PCI Configuration IOBASE register is used to determine the base address for the 32-bit registers in the PCI I/O space. Note that for PCI bus configuration only, the 32-bit registers may also be memory mapped: MBASE defines a 2MB memory space with frame buffer memory mapped into the lower megabyte and the 32-bit registers mapped into the upper megabyte. Revision 1.2 Linear Address Base In PCI bus configuration, this register is ignored. The PCI Configuration MBASE register is used to determine the base address for the linear frame buffer in the 4GB (full 32-bit address) PCI memory address space. 104 65540 / 545 (R) Extension Registers CPU PAGING REGISTER (XR0B) Read/Write at I/O Address 3D7h Index 0Bh 4 D7 D6 D5 D4 D3 D2 D1 D0 Memory Mapping Mode Single/Dual Map CPU Address Divide by 4 Extended Text Mode (545) Linear Addressing Enable 7-5 Linear Addressing Enable 0 Standard VGA (A0000 - BFFFF) memory space decoded on-chip using A17-19 (default on Reset) 1 Linear Addressing Enabled. See XR08 (Linear Addressing Base) for base address selection. Ignored in PCI bus configuration (see DEVCTL). Reserved (0) Reserved(0) 0 1 2 3 Memory Mapping Mode 0 Normal Mode (VGA compatible) (default on Reset) 1 Extended Mode (mapping for > 256 KByte memory configurations) CPU Single/Dual Mapping 0 CPU uses only a single map to access the extended video memory space (default on Reset) 1 CPU uses two maps to access the extended video memory space. The base addresses for the two maps are defined in the Low Map Register (XR10) and High Map Register (XR11). CPU Address Divide by 4 0 Disable divide by 4 for CPU addresses (default on Reset) 1 Enable divide by 4 for CPU addresses. This allows the video memory to be accessed sequentially in mode 13. In addition, all video memory is available in mode 13 by setting this bit. Extended Text Mode ( 65545 only ) Set to enable text font 'scrambling' in plane 2. Setting this bit improves text mode performance in single-DRAM configurations (with the proper BIOS support for font load/reload functions). This bit should be set in single DRAM configurations only. This bit is supported in the 65545 only; it should be programmed to 0 in the 65540. Revision 1.2 START ADDRESS TOP REGISTER (XR0C) Read/Write at I/O Address 3D7h Index 0Ch D7 D6 D5 D4 D3 D2 D1 D0 Start Address Top Reserved(0) 1-0 Start Address Top These bits defines the high order bits for the Display Start Address when 512 KBytes or more of memory is used (see XR04 bits 1-0). 7-2 105 Reserved (0) 65540 / 545 (R) Extension Registers AUXILIARY OFFSET REGISTER (XR0D) Read/Write at I/O Address 3D7h Index 0Dh TEXT MODE CONTROL REGISTER (XR0E) Read/Write at I/O Address 3D7h Index 0Eh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 LSB of Offset (CR13) LSB of Alt Offset (XR1E) Reserved(0) Cursor Blink Disable Cursor Style Reserved(0) Alt Cursor Start (65545) Sync Reset Ignore 0 Offset Register LSB This register is effective for both CRT and flat panel text modes. This bit provides finer granularity to the display memory address offset when word and doubleword modes are used. This bit is used with the regular Offset register (CR13). 1 Reserved (0) 2 Cursor Mode 0 1 Alternate Offset Register LSB This bit provides finer granularity to the display memory address offset when word and doubleword modes are used. This bit is used with the Alternate Offset register (XR1E). 7-2 1-0 3 Cursor Style 0 1 6-4 Reserved (0) Blinking (default on Reset). Non-blinking Replace (default on Reset) Exclusive-Or Alternate Cursor Start (65545 Only) When the alternate CRTC registers are active, this field may be set to specify the Cursor Start Scan Line instead of CR0A bits 0-4 (this field specifies alternate bits 0-2 with bits 3-4 assumed to be 0). VGA software typically changes the shape of the cursor frequently between underline and block styles. This field allows the cursor style to be fixed (typically to 'block' for improved readability on panels). 7 Synchronous Reset Ignore When this bit is set, the chip will ignore SR00 bit-1 (Synchronous Reset) and will remain in normal operation. Synchronous reset is a holdover from the original VGA which is no longer required. VGA software, however, performs synchronous resets frequently, creating the possibility for display memory corruption if the chip is left in the synchronous reset state for too long. The 65540 / 545 display memory sequencer does not need to be periodically reset, so this bit is provided to prevent potential display memory corruption problems. For absolute VGA compatibility, this bit may be set to 0. Revision 1.2 106 65540 / 545 (R) Extension Registers SOFTWARE FLAGS REGISTER 0 (XR0F) Read/Write at I/O Address 3D7h Index 0Fh D7 D6 D5 D4 D3 D2 D1 D0 Memory Size Reserved(0) Hi / True Color Select Packed Pixel Dot Clock Interlace Select Text Compensation Enable This register contains eight read-write bits which have no internal hardware function. All bits are reserved for use by BIOS and driver software. For reference, the functions of the bits of this register are currently defined as follows: 1-0 Memory Size 00 256KB 01 512KB 1x 1MB 2-3 4 Reserved (0) Hi Color / True Color 0 1 5 Current mode is not hi-/true-color mode Current mode is hi-color / true-color mode Packed-Pixel Mode Dot Clock 0 1 Use default dot clock in packed-pixel modes Use 40MHz dot clock in packed-pixel modes This bit is used for high resolution panels in panel mode only. 6 Interlace Select 0 1 7 Set mode 24h, 34h, 72h/75h or 7Eh interlaced Set mode 24h, 34h, 72h/75h or 7Eh non-interlaced Text Compensation Enable / Disable 0 1 Tall font disabled Tall font enabled See also XR2B, XR44, XR45 for definition of other software flags registers. Revision 1.2 107 65540 / 545 (R) Extension Registers SINGLE/LOW MAP REGISTER (XR10) Read/Write at I/O Address 3D7h Index 10h HIGH MAP REGISTER (XR11) Read/Write at I/O Address 3D7h Index 11h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Single or Lower Map Base Address Bits 17-10 Higher Map Base Address Bits 17-10 This register effects CPU memory address mapping. 7-0 This register effects CPU memory address mapping. Single / Low Map Base Address Bits 17-10 7-0 These bits define the base address in single map mode (XR0B bit-1 = 0), or the lower map base address in dual map mode (XR0B bit-1 = 1). The memory map starts on a 1K boundary in planar modes and on a 4K boundary in packed pixel modes. In case of dual mapping, this register controls the CPU window into display memory based on the contents of GR06 bits 3-2 as follows: GR06 Bits 3-2 00 01 10 11 Revision 1.2 High Map Base Address Bits 17-10 These bits define the Higher Map base address in dual map modes (XR0B bit-1=1). The memory map starts on a 1K boundary in planar modes and on a 4K boundary in packed pixel modes. This register controls the CPU window into display memory based on the contents of GR06 bits 3-2 as follows: GR06 bits 3-2 00 01 10 11 Low Map A0000-AFFFF A0000-A7FFF B0000-B7FFF Single mapping only B8000-BFFFF Single mapping only 108 High Map B0000-BFFFF A8000-AFFFF Don't care Don't care 65540 / 545 (R) Extension Registers EMULATION MODE REGISTER (XR14) Read/Write at I/O Address 3D7h Index 14h 6 VSync Status Mode 0 D7 D6 D5 D4 D3 D2 D1 D0 Emulation Mode 1 Herc Config (read only) DE Status Mode V Retrace Status Mode VSync Status Mode Interrupt Polarity 1-0 4 5 Interrupt Output Function This bit controls the function of the interrupt output pin (IRQ): Interrupt State Disabled Enabled, Inactive Enabled, Active Emulation Mode 00 01 10 11 3-2 7 Prevent VSync status from appearing at bit 7 of Input Status Register 1 (I/O Address 3BAh/3DAh). Normally used for CGA, EGA, and VGA modes. Enable VSync status to appear as bit-7 of Input Status Register 1 (I/O Address 3BAh/3DAh). Normally used for MDA/Hercules mode. VGA mode (default on Reset) CGA mode MDA/Herculesmode EGA mode Bit-7=0 3-state 3-state 3-state Bit-7=1 3-state Low High Hercules Configuration Register (3BFh) readback (read only) Display Enable Status Mode 0 Select Display Enable status to appear at bit 0 of Input Status register 1 (I/O Address 3BAh/3DAh) (default on reset). Normally used for CGA, EGA, and VGA modes. 1 Select HSync status to appear at bit 0 of Input Status register 1 (I/O Address 3BAh/3DAh). Normally used for MDA / Hercules mode. Vertical Retrace Status Mode 0 1 Revision 1.2 Select VerticalRetrace status to appear at bit 3 of Input Status register 1 (I/O Address 3BAh/3DAh) (default on Reset). Normally used for CGA, EGA, and VGA modes. Select Video to appear at bit 3 of Input Status register 1 (I/O Address 3BAh/3DAh). Normally used for MDA / Hercules mode. 109 65540 / 545 (R) Extension Registers WRITE PROTECT REGISTER (XR15) Read/Write at I/O Address 3D7h Index 15h 6 Write Protect Group 0 Registers This bit affects CR0-7 (except CR07 bit-4). This bit is logically ORed with CR11 bit-7. 7 D7 D6 D5 D4 D3 D2 D1 D0 Write Protect AR11 This bit is ORed with bit-0, therefore writing to AR11 is possible only if both bit-0 and bit-7 are 0. This feature is used for write protection of the overscan color. This is important in order to keep application software from changing the border color while still permitting the attribute controller to be changed for the addressable portion of the display. Overscan is increasingly becoming an ergonomics requirement and this bit will ensure software compatibility. Wr Protect Group 1 Regs Wr Protect Group 2 Regs Wr Protect Group 3 Regs Wr Protect Group 4 Regs Wr Protect Group 5 Regs Wr Protect Group 6 Regs Wr Protect Group 0 Regs Wr Protect AR11 This register controls write protection for various groups of registers as shown. 0 = unprotected (default on Reset), 1= protected. 0 Write Protect Group 1 Registers This bit affects the Sequencer registers (SR00-04), Graphics Controller registers (GR00-08), and Attribute Controller registers (AR00-14). Note that AR11 is also protected by bit-7 which is ORed with this bit. 1 Write Protect Group 2 Registers This bit affects CR09 bits 0-4, CR0A, and CR0B. 2 Write Protect Group 3 Registers This bit affects CR07 bit-4, CR08, CR11 bits 5-4, CR13, CR14, CR17 bits 0-1 and bits 3-7, and CR18. 3 Write Protect Group 4 Registers This bit affects CR09 bits 5-7, CR10, CR11 bits 0-3 and bits 6-7, CR12, CR15, CR16, and CR17 bit-2. 4 Write Protect Group 5 Registers This bit affects the Miscellaneous Output register (3C2h) and the Feature Control register (3BAh/3DAh). 5 Write Protect Group 6 Registers This bit affects the VGA color palette registers (3C6h-3C9h). If this bit is set, all VGA color palette registers are write protected. Revision 1.2 110 65540 / 545 (R) Extension Registers VERTICAL OVERFLOW REGISTER (XR16) Read/Write at I/O Address 3D7h Index 16h HORIZONTALOVERFLOWREGISTER(XR17) Read/Write at I/O Address 3D7h Index 17h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Vertical Total Bit 10 Vertical Display End Bit 10 Vertical Sync Start Bit 10 Reserved(R/W) Vertical Blank Start Bit 10 Reserved(R/W) Line Compare Bit 10 Reserved(R/W) Horizontal Total Bit 8 Horizontal Disp End Bit 8 Horizontal Sync Start Bit 8 Horizontal Sync End Bit 5 Horizontal Blank Strt Bit 8 Horizontal Blank End Bit 6 Line Compare Bit 10 Reserved(R/W) This register is used for both normal and alternate vertical parameters. This register is used for both normal and alternate horizontal parameters. 0 Vertical Total Bit-10 0 Horizontal Total Bit-8 1 Vertical Display End Bit-10 1 Horizontal Display End Bit-8 2 Vertical Sync Start Bit-10 2 Horizontal Sync Start Bit-8 3 Reserved (R/W) 3 Horizontal Sync End Bit-5 4 Vertical Blank Start Bit-10 4 Horizontal Blank Start Bit-8 5 Reserved (R/W) 5 Horizontal Blank End Bit-6 6 Line Compare Bit-10 6 Line Compare Bit-10 7 Reserved (R/W) 7 Reserved (R/W) Revision 1.2 111 65540 / 545 (R) Extension Registers ALTERNATEHORIZONTAL DISPLAY END REGISTER (XR18) Read/Write at I/O Address 3D7h Index 18h ALTERNATE HORIZONTAL SYNC START REGISTER (XR19) Read/Write at I/O Address 3D7h Index 19h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Alternate H Display End FP HSync Start This register is used in flat panel and CRT CGA text and graphics modes, and Hercules graphics mode. 7-0 This register is used in all flat panel modes with horizontal compression disabled, to set the horizontal sync start. This register is also used in CRT CGA text and graphics modes, and Hercules graphics mode. Alternate Horizontal Display End This register specifies the number of characters displayed per scan line, similar to CR01. 7-0 These bits specify the beginning of the HSync in terms of character clocks from the beginning of the display scan. Similar to CR04. Programmed Value = Actual Value - 1 Note: This register is used in emulation modes only. It is not used in CRT or flat panel VGA modes. Revision 1.2 Alternate Horizontal Sync Start Programmed Value = Actual Value - 1 112 65540 / 545 (R) Extension Registers ALTERNATE HORIZONTAL SYNC END REGISTER (XR1A) Read/Write at I/O Address 3D7h Index 1Ah ALTERNATEHORIZONTALTOTALREGISTER (XR1B) Read/Write at I/O Address 3D7h Index 1Bh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 FP H Sync End FP H Total Alternate H Sync Delay Reserved(0) This register is used in all flat panel modes with horizontal compression disabled, CRT CGA text and graphics modes, and Hercules graphics mode. 4-0 This register is used in all flat panel modes with horizontal compression disabled, CRT CGA text and graphics modes, and Hercules graphics mode. Alternate Horizontal Sync End 7-0 Lower 5 bits of the character clock count which specifies the end of horizontal sync. Similar to CR05. If the horizontal sync width desired is N clocks, then programmed value is: Alternate Horizontal Total This register contents are the total number of character clocks per line. Similar to CR00. Programmed Value = Actual Value - 5 (N + Contents of XR19) ANDed with 01F Hex 6-5 CRT Alternate Horizontal Sync Delay See CR05 for description 7 Reserved (0) Revision 1.2 113 65540 / 545 (R) Extension Registers ALTERNATE HORIZONTAL BLANK START / HORIZONTAL PANEL SIZE REGISTER(XR1C) Read/Write at I/O Address 3D7h Index 1Ch ALTERNATE HORIZONTAL BLANK END REGISTER (XR1D) Read/Write at I/O Address 3D7h Index 1Dh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 H Blank End H Blank Start (Horizontal Panel Size) DE Skew Control Split Screen Enhance The value in this register is the Horizontal Panel Size in all Flat Panel Modes. In CRT mode, it is used for CGA text and graphics and Hercules graphics modes. 7-0 Bits 0-6 of this register are used in CRT CGA text and graphics modes and CRT Hercules graphics mode. Bit 7 of this register is used for all CRT and flat panel modes. FP Horizontal Panel Size 4-0 Horizontal panel size is programmed in terms of number of 8-bit (graphics/text) or 9-bit (text) characters. For double drive flat panels the actual horizontal panel size must be a multiple of two character clocks. See CR03 for description 6-5 CRTAlternateDisplayEnableSkewControl See CR03 for description 7 Programmed Value = Actual Value - 1 Line Compare Fix This bit affects all CRT and FP text modes. This bit is 0 on reset. or 7-0 CRT Alternate Horizontal Blank Start CRT Alternate Horizontal Blank Start 0 See CR02 for description Programmed Value = Actual Value - 1 1 Internal Line Compare (split screen) flag is not delayed so that the Vertical Row Counter is reset too early which in text mode causes the first scanline of the first character row following split screen to be skipped (not displayed). This is IBM VGA compatible. Internal Line Compare (split screen) flag is delayed so that the Vertical Row Counter is reset properly which in text mode causes the first scanline of the first character row following split screen to be displayed. Note: This register is used in emulation modes only. It is not used in CRT or flat panel VGA modes. Revision 1.2 114 65540 / 545 (R) Extension Registers ALTERNATE OFFSET REGISTER (XR1E) Read/Write at I/O Address 3D7h Index 1Eh VIRTUAL EGA SWITCH REGISTER (XR1F) Read/Write at I/O Address 3D7h Index 1Fh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Virtual EGA Switches Alternate Display Buffer Width Reserved(0) Sense Select This register is used in all flat panel modes, CRT CGA text and graphics modes and Hercules graphics mode. 7-0 3-0 Virtual Switch Register If bit-7 is '1', then one of these four bits is read back in Input Status Register 0 (3C2h) bit 4. The selected bit is determined by Miscellaneous Output Register (3C2h) bits 3-2 as follows: Alternate Offset See CR13 for description Programmed Value = Actual Value - 1 Misc 3-2 00 01 10 11 6-4 Reserved (0) 7 Sense Select 0 1 Revision 1.2 115 XR1F Bit Selected bit-3 bit-2 bit-1 bit-0 Select the output of the internal RGB comparator (Sense) for readback in Input Status Register 0 bit-4 (default on Reset). Select one of bits 3-0 for readback in Input Status Register 0 bit-4. 65540 / 545 (R) Extension Registers ALTERNATE MAXIMUM SCANLINE REGISTER (XR24) Read/Write at I/O Address 3D7h Index 24h ALTERNATE HORIZONTAL SYNC START OFFSET REGISTER (XR26) Read/Write at I/O Address 3D7h Index 26h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Alternate Max Scanlines Alt H Sync Start Offset Reserved(R/W) This register is used in flat panel text mode when TallFont is enabled during vertical compensation. This register is used in flat panel mode. 7-0 4-0 Alternate Maximum Scanlines (AMS) Horizontal Sync Start Offset This value is added to CR04 ( Horizontal Sync Start) when XR02 bit 2 is set to '1'. Programmed Value = number of scanlines minus one per character row of TallFont Double scanned lines, inserted lines, and replicated lines are not counted. 7-5 Reserved (R/W) ALTERNATE TEXT MODE / HORIZONTAL VIRTUAL PANEL SIZE REGISTER (XR25) Read/Write at I/O Address 3D7h Index 25h D7 D6 D5 D4 D3 D2 D1 D0 AltText Mode H Virtual Panel Size This register is used in flat panel 9-dot text modes. 7-0 Alternate Text Mode Horizontal Virtual Panel Size Programmed Value = 9/8 [XR1C + 1] - 1 Revision 1.2 116 65540 / 545 (R) Extension Registers VIDEO INTERFACE REGISTER (XR28) Read/Write at I/O Address 3D7h Index 28h 6 8-Bit Video Pixel Panning This bit is effective for both CRT and flat panel when the 8-bit video data path is selected (bit-4 = 1). 0 AR13 bits 2-1 are used to control pixel panning (default on Reset) 1 AR13 bits 2-0 are used to control pixel panning 7 Tall Font Replication D7 D6 D5 D4 D3 D2 D1 D0 Reserved(0) Blank#/DE Select Reserved(0) 256-Color Video Path InterlaceMode 8-Bit Video Pixel Panning Tall Font Replication 0 Reserved (0) 1 Blank / Display Enable Select This bit is effective in CRT mode only. In flat panel mode, XR54 bit-1 controls BLANK# functionality. 0 BLANK# controls color palette blanking (default on reset) 1 Display Enable controls color palette blanking 0 1 HALF LINE COMPARE REGISTER (XR29) Read/Write at I/O Address 3D7h Index 29h D7 D6 D5 D4 D3 D2 D1 D0 Half-Line Compare Note: This bit also controls the functionality of pins 68 or 69 when BLANK# / DE is selected for output instead of the default function (M is normally output on pin 69 and LP is normally output on pin 68 but this can be changed by XR4F bits 6 and 7 respectively). See also XR54 bits 0 and 1. 3-2 In Interlaced mode CRT operation, this register is used to generate the Half Line Compare Signal. Reserved (0) 4 256-Color Video Path This bit is effective for both CRT and flat panel in 256-color modes other than mode 13 (i.e., Super VGA modes). 0 4-bit video data path (default on reset) 1 8-bit video data path (horizontal pixel panning is controlled by bit-6) Note: GR05 bit-5 must be 0 if this bit is set 5 Interlace Video This bit is effective only for CRT graphics mode. This bit should be programmed to 0 for flat panel. In interlace mode XR29 holds the half-line positioning of VSync for odd frames. 0 Non-interlaced video (default on reset) 1 Interlaced video Revision 1.2 Tall font replicates lines 1, 9 and 12 Tall font replicates line 0 twice and line 15 once 7-0 CRT Half-Line Value In CRT interlaced video mode this value is used to generate the 'half-line compare' signal that controls the positioning of the VSync for odd frames. 117 65540 / 545 (R) Extension Registers SOFTWARE FLAGS REGISTER 1 (XR2B) Read/Write at I/O Address 3D7h Index 2Bh FLM DELAY REGISTER (XR2C) Read/Write at I/O Address 3D7h Index 2Ch D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Flag 0 Flag 1 Flag 2 FLM Delay Flag 3 Flag 4 Flag 5 Flag 6 Flag 7 This register contains eight read-write bits which have no internal hardware function. All bits are reserved for use by BIOS and driver software. For reference, the functions of the bits of this register are currently defined as follows: 7-0 This register is used only in flat panel mode when XR2F bit-7=0. The First Line Marker (FLM) signal is generated from an internal FP VSync active edge with a delay specified by this register. The FLM pulse width is always one line for SS panels and two lines for DD panels. Display Mode 7-0 These bits are used by the BIOS to store the current display mode number. These bits define the number of HSyncs between the internal VSync and the rising edge of FLM. See also XR0F, XR44, XR45 for definition of other software flags registers. Revision 1.2 FLM Delay (VDelay) 118 65540 / 545 (R) Extension Registers LPDELAY REGISTER(CMPRENABLED)(XR2D) Read/Write at I/O Address 3D7h Index 2Dh LP DELAYREGISTER (CMPRDISABLED)(XR2E) Read/Write at I/O Address 3D7hIndex 2Eh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 LP Delay (graphics mode horizontal compression enabled) LP Delay (graphics mode horizontal compression disabled) This register is used only in flat panel mode when XR2F bit-6 = 0 and graphics mode horizontal compression is enabled. The LP output is generated from the FP Blank inactive edge with a delay specified by XR2F bit-5 and the value in this register. The LP pulse width is specified in register XR2F. This register is used only in flat panel mode when XR2F bit-6 = 0 and 9-dot text mode is used. The LP output is generated from the FP Blank inactive edge with a delay specified by XR2F bit-4 and the value in this register. The LP pulse width is specified in register XR2F. 7-0 7-0 LP Delay These bits define the number of character clocks between the FP Blank inactive edge and the rising edge of the LP output in flat panel 9-dot text modes. The msb (bit 8) of this parameter is XR2F bit-4. These bits define the number of character clocks between the FP Blank inactive edge and the rising edge of the LP output in flat panel mode with 9-dot text mode forced to 8-dot text. The msb (bit 8) of this parameter is XR2F bit-5. Programmed Value = Actual Value - 1 Note: Programmed Value = Actual Value - 1 Note: LP Delay For DD panels without frame acceleration, the programmed value should be doubled. For DD panels without frame acceleration, the programmed value should be doubled. Revision 1.2 119 65540 / 545 (R) Extension Registers LP WIDTH REGISTER (XR2F) Read/Write at I/O Address 3D7h Index 2Fh D7 D6 D5 D4 D3 D2 D1 D0 LP Width LP Delay (XR2E) Bit-8 LP Delay (XR2D) Bit-8 LP Delay Disable FLM Delay Disable This register is used only in flat panel mode. This register together with XR2D or XR2E defines the LP output pulse in flat panel mode. 3-0 LP Width (HWidth) These bits define the width of LP output pulse in terms of number of character (8-dot only) clocks in flat panel mode. Programmed Value = Actual Value - 1 4 LP Delay (XR2E) Bit 8 This bit is the msb of the LP Delay parameter for 9-dot text modes. 5 LP Delay (XR2D) Bit 8 This bit is the msb of the LP Delay parameter for graphics mode with horizontal compression disabled. 6 LP Delay Disable 0 LP Delay Enable: XR2D and XR2F bit-5 (or XR2E and XR2F bit-4) are used to delay the LP active edge with respect to the FP Blank inactive edge. 1 LP Delay Disable: LP active edge will coincide with the FP Blank inactive edge. 7 FLM Delay Disable 0 FLM Delay Enable: XR2C is used to delay the external FLM active edge with respect to the internal FP VSync active edge. 1 FLM Delay Disable: the external FLM active edge will coincide with the internal FLM active edge. Revision 1.2 120 65540 / 545 (R) Extension Registers CLOCK DIVIDE CONTROL REGISTER (XR30) Read/Write at I/O Address 3D7h Index 30h D7 D6 D5 D4 D3 D2 D1 D0 Reference Divisor Select VCO Post Divide Reserved(R/W) The three clock data registers (XR30-XR32) are programmed with the loop parameters to be loaded into the clock synthesizer. The Memory and Video clock VCO's both have programmable registers. Which of the VCO's is currently selected for programming is determined by the Clock Register Program Pointer (XR33[5]). The data written to this register is calculated based on the reference frequency, the desired output frequency, and characteristic VCO constraints as described in the Functional Description. Data is written to registers XR30, and XR31 followed by a write to XR32. The completion of the write to XR32 causes data from all three registers is transferred to the VCO register file simultaneously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence. 0 Reference Divisor Select Selects the reference pre-scale factor: 0 1 3-1 Divide by 4 Divide by 1 Post Divisor Select Selects the post-divide factor: 000 001 010 011 100 101 110 111 7-4 Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Divide by 128 Reserved (R/W) Revision 1.2 121 65540 / 545 (R) Extension Registers CLOCK M-DIVISOR REGISTER (XR31) Read/Write at I/O Address 3D7h Index 31h CLOCK N-DIVISOR REGISTER (XR32) Read/Write at I/O Address 3D7h Index 32h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 M-Divisor Value N-Divisor Reserved(R/W) Reserved(R/W) The three clock data registers (XR30-XR32) are programmed with the loop parameters to be loaded into the clock synthesizer. The Memory and Video clock VCO's both have programmable registers. Which of the VCO's is currently selected for programming is determined by the Clock Register Program Pointer (XR33[5]). The data written to this register is calculated based on the reference frequency, the desired output frequency, and characteristic VCO constraints as described in the Functional Description. Data is written to registers XR30, and XR31 followed by a write to XR32. The completion of the write to XR32 causes data from all three registers is transferred to the VCO register file simultaneously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence. 6-0 The three clock data registers (XR30-XR32) are programmed with the loop parameters to be loaded into the clock synthesizer. The Memory and Video clock VCO's both have programmable registers. Which of the VCO's is currently selected for programming is determined by the Clock Register Program Pointer (XR33[5]). The data written to this register is calculated based on the reference frequency, the desired output frequency, and characteristic VCO constraints as described in the Functional Description. Data is written to registers XR30, and XR31 followed by a write to XR32. The completion of the write to XR32 causes data from all three registers is transferred to the VCO register file simultaneously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence. VCO M-Divisor 6-0 M-Divisor value calculated for the desired output frequency. 7 N-Divisor value calculated for the desired output frequency. Reserved (R/W) Revision 1.2 VCO N-Divisor 7 122 Reserved (R/W) 65540 / 545 (R) Extension Registers CLOCK CONTROL REGISTER (XR33) Read/Write at I/O Address 3D7h Index 33h 5 This bit determines which of the VCO's is being programmed. Following a write to XR32 the data contained in XR32:30 is synchronously transferred to the appropriate VCO counter latch. D7 D6 D5 D4 D3 D2 D1 D0 VCLK VCO Powerdown MCLK VCO Powerdown Oscillator Powerdown Reserved(R/W) Video Clock Select CLK Reg Program Pointer Power Sequencing Clock Clock Mode Control 0 0 VCLK VCO selected 1 MCLK VCO selected 6 VCLK VCO Powerdown 1 Use AA9 pin as 32 KHz clock input for panel power sequencing reference clock and Standby Mode display memory refreshes. Asymmetric DRAM option (XR05[3]=1) should not be enabled in this case. This bit is only effective if XR01[4] = 1. MCLK VCO Powerdown 0 MCLK VCO Enabled (default) 1 MCLK VCO Disabled 7 This bit is only effective if XR01[4] = 1. 2 Power Sequencing Reference Clock 0 Use RCLK (reference clock) divided by 384 as panel power sequencing reference clock and Standby Mode display memory refreshes. For RCLK=14.31818 MHz, panel power sequencing clock would be 37.5 KHz (default). 0 VCLK VCO Enabled (default) 1 VCLK VCO Disabled 1 Clock Register Program Pointer Clock Mode Control 0 Clock 0 and Clock 1 default to 25.175 and 28.322 MHz respectively. Oscillator Powerdown 1 Clock 0 and Clock 1 default to 31.5 MHz and 35.5 MHz. 0 OSC Enabled (default) 1 OSC Disabled This bit is only effective if XR01[5] = 1 and XR33[6] = 1. 3 Reserved (R/W) 4 Video Clock Select 0 If XR01[4] = 1 (internal clock source), use output of VCLK VCO as video clock otherwise if XR04[4] = 0, use RCLK input as video clock (default). 1 If XR01[4] = 1 (internal clock source), use output of MCLK VCO divided by 2 as the video clock; otherwise if XR01[4]=0, then use MCLK input divided by 2 as the video clock. Revision 1.2 123 65540 / 545 (R) Extension Registers COLOR KEY REGISTER 0 (XR3A) Read/Write at I/O Address 3D7h Index 3Ah COLOR KEY REGISTER 1 (XR3B) Read/Write at I/O Address 3D7h Index 3Bh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Color Compare Data 0 7-0 Color Compare Data 1 Color Compare Data 0 7-0 These bits are compared to the least significant 8 bits of the background video stream. If a match occurs on all enabled bits (see Color Compare Mask Register XR3D) and the key is enabled (XR06[4]), external video is sent to the screen. External video is input on the MCD15:0, CASCH# and CASCL# pins (and CA8-9, ACTI, ENABKL, AA9, and OEC# if 24-bit external video input is enabled (XR05[7]=1)). The logical masking and compare operations are described in the functional description. The color comparison occurs before the RAMDAC. In 4BPP and 8BPP modes using palette LUT data, the LUT index is used in the comparison, not the 18BPP LUT data. Revision 1.2 Color Compare Data 1 These bits are compared to bits 15:8 of the background video stream. If a match occurs on all enabled bits (see Color Compare Mask Register XR3D) and the key is enabled (XR06[4]), external video is sent to the screen. External video is input on the MCD15:0, CASCH# and CASCL# pins (and CA8-9, ACTI, ENABKL, AA9, and OEC# if 24-bit external video input is enabled (XR05[7]=1)). The logical masking and compare operations are described in the functional description. This register should be masked from participating in the comparison in 4BPP and 8BPP modes. This is accomplished by setting Color Mask Register 1 (XR3E) = 0FFh. 124 65540 / 545 (R) Extension Registers COLOR KEY REGISTER 2 (XR3C) Read/Write at I/O Address 3D7h Index 3Ch COLOR KEY MASK REGISTER 0 (XR3D) Read/Write at I/O Address 3D7h Index 3Dh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Color Compare Data 2 7-0 Color Compare Mask 0 Color Compare Data 2 7-0 These bits are compared to bits 23:16 of the background video stream. If a match occurs on all enabled bits (see Color Compare Mask Register XR3D) and the key is enabled (XR06[4]), external video is sent to the screen. External video is input on the MCD15:0, CASCH# and CASCL# pins (and CA8-9, ACTI, ENABKL, AA9, and OEC# if 24-bit external video input is enabled (XR05[7]=1)). The logical masking and compare operations are described in the functional description. This register should be masked from participating in the comparison in 4BPP, 8BPP and 16BPP modes. It should only be used in 24BPP modes. This is accomplished by setting Color Mask Register 2 (XR3F) = 0FFh. Revision 1.2 Color Compare Mask 0 This register is used to select which bits of the background video data stream are used in the comparison with the Color Compare Data 23:0. This register controls bits 7:0. 0 Data does participate in compare operation 1 Data does not participate in compare operation (masked) 125 65540 / 545 (R) Extension Registers COLOR KEY MASK REGISTER 1 (XR3E) Read/Write at I/O Address 3D7h Index 3Eh COLOR KEY MASK REGISTER 2 (XR3F) Read/Write at I/O Address 3D7h Index 3Fh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Color Compare Mask 1 7-0 Color Compare Mask 2 Color Compare Mask 1 7-0 This register is used to select which bits of the background video data stream are used in the comparison with the Color Compare Data 23:0. This register controls bits 7:0. 0 Data does participate in compare operation 1 Data does not participate in compare operation (masked) Revision 1.2 Color Compare Mask 2 This register is used to select which bits of the background video data stream are used in the comparison with the Color Compare Data 23:0. This register controls bits 7:0. 0 Data does participate in compare operation 1 Data does not participate in compare operation (masked) 126 65540 / 545 (R) Extension Registers BitBLTCONFIGREGISTER(XR40) (65545 Only) Read/Write at I/O Address 3D7h Index 40h 3-0 D7 D6 D5 D4 D3 D2 D1 D0 BitBLT Draw Mode Reserved(0) 4 7-5 1-0 BitBLT Draw Mode ( 65545 only ) Optimal Compensation Enable 0 Disable optimal compensation 1 Enable optimal compensation Reserved ( 0 ) See also XR0F, XR2B, XR45 for definition of other software flags registers. The 65545 supports two color depths in its drawing engine: 00 Reserved 01 8BPP 10 16BPP 11 Reserved SOFTWARE FLAGS REGISTER 3 (XR45) Read/Write at I/O Address 3D7h Index 45h Note: 24BPP is handled in 8BPP mode. There is no nibble mode access for 4BPP modes. 7-2 Set Panel Type ( 40K BIOS Only ) 00 Panel #1 01 Panel #2 02 Panel #3 03 Panel #4 04 Panel #5 05 Panel #6 06 Panel #7 07 Panel #8 08-0F Reserved D7 D6 D5 D4 D3 D2 D1 D0 Flag 0 Reserved ( 0 ) Flag 1 Flag 2 Flag 3 SOFTWARE FLAGS REGISTER 2 (XR44) Read/Write at I/O Address 3D7h Index 44h Flag 4 Flag 5 Flag 6 Flag 7 D7 D6 D5 D4 D3 D2 D1 D0 This register contains eight read-write bits which have no internal hardware function. All bits are reserved for use by BIOS and driver software. For reference, the functions of the bits of this register are currently defined as follows: Set Panel Type Optimal Compensation Ena 7-0 Flags ( Reserved ) See also XR0F, XR2B, XR44 for definition of other software flags registers. Reserved(0) This register contains eight read-write bits which have no internal hardware function. All bits are reserved for use by BIOS and driver software. For reference, the functions of the bits of this register are currently defined as follows: Revision 1.2 127 65540 / 545 (R) Extension Registers PANEL FORMAT REGISTER 2 (XR4F) Read/Write at I/O Address 3D7h Index 4Fh D7 D6 D5 D4 D3 D2 D1 D0 001 010 011 100 Bits Per Pixel The setting programmed into this field determines how many most-significant color-bits / pixel are used to generate flat panel video data. In general, 8 bits of monochrome data or 8 bits/color of RGB color data enter the flat panel logic for every dot clock. Not all of these bits, however, are used to generate output colors / gray scales, depending on the type of panel used, graphics / text mode, and the gray-scaling algorithm chosen (the actual number of bits used is indicated in the table above). If the VGA palette is used then a maximum of 6 bits/pixel (bits 7-2) (setting '110') should be used. If the VGA palette is bypassed then a maximum of 8 bits/pixel (bits 7-0) (setting '111) may be used. With 2-frame and 16-frame FRC, settings not listed in the tables above are undefined. Also note that settings which achieve higher gray / color levels may not necessarily produce acceptable display quality on some (or any) currently available panels. This document contains recommended settings for various popular panels that Chips & Technologies has found to produce acceptable results with those panels. Customers may modify these settings to achieve a better match with their requirements. Reserved(R/W) M Functionality Select LP Functionality Select This register is used only in flat panel mode. 2-0 Bits Per Pixel Selection The value in this field, along with the dither and FRC settings, determines gray / color levels produced: No FRC # of msbs Gray / Gray / Used Color Color to Generate Levels Levels Gray / Color without with Levels Dithering Dithering 001 1 2 5 010 2 4 13 011 3 8 29 100 4 16 61 101 5 32 125 110 6 64 253 111 8 256 n/a 010 011 100 101 Revision 1.2 16-Frame FRC (Color or Monochrome STN Panels) # of msbs Gray / Gray / Used Color Color to Generate Levels Levels Gray / Color without with Levels Dithering Dithering 1 2 5 2 4 13 3 8 29 4 16 61 2-Frame FRC (Color TFT or Monochrome Panels) # of msbs Gray / Gray / Used Color Color to Generate Levels Levels Gray / Color without with Levels Dithering Dithering 1 3 9 2 5 25 3 15 57 4 31 121 3-5 128 Reserved (R/W) 6 M Pin Select 0 M signal goes to the M pin (default on reset) 1 FP Display Enable (FP Blank#) signal goes to the M pin. Polarity is controlled by XR54[0]. 7 LP Pin Select 0 FP HSync (LP) signal goes to the LP pin. Polarity is controlled by XR54[6] (default on reset). 1 FP Display Enable (FP Blank#) signal goes to the LP pin. Polarity is controlled by XR54[0]. 65540 / 545 (R) Extension Registers PANEL FORMAT REGISTER 1 (XR50) Read/Write at I/O Address 3D7h Index 50h 6-4 Clock Divide ( CD ) These bits specify the frequency ratio between the dot clock and the flat panel shift clock (SHFCLK) signal. 000 Shift Clock Freq = Dot Clock Freq. This setting is used to output 1 pixel per shift clock with a maximum of 8 bpp (bits/pixel) for single drive monochrome panels. For double drive color panels, this setting is used to output 2 2/3 4-bit pack pixels. FRC and dithering may be enabled. 001 Shift Clk Freq = 1/2 Dot Clock Freq. This setting is used to output 2 pixels per shift clock with a maximum of 8 bits/pixel for single drive monochrome panels and 4 bpp for single drive color panels. For double drive color panels, this setting is used to output 5-1/3 4bit pack pixels. FRC and dithering can be enabled. 010 Shift Clk Freq = 1/4 Dot Clock Freq. This setting is used to output 4 pixels per shift clock with a maximum of 4 bpp for single drive mono panels and 2 bits/pixel for single drive color panels. For single drive color panels this setting is used to output 5-1/3 4bit pack pixels. For double drive monochrome panels, this setting is used to output 8 pixels per shift clock with 1 bit/pixel. FRC and dithering can be enabled. 011 Shift Clk Freq = 1/8 Dot Clock Freq. This setting is used to output 8 pixels per shift clock with a maximum of 2 bpp for single drive mono panels and 1 bit/pixel for single drive color panels. For double drive mono panels, this setting is also used to output 16 pixels per shift clock with 1 bit/pixel. FRC and dithering can be enabled. 100 Shift Clk Freq = 1/16 Dot Clock Freq. This setting is used to output 16 pixels per shift clock with maximum of 1 bit/pixel for single drive monochrome panels. Dithering can also be enabled. 7 TFT Panel Data Width This bit is effective only when TFT (active matrix) panels are used (XR50 bits 1-0=10). 0 16-bit color TFT interface (565 RGB) 1 24-bit color TFT interface (888 RGB) D7 D6 D5 D4 D3 D2 D1 D0 Frame Rate Control Dither Enable Clock Divide TFT Panel Data Width This register is used only in flat panel mode. 1-0 3-2 Frame Rate Control ( FRC ) FRC is gray scale simulation on a frame-byframe basis to generate shades of gray or color on panels that do not support generation of gray / color levels internally. 00 No FRC. This setting may be used with all panels, especially for panels which can generate shades of gray / color internally. 01 16-frame FRC. This setting may be used for Color STN or Monochrome panels. One to four bits/pixel output to the panel are possible and therefore this setting is used only with panels which do not support internal gray scaling. This setting is used to simulate 16 gray / color levels per pixel. The bits per pixel are specified by XR4F[2-0]; valid values are 001, 010, 011, and 100. 10 2-frame FRC. This setting may be used for Color TFT or Monochrome panels. One to four bits/pixel output to the panel are possible and therefore this setting can also be used with panels that support internal gray scaling. Number of input bits used (specified in XR4F[2-0]) are one more than the number of output bits. Therefore, valid values for XR4F[2-0] are 010, 011, 100, and 101. 11 Reserved Dither Enable 00 Disabledithering 01 Enable dithering for 256-color modes (AR10 bit-6 = 1 or XR28 bit 4 = 1) 10 Enable dithering for all modes 11 Reserved Revision 1.2 129 65540 / 545 (R) Extension Registers DISPLAY TYPE REGISTER (XR51) Read/Write at I/O Address 3D7h Index 51h 5 Shift Clock Mask (SM) This bit is effective for flat panel only. 0 D7 D6 D5 D4 D3 D2 D1 D0 1 Panel Type 6 Display Type Shift Clock Divide Reserved(R/W) Shift Clock Mask Enable FP Compensation LP During V Blank 1-0 0 1 7 These bits are effective for flat panel only. 2 LP During Vertical Blank 0 This bit is effective for CRT and flat panel. This bit also controls the BLANK# output. 1 Disable FP compensation Enable FP compensation This bit should be set only for SS panels which require FP HSync (LP) to be active during vertical blank time when XR54 bit-1 = 0 (e.g., Plasma / EL panels). This bit should be reset when using non-SS panels or when XR54 bit-1 = 1. Single Panel Single Drive (SS) Reserved Reserved Dual Panel Double Drive (DD) Display Type (DT) 0 Enable FP Compensation (EFCP) This bit is effective for flat panel only. It enables flat panel horizontal and vertical compensation depending on panel size, current display mode, and contents of the compensation registers. Panel Type (PT) 00 01 10 11 Allow shift clock output to toggle outside the display enable interval Force the shift clock output low outside the display enable interval 1 CRT display (default on reset) BLANK# outputs CRT Blank FP (Flat Panel) display BLANK# outputs FP Blank FP HSync (LP) is generated from internal FP Blank inactive edge FP HSync (LP) is generated from internal FP Horizontal Blank inactive edge Note: There is no pin dedicated to output of BLANK#. Therefore this bit is ignored if BLANK# is not selected to be output on either the M or LP output pins. 3 Shift Clock Divide This bit is effective for flat panel only. 0 1 4 Shift Clock to Dot Clock relationship expressed by XR50[6-4]. In this mode, the Shift Clock is further divided by 2 and different video data is valid on the rising and falling edges of Shift Clock. Reserved (R/W) Revision 1.2 130 65540 / 545 (R) Extension Registers POWER DOWN CONTROL REGISTER (XR52) Read/Write at I/O Address 3D7h Index 52h 5 This bit is effective in Flat Panel Mode during Standby and Panel Off modes (XR52[3] = 1 or (XR52[4] = 1 or STNDBY#, pin 178 is active (low)). D7 D6 D5 D4 D3 D2 D1 D0 0 Video data and/or flat panel control signals are driven inactive (default on reset). 1 Video data and flat panel control signals pins are tri-stated with a weak internal pull-down. Normal Refresh Count Panel Off Mode Software Standby Mode Standby/Panel Off Control Standby Refresh Control CRT Mode Control 2-0 Note: XR61 bit-7 controls the inactive level for video data in text mode; XR63 bit-7 controls the inactive level for video data in graphics mode: FP Normal Refresh Count 0 = low when inactive 1 = high when inactive These bits specify the number of memory refresh cycles to be performed per scanline. A minimum value of 1 should be programmed in this register. 3 Note: This bit does not affect the HSYNC and VSYNC pins. In Standby and Panel Off modes, HSYNC and VSYNC will be driven low. Panel Off Mode This bit provides a software alternative to enter Panel Off mode. Note that Panel Off mode will be effective in both CRT and flat panel modes of operation. 0 1 6 Normal mode (default on reset) Panel Off mode Software Standby Mode 0 Self-Refresh DRAM support. 1 Display memory refresh frequency is derived from the 32KHz input or RCLK (14.31818MHz Reference Clock) divided per the value in XR5F. This bit provides an alternative way to enter the Standby mode. When this bit is set, the chip enters Standby mode. To exit Standby mode, when this bit is set, the STNDBY# pin must be asserted and then reasserted. This bit will also be reset when the STNDBY# pin goes active (low). 0 1 Standby Refresh Control This bit is effective only in Standby mode (STNDBY# pin low). Standby mode is effective for both CRT and flat panel modes. In Standby mode, CPU interface to display memory and internal registers is inactive. The CRT / FP display memory interface, video data and timing signals, and internal RAMDAC are inactive (all CRT and flat panel video control and data pins are 3stated). Display memory refresh is controlled by this bit. In Panel Off mode, the CRT / FP display memory interface is inactive but CPU interface and display memory refresh are still active. The internal RAMDAC is also inactive. 4 Standby and Panel Off Control 7 CRT Mode Control This bit is effective in CRT mode only (nonsimultaneous CRT and flat panel) (XR51 bit-2 = 0). Normal Mode (default on reset) Standby Mode 0 Video data and flat panel control signals are 3-stated with weak internal pull-down (default on reset). 1 Video data and flat panel control signals are inactive. Revision 1.2 131 65540 / 545 (R) Extension Registers PANEL FORMAT REGISTER 3 (XR53) Read/Write at I/O Address 3D7h Index 53h 6 FRC Option 3 This bit affects 2-frame FRC only 0 1 D7 D6 D5 D4 D3 D2 D1 D0 7 Disable AR10 bit-2 Alt Line Gr Char Code Ctrl FRC Option 1 FRC Option 2 FRC data changes every frame FRC data changes every other frame Reserved (R/W) Color STN Pixel Packing FRC Option 3 Reserved(R/W) 0 Disable AR10 Bit-2 0 1 1 Use AR10 bit-2 for Line Graphics control (default on Reset). Use XR53 bit-1 instead of AR10 bit-2 for Line Graphics control AlternateLineGraphicsCharacterControl This bit is effective only if bit-0 = 1. 0 1 Ninth pixel of line graphics character is set to the background color Ninth pixel of line graphics character is identical to the eighth pixel 2 FRC Option 1 (always program to 1) 3 FRC Option 2 (always program to 1) 5-4 Color STN Pixel Packing This field determines the type of pixel packing (the RGB pixel output sequence) for color STN panels. These bits should be programmed only when color STN panels are used. These bits must be programmed to 00 for monochrome panels or color TFT panels. 00 3-bit Pack. XR50 bits 6-4 can be 000, 001, or 010. 01 4-bit Pack. For SS Color STN panels, XR50 bits 6-4 can be 000, 001, or 010. For DD panels, XR50 bits 6-4 may be set to 000 or 001. 10 Reserved 11 Extended 4-bit Pack. XR50 bits 6-4 must be programmed to 001. This setting may be used for 8-bit interface Color STN SS panels only. Revision 1.2 132 65540 / 545 (R) Extension Registers PANEL INTERFACE REGISTER (XR54) Read/Write at I/O Address 3D7h Index 54h 3-2 Select flat panel dot clock source. These bits are used instead of Miscellaneous Output Register (MSR) bits 3-2 in flat panel mode. See description of MSR bits 3-2. D7 D6 D5 D4 D3 D2 D1 D0 FP Blank Polarity FP Blank Select 5-4 FP Feature Control FP LP Polarity FP FLM Polarity 6 0 1 FP Blank Polarity 7 This bit controls the polarity of the BLANK# pin in flat panel mode. In CRT mode, XR28 bit-0 controls polarity of the BLANK# pin. 1 FP HSync (LP) Polarity This bit controls the polarity of the flat panel HSync (LP) pin. This register is used only in flat panel modes. 0 1 FP Feature Control Bits 1-0 Select flat panel dot clock source. These bits are used instead of Feature Control Register (FCR) bits 1-0 in flat panel mode. See description of FCR bits 1-0. FP Clock Select 0 FP Clock Select Bits 1-0 Positive polarity Negative polarity FP VSync (FLM) Polarity This bit controls the polarity of the flat panel VSync (FLM) pin. 0 1 Positive polarity Negative polarity Positive polarity Negative polarity FP Blank Select This bit controls the BLANK# pin output in flat panel mode. In CRT mode, XR28 bit-1 controls the BLANK# output. This bit also affects operation of the flat panel video logic, generation of the FP HSync (LP) pulse signals, and masking of the Shift Clock. 0 1 The BLANK# pin outputs both FP Vertical and Horizontal Blank. In 480-line DD panels, this option will generate exactly 240 FP HSync (LP) pulses. The BLANK# pin outputs only FP Horizontal Blank. During FP Vertical Blank, the flat panel video logic will be active, the FP HSync (LP) pulse will be generated, and Shift Clock can not be masked. Note however that Shift Clock can still be masked during FP Horizontal Blank. Note: The signal polarity selected by bit-0 is applicable for either selection. Revision 1.2 133 65540 / 545 (R) Extension Registers HORIZONTAL COMPENSATION REGISTER (XR55) Read/Write at I/O Address 3D7h Index 55h 4-3 5 Reserved (R/W) Enable Automatic Horizontal Doubling (EAHD)(this bit is effective if bit-0 is 1) 0 D7 D6 D5 D4 D3 D2 D1 D0 Ena H Compensation Ena H Auto Centering Ena H Compression 1 Reserved(R/W) Ena Auto H Doubling Alternate HSync Polarity Alternate VSync Polarity This register is used only in flat panel modes when flat panel compensation is enabled (XR51 bit-6 = 1). 0 0 1 1 1 Alternate CRT HSync Polarity 0 1 Disable horizontal compensation Enable horizontal compensation 7 Enable Automatic Horizontal Centering (EAHC) (effective only if bit-0 is 1) 0 2 6 EnableHorizontalCompensation(EHCP) Positive Negative Alternate CRT VSync Polarity 0 1 Enable non-automatic horizontal centering. The Horizontal Centering Register is used to specify the left border. If no centering is desired then the Horizontal Centering Register can be programmed to 0. Enable automatic horizontal centering. Horizontal left and right borders will be computed automatically. Disable Automatic Horizontal Doubling. Horizontal doubling will only be performed for flat panels when SR01 bit-3 = 1 in any emulation mode or when 3B8/3D8 bit-0 & 3B8/3D8 bit-4 = 0 in CGA emulation. Enable Automatic Horizontal Doubling. Horizontal doubling will be performed for flat panels when SR01 bit-3 = 1 in any emulation mode or when 3B8/3D8 bit-0 & 3B8/3D8 bit-4 = 0 in CGA emulation or when the Horizontal Display width (CR01) is equal to or less than half of the Horizontal Panel Size (XR18). Positive Negative Note: bits 6 and 7 above are used in flat panel mode (XR51 bit-2 = 1) instead of MSR bits 6 and 7). This is primarily used for simultaneous CRT / Flat Panel display. EnableTextModeHorizontalCompression (ETHC)(this bit is effective only if bit-0 is 1 in flat panel text mode). Setting this bit will turn on text mode horizontal compression regardless of horizontal display width or horizontal panel size. 0 1 Text mode horizontal compression off Text mode horizontal compression on. 8-dot text mode is forced when 9-dot text mode is specified (SR01 bit-0 = 0 or Hercules text). Note: This bit affects the horizontal pixel panning logic. When text mode horizontal compression is active, programming 9-bit panning will result in 8-bit panning. Revision 1.2 134 65540 / 545 (R) Extension Registers HORIZONTALCENTERINGREGISTER(XR56) Read/Write at I/O Address 3D7h Index 56h D7 D6 D5 D4 D3 D2 D1 D0 LeftBorder This register is used only in flat panel modes when non-automatic horizontal centering is enabled. 7-0 Horizontal Left Border (HLB) Programmed Value (in character clocks) = Width of Left Border - 1 Revision 1.2 135 65540 / 545 (R) Extension Registers VERTICALCOMPENSATIONREGISTER(XR57) Read/Write at I/O Address 3D7h Index 57h 4-3 These bits are effective if bits 2 and 0 are 1. 00 Double Scanning (DS) and Line Insertion (LI) with the following priority: DS+LI, DS, LI. 01 Double Scanning (DS) and Line Insertion (LI) with the following priority: DS+LI, LI, DS. 10 Double Scanning (DS) and TallFont (TF) with the following priority: DS+TF, DS, TF. 11 Double Scanning (DS) and TallFont (TF) with the following priority: DS+TF, TF, DS. D7 D6 D5 D4 D3 D2 D1 D0 Enable V Compensation Enable Auto V Centering Enable Text V Stretching Text V Stretch Method Enable Gr V Stretching Gr V Stretch Method Disable Fast Centering 5 This register is used only in flat panel modes when flat panel compensation is enabled. 0 1 0 1 6 This bit is effective only if bit-0 is 1. 2 Disable vertical stretching Enable vertical stretching Vertical Stretching (VS) Vertical Stretching can be enabled in both text and graphics modes. This bit is effective only if bits 5 and 0 are 1. Enable Automatic Vertical Centering (EAVC) 1 Enable Vertical Stretching (EVS) This bit is effective only if bit-0 is 1. Enable Vertical Compensation (EVCP) 0 Disableverticalcompensation 1 Enable vertical compensation 0 Text Mode Vertical Stretching (TVS1-0) 0 Enable non-automatic vertical centering. The Vertical Centering Register is used to specify the top border. If no centering is desired then the Vertical Centering Register can be programmed to 0. Enable automatic vertical centering. Vertical top and bottom borders will be computed automatically. 1 7 Double Scanning (DS) and Line Replication (LR) with the following priority: DS+LR, DS, LR. Double Scanning (DS) and Line Replication (LR) with the following priority: DS+LR, LR, DS. Disable Fast Centering This bit is effective only if XR58[1-0] = 11. 0 1 Enable Text Mode Vertical Stretching (ETVS) Enable Fast Centering Disable Fast Centering This bit is effective only if bit-0 is 1. 0 1 Revision 1.2 Disable text mode vertical stretching; graphics mode vertical stretching is used if enabled. Enable text mode vertical stretching 136 65540 / 545 (R) Extension Registers VERTICAL CENTERING REGISTER (XR58) Read/Write at I/O Address 3D7h Index 58h VERTICALLINEINSERTIONREGISTER(XR59) Read/Write at I/O Address 3D7h Index 59h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 V Line Insertion Height Top Border LSBs Reserved(0) Top Border Bits 8-9 Hardware Line Replication This register is used only in flat panel modes when non-automatic vertical centering is enabled. 7-0 This register is used only in flat panel text mode when vertical line insertion is enabled. Vertical Top Border LSBs (VTB7-0) 3-0 Programmed value: Vertical Line Insertion Height (VLIH3-0) ProgrammedValue: Top Border Height (in scan lines) - 1 Number of Insertion Lines - 1 This register contains the eight least significant bits of the programmed value of the Vertical Top Border (VTB). The two most significant bits are in the Vertical Line Insertion Register (XR59). The value programmed in this register - 1 is the number of lines to be inserted between the rows. Insertion lines are never double scanned even if double scanning is enabled. Insertion lines use the background color. 4 6-5 Reserved (0) Vertical Top Border MSBs (VTB9-8) This register contains the two most significant bits of the programmed value of the Vertical Top Border (VTB). The eight least significant bits are in the Vertical Centering Register (XR58). 7 Hardware Line Replication This bit is effective in text mode when Line Replication is selected (XR57[2] = 1). Hardware line replication, when enabled, replicates lines to display a 19-line character from a 16-line font as specified in XR28 bit7. 0 1 Revision 1.2 137 Normal text mode line replication Hardware line replication is enabled 65540 / 545 (R) Extension Registers VERTICAL LINE REPLICATION REGISTER (XR5A) Read/Write at I/O Address 3D7h Index 5Ah PANEL POWER SEQUENCING DELAY REGISTER (XR5B) Read/Write at I/O Address 3D7h Index 5Bh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Line Replication Height Delay on Power Down Reserved(R/W) Delay on Power Up This register is used only in flat panel text or graphics modes when vertical line replication is enabled. 3-0 This register is used only in flat panel modes. The generation of the clock for panel power sequencing logic is controlled by XR33[6]. The delay intervals below assume a 37.5 KHz clock generated by the internal clock synthesizer. If the 32KHz input is used, the delay intervals should be scaled accordingly. Vertical Line Replication Height (VLRH) Programmed Value = Number of Lines Between Replicated Lines - 1 3-0 Double scanned lines are also counted. Programmable value of panel powersequencing during power down. This value can be programmed up to 459 milliseconds in increments of 29 milliseconds. A value of 0 is undefined. In other words, if this field is programmed with '7', every 8th line will be replicated. 7-4 Power Down Delay Reserved (R/W) 7-4 Power Up Delay Programmable value of panel power sequencing during power up. This value can be programmed up to 54 milliseconds in increments of 3.4 milliseconds. A value of 0 is undefined. Revision 1.2 138 65540 / 545 (R) Extension Registers ACTIVITYTIMERCONTROLREGISTER(XR5C) Read/Write at I/O Address 3D7h Index 5Ch D7 D6 D5 D4 D3 D2 D1 D0 Activity Timer Count Reserved(R/W) Activity Timer Action Enable Activity Timer This register is used to control Activity timer functionality. The activity timer is an internal counter that starts counting from a value programmed into this register (see bits 0-4 below) and is reset back to that count by read or write accesses to graphics memory or I/O. If no accesses occur, the counter counts till the end of its programmed interval and activates either the ENABKL pin or Panel Off mode (as selected by bit6 below). The timer count does not have to be reloaded once programmed and the timer enabled: any access to the chip with the timer timed out (ENABKL active or Panel Off mode active) will reset the timer and the ENABKL pin de-activated (or Panel Off mode exited, whichever is selected). The activity timer uses the same clock as power sequencing which is controlled by XR33[6]. The delay intervals below assume a 35.7 KHz clock, if an external 32KHz input is used, the delay is scaled accordingly. 4-0 6 Activity Timer Action 0 When the activity timer count is reached, the ENABKL pin is activated (driven low to turn the backlight off) 1 When the activity timer count is reached, Panel Off mode is entered. 7 Enable Activity Timer 0 Disable activity timer (default on reset) 1 Enable activity timer See also XR5D bit-2. Activity Timer Count For a 35.7 KHz clock the counter granularity is approximately 25.6 seconds. The minimum programmed value of 1 results in 25.6 second delay and the maximum count of 32 results in a delay of 13.7 minutes. If the clock input on pin 154 (AA9) is other than 32 KHz, the delay should be scaled accordingly. 5 Reserved (R/W) Revision 1.2 139 65540 / 545 (R) Extension Registers FP DIAGNOSTIC REGISTER (XR5D) Read/Write at I/O Address 3D7h Index 5Dh 5 18-bit Color TFT Test Mode 0 1 D7 D6 D5 D4 D3 D2 D1 D0 6 Enable Palette Powerdown Enable Access in PNLOFF Enable Activity Timer Test Force 16-bit Local Bus Disable Vertical Comp 18-bit Color Test Mode HSync/VSync Deactivation Enable Palette Powerdown 0 1 1 1 Allow HSYNC and VSYNC to be deactivated when XR06[1] = 1 (default on reset) Prevents HSYNC and VSYNC from being deactivated when XR06[1] = 1. EnablePalettePowerdowninBypassMode 0 1 Enable Panel-Off VGAPalettePowerdown 0 Prevent HSYNC and VSYNC Deactivation 0 7 Disable 18-bit color TFT test mode (default on reset) Enable 18-bit color TFT test mode Disable VGA palette powerdown when XR06[5]=1 Enable VGA palette powerdown when XR06[5]=1 and XR06[1]=1 Disable VGA Palette powerdown in Panel Off Mode (default on reset) Enable VGA Palette powerdown in Panel Off mode Enable Panel-Off VGA Palette Access This bit is effective when bit 0=1 or bit 7=1. 0 1 2 Enable Activity Timer Test 0 1 3 Disable CPU access to VGA Palette in Panel Off Mode (default on reset) Enable CPU access to VGA Palette in Panel Off Mode Disable Activity Timer test mode (default on reset) Enable Activity Timer test mode Force 16-Bit Local Bus This bit is effective when 32-bit local bus and 16-bit memory interface are used during font load. 0 1 4 Do not force 16-bit local bus when loading font (default on reset) Force 16-bit local bus when loading font Disable Vertical Compensation 0 1 Revision 1.2 Vertical compensation can be enabled in all cases (default on reset) Disable vertical compensation if Vertical Display Enable End equals Vertical Panel Size. 140 65540 / 545 (R) Extension Registers M (ACDCLK) CONTROL REGISTER (XR5E) Read/Write at I/O Address 3D7h Index 5Eh POWER DOWN REFRESH REGISTER (XR5F) Read/Write at I/O Address 3D7h Index 5Fh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 M (ACDCLK) Count Power Down Refresh Freq M (ACDCLK) Control 7-0 This register is used only in flat panel mode. 6-0 These bits define the frequency of memory refresh cycles in power down (standby) mode (STNDBY# pin low). CAS-BeforeRAS (CBR) refresh cycles are performed. M ( ACDCLK ) Count ( ACDCNT ) These bits define the number of HSyncs between adjacent phase changes on the M (ACDCLK) output. These bits are effective only when bit 7 = 0 and the contents of this register are greater than 2. If XR52 bit-6 = 1, the interval between two refresh cycles is determined by bits 0-3 of this register per the table below. Bits 4-7 of this register are reserved for future use in this mode (and should be programmed to 0). Programmed Value = Actual Value - 2 7 Power Down Refresh Frequency M ( ACDCLK ) Control 0 1 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 The M (ACDCLK) phase changes depending on bits 0-6 of this register The M (ACDCLK) phase changes every frame if the frame accelerator is not used. If the frame accelerator is used, the M (ACDCLK) phase changes every other frame. If XR4F bit-6 is programmed to one to enable flat panel DE / BLANK# to be output on the M (ACDCLK) pin, the contents of this register will be ignored. Approximate Refresh Interval 16 usec / cycle 47 usec / cycle 63 usec / cycle 78 usec / cycle 94 usec / cycle 109 usec / cycle 125 usec / cycle 141 usec / cycle 156 usec / cycle These refresh intervals assume a 32 KHz clock. If the internal clock is used, the refresh interval is scaled accordingly. If XR52 bit-6 = 0, a value of 0 causes no refresh to be performed. Self-Refresh DRAMs should be used in this case. Revision 1.2 141 65540 / 545 (R) Extension Registers BLINK RATE CONTROL REGISTER (XR60) Read/Write at I/O Address 3D7h Index 60h D7 D6 D5 D4 D3 D2 D1 D0 Cursor Blink Rate Char Blink Duty Cycle This register is used in all modes. 5-0 Cursor Blink Rate These bits specify the cursor blink period in terms of number of VSyncs (50% duty cycle). In text mode, the character blink period and duty cycle is controlled by bits 76 of this register. These bits default to 000011 (decimal 3) on reset which corresponds to eight VSyncs per cursor blink period per the following formula (four VSyncs on and four VSyncs off): Programmed Value = (Actual Value) / 2 - 1 Note: In graphics mode, the pixel blink period is fixed at 32 VSyncs per cursor blink period with 50% duty cycle (16 on and 16 off). 7-6 Character Blink Duty Cycle These bits specify the character blink (also called 'attribute blink') duty cycle in text mode. 7 0 0 1 1 6 0 1 0 1 Character Blink Duty Cycle 50% 25% 50% (default on Reset) 75% For setting 00, the character blink period is equal to the cursor blink period. For all other settings, the character blink period is twice the cursor blink period (character blink is twice as slow as cursor blink). Revision 1.2 142 65540 / 545 (R) Extension Registers SMARTMAPTM CONTROL REGISTER (XR61) Read/Write at I/O Address 3D7h Index 61h 4-1 These bits are used only in flat panel text mode when SmartMapTM is enabled (bit-0 = 1). They define the minimum difference between the foreground and background colors. If the difference is less than this threshold, the colors are separated by adding and subtracting the shift values (XR62) to the foreground and background colors. However, if the foreground and background color values are the same, then the color values are not adjusted. D7 D6 D5 D4 D3 D2 D1 D0 SmartMapTM Enable SmartMapTM Threshold SmartMapTM Saturation Text Enhancement Text Video Output Polarity 5 SmartMapTM Enable 0 1 Disable SmartMapTM, use color lookup table and use internal RAMDAC palette if enabled (XR06 bit-2 = 1). Enable SmartMapTM, bypass both color lookup table and internal RAMDAC palette in flat panel text mode. Although color lookup table is bypassed, translation of 4 bits/pixel data to 6 bits/pixel data is still performed depending on AR10 bit-1 (monochrome / color display) as follows: Output Out0 Out1 Out2 Out3 Out4 Out5 6 0 The color result is clamped to the maximum and minimum values (0Fh and 00h respectively) 1 The color result is computed modulo 16 (no clamping) Text Enhancement This bit is used only in flat panel text mode. 0 1 Normal text Text attribute 07h and 0Fh are reversed to maximize the brightness of the normal DOS prompt Note: This bit should be set to 0 if XR63[6] is set to 1. Conversely, if this bit is set to 1, XR63[6] should be set to 0. AR10 bit-1 = 0 AR10 bit-1 = 1 In0 In0 In1 In1 In2 In2 In3 In0+In1+In2+In3 In3 In3 In3 In3 7 Text Video Output Polarity (TVP) This bit is effective for flat panel text mode only. 0 1 Note: This bit does not affect CRT text / graphics mode or flat panel graphics mode; i.e.: the color lookup table is always used, and similarly the internal RAMDAC palette is used if enabled. Revision 1.2 SmartMapTM Saturation This bit is used only in flat panel text mode when SmartMapTM is enabled (bit-0 = 1). It selects the clamping level after the color addition/subtraction. This register is used in flat panel text mode only. 0 SmartMapTM Threshold Normal polarity Inverted polarity Note: Graphics video output polarity is controlled by XR63 bit-7 (GVP). 143 65540 / 545 (R) Extension Registers SMARTMAPTM SHIFT PARAMETER REGISTER (XR62) Read/Write at I/O Address 3D7h Index 62h SMARTMAPTMCOLORMAPPINGCONTROL REGISTER(XR63) Read/Write at I/O Address 3D7h Index 63h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Foreground Shift Color Threshold Background Shift New Text Enhancement Gr Video Output Polarity This register is used in flat panel text mode when SmartMapTM is enabled (XR61 bit-0 = 1). 3-0 5-0 These bits are effective for monochrome (XR51 bit-5 = 1) single/double drive flat panel with 1 bit/pixel (XR50 bits 4-5 = 11) without FRC (XR50 bits 0-1 = 11). They specify the color threshold used to reduce 6bit video to 1-bit video color. Color values equal to or greater than the threshold are mapped to 1 and color values less than the threshold are mapped to 0. Foreground Shift These bits define the number of levels that the foreground color is shifted when the foreground and background colors are closer than the SmartMapTM Threshold (XR61 bits 1-4). If the foreground color is "greater" than the background color, then this field is added to the foreground color. If the foreground color is "smaller" than the background color, then this field is subtracted from the foreground color. 7-4 6 New Text Enhancement If set this bit enables new text enhancement that does not affect the CRT display. If this bit is set to 1, the old text enhancement bit (XR61[6]) must be set to 0. Conversely, if XR61[6] is 1 then this bit should be set to 0. Reset defaults this bit to 1. Background Shift These bits define the number of levels that the background color is shifted when the foreground and background colors are closer than the SmartMapTM Threshold (XR61 bits 1-4). If the background color is "greater" than the foreground color, then this field is added to the background color. If the background color is "smaller" than the foreground color, then this field is subtracted from the background color. Revision 1.2 Color Threshold 7 Graphics Video Output Polarity (GVP) This bit is effective for CRT and flat panel graphics mode only. 0 1 Normal polarity Inverted polarity Note: Text video output polarity is controlled by XR61 bit-7 (TVP). 144 65540 / 545 (R) Extension Registers FP ALTERNATE VERTICAL TOTAL REGISTER (XR64) Read/Write at I/O Address 3D7h Index 64h FP ALTERNATE OVERFLOW REGISTER (XR65) Read/Write at I/O Address 3D7h Index 65h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 FP Alt V Total Bit-8 FP V Panel Size Bit-8 FP Alt VSync Start Bit-8 Reserved (R/W) FP Alternate V Total Reserved (R/W) FP Alt V Total Bit-9 FP Alt Panel Size Bit-9 FP Alt VSync Start Bit-9 This register is used in all flat panel modes. 7-0 This register is used in all flat panel modes. FP Alternate Vertical Total 0 FP Alternate Vertical Total Bit-8 The contents of this register are 8 low order bits of a 10-bit value. Bits 9 and 10 are defined in XR65. The vertical total value specifies the total number of scan lines per frame. Similar to CR06. 1 FP Vertical Panel Size Bit-8 2 FP Alternate Vertical Sync Start Bit-8 3 Reserved (R/W) 4 Reserved (R/W) 5 FP Alternate Vertical Total Bit-9 6 FP Vertical Panel Size Bit-9 7 FP Alternate Vertical Sync Start Bit-9 Programmed Value = Actual Value _ 2 Revision 1.2 145 65540 / 545 (R) Extension Registers FP ALTERNATE VERTICAL SYNC START REGISTER (XR66) Read/Write at I/O Address 3D7h Index 66h FP ALTERNATE VERTICAL SYNC END REGISTER (XR67) Read/Write at I/O Address 3D7h Index 67h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 FP Alt VSync End FP Alternate VSync Start Reserved(R/W) This register is used in all flat panel modes. 7-0 This register is used in all flat panel modes. FP Alternate Vertical Sync Start 3-0 The contents of this register are the 8 low order bits of a 10-bit value. Bits 9 and 10 are defined in XR65. This value defines the scan line position at which vertical sync becomes active. Similar to CR10. FP Alternate Vertical Sync End The lower 4 bits of the scan line count that defines the end of vertical sync. Similar to CR11. If the vertical sync width desired is N lines, the programmed value is: (contents of XR66 + N) ANDed with 0FH Programmed Value = Actual Value - 1 7-4 Revision 1.2 146 Reserved (R/W) 65540 / 545 (R) Extension Registers VERTICAL PANEL SIZE REGISTER (XR68) Read/Write at I/O Address 3B7h/3D7h Index 68h PROGRAMMABLEOUTPUTDRIVEREGISTER (XR6C) Read/Write at I/O Address 3B7h/3D7h Index 6Ch D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved(R/W) CFG8/LV#: Vcc Select Flat Panel Output Drive Bus Interface Output Drive Mem Intfc A&B Out Drive Mem Intfc C Out Drive Vertical Panel Size Reserved(R/W) This register is used in all flat panel modes. 7-0 This register is used to control the output drive of the bus, video, and memory interface pins. 0 Reserved (R/W) 1 CFG8 / LV# - Internal Logic Vcc Selection This bit determines pad input threshold. On the trailing edge of reset, this bit will latch the state of AA8 pin (CFG8). 0 VCC for internal logic (IVCC) is 3.3V 1 VCC for internal logic (IVCC) is 5V (Default) 2 Flat Panel Interface Output Drive Select 0 Lower drive (Default) (Use for DVCC=5V) 1 Higher drive (Use for DVCC=3.3V) 3 Bus Interface Output Drive Select 0 Higher drive (Default) (Use for BVCC=3.3V) 1 Lower drive (Use for BVCC=5V) 4 MemoryInterfaceA&BOutputDriveSelect This bit affects memory interface groups A & B control pins: RASB#, CASBH#, CASBL#, WEB#, OEB#, MAD[15:0] and MBD[15:0] 0 Lower drive (Default) (Use for MVCCA/B=5V) 1 Higher drive (Use for MVCCA/B=3.3V) 5 Memory Interface C Output Drive Select This bit affects memory interface group C control pins: RASC#, CASCH#, CASCL#, WEC#, OEC#, and MCD15:0. 0 Lower drive (Default) (Use for MVCCC=5V) 1 Higher drive (Use for MVCCC=3.3V) 7-6 Reserved (R/W) Vertical Panel Size The contents of this register define the number of scan lines per frame. Programmed Value = Actual Value - 1 Panel size bits 8-9 are defined in overflow register XR65. Note: Programming lower drive for 3.3V operation results in lower than rated output drive. Programming higher output drive for 5V operation results in higher than rated output drive. Revision 1.2 147 65540 / 545 (R) Extension Registers POLYNOMIAL FRC CONTROL REGISTER (XR6E) Read/Write at I/O Address 3D7h Index 6Eh D7 D6 D5 D4 D3 D2 D1 D0 Polynomial 'N' Value Polynomial 'M' Value This register is effective in flat panel mode when polynomial FRC is enabled (see XR50 bits 0-1). It is used to control the FRC polynomial counters. The values in the counters determine the offset in rows and columns of the FRC count. These values are usually determined by trial and error. 3-0 Polynomial 'N' value 7-4 Polynomial 'M' value This register defaults to '10111101' on reset. Revision 1.2 148 65540 / 545 (R) Extension Registers FRAMEBUFFERCONTROLREGISTER(XR6F) Read/Write at I/O Address 3D7h Index 6Fh 2 Asymmetric Address for DRAM C 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Frame Buffer Enable Frame Accelerator Enable DRAM C Asym addr select This bit is effective only if bit 7=1. Either Symmetric or Asymmetric DRAMs may be used. Frame Buffer Refrsh Count 5-3 6 Frame Buffer Lines / Page 0 1 This register is effective in flat panel mode only. 1 line per DRAM page 2 lines per DRAM page Frame Buffer Enable This bit is effective only if bit 7=1. This bit is used to enable frame buffer operation (external or embedded). Frame buffering is required for DD panel operation. For SS panel operation (LCD, Plasma or EL), frame buffering is not required so this bit should be set to 0. Note: 65540 only, should be programmed with 0 in the 65545. 0 1 7 Frame Buffer Method 0 Disable frame buffer (default) Enable frame buffer Since the 65540 and 65545 have the ability to embed frame buffer data in display memory, enabling frame buffering does not mean that an external DRAM frame buffer chip is required (see bit-7 of this register to set the frame buffer method). 1 Frame Buffer Refresh Count These bits are effective only if bit 7=1. Frame Buffer Lines/Page Frame Buffer Method 0 64Kx16 DRAM (8-bit RAS and CAS address) Symmetric or Asymmetric 256Kx16 DRAM (9-bit RAS and CAS address or 10 bit RAS and 8 bit CAS addresses) 1 Embedded Frame Buffer. Frame buffer data is stored in display memory (DRAM A or DRAMs A & B depending on the setting of XR04 bits 0-1) External Frame Buffer. DRAM "C" is used exclusively for frame buffer data. Note: This bit can be set to 1 only when XR04[1-0] (Memory Configuration) is set to either 00 (Display Memory in DRAMs A & B) or 01 (Display Memory in DRAM A). Frame Accelerator Enable Frame acceleration may be used for panels with vertical refresh rate specifications above 110 Hz to reduce the dot clock rate. For panels with vertical refresh rate specifications below 110 Hz, Frame Acceleration will violate panel specifications and should not be used. This bit should be programmed to 0 when the Frame Buffer is disabled (bit-0 of this register set to 0) or for non-DD panels. If this bit is set to 1, bit-0 of this register must be set to 1 and a DD panel must be used (XR51[1-0], Panel Type, must be set to 11). 0 1 Revision 1.2 Disable frame accelerator (default) Enable frame accelerator 149 65540 / 545 (R) Extension Registers SETUP/DISABLECONTROLREGISTER(XR70) Read/Write at I/O Address 3D7h Index 70h D7 D6 D5 D4 D3 D2 D1 D0 Reserved(0) 3C3/46E8 Register Disable 6-0 7 Reserved (0) 3C3 / 46E8 Register Disable 0 1 In local bus configuration, port 3C3h works as defined to provide control of VGA disable. In ISA bus configuration, port 46E8h works as defined to provide control of VGA disable and setup mode. In local bus configuration, writes to I/O port 3C3 have no effect. In ISA bus configuration, writes to I/O port 46E8h have no effect (the VGA remains enabled and will not go into setup mode). Note: Writes to register 46E8 are only effective in ISA bus configurations (46E8 is ignored in local bus configurations independent of the state of this bit). Writes to 3C3 are only effective in local bus configurations (3C3 is ignored in ISA bus configurations independent of the state of this bit). In PCI bus configuration (65545), this register has no effect; the chip comes up disabled except for the PCI configuration registers and the PCI configuration registers control VGA access. Reads from ports 3C3 and 46E8h have no effect independent of the programming of this register (both 3C3 and 46E8h are write-only registers). This register is cleared by reset. Revision 1.2 150 65540 / 545 (R) Extension Registers EXTERNAL DEVICE I/O REGISTER (XR72) Read/Write at I/O Address 3D7h Index 72h 5 This bit always reads back the status of the ENABKL pin (pin 54). When ENABKL is configured as general purpose output (XR72[7-6]=11), this bit determines the data output on the ENABKL pin. D7 D6 D5 D4 D3 D2 D1 D0 Reserved(R/W) ENAVEE Pin Control GPIO0 (ACTI) Data 7-6 00 Pin 54 is used to output ENABKL (enable backlight) (default on reset) 01 Reserved 10 Pin 54 is general purpose input 1 (GPIO1) 11 Pin 54 is general purpose output 1 (GPIO1) GPIO1 (ENABKL) Pin Ctrl Reserved (R/W) 1 ENAVEE Pin Control 0 1 2 GPIO1 ( ENABKL ) Pin Control This bit is effective only when XR01[4]=1, XR50[7]=0, and XR05[7-6]11. GPIO0 (ACTI) Pin Control GPIO1 (ENABKL) Data 0 GPIO1 ( ENABKL ) Data See also XR5C "Activity Timer Control Register". The activity timer may be used to activate ENABKL or to evoke Panel Off mode after a specified time interval. Pin 61 is used as Enable VEE (ENAVEE) output (default on reset) Pin 61 is used as Enable Backlight (ENABKL) output GPIO0 ( ACTI ) Data This bit always reads back the state of the ACTI pin (pin 53). When ACTI is configured as general purpose output (XR72[4-3]=11) this bit determines the data output on ACTI pin. 4-3 GPIO0 ( ACTI ) Pin Control This bit is effective only when XR01[4]=1, XR50[7]=0, and XR05[7-6]11. 00 Pin 53 is ACTI output (default on reset). ACTI goes high during valid VGA memory or I/O read or write operations that are recognized by the chip. 01 Reserved 10 Pin 53 is general purpose input 0 (GPIO0) 11 Pin 53 is general purpose output 0 (GPIO0) Revision 1.2 151 65540 / 545 (R) Extension Registers DPMS CONTROL REGISTER (XR73) Read/Write at I/O Address 3D7h Index 73h DIAGNOSTIC REGISTER (XR7D) (65545 Only) Read/Only at I/O Address 3D7h Index 72h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 HSYNC Data HSYNC Control VSYNC Data VSYNC Control Reserved(0) Reserved(0) BitBLT Clock Control This register is provided to allow the controller to independently shut down either or both of the HSYNC and VSYNC outputs. This capability allows the controller to signal a CRT monitor to enter power-saving states per the VESA DPMS (Display Power Management Signaling) Standard. The DPMS states are: H Active Inactive Active Inactive V Active Active Inactive Inactive 6-0 7 HSYNC Data If bit-1 of this register is programmed to 1, the state of this bit (XR73[0]) will be output on HSYNC (pin 65). 1 HSYNC Control Determines whether bit-0 of this register or internal CRTC horizontal sync information is output on HSYNC (pin 65). BitBLT Clock Control ( 65545 Only ) 0 1 Power Management State Normal Operation Standby (Quick Recovery) Opt Suspend (Max Power Savings) Off (Autorecovery is optional) 0 Reserved (0) BitBLT logic receives a continuous running memory clock The clock to the BitBLT logic is shut off 0 CRTC HSYNC is output (Default) 1 XR73[0] is output 2 VSYNC Data If bit-3 of this register is programmed to 1, the state of this bit (XR73[2]) will be output on VSYNC (pin 64). 3 VSYNC Control Determines whether bit-2 of this register or internal CRTC vertical sync information is output on VSYNC (pin 64). 0 CRTC VSYNC is output (Default) 1 XR73[2] is output 7-4 Reserved (0) Revision 1.2 152 65540 / 545 (R) Extension Registers CGA/HERCCOLORSELECTREGISTER(XR7E) Read/Write at I/O Address 3D7h Index 7Eh DIAGNOSTIC REGISTER (XR7F) Read/Write at I/O Address 3D7h Index 7Fh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Color Bit-0 (Blue) Color Bit-1 (Green) Color Bit-2 (Red) Color Bit-3 (Intensity) Intensity Enable Color Set Select 3-State Control Test Function Test Function Enable Special Test Function Reserved(0) This I/O address is mapped to the same register as I/O address 3D9h. This alternate mapping effectively provides a color select register for Hercules mode. Writes to this register will change the copy at 3D9h. The copy at 3D9h is visible only in CGA emulation or when the extension registers are enabled. The copy at XR7E is visible when the extension registers are enabled. 5-0 See Register 3D9 7-6 Reserved (0) 0 3-State Control Bit 0 0 1 1 3-State Control Bit 1 0 1 5-2 Normal outputs (default on reset) 3-state system bus and display output pins: HSYNC, VSYNC, FLM, LP, M, SHFCLK, P0-15, LDEV#, and LRDY#. Normal outputs (default on reset) 3-state memory output pins: RASA#, RASB#, RASC#, CASAL#, CASAH#, CASBL#, CASBH#, CASCL#, CASCH#, WEA#, WEB#, WEC#, OEAB#, OEC#, AA0-9, and CA0-9. Test Function These bits are used for internal testing of the chip when bit-6 = 1. 6 Test Function Enable This bit enables bits 5-2 for internal testing. 0 1 7 Disable test function bits (default) Enable test function bits Special Test Function This bit is used for internal testing and should be set to 0 (default to 0 on reset) for normal operation. Revision 1.2 153 65540 / 545 (R) Extension Registers Revision 1.2 154 65540 / 545 (R) 32-Bit Registers 32-Bit Registers ( 65545 Only ) Register Register Extension MnemonicGroup RegisterName Access I/O Type Address State After Reset Page DR00 DR01 DR02 DR03 DR04 DR05 DR06 DR07 BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Offset 16/32-bit BitBLT Pattern ROP 16/32-bit BitBLT BG Color 16/32-bit BitBLT FG Color 16/32-bit BitBLT Control 16/32-bit BitBLT Source 16/32-bit BitBLT Destination 16/32-bit BitBLT Command 16/32-bit R/W R/W R/W R/W R/W R/W R/W R/W 83D0-3 87D0-3 8BD0-3 8FD0-3 93D0-3 97D0-3 9BD0-3 9FD0-3 - - - - xxxx -------xxxxxxxx xxxxxxxx ---------------------- - - - 0000 xxxxxxxx - - - xxxxx xxxxxxxx xxxxxxxx - - - 0xxxx - - - xxxxx - - - xxxxx 00000000 - - - - xxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx - - - - xxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 156 156 157 157 158 159 159 160 DR08 DR09 DR0A DR0B DR0C Cursor Cursor Cursor Cursor Cursor Cursor Control Cursor Color 0-1 Cursor Color 2-3 Cursor Position Cursor Base Address R/W R/W R/W R/W R/W A3D0-3 A7D0-3 ABD0-3 AFD0-3 B3D0-3 -------xxxxxxxx xxxxxxxx x - - - - xxx -------- -------xxxxxxxx xxxxxxxx xxxxxxxx - - - - xxxx * * * *0000 xxxxxxxx xxxxxxxx x - - - - xxx xxxxxx - - 000 * * *00 xxxxxxxx xxxxxxxx xxxxxxxx -------- 161 162 162 163 164 Reset Codes: x d h r Revision 1.2 = = = = 16/32-bit 16/32-bit 16/32-bit 16/32-bit 16/32-bit Not changed by RESET (indeterminate on power-up) Set from the corresponding pin on falling edge of RESET Read-only Hercules Configuration Register Readback bits Chip revision # (starting from 0000) 155 - = Not implemented (always reads 0) * = Not implemented (read/write, reset to 0) 0/1 = Reset to 0 or 1 by falling edge of RESET 65540 / 545 (R) 32-Bit Registers BitBLT OFFSET REGISTER (DR00) BitBLT PATTERN ROP REGISTER (DR01) Write at I/O Address 83D0-83D3h Read at I/O Address 83D0-83D3h Word or DoubleWord Accessible Write at I/O Address 87D0-87D3h Read at I/O Address 87D0-87D3h Word or DoubleWord Accessible 3128 27 31 16 1512 11 0 21 20 0 Source Offset Pattern Pointer Reserved(0) Destination Offset Reserved(0) Reserved(0) 11-0 Source Offset 20-0 Pattern Pointer This value is added to the start address of the Source BitBLT to calculate the starting position for the next line. Address of Pattern Size - aligned 8 Pixel x 8 line pattern. For an 8BPP pattern (occupying 8 bits / pixel * 8 pixels / line * 8 lines / pattern) the pattern must be aligned on a 64 byte (16 DWord) boundary. For a 16BPP pattern (occupying 16bits / pixel * 8 pixels / line * 8 lines / pattern) the pattern must be aligned on a 128byte (32 DWord) boundary. For monochrome patterns (1 Bit / pixel * 8 pixels / line * 8 lines / pattern) the pattern must be aligned on an 8 byte (2 DWord) boundary. The lower bits of the Pattern Pointer are read/write, however the Drawing Engine forces them to zero for drawing operations. 15-12 Reserved (0) 27-16 Destination Offset This value is added to the start address of the Destination BitBLT to calculate the starting position for the next line. 31-28 Reserved (0) 31-21 Reserved (0) Warning: Revision 1.2 156 Do not read t his egister while a BitBLT is active. 65540 / 545 (R) 32-Bit Registers BitBLT BACKGROUND COLOR REGISTER (DR02) Write at I/O Address 8BD0-8BD3h Read at I/O Address 8BD0-8BD3h Word or DoubleWord Accessible BitBLT FOREGROUND COLOR REGISTER (DR03) Write at I/O Address 8FD0-8FD3h Read at I/O Address 8FD0-8FD3h Word or DoubleWord Accessible 31 31 0 0 Background Color Foreground Color 15-0 Foreground / Solid Color 15-0 Background Color This register contains the color data used during solid paint operations. It also is used as the foreground color during mono-color expansions. This register contains the background color data used during opaque mono-color expansions. All 16 bits must be written regardless of pixel depth. If the drawing engine is operating at 8BPP, then the same data should be duplicated in bits 31:24, 23:16, 15:8, and 7:0. For 16BPP the data is duplicated twice. All 16 bits must be written regardless of pixel depth. If the drawing engine is operating at 8BPP, then the same data should be duplicated in bits 31:24, 23:16, 15:8, and 7:0. For 16BPP the data is duplicated twice. 31-16 Duplicate of 15-0 31-16 Duplicate of 15-0 Warning: Only bits 15-0 are used. They are duplicated in bits 31-16 when this register is read back by the CPU. Revision 1.2 Warning: Only bits 15-0 are used. They are duplicated in bits 31-16 when this register is read back by the CPU. 157 65540 / 545 (R) 32-Bit Registers BitBLT CONTROL REGISTER (DR04) 12 Write at I/O Address 93D0-93D3h Read at I/O Address 93D0-93D3h Word or DoubleWord Accessible 31 27 23 20 19 16 15 87 0 ROP 13 INC_X, INC_Y Source Data Source Depth Pattern Depth Background BitBLT Src/Dst Pattern Seed Solid Pattern BitBLT Status Reserved(0) Buffer Status Reserved(0) 7-0 ROP Raster Operation as defined by Microsoft Windows. All logical operations of Source, Pattern, and Destination Data are supported. 8 INC_Y DeterminesBitBLTY-direction: 0 Decrement (Bottom to Top) 1 Increment (Top to Bottom) 9 INC_X DeterminesBitBLTX-direction: 0 Decrement (Right to Left) 1 Increment (Left to Right) 10 Source Data Selects variable data or color register data: 1 Source is FG Color Reg (DR03) 0 Source data selected by DR04[14] 11 15-14 18-16 19 20 Source Depth Selects between monochrome and color source data. This allows BitBLTs to either transfer source data directly to the screen or perform a font expansion (INC_X=1 only): 0 Source is Color 1 Source is Mono (Font expansion) 23-21 27-24 31-25 Revision 1.2 158 Pattern Depth Selects between monochrome and color pattern data. This allows the pattern register to operate either as a full pixel depth 8x8 pattern for use by the ROP, or as an 8x8 monochromepattern: 0 Pattern is Color 1 Pattern is Monochrome Background The 65540 / 545 supports both transparent and opaque backgrounds for monochrome patterns and font expansion: 0 BG is Opaque (BG Color Reg DR02) 1 BG is Transparent (Unchanged) BitBLT Source / Destination The 65540 / 545 only supports its local display memory as the destination for BitBLT operations. The source may be either display memory or system memory (CPU): 15 14 BitBLT Source --> Dest 0 0 Screen --> Screen (Dest) 0 1 System --> Screen (Dest) 1 0 Reserved 1 1 Reserved Pattern Seed Determines the starting row of the 8x8 pattern for the current BitBLT. A pattern is typically required to be destination aligned. The 65540 / 545 can determine the xalignment from the destination address however the y-alignment must be generated by the programmer. These three bits determine which row of the pattern is output on the first line of the BitBLT. Incrementing and decrementing are controlled by bit DR04[8]. Solid Pattern 1 = Solid Pattern (Brush) 0 = Bitmap Pattern BitBLT Status ( Read Only ) 0 BitBLT Engine Idle 1 BitBLT Active - do not write BitBLT regs Reserved (0) Buffer Status # of DWords that can be written to the chip: 0000 Buffer Full 0001 1 Space available in the queue ... ... 1111 15 Spaces available in the queue Reserved (0) 65540 / 545 32-BitRegisters BitBLT SOURCE REGISTER (DR05) BitBLT DESTINATION REGISTER (DR06) Write at I/O Address 97D0-97D3h Read at I/O Address 97D0-97D3h Word or DoubleWord Accessible Write at I/O Address 9BD0-9BD3h Read at I/O Address 9BD0-9BD3h Word or DoubleWord Accessible 31 31 21 20 0 Destination Addr Reserved(0) Reserved(0) 20-0 DestinationAddress Address of Byte aligned source block. Address of Byte aligned destination block. 31-21 Reserved (0) Revision 1.2 0 SourceAddress 20-0 Source Address Warning: 21 20 31-21 Reserved (0) Do not read this register while a BitBLT is active. Warning: 159 Do not read this register while a BitBLT is active. 65540 / 545 (R) 32-Bit Registers BitBLT COMMAND REGISTER (DR07) Write at I/O Address 9FD0-9FD3h Read at I/O Address 9FD0-9FD3h Word or DoubleWord Accessible 3128 27 16 1512 11 0 Bytes per Line Reserved(0) Lines per Block Reserved(0) 11-0 Bytes Per Line Number of bytes to be transferred per line 15-12 Reserved (0) 27-16 Lines Per Block Height in lines of the block to be transferred 31-28 Reserved (0) Warning: Do not attempt to perform a CPU read/write to display memory while a BitBLT is active. Revision 1.2 160 65540 / 545 (R) 32-Bit Registers CURSOR/POP-UPCONTROLREGISTER(DR08) 7-6 Write at I/O Address A3D0-A3D3h Read at I/O Address A3D0-A3D3h Word or DoubleWord Accessible 31 8 Cursor Enable Resrvd (must be 0) ULC Select 9 10 Reserved(R/W) Cursor / Pop-Up Menu Enable This bit enables the hardware cursor. The cursor will be enabled/disabled in the frame following the current active frame (synchronized to vertical blank). 11 Auto Zoom 0 Auto zoom off 1 Replicate pixels in high resolution modes. No pixel replication takes place in CRT interlace mode and for 32x32 cursor. Both Disabled 32x32 Cursor Enable 64x64 Cursor Enable Pop-Up Menu Enable 15-12 Reserved (R/W) Reserved (R/W) 31-16 Reserved (0) Must be programmed to 0. 5 Y Zoom (Manual) 0 No pixel replication. 1 Replicate pixels in the vertical direction. No pixel replication takes place in CRT mode and for 32x32 cursor. Reserved(0) 4-2 X Zoom (Manual) 0 No pixel replication. 1 Replicate pixels in the horizontal direction. No pixel replication takes place in CRT interlace mode and for 32x32 cursor. Test Pop-up Width X Zoom Y Zoom Auto Zoom 00 01 10 11 Pop-Up Menu Width 0 One bpp. Menu width = 128 pixels. This also forces a height of 128 lines. CC0 and CC1 (DR09) determine menu colors. 1 Two bpp. Menu width = 64 pixels. CC0-3 (DR09 and DR0A) determine menu colors. 16 1512 1110 9 8 7 6 5 4 2 1 0 1-0 Test Refer to the Functional Description section of this document for additional information on programming of the Hardware Cursor feature. Upper Left Corner ( ULC ) Select The cursor is set relative to either the Upper Left Corner (ULC) of the active display or of the overscan region. When set relative to the active display (BLANK#) the cursor will not be visible in the overscan area. When relative to Display Enable, the cursor may appear in the overscan region. All x,y positioning is relative to the selected ULC. 0 ULC is BLANK# (x=0, y=0 corresponds to the top left of the panel) 1 ULC is Display Enable (x=0, y=0 corresponds to the top left of the image) Revision 1.2 161 65540 / 545 (R) 32-Bit Registers CURSOR/POP-UPCOLOR0-1REGISTER(DR09) CURSOR/POP-UPCOLOR2-3REGISTER(DR0A) Write at I/O Address A7D0-A7D3h Read at I/O Address A7D0-A7D3h Word or DoubleWord Accessible Write at I/O Address ABD0-ABD3h Read at I/O Address ABD0-ABD3h Word or DoubleWord Accessible 31 31 27 26 21 20 16 15 11 10 5 4 0 21 20 16 15 11 10 5 4 0 CC0 - Blue CC2 - Blue CC0 - Green CC2 - Green CC0 - Red CC2 - Red CC1 - Blue CC3 - Blue CC1 - Green CC3 - Green CC1 - Red CC3 - Red Cursor Colors 0 and 1 are 16-bit high color values consisting of 5 bits of Red, 6 bits of Green, and 5 bits of Blue. Colors 0 and 1 may be accessed either as two 16-bit registers or as a single 32-bit register. A write to this register immediately affects the cursor color displayed. 4-0 27 26 Cursor Colors 2 and 3 are 16-bit high color values consisting of 5 bits of Red, 6 bits of Green, and 5 bits of Blue. Colors 2 and 3 may be accessed either as two 16-bit registers or as a single 32-bit register. Colors 2 and 3 are only used when the Cursor is in Pop-Up Mode. A write to this register immediately affects the cursor color displayed. CC0 - Blue 4-0 Cursor Color 0 Blue value CC2 - Blue Cursor Color 2 Blue value 10-5 CC0 - Green 10-5 CC2 - Green Cursor Color 0 Green value Cursor Color 2 Green value 15-11 CC0 - Red 15-11 CC2 - Red Cursor Color 0 Red value Cursor Color 2 Red value 20-16 CC1 - Blue 20-16 CC3 - Blue Cursor Color 1 Blue value Cursor Color 3 Blue value 26-21 CC1 - Green 26-21 CC3 - Green Cursor Color 1 Green value Cursor Color 3 Green value 31-27 CC1 - Red 31-27 CC3 - Red Cursor Color 1 Red value Cursor Color 3 Red value Revision 1.2 162 65540 / 545 (R) 32-Bit Registers CURSOR/POP-UPPOSITIONREGISTER(DR0B) 26-16 Y Offset Write at I/O Address AFD0-AFD3h Read at I/O Address AFD0-AFD3h Word or DoubleWord Accessible 3130 27 26 16 1514 11 10 Cursor Y-position. The cursor position is calculated as the signed offset (in pixels) between the Upper Left Corner (ULC) of the screen (as defined by BLANK#) and the Upper Left Corner of the cursor. Y Offset is the magnitude portion of the signed offset of the cursor position in the vertical axis. This magnitude in combination with the Y SIGN bit (31) form the signed offset of the cursor in the Y direction. 0 X Offset The Y OFFSET and Y SIGN may be written as a 16-bit quantity with bits 30-27 ignored. Reserved(0) X SIGN The range for the ULC of the cursor is: -2047 <= Y-Position <= 2047 Y Offset 30-27 Reserved (0) 31 Reserved(0) Y Sign Sign associated with the Y OFFSET magnitude which together form the signed offset of the cursor in the Y direction. Y SIGN 10-0 X Offset In pop-up menu mode negative values are not supported. Cursor X-position. The cursor position is calculated as the signed offset (in pixels) between the Upper Left Corner (ULC) of the screen (as defined by BLANK#) and the Upper Left Corner of the cursor. X Offset is the magnitude portion of the signed offset of the cursor position in the horizontal axis. This magnitude in combination with the X SIGN bit (15) form the signed offset of the cursor in the X direction. The X OFFSET and X SIGN may be written as a 16-bit quantity with bits 14-11 ignored. The range for the ULC of the cursor is: -2047 <= X-Position <= 2047 14-11 Reserved (0) 15 X Sign Sign associated with the X OFFSET magnitude which together form the signed offset of the cursor in the X direction. Revision 1.2 163 65540 / 545 (R) 32-Bit Registers CURSOR/POP-UP BASE ADDRESS (DR0C) Write at I/O Address B3D0-B3D3h Read at I/O Address B3D0-B3D3h Word or DoubleWord Accessible 31 20 19 10 9 0 Reserved(0) BaseAddress Reserved(0) 9-0 Reserved (0) 19-10 Base Address Base address for cursor / pop-up data in display memory. Bit 10 (address lsb) should be programmed to 0 when the 128x128 pop-up menu is being displayed. Defines a byte address in display memory as seen by the CPU. 31-20 Reserved (0) Refer to the Functional Description section of this document for additional information on programming of the Hardware Cursor feature. Revision 1.2 164 65540 / 545 (R) Functional Description System Interface Functional Blocks VL-Bus Interface The 65540 / 545 contains 5 major functional blocks including the standard VGA core (Sequencer, Attribute controller, Graphics Controller, and CRT Controller), a BitBLT engine (65545 only), Hardware Cursor (65545 only), Palette DAC, and Clock Synthesizer. There are also other subsystems such as the bus and memory interfaces which are transparent to both the user and software programmer. While in standard VGA modes only the VGA core, Palette DAC, and clock synthesizer are active. The 65540 / 545 operates as a 32-bit target on the VL-Bus. It has an optimized direct pin-to-pin connection for all VL-Bus signals to eliminate external components. Up to 28 bits of the 32-bit VLBus address may be decoded on-chip permitting location of the linear frame buffer anywhere in a 256MByte address space. Optionally, the upper 4 address bits may be decoded externally to support the full 32-bit, 4GB VL-Bus address space. Zero wait state read accesses are not permitted, however, the 65540 / 545 will terminate a read cycle in the second T2 if the data is available. Burst cycles are not supported. Bus Interface Two major buses are directly supported by the 65540 and 65545: Industry Standard Architecture (ISA), and VESA Local Bus (VL-Bus); the 65545 also supports the PCI Bus. Direct interfaces to popular 80486DX, 80486DX2, 80486SX, and 80386DX processors are supported by both chips. Connection to 16-bit PI bus and other 32-bit system buses such as EISA and Micro Channel (MC) are possible with external logic but are not inherently supported. Direct Processor Interface The 65540 / 545 can interface directly to all 32-bit x86-architecture processors. Its full non-multiplexed 28-bit address makes it simple to connect to the CPU. On valid 65540 / 545 accesses it will generate LDEV# which is monitored by the system logic controller. This interface is essentially the same as the VL-Bus interface with the exception that both 1x and 2x CPU clocks are acceptable. When using a 2x clock the CPU Reset must be connected to the 65540 / 545 CRESET input for phase coherency. The 65540 / 545 does not support pipelined mode in its 386 processor interface. ISA Interface The 65540 / 545 operates as a 16-bit slave device on the ISA bus. It maps its display memory into the standard VGA address range (0A0000-0BFFFFh). The VGA BIOS ROM is decoded in the 32KByte space at 0C0000-0C7FFFh (an output is available on the ROMCS# pin for ROM chip selection). Address lines LA23:17 are required for decoding MEMCS16# hence these addresses are latched internally by ALE. The remaining addresses (SA16:0) are accepted from the system without internal latching. The 65540 / 545 supports 16-bit memory and I/O cycles. Whenever possible the 65540 / 545 executes zero wait state memory cycles by asserting ZWS#. It does not generate MEMCS16# or ZWS# on ROM accesses. Memory may be mapped as a single linear frame buffer anywhere in the 16 MByte ISA memory space on a 512K/1MByte boundary (depending on the amount of display memory installed - see XR0B[4]). The 16-bit bus extension signals MEMR# and MEMW# are used for memory control since mapping above the 1MByte boundary is permitted. For ISA compatibility the IRQ pin operates as an active high level-triggered interrupt. Revision 1.2 PCI Interface The 65545 also supports a full 32-bit PCI bus interface as defined by PCI Interface Specification Revision 2.0. All features required of a non-busmaster 'target' device are implemented on-chip with no external glue logic required. Read/Write cycles are supported for Memory, I/O, and Configuration address spaces. Burst accesses are not supported. Interrupt capability is provided for vertical interrupts. Refer to the PCI Pin Descriptions and Configuration Registers sections for further information. 165 65540 / 545 (R) Functional Description Display Memory Interface Memory Architecture memory data bus of the 65540 / 545 to traditional VGA 'plane' concepts. For example, text data is still stored in 'plane' 0, attribute data in 'plane' 1, and font data in 'plane' 2, but due to the extensive use of page-mode cycles and the use of a single address bus for display memory data, where those planes are physically located in the DRAMs is much different. The 65540 / 545 supports both 512K and 1MB configurations for display memory plus an additional 512K for an optional external frame buffer. Frame buffering is required for support of simultaneous display on CRTs and DD panels, however, the 65540 / 545 has the ability to embed frame buffer data in display memory. Since this uses some of the available memory bandwidth, the 65540 / 545 also supports an additional DRAM for use as an external frame buffer for improved performance. In addition, the 65540 / 545 make extensive use of internal FIFOs to improve performance. As a result the read / write activity on the DRAM interface pins at any point in time corresponds only approximately to system bus and CRT / panel output activity at that time. The 65540 / 545 implements a 32-bit wide data bus for display memory and 16-bit for the optional external frame buffer. The memory data buses are named 'A', 'B', and 'C' in groups of 16 bits. 'A' holds the lower 512K of display memory, 'B' normally holds the upper 512K of display memory in 1MB configurations and 'C' is normally used for the external frame buffer (if used). The chip may, however, be optionally programmed to put the upper half of display memory in DRAM 'C' instead (i.e., 'C' may be programmed to hold either display memory or external frame buffer data). When an external frame buffer is not required, 'C' may also be used as an input port for external video data (to implement overlay of live video over VGA output for example) and to provide additional panel interface data bits beyond the basic 16 (for TFT panels with 18-bit or 24-bit data interfaces since TFT panels are single panels and never require frame buffering). Memory Chip Requirements The 65540 / 545 is designed to use 256K x 4 or 256K x 16 DRAMs. Fast-page-mode capability is required. Either 'CAS-Before-RAS' or 'SelfRefresh' DRAMs may be used. Both dual-CAS# (default) and dual-WE# types of 256Kx16 DRAMs are supported. DRAMs with 'symmetrical' address inputs (A0-8) are supported by default, but the chip can be configured to support 'asymmetrical' address (A0-9) DRAMs. The BIOS can test the DRAMs to detect the type of DRAM used and program the chip accordingly. The 65540 / 545 can generate Page Mode Read, Page Mode Write, and Page Mode Read-Modify-Write cycles. CAS-before-RAS Refresh and Self-Refresh cycles are also supported. The memory interface is optimized for 40ns page mode cycles but is flexible and can be tuned for any speed DRAM. There are separate groups of RAS, CAS, and WE pins for each of the three DRAMs (A, B, and C). There are only two OE pins and two address buses however, one for A and B and another for C. Configuration initialization data is latched from memory address pins AA0-8 (the address bus for DRAMs A and B) at the end of reset. These bits are readable in XR01[0-7] and XR6C[1] respectively. The 65540 / 545 supports various DRAM speeds. The maximum frequency of the 65540 / 545 is 75 MHz. The recommended maximum memory clock frequency for various DRAM based on commonly available DRAM specifications is as follows: The 65540 and 65545 support all VGA text and graphics modes (planar, packed pixel, odd/even chain modes, etc.) but the storage locations of the data (i.e., the locations and bit positions in the DRAMs) does not correspond to the original VGA which implemented 256KB of display memory as 4 physical 'planes' of 64KB (using two 64Kx4 DRAMs to implement each 'plane' with separate address buses for planes 0-1 and 2-3). In other words, no assumptions should be made regarding the correspondence of the data pins on the display Revision 1.2 DRAM Speed 100 ns 80 ns 70 ns Memory Clock Frequency* 50.000 MHz 57.000 MHz 65.000 MHz * DRAM AC timing parameters varies among different DRAM manufacturers therefore please check with DRAM specifications and 65540 / 545 memory timing. 166 65540 / 545 (R) Functional Description Clock Synthesizer An integrated clock synthesizer supports all pixel clock (VCLK) and memory clock (MCLK) frequencies which may be required by the 65540 / 545. Each of the two clock synthesizer phase lock loops may be programmed to output frequencies ranging between 1MHz and the maximum specified operating frequency for that clock in increments not exceeding 0.5%. The frequencies are generated by an 18-bit divisor word. This value contains divisor fields for the Phase Lock Loop (PLL), Voltage Controlled Oscillator (VCO) and Pre/Post Divide Control blocks. The divisor word for both synthesizers is programmable via Clock Control Registers XR30-32. Specifications for maximum frequencies at 3.3V and 5V (the maximum frequency at 3.3V will be slightly lower). Normal MCLK operational frequencies are defined by the display memory sequencer parameters described in the Memory Timing section. The frequency selected is also dependent upon the AC characteristics of the display memories connected to the 65540 / 545. A typical match is between industry standard 70ns access memories and a 65MHz MCLK. The MCLK output defaults to 60MHz on reset and is fully programmable. This initial value is conservative enough not to violate slow DRAM parameters but not so slow as to cause a system timeout on CPU accesses. The MCLK frequency must always equal or exceed the host clock (CCLK) frequency. MCLK Operation Normal operational frequencies for MCLK are between 50MHz and 68MHz. Refer to the Electrical VCLKRegisterTable VGA CLK0 = 25.175MHz 21 VGA CLK1 = 28.322MHz VCLK Synthesizer CLK2 = Programmable XR32:30 MCLKRegisterTable 21 MCLK = Programmable CLKSEL1:0 MCLK Synthesizer MISC Output Reg[3:2] Clock Synthesizer Register Structure XR30[0] 1 Reference XR32[6:0] 7 PSN /N Phase Detector Charge Pump VCO /2 P CLK Internal Loop Filter XR31[6:0] XR30[3:1] /4M 7 3 post-VCO divider select Phase-Locked Loop Oscillator Clock Synthesizer PLL Block Diagram Revision 1.2 167 65540 / 545 (R) Functional Description VCLK Operation Programming Constraints There are five primary programming constraints the programmer must be aware of: 4 MHz FREF 20 MHz 150 KHz F REF/(PSN * N) 2 MHz 48 MHz < FVCO 220 MHz 3 M 127 3 N 127 The VCLK output typically ranges between 19MHz and 65MHz. VCLK has a table of three frequencies from which to select a frequency. This is required for VGA compatibility. CLK0 and CLK1 are fixed at the VGA compatible frequencies of 25.175MHz and 28.322MHz respectively. These values can not be changed unlike CLK2 which is fully programmable. The active frequency is chosen by clock select bits MSR[3:2]. The constraints have to do with trade-offs between optimum speed with lowest noise, VCO stability, and factors affecting the loop equation. Programming the Clock Synthesizer The desired output frequency is defined by an 18-bit value programmed in XR30-32. The 65540 / 545 has two programmable clock synthesizers; one for memory (MCLK) and one for video (VCLK). They are both programmed by writing the divisor values to XR30-32. The clock to be programmed is selected by the Clock Register Program Pointer XR33[5]. The output frequency of each of the clock synthesizers is based on the reference frequency (FREF) and the 4 programmed fields: Field Prescale N (PSN) Mcounter(M') N counter (N') Post Divisor (P) FOUT = # Bits XR30[0] XR31[6:0] XR32[6:0] XR30[3:1] The value of FVCO must remain between 48 MHz and 220 MHz inclusive. Therefore, for output frequencies below 48 MHz, FVCO must be brought into range by using the post-VCO Divisor. To avoid crosstalk between the VCO's, the VCO frequencies should not be within 0.5% of each other nor should their harmonics be within 0.5% of the other's fundamental frequency. The 65540 / 545 clock synthesizers will seek the new frequency as soon as it is loaded following a write to XR32. Any change in the post-divisor will take affect immediately. There is a possibility that the output may glitch during this transition of post divide values. Because of this, the programmer may wish to hold the post-divisor value constant across a range of frequencies (eg. changing MCLK from the reset value of 50MHz to 72MHz). There is also the consideration of changing from a low frequency VCO value with a post-divide /1 (eg. 50MHz) to a high frequency /4 (eg. 220MHz). Although the beginning and ending frequencies are close together, the intermediate frequencies may cause the 65540 / 545 to fail in some environments. In this example there will be a short-lived time frame during which the output frequency will be in the neighborhood of 12.5MHz. The bus interface may not function correctly if the MCLK frequency falls below a certain value. Register and memory accesses which are synchronized to MCLK may be so slow as to violate bus timing and cause a watchdog timer error. Programmers should time-out the system (CPU) for approximately 10ms after writing XR32 before accessing the VGA again. This will ensure that accesses do not occur to the VGA while the clocks are in an indeterminate state. (/1 or /4) (M' = M - 2) (N' = N - 2) (/2P; 0 P 5) FREF * 4 * M PSN * N * 2 P The frequency of the Voltage Controlled Oscillator (FVCO) is determined by these fields as follows: FVCO = FREF * 4 * M PSN * N where F REF = Reference frequency (between 4 MHz - 20 MHz; typically 14.31818 MHz) Note: If a reference frequency other than 14.31818 MHz is used, then the frequencies loaded on RESET will not be correct. P Post Divisor 000 001 010 011 100 101 1 2 4 8 16 32 Revision 1.2 Note: On reset the MCLK is initialized to a 60MHz output with a post divisor = 2 (FVCO = 120MHz). 168 65540 / 545 (R) Functional Description Programming Example PCB Layout Considerations The following is an example of the calculations which are performed: Clock synthesizers, like most analog components, must be isolated from the digital noise which exists on a PCB power plane. Care must be taken not to route any high frequency digital signals in close proximity to the analog sections. Inside the 65540/545, the clocks are physically located in the lower left corner of the chip surrounded by low frequency input and output pins. This helps minimize both internally and externally coupled noise. Derive the proper programming word for a 25.175 MHz output frequency using a 14.31818 MHz reference frequency: Since 25.175 MHz < 48 MHz, double it to 50.350 MHz to get FVCO in its valid range. Set the post divide field (P) to 001. Prescaling PSN = 4 The memory clock and video clock power pins on the 65540/545 each require similar RC filtering to isolate the synthesizers from the VCC plane and from each other. The filter circuit for each CVCCn / CGNDn pair is shown below: The result: FVCO = 50.350 = (14.31818 x 4 x M/4 x N) M/N = 3.51655 +5V Several choices for M and N are available: M 109 102 N 31 29 FVCO 50.344 50.360 10 CVCCn Error -0.00300 +0.00500 0.1F CGNDn The suggested method for layout assumes a multilayer board including VCC and GND planes. All ground connections should be made as close to the pin / component as possible. The CVCC trace should route from the 65540/545 throughthepads of the filter components. The trace should NOT be connected to the filter components by a stub. All components (particularly the initial 0.1F capacitor) should be placed as close as possible to the 65540/545. Prescaling PSN = 1 The result: FVCO = 50.350 = (14.31818 x 4 x M/1 x N) M/N = 0.879127 N 91 FVCO 50.349 0.1F GND Choose (M, N) = (109,31) for best accuracy. M 80 47F Error -0.00050 FREF/(PSN x N) = 157.3KHz A19 GND VCC A20 A21 GND Therefore M/N = 80/91 with PSN = 1 is even better than with PSN = 4. XR30 = 0000010b (02h) XR31 = 80 - 2 = 78 (4Eh) XR32 = 91 - 2 = 89 (59h) C2 C1 A22 R1 C3 CGND0 GND XTALI XTALO GND CVCC0 CVCC1 RESET# CGND1 R2 Designator C1,C3,C4,C6,C7 C2,C5 R1,R2 Value 0.1F 47F 10 NOTE: Do not connect Vcc here. Force the trace through the decoupling cap pad. C6 GND C5 VCC VCC GND C4 GND C7 GND Always pass the Vcc trace through the decoupling cap pad. Do not leave a stub as shown here. Revision 1.2 169 65540 / 545 (R) Functional Description VGA Color Palette DAC The 65540 / 545 integrates a VGA compatible triple 6-bit lookup table (LUT) and high speed 6/8-bit DACs. Additionally the internal color palette DAC supports true-color bypass modes displaying color depths up to 24bpp (8-8-8). The palette DAC can switch between true-color data and LUT data on a pixel by pixel basis. Thus, video overlays may be any arbitrary shape and can lie on any pixel boundary. The hardware cursor is also a true-color bitmap which may overlay both video and graphics on any pixel boundary. RDY in the ISA configuration and by delaying LRDY# for VL-Bus and direct processor interfaces. For compatibility with the VL-Bus Specification the 65540 / 545 may be disabled from responding to palette writes (although it will perform them) so that an adapter card on a slow (ISA) bus which is shadowing the palette LUT may see the access. The 65540 / 545 always responds to palette read accesses so it is still possible for the shadowing adapter to become out of phase with the internal modulo-3 RGB pointer. It is presumed that this will not be a problem with well-behaved software. The internal palette DAC register I/O addresses and functionality are 100% compatible with the VGA standard. In all bus interfaces the palette DAC automatically controls accesses to its registers to avoid data overrun. This is accomplished by holding Extended display modes may be selected in the Palette Control Register (XR06). Two 16bpp formats are supported: 5-5-5 Targa format and 5-6-5 XGA format. HighColorPixelData Hardware Cursor ExternalRGBVideo (565, 666, or 888) LUTPixelData 24 8 Triple6-bit LUT Red Triple 6/8-bit DAC Green Blue 18 VGA Color Palette DAC Data Flow Revision 1.2 170 65540 / 545 (R) Functional Description BitBLT Engine ( 65545 only ) Bit Block Transfer destination screen widths are independently programmable. This permits expansion of a compressed offscreen bitmap transparent to the software driver. The BitBLT Control Register (DR04) uses the same raster-op format as the Microsoft Windows ROP so no translation is required. All 256 Windows defined ROPs are available. The 65545 integrates a Bit Block Transfer (BitBLT) Engine which is optimized for operation in a Microsoft Windows environment. The BitBLT engine supports system-to-screen and screen-toscreen memory data transfers. It handles monochrome to color data expansion using either system or screen data sources. Color depths of 8 and 16bpp are supported in the expansion logic. Integrated with the screen and system BitBLT data streams is a 3-operand raster-op (ROP) block. This ROP block includes an independent 8x8 pixel (mono or color) pattern. Color depths of 8 and 16bpp are supported by the pattern array. All possible logical combinations of Source (system or screen data), Destination (screen data), and Pattern data are available. All possible overlaps of source and destination data are handled by controlling the direction of the BitBLT in the x and y directions. As shown below there are eight possible directions for a screen-toscreen BitBLT (no change in position is a subset of all eight). Software must determine the overlap, if any, and set the INC_X and INC_Y bits accordingly. This is only critical if the source and destination actually overlap. For most BitBLTs this will not be the case. In BitBLTs where INC_X is a 'don't care' it should be set to 1 (proceed from left to right). This will increase the performance in some cases. The BitBLT and ROP subsystems have been architected for compatibility with the standard Microsoft Windows BitBLT parameter block. The source and Source Dest INC_X = X; INC_Y = 0 Source Source Source Dest INC_X = 0; INC_Y = X Dest Dest INC_X = X; INC_Y = 0 Arrows indicate appropriate direction for BitBLT progression so that destination overlap does not corrupt data. Dest Dest INC_X = X; INC_Y = 0 Dest INC_X = 1; INC_Y = X Dest Source Source INC_X = X; INC_Y = 1 INC_X = X; INC_Y = 1 Source Source INC_X = X; INC_Y = 1 Possible BitBLT Orientations With Overlap Revision 1.2 171 65540 / 545 (R) Functional Description Sample Screen-to-Screen Transfer The Pattern ROP Register does not need to be programmed since there is no pattern involved. Neither the Foreground Color nor Background Color Register has to be programmed since this does not involve a color expansion or rectangle solid color paint. The BitBLT Control Register contains the most individual fields to be set: Below is an example of how a screen-to-screen BitBLT operation is traditionally performed. The source and destination blocks both appear on the visible region of the screen and have the same dimensions. The BitBLT is to be a straight source copy with no raster operation. The memory address space is 2MBytes and display resolution is 1024 x 768. The size of the block to be transferred is 276 horizontal x 82 vertical pixels (114h x 52h). The coordinates of the upper left corner (ULC) of the source block is 25h,30h. The ULC coordinates of the destination block are 157h,153h. Because the source and destination blocks do not overlap, the INC_X and INC_Y BitBLT direction bits are not important. We will assume that INC_X = 1, INC_Y = 0, and the BitBLT will proceed one scan line at a time from the lower left corner of the source moving to the right and then from the bottom to the top. ROP = Source Copy = 0CCh INC_Y = 0 (Bottom to Top) INC_X = 1 (Left to Right) Source Data = Variable Data = 0 Source Depth = Source is Color = 0 Pattern Depth = Don't Care = 0 Background = Don't Care = 0 BitBLT = Screen-to-Screen = 00 Pattern Seed = Don't Care = 000 BitBLT Control Register (DR04) = 002CCh Since the BitBLT will be starting in the lower left corner (LLC) of the source rectangle, the start address for the source data is calculated as: The source and destination offsets are both the same as the screen width (400h): BitBLT Offset Register (DR00) = 04000400h 400h (1024) 1FFFFFh 25h,30h 52h 114h Source Line 52h 020425h 0C0000h 138h,81h 300h (768) 020538h Off-Screen Memory 157h,153h 06926Ah Dest 054D57h Destination 26Ah, 1A4h 020538h Source 00C025h 000000h 1024 x 768 x 8BPP 00C938h Line 3 00C825h 2EDh 400h 00C538h Line 2 00C425h Line 1 00C138h 00C025h Screen-to-Screen BitBLT Revision 1.2 172 65540 / 545 (R) Functional Description (81h * 400h) + 25h = 020425h BitBLT Source Register (DR05) = 020425h determine when the BitBLT is finished so that another BitBLT may be issued. No reads or writes of the display memory by the CPU are permitted while the BitBLT engine is active. Similarly, the LLC of the destination register calculated as: In the present example the BitBLT source and destination blocks have the same width as the display. As can be seen below each scan line is transferred from source to destination. Alignment is handled by the BitBLT engine without assistance from software. (1A4h * 400H) + 157h = 069157h BitBLT Destination Register (DR06) = 069157h To begin any BitBLT the Command Register must be written. This register contains key information about the size of the current BitBLT which must be written for all BitBLT operations: Compressed Screen-to-Screen Transfer Next we consider an example of how a screen-toscreen BitBLT operation is performed when the source and destination blocks have different widths (pitch). This type of BitBLT is commonly used to store bitmaps efficiently in offscreen memory or when recovering a saved bitmap from offscreen memory. Lines per Block = 52h Bytes per line = 114h (Current example 8bpp) Command Register (DR07) = 00520114h The 65545 display memory consists of a single linear frame buffer. The number of bytes per scan line and lines displayed changes with resolution and pixel depth. For simplification, the concepts of pixels, After the Command Register (XR07) is written the BitBLT engine performs the requested operation. The status of the BitBLT operation may be read in DR04[20] (read only bit). This is necessary to 1FFFFFh 020538h Off-Screen Memory 06926Ah Line 52h Line 52h 020425h 069157h Off-Screen Memory 1FFFFFh 0C0000h 0C0000h 069269h Dest 054D57h 069269h Dest 054D57h 020538h Source 00C025h 000000h 00C938h 05566Ah Line 3 Line 3 00C825h 055557h 020538h Source 00C025h 000000h 2EDh 400h 00C538h 05526Ah 00C425h 055157h 00C138h 054E6Ah 00C025h 054D57h Line 2 Line 1 Line 2 Line 1 BitBLT Data Transfer Revision 1.2 173 65540 / 545 (R) Functional Description lines, and columns are foreign to the BitBLT engine. Instead, the 65545 operates on groups of bytes (rows) which are separated by the width of the screen. The 65545 permits separation between the row lengths to be different for source and destination bitmaps. For efficient use of offscreen memory we may assume that the "width" of the screen is the same as the width of the data. moving to the right and then from the top to the bottom. The source offset is the same as the screen width (400h) and the destination offset is the same as the source block width (114h): BitBLT Offset Register (DR00) = 01140400h The Pattern ROP Register does not need to be programmed since there is no pattern involved. Neither the Foreground Color nor Background Color Register has to be programmed since there is no color expansion. The BitBLT Control Register contains the following bit fields: Below is an example of how a screen-to-screen BitBLT operation is performed with the destination data efficiently compressed into the offscreen area. The reverse operation is also valid to recreate the original block on the visible screen. Once again the BitBLT is to be a straight source copy with the source block in the same location as the previous example. The destination block is to be located beginning at the first byte of off-screen memory. Because the source and destination blocks do not overlap the INC_X and INC_Y BitBLT direction bits are not important. We will assume that INC_X = 1, INC_Y = 1 and the BitBLT will proceed one scan line at a time from the upper left corner of the source 1FFFFFh ROP = Source Copy = 0CCh INC_Y = 1 (Top to Bottom) INC_X = 1 (Left to Right) Source Data = Variable Data = 0 Source Depth = Source is Color = 0 Pattern Depth = Don't Care = 0 Background = Don't Care = 0 BitBLT = Screen --> Screen = 00 020538h 1FFFFFh Line 52h 020425h Off-Screen Memory Off-Screen Memory 0C5867h Line 52h 0C5754h Dest Dest 0C0000h 020538h 0C0000h Source 00C938h Line 3 00C025h 000000h Source 0C0336h 0C0228h 0C0227h 0C0114h 0C0113h 00C825h 2EDh 400h Line 3 020538h Source 00C025h Line 2 Line 1 000000h 0C0000h 00C538h Destination Line 2 00C425h Line 1 00C138h 00C025h Source Differential Pitch BitBLT Data Transfer Revision 1.2 174 65540 / 545 (R) Functional Pattern Seed = Don't Care = 000 will be recognized as BitBLT source data and will be routed to the correct address by the BitBLT engine. This enables the programmer to set up a destination pointer into the video address window (doubleword aligned) and simply perform a REP MOVSD. Any unused data in the last word/doubleword write will be discarded by the BitBLT Engine. BitBLT Control Register (DR04) = 003CCh Since the BitBLT will be beginning in the ULC of the source rectangle, the start address for the source data is calculated as: (30h * 400h) + 25h = 0C025h BitBLT Source Register (DR05) = 0C025h For system-to-screen monochrome (font) expansions the data is handled on a scanline by scanline basis. As with the system-to-screen BitBLT with ROP, this type of transfer uses the 2 LSbits of the source address register to determine the beginning byte index into the first doubleword. On subsequent scanlines the source offset register is added to the current scanline byte index to determine the indexing for the start of the next scan line. Monochrome data is taken from bit 7 through bit 0, byte 0 through 3 and expanded left to right in video memory (NOTE: monochrome source only supports left to right operation). At the end of the first scanline any remaining data in the active doubleword is flushed and the byte pointer for the starting byte in the next doubleword (for the next scanline) is calculated by adding 2 LSbits of the source offset to the starting byte position in the previous scanline. Monochrome expansion then continues bit 7 through 0 incrementing byte (after byte 3 bit 0 a new doubleword begins at byte 0: bit 7) until the scanline is complete. Note that the number of bytes programmed into the Command register references the number of expanded bytes written; not the number of bytes to be expanded. Similarly, the ULC of the destination register calculated as (Number of scan lines * Bytes per scan line): 300h * 400h = 0C0000h BitBLT Destination Register (DR06) = 0C0000h As in the previous example the Command Register must be written to begin the BitBLT. This register contains the size of the current BitBLT which must be written for all BitBLT operations: Lines per Block = 52h Bytes per line = 114h (Current example 8bpp) Command Register (DR07) = 00520114h System-to-Screen BitBLTs When performing a system-to-screen BitBLT the source rotation information is passed in the BitBLT Source Address and Source Offset registers. The 2 LSbits of the Source Address register indicate the alignment. For example if the system data resides at system address 0413456h then the processor pointer should be set to 0413454h (doubleword aligned) and the Source address register is written with xxxxx2h. When the end of the scan line is reached (the number of bytes programmed in the Command Register have been written) any remaining bytes in the last doubleword written to the 65545 are discarded. The 2 LSbits of the Source Offset Register are then added to the 2 LSbits of the Source Address Register to determine the starting byte alignment for the first doubleword of the next scanline. This process is continued until all scanlines are completed. The most common case will be a doubleword aligned bitmap in system memory in which case the 2 Lbits of the Source Address Register are zero. It is also common for bitmaps to be stored with each scanline doubleword aligned (Source Offset Register = xxxxx0h). Once the Command Register is written and the BitBLT operation has begun the 65545 will wait for data to be sent to its memory address space. Any write to a valid 65545 memory address, either in the VGA space or linear address space if enabled, Revision 1.2 Description 175 65540 / 545 (R) Functional Description Revision 1.2 176 65540 / 545 (R) Functional Description Hardware Cursor ( 65545 only ) The 65545 supports four types of cursors: 32 x 32 64 x 64 64 x 64 128 x 128 x 2bpp x 2bpp x 2bpp x 1bpp Cursor Data Array Format and Layout (and/xor) (and/xor) (4-color) (2-color) Cursor data is stored in display memory as shown: 32x32 2bpp Cursor Offset Line Plane 0 Plane 1 Plane 2 000h 0 A7-0 X7-0 A15-8 004h 0 A23-16 X23-16 A31-24 008h 1 A7-0 X7-0 A15-8 00Ch 1 A23-16 X23-16 A31-24 ... ... ... ... ... 0FCh 31 A23-16 X23-16 A31-24 The first two hardware cursor types indicated as 'and/xor' above follow the MS WindowsTM AND/XOR cursor data plane structure which provides for two colors plus 'transparent' (background color) and 'inverted' (background color inverted). The last two types in the list above are also referred to as 'Pop-Ups' because they are typically used to implement pop-up menu capabilities. Hardware cursor / pop-up data is stored in display memory, allowing multiple cursor values to be stored and selected rapidly. The two or four colors specified by the values in the hardware cursor data arrays are stored in on-chip registers as highcolor (5-6-5) values independent of the on-chip color lookup tables (i.e., Attribute Controller and VGA Color Palette). 64x64 2bpp Cursor / Pop-Up Offset Line Plane 0 Plane 1 Plane 2 Plane 3 000h 0 A7-0 X7-0 A15-8 X15-8 004h 0 A23-16 X23-16 A31-24 X31-24 008h 0 A39-32 X39-32 A47-40 X47-40 00Ch 0 A55-48 X55-48 A63-56 X63-56 010h 1 A7-0 X7-0 A15-8 X15-8 014h 1 A23-16 X23-16 A31-24 X31-24 ... ... ... ... ... ... 3FCh 63 A55-48 X55-48 A63-56 X63-56 128x128 1bpp Pop-Up Offset Line Plane 0 Plane 1 Plane 2 Plane 3 000h 0 P7-0 P15-8 P23-16 P31-24 004h 0 P39-32 P47-40 P55-48 P63-56 008h 0 P71-64 P79-72 P87-80 P95-88 00Ch 0 P103-96 P111-104 P119-112 P127-120 010h 1 P7-0 P15-8 P23-16 P31-24 014h 1 P39-32 P47-40 P55-48 P63-56 ... ... ... ... ... ... 7FCh 127 P103-96 P111-104 P119-112 P127-120 The hardware cursor can overlay either graphics or video data on a pixel by pixel basis. It may be positioned anywhere within screen resolutions up to 2048x2048 pixels. 64x64 'and/xor' cursors may also be optionally doubled in size to 128 pixels either horizontally and/or vertically by pixel replication. Hardware cursor screen position, type, color, and base address of the cursor data array in display memory may be controlled via the 32-bit 'DR' extension registers. A7/X7 is the left-most pixel of the cursor pattern displayed on the screen for all cursor types. Note that 32x32 cursors take up 256 bytes each (the upper 3/4 of the 1KB space allocated for each cursor storage location in display memory is unused). 128x128 cursors (pop-ups) take up 2KB each, so require A10 of the base address to be set to 0. Hardware Cursor Programming Once the 32-bit extension registers are enabled (XR03[1]=1), the cursor registers (DR08-DR0C) may be accessed. DR08 controls the cursor type and X/Y zoom (H/V pixel replication). It also enables the hardware cursor to appear on the screen. DR09 and DR0A specify up to four 16-bit RGB (5-6-5) cursor color values. DR0B specifies the cursor position on screen in X-Y coordinates (number of pixels from the left and top edges of the addressable portion of the display). DR0C specifies the address in display memory where the cursor data array is stored. A 10bit base address may be specified allowing cursor data patterns to be stored in any of 1024 different locations in the maximum 1MB of display memory. Each cursor storage area takes up 1024 bytes of display memory which is exactly large enough to hold a 64x64x2 cursor pattern. Revision 1.2 Plane 3 X15-8 X31-24 X15-8 X31-24 ... X31-24 Cursor data array elements map as follows: Ann Xnn 0 0 0 1 1 0 1 1 And/Xor Type Color 0 Color 1 Transparent Inverted 4-Color Type Color 0 Color 1 Color 2 Color 3 where colors 0 and 1 are defined by DR09 and colors 2 and 3 are defined by DR0A. Each pixel in 2-color (1bpp) cursors (pop-ups) may be either color 0 or color 1. 177 65540 / 545 (R) Display Memory Base Address Formation Copying Cursor Data to Display Memory The address bits in the cursor base address register DR0C are aligned so they are in the proper position corresponding to the CPU address required to write to display memory. However, there are two methods of addressing display memory, VGA-style and 'Linear Frame Buffer' style, so the actual CPU address for loading a cursor data array must be constructed differently depending on the addressing method used. If VGA addressing is used, the lower 16-bits of DR0C may be used as an offset into the 64KB VGA address space (starting at either 0A0000h or 0B0000h depending on whether the VGA is set for text mode or graphics mode). DR0C bits 16-19 would then be used to control the VGA's paging mechanism to set the 64KB CPU aperture into display memory to the correct location for storing the cursor pattern (see XR0B, XR10, and XR11). If 'linear frame buffer' addressing is used, the entire 1MB of display memory can be accessed directly and the base value in DR0C may be used directly as a 24-bit offset into a programmable 1MB space in system memory (specified in the Linear Addressing Base register XR08). Once the base address for the cursor data pattern in display memory has been determined and the VGA has been properly programmed, the cursor data pattern may be copied from system memory to display memory. The following program sequence shows an example of one method which may be used: es:edi = display memory base address for cursor ds:si = address of AND array in system memory ds:bx = address of XOR array in system memory MOV MOV SHL MOV MOV STOSD Setting the Cursor Position, Type, and Base Address Following storage of the cursor data array in display memory, the location of the cursor in display memory is set via the Cursor Base Address register (DR0C) and the X-Y coordinates for positioning the cursor are written to the Cursor Position Register (DR0B). The cursor type and X/Y zoom (H/V pixel replication) factors are then set and the cursor enabled via the Cursor Control Register (DR08). VGA Controller Programming In order to copy the cursor data pattern to the controller, the VGA controller must be properly programmed for 32-bit direct access to all 4 planes. Proper programming for the controller consists of putting the controller in either 'text' or 'graphics' mode and then setting the following registers as indicated: SR04 =0Eh SR02 =0Fh GR05 =00h GR06 =04h (text mode) =05h (gr mode) XR0B =x5h To update the cursor position, a 32-bit write (or two 16-bit writes) are performed to the Cursor Position Register (DR0B). This new position will take effect on the next frame (synchronized to VSync). Sequencer Memory Mode Sequencer Plane Mask Graphics Controller Mode Graphics Controller Misc Graphics Controller Misc Paging Control When the cursor changes shape, it should normally be disabled, reprogrammed as described above, and then re-enabled. Alternately, a new shape may be stored in a different location in display memory, the cursor screen XY location updated (via DR0B), then the new cursor selected as the active cursor (by reprogramming the base register DR0C). Cursor base register changes are also synchronized to VSync to avoid glitching of the cursor on the display. This sets up the VGA controller to allow 32-bit direct access to all 4 planes of all 1MB of display memory in a linear fashion. It also sets the VGA memory aperture to a 64KB space at 0A0000h independent of initial graphics or text mode settings. Revision 1.2 AL, [SI+1] AH, [BX+1] EAX,16 AL, [SI] AH, [BX] 178 65540 / 545 (R) Flat Panel Timing Flat Panel Timing Overview A number of extension registers in the 65540 / 545 control the panel interface, including the functions of the interface pins and the timing sequences produced for compatibility with various types of panels. Some key registers of interest for panel interfacing are: Panel Size The horizontal panel size register (XR1C) is an 8-bit register programmed with panel width (minus one) in units of 8-pixel characters (e.g., a 640x480 panel is 80 'characters' wide so XR1C would be programmed with 79 decimal). The vertical panel size register is programmed with the panel height (minus one) in scan lines (independent of single or dual panel type). The programmed value is 10 bits in size with the 8 lsbs in XR68 and the overflow in XR65 bits 1 and 6. The maximum panel resolution supported is 2048 x 1024. XR1C H Panel Size (# of characters - 1) XR68 V Panel Size (# of scan lines - 1) bits 0-7 (XR65[1]=Vsize bit-8, XR65[6]=bit-9) XR4F XR50 XR51 XR53 XR54 XR5E XR6F Panel Format 2 (Bits/pixel,M/LP function) Panel Format 1 (FRC,dither,clkdiv,VAM) Display Type (Panel type,clk/LP control) Panel Format 3 (FRC opt,pixel packing) Panel Interface (FLM/LP Control) M (ACDCLK) Control Frame Buffer Control Panel Type The panel type (PT) is determined by XR51 bits 1-0: 00 11 This section summarizes the function of the various fields of the above registers as they pertain to panel interfacing. Detailed timing diagrams are shown for output of data and control sequences to a variety of panel types. The 65540 / 545 highly configurable controllers can interface to virtually all existing monochrome LCD, EL, and Plasma panels and all color LCD STN and TFT panels. The panel types supported are: Single panel-Single drive (SS) Dual panel-Double drive (DD) For DD panels, XR6F bit-0 (Frame Buffer Enable) and/or bit-1 (Frame Accelerator Enable) must also be set (either external or embedded may be used). TFT Panel Data Width XR50 bit-7 controls output width for TFT panels: 0 1 16-bit color TFT panel interface (565 RGB) 24-bit color TFT panel interface (888 RGB) Single panel-Single drive (SS) Monochrome 1 pixel/clock, 8 bits/pixel 2 pixels/clock, 8 bits/pixel 4 pixels/clock, 4 bits/pixel 8 pixels/clock, 2 bit/pixel 16 pixels/clock, 1 bit/pixel Dual panel-Double drive (DD) Monochrome 8 pixels/clock, 1 bit/pixel 16 pixels/clock, 1 bit/pixel Single panel-Single drive (SS) Color TFT 1 pixel/clock, 16 bit/pixel 5-6-5 RGB 1 pixel/clock, 24 bit/pixel 8-8-8 RGB 2 pixels/clock, 12 bit/pixel 4-4-4 RGB Single panel-Single drive (SS) Color STN 2 2/3 pixels/clock, 3 bit/pixel 1-1-1 RGB 5 1/3 pixels/clock, 3 bit/pixel 1-1-1 RGB Dual panel-Double drive (DD) Color STN 2 2/3 pixels/clock, 3 bit/pixel 1-1-1 RGB 5 1/3 pixels/clock, 3 bit/pixel 1-1-1 RGB Revision 1.2 179 65540 / 545 (R) Flat Panel Timing Display Quality Settings Gray / Color Levels Gray / color levels are selected via XR4F bits 2-0 (somewhat misleading called 'Bits Per Pixel'): No FRC # of msbs Used Gray / Gray / Color to Generate Color Levels with Gray/Color Levels Levels Dithering 001 1 2 5 010 2 4 13 011 3 8 29 100 4 16 61 101 5 32 125 110 6 64 253 111 8 256 n/a 2-Frame FRC (Color TFT or Monochrome Panels) # of msbs Used Gray / Gray / Color to Generate Color Levels with Gray/Color Levels Levels Dithering 010 1 3 9 011 2 5 25 100 3 15 57 101 4 31 121 16-Frame FRC (Color or Monochrome STN Panels) # of msbs Used Gray / Gray / Color to Generate Color Levels with Gray/Color Levels Levels Dithering 001 1 2 5 010 2 4 13 011 3 8 29 100 4 16 61 Frame Rate Control (FRC) The 65540 / 545 provides 2 and 16 level FRC to generate multiple gray / color levels. FRC selection is determined by XR50 bits 1-0: 00 No FRC 01 16-frame FRC (color or mono STN panels) 10 2-frame FRC (color TFT or mono panels) Three options are provided for FRC control: FRC option 1 (XR53[2]) (always set to 1) FRC option 2 (XR53[3]) (always set to 1) FRC option 3 (XR53[6]) (for 2-frame FRC only): 0 1 FRC data changes every frame FRC data changes every other frame A setting of 0 typically results in better display quality, but panels with an internal 'M' signal typically recommend this bit be set to 1 for longer panel life. XR6E is also provided for FRC polynomial control. The values of the 'm' and 'n' parameters are typically set by trial and error (recommended settings are given elsewhere in this manuals for selected panels as derived by Chips and Technologies). Dither The 65540 / 545 also provides Dither capability to generate multiple gray / color levels. Ditherselection is determined by XR50 bits 3-2: 00 No Dither 01 Enable Dither for 256-color modes only 10 Enable Dither for all modes The setting programmed into XR4F bits 0-2 above determines how many most-significant color-bits / pixel are used to generate flat panel video data. In general, 8 bits of monochrome data or 8 bits/color of RGB color data enter the flat panel logic for every dot clock. Not all of these bits, however, are used to generate output colors / gray scales, depending on the type of panel used, graphics / text mode, and the gray-scaling algorithm chosen (the actual number of bits used is indicated in the table above). Also note that settings which achieve higher gray / color levels may not necessarily produce acceptable display quality on some (or any) currently available panels. This document contains recommended settings for various popular panels that Chips & Technologies has found to produce acceptable results with those panels. Customers may modify these settings to achieve a better match with their requirements. M Signal Timing Register XR5E (M/ACDCLK Control) is provided to control the timing of the M (sometimes called ACDCLK) signal. XR5E bit-7 selects between two types of timing control: 0 1 Use XR5E bits 0-6 to determine M signal timing (bits 0-6 are programmed with the number of HSYNCs between phase changes minus 2) M phase changes every frame if the frame buffer is used, otherwise the phase changes every other frame XR4F bit-6 controls the M pin output. If set, the M pin will output flat panel BLANK# / Display Enable (DE) instead of the normal M signal (and XR5E will be ignored). Revision 1.2 180 65540 / 545 (R) Flat Panel Timing Pixels Per Shift Clock The 65540 / 545 can be programmed to output 1, 2, 4, 8, or 16 pixels per shift clock. This is achieved by programming the frequency ratio between the dot clock and the shift clock. The shift clock divide (CD) is set by XR50 bits 6-4. For monochrome panels, the valid settings are: The number of bits per pixel is determined as follows: 1bpp: Bits/Pixel=000 or 001 or 16-Frame FRC or 2-Frame FRC with Bits/Pixel=010 2bpp: Not 1bpp and CD=011 (8 Pixels/Clock) 4bpp: Not 1bpp and CD=010 (4 Pixels/Clock) 8bpp: Not 1bpp and CD=001 (2 Pixels/Clock) or Not 1bpp and CD=000 (1 Pixels/Clock) Pixels Per Pixels Per Shift Shift Clock Shift Clock Clock without Frm Acc with Frm Acc 000 Dot clk 1 2 001 Dclk / 2 2 4 010 Dclk / 4 4 8 011 Dclk / 8 8 16 100 Dclk / 16 16 n/a Pixels 8-Bit Valid 16-Bit Valid Per Shift Panel Outputs Panel Outputs Clock Interface (8-bit) Interface (16-bit) 1 8bpp P8-15 8bpp P8-15 2 4bpp P8-15 (8-11 1st) 8bpp P0-15 4 2bpp P8-15 (8-9 1st) 4bpp P0-15 8 1bpp P1,3,5,... (1 1st) 2bpp P0-15 16 n/a n/a 1bpp P0-15 The pixel on the lowest numbered output pin is always the first pixel output (the pixel shown first on the left side of the screen). For example, for 8 pixels per clock, 1bpp on an 8-bit interface, P1 is the first pixel, P3 is the second, etc. For 16 pixels per clock, 1bpp on a 16-bit interface, P0 is the first pixel, P1 is the second, etc. For 4 pixels per clock, 2bpp on an 8-bit interface, P8-9 is the first pixel, P10-11 is the second, etc. Valid Color TFT panel shift clock divide settings are: Pixels per TFT TFT "B0-n" "G0-n" "R0-n" Shift Output Output Panel Panel Panel Clock Width Format Outputs Outputs Outputs 000 1 16 5-6-5 P0-4 P5-10 P11-15 24 8-8-8 P0-7 P8-15 P16-23 001 2 24 4-4-4 P0-3 P8-11 P16-19 P4-7 P12-15 P20-23 For 2 pixels/shift clock, the first pixel output is on P0-3, 8-11, and 16-19. For Color STN, valid shift clock divide settings are: Pixels Per Clock Pixels Per Clock without with FrameAcceleration FrameAcceleration SS or DD Panels DD Panels Only 000 1 2 001 2 4 010 4 n/a For Color STN data, pixel output sequences are controlled by the 'Color STN Pixel Packing' bits (XR53[5-4]) described on the following page (packing may be selected as '3-Bit Pack', '4-Bit Pack', or 'Extended 4-Bit Pack' sometimes referred to in this document as 3bP, 4bP, and X4bP). All cases in the above table can use 3-Bit Pack or 4-Bit Pack. Extended 4-Bit Pack is only used for the single case of 2 pixels per shift clock without frame acceleration. Pixel Packing is not used for EL/Plasma, Monochrome DD, or Color TFT panels so the pixel packing bits should be set to 00 for all panels except color STN. Shift Clock Divide The above clock divide ('CD') bits (XR50 bits 6-4) affect both shift clock and data out. XR51[3] (Shift Clock Divide or SD) may be set so that only the shift clock (and not the video data) is further divided by two beyond the setting of XR50 bits 6-4. This has the effect of causing a new pixel to be output on every clock edge (i.e., both rising and falling) instead of just every falling clock edge (the first pixel output on every scan line will be on the rising edge). Extended 4-Bit Pack for Color STN panels requires that the SD bit (XR51[3]) be set to 1. In all other cases in the Color STN table above, either setting may be used. 24bit 24bit 16bit 8bit 16bit 16bit 16bit Color Color Color Mono Mono Mono Mono Pix/clk: 1 2 1 1 2 4 8 CD: 000 001 000 000 001 010 011 P0 B0n B4n B3n - G0n G4n G6n P1 B1n B5n B4n - G1n G5n G7n P2 B2n B6n B5n - G2n G4n+1 G6n+1 P3 B3n B7n B6n - G3n G5n+1 G7n+1 P4 B4n B4n+1 B7n G0n G0n+1 G4n+2 G6n+2 P5 B5n B5n+1 G2n G1n G1n+1 G5n+2 G7n+2 P6 B6n B6n+1 G3n G2n G2n+1 G4n+3 G6n+3 P7 B7n B7n+1 G4n G3n G3n+1 G5n+3 G7n+3 P8 G0n G4n G5n G0n G4n G6n G6n+4 P9 G1n G5n G6n G1n G5n G7n G7n+4 P10 G2n G6n G7n G2n G6n G6n+1 G6n+5 P11 G3n G7n R3n G3n G7n G7n+1 G7n+5 P12 G4n G4n+1 R4n G4n G4n+1 G6n+2 G6n+6 P13 G5n G5n+1 R5n G5n G5n+1 G7n+2 G7n+6 P14 G6n G6n+1 R6n G6n G6n+1 G6n+3 G6n+7 P15 G7n G7n+1 R7n G7n G7n+1 G7n+3 G7n+7 P16 R0n R4n - - - - - P17 R1n R5n - - - - - P18 R2n R6n - - - - - P19 R3n R7n - - - - - P20 R4n R4n+1 - - - - - P21 R5n R5n+1 - - - - - P22 R6n R6n+1 - - - - - P23 R7n R7n+1 - - - - - For information only, not recommended for panel connections Revision 1.2 181 65540 / 545 (R) Flat Panel Timing Color STN Pixel Packing ( Pixel Output Order ) For color STN panels, pixel packing must be selected via XR53 bits 5-4: Pixel output order for 4-Bit Pack 8-bit STN DD panels: Shift Clock Edge 1st 2nd 3rd 4th CD Settings Allowable SS: 000, 001, or 010 DD: 000, 001 (010 w/o FA) 01 4-Bit Pack SS: 000, 001, or 010 DD: 000, 001 (010 w/o FA) 11 Ext'd 4-Bit Pack SS: 001 (8bit panels only) 00 Packing 3-Bit Pack Upper: P0 R1 P1 G1 P2 B1 P3 R2 Lower: P4 R1 P5 G1 P6 B1 P7 R2 These settings are valid for color STN panels only (these bits must be set to 00 for monochrome and color TFT panels). P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P0 P1 P2 P3 P4 P5 P6 P7 CD=001 (2p/clk) CD=010 (4p/clk) Shift Clock Edge Shift Clock Edge 1st 2nd 3rd 4th 1st 2nd 3rd 4th ... ... R1 R3 R5 ... R1 R5 R9 ... G1 G3 G5 ... G1 G5 G9 ... B1 B3 B5 ... B1 B5 B9 ... - - - - - - R2 R4 R6 ... R2 R6 R10 ... G2 G4 G6 ... G2 G6 G10 ... B2 B4 B6 ... B2 B6 B10 ... - - - ... - - - R3 R7 R11 ... - - - G3 G7 G11 ... - - - B3 B7 B11 ... - - - - - - - - - R4 R8 R12 ... - - - G4 G8 G12 ... - - - B4 B8 B12 ... ... ... ... ... G2 B2 R3 G3 B3 R4 G4 B4 ... ... ... ... Pixel output order for 16-bit STN panels (4bit Pack): P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 4b Pack, CD=001 Ext'd 4b Pack, CD=001 Shift Clock Edge Shift Clock Edge 1st 2nd 3rd 4th 1st 2nd 3rd 4th 5th 6th 7th R1 B3 G6 ... R1 G1 G6 B6 B11 R12 ... G1 R4 B6 ... B1 R2 R7 G7 G12 B12 ... B1 G4 R7 ... G2 B2 B7 R8 R13 G13 ... R2 B4 G7 ... R3 G3 G8 B8 B13 R14 ... G2 R5 B7 ... B3 R4 R9 G9 G14 B14 ... B2 G5 R8 ... G4 B4 B9 R10 R15 G15 ... R3 B5 G8 ... R5 G5 G10 B10 B15 R16 ... G3 R6 B8 ... B5 R6 R11 G11 G16 B16 ... STN-SS Panels Shift Clock Edge 1st 2nd 3rd 4th R1 G6 B11 ... G1 B6 R12 ... B1 R7 G12 ... R2 G7 B12 ... G2 B7 R13 ... B2 R8 G13 ... R3 G8 B13 ... G3 B8 R14 ... B3 R9 G14 ... R4 G9 B14 ... G4 B9 R15 ... B4 R10 G15 ... R5 G10 B15 ... G5 B10R16 ... B5 R11G16 ... R6 G11B16 ... STN-DD Panels Shift Clock Edge 1st 2nd 3rd 4th Upper: P0 R1 P1 G1 P2 B1 P3 R2 P8 G2 P9 B2 P10 R3 P11 G3 Lower: P4 R1 P5 G1 P6 B1 P7 R2 P12 G2 P13 B2 P14 R3 P15 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 ... ... ... ... ... ... ... ... B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 ... ... ... ... ... ... ... ... For STN-SS panels the pixel sequence repeats with 16 pixels every 3 shift clock edges (5-1/3 pixels per shift clock edge). Clock divide must be set to 010. The pixel sequence for 3-bit Pack repeats with either 1, 2, or 4 pixels every shift clock edge depending on the setting of the clock divide (CD) field. The pixel sequence for 4-bit Pack repeats with 8 pixels every 3 shift clock edges. The sequence for Extended 4-Bit Pack repeats with 16 pixels every 6 shift clock edges. Extended 4-bit Pack is used only for 8-bit color STN-SS panels. It is not used for color STN DD panels or for 16-bit color STN interfaces. Revision 1.2 B3 R4 G4 B4 The pixel sequence repeats with 8 pixels (4 for each of the upper and lower panels) every 3 shift clock edges. Clock divide must be set to 000 with Frame Acceleration and 001 without Frame Acceleration. Pixel output order for 3-Bit Pack STN-SS panels without frame acceleration: CD=000 (1p/clk) ShfClk Edge 1st 2nd 3rd 4th - - - R1 R2 R3 ... G1 G2 G3 ... B1 B2 B3 ... - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - G2 B2 R3 G3 For STN-DD panels the pixel sequence repeats with 16 pixels (8 for each of the upper and lower panels) every 3 shift clock edges (2-2/3 pixels per shift clock edge per panel). Clock divide must be set to 001 with Frame Acceleration and 010 without Frame Acceleration. 182 65540 / 545 (R) Flat Panel Timing Output Signal Timing Pixel Timing Diagrams Pixel output timing sequences are shown for the following panel configurations: LP Signal Timing LP output polarity is controlled by XR54[6] (0=positive, 1=negative). Setting XR4F bit-7, however, causes the LP pin to output flat panel BLANK# / DE instead of the normal LP signal (and all other LP timing control parameters will be ignored). Some panels (e.g., Plasma and EL) require LP to be active during vertical blank time. XR51[7] may be set to enable this. Otherwise LP pulses are not generated during vertical blank. 1) SS Monochrome Plasma / EL Single Panel-Single Drive (Panel Type = 00) Plasma/EL Panel 2 pixels/shift clock, 4 bits/pixel (CD = 001) 2) DD Monochrome LCD Dual Panel-Double Drive (Panel Type = 11) Monochrome LCD Panel 8 pixels/shiftclk, 1bit/pixel, CD = 011 (010 with FB) 16 pixels/shiftclk, 1bit/pixel, CD = 100 (011 with FB) FLM Output Signal Timing FLM signal output polarity is controlled by XR54[7] (0=positive, 1=negative). BLANK# / DE Output Signal Timing The polarity of the BLANK# / DE output (if selected for output on M, LP, or FLM as indicated above) may be controlled by XR54[0] (0=positive, 1=negative). XR54[1] selects whether BLANK# / DE outputs both H and V (0) or just H (1). XR51[2] selects whether BLANK# / DE is generated from CRT Blank or Flat Panel Blank. 3) SS Color TFT LCD Single Panel-Single Drive (Panel Type = 00) Color TFT LCD Panel 4/5/6/8 bits/color/pixel (12/16/18/24 bits total) 1 pixel/shift clock, 16-bit 5-6-5 RGB, CD=000 1 pixel/shift clock, 24-bit 8-8-8 RGB, CD=000 2 pixels/shift clock, 24-bit 4-4-4 RGB, CD=001 SHFCLK Output Signal Timing XR51[5] (Shift Clock Mask or SM) may be set to force the shift clock output low outside the display enable interval. 4) SS Color STN LCD Single Panel-Single Drive (Panel Type = 00) Color STN LCD Panel 1 bit/color/pixel (3 bits total) 1-1-1 RGB 1 pixel/shiftclk (3bit), CD=000 2 pixels/shiftclk (6bit), CD=001 2-2/3 pixels/shift clock (8bit), CD=010 5-1/3 pixels/shift clock (8bit), CD=010, SD=1 5-1/3 pixels/shift clock (16bit), CD=010 5) DD Color STN LCD Dual Panel-Dual Drive (Panel Type = 11) Color STN LCD Panel All timings = 1 bit/color/pixel (3 bits total) RGB 2-2/3 pixels/shift clock (8-bit), CD=001 5-1/3 pixels/shift clock (16-bit), CD=010 Revision 1.2 183 65540 / 545 (R) Flat Panel Timing LP BLANK# SHFCLK 320 Clks / H 320 Clks / H 320 Clks / H (1,1)...(640,1) (1,2)...(640,2) (1,480)...(640,480) FLM P8-15 480 Data Transfer Cycles / V SHFCLK (Plasma) SHFCLK (EL ) P8 (1,1) -1 (3,1) -1 (637,1) -1 (639,1) -1 (637,480) (639,480) -1 -1 P9 (1,1) -2 (3,1) -2 (637,1) -2 (639,1) -2 (637,480) (639,480) -2 -2 P10 (1,1) -4 (3,1) -4 (637,1) -4 (639,1) -4 (637,480) (639,480) -4 -4 P11 (1,1) -8 (3,1) -8 (637,1) -8 (639,1) -8 (637,480) (639,480) -8 -8 P12 (2,1) -1 (4,1) -1 (638,1) -1 (640,1) -1 (638,480) (640,480) -1 -1 P13 (2,1) -2 (4,1) -2 (638,1) -2 (640,1) -2 (638,480) (640,480) -2 -2 P14 (2,1) -4 (4,1) -4 (638,1) -4 (640,1) -4 (638,480) (640,480) -4 -4 P15 (2,1) -8 (4,1) -8 (638,1) -8 (640,1) -8 (638,480) (640,480) -8 -8 EL panels use the rising edge of SHFCLK to clock in panel data, so the SHFCLK output from the 65540 / 545 must be inverted prior to driving the panel Panel Timing - Monochrome 16-Gray-Level EL / Plasma 8-Bit Interface Revision 1.2 184 65540 / 545 (R) Flat Panel Timing Panel Output Timing - 640 x 480 Monochrome DD 8-Bit (1 Bit / Pixel, 8 Pixels / Shift Clock) LP BLANK# SHFCLK 160 Clks / H (640 x 480) 160 Clks / H (640 x 480) 160 Clks / H (640 x 480) (1,1)...(640,1) (1,241)...(640,241) (1,2)...(640,2) (1,242)...(640,242) (1,240)...(640,240) (1,480)...(640,480) FLM P0-7 240 Data Transfer Cycles / V (640 x 480) Panel Output Pixel Order - 640 x 480 (No FA) DCLK (FA) DCLK SHFCLK (1,1) (5,1) (UD3) P0 (2,1) (6,1) (UD2) P1 (3,1) (7,1) (UD1) P2 (4,1) (8,1) (UD0) P3 (1,241) (5,241) (LD3) P4 (2,241) (6,241) (LD2) P5 (3,241) (7,241) (LD1) P6 (4,241) (8,241) (LD0) P7 (SHFCLK x 8) CD = 011 (SHFCLK x 4) CD = 010 (633,1) (637,1) (633,240) (637,240) (634,1) (638,1) (634,240) (638,240) (635,1) (639,1) (635,240) (639,240) (636,1) (640,1) (636,240) (640,240) (633,241) (637,241) (633,480) (637,480) (634,241) (638,241) (634,480) (638,480) (635,241) (639,241) (635,480) (639,480) (636,241) (640,241) (636,480) (640,480) FA = Frame Accelerator (Imbedded or External) Panel Timing - Monochrome LCD DD 8-Bit Interface Revision 1.2 185 65540 / 545 (R) Flat Panel Timing Panel Output Timing - 1024 x 768 Monochrome DD 16-Bit (1 Bit / Pixel, 16 Pixels / Shift Clock) LP BLANK# SHFCLK 256 Clks / H (1024 x 768) 256 Clks / H (1024 x 768) 256 Clks / H (1024 x 768) (1,1)...(1024,1) (1,385)...(1024,385) (1,2)...(1024,2) (1,386)...(1024,386) (1,384)...(1024,384) (1,768)...(1024,768) FLM P0-15 384 Data Transfer Cycles / V (1024 x 768) Pixel Output Pixel Order - 1024 x 768 (No FA) DCLK (FA) DCLK SHFCLK (1,1) (UD7) P0 (2,1) (UD6) P1 (3,1) (UD5) P2 (4,1) (UD4) P3 (5,1) (UD3) P4 (6,1) (UD2) P5 (7,1) (UD1) P6 (8,1) (UD0) P7 (1,385) (LD7) P8 (2,385) (LD6) P9 (3,385) (LD5) P10 (4,385) (LD4) P11 (5,385) (LD3) P12 (6,385) (LD2) P13 (7,385) (LD1) P14 (8,385) (LD0) P15 (SHFCLK x 16) CD = 100 (SHFCLK x 8) CD = 011 (9,1) (1009,384) (10,1) (11,1) (1010,384) (12,1) (1012,384) (13,1) (1013,384) (14,1) (1014,384) (15,1) (1015,384) (16,1) (1016,384) (9,385) (1009,768) (10,385) (1010,768) (11,385) (1011,768) (12,385) (1012,768) (13,385) (1013,768) (14,385) (1014,768) (15,385) (1015,768) (16,385) (1016,768) (1011,384) FA = Frame Accelerator (Embedded or External) Panel Timing - Monochrome LCD DD 16-Bit Interface Revision 1.2 186 65540 / 545 (R) Flat Panel Timing DCLK SHFCLK P0 B0(0) B1(0) B0(0) B2(0) P1 B0(1) B1(1) B0(1) B2(1) P2 B0(2) B1(2) B0(2) B2(2) P3 B0(3) B1(3) B1(0) B3(0) P4 B0(4) B1(4) B1(1) B3(1) P5 G0(0) G1(0) B1(2) B3(2) P6 G0(1) G1(1) G0(0) G2(0) P7 G0(2) G1(2) G0(1) G2(1) P8 G0(3) G1(3) G0(2) G2(2) P9 G0(4) G1(4) G1(0) G3(0) P10 G0(5) G1(5) G1(1) G3(1) P11 R0(0) R1(0) G1(2) G3(2) P12 R0(1) R1(1) R0(0) R2(0) P13 R0(2) R1(2) R0(1) R2(1) P14 R0(3) R1(3) R1(0) R3(0) P15 R0(4) R1(4) R1(1) R3(1) CD: FRC: Bits / Pixel: Pixel Format: DataWidth: 000 (1 Pixel / Clock) 10 (2 Frame) 110 (6 bits/pixel) 5-6-5 RGB 16-Bit 001 (2 Pixels / Clock) 10 (2-Frame) 011 (3 bits/pixel) 2-3-3 RGB 16-Bit Panels with 9 or 12-bit data interfaces would use this setting and only connect to the msbs of each color Panel Timing - Color LCD TFT 9 / 12 / 16-Bit Interface Revision 1.2 187 65540 / 545 (R) Flat Panel Timing DCLK SHFCLK P0 B0(0) B1(0) B0(0) B2(0) P1 B0(1) B1(1) B0(1) B2(1) P2 B0(2) B1(2) B0(2) B2(2) P3 B0(3) B1(3) B0(3) B2(3) P4 B0(4) B1(4) B1(0) B3(0) P5 B0(5) B1(5) B1(1) B3(1) P6 B0(6) B1(6) B1(2) B3(2) P7 B0(7) B1(7) B1(3) B3(3) P8 G0(0) G1(0) G0(0) G2(0) P9 G0(1) G1(1) G0(1) G2(1) P10 G0(2) G1(2) G0(2) G2(2) P11 G0(3) G1(3) G0(3) G2(3) P12 G0(4) G1(4) G1(0) G3(0) P13 G0(5) G1(5) G1(1) G3(1) P14 G0(6) G1(6) G1(2) G3(2) P15 G0(7) G1(7) G1(3) G3(3) P16 R0(0) R1(0) R0(0) R2(0) P17 R0(1) R1(1) R0(1) R2(1) P18 R0(2) R1(2) R0(2) R2(2) P19 R0(3) R1(3) R0(3) R2(3) P20 R0(4) R1(4) R1(0) R3(0) P21 R0(5) R1(5) R1(1) R3(1) P22 R0(6) R1(6) R1(2) R3(2) P23 R0(7) R1(7) R1(3) R3(3) CD: FRC: Bits / Pixel: Pixel Format: DataWidth: 000 (1 Pixel / Clock) 00 (no FRC) 111(8 bits/pixel) 8-8-8 RGB 24-Bit 001 (2 Pixels / Clock) 10 (2-Frame) 100/101 (4 or 5 bits/pixel) 4-4-4 RGB 24-Bit Panels with 18-bit data interfaces would use this setting and only connect to the msbs of each color Panel Timing - Color LCD TFT 18 / 24-Bit Interface Revision 1.2 188 65540 / 545 (R) Flat Panel Timing DCLK IDCLK IDCLK/2 SHFCLKU (Pin 70) SHFCLKL (Pin 81) P0 R1 G1 G6 B6 B11 R12 P1 B1 R2 R7 G7 G12 B12 P2 G2 B2 B7 R8 R13 G13 P3 R3 G3 G8 B8 B13 R14 P4 B3 R4 R9 G9 G14 B14 P5 G4 B4 B9 R10 R15 G15 P6 R5 G5 G10 B10 B15 R16 P7 B5 R6 R11 G11 G16 B16 PT: CD: FRC: Pixel Packing: Bits / Pixel: Frame Buffer / Acceleration: 00 (SS Panel) 010 (5-1/3 Pixels / Clock) 01 (16-Frame) 11 (Extended 4-Bit Pack) 100 (4 bits / pixel) Disabled / Disabled 16 Pixels are transferred every 16 dot clocks (6 shift clock edges) Panel Timing - Color LCD STN 8-Bit ( Extended 4-Bit Pack ) Interface Revision 1.2 189 65540 / 545 (R) Flat Panel Timing DCLK IDCLK SHFCLK (IDCLK/2) P0 R1 G6 B11 R17 G22 B27 P1 G1 B6 R12 G17 B22 R28 P2 B1 R7 G12 B17 R23 G28 P3 R2 G7 B12 R18 G23 B28 P4 G2 B7 R13 G18 B23 R29 P5 B2 R8 G13 B18 R24 G29 P6 R3 G8 B13 R19 G24 B29 P7 G3 B8 R14 G19 B24 R30 P8 B3 R9 G14 B19 R25 G30 P9 R4 G9 B14 R20 G25 B30 P10 G4 B9 R15 G20 B25 R31 P11 B4 R10 G15 B20 R26 G31 P12 R5 G10 B15 R21 G26 B31 P13 G5 B10 R16 G21 B26 R32 P14 B5 R11 G16 B21 R27 G32 P15 R6 G11 B16 R22 G27 B32 PT: CD: FRC: Pixel Packing: Bits / Pixel: Frame Buffer / Acceleration: 00 (SS Panel) 010 (5-1/3 Pixels / Clock) 01 (16-Frame) 01 (4-Bit Pack) 100 (4 bits / pixel) Disabled / Disabled Panel Pixel Timing - Color LCD STN 16-Bit ( 4-Bit Pack ) Interface Revision 1.2 190 65540 / 545 (R) Flat Panel Timing DCLK SHFCLK (IDCLK) P0 R(1,1) G(2,1) B(3,1) R(5,1) G(6,1) P1 G(1,1) B(2,1) R(4,1) G(5,1) B(6,1) P2 B(1,1) R(3,1) G(4,1) B(5,1) R(7,1) P3 R(2,1) G(3,1) B(4,1) R(6,1) G(7,1) P4 R(1,241) G(2,241) B(3,241) R(5,241) G(6,241) P5 G(1,241) B(2,241) R(4,241) G(5,241) B(6,241) P6 B(1,241) R(3,241) G(4,241) B(5,241) R(7,241) P7 R(2,241) G(3,241) B(4,241) R(6,241) G(7,241) PT: CD: FRC: Bits / Pixel: Pixel Packing: FrameBuffer/Acceleration: 11 (DD Panel) 000 (2-2/3 Pixels / Clock) 01 (16-Frame) 100 (4 bits/pixel) 01 (4-Bit Pack) Enabled/Enabled 8 Pixels (4 each for the upper and lower panels) are transferred every 4 Dot Clocks (3 Shift Clock Edges) Panel Pixel Timing - Color LCD STN-DD 8-Bit ( 4-Bit Pack ) Interface - With Frame Acceleration Revision 1.2 191 65540 / 545 (R) Flat Panel Timing DCLK IDCLK SHFCLK (IDCLK/2) P0 R(1,1) G(2,1) B(3,1) R(5,1) G(6,1) P1 G(1,1) B(2,1) R(4,1) G(5,1) B(6,1) P2 B(1,1) R(3,1) G(4,1) B(5,1) R(7,1) P3 R(2,1) G(3,1) B(4,1) R(6,1) G(7,1) P4 R(1,241) G(2,241) B(3,241) R(5,241) G(6,241) P5 G(1,241) B(2,241) R(4,241) G(5,241) B(6,241) P6 B(1,241) R(3,241) G(4,241) B(5,241) R(7,241) P7 R(2,241) G(3,241) B(4,241) R(6,241) G(7,241) PT: CD: FRC: Bits / Pixel: Pixel Packing: FrameBuffer/Acceleration: 11 (DD Panel) 001 (2-2/3 Pixels / Clock) 01 (16-Frame) 100 (4 bits/pixel) 01 (4-Bit Pack) Enabled/Disabled 8 Pixels (4 each for the upper and lower panels) are transferred every 8 Dot Clocks (3 Shift Clock Edges) Panel Pixel Timing - Color LCD STN-DD 8-Bit ( 4-Bit Pack ) Interface - Without Frame Acceleration Revision 1.2 192 65540 / 545 (R) Flat Panel Timing DCLK IDCLK SHFCLK (IDCLK /2) P0 R(1,1) B(3,1) G(6,1) R(9,1) B(11,1) P1 G(1,1) R(4,1) B(6,1) G(9,1) R(12,1) P2 B(1,1) G(4,1) R(7,1) B(9,1) G(12,1) P3 R(2,1) B(4,1) G(7,1) R(10,1) B(12,1) P4 R(1,241) B(3,241) G(6,241) R(9,241) B(11,241) P5 G(1,241) R(4,241) B(6,241) G(9,241) R(12,241) P6 B(1,241) G(4,241) R(7,241) B(9,241) G(12,241) P7 R(2,241) B(4,241) G(7,241) R(10,241) B(12,241) P8 G(2,1) R(5,1) B(7,1) G(10,1) R(13,1) P9 B(2,1) G(5,1) R(8,1) B(10,1) G(13,1) P10 R(3,1) B(5,1) G(8,1) R(11,1) B(13,1) P11 G(3,1) R(6,1) B(8,1) G(11,1) R(14,1) P12 G(2,241) R(5,241) B(7,241) G(10,241) R(13,241) P13 B(2,241) G(5,241) R(8,241) B(10,241) G(13,241) P14 R(3,241) B(5,241) G(8,241) R(11,241) B(13,241) P15 G(3,241) R(6,241) B(8,241) G(11,241) R(14,241) PT: CD: FRC: Pixel Packing: Bits / Pixel: Frame Buffer / Acceleration: 11 (DD Panel) 001 (5-1/3 Pixels / Clock) 01 (16-Frame) 01 (4-Bit Pack) 100 (4 bits / pixel) Enabled / Enabled 16 Pixels (8 each for the upper and lower panels) are transferred every 8 Dot Clocks (3 Shift Clock Edges) Panel Pixel Timing - Color LCD STN-DD 16-Bit ( 4-Bit Pack ) Interface - With Frame Acceleration Revision 1.2 193 65540 / 545 (R) Flat Panel Timing DCLK IDCLK IDCLK /2 SHFCLK (IDCLK /4) P0 R(1,1) B(3,1) G(6,1) P1 G(1,1) R(4,1) B(6,1) P2 B(1,1) G(4,1) R(7,1) P3 R(2,1) B(4,1) G(7,1) P4 R(1,241) B(3,241) G(6,241) P5 G(1,241) R(4,241) B(6,241) P6 B(1,241) G(4,241) R(7,241) P7 R(2,241) B(4,241) G(7,241) P8 G(2,1) R(5,1) B(7,1) P9 B(2,1) G(5,1) R(8,1) P10 R(3,1) B(5,1) G(8,1) P11 G(3,1) R(6,1) B(8,1) P12 G(2,241) R(5,241) B(7,241) P13 B(2,241) G(5,241) R(8,241) P14 R(3,241) B(5,241) G(8,241) P15 G(3,241) R(6,241) B(8,241) PT: CD: FRC: Pixel Packing: Bits / Pixel: FrameBuffer/Acceleration: 11 (DD Panel) 010 (5-1/3 Pixels / Clock) 01 (16-Frame) 01 (4-Bit Pack) 100 (4 bits / pixel) Enabled/Disabled 16 Pixels (8 each for the upper and lower panels) are transferred every 16 Dot Clocks (3 Shift Clock Edges) Panel Pixel Timing - Color LCD STN-DD 16-Bit (4-Bit Pack) Interface - Without Frame Acceleration Revision 1.2 194 65540 / 545 (R) Programming Programming and Parameters GENERAL PROGRAMMING HINTS values have a wide range of acceptable values. The 65540 / 545 also has the versatility to program an LP delay to aid in interfacing to panels with a wide variety of timing requirements. The values presented in this section make certain assumptions about the operating environment. The flat panel clock ('dot clock') is assumed to be generated by the internal clock synthesizer. The values programmed into the SmartMapTM control registers (XR61 and XR62) give a threshold of 3 with foreground and background shift of 3 but SmartMapTM is turned off. To enable it, set XR61 bit-0 = 1. The 65540 and 65545 provide programmability of the gray scaling algorithm by adjusting 'm' and 'n' polynomial values in extended register 6E. In order to program the 65540 / 545 for simultaneous display, two FLM signals are required. The first shorter FLM will match the normal FLM frequency as the data is displayed on the first half of the CRT display data. The second FLM will be longer to allow for the CRT blank time. The FLM delay is programmed in XR2C and should be equal to the CRT blank time -- FLM front porch -- FLM width. The horizontal parameter values presented here are the minimum required for each panel type. For high resolution panels, these parameters may be changed to suit the panel size. The horizontal values equal the number of characters clocks output per line. In dual drive panels this value includes both panels. Therefore, the horizontal values are double those expected. For flat panel types and sizes not presented here, start with the parameters for a panel that most closely resembles the target panel. Adjust the flat panel configuration registers as needed and adjust the horizontal and vertical parameters as needed. Adaption to a non-standard panel is usually a trial and error process. These parameters are recommended by Chips and Technologies, Inc. for the 65540 / 545. They have been tested on several different flat panel displays. Customers should feel free to test other register values to improve the screen appearance or to customize the 65540 / 545 for other flat panel displays. Due to pipelining of the horizontal counters, certain sync or blank values may result in no display. Generally, the horizontal blank start must equal the display end and the blank end must equal the horizontal total. The horizontal sync start and end Revision 1.2 195 65540 / 545 (R) Programming EXTENSION REGISTER VALUES The 65540 / 545 controller can be programmed for a wide variety of flat panels, compensation techniques and backwards compatibility. The following pages provide the following 65540 / 545 Extension Register Value tables: Extension Table Registers #1 Minimum #2 Additional Display Type Description Parameters for Initial Boot (Analog CRT VGA Mode) Parameters for Emulation Modes Panels #3 Additional 640x480 Monochrome LCD-DD (Panel Mode Only)...............Epson EG-9005F-LS Citizen G6481L-FF Sharp LM64P80 Sanyo LCM-6494-24NTK Hitachi LMG5364XUFC #4 Additional 640x480 Monochrome LCD-DD (Simultaneous Mode Display) #5 Additional #6 Additional 640x480 Color TFT LCD (Panel Mode Only) ..........................Hitachi TX26D02VC2AA Sharp LQ9D011 Toshiba LTM-09C015-1 640x480 Color TFT LCD (Simultaneous Mode Display) #7 Additional 640x480 Color STN-SS LCD - 4-Bit Pack ...............................Sanyo LM-CK53-22NEZ (Panel Mode & Simultaneous Mode Display) Sanyo LCM5327-24NAK Sanyo LCM5330 #8 Additional 640x480 Color STN-SS LCD - Extended 4-Bit Pack ...............Sharp LM64C031 #9 Additional 640x480 Color STN-DD LCD - 16-Bit Interface......................Sharp LM64C08P (Panel & Simultaneous Mode Display) Sanyo LCM5331-22NTK Hitachi LMG9721XUFC Toshiba TLX-8062S-C3X Optrex DMF-50351NC-FW #10 #11 Additional Additional 640x480 16 Internal Gray Scale Plasma....................................Matsushita S804 640x480 16 Internal Gray Scale EL ..........................................Sharp LJ64ZU50 Table #1 specifies the minimum Extension Register values required for the 65540 / 545 to boot to VGA mode on an analog CRT monitor. Table #2 specifies the additional Extension Register values required for emulation of EGA, CGA, MDA and Hercules backwards compatibility modes. The registers in Table #2 should be used in conjunction with the registers specified in Table #1. For registers listed in both tables, use the values in Table #2 (shown in bold text). Tables #3-11 specify the additional Extension Register values required to support various panels. The registers in Tables #3-11 should be used in conjunction with the registers specified in Table #1 (and optionally Table #2). For registers listed in more than one table, use the values in Tables #3-11 (shown in bold text). Revision 1.2 196 65540 / 545 (R) Programming Table #1 - Parameters for Initial Boot Initial Boot-Up Extension Register Values for VGA Display on an Analog CRT Monitor Register Value (in Hex) Register XR02 XR04 XR05 XR06 XR08 XR0B XR0C XR0D XR0E XR0F XR10 XR11 XR14 XR15 XR16 XR17 XR1E XR1F XR24 XR25 XR28 XR29 XR2B XR30 XR31 XR32 XR33 XR30 XR31 XR32 XR33 XR44 XR45 XR51 XR52 XR53 XR54 XR5F XR60 XR61 XR62 XR63 XR70 XR72 01 A1 00 00 00 00 00 00 80 10 00 00 00 00 00 00 00 00 12 59 80 4C 00 03 6B 3C 20 03 4E 59 00 10 00 63 40 00 32 06 88 2E 07 41 80 24 Comments CPU Interface Control 1 Memory Control 1 Memory Control 2 Palette Control Linear Addressing Base CPU Paging Start Address Top Auxiliary Offset Text Mode Control Software Flags 0 Single/Low Map High Map Emulation Mode Write Protect Vertical Overflow Horizontal Overflow Alternate Offset Virtual EGA Switch Alternate Max Scanline Horizontal Virtual Panel Size Video Interface Half Line Compare Software Flags 1 Clock Divide Control Clock M-Divisor Clock N-Divisor Clock Control Clock Divide Control Clock M-Divisor Clock N-Divisor Clock Control Software Flags 2 Software Flags 3 Display Type Power Down Control Panel Format 3 Panel Interface Power Down Mode Refresh Blink Rate Control SmartMapTM Control SmartMapTM Shift Parameter SmartMapTM Color Mapping Control Setup / Disable Control External Device I/O Note 1 Note 2 Note 2 (Initialize Memory Clock) (Initialize Memory Clock) (Initialize Memory Clock) (Initialize Memory Clock) (Initialize Clock 2) (Initialize Clock 2) (Initialize Clock 2) (Initialize Clock 2) Note 2 Note 2 Note: 1) Memory Control Register 1 is automatically re-programmed with the proper display memory configuration by the BIOS 2) The Software Flag Registers are used by the BIOS and should not be re-programmed Revision 1.2 197 65540 / 545 (R) Programming Table #2 - Parameters for Emulation Modes Extension Register Values for CRT-Only, Panel-Only, & Simultaneous CRT / Panel Display Register Value (in Hex) Register XR14 XR15 00 18 Comments Emulation Mode Write Protect EGA Emulation EGA Emulation Register Value (in Hex) Register XR14 XR15 XR18 XR19 XR1A XR1B XR1C XR1D XR1E XR7E 01 0D 27 2B A0 2D 28 10 14 30 Comments Emulation Mode Write Protect Alternate Horizontal Display Enable End Alternate Horizontal Retrace Start Alternate Horizontal Retrace End Alternate Horizontal Total Alternate Horizontal Blanking Start Alternate Horizontal Blanking End Alternate Offset CGA / Hercules Color Select Register Value (in Hex) Register XR14 XR15 XR7E 52 0D 0F Comments Emulation Mode Write Protect CGA / Hercules Color Select Register Value (in Hex) Register XR0D XR14 XR15 XR18 XR19 XR1A XR1B XR1C XR1D XR1E XR7E 02 52 0D 59 60 8F 6E 5C 31 16 0F CGA Emulation CGA Emulation CGA Emulation CGA Emulation CGA Emulation CGA Emulation CGA Emulation CGA Emulation CGA Emulation CGA Emulation MDA Emulation MDA Emulation MDA Emulation Comments Auxiliary Offset Emulation Mode Write Protect Alternate Horizontal Display Enable End Alternate Horizontal Retrace Start Alternate Horizontal Retrace End Alternate Horizontal Total Alternate Horizontal Blanking Start Alternate Horizontal Blanking End Alternate Offset CGA / Hercules Color Select Hercules Emulation Hercules Emulation Hercules Emulation Hercules Emulation Hercules Emulation Hercules Emulation Hercules Emulation Hercules Emulation Hercules Emulation Hercules Emulation Hercules Emulation Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 198 65540 / 545 (R) Programming Table #3 - Parameters for 640x480 Monochrome LCD-DD Panels (Panel Mode Only) Extension Register Values for Epson EG9005F-LS Citizen G6481L-FF Sharp LM64P80 Sanyo LCM-6494-24NTK Hitachi LMG5364XUFC Register Value (in Hex) Register XR06 XR19 XR1A XR1B XR1C XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5D XR5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F 02 57 19 59 4F 04 50 50 00 44 25 67 41 0C 3A E5 00 1B 00 84 00 8F 10 80 E4 07 E0 01 DF 00 26 1B Comments Palette Control Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 2 Panel Format 1 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Power Sequencing Delay FP Diagnostic M (ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Register Frame Buffer Control Disable Internal DAC Optimize for best display quality Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 199 65540 / 545 (R) Programming Table #4 - Parameters for 640x480 Monochrome LCD-DD Panels (Simultaneous Mode Display) Extension Register Values for Epson EG9005F-LS Citizen G6481L-FF Sharp LM64P80 Sanyo LCM-6494-24NTK Hitachi LMG5364XUFC Register Value (in Hex) Register XR19 XR1A XR1B XR1C XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5D XR5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F 55 00 5F 4F 21 50 50 00 44 25 67 41 0C 3A E5 00 1B 00 84 00 8F 10 80 0B 26 EA 0C DF 02 26 1B Comments Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 2 Panel Format 1 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Power Sequencing Delay FP Diagnostic M (ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Register Frame Buffer Control Optimize For LCD Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 200 65540 / 545 (R) Programming Table #5 - Parameters for 640x480 Color TFT Panels (Panel Mode Only) Extension Register Values for Hitachi TX26D02VC2AA Sharp LQ9D011 (set to accommodate the DE signal) Toshiba LTM-09C015-1 Register Value (in Hex) XR06 XR19 XR1A XR1B XR1C XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5D XR5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F C2 56 13 5F 4F 04 4F 4F 0F 44 02 C4 41 0C FA E5 00 1B 00 84 00 8F 10 80 01 26 DF 0C DF 02 BD 00 Register Comments Palette Control Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 1 Panel Format 2 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Power Sequencing Delay FP Diagnostic M(ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Frame Buffer Control Color Reduction Set to F9 for Toshiba color panels Optimize for best display quality Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 201 65540 / 545 (R) Programming Table #6 - Parameters for 640x480 Color TFT Panels ( Simultaneous Mode Display ) Extension Register Values for Hitachi TX26D02VC2AA Sharp LQ9D011 (set to accommodate the DE signal) Toshiba LTM-09C015-1 Register Value (in Hex) Register XR06 XR19 XR1A XR1B XR1C XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5D XR5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F C0 55 00 5F 4F 00 4F 4F 0F 44 02 C4 41 0C FA E5 00 1B 00 84 00 8F 10 80 0C 26 EA 0C DF 02 BD 00 Comments Palette Control Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 2 Panel Format 1 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Power Sequencing Delay FP Diagnostic M (ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Frame Buffer Control Color Reduction Set to F9 for Toshiba color panels Optimize for best display quality Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 202 65540 / 545 (R) Programming Table #7 - Parameters for 640x480 Color STN-SS Panels with 16-Bit Interface 4-Bit Pack (Panel & Simultaneous Mode Display) Extension Register Values for Sanyo LM-CK53-22NEZ Sanyo LCM5327-24NAK Sanyo LCM5330 Register Value (in Hex) Register XR06 XR19 XR1A XR1B XR1C XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR50 XR5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F C2 56 19 59 4F 04 5C 5C 5C 44 25 C4 41 1C 3A E5 00 1B 00 84 00 8F 10 80 E4 07 E1 02 DF 02 61 00 Comments Palette Control Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 1 Panel Format 2 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Power Sequencing Delay Panel Format 1 M (ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Frame Buffer Control C0 for Simultaneous Display 55 for Simultaneous Display 00 for Simultaneous Display 5F for Simultaneous Display 22 for Simultaneous Display 62 for Simultaneous Display 62 for Simultaneous Display 60 for Simultaneous Display 0B for Simultaneous Display 26 for Simultaneous Display EA for Simultaneous Display 0C for Simultaneous Display Optimize for best display quality Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 203 65540 / 545 (R) Programming Table #8 - Parameters for 640x480 Color STN-SS Panels with 8-Bit Interface (Extended 4-Bit Pack) Extension Register Values for Sharp LM64C031 Register Value (in Hex) Register XR06 XR19 XR1A XR1B XR1C XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5D XR5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F C2 56 00 59 4F 02 50 50 00 44 15 6C 41 3C 3A E5 00 1B 00 84 00 8F 10 80 E8 07 E1 02 DF 02 36 00 Comments Palette Control Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 2 Panel Format 1 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Power Sequencing Delay FP Diagnostic M (ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Frame Buffer Control C0 simultaneous mode 55 simultaneous mode 5F simultaneous mode 2B simultaneous mode 15 simultaneous mode 26 simultaneous mode EA simultaneous mode 0C simultaneous mode Optimize for best display quality Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 204 65540 / 545 (R) Programming Table #9 - Parameters for 640x480 Color STN-DD Panels with 16-Bit Interface with Frame Acceleration (Panel & Simultaneous Mode Display) Extension Register Values for Sharp LM64C08P Sanyo LCM5331-22NTK Hitachi LMG9721XUFC Toshiba TLX-8062S-C3X Optrex DMF-50351NC-FW Register Value (in Hex) Register XR06 XR19 XR1A XR1B XR1C XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5D XR5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F C2 57 19 59 4F 15 50 50 00 04 25 67 41 1C 3A E5 00 1B 00 1F 00 8F 10 80 0B 07 EA 0C DF 02 33 1B Comments Palette Control Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 1 Panel Format 2 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Replication Vertical Line Replication Power Sequencing Delay FP Diagnostic M (ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Frame Buffer Control 22 for no frame acceleration 9E for no frame acceleration 35 for no frame acceleration Optimize for best display quality. 9F for external frame buffer with frame acceleration. 99 for external frame buffer without frame acceleration. Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 205 65540 / 545 (R) Programming Table #10 - Parameters for 640x480 Plasma Panels with 16 Internal Gray Levels Extension Register Values for Matsushita S804 Register Value (in Hex) Register XR19 XR1A XR1B XR1C XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5D XR5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F 60 00 60 4F 04 62 6D 08 04 17 C4 41 0C 39 E5 00 1B 00 84 00 8F 10 80 0D 26 E8 0A DF 02 0D 00 Comments Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 1 Panel Format 2 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Power Sequencing Delay FP Diagnostic M (ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Frame Buffer Control Optimize for best display quality Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 206 65540 / 545 (R) Programming Table # 11 - Parameters for 640x480 EL Panels with 16 Internal Gray Levels Extension Register Values for Sharp LJ64ZU50 Register Value (in Hex) Register XR19 XR1A XR1B XR1C XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5D XR5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F 52 15 54 4F 0C 4F 4E 81 04 17 44 41 0C F9 E5 00 1B 00 84 00 8F 10 80 F0 07 E5 05 DF 02 9D 00 Comments Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 1 Panel Format 2 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Power Sequencing Delay FP Diagnostic M (ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Frame Buffer Control Optimize for best display quality Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 207 65540 / 545 (R) Programming Revision 1.2 208 65540 / 545 (R) Application Schematic Examples Application Schematic Examples This section includes schematic examples showing various 65540 / 65545 interfaces. The schematics are divided into into three main groups: 1) System Bus Interface * ISA (PC/AT) Bus * VL-Bus / 486 CPU-Direct Local Bus (1x Clock) * PCI Local Bus (16-bit) (32-bit) (32-bit) 2) Display Memory Interface 3) CRT / Panel / Video Interface To design a system around the 65540 or 65545, one schematic page would be selected from each of the groups above. Selection of a bus interface for the VGA controller is generally dictated by the type of bus and CPU available in the system. If performance is a concern, however, and a 386 or 486 CPU is being used, a local bus interface should be considered and linear addressing support should be implemented. Linear addressing improves performance in GUI environments such as WindowsTM by allowing the software used to access display memory (typically the Windows Driver) to be more efficient. Clock connections are shown as part of the bus interface diagrams. A 14.31818 MHz reference crystal is shown, although if a clean source of 14.31818 MHz is available in the system, it may be input on XTALI and the crystal would then not be required. Generally, 256Kx16 DRAMs would be used for display memory, although, if desired, the memory interface may be designed to use 256Kx4's instead. 256Kx16 DRAMs come in two types: one write enable (WE#) with two CAS# inputs (one for the high byte and one for the low byte) or one CAS# input with two write enables (one for the high byte and one for the low byte). Either variety of DRAM may be used (default is to the 2-CAS variety with a programming option in the 65540 / 545 to change the memory control outputs for compatibility with either type). CHIPS' BIOS is able to detect which type is connected and program the controller accordingly. It is also possible to lay out a PCB to allow either type to be used. The memory interface diagram also shows how to interface the 6554x to CHIPS' PC-Video products to provide live video overlay capability. An interface diagram is included showing connections to a standard CRT display. Panel interfaces, however, are not as standardized (generally every panel interface is different). To show how to interface to a wide variety of commonly available panels, the interface diagram in this section shows the connections used on CHIPS' DK (Development Kit) Printed Circuit Board from the 6554x chip to connectors defined by CHIPS on that board. In the following section of this document, examples are included showing connections from those DK board connectors to a number of typical panels. The DK board connectors are used to simplify evaluation of the 6554x with various panels; a real system would not typically use the connectors shown, but would instead interface directly to the connector(s) used by the panel manufacturer. Revision 1.2 209 65540 / 545 (R) Application Schematic Examples 207 203 14.31818 204 0.01uF MHz ALE 22 B28 AEN 31 A11 MEMR# 11 C09 IORD# 27 B14 RDY 24 A10 IOWR# 25 B13 MEMW# 23 C10 Use as ENABKL 54 53 Use as ACTI IRQ9 30 B04 Use as ROMCS# if required 29 LA23 28 C02 LA22 201 C03 LA21 200 C04 LA20 199 C05 A19 198 A12 A18 197 A13 A17 196 A14 A16 195 A15 A15 194 A16 A14 193 A17 A13 192 A18 A12 191 A19 A11 190 A20 A10 189 A21 A9 188 A22 A8 187 A23 A7 186 A24 A6 185 A25 A5 183 A26 A4 182 A27 A3 180 A28 A2 179 A29 RFSH# 10 B19 A1 21 A30 BHE# 32 C01 A0 43 A31 1 Circuit Example +5V = B3, B29, D16 2 6554x ISA Bus Interface 3 GND = B1, B10,B31,D18 4 5 NOTE: Additional data output drive may be enabled by programming 6 XR6C bit 3=0. 7 NOTE: The 6554x may be configured for ISA operation by connecting pin 8 146 (AA1/ISA#) to GND via a 4.7K resistor. 13 14 NOTE: Can use external 14.31818MHz oscillator into XTALI (with XTALO 15 not connected) by connecting pin 150 (AA5/OC#) to GND via a 16 4.7K resistor. 17 IOCS16# 18 D02 MEMCS16# 19 D01 ZWS# 20 B08 D15 33 C18 D14 34 C17 D13 35 C16 D12 36 C15 D11 37 C14 D10 38 C13 D09 40 C12 D08 41 C11 D07 44 A02 D06 45 A03 D05 46 A04 D04 47 A05 D03 48 A06 D02 49 A07 D01 50 A08 D00 51 A09 B02 Revision 1.2 RESET 33 ohm 210 RESET# (65545 Only) XTALI XTALO ISA Bus PCI Bus ADS# <ALE> "FRAME#" M/IO# <AEN> "PAR" W/R# <MEMR#> "IDSEL" LCLK (2XCLK) <IORD#> "STOP#" LRDY# <RDY> "TRDY#" LDEV# <IOWR#> "DEVSEL#" RRTN# (CRST) <MEMW#> "IRDY#" A27 (ENABKL) A26 (ACTI) A25 <IRQ> "SERR#" A24 <ROMCS#> "PERR#" A23 <LA23> "Reserved" A22 <LA22> "CLK" A21 <LA21> "Reserved" A20 <LA20> "Reserved" A19 <LA19> "Reserved" A18 <LA18> "Reserved" A17 <LA17> "Reserved" A16 <A16> "Reserved" A15 <A15> "Reserved" Bus A14 Interface <A14> "Reserved" A13 <A13> "Reserved" A12 Default <A12> "Reserved" A11 Names <A11> "Reserved" A10 Indicate <A10> "Reserved" A9 <A9> "Reserved" VL-Bus A8 "Reserved" or 1x/2x <A8> A7 486 CPU <A7> "Reserved" A6 <A6> "Reserved" Direct A5 Local Bus <A5> "Reserved" A4 <A4> "Reserved" A3 <A3> "Reserved" A2 <A2> "Reserved" BE3# <RFSH#> "C/BE3#" BE2# <A1> "C/BE2#" BE1# <BHE#> "C/BE1#" BE0# <A0> "C/BE0#" D31 <Reserved> "AD31" D30 <Reserved> "AD30" D29 <Reserved> "AD29" D28 <Reserved> "AD28" D27 <Reserved> "AD27" D26 <Reserved> "AD26" D25 <Reserved> "AD25" D24 <Reserved> "AD24" D23 <Reserved> "AD23" D22 <Reserved> "AD22" D21 <Reserved> "AD21" D20 <Reserved> "AD20" D19 <Reserved> "AD19" D18 <IOCS16#> "AD18" D17 <MCS16#> "AD17" D16 <ZWS#> "AD16" D15 <D15> "AD15" D14 <D14> "AD14" D13 <D13> "AD13" D12 <D12> "AD12" D11 <D11> "AD11" D10 <D10> "AD10" D9 <D9> "AD9" D8 <D8> "AD8" D7 <D7> "AD7" D6 <D6> "AD6" D5 <D5> "AD5" D4 <D4> "AD4" D3 <D3> "AD3" D2 <D2> "AD2" D1 <D1> "AD1" D0 <D0> "AD0" 65540 or 65545 65540 / 545 (R) Application Schematic Examples To Systems Logic SYSRESET# 486 S-Series 486DX/SX 196pin PQFP Cx486S/S2 ADS# CPU-145 CPU-S17 CPU-111 CPU-N16 MIO# CPU-120 CPU-N17 W/R# CPUCLK CPU-123 CPU-C3 RDY# CPU-133 CPU-F16 To Local Bus Control Logic A27 or ENABKL CPU-9 CPU-?? A26 or ACTI CPU-8 CPU-?? A25 CPU-7 CPU-?? A24 CPU-5 CPU-?? A23 CPU-4 CPU-S3 A22 CPU-3 CPU-Q7 A21 CPU-2 CPU-Q5 A20 CPU-193 CPU-Q8 A19 CPU-191 CPU-Q4 A18 CPU-189 CPU-R5 A17 CPU-183 CPU-Q3 A16 CPU-181 CPU-Q9 A15 CPU-180 CPU-R7 A14 CPU-178 CPU-S5 CPU-176 CPU-Q10 A13 A12 CPU-174 CPU-S7 CPU-172 CPU-R12 A11 CPU-165 CPU-S13 A10 CPU-163 CPU-Q11 A9 CPU-161 CPU-R13 A8 CPU-159 CPU-Q13 A7 CPU-158 CPU-S15 A6 CPU-154 CPU-Q12 A5 CPU-152 CPU-S16 A4 CPU-150 CPU-R15 A3 CPU-146 CPU-Q14 A2 CPU-113 CPU-F17 BE3# BE2# CPU-115 CPU-J15 BE1# CPU-116 CPU-J16 CPU-117 CPU-K15 BE0# D31 CPU-74 CPU-B8 D30 CPU-71 CPU-C9 D29 CPU-69 CPU-A8 D28 CPU-67 CPU-C8 D27 CPU-65 CPU-C6 D26 CPU-63 CPU-C7 D25 CPU-61 CPU-B6 D24 CPU-59 CPU-A6 D23 CPU-55 CPU-A4 D22 CPU-53 CPU-A2 D21 CPU-51 CPU-B2 D20 CPU-48 CPU-A1 D19 CPU-47 CPU-B1 D18 CPU-46 CPU-C2 D17 CPU-45 CPU-D3 D16 CPU-44 CPU-J3 D15 CPU-42 CPU-F3 D14 CPU-41 CPU-K3 D13 CPU-39 CPU-D2 D12 CPU-38 CPU-G3 D11 CPU-37 CPU-C1 D10 CPU-35 CPU-E3 D09 CPU-32 CPU-D1 D08 CPU-31 CPU-F2 D07 CPU-29 CPU-L3 D06 CPU-27 CPU-L2 D05 CPU-26 CPU-J2 D04 CPU-25 CPU-M3 D03 CPU-23 CPU-H2 D02 CPU-20 CPU-N1 D01 CPU-18 CPU-N2 D00 CPU-17 CPU-P1 Revision 1.2 RESET# VL-B42 14.31818 MHz ADS# VL-A45 VL-B44 M/IO# VL-B45 W/R# LCLK VL-B56 LRDY# VL-A48 LDEV# VL-A49 VL-B48 RDYRTN# A27 VL-B24 VL-A23 A26 A25 VL-B25 A24 VL-A25 VL-B26 A23 A22 VL-A26 A21 VL-B27 A20 VL-A28 A19 VL-B28 VL-A29 A18 A17 VL-B30 A16 VL-A30 A15 VL-B31 A14 VL-A31 A13 VL-B33 A12 VL-A32 A11 VL-B34 A10 VL-A33 A09 VL-B35 A08 VL-A34 A07 VL-B36 A06 VL-A36 A05 VL-B37 A04 VL-A37 A03 VL-B39 A02 VL-B40 BE3# VL-A44 BE2# VL-A42 BE1# VL-A41 BE0# VL-A39 D31 VL-A20 D30 VL-B19 D29 VL-A19 D28 VL-B18 D27 VL-A18 D26 VL-B17 D25 VL-A16 D24 VL-B16 D23 VL-A15 D22 VL-B15 D21 VL-A14 D20 VL-B13 D19 VL-A13 D18 VL-B12 D17 VL-A11 D16 VL-B11 D15 VL-A09 D14 VL-B10 D13 VL-A08 D12 VL-B08 D11 VL-A07 D10 VL-B07 D09 VL-A06 D08 VL-B05 D07 VL-A05 D06 VL-B04 D05 VL-A04 D04 VL-B03 D03 VL-A02 D02 VL-B02 D01 VL-A01 D00 VL-B01 211 207 203 204 22 31 11 27 24 25 23 54 53 30 29 28 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 183 182 180 179 10 21 32 43 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 33 34 35 36 37 38 40 41 44 45 46 47 48 49 50 51 RESET# (65545 Only) XTALI XTALO ISA Bus PCI Bus ADS# <ALE> "FRAME#" M/IO# <AEN> "PAR" W/R# <MEMR#> "IDSEL" LCLK (2XCLK) <IORD#> "STOP#" LRDY# <RDY> "TRDY#" LDEV# <IOWR#> "DEVSEL#" RRTN# (CRST) <MEMW#> "IRDY#" A27 (ENABKL) A26 (ACTI) A25 <IRQ> "SERR#" A24 <ROMCS#> "PERR#" A23 <LA23> "Reserved" A22 <LA22> "CLK" A21 <LA21> "Reserved" A20 <LA20> "Reserved" A19 <LA19> "Reserved" A18 <LA18> "Reserved" A17 <LA17> "Reserved" A16 <A16> "Reserved" A15 <A15> "Reserved" Bus A14 Interface <A14> "Reserved" A13 <A13> "Reserved" A12 Default <A12> "Reserved" A11 Names <A11> "Reserved" A10 Indicate <A10> "Reserved" A9 <A9> "Reserved" VL-Bus A8 "Reserved" or 1x/2x <A8> A7 486 CPU <A7> "Reserved" A6 <A6> "Reserved" Direct A5 Local Bus <A5> "Reserved" A4 <A4> "Reserved" A3 <A3> "Reserved" A2 <A2> "Reserved" BE3# <RFSH#> "C/BE3#" BE2# <A1> "C/BE2#" BE1# <BHE#> "C/BE1#" BE0# <A0> "C/BE0#" D31 <Reserved> "AD31" D30 <Reserved> "AD30" D29 <Reserved> "AD29" D28 <Reserved> "AD28" D27 <Reserved> "AD27" D26 <Reserved> "AD26" D25 <Reserved> "AD25" D24 <Reserved> "AD24" D23 <Reserved> "AD23" D22 <Reserved> "AD22" D21 <Reserved> "AD21" D20 <Reserved> "AD20" D19 <Reserved> "AD19" D18 <IOCS16#> "AD18" D17 <MCS16#> "AD17" D16 <ZWS#> "AD16" D15 <D15> "AD15" D14 <D14> "AD14" D13 <D13> "AD13" D12 <D12> "AD12" Circuit <D11> Example "AD11" D11 D10 6554x VL-Bus <D10>/ 486 "AD10" D9 <D9> Local "AD9" CPU Direct D8 <D8> "AD8" Bus Interface D7 <D7> "AD7" D6 <D6> "AD6" D5 <D5> "AD5" D4 <D4> "AD4" D3 <D3> "AD3" D2 <D2> "AD2" D1 <D1> "AD1" D0 <D0> "AD0" 65540 or 65545 65540 / 545 (R) Application Schematic Examples REQ# n/c GNT# n/c REQ64# n/c n/c ACK64# n/c n/c n/c n/c INTA# INTB# INTC# INTD# n/c PRSNT1# n/c PRSNT2# n/c Reserved n/c Reserved n/c Reserved n/c Reserved n/c Reserved n/c Reserved +V-I/O To +V-I/O 65545 +V-I/O IVcc +V-I/O +V-I/O Pins +5V +5V +5V +5V +5V +5V +5V +5V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +12V -12V NOTE: Can use external 14.31818MHz oscillator into XTALI (with XTALO not connected)by connecting pin 150 (AA5/OC#) to GND via a 4.7K resistor. CircuitExample 65545 Interface to PCI Local Bus Revision 1.2 PCI-B18 PCI-A17 PCI-A60 PCI-B60 PCI-A06 PCI-B07 PCI-A07 PCI-B08 PCI-B09 PCI-B11 PCI-A09 PCI-B10 PCI-A11 PCI-A14 PCI-B14 PCI-A19 PCI-A10 PCI-A16 PCI-B19 PCI-A59 PCI-B59 PCI-A05 PCI-B05 PCI-B06 PCI-A08 PCI-A61 PCI-B61 PCI-A62 PCI-B62 PCI-A21 PCI-B25 PCI-A27 PCI-B31 PCI-A33 PCI-B36 PCI-A39 PCI-B41 PCI-B43 PCI-A45 PCI-A53 PCI-B54 PCI-A02 PCI-B01 PCI-B03 PCI-B15 PCI-B17 PCI-A18 PCI-B22 PCI-A24 PCI-B28 PCI-A30 PCI-B34 PCI-A35 PCI-A37 PCI-B38 PCI-A42 PCI-B46 PCI-A48 PCI-B49 PCI-A56 PCI-B57 PCI-A15 RST# 14.318 MHz FRAME# PAR IDSEL STOP# TRDY# DEVSEL# IRDY# PCI-A34 PCI-A43 PCI-A26 PCI-A38 PCI-A36 PCI-B37 PCI-B35 Use as ACTI & ENABKL SERR# PCI-B42 PERR# PCI-B40 PCI-B16 PCI-B39 PCI-A41 PCI-A40 PCI-A12 PCI-B12 PCI-A13 PCI-B13 PCI-A50 PCI-B50 PCI-A51 PCI-B51 PCI-A01 PCI-B02 PCI-A03 PCI-B04 PCI-A04 PCI-B26 PCI-B33 PCI-B44 PCI-A52 PCI-B20 PCI-A20 PCI-B21 PCI-A22 PCI-B23 PCI-A23 PCI-B24 PCI-A25 PCI-B27 PCI-A28 PCI-B29 PCI-A29 PCI-B30 PCI-A31 PCI-B32 PCI-A32 PCI-A44 PCI-B45 PCI-A46 PCI-B47 PCI-A47 PCI-B48 PCI-A49 PCI-B52 PCI-B53 PCI-A54 PCI-B55 PCI-A55 PCI-B56 PCI-A57 PCI-B58 PCI-A58 CLK LOCK# SBO# SDONE Keyway Keyway Keyway Keyway Keyway Keyway Keyway Keyway TRST# TCK TMS TDO TDI C/BE3# C/BE2# C/BE1# C/BE0# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00 212 n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c 207 203 204 22 31 11 27 24 25 23 54 53 30 29 28 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 183 182 180 179 10 21 32 43 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 33 34 35 36 37 38 40 41 44 45 46 47 48 49 50 51 RESET# XTALI XTALO ISA Bus ADS# <ALE> M/IO# <AEN> W/R# <MEMR#> LCLK (2XCLK) <IORD#> LRDY# <RDY> LDEV# <IOWR#> RRTN# (CRST) <MEMW#> A27 (ENABKL) A26 (ACTI) A25 <IRQ> A24 <ROMCS#> A23 <LA23> A22 <LA22> A21 <LA21> A20 <LA20> A19 <LA19> A18 <LA18> A17 <LA17> Bus A16 Interface <A16> A15 <A15> A14 Default <A14> A13 Names <A13> A12 Indicate <A12> A11 VL-Bus <A11> A10 or 1x/2x <A10> A9 486 CPU <A9> A8 <A8> Direct A7 Local Bus <A7> A6 <A6> A5 <A5> A4 <A4> A3 <A3> A2 <A2> BE3# <RFSH#> BE2# <A1> BE1# <BHE#> BE0# <A0> D31 <Reserved> D30 <Reserved> D29 <Reserved> D28 <Reserved> D27 <Reserved> D26 <Reserved> D25 <Reserved> D24 <Reserved> D23 <Reserved> D22 <Reserved> D21 <Reserved> D20 <Reserved> D19 <Reserved> D18 <IOCS16#> D17 <MCS16#> D16 <ZWS#> D15 <D15> D14 <D14> D13 <D13> D12 <D12> D11 <D11> D10 <D10> D9 <D9> D8 <D8> D7 <D7> D6 <D6> D5 <D5> D4 <D4> D3 <D3> D2 <D2> D1 <D1> D0 <D0> 65545 PCI Bus "FRAME#" "PAR" "IDSEL" "STOP#" "TRDY#" "DEVSEL#" "IRDY#" "SERR#" "PERR#" "Reserved" "CLK" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "C/BE3#" "C/BE2#" "C/BE1#" "C/BE0#" "AD31" "AD30" "AD29" "AD28" "AD27" "AD26" "AD25" "AD24" "AD23" "AD22" "AD21" "AD20" "AD19" "AD18" "AD17" "AD16" "AD15" "AD14" "AD13" "AD12" "AD11" "AD10" "AD9" "AD8" "AD7" "AD6" "AD5" "AD4" "AD3" "AD2" "AD1" "AD0" 65540 / 545 (R) Application Schematic Examples J3 DK PCB Panel Connector The following bits effect the DRAM / PC-Video interface: XR04[1-0] 00 01 10 11 Display Int Ext Mem FB FB A&B A&B Opt A A Opt A&C A n/a ---- Reserved ---- XR6F[7] 0=FB in DRAMs A/B 1=FB in DRAM C XR6F[2] 0=Sym Addr (C) 1=Asym Addr (C) 0=Sym Addr (A/B) 1=Asym Addr (A/B) XR05[3] XR05[4] XR05[5] XR05[6] XR05[7] XR6C[4] XR6C[5] n/c n/c n/c VG1 2x Output Drive (A/B) 2x Output Drive (C) Revision 1.2 65 64 154 99 54 53 VB7 VB6 VB5 VB4 VB3 VB2 MAD15-0 AA8-0 RASA# (CASA#) CASAH# (WEAL#) CASAL# (WEAH#) WEA# OEAB# J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 J2-2 J2-4 J2-42 J2-44 J2-46 J2-48 J2-50 J2-6 J2-8 J2-10 J2-12 J2-14 J2-16 J2-11 J2-13 J2-18 J2-20 J2-22 J2-24 J2-26 J2-28 J2-23 J2-25 J2-30 J2-32 J2-34 J2-36 J2-38 J2-40 J2-35 J2-37 DRAM "C" Not Installed 16 / 18 / 24-Bit PC-Video 16 / 18 / 24-Bit TFT Panels No ACTI feature w/24-bit No ENABKL feature w/24-bit 26-bit VL-Bus address range with 18 / 24-bit PC-Video (up to 28-bit w/16-bit video) J2-1 J2-3 J2-41 J2-43 J2-45 J2-47 J2-49 Reserved n/c J2-5 J2-7 J2-9 J2 DK PCB PC-Video Connector J2-15 J2-17 J2-19 J2-21 J2-27 J2-29 J2-31 J2-33 J2-39 101 103 104 102 100 D15:0 A8:0 RAS 256K CU x16 CL DRAM WE OE DRAM "C" Optional Used for improving performance with color DD STN panels in simultaneous display mode (PC-Video port not available & panel interface limited to 16-bit when DRAM "C" is used) 123 125 126 124 D15:0 A8:0 RAS 256K CU x16 CL DRAM WE OE DRAM "B" Optional Provides additional 512KB embedded frame buffer & display memory 156 159 160 157 155 D15:0 A8:0 RAS 256K CU x16 CL DRAM WE OE DRAM "A" MBD15-0 RASB# (CASB#) CASBH# (WEBL#) CASBL# (WEBL#) WEB# (CFG8-0) VR7 VR6 VR5 VR4 VR3 VR2 VR1 VR0 VG7 VG6 VG5 VG4 VG3 VG2 VG1 VG0 VB7 VB6 VB5 VB4 VB3 VB2 VB1 VB0 VG7 VG6 VG5 VG4 VG3 VG2 PC-Video Port Enable 0=18-bit PC-Video 1=24-bit PC-Video 65540 / 545 Reserved Reserved HSYNC VSYNC KEY PCLK Reserved VR5 VR4 VR3 VR2 0=2C/1W (A/B) 1=1C/2W (A/B) 0=2C/1W (C) 1=1C/2W (C) HSYNC VSYNC (VR0) AA9 (VG0) CA9 (VB1) (A27) (GPIO1) ENABKL (VB0) (A26) (GPIO0) ACTI (VR5-2,VG7-2,VB7-2) MCD15-0 (VG1,P23-16) CA8-0 (KEY) RASC# (VR7) (CASC#) CASCH# (VR6) (WECL#) CASCL# (PCLK) (WECH#) WEC# (VR1) OEC# P23 P22 P21 P20 P19 P18 P17 P16 P23 P22 P21 P20 P19 P18 P17 P16 213 Circuit Example Display Memory / PC-Video Circuit Provides base 512KB embedded frame buffer & display memory 65540 / 545 (R) Application Schematic Examples J3 = DK PCB 50-Pin Connector SHFCLK (BLANK#) (DE) M (BLANK#) (DE) LP FLM 70 69 68 67 From System Power Control (Tie high if not used) n/c Panel Power Control Circuitry STNDBY# 178 ENAVDD (ENABKL) ENAVEE (GPIO1)* (A27) ENABKL (GPIO0)** (A26) ACTI SHFCLK M LP FLM DE (BLANK#) (DE) (BLANK#) (DE) 62 61 54 53 J5 = DK PCB 26-Pin Connector J3-13 J3-7 J3-10 J3-11 J3-8 SHFCLK M LP FLM DE J5-9 J5-1 J5-5 J5-3 J5-2 J3-4 J3-1 J3-3 J3-2 VDDSAFE VEESAFE 12VSAFE J5-6 J5-8 J5-12 J5-10 Circuitry Reserved VDDSAFE VEESAFE 12VSAFE ENABKL J3-5 ENABKL J5-4 To System Power Control Circuitry (Leave unconnected if not used) (P23) (P22) (P21) (P20) (P19) (P18) (P17) (P16) 65540 or 65545 FlatPanel VGAController CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 97 96 95 94 93 92 91 90 88 87 86 85 84 83 82 81 79 78 76 75 74 73 72 71 R 60 G 58 B 57 AVCC 59 RSET 55 AGND 56 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Rset 1% 22 uF J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 4.7 uH +5V P7 P6 P5 P4 P3 P2 P1 P0 (LD0) (LD1) (LD2) (LD3) (UD0) (UD1) (UD2) (UD3) 150, 2% FB HSYNC 65 (DDC1CLK)VSYNC 64 Note: DDC2CLK* 5V Digital Ground DDCDAT** Analog Ground 15K J5-19 J5-21 J5-23 J5-25 J5-11 J5-13 J5-15 J5-17 J1 = CRT Analog Video 15-Pin Connector FB R J1-1 G J1-2 B J1-3 RL J1-10 J1-5 0.1 0.047 270 Rset= 5.4* Rload Rload = R L * 75 R L + 75 For R L=75: Rset=202 For R L=150: Rset=270 J5-7 J5-14 J5-16 J5-18 J5-20 J5-22 J5-24 J5-26 5V 220pF HSYNC VSYNC .001uF n/c (MS3)ENABKL* (MS2) n/c (MS1)ACTI** (MS0) n/c J1-6 J1-7 J1-8 J1-13 J1-14 J1-9 J1-15 J1-4 J1-12 J1-11 65540 / 545 CRT / Panel Interface Circuit Revision 1.2 214 65540 / 545 (R) Panel Interface Examples Panel Interface Examples This section includes schematic examples showing how to connect the 65540 / 545 to various flat panel displays. Plasma / EL Panels Panel Panel Panel Panel Resolution Technology Drive Interface 640x480 Plasma SS 8-bit 640x480 EL SS 8-bit Panel Data Transfer 2 Pixels/Clk 2 Pixels/Clk Panel Gray Levels Page 16 217 16 218 Part Number EG-9005F-LS G6481L-FF LM64P80 LCM-6494-24NTK LMG5364XUFC Panel Panel Panel Panel Resolution Technology Drive Interface 640x480 LCD DD 8-bit 640x480 LCD DD 8-bit 640x480 LCD DD 8-bit 640x480 LCD DD 8-bit 640x480 LCD DD 8-bit Panel Data Transfer 8 Pixels/Clk 8 Pixels/Clk 8 Pixels/Clk 8 Pixels/Clk 8 Pixels/Clk Panel Gray Levels 2 2 2 2 2 Page 219 220 221 222 223 LCM-5491-24NAK ECM-A9071 1024x768 1024x768 LCD LCD 16 Pixels/Clk 16 Pixels/Clk 2 2 224 225 Part Number TM26D50VC2AA LQ9D011 LTM-09C015-1 LQ10D311 Panel Resolution 640x480 640x480 640x480 640x480 Panel Technology TFT LCD TFT LCD TFT LCD TFT LCD Panel Data Transfer 1 Pixel/Clk 1 Pixel/Clk 1 Pixel/Clk 1 Pixel/Clk Panel Colors 512 512 512 256K Page 226 227 228 229 LQ10DX01 1024x768 TFT LCD 2 Pixels/Clk 512 230 Mfr Part Number 1) Matsushita S804 2) Sharp LJ64ZU50 Monochrome LCD Panels 3) 4) 5) 6) 7) Mfr Epson Citizen Sharp Sanyo Hitachi 8) Sanyo 9) Epson Active Color Panels 10) 11) 12) 13) Mfr Hitachi Sharp Toshiba Sharp 14) Sharp Passive Color Panels Mfr 15) Sanyo 16) Sanyo 17) Sharp Part Number LM-CK53-22NEZ LCM5327-24NAK LM64C031 Panel Resolution 640x480 640x480 640x480 Panel Technology STN LCD STN LCD STN LCD 18) 19) 20) 21) 22) 23) 24) KCL6448 LMG9720XUFC LM64C08P LCM5331-22NTK LMG9721XUFC TLX-8062S-C3X DMF-50351NC-FW 640x480 640x480 640x480 640x480 640x480 640x480 640x480 STN LCD STN LCD STN LCD STN LCD STN LCD STN LCD STN LCD Kyocera Hitachi Sharp Sanyo Hitachi Toshiba Optrex DD DD 16-bit 16-bit Panel Panel Drive Interface SS 9-bit SS 9-bit SS 9-bit SS 18-bit SS 18-bit Panel Panel Panel Data Panel Drive Interface Transfer Colors SS 16-bit 5-1/3 Pixels/Clk 8 SS 16-bit 5-1/3 Pixels/Clk 8 SS 8-bit 2-2/3 Pixels/Clk 8 DD DD DD DD DD DD DD 8-bit 8-bit 16-bit 16-bit 16-bit 16-bit 16-bit 2-2/3 Pixels/Clk 2-2/3 Pixels/Clk 5-1/3 Pixels/Clk 5-1/3 Pixels/Clk 5-1/3 Pixels/Clk 5-1/3 Pixels/Clk 5-1/3 Pixels/Clk 8 8 8 8 8 8 8 Page 231 232 233 234 235 236 237 238 239 240 Glossary: SS = Single Panel Single Scan DD = Dual Panel Dual Scan TFT = Thin Film Transistor ('Active Matrix') STN = Super Twist Nematic ('Passive Matrix') Revision 1.2 215 65540 / 545 (R) Panel Interface Examples DEVELOPMENT KIT (DK) PRINTED CIRCUIT BOARD CONNECTOR SUMMARY DK6554x DK6554x Mono Mono Mono Color Color Color Color Color Color Color 6554x 6554x 26-Pin 50-Pin SS DD DD TFT TFT TFTHiRes STN STN STN DD STN DD Pin# Pin Name Connector Connector 8-bit 8-bit 16-bit 9/12/16-bit 18/24-bit 18/24-bit 8-bit 16-bit 8-bit 16-bit Pixels Transferred Per Shift Clock: 8 8 16 1 1 2 2-2/3 5-1/3 2-2/3 5-1/3 71 P0 17 15 - UD3 UD7 B0 B0 B00 R1... R1... UR1... UR1... 72 P1 15 16 - UD2 UD6 B1 B1 B01 B1... G1... UG1... UG1... 73 P2 13 18 - UD1 UD5 B2 B2 B02 G2... B1... UB1... UB1... 74 P3 11 19 - UD0 UD4 B3 B3 B03 R3... R2... UR2... UR2... 75 P4 25 21 - LD3 UD3 B4 B4 B10 B3... G2... LR1... LR1... 76 P5 23 22 - LD2 UD2 G0 B5 B11 G4... B2... LG1... LG1... 78 P6 21 24 - LD1 UD1 G1 B6 B12 R5... R3... LB1... LB1... 79 P7 19 25 - LD0 UD0 G2 B7 B13 B5... G3... LR2... LR2... 81 P8 - 27 P0 - LD7 G3 G0 G00 SHFCLKU B3... - UG2... 82 P9 - 28 P1 - LD6 G4 G1 G01 - R4... - UB2... 83 P10 - 30 P2 - LD5 G5 G2 G02 - G4... - UR3... 84 P11 - 31 P3 - LD4 R0 G3 G03 - B4... - UG3... 85 P12 - 33 P4 - LD3 R1 G4 G10 - R5... - LG2... 86 P13 - 34 P5 - LD2 R2 G5 G11 - G5... - LB2... 87 P14 - 36 P6 - LD1 R3 G6 G12 - B5... - LR3... 88 P15 - 37 P7 - LD0 R4 G7 G13 - R6... - LG3... 90 P16 - 39 - - - - R0 R00 - - - - 91 P17 - 40 - - - - R1 R01 - - - - 92 P18 - 42 - - - - R2 R02 - - - - 93 P19 - 43 - - - - R3 R03 - - - - 94 P20 - 45 - - - - R4 R10 - - - - 95 P21 - 46 - - - - R5 R11 - - - - 96 P22 - 48 - - - - R6 R12 - - - - 97 P23 - 49 - - - - R7 R13 - - - - 54/61 ENABKL 4 5 ENABKLENABKLENABKL ENABKL ENABKL ENABKL ENABKL ENABKLENABKLENABKL 70 SHFCLK 9 13 SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLKLSHFCLK SHFCLK SHFCLK 69 M 1 7 M M M M M M M M M M 68 LP 5 10 LP LP LP LP LP LP LP LP LP LP 67 FLM 3 11 FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM 68/69 DE 2 8 DE DE DE DE DE DE DE DE DE DE - VDDSAFE 6, 8 1 - - - - - - - - - - - +12VSAFE 10 2 - - - - - - - - - - - VEESAFE 12 3 - - - - - - - - - - - GND 7,14, 6,9,12,14, - - - - - - - - - - 16,18, 17,20,23,26, 20,22, 29,32,35,38, 24,26 41,44,47,50 M FLM LP GND SHFCLK UD0 UD1 UD2 UD3 LD0 LD1 LD2 LD3 J 1 3 5 7 9 11 13 15 17 19 21 23 25 [+5V] VDDSAFE VEESAFE ENABKL M 5 GND 2 DE FLM 4 ENABKL SHFCLK 6 VDDSAFE (+5V) P0 8 VDDSAFE (+5V) GND P3 10 +12 VSAFE P4 12 VEESAFE GND 14 GND P7 16 GND (-12V TO -45V) P8 18 GND or GND P11 20 GND (+12V TO +45V) P12 22 GND GND 24 GND P15 26 GND P16 GND P19 P20 DevelopmentBoard GND Panel Connectors P23 Revision 1.2 J3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 216 +12 VSAFE Reserved GND DE LP GND GND P1 P2 GND P5 P6 GND P9 P10 GND P13 P14 GND P17 P18 GND P21 P22 GND GND GND GND GND GND VR1 VR0 GND GND GND GND VG1 VG0 GND GND GND GND VB1 VB0 GND GND [Reserved] GND GND GND J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 [DPCLK] [BLANK#] VR7 VR6 VR5 VR4 VR3 VR2 VG7 VG6 VG5 VG4 Development VG3 Board VG2 PC-Video VB7 Connector VB6 VB5 VB4 VB3 VB2 HSYNC VSYNC KEY PCLK [Reserved] 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-1 J3-2 J3-3 n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 Parameter Panel Width Matsushita S804 Panel Height Panel Panel Type Connector Clock Divide (CD) 34 DISPTMG Shiftclk Div (SD) 27 GND Gray/Color Levels 25 GND TFT Data Width STN Pixel Packing 23 CLOCK# Frame Accel Ena 24 30 29 32 28 GND HSYNC GND VSYNC GND 14 18 22 26 7 11 15 19 DATA-E0 DATA-E1 DATA-E2 DATA-E3 DATA-O0 DATA-O1 DATA-O2 DATA-O3 n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND VDDSAFE (+5V) +12VSAFE VEESAFE (12 to 45) n/c n/c 1 3 NC NC Register XR1C XR65/68 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Value 4Fh 1DFh 00 001 0 100 0 00 0 Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] 0 XR2F[6] 0 XR2F/2D 062h XR2F/2E 06Dh XR2F[3-0] 8h XR54[6] 0 XR4F[7] 0 XR51[7] 1 XR2F[7] 0 XR2C 04h XR54[7] 0 XR54[0] 1 XR54[1] 0 XR51[2] 1 Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity GND GND GND GND GND GND GND GND GND Display Quality Recommendations FRC XR50[1-0] 00 FRC Option 1 XR53[2] 1 FRC Option 2 XR53[3] 1 FRC Option 3 XR53[6] 0 FRC Polynomial XR6E[7-0] Dither XR50[3-2] 01 31 33 +5V +5V 8 6 4 2 +12V +12V +12V +12V Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 n/a n/a Disabled 60h 00h 60h 20Dh 1E8h 0Ah 1 1 M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] 21 20 17 16 13 12 10 9 5 Comment (640 / 8) - 1 480 - 1 No FRC Set to 1 Set to 1 n/a n/a n/a 1 1 0 0 1 00h 000h Text Compression XR55[2] 1 AutoDoubling XR55[5] 1 Text Stretching XR57[2] 1 Text Stretch Mode XR57[4-3] 11 Stretching XR57[5] 0 Stretching Mode XR57[6] 0 Line Insertion Height XR59[3-0] 0Fh H/W Line Replication XR59[7] 0 Line Repl Height XR5A[3-0] 0 6554x Interface - Matsushita S804 ( 640x480 16-Gray Level Plasma Panel ) Revision 1.2 217 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-1 J3-2 J3-3 n/c n/c n/c SHFCLK GND LP (HS) n/c GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 Sharp LJ64ZU50 Panel Connector A8 H.D. B8 GND A7 B7 CKD GND A9 B9 V.D. GND A5 B5 A4 B4 A3 B3 A2 B2 D13 D12 D11 D10 D03 D02 D01 D00 n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND VDDSAFE (+5V) +12VSAFE VEESAFE (12 to 45) Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register XR1C XR65/68 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Value 4Fh 1DFh 00 001 0 100 0 00 0 Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] 0 0 04Fh 04Eh 01h 1 0 1 1 0Ch 1 1 0 1 Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] 52h 15h 54h 1F0h 1E5h 0Eh 1 1 Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] 00 FRC Option 1 XR53[2] 1 FRC Option 2 XR53[3] 1 FRC Option 3 XR53[6] 0 FRC Polynomial XR6E[7-0] Dither XR50[3-2] 01 M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] n/c A1 NC B10 A10 GND GND B12 A12 VL VL B13 A13 VD VD Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Comment (640 / 8) - 1 480 - 1 n/a n/a Disabled No FRC Set to 1 Set to 1 n/a n/a n/a 1 1 0 0 0 00h 000h Text Compression XR55[2] 1 AutoDoubling XR55[5] 1 Text Stretching XR57[2] 0 Text Stretch Mode XR57[4-3] 11 Stretching XR57[5] 0 Stretching Mode XR57[6] 0 Line Insertion Height XR59[3-0] 0Fh H/W Line Replication XR59[7] 0 Line Repl Height XR5A[3-0] 0 6554x Interface - Sharp LJ64ZU50 ( 640x480 16-Gray Level EL Panel ) Revision 1.2 218 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 n/c n/c n/c n/c n/c n/c n/c n/c J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 n/c n/c n/c n/c n/c n/c n/c n/c J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 Epson EG-9005F-LS Panel Connector 5 FR GND GND GND GND GND GND GND GND GND GND GND GND XSCL 4 7 8 LP YSCL DIN 15 16 17 18 11 12 13 14 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] n/c n/c VDDSAFE (+5V) +12VSAFE VEESAFE (12 to 45) 9 Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena -19V 10 6 NC NC 2 VSS 1 19 20 VDD EI EO 3 VLCD Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Epson EG-9005F-LS ( 640x480 Monochrome LCD DD Panel ) Revision 1.2 219 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 n/c n/c n/c n/c n/c n/c n/c n/c J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 n/c n/c n/c n/c n/c n/c n/c n/c J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-1 J3-2 J3-3 7 CP 8 LOAD 10 J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 Citizen G6481L-FF Panel Connector 9 DF GND GND GND GND GND GND GND GND GND GND GND GND 18 17 16 15 14 13 12 11 FRAME LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] n/c n/c n/c VDDSAFE (+5V) NC NC NC 3 VSS 5 4 DISPOFF# H AutoDoubling V Text Stretching VDD 1 2 VO VAA +12VSAFE VEESAFE (12 to 45) +28V Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] 6 19 20 Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering XR57[7] XR55[1] XR57[1] XR56 XR59/58 H Text Compression V V V V V V XR55[2] XR55[5] XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Citizen G6481L-FF ( 640x480 Monochrome LCD DD Panel ) Revision 1.2 220 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 n/c n/c n/c n/c n/c n/c n/c n/c J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 n/c n/c n/c n/c n/c n/c n/c n/c J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 Sharp LM64P80 Panel Connector CP2 2 CP1 1 S 12 13 14 15 8 9 10 11 GND GND GND GND GND GND GND GND GND GND GND GND DL0 DL1 DL2 DL3 DU0 DU1 DU2 DU3 Register XR1C XR65/68 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] 0 Enabled XR2F/2D 050h XR2F/2E 050h XR2F[3-0] 0h XR54[6] XR4F[7] 0 XR51[7] XR2F[7] 0 Enabled XR2C 04h 4 lines XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Value 4Fh 1DFh 11 010 100 0 0 1 Comment (640 / 8) - 1 480 - 1 DD Dclk / 4 16Level (61w/dith) n/a n/a Enabled 57h 19h 59h 1E4h 1E0h 1 1 Negative 1 Negative Display Quality Recommendations FRC XR50[1-0] 01 FRC Option 1 XR53[2] 1 FRC Option 2 XR53[3] 1 FRC Option 3 XR53[6] 0 FRC Polynomial XR6E[7-0] 26h Dither XR50[3-2] 01 16-Frame FRC Set to 1 Set to 1 n/a 256-color modes M Phase Change XR5E[7] 1 Every other frame M Phase Change Count XR5E[6-0] 00h n/a Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering VDDSAFE (+5V) +12VSAFE VEESAFE (12 to 45) 3 Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena -18V 6 VSS 5 4 VDD DISP 7 VEE H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 1 1 Enabled Enabled 0 0 1 00h 000h Enabled Disabled Enabled No left border No top border Text Compression XR55[2] 1 AutoDoubling XR55[5] 1 Text Stretching XR57[2] 0 Text Stretch Mode XR57[4-3] 11 Stretching XR57[5] 0 Stretching Mode XR57[6] 0 Line Insertion Height XR59[3-0] 0Fh H/W Line Replication XR59[7] 0 Line Repl Height XR5A[3-0] 0 Enabled Enabled Disabled DS+TF,TF,DS Disabled n/a 16 - 1 Disabled n/a 6554x Interface - Sharp LM64P80 ( 640x480 Monochrome LCD DD Panel ) Revision 1.2 221 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 n/c n/c n/c n/c n/c n/c n/c n/c J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 n/c n/c n/c n/c n/c n/c n/c n/c J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 Sanyo LCM-6494-24NTK Panel Connector CN2-18 M GND GND GND GND GND GND GND GND GND GND GND GND CN1-5 CL2 CN1-3 CL1 CN1-1 FLM Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity CN2-12 CN2-13 CN2-14 CN2-15 CN1-8 CN1-9 CN1-10 CN1-11 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 n/c n/c CN1-7 CN2-21 NC NC n/c CN2-24 VO CN2-20 CN2-19 CN1-6 CN1-4 CN1-2 VSS VSS VSS VSS VSS CN2-16 CN2-17 CN2-25 H AutoDoubling VDD V Text Stretching VDD DISPOFF# V Text Stretch Mode CN2-23 CN2-22 VEE VEE VDDSAFE (+5V) +12VSAFE VEESAFE (12 to 45) -23V Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering XR57[7] XR55[1] XR57[1] XR56 XR59/58 H Text Compression V V V V V XR55[2] XR55[5] XR57[2] XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Sanyo LCM-6494-24NTK ( 640x480 Monochrome LCD DD Panel ) Revision 1.2 222 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 n/c n/c n/c n/c n/c n/c n/c n/c J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 n/c n/c n/c n/c n/c n/c n/c n/c J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 Hitachi LMG5364XUFC Panel Connector 3 CP LOAD 1 FRAME 12 13 14 15 8 9 10 11 GND GND GND GND GND GND GND GND GND GND GND GND LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) XR51[5] LP Delay Disable XR2F[6] LP Delay (CMPR ena) XR2F/2D LP Delay (CMPR disa) XR2F/2E LP Pulse Width XR2F[3-0] LP Polarity XR54[6] LP Blank XR4F[7] LP Active during V XR51[7] FLM Delay Disable XR2F[7] FLM Delay XR2C FLM Polarity XR54[7] Blank#/DE Polarity XR54[0] Blank#/DE H-Only XR54[1] Blank#/DE CRT/FP XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering VDDSAFE (+5V) +12VSAFE 2 Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena n/c VEESAFE (12 to 45) -23V 6 VSS 5 4 H AutoDoubling VDD DISPOFF# V Text Stretching 7 VEE XR57[7] XR55[1] XR57[1] XR56 XR59/58 H Text Compression V V V V V V XR55[2] XR55[5] XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Hitachi LMG5364XUFC ( 640x480 Monochrome LCD DD Panel ) Revision 1.2 223 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c Sanyo LCM-5491-24NAK Panel Connector 2 M SHFCLK GND LP (HS) GND FLM (VS) GND 6 CL2 4 CL1 1 FLM J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 (LD0) (LD1) (LD2) (LD3) (LD4) (LD5) (LD6) (LD7) 17 18 19 20 21 22 23 24 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 (UD0) (UD1) (UD2) (UD3) (UD4) (UD5) (UD6) (UD7) 9 10 11 12 13 14 15 16 UD0 UD1 UD2 UD3 UD4 UD5 UD6 UD7 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 n/c n/c n/c n/c n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND Register Value Comment XR1C 7Fh (1024 / 8) - 1 XR65/68 2FFh 768 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] VDDSAFE (+5V) 26 27 5 8 VSS1 VSS1 VSS2 VSS2 25 VDD 28 29 VEE VEE +12VSAFE VEESAFE (12 to 45) Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena +36V Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Sanyo LCM-5491-24NAK ( 1024x768 LCD DD Panel ) Revision 1.2 224 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND Epson ECM-A9071 Panel Connector A8 XSCL A10 VSS A6 LP A5 VSS A7 DIN J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 (LD0) (LD1) (LD2) (LD3) (LD4) (LD5) (LD6) (LD7) B12 B13 B14 B15 B17 B18 B19 B20 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 (UD0) (UD1) (UD2) (UD3) (UD4) (UD5) (UD6) (UD7) B2 B3 B4 B5 B7 B8 B9 B10 UD0 UD1 UD2 UD3 UD4 UD5 UD6 UD7 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 n/c n/c n/c n/c n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register Value Comment XR1C 7Fh (1024 / 8) - 1 XR65/68 2FFh 768 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] VDDSAFE (+5V) +12VSAFE B1 B6 B11 B16 VSS VSS VSS VSS A3 A4 A9 VDD VDD DISP VEESAFE (12 to 45) +V A1 VDDH A2 VDDH Voltage not specified in panel data sheet; contact panel manufacturer for more information. Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Epson A9071 ( 1024x768 LCD DD Panel ) Revision 1.2 225 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 (R4) (R3) (R2) (R1) (R0) (G5) (G4) (G3) J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 (G2) (G1) (G0) (B4) (B3) (B2) (B1) (B0) J3-1 J3-2 J3-3 n/c SHFCLK GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 n/c n/c Hitachi TM26D50VC2AA Panel Connector 15 DTMG 16 GND 21 20 19 25 17 18 DCLK GND HSYNC GND VSYNC GND n/c n/c n/c n/c n/c n/c n/c n/c R3 R2 R1 R0 6 7 8 G3 G2 G1 9 G0 n/c n/c n/c 10 11 12 13 B3 B2 B1 B0 30 31 32 VR1 VR2 VR3 n/c GND GND GND GND GND GND GND GND GND GND GND GND n/c n/c n/c VDDSAFE (+5V) +12VSAFE 2 3 4 5 n/c VEESAFE (12 to 45) -24V 29 14 DOTE HREV 1 22 GND GND 23 24 28 VDD VDD BLC 26 27 VEE VEE Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register XR1C XR65/68 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Value 4Fh 1DFh 00 000 0 100 0 00 0 Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] 0 0 04Fh 04Fh 0Fh 1 0 1 0 04h 1 1 1 1 Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] 56h 13h 5Fh 201h 1DFh 5h 1 1 Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] 10 FRC Option 1 XR53[2] 1 FRC Option 2 XR53[3] 1 FRC Option 3 XR53[6] 0 FRC Polynomial XR6E[7-0] Dither XR50[3-2] 01 M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Comment (640 / 8) - 1 480 - 1 n/a n/a Disabled Set to 1 Set to 1 n/a n/a n/a 1 1 0 0 0 00h 000h Text Compression XR55[2] 1 AutoDoubling XR55[5] 1 Text Stretching XR57[2] 1 Text Stretch Mode XR57[4-3] 11 Stretching XR57[5] 0 Stretching Mode XR57[6] 0 Line Insertion Height XR59[3-0] 0Fh H/W Line Replication XR59[7] 0 Line Repl Height XR5A[3-0] 0 6554x Interface - Hitachi TM26D50VC2AA ( 640x480 512-Color TFT LCD Panel ) Revision 1.2 226 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 (R4) (R3) (R2) (R1) (R0) (G5) (G4) (G3) J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 (G2) (G1) (G0) (B4) (B3) (B2) (B1) (B0) J3-1 J3-2 J3-3 n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 Sharp LQ9D011 Panel Connector CN2-5 ENAB CN1-8 GND CN1-1 CN1-2 CN1-3 CN1-8 CN1-4 CN1-12 CK GND HSYNC GND VSYNC GND CN1-7 CN1-6 CN1-5 R2 R1 R0 CN1-11 CN1-10 CN1-9 G2 G1 G0 n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c CN1-15 CN1-14 CN1-13 n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND Register XR1C XR65/68 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Value 4Fh 1DFh 00 000 0 100 0 00 0 Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] 0 0 04Fh 04Fh 0Fh 1 0 1 0 04h 1 1 1 1 Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] 56h 13h 5Fh 201h 1DFh 5h 1 1 Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] 10 FRC Option 1 XR53[2] 1 FRC Option 2 XR53[3] 1 FRC Option 3 XR53[6] 0 FRC Polynomial XR6E[7-0] Dither XR50[3-2] 01 M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] n/c VDDSAFE (+5V) +12VSAFE B2 B1 B0 Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena n/c CN2-6 TST CN2-3 CN2-4 GND GND CN2-1 CN2-2 VCC VCC VEESAFE (12 to 45) n/c Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Comment (640 / 8) - 1 480 - 1 n/a n/a Disabled Set to 1 Set to 1 n/a n/a n/a 1 1 0 0 0 00h 000h Text Compression XR55[2] 1 AutoDoubling XR55[5] 1 Text Stretching XR57[2] 1 Text Stretch Mode XR57[4-3] 11 Stretching XR57[5] 0 Stretching Mode XR57[6] 0 Line Insertion Height XR59[3-0] 0Fh H/W Line Replication XR59[7] 0 Line Repl Height XR5A[3-0] 0 6554x Interface - Sharp LQ9D011 ( 640x480 512-Color TFT LCD Panel ) Revision 1.2 227 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c SHFCLK GND LP (HS) n/c GND FLM (VS) n/c GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 n/c n/c n/c n/c n/c n/c n/c n/c J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 (R4) (R3) (R2) (R1) n/c (R0) n/c (G5) (G4) (G3) J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 (G2) (G1) (G0) (B4) (B3) (B2) (B1) (B0) J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 Toshiba LTM-09C015-1 Panel Connector CN2-7 ENAB GND CN1-1 CN1-2 NCLK GND CN1-6 GND CN1-12 GND CN1-7 CN1-5 CN1-3 R2 R1 R0 CN1-13 CN1-11 CN1-9 G2 G1 G0 n/c n/c n/c CN2-5 CN2-3 CN2-1 B2 B1 B0 n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND n/c VDDSAFE (+5V) +12VSAFE CN1-8 n/c CN1-15 NC CN2-8 CN2-6 GND GND CN1-14 GND CN1-10 CN1-4 GND GND CN2-4 CN2-2 GND GND CN2-9 VDD CN2-10 VDD VEESAFE (12 to 45) n/c Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register XR1C XR65/68 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Value 4Fh 1DFh 00 000 0 100 0 00 0 Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] 0 0 04Fh 04Fh 0Fh 1 0 1 0 04h 1 1 0 Reqd for this panel 1 Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] 56h 13h 5Fh 201h 1DFh 5h 1 1 Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] 10 FRC Option 1 XR53[2] 1 FRC Option 2 XR53[3] 1 FRC Option 3 XR53[6] 0 FRC Polynomial XR6E[7-0] Dither XR50[3-2] 01 M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Comment (640 / 8) - 1 480 - 1 n/a n/a Disabled Set to 1 Set to 1 n/a n/a n/a 1 1 0 0 0 00h 000h Text Compression XR55[2] 1 AutoDoubling XR55[5] 1 Text Stretching XR57[2] 1 Text Stretch Mode XR57[4-3] 11 Stretching XR57[5] 0 Stretching Mode XR57[6] 0 Line Insertion Height XR59[3-0] 0Fh H/W Line Replication XR59[7] 0 Line Repl Height XR5A[3-0] 0 6554x Interface - Toshiba LTM-09C015-1 ( 640x480 512-Color TFT LCD Panel ) Revision 1.2 228 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-1 J3-2 J3-3 n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 Sharp LQ10D311 Panel Connector CN2-5 ENAB n/c n/c GND CN1-1 CN1-2 CN1-3 CN1-8 CN1-4 CN1-12 CK GND HSYNC GND VSYNC GND CN1-7 CN1-6 CN1-5 CN3-3 CN3-2 CN3-1 R5 R4 R3 R2 R1 R0 CN1-11 CN1-10 CN1-9 CN3-7 CN3-6 CN3-5 G5 G4 G3 G2 G1 G0 CN1-15 CN1-14 CN1-13 CN3-11 CN3-10 CN3-9 B5 B4 B3 B2 B1 B0 CN3-14 CN3-13 CN3-12 CN2-6 TST TST TST TST n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND n/c n/c n/c n/c VDDSAFE (+5V) +12VSAFE CN2-4 n/c CN3-8 CN3-4 CN2-3 GND GND GND CN2-1 CN2-2 VCC VCC VEESAFE (12 to 45) n/c Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Sharp LQ10D311 ( 640x480 256K-Color TFT LCD Panel ) Revision 1.2 229 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c n/c n/c Sharp LQ10DX01 Panel Connector CN2-2 CK CN2-1 GND CN2-4 HSYNC CN2-3 GND CN2-6 VSYNC CN2-5 GND SHFCLK GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 (even pixel red msb) PNL22 PNL21 (even pixel red lsb) PNL20 n/c PNL19 (odd pixel red msb) PNL18 PNL17 (odd pixel red lsb) PNL16 n/c CN1-7 CN1-6 CN1-5 R12 R11 R10 CN1-4 CN1-3 CN1-2 R02 R01 R00 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 (even pixel green msb) PNL14 PNL13 (even pixel green lsb) PNL12 n/c PNL11 (odd pixel green msb) PNL10 PNL9 (odd pixel green lsb) PNL8 n/c CN1-14 CN1-13 CN1-12 G12 G11 G10 CN1-11 CN1-10 CN1-9 G02 G01 G00 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 CN1-21 CN1-20 CN1-19 B12 B11 B10 CN1-18 CN1-17 CN1-16 B02 B01 B00 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 (even pixel blue msb) (even pixel blue lsb) n/c (odd pixel blue msb) (odd pixel blue lsb) n/c GND GND GND GND GND GND GND GND GND GND GND GND Register Value Comment XR1C 7Fh (1024 / 8) - 1 XR65/68 2FFh 768 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] n/c n/c VDDSAFE (+5V) +12VSAFE Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena +5V n/c VEESAFE (12 to 45) n/c Use separate +12V source, not +12VSAFE (sequenced), for panel VDD (panel VDD +12V must be active before panel VCC) CN2-8 CN2-7 TEST2 TEST1 CN1-1 CN1-8 CN1-15 GND GND GND CN2-13 CN2-14 CN2-15 CN2-9 VCC VCC VCC TEST3 CN2-10 CN2-11 CN2-12 VDD VDD VDD Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Sharp LQ10DX01 ( 1024x768 512-Color TFT LCD Panel ) Revision 1.2 230 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND Sanyo LM-CK53-22NEZ (LCM 5330) Panel Connector 29 M n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND 25 CL2 27 CL1 30 FLM J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 (R6...) (B5...) (G5...) (R5...) (B4...) (G4...) (R4...) (B3...) 15 23 14 22 13 21 12 20 LD0 UD0 LD1 UD1 LD2 UD2 LD3 UD3 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 (G3...) (R3...) (B2...) (G2...) (R2...) (B1...) (G1...) (R1...) 11 19 10 18 9 17 8 16 LD4 UD4 LD5 UD5 LD6 UD6 LD7 UD7 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 n/c n/c n/c n/c n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] n/c VDDSAFE (+5V) 1 NC 26 24 VSS VSS 6 5 GND GND 7 28 VDD DISP +12VSAFE VEESAFE (12 to 45) +38V VO 4 3 VEE VEE Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Sanyo LM-CK53-22NEZ ( LCM 5330 ) ( 640x480 Color STN LCD Panel ) Revision 1.2 231 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK/DE# M (ACDCLK) GND n/c n/c n/c Sanyo LCM-5327-24NAK Panel Connector 2 M SHFCLK GND LP (HS) GND FLM (VS) GND 6 CL2 4 CL1 1 FLM J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 (R6...) (B5...) (G5...) (R5...) (B4...) (G4...) (R4...) (B3...) 16 8 17 9 18 10 19 11 LD0 UD0 LD1 UD1 LD2 UD2 LD3 UD3 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 (G3...) (R3...) (B2...) (G2...) (R2...) (B1...) (G1...) (R1...) 20 12 21 13 22 14 23 15 LD4 UD4 LD5 UD5 LD6 UD6 LD7 UD7 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 n/c n/c n/c n/c n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND VDDSAFE (+5V) +12VSAFE n/c VEESAFE (12 to 45) +36V Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] 26 27 5 8 VSS1 VSS1 VSS2 VSS2 25 3 VDD DISPOFF 28 29 VEE VEE Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Sanyo LCM5327-24NAK ( 640x480 Color STN LCD Panel ) Revision 1.2 232 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c n/c SHFCLK (SCL) GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 n/c n/c n/c n/c n/c n/c n/c n/c J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 (SCH) n/c n/c n/c n/c n/c n/c n/c J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 Sharp LM64C031 Panel Connector 3 XCKL 2 LP 1 YD 4 (B5...) (R5...) (G4...) (B3...) (R3...) (G2...) (B1...) (R1...) 17 16 15 14 13 12 11 10 GND GND GND GND GND GND GND GND GND GND GND GND XCKU D7 D6 D5 D4 D3 D2 D1 D0 Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] n/c VDDSAFE (+5V) +12VSAFE 5 NC 18 9 7 VSS VSS VSS 6 VDD 8 VEE n/c VEESAFE (12 to 45) +32V Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Sharp LM64C031 ( 640x480 Color STN LCD Panel ) Revision 1.2 233 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND SHFCLK GND LP (HS) GND FLM (VS) GND 6 30 8 28 1 35 J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 n/c n/c n/c n/c n/c n/c n/c n/c J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 n/c n/c n/c n/c n/c n/c n/c n/c J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 Kyocera KCL6448 Panel Connector 10 DF 26 DF n/c n/c n/c (LR2...) (LB1...) (LG1...) (LR1...) (UR2...) (UB1...) (UG1...) (UR1...) 5 4 3 2 31 32 33 34 GND GND GND GND GND GND GND GND GND GND GND GND LD0 LD1 LD2 LD3 HD0 HD1 HD2 HD3 Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering VDDSAFE (+5V) +12VSAFE CP CP LOAD LOAD FRM FRM Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena n/c VEESAFE (12 to 45) n/c 18 GND 27 9 7 29 VDD VDD DISP# DISP# H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Kyocera KCL6448 ( 640x480 Color STN-DD LCD Panel ) Revision 1.2 234 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 n/c n/c n/c n/c n/c n/c n/c n/c J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 n/c n/c n/c n/c n/c n/c n/c n/c J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 Hitachi LMG9720XUFC Panel Connector 3 CL2 CL1 1 FLM 12 13 14 15 8 9 10 11 GND GND GND GND GND GND GND GND GND GND GND GND LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering VDDSAFE (+5V) +12VSAFE 2 Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena n/c VEESAFE (12 to 45) +27V 6 VSS 5 4 H AutoDoubling VDD DISPOFF# V Text Stretching 7 VEE XR57[7] XR55[1] XR57[1] XR56 XR59/58 H Text Compression V V V V V V XR55[2] XR55[5] XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Hitachi LMG9720XUFC ( 640x480 Color STN-DD LCD Panel ) Revision 1.2 235 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND Sharp LM64C08P Panel Connector CN1-3 XCK CN1-2 LP CN1-1 YD J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 (LG3...) (LR3...) (LB2...) (LG2...) (UG3...) (UR3...) (UB2...) (UG2...) CN2-17 CN2-18 CN2-19 CN2-20 CN1-8 CN1-9 CN1-10 CN1-11 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 (LR2...) (LB1...) (LG1...) (LR1...) (UR2...) (UB1...) (UG1...) (UR1...) CN2-21 CN2-22 CN2-23 CN2-24 CN1-12 CN1-13 CN1-14 CN1-15 DL4 DL5 DL6 DL7 DU4 DU5 DU6 DU7 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 n/c n/c n/c n/c n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] 0BAh ** Important ** Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] VDDSAFE (+5V) +12VSAFE Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena n/c VEESAFE (12 to 45) +25V CN1-6 CN2-1 CN2-10 CN2-16 CN2-25 VSS VSS VSS VSS VSS CN1-5 CN1-4 VDD DISP CN1-7 VEE Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Sharp LM64C08P ( 640x480 Color STN-DD LCD Panel ) Revision 1.2 236 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND Sanyo LCM-5331-22NTK Panel Single Dual Connector Connector (Panel Spec) (Prototypes) 29 CN1-2 M 25 26 27 24 30 CN1-6 CN1-7 CN1-4 CN1-5 CN1-1 J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 15 14 13 12 23 22 21 20 CN2-16 CN2-17 CN2-18 CN2-19 CN1-8 CN1-9 CN1-10 CN1-11 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 11 10 9 8 19 18 17 16 CN2-20 CN2-21 CN2-22 CN2-23 CN1-12 CN1-13 CN1-14 CN1-15 LD4 LD5 LD6 LD7 UD4 UD5 UD6 UD7 J3-1 J3-3 J3-2 n/c n/c n/c n/c n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND +12VSAFE LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] n/c VDDSAFE (+5V) VEESAFE (12 to 45) Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] CL2 VSS CL1 Output Signal Timing VSS Shift Clock Mask (SM) XR51[5] XR2F[6] FLM LP Delay Disable PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena +30V Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] 1 NC 28 DISPOFF# Fast Centering Disable H AutoCentering V AutoCentering H Centering VSS V Centering 6 5 CN2-26 CN2-25 7 CN2-24 VDD H AutoDoubling 3 4 CN2-27 CN2-28 VEE V VEE V 2 CN2-29 VO VSS XR57[7] XR55[1] XR57[1] XR56 XR59/58 H Text Compression V V V V V XR55[2] XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Sanyo LCM-5331-22NTK ( 640x480 Color STN-DD LCD Panel ) Revision 1.2 237 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 GND GND GND GND GND GND GND GND GND GND GND GND CN1-2 CL1 CN1-1 FLM CN2-6 CN2-7 CN2-8 CN2-9 CN2-1 CN2-2 CN2-3 CN2-4 LD4 LD5 LD6 LD7 UD4 UD5 UD6 UD7 CN1-12 CN1-13 CN1-14 CN1-15 CN1-8 CN1-9 CN1-10 CN1-11 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 n/c n/c n/c n/c n/c n/c n/c n/c PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 Hitachi LMG9721XUFC Panel Connector CN1-3 CL2 Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] CN2-10 CN2-5 CN1-6 VSS VSS VSS Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H J3-1 CN1-5 VDD V DISPOFF# V CN1-4 +12VSAFE n/c J3-2 V V VEESAFE (12 to 45) +V J3-3 CN1-7 VEE V Voltage not specified in panel data sheet; contact panel manufacturer V V VDDSAFE (+5V) for more information. XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Hitachi LMG9721XUFC ( 640x480 Color STN-DD LCD Panel ) Revision 1.2 238 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND Toshiba TLX-8062S-C3X Panel Connector CN1-3 SCP CN1-2 LP CN1-1 FP J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 CN2-2 CN2-3 CN2-4 CN2-5 CN1-8 CN1-9 CN1-10 CN1-11 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 CN2-6 CN2-7 CN2-8 CN2-9 CN1-12 CN1-13 CN1-14 CN1-15 LD4 LD5 LD6 LD7 UD4 UD5 UD6 UD7 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 n/c n/c n/c n/c n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] VDDSAFE (+5V) +12VSAFE Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena n/c VEESAFE (12 to 45) +24.5V CN2-10 CN2-1 CN1-6 GND GND GND CN1-5 CN1-4 VDD DISP CN1-7 VEE Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering H H V V V V V V V XR57[7] XR55[1] XR57[1] XR56 XR59/58 Text Compression XR55[2] AutoDoubling XR55[5] Text Stretching XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Toshiba TLX-8062S-C3X ( 640x480 Color STN-DD LCD Panel ) Revision 1.2 239 65540 / 545 (R) Panel Interface Examples DK6554x PCB Connector J3-5 J3-4 J3-8 J3-7 J3-6 J3-13 J3-14 J3-10 J3-9 J3-11 J3-12 Programming Recommendations/Requirements ENABKL Reserved BLANK#/DE M (ACDCLK) GND n/c n/c n/c n/c SHFCLK GND LP (HS) GND FLM (VS) GND Optrex DMF-50351NC-FW Panel Connector CN1-3 CP CN1-2 LP CN1-1 FLM J3-49 J3-48 J3-46 J3-45 J3-43 J3-42 J3-40 J3-39 PNL23 PNL22 PNL21 PNL20 PNL19 PNL18 PNL17 PNL16 J3-37 J3-36 J3-34 J3-33 J3-31 J3-30 J3-28 J3-27 PNL15 PNL14 PNL13 PNL12 PNL11 PNL10 PNL9 PNL8 CN2-2 CN2-3 CN2-4 CN2-5 CN1-8 CN1-9 CN1-10 CN1-11 DL0 DL1 DL2 DL3 DU0 DU1 DU2 DU3 J3-25 J3-24 J3-22 J3-21 J3-19 J3-18 J3-16 J3-15 PNL7 PNL6 PNL5 PNL4 PNL3 PNL2 PNL1 PNL0 CN2-6 CN2-7 CN2-8 CN2-9 CN1-12 CN1-13 CN1-14 CN1-15 DL4 DL5 DL6 DL7 DU4 DU5 DU6 DU7 J3-17 J3-20 J3-23 J3-26 J3-29 J3-32 J3-35 J3-38 J3-41 J3-44 J3-47 J3-50 J3-1 J3-2 J3-3 n/c n/c n/c n/c n/c n/c n/c n/c GND GND GND GND GND GND GND GND GND GND GND GND Register Value Comment XR1C 4Fh (640 / 8) - 1 XR65/68 1DFh 480 - 1 XR51[1-0] XR50[6-4] XR51[3] XR4F[2-0] XR50[7] XR53[5-4] XR6F[1] Output Signal Timing Shift Clock Mask (SM) LP Delay Disable LP Delay (CMPR ena) LP Delay (CMPR disa) LP Pulse Width LP Polarity LP Blank LP Active during V FLM Delay Disable FLM Delay FLM Polarity Blank#/DE Polarity Blank#/DE H-Only Blank#/DE CRT/FP XR51[5] XR2F[6] XR2F/2D XR2F/2E XR2F[3-0] XR54[6] XR4F[7] XR51[7] XR2F[7] XR2C XR54[7] XR54[0] XR54[1] XR51[2] Alt Alt Alt Alt Alt Alt Alt Alt XR19 XR1A XR1B XR65/64 XR65/66 XR67[3-0] XR55[6] XR55[7] Hsync Start (CR04) Hsync End (CR05) H Total (CR00) V Total (CR06) Vsync Start (CR10) Vsync End (CR11) Hsync Polarity Vsync Polarity Display Quality Recommendations FRC XR50[1-0] FRC Option 1 XR53[2] FRC Option 2 XR53[3] FRC Option 3 XR53[6] FRC Polynomial XR6E[7-0] Dither XR50[3-2] M Phase Change XR5E[7] M Phase Change Count XR5E[6-0] Compensation Typical Settings H Compensation XR55[0] V Compensation XR57[0] VDDSAFE (+5V) +12VSAFE Parameter Panel Width Panel Height Panel Type Clock Divide (CD) Shiftclk Div (SD) Gray/Color Levels TFT Data Width STN Pixel Packing Frame Accel Ena n/c VEESAFE (12 to 45) +V Fast Centering Disable H AutoCentering V AutoCentering H Centering V Centering CN2-10 CN2-1 CN1-6 VSS VSS VSS CN1-5 CN1-4 H AutoDoubling VCC DISPOFF# V Text Stretching CN1-7 VEE Voltage not specified in panel data sheet; contact panel manufacturer for more information. XR57[7] XR55[1] XR57[1] XR56 XR59/58 H Text Compression V V V V V V XR55[2] XR55[5] XR57[2] Text Stretch Mode XR57[4-3] Stretching XR57[5] Stretching Mode XR57[6] Line Insertion Height XR59[3-0] H/W Line Replication XR59[7] Line Repl Height XR5A[3-0] 6554x Interface - Optrex DMF-50351NC-FW ( 640x480 Color STN-DD LCD Panel ) Revision 1.2 240 65540 / 545 (R) Electrical Specifications Electrical Specifications 65540 / 545 ABSOLUTE MAXIMUM CONDITIONS Symbol PD VCC VI VO TOP TSTG Parameter Power Dissipation Supply Voltage Input Voltage OutputVoltage OperatingTemperature(Ambient) StorageTemperature Min - - 0.5 - 0.5 - 0.5 - 25 - 40 Typ - - - - - - Max 1 7.0 VCC+0.5 VCC+0.5 85 125 Units W V V V C C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions described under Normal Operating Conditions. 65540 / 545 NORMAL OPERATING CONDITIONS Symbol VCC VCC TA Parameter Supply Voltage (5V 10%) Supply Voltage (3.3V 10%) Ambient Temperature Min 4.5 3.1 0 65540 / 545 DAC CHARACTERISTICS Symbol Parameter VO OutputVoltage IO Output Current Full Scale Error DAC to DAC Correlation DACLinearity Full Scale Settling Time Rise Time Glitch Energy ComparatorSensitivity Typ 5 3.3 - Max 5.5 3.6 70 Units V V C (Under Normal Operating Conditions Unless Noted Otherwise) Notes IO 10 mA VO 1V @ 37.5 Load 10% to 90% Min 1.5 21 - - 2 - - - - Typ - - - 1.27 - - - - 50 Max - - 5 - - 28 6 200 - Units V mA % % LSB nS nS pVsec mV Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 11/11/93 241 65540 / 545 (R) Electrical Specifications 65540 / 545 DC CHARACTERISTICS (Under Normal Operating Conditions Unless Noted Otherwise) Symbol Parameter Notes Min Typ Max Units ICCDE Power Supply Current 0C, 5.5V, 68 MHz, DAC on, 65540 - 180 230 mA ICCDO Power Supply Current 0C, 5.5V, 68 MHz, DAC off, 65540 - 140 200 mA ICCDO Power Supply Current 0C, 3.3V, 62 MHz, DAC off, 65540 - 78 132 mA ICCDE Power Supply Current 0C, 5.5V, 68 MHz, DAC on, 65545 - TBD TBD mA ICCDO Power Supply Current 0C, 5.5V, 68 MHz, DAC off, 65545 - TBD TBD mA ICCDO Power Supply Current 0C, 3.3V, 56 MHz, DAC off, 65545 - TBD TBD mA ICCS Power Supply Current 0C, 5.5V, Standby, 65540 - - 200 A ICCS Power Supply Current 0C, 5.5V, Standby, 65545 - - TBD A IIL Input Leakage Current - 100 - +100 uA IOZ Output Leakage Current High Impedance - 100 - +100 uA IOZ Output Leakage Current High Impedance - 100 - +100 uA VIL Input Low Voltage All input pins - 0.5 - 0.8 V VOL Output Low Voltage Under max load per table below (5V) - - 0.5 V VOL Output Low Voltage Under max load per table below (3.3V) - - 0.5 V VOH Output High Voltage Under max load per table below (5V) VCC- 0.5 - - V VOH Output High Voltage Under max load per table below (3.3V) 2.4 - - V VIH Input High Voltage All pins except XTALI 2.0 - VCC+0.5 V VIH Input High Voltage All pins except XTALI 2.0 - VCC+0.5 V 65540 / 545 DC DRIVE CHARACTERISTICS (Under Normal Operating Conditions Unless Noted Otherwise) Symbol Parameter OutputPins IOL Output Low Drive H/VSYNC, LDEV#, LRDY#, ROMCS#, IRQ FLM, LP, M, P0-15, SHFCLK, D0-31 ENAVEE, ENAVDD, ENABKL, ACTI RASA#, CASAH/L#, WEA#, PAR (65545 only) RASB#, CASBH/L#, WEB#, OEAB#, AA0-9 RASC#, CASCH/L#, WEC#, OEC#, CA0-9 All other outputs IOH Output High Drive H/VSYNC, LDEV#, LRDY#, ROMCS#, IRQ FLM, LP, M, P0-15, SHFCLK, D0-31 ENAVEE, ENAVDD, ENABKL, ACTI RASA#, CASAH/L#, WEA#, PAR (65545 only) RASB#, CASBH/L#, WEB#, OEAB#, AA0-9 RASC#, CASCH/L#, WEC#, OEC#, CA0-9 All other outputs DCTestConditions VOUT=VOL, VCC=4.5V VOUT=VOL, VCC=4.5V VOUT=VOL, VCC=4.5V VOUT=VOL, VCC=4.5V VOUT=VOL, VCC=4.5V VOUT=VOL, VCC=4.5V VOUT=VOL, VCC=4.5V VOUT=VOH, VCC=4.5V VOUT=VOL, VCC=4.5V VOUT=VOH, VCC=4.5V VOUT=VOH, VCC=4.5V VOUT=VOH, VCC=4.5V VOUT=VOH, VCC=4.5V VOUT=VOH, VCC=4.5V Min Units 12 mA 8 mA 8 mA 4 mA 4 mA 4 mA 2 mA 12 mA 8 mA 8 mA 4 mA 4 mA 4 mA 2 mA Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Note: Standby power was measured using Self Refresh DRAMs with all chip inputs driven to inactive levels and outputs not connected (or connected to typical external loads). Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 242 65540 / 545 (R) Electrical Specifications 65540 / 545 AC TEST CONDITIONS (Under Normal Operating Conditions Unless Noted Otherwise) Output Output Capacitive LowVoltage HighVoltage Load VOL 2.4V 80pF VOL 2.4V 50pF VOL 2.4V 30pF OutputPins All 12mA and 8mA outputs plus PAR for PCI bus in the 65545 All Other 4mA output pads All Other 2mA output pads 65540 / 65545 AC TIMING CHARACTERISTICS - REFERENCE CLOCK Symbol FREF TREF THI /TREF Parameter Reference Frequency Reference Clock Period Reference Clock Duty Cycle Notes (100 ppm) 1/FREF Min Typ Max Units 1 14.31818 60 MHz 16.6 69.84128 1000 nS 25 - 75 % TREF THI Reference Clock Input Reference Clock Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 243 65540 / 545 (R) Electrical Specifications 65540 / 545 AC TIMING CHARACTERISTICS - CLOCK GENERATOR Symbol Parameter TC VCLK Period (5V) TC VCLK Period (3.3V) TCH VCLK High Time TCL VCLK Low Time TM MCLK Period (5V) TM MCLK Period (3.3V) TMH MCLK High Time TML MCLK Low Time TRF Clock Rise / Fall - MCLK Frequency for - MCLK Frequency for - MCLK Frequency for Notes 68 MHz 56 MHz Min 14.7 17.6 0.45T C 0.45T C 14.7 17.6 0.45T M 0.45T M - - - - 68 MHz 56 MHz 100 ns DRAMs (5V) 80 ns DRAMs (5V) 70 ns DRAMs (5V) Typ - - - - - - - - - 50.350 56.644 65 Max - - 0.55T C 0.55T C - - 0.55T M 0.55T M 5 - - - Units nS nS nS nS nS nS nS nS nS MHz MHz MHz TC TCH TCL VCLK TM TMH TML MCLK Clock Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 244 65540 / 545 (R) Electrical Specifications 65540 / 545 AC TIMING CHARACTERISTICS - RESET Symbol TIPR TORS TRES TRSR TRSO TCSU TCHD Parameter Reset Active Time from Power Stable Reset Active Time from Ext. Osc. Stable Reset Active Time with Power Stable Reset Rise Time Reset Active to Output Float Delay Configuration Setup Time Configuration Hold Time Notes See Note 1 See Note 2 See Note 3 Reset fall time is non-critical Min 5 0 2 - - 20 5 See Note 4 Max - - - 20 40 - - Units mS nS mS nS nS nS nS Note 1: This parameter includes time for internal voltage stabilization of all sections of the chip, startup and stabilization of the internal clock synthesizer, and setting of all internal logic to a known state. Note 2: The external oscillator input is optional, it may be selected by XR01 bit 5. Note 3: This parameter includes time for the internal clock synthesizer to reset to its default frequency and time to set all internal logic to a known state. It assumes power is stable and the internal clock synthesizer is already operating at some stable frequency. Note 4: Setup time to latch the state of the configuration bits reliably into XR01 and XR6C is specified by this parameter. Changes in some configuration bits may take longer to stabilize inside the chip (such as internal clock synthesizer-related bits 4 and 5). It is therefore recommended that configuration bit setup time be TRES (2mS) to insure that the chip is in a completely stable state when Reset goes inactive. ResetwithChipOperating andPowerStable InitialPower-UpReset VCC TIPR TORS Valid 14.318 MHz (from external oscillator) TRES RESET# TRSR TCSU TRSR TCHD TCSU TCHD Configuration Lines AA0-AA8 Bus Output Pins TRSO Reset Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 245 65540 / 545 (R) Electrical Specifications 65540 / 65545 AC TIMING CHARACTERISTICS - LOCAL BUS CLOCK ( 33 MHz ) Symbol Parameter TLCP Local Bus Clock Period (33MHz) TLCH Local Bus Clock High Time TLCL Local Bus Clock Low Time TLCR Local Bus Clock Rise Time TLCF Local Bus Clock Fall Time -- Local Bus Clock Slew Rate TCRS CPU Reset Setup Time to Local Bus Clock TCRH CPU Reset Hold Time from Local Bus Clock Notes 0.1% stability at 2.0V / 0.8V Min 30 12 12 - - 1 2 5 For 2x Clock Sync For 2x Clock Sync Max 30 - - 3 3 4 - - Units nS nS nS nS nS V / nS nS nS TLCP TLCH CCLK / LCLK TLCR TLCL TLCF Local Bus Clock Timing CCLK / LCLK (2x Bus Clock Configuration) TCRH TCRS CRESET 65540/545 CRESET to CCLK timing should match CPU RESET to CLK2 timing of the CPU. Local Bus '2x' Clock Synchronization Timing Note: VL-Bus timing is compatible with VL-Bus Specification 2.0. Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 246 65540 / 545 (R) Electrical Specifications 65540 / 65545 AC TIMING CHARACTERISTICS - LOCAL BUS INPUT SETUP & HOLD (33 MHz) Symbol Parameter TADS Setup Time - A2-31, BEn#, M/IO#, W/R# TASS Setup Time - ADS# TDWS Setup Time - D0-31 (Write) TRRS Setup Time - RDYRTN# TADH Hold Time - A2-31, BEn#, M/IO#, W/R# TASH Hold Time - ADS# TDWH Hold Time - D0-31 (Write) TRRH Hold Time - RDYRTN# Notes Min 7 7 7 5 2 2 2 2 Max Units - nS - nS - nS - nS - nS - nS - nS - nS CCLK / LCLK TDWS TDWH TRRS TRRH TASS TASH TADS TADH D31-0 (Write) RDYRTN# ADS# BEn#, A31-2 M/IO#, W/R# Local Bus Input Setup & Hold Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 247 65540 / 545 (R) Electrical Specifications 65540 / 65545 AC TIMING CHARACTERISTICS - LOCAL BUS OUTPUT VALID ( 33 MHz ) Symbol Parameter TDAV Bus Clock to Output Valid - D0-31 (Read) TRDV Bus Clock to Output Valid - LRDY# Notes CLMax Min 125pF 3 100pF 3 Max Units 18 nS 14 nS CCLK / LCLK TDAV min D31-0 (Read) ValidN Valid N+1 TRDV min LRDY# max max ValidN Valid N+1 Local Bus Output Valid Timing 65540 / 65545 AC TIMING CHARACTERISTICS - LOCAL BUS FLOAT DELAY (33MHz) Symbol Parameter Notes CLMax Min TDAF Float Delay - D0-31 (Read) 125pF - TRDF Float Delay - LRDY# Driven high before floating 100pF - Max Units 20 nS 30 nS CCLK / LCLK TDAF D31-0 (Read) ValidN TRDF LRDY# Local Bus Output Float Delay Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 248 65540 / 545 (R) Electrical Specifications 65540 / 65545 AC TIMING CHARACTERISTICS - VL-BUS LDEV# Symbol Parameter TLDV Address to LDEV# change Notes Address Min 3 Typ - Max 20 Units nS Valid TLDV TLDV LDEV# VL-Bus LDEV# Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 249 65540 / 545 (R) Electrical Specifications 65540 / 545 AC TIMING CHARACTERISTICS - PCI BUS FRAME Symbol Parameter TFRS FRAME# Setup to CLK TCMS C/BE#[3:0] (Bus CMD) Setup to CLK TCMH C/BE#[31:0] (Bus CMD) Hold from CLK TBES C/BE#[3:0] (Byte Enable) Setup to CLK TBEH C/BE#[3:0] (Byte Enable) Hold from CLK TADS AD[31:0] (Address) Setup to CLK TADH AD[31:0] (Address) Hold from CLK TDAD AD[31:0] (Data) Valid from CLK TDAS AD[31:0] (Data) Setup to CLK TDAH AD[31:0] (Data) Hold from CLK TTZH TRDY# High Z to High from CLK TTHL TRDY# Active from CLK TTLH TRDY# Inactive from CLK TTHZ TRDY# High before High Z TDZL DEVSEL# Active from CLK TDLH DEVSEL# Inactive from CLK TDHZ DEVSEL# High before High Z TISC IRDY# Setup to CLK TIHC IRDY# Hold from CLK Notes Read Cycles Write Cycles Min 7 7 2 7 2 7 2 - 7 2 - - - 1 - - 1 7 2 Max - - - - - - - 11 - - 11 11 11 1 11 11 1 - - Units nS nS nS nS nS nS nS nS nS nS nS nS nS CLK nS nS CLK nS nS Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 250 65540 / 545 (R) Electrical Specifications CLK 1 2 3 4 TFRS FRAME# Hi-Z Bus Hi-Z Turnaround TCMS TCMH C/BE#[3:0] Hi-Z Command TBES Byte Enables TADS TADH Read AD[31:0] Hi-Z Address TADS TADH WriteAD[31:0] Hi-Z Address Hi-Z Bus Hi-Z Byte Enables Turnaround TDAD TDAH Bus Hi-Z Read Turnaround Read Data Turnaround TDAS TDAH WriteData TTZH TRDY# TBEH Bus Hi-Z WriteData Turnaround TTHL TTLH TTHZ Bus Turnaround Hi-Z TISC TIHC IRDY# Hi-Z Bus Turnaround Hi-Z TDZL DEVSEL# Hi-Z Bus Turnaround TDLH TDHZ Hi-Z PCI Bus Frame Timing Note: The above diagram shows a typical PCI bus cycle. PCI bus read cycles require a bus turn-around cycle between address output and data input on AD31:0. PCI bus write cycles do not require this bus turnaround cycle so the write data is available from the bus master immediately after address output (in clock cycle 2 instead of clock cycle 3). Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 251 65540 / 545 (R) Electrical Specifications 65540 / 545 AC TIMING CHARACTERISTICS - PCI BUS STOP Symbol Parameter TSZH STOP# High Z to High from CLK TSHL STOP# Active from CLK TSLH STOP# Inactive from CLK TSHZ STOP# High before High Z Notes Min - - - 1 Max 11 11 11 1 Units nS nS nS CLK CLK TSZH STOP# TSHL TSLH TSHZ High Z PCI Bus Stop Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 252 65540 / 545 (R) Electrical Specifications 65540 / 65545 AC TIMING CHARACTERISTICS - ISA BUS Symbol Parameter Notes TCPW Command Strobe Pulse Width TCHR Command Strobe Hold from Ready TNXT Command Strobe Inactive to Next Strobe TALE Address Setup to ALE Inactive TASC Address Setup to Command Strobe TICS Address to IOCS16# & MEMCS16# Delay TRSR Read Data Setup to Ready Mem Accesses Only TRPW RDY Pulse Width Mem Accesses Only TAHC Address Hold to Command Strobe TRDH Read Data Hold from Command Strobe TRDZ Read Data Tri-Stated from Command Strobe TWDD Write Data Delay from Command Strobe TWDH Write Data Hold from Command Strobe TRLC RDY Low Delay from Command Strobe (+5V) Mem Accesses Only TRLC RDY Low Delay from Command Strobe (+3.3V) Mem Accesses Only Min 6Tm 0 3Tm 29 30 - 25 0 20 10 - - 10 - - Typ Max Units - - nS - - nS - - nS - - nS - - nS - 2Tm nS - - nS - 100Tm nS - - nS - - nS - 30 nS - 20 nS - - nS - 40 nS - 55 nS RFSH#, AEN, A0-19, BHE# TALE ALE TASC Command Strobe IORD#, IOWR# MEMR#,MEMW# RDY TAHC TRLC TCPW TRPW TNXT TCHR TICS IOCS16#, MCS16# TRSR TRDZ TRDH Data (Read) TWDD TWDH Data(Write) ISA Bus Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 253 65540 / 545 (R) Electrical Specifications 65540 / 65545 AC TIMING CHARACTERISTICS - DRAM READ / WRITE Symbol Parameter Notes TRC Read/Write Cycle Time TRAS RAS# Pulse Width TRP RAS# Precharge TCRP CAS# to RAS# Precharge TCSH CAS# Hold from RAS# TRCD RAS# to CAS# Delay TRSH RAS# Hold from CAS# TCP CAS# Precharge TCAS CAS# Pulse Width TASR Row Address Setup to RAS# TASC Column Address Setup to CAS# TRAH Row Address Hold from RAS# TCAH Column Address Hold from CAS# TCAC Data Access Time from CAS# XR05[2-1]=0 (3MCLK CAS Cycle) XR05[2-1]=1 (4MCLK CAS Cycle) TRAC Data Access Time from RAS# XR05[2-1]=0 (3MCLK CAS Cycle) XR05[2-1]=1 (4MCLK CAS Cycle) TDS Write Data Setup to CAS# TDH Write Data Hold from CAS# TPC CAS Cycle Time TWS WE# Setup to CAS# TWH WE# Hold from CAS# Min 12Tm - 5 8Tm - 5 4Tm - 3 4Tm - 5 5Tm - 2 3Tm - 5 2Tm - 5 Tm - 5 2Tm - 5 Tm - 5 2Tm - 8 Tm - 2 Tm - 2 - - - - Tm - 5 Tm - 2 3Tm - 1 1Tm - 5 2Tm - 5 Max - - - - - - - - - - - - - 2Tm - 5 3Tm - 5 5Tm - 2 6Tm - 2 - - - - - Units nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 254 65540 / 545 (R) Electrical Specifications TRC TRAS TRP RAS# TCRP TRCD TPC TCAS TRSH TCP TCAS CAS# TCSH TCAH TASR TRAH Address Row TCAH TASC Column TASR Column Row TASC WE# Data TCAC TCAC TRAC High Z Read High Z High Z Read DRAM Page Mode Read Cycle Timing TRC TRAS TRP RAS# TCRP TRCD TRSH TPC TCAS TCAS CAS# TASR TRAH TASC Address Row TCSH TCAH TCP TASC Column TCAH Column TWS TASR Row TWH WE# TDS Data TDH TDS Write Data TDH Write Data DRAM Page Mode Write Cycle Timing Note: The above diagrams represent typical page mode cycles. The number of actual CAS cycles may vary. Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 255 65540 / 545 (R) Electrical Specifications 65545 AC TIMING CHARACTERISTICS - DRAM READ / MODIFY / WRITE Symbol Parameter TRRMW RAS# Pulse Width TCRMW CAS# Pulse Width TAWD Col Address to WE# Delay TRWD RAS# to WE# Delay TCPWD CAS# Precharge to WE# Delay TOEZ Output Turnoff Delay from OE# TOEW OE# Write Data Delay TOER OE# Read Data Delay TOER OE# Read Data Delay Notes XR05[1] = 0 (3 MCLK CAS Cycle) XR05[1] = 1 (4 MCLK CAS Cycle) Min 16Tm - 5 6Tm - 5 6Tm - 8 7Tm - 5 5Tm - 5 - Tm + 3 - - Max - - - - - Tm - 2Tm - 5 3Tm - 5 Units nS nS nS nS nS nS nS nS nS Note: Read Modify Write timing for 65545 only. TRRMW RAS# TCRP TRCD TCP TCRMW TCRMW CAS# TASR TRAH TASC TCAH Address Row TRWD TASC TCAH Column TAWD Column Row TCPWD WE# TCAC TCAC OE# TOER TOEW TOEZ Data Read TOER TOEW TOEZ TDS TDH Write Read TDS TDH Write DRAM Page Mode Read Modify Write Cycle Timing Note: The above diagrams represent typical page mode cycles. The number of actual CAS cycles may vary. Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 256 65540 / 545 (R) Electrical Specifications 65540 / 65545 AC TIMING CHARACTERISTICS - CBR REFRESH Symbol Parameter Notes TCHR RAS# to CAS# Delay Tm = 15.4 @ 65 MHz TCSR CAS# to RAS# Delay Normal Operation Standby Mode TRAS RAS# Pulse Width 5Tm = 89 ns (56 MHz) or 77 ns (65 MHz) Min 5Tm - 5 Tm - 5 2Tm - 5 5Tm - 5 Typ - - - - Max - - - - Units nS nS nS nS TRAS RAS# TCSR TCHR CAS# CAS-Before-RAS ( CBR ) DRAM Refresh Cycle Timing 65540 / 65545 AC TIMING CHARACTERISTICS - SELF REFRESH Symbol Parameter Notes TRASS RAS# Pulse Width for Self-Refresh TRP RAS# Precharge TRPS RAS# Precharge for Self-Refresh TRPC RAS# to CAS# Delay TCSR CAS# to RAS# Delay Normal Operation Standby Mode TCHS CAS# Hold Time TCPN CAS# Precharge TRP RAS# TRPC Min 100 4Tm - 3 10Tm 3Tm - 5 Tm - 5 2Tm - 5 0 Tm - 5 TRASS TCSR Typ - - - - - - - - Max - - - - - - - - Units S nS nS nS nS nS nS nS TRPS TCHS TCPN CAS# Dout High Z Address 'Self-Refresh DRAM' Refresh Cycle Timing Note: Upon exiting self-refresh mode, the 65540 / 65545 will perform a complete set of CBR refresh cycles before resuming normal DRAM activity. The duration of the burst refresh will equal the panel power sequencing delay, programmed in XR5B bits 7-4. Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 257 65540 / 545 (R) Electrical Specifications 65540 / 545 AC TIMING CHARACTERISTICS - CRT OUTPUT TIMING Symbol Parameter TSYN HSYNC, VSYNC delay from VCLK in TSYN HSYNC, VSYNC delay from VCLK in (3.3V) TSD VCLK in to SHFCLK delay TSD VCLK in to SHFCLK delay (3.3V) Notes Min - - - - Max 50 80 30 50 Units nS nS nS nS Min 12 0 Max - - Units nS nS VCLK in TSYN HSYNC, VSYNC out TSD SHFCLK out CRT Output Timing 65540 / 545 AC TIMING CHARACTERISTICS - PC VIDEO TIMING Symbol Parameter TPVS Video Data setup to PCLK TPVH Video Data hold to PCLK Notes PCLK TPVS TPVH VideoData HSYNC VSYNC PC Video Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 258 65540 / 545 (R) Electrical Specifications 65540 / 545 AC TIMING CHARACTERISTICS - PANEL OUTPUT TIMING Symbol Parameter TDSU Panel Data Setup to SHFCLK TDH Panel Data Hold to SHFCLK TDLY Panel Data Delay from SHFCLK TL2S SHFCLK Allowance Time from LP TS2L LP Allowance Time from SHFCLK TFSU FLM Setup Time TFSH FLM Hold Time Notes Min 5 10 10 Tc Tc 8 Tc 8 Tc Max - - - - - - - Units nS nS nS nS nS nS nS LP TS2L TL2S SHFCLK TDSU TDLY TDH Data TFSU TFSH FLM Flat Panel Vertical Refresh LP First Second Line Line Data Data Transfer Transfer Last Line Data Transfer FLM Panel Output Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 259 65540 / 545 (R) Electrical Specifications Revision 1.2 260 65540 / 545 (R) Mechanical Specifications Mechanical Specifications Lead Length 0.5 0.2 (0.020 0.008) Lead Pitch 0.50 (0.0197) Vendor Mask Identifier Date Code and Country of Assembly Lot Code (Optional) F6554x R XXXXXXX YYWW CCCCCC LLLLLLL 30.6 0.4 (1.205 0.016) CHIPS Part No. and Revision Footprint 208-Pin Plastic Flat Pack 28.0 0.1 (1.102 0.004) (R) Body Size Lead Width 0.20 0.10 (0.008 0.004) DIMENSIONS: mm (in) Clearance 0.25 (0.010) Minimum Pin 1 Revision 1.2 Body Size 28.0 0.1 (1.102 0.004) Footprint 30.6 0.4 (1.205 0.016) 261 Seating Plane Height 4.07 (0.160) Maximum 65540 / 545 (R) Chips and Technologies, Inc. 2950 Zanker Road San Jose, California 95134 Phone: 408-434-0600 FAX: 408-894-2080 Title: 65540 / 545 Data Sheet Publication No.: DS170.2 Stock No.: 010170-002 Revision No.: 1.2 Date: 10/30/95