65545 - Asiliant Technologies - Datasheet.Directory

High Performance

Flat Panel / CRT

VGA Controllers

65540 / 545

Data Sheet

Revision 1.2

October 1995

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Trademark Acknowledgement

CHIPS Logotype, CHIPSlink, CHIPSPort, ELEAT, LeAPSet, NEAT, NEATsx, PEAK,

PRINTGINE, SCAT, SuperMathDX, SuperState, and WINGINE are registered trademarks

of Chips and Technologies, Incorporated.

CHIPSet, Super Math, WinPC, and XRAM Video Cache are trademarks of Chips and

Technologies, Incorporated.

IBM® AT, XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter,

Color Graphics Adapter, Video Graphics Adapter, IBM Color Display, and IBM

Monochrome Display are trademarks of International Business Machines Corporation.

Hercules is a trademark of Hercules Computer Technology.

MS-DOS and Windows are trademarks of Microsoft Corporation.

MultiSync is a trademark of Nippon Electric Company (NEC).

Brooktree and RAMDAC are trademarks of Brooktree Corporation.

Inmos is a trademark of Inmos Corporation.

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

VESA® is a registered trademark of Video Electronics Standards Association.

VL-Bus is a trademark of Video Electronics Standards Association.

All other trademarks are the property of their respective holders.

Disclaimer

This document is provided for the general information of the customer. Chips and

Technologies, Inc., reserves the right to modify the information contained herein as

necessary and the customer should ensure that it has the most recent revision of the data

sheet. CHIPS makes no warranty for the use of its products and bears no responsibility

for any errors which may appear in this document. The customer should be on notice that

the field of personal computers is the subject of many patents held by different parties.

Customers should ensure that they take appropriate action so that their use of the products

does not infringe upon any patents. It is the policy of Chips and Technologies, Inc. to

respect the valid patent rights of third parties and not to infringe upon or assist others to

infringe upon such rights.

Revision 1.2 65540 / 545

nHighly integrated design (flat panel / CRT VGA

controller, RAMDAC, clock synthesizer)

nMultiple Bus Architecture Integrated Interface

• Local Bus (32-bit CPU Direct and VL)

• EISA/ISA (PC/AT) 16-bit Bus

• PCI Bus (65545)

nFlexible display memory configurations

• One 256Kx16 DRAM (512KB)

• Four 256Kx4 DRAMs (512KB)

• Two 256Kx16 DRAMs (1MB)

nAdvanced frame buffer architecture uses

available display memory, maximizing

integration and minimizing chip count

nIntegrated programmable linear address feature

accelerates GUI performance

nHardware windows acceleration (65545)

• 32-bit graphics engine

- System-to-screen and screen-to-screen

BitBLT

- 3 operand ROP's

- Color expansion

- Optimized for Windows™ BitBLT format

• Hardware line drawing

• 64x64x2 hardware cursor

nHardware pop-up icon (65545)

• 64x64 pixels by 4 colors

• 128x128 pixels by 2 colors

nHigh performance resulting from zero wait-state

writes (write buffer) and minimum wait-state

reads (internal asynchronous FIFO design)

nMixed 3.3V ±0.3V / 5.0V ±10% Operation

nInterface to CHIPS' PC Video to display "live"

video on flat panel displays

nSupports panel resolutions up to 1280 x 1024

resolution including 800x600 and 1024x768

nSupports non-interlaced CRT monitors with

resolutions up to 1024 x 768 / 256 colors

nTrue-color and Hi-color display capability with

flat panels and CRT monitors up to 640x480

resolution

nDirect interface to Color and Monochrome Dual

Drive (DD) and Single Drive (SS) panels

(supports 8, 9, 12, 15, 16, 18 and 24-bit data

interfaces)

nAdvanced power management features minimize

power consumption during:

• Normal operation

• Standby (Sleep) modes

• Panel-Off Power-Saving Mode

nFlexible on-board Activity Timer facilitates

ordered shut-down of the display system

nPower Sequencing control outputs regulate

application of Bias voltage, +5V to the panel and

+12 V to the inverter for backlight operation

nSMARTMAP™ intelligent color to gray scale

conversion enhances text legibility

nText enhancement feature improves white text

contrast on flat panel displays

nFully Compatible with IBM™ VGA

nEIAJ-standard 208-pin plastic flat pack

System Diagram

65540

65545

To CRT

Display

To Flat

Panel

Display

RGB

H/V Sync

Panel Control

Panel Data

Address

Data

Control

14.31818 MHz

32-bit 386/486

CPU Direct or VL

Local Bus, PCI

Bus, or 16-bit ISA

System Bus

BIOS

ROM

65540 / 545

High Performance

Flat Panel / CRT VGA Controller

16/24

512KByte or

1MByte Video

Memory

Optional

PCVideo

Multi-Media

Interface

Revision Date By Comment

1.1 9/94 DH Added note: Refer to Electrical Specs for maximum clock frequencies in

'Supported Video Modes' table

Added note: Not all above resolutions can be supported at 3.3V and/or 5V

Changed Mode 50 in Supported Video Modes-Extended Resolution Table

from 16 to 16M

Reset column in Reset/Setup/Test/Standby/Panel-Off Mode table was

incorrect. Now reads: "RESET#/Low/–/–/High/High"

Changed note for Pin List-Bus Interface: from "Drive=5V low drive and

3V high drive" to "IOL and IOH drive listed above indicates 5V low

drive and 3.3V high drive (see also XR6C)"

Changed pin description: pin 25 LDEV# pin type "Out/OC" to "Out"

Changed Config Reg XR01 bits 2-1 VL-Bus description for pin

23=CRESET should read pin 23=RDYRTN#

Changed Ext Reg XR2D and XR2E to (CMPR Enabled) and (CMPR

Disabled) and added note: "For DD panels without frame acceleration,

the programmed value should be doubled"

Updated tables for "No FRC" and "2-Frame FRC"

Updated Flat Panel Timing "CD: 010" should read "CD: 001"

Updated Programming: FLM delay programmed in XR2C should be equal

to: CRT blank time – FLM front porch – FLM width

XR2D LP Delay (CMPR enabled) & XR2E LP Delay (CMPR disabled)

Added note: "Can use external 14.31818 MHz oscillator into XTALI (203)

with XTALO (204) as no connect"

Updated Elec Specs: changed "Max" under "Normal Operating Conditions"

from 90 to 100; "memory clock is assumed to be 68 MHz not 65 MHz;"

and "VL-Bus timing is compatible with VL-Bus Specification 2.0"

Added timing for VL-Bus LDEV#, 14.31818 MHz, DRAM R/M/W and

PC-Video and modified timing for PCI Bus Frame

Clarified function of ACTI output.

1.2 7/95 BB/MP Updated Supported Video Modes table

Updated I/O Map section

Added 64310 to CHIPS VGA Product Family in Register Summary

Updated Extension Registers table

Updated XR33, XR6C, XR6F in the Extension Registers section

Added Rset formula to CRT Panel Interface Circuit

Updated Interface-Optrex DMF-50351NC-FW (640x480 Color STN-DD)

LCD Panel Interface example

Updated 65540/545 DC Characteristics in timing section

Updated Local Bus Input Setup & Hold, Local Bus Output Valid, Local

Bus Output Float Delay, VL-Bus LDEV#, CRT Output, Panel Output

Timing diagrams

Added 65545B2 specifications

Revision History

Revision 1.2 2 65540 / 545

Revision History

Table of Contents

Revision 1.2 3 65540 / 545

Table of Contents

Section Page

Introduction / Overview.................................. 7

Minimum Chip Count / Board Space.......... 8

Display Memory Interface........................... 8

CPU Bus Interface....................................... 10

High Performance Features......................... 10

65545 Acceleration...................................... 10

65545 Hardware Cursor............................... 10

PC Video / Overlay Support........................ 10

Display Interface.......................................... 11

Flat Panel Displays.................................. 11

Panel Power Sequencing ............................. 11

CRT Displays.......................................... 11

Simultaneous Flat Panel / CRT Display.. 14

Display Enhancement Features ................... 14

"True-Gray" Gray Scale Algorithm ........ 14

RGB Color to Gray Scale Reduction ...... 14

SmartMap™............................................ 14

Text Enhancement................................... 15

Vertical and Horizontal Compensation... 15

Advanced Power Management.................... 16

Normal Operating Mode ......................... 16

Mixed 3.3V and 5V Operation................ 16

Panel Off Mode....................................... 16

Standby Mode ......................................... 16

CRT Power Management (DPMS) ......... 16

CPU Activity Indicator / Timer................... 17

Full Compatibility ....................................... 17

Write Protection ...................................... 17

Extension Registers................................. 17

Panel Interface Registers......................... 17

Alternate Panel Timing Registers ........... 17

Context Switching................................... 17

Reset, Setup, and Test Modes...................... 18

Reset Mode.............................................. 18

Setup Mode ............................................. 18

Tri-State Mode ........................................ 18

ICT (In-Circuit-Test) Mode .................... 18

Chip Architecture ........................................ 19

Sequencer................................................ 19

CRT Controller........................................ 19

Graphics Controller................................. 19

Attribute Controller................................. 19

VGA / Color Palette DAC....................... 19

Clock Synthesizers.................................. 20

Configuration Inputs.................................... 21

Virtual Switch Register ............................... 21

Light Pen Registers...................................... 21

BIOS ROM Interface................................... 21

Package........................................................ 21

Application Schematics............................... 22

Section Page

Pinouts (65540)............................................... 23

Pinouts (65545)............................................... 24

Pin Diagram (65540)................................... 23

Pin Diagram (65545)................................... 24

Pin Lists....................................................... 25

Pin Descriptions - ISA/VL-Bus Interface.... 31

Pin Descriptions - PCI Bus Interface

(65545 only)............................................ 34

Pin Descriptions - Display Memory............ 37

Pin Descriptions - Flat Panel Interface........ 39

Pin Descriptions - CRT and Clock Interface 40

Pin Descriptions - Power / Gnd / Standby... 42

I/O Map........................................................ 43

CGA, MDA, and Hercules Registers........... 44

EGA Registers............................................. 44

VGA Registers............................................. 44

VGA Indexed Registers............................... 45

Extension Registers ..................................... 46

32-Bit Registers (65545) ............................. 49

PCI Configuration Registers (65545).......... 50

Global Control (Setup) Registers ................ 53

PCI Configuration Registers........................ 55

General Control & Status Registers............. 59

CGA / Hercules Registers............................ 61

Sequencer Registers..................................... 63

CRT Controller Registers............................ 67

Graphics Controller Registers ..................... 81

Attribute Controller and

VGA Color Palette Registers .................. 89

Extension Registers ..................................... 95

32-Bit Registers (65545 only) ..................... 155

Table of Contents

Revision 1.2 4 65540 / 545

Table of Contents

Section Page

Functional Description.................................... 165

System Interface.......................................... 165

Functional Blocks ................................... 165

Bus Interface .......................................... 165

ISA Interface ..................................... 165

VL-Bus Interface ............................... 165

Direct Processor Interface ................. 165

PCI Interface ..................................... 165

Display Memory Interface .......................... 166

Memory Architecture ............................. 166

Memory Chip Requirements .................. 166

Clock Synthesizer ....................................... 167

MCLK Operation ................................... 167

VCLK Operation .................................... 168

Programming the Clock Synthesizer . 168

Programming Constraints .................. 168

Programming Example ...................... 169

PCB Layout Considerations ................... 169

VGA Color Palette DAC ............................ 170

BitBLT Engine (65545 only) ...................... 171

Bit Block Transfer .................................. 171

Sample Screen-to-Screen Transfer ......... 172

Compressed Screen-to-Screen Transfer . 173

System-to-Screen BitBLTs .................... 175

Hardware Cursor (65545 only) ................... 177

Programming .......................................... 177

Cursor Data Array Format & Layout 177

Display Mem Base Addr Formation . 178

VGA Controller Programming .......... 178

Copying Cursor Data to Disp Mem ... 178

Setting Position, Type, & Base Addr 178

Flat Panel Timing............................................ 179

Overview ..................................................... 179

Panel Size .................................................... 179

Panel Type................................................... 179

TFT Panel Data Width................................. 179

Display Quality Settings.............................. 180

Frame Rate Control (FRC)...................... 180

Dither....................................................... 180

M Signal Timing ..................................... 180

Gray / Color Levels................................. 180

Pixels Per Shift Clock.................................. 181

Color STN Pixel Packing ............................ 182

Output Signal Timing.................................. 183

LP Signal Timing.................................... 183

FLM Output Signal Timing..................... 183

Blank#/DE Output Signal Timing........... 183

Shift Clock Output Signal Timing .......... 183

Pixel Timing Sequence Diagrams ............... 183

Section Page

Programming and Parameters ......................... 195

General Programming Hints........................ 195

Parameters for Initial Boot .......................... 197

Parameters for Emulation Modes................ 198

Parameters for Monochrome LCD Panels

(Panel Mode Only).................................. 199

Parameters for Monochrome LCD Panels

(Simultaneous Mode Display)................. 200

Parameters for Color TFT Panels

(Panel Mode Only).................................. 201

Parameters for Color TFT Panels

(Simultaneous Mode Display)................. 202

Parameters for Color STN SS Panels

(Panel & Simultaneous Mode Display)... 203

Parameters for Color STN SS Panels

(Extended 4-bit Pack).............................. 204

Parameters for Color STN DD Panels

(Panel & Simultaneous Mode Display)... 205

Parameters for Plasma Panels...................... 206

Parameters for EL Panels ............................ 207

Application Schematics................................... 209

System Bus Interface................................... 210

VL-Bus / 486 CPU Local Bus Interface...... 211

PCI Local Bus Interface .............................. 212

Display Memory / PC Video Interface........ 213

CRT / Panel Interface.................................. 214

Panel Interface Examples................................ 215

Electrical Specifications.................................. 241

Absolute Maximum Conditions................... 241

Normal Operating Conditions ..................... 241

DAC Characteristics.................................... 241

DC Characteristics....................................... 242

DC Drive Characteristics............................. 242

AC Test Conditions..................................... 243

AC Characteristics

Reference Clock Timing ......................... 243

Clock Generator Timing.......................... 244

Reset Timing........................................... 245

Bus Timing.............................................. 246

DRAM Timing........................................ 254

CRT Output Timing................................ 258

PC Video Timing .................................... 258

Panel Output Timing............................... 259

Mechanical Specifications............................... 261

Plastic 208-PFP Package Dimensions......... 261

List of Tables

Revision 1.2 5 65540 / 545

List of Tables

Table Page

Feature Differences......................................... 7

Display Capabilities ........................................ 9

Supported Video Modes - VGA...................... 12

Supported Video Modes - Extended ............... 13

Supported Video Modes - High Refresh......... 13

Vcc Pin to Interface Pin Correspondence ....... 16

Reset/Setup/Test/Standby/Panel-Off Modes... 18

Configuration Pin Summary............................ 21

Pin List ............................................................ 25

Pin Descriptions .............................................. 31

Standby Mode Panel Output Signal Status ..... 41

Standby Mode Memory Output Signal Status. 41

Standby Mode Bus Output Signal Status........ 42

I/O Map........................................................... 43

and VGA Color Palette................................ 89

DRAM Speed vs. Memory Clock Frequency . 166

Table Page

Parameters - Initial Boot ................................ 197

Parameters - Emulation Modes....................... 198

Parameters - Monochrome LCD-DD

Panel Mode Only......................................... 199

Simultaneous Mode Display........................ 200

Parameters - Color TFT LCD

Panel Mode Only......................................... 201

Simultaneous Mode Display........................ 202

Parameters - Color STN-SS LCD

Panel & Simultaneous Mode Display.......... 203

Parameters - Color STN-DD LCD

8-bit Interface Extended 4-bit Pack............. 204

16-bit Interface (with FA)............................ 205

Parameters - Monochrome Plasma.................. 206

Parameters - Monochrome EL ........................ 207

Panel Interface Examples Summary ............... 215

DK Board Connector Summary...................... 216

Absolute Maximum Conditions ..................... 241

Normal Operating Conditions ........................ 241

DAC Characteristics ....................................... 241

DC Characteristics .......................................... 242

DC Drive Characteristics ............................... 242

AC Test Conditions ........................................ 243

AC Timing Characteristics ............................. 243

Reference Clock .......................................... 243

Clock Generator........................................... 244

Reset ............................................................ 245

Local Bus Clock .......................................... 246

Local Bus Input Setup & Hold.................... 247

Local Bus Output Valid............................... 248

Local Bus Float Delay................................. 248

VL-Bus LDEV# .......................................... 249

PCI Bus Frame............................................. 250

PCI Bus Stop .............................................. 252

ISA Bus........................................................ 253

DRAM Read / Write.................................... 254

DRAM Read / Modify / Write..................... 256

DRAM CBR-Refresh .................................. 257

DRAM Self-Refresh.................................... 257

CRT Output ................................................ 258

PC Video ..................................................... 258

Panel Output ............................................... 259

List of Figures

Revision 1.2 6 65540 / 545

List of Figures

Figure Page

System Diagram.............................................. 1

Panel Power Sequencing................................. 11

Color Palette / DAC Block Diagram............... 19

Clock Synthesizer Register Structure.............. 20

Pinouts (65540)............................................... 23

Pinouts (65545)............................................... 24

Pin List ............................................................ 25

Pin Descriptions .............................................. 26

Functional Description

Clock Synthesizer Register Structure.......... 167

Clock Synthesizer PLL Block Diagram ...... 167

Clock Filter Circuit...................................... 169

Clock Power / Ground Layout Example...... 169

VGA Color Palette DAC Data Flow ........... 170

Possible BitBLT Orientations With Overlap 171

Screen-to-Screen BitBLT............................ 172

BitBLT Data Transfer.................................. 173

Differential Pitch BitBLT Data Transfer..... 174

Flat Panel Timing

Monochrome 16 Gray-Level EL ................ 184

Monochrome LCD DD 8-bit Interface ....... 185

Monochrome LCD DD 16-bit Interface ..... 186

Color LCD TFT 9/12/16-bit Interface ........ 187

Color LCD TFT 18/24-bit Interface ........... 188

Color LCD STN 8-bit Interface .................. 189

Color LCD STN 16-bit Interface ................ 190

Color LCD STN-DD 8-bit Interface

(with Frame Acceleration)...................... 191

Color LCD STN-DD 8-bit Interface

(without Frame Acceleration) ................ 192

Color LCD STN-DD 16-bit Interface

(with Frame Acceleration) ..................... 193

Color LCD STN-DD 16-bit Interface

(without Frame Acceleration) ................ 194

Application Schematics

ISA Bus Interface ....................................... 210

VL-Bus / 486 Processor Direct Interface ... 211

PCI Bus Interface ........................................ 212

Display Memory Interface .......................... 213

CRT / Panel Interface ................................. 214

Figure Page

Flat Panel Interface Schematics

Plasma-16 - Matsushita S804...................... 217

EL-16 - Sharp LJ64ZU50............................ 218

Mono DD - Epson EG9005F-LS................. 219

Mono DD - Citizen G6481L-FF.................. 220

Mono DD - Sharp LM64P80....................... 221

Mono DD - Sanyo LCM6494-24NTK ........ 222

Mono DD - Hitachi LMG5364XUFC......... 223

Mono DD - Sanyo LCM-5491-24NAK....... 224

Mono DD - Epson ECM-A9071.................. 225

Color TFT - Hitachi TM26D50VC2AA...... 226

Color TFT - Sharp LQ9D011...................... 227

Color TFT - Toshiba LTM-09C015-1......... 228

Color TFT - Sharp LQ10D311.................... 229

Color TFT - Sharp LQ10DX01................... 230

Color STN SS - Sanyo LM-CK53-22NEZ.. 231

Color STN SS - Sanyo LCM5327-24NAK. 232

Color STN SS - Sharp LM64C031.............. 233

Color STN DD - Kyocera KCL6448........... 234

Color STN DD - Hitachi LMG9720XUFC. 235

Color STN DD - Sharp LM64C08P............ 236

Color STN DD - Sanyo LCM5331-22NTK 237

Color STN DD - Hitachi LMG9721XUFC. 238

Color STN DD - Tosh. TLX-8062S-C3X... 239

Color STN DD - Opt DMF-50351NC-FW.. 240

Electrical Specifications

Reference Clock Timing.............................. 243

Clock Generator Timing.............................. 244

Reset Timing................................................ 245

Local Bus Clock Timing.............................. 246

Local Bus '2x' Clock Synch Timing............ 246

Local Bus Input Setup & Hold Timing ....... 247

Local Bus Output Valid Timing.................. 248

Local Output Float Delay Timing ............... 248

VL-Bus LDEV# Timing ............................. 249

PCI Bus Frame Timing................................ 251

PCI Bus Stop Timing................................... 252

ISA Bus Timing........................................... 253

DRAM Page Mode Read Cycle Timing...... 255

DRAM Page Mode Write Cycle Timing..... 255

DRAM Read/Modify/Write Cycle Timing.. 256

DRAM CAS-Before-RAS (CBR) Timing... 257

DRAM 'Self-Refresh' Cycle Timing ........... 257

CRT Output Signal Timing ......................... 258

PC Video Timing......................................... 258

Panel Output Signal Timing........................ 259

Mechanical Specifications

Plastic 208-PFP Package Dimensions......... 261

Revision 1.2 7 65540 / 545

Introduction / Overview

The 65540 / 545 High Performance Flat Panel /

CRT Controllers initiate a family of 208-pin, high

performance solutions for full-featured notebook /

sub-notebook and other portable applications that

require the highest graphics performance available.

The 65545 is pin-to-pin compatible with the 65540

and adds a sophisticated graphics hardware engine

for Bit Block Transfer (BitBLT), line drawing,

hardware cursor, and other functions intensively

used in Graphical User Interfaces (GUIs) such as

Microsoft Windows™. The 65540 and 65545 also

use the same video BIOS, offering the system

manufacturer a wide range of price / performance

points while minimizing overhead for system

integration and improving time-to-market. The

following table indicates feature differences

between the 65540 and 65545:

The 65540 / 545 family achieves superior

performance through direct connection to system

processor buses up to 32-bits in width. When

combined with CHIPS' advanced linear acceleration

software driver technology, these devices exhibit

exceptional performance compared with devices of

similar architecture. The 65540 / 545 architecture

provides a fast throughput to video memory,

maximizing the capability of today's powerful

microprocessors to manipulate graphics operations.

Based on the architecture of the 65540, the 65545

adds a powerful 32-bit graphics engine to offload

graphics processing from the microprocessor for

maximum performance.

Minimum chip-count, low-power graphics

subsystem implementations are enabled through the

high integration level of the 65540 / 545 family.

These devices integrate the VGA-compatible

graphics controller, true color RAMDAC, and dual

PLL clock synthesizers. The entire graphics sub-

system can be implemented with a single 256Kx16

DRAM. The 32-bit local bus interface of the 65540

/ 545 family eliminates external buffers.

For maximum performance, the 65540 / 545

supports an additional 256Kx16 DRAM, which

provides a 32-bit video memory bus and additional

display memory to support resolutions up to

1024x768 with 256 colors, 800x600 with 256

colors, and 640x480 with 16M colors. In addition,

the 65540 / 545 family can support PC Video multi-

media features while interfacing to a 32-bit local

bus and one MByte of video memory.

The 65540 / 545 family supports a wide variety of

monochrome and color Single-Panel, Single-Drive

(SS) and Dual-Panel, Dual Drive (DD) passive STN

and active matrix TFT / MIM LCD, EL, and plasma

panels. The 65540 / 545 family supports panel

resolutions of 800x600, 1024x768, and 1280x1024.

For monochrome panels, up to 64 gray scales are

supported. Up to 226,981 different colors can be

displayed on passive STN LCDs and up to 16M

colors on 24-bit active matrix LCDs using the

65540 / 545 controllers.

The 65540 / 545 family offers a variety of

programmable features to optimize display quality.

For text modes which do not fill all 480 lines of a

standard VGA panel, the 65540 / 545 provides tall

font stretching in the hardware. Fast vertical

centering and programmable vertical stretching in

graphics modes offer more options for handling

modes with less than 480 lines. Three selectable

color-to-grayscale reduction techniques and

SMARTMAP™ are available for improving the

viewability of color applications on monochrome

panels. CHIPS' polynomial FRC algorithm reduces

panel flicker on a wider range of panel types with a

single setting for a particular panel type.

The 65540 / 545 employs a variety of advanced

power management features to reduce power

consumption of the display subsystem and extend

battery life. The 65540 / 545's internal logic,

memory interface, bus interface, and flat panel

interfaces can be independently configured to

operate at either 3.3 V or 5.0 V. The 65540 / 545 is

optimized for minimum power consumption during

normal operation and provides two power-saving

modes - Panel Off and Standby. During Panel Off

mode, the 65540 / 545 turns off the flat panel while

Introduction / Overview

Features

65540

65545

Support for all flat panels 3 3

VESA Local Bus / 16-bit ISA Bus 3 3

32-bit PCI Bus —3

Linear Addressing 3 3

Hardware Accelerator —3

Hardware Cursor —3

Pin Compatible 3 3

BIOS Compatible

3 3

Revision 1.2 8 65540 / 545

Introduction / Overview

the VGA subsystem remains active. The palette

may also be automatically shut off during Panel Off

mode to further reduce power consumption. During

Standby mode, the 65540 / 545 suspends all CPU,

memory and display activities. In this mode, the

65540 / 545 places the DRAM in self-refresh mode

and the 65540 / 545 reference input clock can be

turned off. The 65540 / 545 also provides a

programmable activity timer which monitors VGA

activity. After all display activity ceases, the timer

will automatically shut down the panel by either

disabling the backlight or putting the 65540 / 545 in

Panel Off mode.

The 65540 / 545 is fully compatible with the VGA

graphics standard at the register, gate, and BIOS

levels. The 65540 / 545 provides full backwards

compatibility with the EGA and CGA graphics

standards without using NMIs. CHIPS and third-

party vendors supply fully VGA-compatible BIOS,

end-user utilities and drivers for common

application programs (e.g., Microsoft Windows™,

OS/2, WordPerfect, Lotus, etc.). CHIPS' drivers for

Windows include a Big Cursor (to increase the

cursor's legibility on monochrome flat panels) and

panning / scrolling capability (to increase

performance).

MINIMUM CHIP COUNT / BOARD SPACE

The 65540 / 545 provides a minimum chip count /

board space, yet highly flexible VGA subsystem.

The 65540 / 545 integrates a high-performance

VGA flat panel / CRT controller, industry-standard

RAMDAC, clock synthesizer, monitor sense

circuitry and an activity timer in a 208-pin plastic

flat pack package. In its minimum configuration,

the 65540 / 545 requires only a single 256Kx16

DRAM, such that a complete VGA subsystem for

motherboard applications can be implemented with

just two ICs. This configuration consumes less than

2 square inches (1290 sq mm) of board space and is

capable of supporting simultaneous flat panel / CRT

display requirements while directly interfacing to a

32-bit local bus. As an option, a second memory

chip may be implemented to increase performance

(via a 32-bit data path to display memory) and

support graphics modes which require more than

512 KBytes of display memory. No external

buffers or glue logic are required for the 65540 /

545's bus interface, memory interface, or panel

interface. The 65540 / 545 employs separate

address and data buses with sufficient drive

capability such that the bus can be driven directly.

The 65540 / 545 also provides up to 24 bits of panel

data with sufficient drive capability such that

virtually all flat panels can be driven directly.

DISPLAY MEMORY INTERFACE

The 65540 / 545 supports multiple display memory

configurations, providing the OEM with the

flexibility to use the same VGA controller in

several designs with differing cost, power

consumption and performance criteria. The 65540 /

545 supports the following display memory

configurations:

nOne 256Kx16 DRAM (512 KBytes)

nTwo 256Kx16 DRAMs (1 MBytes)

nFour 256Kx4 DRAMs (512 KBytes)

Performance is significantly improved when the

65540 / 545 is configured with a 32-bit data path to

display memory, which is accomplished by using

two 256Kx16 DRAMs. Two 256Kx16 DRAMs

support all standard, Super, and Extended VGA

resolutions up to 1024x768 256 colors as well as

"high" 16bpp color and "true" 24bpp color modes.

The table on the following page summarizes the

display capabilities of the 65540 / 545.

Display memory control signals are derived from

the integrated clock synthesizer's memory clock.

The 65540 / 545 serves as a DRAM controller for

the system's display memory. It handles DRAM

refresh, fetches data from display memory for

display refresh, interfaces the CPU to display

memory, and supplies all necessary DRAM control

signals.

The 65540 / 545 supports 'two-CAS / one-WE' and

'one-CAS / two-WE' 256Kx16 DRAMs. The 65540

/ 545 supports the self-refresh features of 256Kx16

DRAMs and certain 256Kx4 DRAMs during

Standby mode, enabling the 65540 / 545 to be

powered down completely during suspend/resume

operation.

Revision 1.2 9 65540 / 545

Introduction / Overview

CRT Mode Mono LCD DD STN LCD 9-Bit TFT LCD Video Simultaneous

Resolution Color4Gray Scales 4Colors 2, 3, 4 Colors 1, 2, 3, 4 Memory Display

320x200 256 / 256K† 61 / 61 256 / 226,981 256 / 185,193 512KB Yes

640x480 16 / 256K† 16 / 61 16 / 226,981 16 / 185,193 512KB Yes

640x480 256 / 256K† 61 / 61 256 / 226,981 256 / 185,193 512KB Yes

800x600 16 / 256K† 16 / 61 16 / 226,981 16 / 185,193 512KB Yes with 1MB

800x600 256 / 256K† 61 / 61 256 / 226,981 256 / 185,193 512KB Yes with 1MB

1024x768 16 / 256K† 16 / 61 16 / 226,981 16 / 185,193 512KB Yes with 1MB

1024x768 256 / 256K† 61 / 61 256 / 226,981 256 / 185,193 1MB Yes

1280x1024 16 / 256K† 16 / 61 n/a n/a 1MB n/a

65540 / 545 Display Capabilities

Notes:

1 Larger color palettes and simultaneous colors can be displayed on 12-bit, 18-bit, and 24-bit TFT panels via the 65540 / 545 video input port

2 Includes dithering

3 Includes frame rate control

4 Colors are described as number of simultaneous on-screen colors and number of unique colors available in the color palette

† 256K colors assumes DAC output mode is set to 6 bits of R, G, & B. If DAC is set to 8-bit output mode, the number of available colors is 16M

Revision 1.2 10 65540 / 545

Introduction / Overview

CPU BUS INTERFACE

The 65540 / 545 provides a direct interface to:

n 32-bit VL-Bus

n 32-Bit 386/486 CPU local bus

n EISA/ISA (PC/AT) 16-bit bus

n PCI Bus (65545 only)

Strap options allow the user to configure the chip

for the type of interface desired. Control signals for

all interface types are integrated on chip. All

operations necessary to ensure proper functioning in

these various environments are handled in a fashion

transparent to the CPU. These include internal

decoding of all memory and I/O addresses, bus

width translations, and generation of necessary

control signals.

HIGH PERFORMANCE FEATURES

The 65540 / 545 includes a number of performance

enhancement techniques including:

nDirect 32-bit local bus CPU support

n32-bit interface to video memory

nLinearly addressable display memory

n32-bit graphics hardware engine (65545 only)

n64x64x2 hardware cursor (65545 only)

The 65540 /545 provides an optimized 32-bit path

from 32-bit CPUs direct to the video memory.

Running the 32-bit local bus of the 65540 / 545 at

CPU speeds up to 33 MHz maximizes data

throughput and drawing speed for today's powerful

CPU architectures. Addressing pixels linearly

maximizes the efficiency of software drivers,

enabling the CPU to make the most use of the full

32-bit path through the 65540 / 545 controller.

Software drivers optimized for linear addressing are

available from CHIPS and improve performance up

to 80% over standard software methods.

65545 ACCELERATION

Several functions traditionally performed by

software have been implemented in hardware in the

65545 to off load the CPU and further improve

performance. Three-Operand BitBLT logic

supports all 256 logical combinations of Source,

Destination, and Pattern. All BitBLTs are executed

up to 32-bits per cycle, maximizing the efficiency

of memory accesses. A 32-bit color expansion

engine allows the host CPU to transfer

monochrome "maps" of color images over the

system bus at high speeds to the 65545, which

decodes the monochrome images into their color

form. Line drawing is also accelerated with

hardware assistance.

65545 HARDWARE CURSOR

A programmable-size hardware cursor frees

software from continuously generating the cursor

image on the display. The 65545 supports four

types of cursors:

32 x 32 x 2bpp (and/xor)

64 x 64 x 2bpp (and/xor)

64 x 64 x 2bpp (4-color)

128 x 128 x 1bpp (2-color)

The first two hardware cursor types indicated as

'and/xor' above follow the MS Windows™

AND/XOR cursor data plane structure which

provides for two colors plus 'transparent'

(background color) and 'inverted' (background color

inverted). The last two types in the list above are

also referred to as 'Pop-Ups' because they are

typically used to implement pop-up menu

capabilities. Hardware cursor / pop-up data is

stored in display memory, allowing multiple cursor

values to be stored and selected rapidly. The two or

four colors specified by the values in the hardware

cursor data arrays are stored in on-chip registers as

high-color (5-6-5) values independent of the on-

chip color lookup tables.

The hardware cursor can overlay either graphics or

video data on a pixel by pixel basis. It may be

positioned anywhere within screen resolutions up to

2048x2048 pixels. 64x64 'and/xor' cursors may also

be optionally doubled in size to 128 pixels either

horizontally and/or vertically by pixel replication.

Hardware cursor screen position, type, color, and

base address of the cursor data array in display

memory may be controlled via the 32-bit 'DR'

extension registers.

PC VIDEO / OVERLAY SUPPORT

The 65540 / 545 allows up to 24 bits of external

RGB video data to be input and merged with the

internal VGA data stream. The 65540 / 545

supports two forms of video windowing: (i) color

key input and (ii) X-Y window keying. The X-Y

window key input can be used to position the live

video window coordinates. The 65540 / 545 can be

used in conjunction with Chips and Technologies,

Inc. PC Video products to provide portable multi-

media solutions.

Revision 1.2 11 65540 / 545

Introduction / Overview

DISPLAY INTERFACE

The 65540 / 545 is designed to support a wide range

of flat panel and CRT displays of all different types

and resolutions.

Flat Panel Displays

The 65540 / 545 supports all flat panel display

technologies including plasma, electroluminescent

(EL) and liquid crystal displays (LCD). LCD panel

interfaces are provided for single panel-single drive

(SS) and dual panel-dual drive (DD) configurations.

A single panel sequences data similar to a CRT

(i.e., sequentially from one area of video memory).

In contrast, a dual panel requires video data to be

provided alternating from two separate areas of

video memory. In addition, a dual drive panel

requires the data from the two areas to be provided

to the panel simultaneously. Due to its integrated

frame buffer and 24-data-line panel interface, the

65540 / 545 supports all panels directly. Support

for LCD-DD panels does not require external

hardware such as a frame buffer. Support for high-

resolution, 'high color' flat panels also does not

require additional components. The 65540 / 545

handles display data sequencing transparently to

applications software, providing full compatibility

on both CRT and flat panel displays.

9-bit 12-bit

'512-Color' '4096-Color' Dither FRC

512 (83) 4096 (163) No No

3,375 (153) 29,791 (313) No Yes

24,389 (293) 226,981 (613) Yes No

185,193 (573) 1,771,561 (1213) Yes Yes

There is currently no standard interface for flat

panel displays. Interface signals and timing

requirements vary between panel technologies and

suppliers. The 65540 / 545 provides register

programmable features to allow interfacing to the

widest possible range of flat panel displays. The

65540 / 545 provides a direct interface to panels

from vendors such as Sharp, Sanyo, Epson, Seiko

Instruments, Oki, Toshiba, Hitachi, Fujitsu, NEC,

Matsushita/Panasonic, and Planar.

PANEL POWER SEQUENCING

Flat panel displays are extremely sensitive to condi-

tions where full biasing voltage VEE is applied to

the liquid crystal material without enabling the

control and data signals to the panel. This results in

severe damage to the panel and may disable the

panel permanently. The 65540 / 545 provides a

simple and elegant method to sequence power to the

flat panel display during various modes of operation

to conserve power and provide safe operation to the

flat panel. The 65540 / 545 provides three pins

called ENAVEE, ENAVDD and ENABKL to

regulate the LCD Bias Voltage (VEE), the driver

electronics logic voltage (VDD), and the backlight

voltage (BKL) to provide intelligent power

sequencing to the panel. The timing diagram below

illustrates the power sequencing cycle. In the

65540 / 545, the power on/off delay time (TPO) is

programmable (with a default of 32 mS).

The 65540 / 545 initiates a 'panel off' sequence if

the STNDBY# input is asserted (low), or if XR52

bit-4 is set to a '1' putting the chip into STNDBY

mode. The 65540 / 545 also initiates a 'panel off'

sequence if the chip is programmed to enter 'panel

off' mode (by setting extension register XR52 bit-

3=1), or if the 'Display Type' is programmed to

'CRT' (extension register XR51 bit-2 transitions

from '1' to '0'). The 65540 / 545 initiates a 'panel

on' sequence if the STNDBY# input is high and the

chip is programmed to 'panel on' (XR52 bit-3

transitions from a '1' to '0') and 'flat panel display'

(XR51 bit-2 is set to '1').

CRT Displays

The 65540 / 545 supports high resolution fixed

frequency and variable frequency analog monitors

in interlaced and non-interlaced modes of operation.

Digital monitor support is also built in.

The 65540 / 545 supports resolutions up to

1024x768 256 colors, 800x600 256 colors or

640x480 16,777,216 colors in 1 MByte display

memory configurations, 1024x768 16 colors,

800x600 256 colors in 512 KBytes display memory

configurations. The tables starting on the following

page list all 65540 / 545 CRT monitor video modes.

Panel Power Sequencing

ENAVDD

ENABKL

ENAVEE

Panel On Panel Off

TPO

TPO TPO

TPO

Flat Panel

Control &

Data Signals

Valid

Revision 1.2 12 65540 / 545

Introduction / Overview

Supported Video Modes - VGA Standard

Note: Not all above resolutions can be supported at both 3.3V and 5V.

† Refer to Electrical Specifications section for maximum clock frequencies for 5V and 3.3V operation.

CRT Codes:

A PS/2 fixed frequency analog CRT monitor or equivalent (31.5 / 35.5 KHz Horizontal Frequency Specification)

B Multi-Frequency CRT monitor (37.5 KHz Minimum Horizontal Frequency Specification) (NEC MultiSync 3D or equivalent)

C Multi-Frequency High-Performance CRT Monitor (48.5 KHz Min H Freq Specification) (Nanao Flexscan 9070s, MultiSync 5D, or equivalent)

Horizontal Vertical

Mode# Display Text Font Pixel DotClock Frequency Frequency Video

(Hex) Mode Colors Display Size Resolution (MHz) † (KHz) (Hz) Memory CRT

0, 1 Text 16 40 x 25 8x8 360x400 28.322 31.5 70 256 KB A,B,C

0*, 1* 40 x 25 8x14 320x350 25.175

0+, 1+ 40 x 25 8x8 320x200 25.175

2, 3 Text 16 80 x 25 9x16 720x400 28.322 31.5 70 256 KB A,B,C

2*, 3* 80 x 25 8x14 640x350 25.175

2+, 3+ 80 x 25 8x8 640x200 25.175

4 Graphics 4 40 x 25 8x8 320x200 25.175 31.5 70 256 KB A,B,C

5 Graphics 4 40 x 25 8x8 320x200 25.175 31.5 70 256 KB A,B,C

6 Graphics 2 80 x 25 8x8 640x200 25.175 31.5 70 256 KB A,B,C

7 Text Mono 80 x 25 9x16 720x400 28.322 31.5 70 256 KB A,B,C

7+ 80 x 25 9x14 720x350

D Planar 16 40 x 25 8x8 320x200 25.175 31.5 70 256 KB A,B,C

E Planar 16 80 x 25 8x8 640x200 25.175 31.5 70 256 KB A,B,C

F Planar Mono 80 x 25 8x14 640x350 25.175 31.5 70 256 KB A,B,C

10 Planar 16 80 x 25 8x14 640x350 25.175 31.5 70 256 KB A,B,C

11 Planar 2 80 x 30 8x16 640x480 25.175 31.5 60 256 KB A,B,C

12 Planar 16 80 x 30 8x16 640x480 25.175 31.5 60 256 KB A,B,C

13 Packed Pixel 256 40 x 25 8x8 320x200 25.175 31.5 70 256 KB A,B,C

Note: •All of the above VGA standard modes are supported directly in the 65548 BIOS (both 32K and 40K BIOS versions).

•All of the above VGA standard modes are supported at both 3.3V and 5V.

•All VGA modes using 25.175 MHz and 28.322 MHz can also be supported using 32 MHz and 36 MHz respectively.

In this case, the horizontal frequency becomes 40.000 KHz and the vertical frequency becomes 89 Hz.

(see XR33 bit-7 "ISO Mode Control" for selection of VGA dot clock frequencies)

Revision 1.2 13 65540 / 545

Introduction / Overview

Supported Video Modes - High Refresh

Supported Video Modes - Extended Resolution

Horizontal Vertical

Mode# Display Text Font Pixel DotClock Frequency Frequency Video

(Hex) Mode Colors Display Size Resolution (MHz) † (KHz) (Hz) Memory CRT

20 4 bit Linear 16 80 x 30 8x16 640x480 25.175 31.5 60 512 KB A,B,C

22 4 bit Linear 16 100 x 37 8x16 800x600 40.000 37.5 60 512 KB B,C

24 4 bit Linear 16 128 x 48 8x16 1024x768 65.000 48.5 60 512 KB C

24 I 4 bit Linear 16 128 x 48 8x16 1024x768 44.900 35.5 43 512 KB B,C

28I 4 bit Linear 16 128 x 48 8x16 1280x1024 65.000 42.5 39 1 MB C

30 8 bit Linear 256 80 x 30 8x16 640x480 25.175 31.5 60 512 KB A,B,C

32 8 bit Linear 256 100 x 37 8x16 800x600 40.000 37.5 60 512 KB B,C

34 8 bit Linear 256 128 x 48 8x16 1024x768 65.000 48.5 60 1 MB C

34 I 8 bit Linear 256 128 x 48 8x16 1024x768 44.900 35.5 43 1 MB B,C

40 15bit Linear 32K 80 x 30 8x16 640x480 50.350 31.5 60 1 MB A,B,C

41 16bit Linear 64K 80 x 30 8x16 640x480 50.350 31.5 60 1 MB A,B,C

50 24bit Linear 16M 80 x 30 8x16 640x480 65.000 27.1 51.6 1 MB B,C

60 Text 16 132 x 25 8x16 1056x400 40.000 30.5 68 256 KB A,B,C

61 Text 16 132 x 50 8x16 1056x400 40.000 30.5 68 256 KB A,B,C

6A, 70 Planar 16 100 x 37 8x16 800x600 40.000 38.0 60 256 KB B,C

72,75 Planar 16 128 x 48 8x16 1024x768 65.000 48.5 60 512 KB C

72, 75I Planar 16 128 x 48 8x16 1024x768 44.900 35.5 43 512 KB B,C

78 Packed Pixel 16 80 x 25 8x16 640x400 25.175 31.5 70 256 KB A,B,C

79 Packed Pixel 256 80 x 30 8x16 640x480 25.175 31.5 60 512 KB A,B,C

7C Packed Pixel 256 100 x 37 8x16 800x600 40.000 37.5 60 512 KB B,C

7E Packed Pixel 256 128 x 48 8x16 1024x768 65.000 48.5 60 1 MB C

7E I Packed Pixel 256 128 x 48 8x16 1024x768 44.900 35.5 43 1 MB B,C

76 I 4 bit Planar 16 128 x 48 8x16 1280x1024 65.000 42.5 39 1 MB C

Horizontal Vertical

Mode# Display Text Font Pixel DotClock Frequency Frequency Video

(Hex) Mode Colors Display Size Resolution (MHz) † (KHz) (Hz) Memory CRT

12* Planar 16 80 x 30 8x16 640x480 31.500 37.5 75 256 KB B,C

30 8 bit Linear 256 80 x 30 8x16 640x480 31.500 37.5 75 256 KB C

79 Packed Pixel 256 80 x 30 8x16 640x480 31.500 37.5 75 512 KB C

6A, 70 Planar 16 100 x 37 8x16 800x600 49.500 46.9 75 512 KB C

32 8 bit Linear 256 100 x 37 8x16 800x600 49.500 46.9 75 1 MB C

7C Packed Pixel 256 100 x 37 8x16 800x600 49.500 46.9 75 1 MB C

Note: Support for the modes in the above table is included directly in the BIOS (both 32K and 40K versions).

The "I" in the mode # column indicates "Interlaced".

CRT Codes:

A PS/2 fixed frequency analog CRT monitor or equivalent (31.5 / 35.5 KHz Horizontal Frequency Specification)

B Multi-Frequency CRT monitor (37.5 KHz Minimum Horizontal Frequency Specification) (NEC MultiSync 3D or equivalent)

C Multi-Frequency High-Performance CRT Monitor (48.5 KHz Min H Freq Specification) (Nanao Flexscan 9070s, MultiSync 5D, or equivalent)

† Refer to Electrical Specifications section for maximum clock frequencies for 5V and 3.3V operation.

Note: Not all above resolutions can be supported at both 3.3V and 5V.

Simultaneous Flat Panel / CRT Display

The 65540 / 545 provides simultaneous display

operation with Multi-Sync variable frequency or

PS/2 fixed frequency CRT monitors and single

panel-single drive LCDs (LCD-SS), dual panel-dual

drive LCDs (LCD-DD), and plasma and EL panels

(which employ single panel-single drive interfaces).

Single drive panels sequence data in the same

manner as CRTs, so the 65540 / 545 provides

simultaneous CRT display with LCD-SS, Plasma,

and EL panels by driving the panels with CRT

timing. LCD-DD panels require video data alter-

nating between two separate locations in memory.

In addition, a dual drive panel requires data from

both locations simultaneously. A framestore area,

also called the frame buffer, is required to achieve

this operation. The 65540 / 545 innovative archi-

tecture implements the frame buffer in an unused

area of display memory, reducing chip count and

subsystem cost. As an option, an extra 16-bit wide

DRAM can be used as an external frame buffer,

improving performance while in simultaneous flat

panel/CRT modes. The 65540 / 545 provides

simultaneous display with monochrome and color

LCD-DD panels with a single 256Kx16 DRAM.

DISPLAY ENHANCEMENT FEATURES

Display quality is one of the most important

features for the success of any flat panel-based

system. The 65540 / 545 provides many features to

enhance the flat panel display quality.

"TRUE-GRAY" Gray Scale Algorithm

A proprietary polynomial-based Frame Rate

Control (FRC) and dithering algorithm in the 65540

/ 545's hardware generates a maximum of 61 gray

levels on monochrome panels. The FRC technique

simulates a maximum of 16 gray levels on

monochrome panels by turning the pixels on and off

over several frames in time. The dithering

technique increases the number of gray scales from

16 to 61 by altering the pattern of gray scales in

adjacent pixels. The persistence (response time)

of the pixels varies among panel manufacturers and

models. By re-programming the polynomial (an 8-

bit value in Extension Register XR6E) while

viewing the display, the FRC algorithm can be

adjusted to match the persistence of the particular

panel without increasing the panel's vertical refresh

rate. With this technique, the 65540 / 545 produces

up to 61 flicker-free gray scales on the latest fast

response "mouse quick" film-compensated mo-

nochrome STN LCDs. The alternate method of

reducing flicker -- increasing the panel's vertical

refresh rate -- has several drawbacks. As the

vertical refresh rate increases, panel power

consumption increases, ghosting (cross-talk)

increases, and contrast decreases. CHIPS'

polynomial FRC gray scale algorithm reduces

flicker without increasing the vertical refresh rate.

RGB Color To Gray Scale Reduction

The 24 bits of color palette data from the VGA

standard color lookup table (CLUT) are reduced to

6 bits for 64 gray scales via one of three selectable

RGB color to gray scale reduction techniques:

1) NTSC Weighting: 5/16 Red 9/16 Green 2/16 Blue

2) Equal Weighting: 5/16 Red 6/16 Green 5/16 Blue

3) Green Only: 6 bits of Green only

NTSC is the most common weighting, which is

used in television broadcasting. Equal weighting

increases the weighting for Blue, which is useful for

Applications such as Microsoft Windows 3.1 which

often uses Blue for background colors. Green-Only

is useful for replicating on a flat panel the display of

software optimized for IBM's monochrome

monitors which use the six green bits of palette

data.

SmartMap™

SmartMap™ is a proprietary feature that can be

invoked to intelligently map colors to gray levels in

text mode. SmartMap™ improves the legibility of

flat panel displays by solving a common problem:

Most application programs are optimized for color

CRT monitors using multiple colors. For example,

a word processor might use a blue background with

white characters for normal text, underlined text

could be displayed in green, italicized text in

yellow, and so on. This variety of colors, which is

quite distinct on a color CRT monitor, can be

illegible on a monochrome flat panel display if the

colors are mapped to adjacent gray scale values. In

the example, underlined and italicized text would be

illegible if yellow is mapped to gray scale 4, green

to gray scale 6 with the blue background mapped to

gray scale 5.

SmartMap™ compares and adjusts foreground and

background grayscale values to produce adequate

display contrast on flat panel displays. The

minimum contrast value and the foreground /

background grayscale adjustment values are

programmed in the 65540 / 545's Extension

Registers. This feature can be disabled if desired.

Introduction / Overview

Revision 1.2 14 65540 / 545

Text Enhancement

Text Enhancement is another feature of the 65540 /

545 that improves image quality on flat panel

displays. When enabled, the Text Enhancement

feature displays Dim White as Bright White,

thereby optimizing the contrast level on flat panels.

Text Enhancement can be enabled and disabled by

changing a bit in one of the Extension Registers.

Vertical & Horizontal Compensation

Vertical & Horizontal Compensation are program-

mable features that adjust the display to completely

fill the flat panel display. Vertical Compensation

increases the useable display area when running

lower resolution software on a higher resolution

panel. Unlike CRT monitors, flat panels have a

fixed number of scan lines (e.g., 200, 400, 480 or

768 lines). Lower resolution software displayed on

a higher resolution panel only partially fills the

useable display area. For instance, 350-line EGA

software displayed on a 480-line panel would leave

130 blank lines at the bottom of the display and

400-line VGA text or Mode 13 images would leave

80 blank lines at the bottom. The 65540 / 545

offers the following Vertical Compensation

techniques to increase the useable screen area:

Vertical Centering displays text or graphics images

in the center of the flat panel, with a border of

unused area at the top and bottom of the display.

Automatic Vertical Centering automatically adjusts

the Display Start address such that the unused area

at the top of the display equals the unused area at

the bottom. Non-Automatic Vertical Centering

enables the Display Start address to be set (by

programming the Extension Registers) such that

text or graphics images can be positioned anywhere

on the display.

Line replication (referred to as "stretching")

duplicates every Nth display line (where N is

programmable), thus stretching text characters and

graphic images an adjustable amount. The display

can be stretched to completely fill the flat panel

area. Double scanning, a form of line replication

where every line is replicated, is useful for running

200-line software on a 400-line panel or 480-line

software on a 1024-line panel.

Blank line insertion, inserts N lines (where N is

programmable) between each line of text

characters. Thus text can be evenly spaced to fill

the entire panel display area without altering the

height and shape of the text characters. Blank line

insertion can be used in text mode only.

The 65540 / 545 implements the Tall Font™

scheme so that there are very few blank lines on the

flat panel in text modes. For example, using an

8x19 Tall Font™ would fill 475 lines on a 480-line

panel in VGA mode 3. Lines 1, 9, 12 of the 16 line

font may be replicated to generate the 8x19 font.

Alternately, line 0 may be replicated twice and line

15 replicated once. The Tall Font™ scheme is

implemented in hardware thereby avoiding any

compatibility issues.

Each of these Vertical Compensation techniques

can be controlled by programming the Extension

Registers. Each Vertical Compensation feature can

be individually disabled, enabled, and adjusted. A

combination of Vertical Compensation features can

be used by adjusting the features' priority order.

For example, text mode vertical compensation

consists of four priority order options:

nDouble Scanning+Line Insertion, Double

Scanning, Line Insertion

nDouble Scanning+Line Insertion, Line

Insertion, Double Scanning

nDouble Scanning+Tall Fonts, Double

Scanning, Tall Fonts

nDouble Scanning+Tall Fonts, Tall Fonts,

Double Scanning

Text and graphics modes offer two Line Replication

priority order options:

nDouble Scanning+ Line Replication, Double

Scanning, Line Replication

nDouble Scanning+ Line Replication, Line

Replication, Double Scanning

Horizontal Compensation techniques include

Horizontal Compression, Horizontal Centering, and

Horizontal Doubling. Horizontal Compression will

compress 9-dot text to 8-dots such that 720-dot text

in Hercules modes will fit on a 640-dot panel.

Automatic Horizontal Centering automatically

centers the display on a larger resolution panel such

that the unused area at the left of the display equals

the unused area at the right. Non-Automatic

Horizontal Centering enables the left border to be

set (by programming the Horizontal Centering

Extension Register) such that the image can be

positioned anywhere on the display. Automatic

Horizontal Doubling will automatically double the

display in the horizontal direction when the

horizontal display width is equal to or less than half

of the horizontal panel size.

Introduction / Overview

Revision 1.2 15 65540 / 545

Revision 1.2 16 65540 / 545

Introduction / Overview

ADVANCED POWER MANAGEMENT

Normal Operating Mode

The 65540 / 545 is a full-custom, sub-micron

CMOS integrated circuit optimized for low power

consumption during normal operation. The 65540 /

545 provides CAS-before-RAS refresh cycles for

the DRAM display memory. The 65540 / 545

provides "mixed" 3.3V and 5.0V operation by

providing dedicated Vcc pins for the 65540 / 545's

internal logic, bus interface, memory interface, and

display interface. If the 65540 / 545 internal logic

operates at 3.3V, the memory, bus, and panel

interfaces can independently operate at either 3.3V

or 5.0V. The clock Vcc must be the same as the

Vcc of the internal logic. The 65540 / 545 provides

direct interface to 386/486 local bus which

conserves power when 3.3V microprocessors are

used. A flexible clock synthesizer is used to

generate independent memory and video clocks.

The 65540 / 545's performance-enhancement

features minimize the memory clock frequency (and

thus power consumption) required to achieve a

given performance level. The 65540 / 545's

proprietary gray scaling algorithm produces a

flicker-free display with a minimum video clock

and panel vertical refresh rate. (Note: the power

consumption of the controller increases linearly

with video clock frequency).

Panel Off Mode

In 'Panel Off' mode, the 65540 / 545 turns off both

the flat panel and CRT interface logic. The VGA

subsystem remains active, such that the CPU can

read/write display memory and I/O registers. The

65540 / 545's video clock can be reduced

significantly, saving power. Panel Off mode is

activated by programming Extended Register XR52

bit-3=1.

Standby Mode

In 'Standby' mode, the 65540 / 545 suspends all

CPU, memory and display activities. The 65540 /

545 places the DRAM in its self-refresh mode of

operation, and the 65540 / 545's clock can be shut

off. The VGA subsystem dissipates a minimum

amount of power during Standby. Since the 65540 /

545 is a fully static device, the contents of the

controller's registers and on-chip palette are

maintained during Standby. Therefore, Standby

mode provides fast Suspend / Resume modes. The

Standby mode may be activated by forcing the

STNDBY# pin low or programming XR52 bit-4 to

'1'. The state of all 65540 / 545 pins during

Standby mode is summarized in the tables on the

following page.

CRT Power Management (DPMS)

The 65540 / 545 supports the VESA DPMS

(Display Power Management Signaling) protocol.

This includes the ability to independently stop

HSYNC and/or VSYNC and hold them at a static

level to signal the CRT to enter various power-

saving states. Additionally, the RAMDAC may be

powered down and the clock frequencies lowered

for further power savings.

Mixed 3.3V and 5.0V Operation

The 65540 supports operation at either 5.0V ±10%

or 3.3V ±0.3V. The 65540 also provides "mixed"

5V and 3.3V operation by providing dedicated Vcc

pins for the 65540's internal logic, bus interface,

memory interface, and display interface. Each

dedicated Vcc can be either 5V or 3.3V, such that

the 65540 internal logic operates at 3.3V and the

various interfaces at either 3.3V or 5V. The clock

VCC must be the same as the Vcc of the internal

logic. The following table shows the relationship

between the VCC inputs to the 65540 and the

interface pins controlled by each Vcc input.

* Must be same as the Vcc of the internal logic.

The 65545B1/B2 and 65545B1-5/B2-5 are the same

part (die) that has been tested for operation at

different voltage requirements.

The 65545B1/B2 provides a dedicated Vcc

(Voltage) pins for the internal logic, clock

synthesizer, bus interface, memory interface and the

display interface. Each dedicated Vcc can be either

5V or 3.3V independently except for the internal

core and clock synthesizer which must be at the

same voltage level.

The 65545B1-5/B2-5 limits the internal core and

clock synthesizer Vcc to 5V only operation and

meets all 5V data sheet requirements.

Subject to change without notice

Vcc Pins Interface Pins Affected

80, 181 Internal Logic --

9, 42 Bus 1-54, 178-201, 207

158 Memory A 145-177

142 Memory B 123-144

108 Memory C 90-122

66 Display 61-89

205, 206 Clock* 203, 204

59 DAC 55,57,58,60

CPU ACTIVITY INDICATOR / TIMER

The 65540 / 545 provides an output pin called

ACTI (pin 53) to facilitate an orderly power-down

sequence. The ACTI output is an active high signal

which is driven high every time a valid VGA

memory read/write operation or VGA I/O

read/write operation is executed by the CPU. This

signal may be used by power management circuitry

to put the 65540 / 545 in Panel Off or Standby

power down modes. The 65540 / 545 may also

evoke its own low power operation by using the

activity timer which monitors the ACTI signal. The

activity timer will either disable the backlight or

evoke Panel Off mode after a specified time

interval. This time interval is programmed in 30

second intervals via Extension Register XR5C.

FULL COMPATIBILITY

The 65540 / 545 is fully compatible with the IBM™

VGA standard at the hardware, register, and BIOS

level. The 65540 / 545 also provides enhanced

backward compatibility to EGA™ and CGA™

standards without using NMIs. These controllers

include a variety of features to provide

compatibility on flat panel displays in addition to

CRT monitors. Internal compensation techniques

ensure that industry-standard software designed for

different displays can be executed on the single flat

panel used in an implementation. Mode

initialization is supported at the BIOS and register

levels, ensuring compatibility with all application

software.

Write Protection

The 65540 / 545 has the ability to write protect

most of the standard VGA registers. This feature is

used to provide backwards compatibility with

software written for older generation display types.

The write protection is grouped into register sets

and controlled by the Write Protect Register

(XR15).

Extension Registers

The 65540 / 545 employs an "Extension" Register

set to control its enhanced features. These

Extension Registers provide control of the flat panel

interface, flat panel timing, vertical compensation,

SMARTMAP™, and Backwards Compatibility.

These registers are always accessible as an

index/data register set at port addresses 3D6-3D7h.

None of the unused bits in the regular VGA

registers are used for extensions.

Panel Interface Registers

Flat Panel Interface characteristics are controlled by

a subset of the Extension Registers. These

Registers select the panel type, data formatting,

panel configuration, panel size, clock selection and

video polarity. Since the 65540 / 545 is designed to

support a wide range of panel types and sizes, the

control of these features is fully programmable.

The video polarity of text and graphics modes is

independently selectable to allow black text on a

white background and still provide normal graphics

images.

Alternate Panel Timing Registers

Flat panel displays usually require sync signal

timing that is different from a CRT. To provide full

compatibility with the IBM VGA standard,

alternate timing registers are used to allow

independent timing of the sync signals for flat panel

displays. Unlike the values programmed into the

standard CRT timing registers, the value

programmed into the alternate timing registers is

dependent on the panel type used and is

independent of the display mode.

Context Switching

For support of multi-tasking, windowing, and

context switching, the entire state of the 65540 /

545 (internal registers) is readable and writable.

This feature is fully compatible with IBM's VGA.

Additional registers are provided to allow read back

of internal latches not readable in the IBM VGA.

Revision 1.2 17 65540 / 545

Introduction / Overview

Revision 1.2 18 65540 / 545

RESET, SETUP, AND TEST MODES

Reset Mode

When this mode is activated by pulling the RESET#

pin low, the 65540 / 545 is forced to VGA-compati-

ble mode and the CRT is selected as the active dis-

play. In addition, the 65540 / 545 is disabled; it

must be enabled after deactivating the RESET# pin

by writing to the Global Enable Register (102h in

Setup Mode for ISA bus configurations or to port

3C3h or Local Bus configurations). Access to all

Extension Registers is always enabled after reset (at

3D6/3D7h). The RESET# pin must be active for at

least 64 clock cycles.

Setup Mode

In this mode, only the Global Enable register is

accessible. In IBM-compatible PC implementa-

tions, setup mode is entered by writing a 1 to bit-4

of port 46E8h. This port is incorporated in the

65540 / 545. While in Setup mode, the video

output is active if it was active prior to entering

Setup mode and inactive if it was inactive prior to

entering Setup mode. After power up, video BIOS

can optionally disable the video 46E8 or 3C3

registers (via XR70) for compatibility in case other

non-IBM-compatible peripheral devices use those

ports.

Tri-State Mode

In this mode, all output pins of the 65540 / 545 chip

may be disabled for testing of circuitry external to

the chip. The 65540 / 545 will enter Tri-State mode

if it sees a rising edge on XTALI during RESET

with one of the display memory data pins pulled

low (MAD0 pin 162). The 65540 / 545 will exit

Tri-State mode with the enabling memory data pin

(MAD0) high or RESET# low.

ICT (In-Circuit Test) Mode

In this mode, all digital pins of the 65540 / 545 chip

may be tested individually to determine if they are

properly connected (the analog RGB and RESET#

pins cannot be tested in ICT mode). The 65540 /

545 will enter ICT mode if it sees a rising edge on

XTALI during RESET with one of the display

memory data pins pulled low (a different pin from

the one used to enable Tri-state mode: MAD1). In

ICT mode, all digital signal pins become inputs

which are part of a long path starting at ENAVDD

(pin 62) and proceeding to lower pin numbers

around the chip to pin 1 (except analog pins 55, 57,

58, and 60) then to pin 208 and ending at VSYNC

(pin 64). If all pins in the path are high, the

VSYNC output will be high. If any pin is low, the

VSYNC output will be low. Thus the chip can be

checked in circuit to determine if all pins are

connected properly by toggling all pins one at a

time (XTALI last) and observing the effect on

VSYNC. XTALI must be toggled last because

rising edges on XTALI with either of the enabling

memory data pins high or RESET# low will exit

ICT mode. As a side effect, ICT mode effectively

Tri-States all pins except VSYNC.

Introduction / Overview

Reset / Setup / Test / Standby / Panel-Off Mode Summary

Display

Mode of RESET# STNDBY# Memory Video

Operation Pin†† Pin Access Output

Reset Low xxx ----- -----

Setup ----- ----- No Yes

Test ----- ----- No Yes

Standby† High Low No No

Panel-Off†† High High Yes No

† It is illegal to go from Panel-Off Mode to Standby Mode. Panel-Off Mode must be exited first and a delay must

occur of twice the value programmed into XR5B[7-4] prior to entering Standby Mode.

†† In 65540 ES Silicon reset is active high (RESET); in all following revisions reset is active low (RESET#).

Introduction / Overview

Revision 1.2 19 65540 / 545

Triple 6-bit

LUT

LUT Pixel Data

Red

Green

Blue

High Color Pixel Data

RGB 5-6-5 External Video

Color Palette / DAC Internal Block Diagram

graphic modes the 4-bit pixel data acts as an index

into a set of 16 internal color look-up registers

which generate a 6-bit color value. Two additional

bits of color data are added to provide an 8-bit

address to the VGA color palette. In 256-color

modes, two 4-bit values may be passed through the

color look-up registers and assembled into one 8-bit

video data value. In high-resolution 256-color

modes, an 8-bit video data value may be provided

directly, bypassing the attribute controller color

lookup registers. Text and cursor blink, underline

and horizontal scrolling are also the responsibility

of the Attribute Controller.

VGA / Color Palette DAC

The 65540 / 545 integrates a VGA compatible triple

6-bit Color Lookup Table (sometimes referred to as

a "CLUT" or just "LUT") and high speed 6/8-bit

DACs. Additionally true color bypass modes are

supported displaying color depths of up to 24bpp

(8-red, 8-green, 8-blue). The palette DAC can

switch between true color data and LUT data on a

pixel by pixel basis. Thus, video overlays may be

any arbitrary shape and can lie on any pixel

boundary. The hardware cursor is also a true color

bitmap which may overlay on any pixel boundary.

The internal palette DAC register I/O addresses

and functionality are 100% compatible with the

VGA standard. In all bus interfaces the palette

DAC automatically controls accesses to its registers

to avoid data overrun. This is handled by holding

RDY in the ISA configuration and by delaying

RDY# for VL-Bus and local bus interfaces.

Extended RAMDAC display modes are selected in

the Palette Control Register (XR06). Two 16bpp

formats are supported: 5-red, 5-green, 5-blue Targa

format and 5-red, 6-green, 5-blue XGA format.

The internal Palette / DAC may also be disabled via

the Palette Control Register (XR06).

CHIP ARCHITECTURE

The 65540 / 545 integrates six major internal

modules:

Sequencer

The Sequencer generates all CPU and display

memory timing. It controls CPU access of display

memory by inserting cycles dedicated to CPU

access. It also contains mask registers which can

prevent writes to individual display memory planes.

CRT Controller

The CRT Controller generates all the sync and

timing signals for the display and also generates the

multiplexed row and column addresses used for

both display refresh and CPU access of display

memory.

Graphics Controller

The Graphics Controller interfaces the 8, 16, or 32-

bit CPU data bus to the 32-bit internal data bus used

by the four planes (Maps) of display memory. It

also latches and supplies display memory data to

the Attribute Controller for use in refreshing the

screen image. For text modes this data is supplied

in parallel form (character generator data and

attribute code); for graphics modes it is converted to

serial form (one bit from each of four bytes form a

single pixel). The Graphics Controller can also

perform any one of several types of logical

operations on data while reading it from or writing

it to display memory or the CPU data bus.

Attribute Controller

The Attribute Controller generates the 4-bit-wide

video data stream used to refresh the display. This

is created in text modes from a font pattern and an

attribute code which pass through a parallel to serial

conversion. In graphics modes, the display memory

contains the 4-bit pixel data. In text and 16 color

Introduction / Overview

Revision 1.2 20 65540 / 545

Clock Synthesizers

Integrated clock synthesizers support all pixel clock

(VCLK) and memory clock (MCLK) frequencies

which may be required by the 65540 / 545. Each of

the two clock synthesizers may be programmed to

output frequencies ranging between 1MHz and the

maximum specified operating frequency for that

clock in increments not exceeding 0.5%. The

frequencies are set via a programmable 18-bit

divisor value which contains fields for Phase Lock

Loop (PLL), Voltage Controlled Oscillator (VCO)

and Pre/Post Divide Control. A block diagram

showing the clock synthesizer registers is included

below. Refer to the Functional Description section

of this document for additional information.

Clock Synthesizer Register Diagram

VGA CLK0 = 25.175MHz

VGA CLK1 = 28.322MHz

CLK2 = Programmable

MCLK = Programmable

XR32:30

MISC Output Reg[3:2]

CLKSEL1:0

VCLK Synthesizer

MCLK Synthesizer

VCLK Register Table

MCLK Register Table

Revision 1.2 21 65540 / 545

Introduction / Overview

CONFIGURATION INPUTS

The 65540 / 545 can read up to nine configuration

bits. These signals are sampled on memory address

bus AA0-AA8 on the trailing edge of Reset. The

65540 / 545 implements pull-up resistors on-chip

on all configuration input pins. If the user wishes to

force a certain option, then a 4.7K ohm resistor may

be used to pull-down the desired configuration pin.

AA2 determines the CPU clock rate for purposes of

local bus implementation (0=2x CPU clock, 1=1x

CPU clock). AA3 has no hardware function, but

the status of the pin is latched in extension register

1 bit 3 on reset so it may be used to input system-

specific information. AA4 is reserved and should

be sampled high on reset. AA5, if forced to 0,

indicates that a reference frequency of 14.31818

MHz must be input on XTALI (pin 203). AA6

selects between ACTI/ENABKL and A26-27 on

pins 53-54 (default is ENABKL and ACTI). AA7,

when forced low, enables clock test mode (VCLK

and MCLK are output on A24-25 (pins 29-30).

AA8, when forced low, selects 3.3V level of

operation for the internal logic and the clock core.

VIRTUAL SWITCH REGISTER

The 65540 / 545 implements a 'virtual switch

Feature control register (3C2 bit 4) may be set up to

read a selected bit from the 'virtual switch register'

(an extension register set up by BIOS at

initialization time) instead of reading the state of the

internal comparator output.

LIGHT PEN REGISTERS

In the CGA and Hercules modes, the contents of the

Display Address counter are saved at the end of the

frame before being reset. The saved value can be

read in the CRT Controller Register space at indices

10h and 11h. This allows simulation of a light pen

hit in CGA and Hercules modes.

BIOS ROM INTERFACE

In typical ISA bus and VL-Bus applications, the

65540 / 545 is placed on the motherboard and the

video BIOS is integrated with the system BIOS (in

PCI Bus, the video BIOS is always included in the

system BIOS). A separate signal (ROMCS#) is

generated on the A24 pin for ISA bus or may be

created external to the 65540 / 545 for imple-

menting a separate external ROM BIOS.

Typically, an 8-bit BIOS is implemented with one

external ROM chip. A 16-bit dedicated video BIOS

ROM could be implemented with the 65540 / 545 if

required using two BIOS ROM chips, an external

PAL, and a 74LS244 buffer. However, a higher-

performance and lower-cost video system will

result from implementation of the video BIOS as

either an 8-bit dedicated video BIOS ROM or as

part of the system BIOS and having the video BIOS

be copied into system RAM by the system BIOS on

startup.

Chips and Technologies, Inc. supplies a video BIOS

that is optimized for the 65540 / 545 hardware. The

BIOS supports the extended functions of the 65540

/ 545, such as switching between the flat panel and

the CRT, SMARTMAP™, Vertical Compensation,

and palette load/save. The BIOS Modification

Program (BMP) enables OEMs to tailor their

feature set by programming the extended functions.

CHIPS offers the BIOS as a standard production

version, a customized version, or as source code.

PACKAGE

The 65540 / 545 is available in a EIAJ-standard

208-pin plastic flat pack with a 28 x 28 mm body

size and 0.5 mm (19.7 mil) lead pitch.

65540 / 545

Pin # Signal Active

Functionality

145 LB# Low Bus Configuration

146 ISA# Low Bus Configuration

147 2X# Low 2xCPU Clock Select

148 —Low Reserved

149 —Low Reserved (Do Not Use)

150 OS# Low External Oscillator Select

151 AD# Low ENABKL/ACTI=A26,A27

152 TS# Low Test Mode Enable

153 LV# Low Low Voltage Select

2X#

(AA2)

Pin 147

ISA#

(AA1)

Pin 146

LB#

(AA0)

Pin 145

Bus Functionality

Low Low Low Reserved

Low Low High Reserved

Low High Low Reserved

Low High High 32-bit CPU Bus (2x clk)

High Low Low Reserved

High Low High 16-bit ISA Bus

High High Low PCI Bus (65545 only)

High High High 32-bit VL-Bus (1x clk)

APPLICATION SCHEMATIC EXAMPLES

This document includes application schematic

examples of the following:

1. Bus Interface - 16-bit EISA/ISA Bus

Bus Interface - 32-bit 486 Local Bus (1x Clock)

Bus Interface - 32-bit VL-Bus (1x Clock)

Bus Interface - 32-bit PCI Bus

2. Display Memory Interface

3. CRT / Panel Interface

4. PC Video Interface

Revision 1.2 22 65540 / 545

Introduction / Overview

(WEAH#) WEA#

[]

157 (WECL#) (VR6) 104

[]

CASCL#

MVCCA

[]

158 (CASC#) (VR7) 103

[]

CASCH#

(CASA#) CASAH#

[]

159 (WECH#) (PCLK) 102

[]

WEC#

(WEAL#) CASAL#

[]

160 (KEY) 101

[]

RASC#

MGNDA

[]

161 (VR1) 100

[]

OEC#

(TSENA#) MAD0

[]

162 (VG0) 99

[]

CA9

(ICTENA#) MAD1

[]

163 (VG1) 98

[]

CA8

MAD2

[]

164 (P23) 97

[]

CA7

MAD3

[]

165 (P22) 96

[]

CA6

MAD4

[]

166 (P21) 95

[]

CA5

MAD5

[]

167 (P20) 94

[]

CA4

MAD6

[]

168 (P19) 93

[]

CA3

MAD7

[]

169 (P18) 92

[]

CA2

MAD8

[]

170 (P17) 91

[]

CA1

MAD9

[]

171 (P16) 90

[]

CA0

MAD10

[]

172 89

[]

DGND

MAD11

[]

173 88

[]

P15

MAD12

[]

174 87

[]

P14

MAD13

[]

175 86

[]

P13

MAD14

[]

176 85

[]

P12

MAD15

[]

177 84

[]

P11

STNDBY#

[]

178 83

[]

P10

[]

179 <A2> 82

[]

180 <A3> 81

[]

IVCC

[]

181 80

[]

IVCC

[]

182 <A4> 79

[]

183 <A5> 78

[]

IGND

[]

184 77

[]

IGND

[]

185 <A6> 76

[]

186 <A7> 75

[]

187 <A8> 74

[]

188 <A9> 73

[]

A10

[]

189 <A10> 72

[]

A11

[]

190 <A11> 71

[]

A12

[]

191 <A12> 70

[]

SHFCLK

A13

[]

192 <A13> (DE)(BLANK#) 69

[]

A14

[]

193 <A14> (DE)(BLANK#) 68

[]

A15

[]

194 <A15> 67

[]

FLM

A16

[]

195 <A16> 66

[]

DVCC

A17

[]

196 <LA17> 65

[]

HSYNC

A18

[]

197 <LA18> 64

[]

VSYNC

A19

[]

198 <LA19> 63

[]

DGND

A20

[]

199 <LA20> 62

[]

ENAVDD

A21

[]

200 <LA21> (ENABKL) 61

[]

ENAVEE

A22

[]

201 <LA22> 60

[]

RED

CGND0

[]

202 59

[]

AVCC

XTALI

[]

203 58

[]

GREEN

XTALO

[]

204 57

[]

BLUE

CVCC0

[]

205 56

[]

AGND

CVCC1

[]

206 55

[]

RSET

††† RESET#

[]

207 54

[]

ENABKL

CGND1

[]

208 53

[]

ACTI

D31

[]

1 <reserved> 156

[]

RASA#

D30

[]

2 <reserved> 155

[]

OEAB#

D29

[]

3 <reserved> (32KHZ) 154

[]

AA9 (VR0)

D28

[]

4 <reserved> 153

[]

AA8 (CFG8) (LV#)

D27

[]

5 <reserved> 152

[]

AA7 (CFG7) (TS#)

D26

[]

6 <reserved> 151

[]

AA6 (CFG6) (AD#)

D25

[]

7 <reserved> 150

[]

AA5 (CFG5) (OS#)

D24

[]

8 <reserved> 149

[]

AA4 (CFG4)

BVCC

[]

9 148

[]

AA3 (CFG3)

BE3#

[]

10 <RFSH#> 147

[]

AA2 (CFG2) (2X#)

W/R#

[]

11 <MEMR#> 146

[]

AA1 (CFG1) (ISA#)

BGND

[]

12 145

[]

AA0 (CFG0) (LB#)

D23

[]

13 <reserved> 144

[]

MBD15

D22

[]

14 <reserved> 143

[]

MBD14

D21

[]

15 <reserved> 142

[]

MVCCB

D20

[]

16 <reserved> 141

[]

MBD13

D19

[]

17 <reserved> 140

[]

MBD12

D18

[]

18 <IOCS16#> 139

[]

MGNDB

D17

[]

19 <MCS16#> 138

[]

MBD11

D16

[]

20 <ZWS#> 137

[]

MBD10

BE2#

[]

21 <A1> 136

[]

MBD9

ADS#

[]

22 <ALE> 135

[]

MBD8

RDYRTN#

[]

23 <MEMW#> (CRESET)† 134

[]

MBD7

LRDY#

[]

24 <RDY> 133

[]

MBD6

LDEV#

[]

25 <IOWR#> 132

[]

MBD5

BGND

[]

26 131

[]

MBD4

LCLK

[]

27 <IORD#> 130

[]

MBD3

A23

[]

28 <LA23> 129

[]

MBD2

A24

[]

29 <ROMCS#> (VCLKOUT)†† 128

[]

MBD1

A25

[]

30 <IRQ> (MCLKOUT)†† 127

[]

MBD0

M/IO#

[]

31 <AEN> (WEBL#) 126

[]

CASBL#

BE1#

[]

32 <BHE#> (CASB#) 125

[]

CASBH#

D15

[]

33 <D15> (WEBH#) 124

[]

WEB#

D14

[]

34 <D14> 123

[]

RASB#

D13

[]

35 <D13> 122

[]

MCD15 (VR5)

D12

[]

36 <D12> 121

[]

MCD14 (VR4)

D11

[]

37 <D11> 120

[]

MCD13 (VR3)

D10

[]

38 <D10> 119

[]

MCD12 (VR2)

BGND

[]

39 118

[]

MCD11 (VG7)

[]

40 <D9> 117

[]

MCD10 (VG6)

[]

41 <D8> 116

[]

MCD9 (VG5)

BVCC

[]

42 115

[]

MCD8 (VG4)

BE0#

[]

43 <A0> 114

[]

MCD7 (VG3)

[]

44 <D7> 113

[]

MCD6 (VG2)

[]

45 <D6> 112

[]

MCD5 (VB7)

[]

46 <D5> 111

[]

MCD4 (VB6)

[]

47 <D4> 110

[]

MCD3 (VB5)

[]

48 <D3> 109

[]

MCD2 (VB4)

[]

49 <D2> 108

[]

MVCCC

[]

50 <D1> 107

[]

MCD1 (VB3)

[]

51 <D0> 106

[]

MCD0 (VB2)

BGND

[]

52 105

[]

MGNDC

Revision 1.2 23 65540 / 545

Pin Diagram

Clock

Group

DAC

Group

Pin names shown indicate VL-Bus connections (Default)

Pin names in brackets <...> indicate ISA-Bus connections (ISA# = 0)

Pin names in parentheses indicate alternate functions

65540

Flat Panel VGA Controller

10/30/95

Bus

Interface

Group

DRAM "C"

Frame Buffer

24-Bit

PC-Video

Interface

Panel

Interface

Group

DRAM "B"

Display Memory Upper 512KB

Bus

Interface

Group

DRAM "A"

Display Memory

Lower 512KB

Configuration Pins

2X# = 0 2X LCLK

OS# = 0 External Oscillator (1=Xtal)

AD# = 0 ENABKL & ACTI are A26,A27

TS# = 0 Enable Clock Test Mode

LV# = 0 Input Threshold Level Control

ENABKL = (GPIO) (A27) (VB1)

ACTI = (GPIO) (A26) (VB0)

†In 2x clock mode, pin 23 becomes CRESET instead of RDYRTN#

†† In Test mode, pin 29 becomes VCLKOUT and pin 30 becomes MCLKOUT

††† In 65540 ES Silicon reset is active high (RESET); in all following revisions reset is active low (RESET#).

(WEAH#) WEA#

[]

157 (WECL#) (VR6) 104

[]

CASCL#

MVCCA

[]

158 (CASC#) (VR7) 103

[]

CASCH#

(CASA#) CASAH#

[]

159 (WECH#) (PCLK) 102

[]

WEC#

(WEAL#) CASAL#

[]

160 (KEY) 101

[]

RASC#

MGNDA

[]

161 (VR1) 100

[]

OEC#

(TSENA#) MAD0

[]

162 (VG0) 99

[]

CA9

(ICTENA#) MAD1

[]

163 (VG1) 98

[]

CA8

MAD2

[]

164 (P23) 97

[]

CA7

MAD3

[]

165 (P22) 96

[]

CA6

MAD4

[]

166 (P21) 95

[]

CA5

MAD5

[]

167 (P20) 94

[]

CA4

MAD6

[]

168 (P19) 93

[]

CA3

MAD7

[]

169 (P18) 92

[]

CA2

MAD8

[]

170 (P17) 91

[]

CA1

MAD9

[]

171 (P16) 90

[]

CA0

MAD10

[]

172 89

[]

DGND

MAD11

[]

173 88

[]

P15

MAD12

[]

174 87

[]

P14

MAD13

[]

175 86

[]

P13

MAD14

[]

176 85

[]

P12

MAD15

[]

177 84

[]

P11

STNDBY#

[]

178 83

[]

P10

"reserved" A2

[]

179 <A2> 82

[]

"reserved" A3

[]

180 <A3> 81

[]

IVCC

[]

181 80

[]

IVCC

"reserved" A4

[]

182 <A4> 79

[]

"reserved" A5

[]

183 <A5> 78

[]

IGND

[]

184 77

[]

IGND

"reserved" A6

[]

185 <A6> 76

[]

"reserved" A7

[]

186 <A7> 75

[]

"reserved" A8

[]

187 <A8> 74

[]

"reserved" A9

[]

188 <A9> 73

[]

"reserved" A10

[]

189 <A10> 72

[]

"reserved" A11

[]

190 <A11> 71

[]

"reserved" A12

[]

191 <A12> 70

[]

SHFCLK

"reserved" A13

[]

192 <A13> (DE)(BLANK#) 69

[]

"reserved" A14

[]

193 <A14> (DE)(BLANK#) 68

[]

"reserved" A15

[]

194 <A15> 67

[]

FLM

"reserved" A16

[]

195 <A16> 66

[]

DVCC

"reserved" A17

[]

196 <LA17> 65

[]

HSYNC

"reserved" A18

[]

197 <LA18> 64

[]

VSYNC

"reserved" A19

[]

198 <LA19> 63

[]

DGND

"reserved" A20

[]

199 <LA20> 62

[]

ENAVDD

"reserved" A21

[]

200 <LA21> (ENABKL) 61

[]

ENAVEE

"CLK" A22

[]

201 <LA22> 60

[]

RED

CGND0

[]

202 59

[]

AVCC

XTALI

[]

203 58

[]

GREEN

XTALO

[]

204 57

[]

BLUE

CVCC0

[]

205 56

[]

AGND

CVCC1

[]

206 55

[]

RSET

RESET#

[]

207 54

[]

ENABKL

CGND1

[]

208 53

[]

ACTI

"AD31" D31

[]

1 <reserved> 156

[]

RASA#

"AD30" D30

[]

2 <reserved> 155

[]

OEAB#

"AD29" D29

[]

3 <reserved> (32KHZ) 154

[]

AA9 (VR0)

"AD28" D28

[]

4 <reserved> 153

[]

AA8 (CFG8) (LV#)

"AD27" D27

[]

5 <reserved> 152

[]

AA7 (CFG7) (TS#)

"AD26" D26

[]

6 <reserved> 151

[]

AA6 (CFG6) (AD#)

"AD25" D25

[]

7 <reserved> 150

[]

AA5 (CFG5) (OS#)

"AD24" D24

[]

8 <reserved> 149

[]

AA4 (CFG4)

BVCC

[]

9 148

[]

AA3 (CFG3)

"C/BE3#" BE3#

[]

10 <RFSH#> 147

[]

AA2 (CFG2) (2X#)

"IDSEL" W/R#

[]

11 <MEMR#> 146

[]

AA1 (CFG1) (ISA#)

BGND

[]

12 145

[]

AA0 (CFG0) (LB#)

"AD23" D23

[]

13 <reserved> 144

[]

MBD15

"AD22" D22

[]

14 <reserved> 143

[]

MBD14

"AD21" D21

[]

15 <reserved> 142

[]

MVCCB

"AD20" D20

[]

16 <reserved> 141

[]

MBD13

"AD19" D19

[]

17 <reserved> 140

[]

MBD12

"AD18" D18

[]

18 <IOCS16#> 139

[]

MGNDB

"AD17" D17

[]

19 <MCS16#> 138

[]

MBD11

"AD16" D16

[]

20 <ZWS#> 137

[]

MBD10

"C/BE2#" BE2#

[]

21 <A1> 136

[]

MBD9

"FRAME#" ADS#

[]

22 <ALE> 135

[]

MBD8

"IRDY#" RDYRTN#

[]

23 <MEMW#> (CRESET)† 134

[]

MBD7

"TRDY#" LRDY#

[]

24 <RDY> 133

[]

MBD6

"DEVSEL#" LDEV#

[]

25 <IOWR#> 132

[]

MBD5

BGND

[]

26 131

[]

MBD4

"STOP#" LCLK

[]

27 <IORD#> 130

[]

MBD3

"reserved" A23

[]

28 <LA23> 129

[]

MBD2

"PERR#" A24

[]

29 <ROMCS#> (VCLKOUT)†† 128

[]

MBD1

"SERR#" A25

[]

30 <IRQ> (MCLKOUT)†† 127

[]

MBD0

"PAR" M/IO#

[]

31 <AEN> (WEBL#) 126

[]

CASBL#

"C/BE1#" BE1#

[]

32 <BHE#> (CASB#) 125

[]

CASBH#

"AD15" D15

[]

33 <D15> (WEBH#) 124

[]

WEB#

"AD14" D14

[]

34 <D14> 123

[]

RASB#

"AD13" D13

[]

35 <D13> 122

[]

MCD15 (VR5)

"AD12" D12

[]

36 <D12> 121

[]

MCD14 (VR4)

"AD11" D11

[]

37 <D11> 120

[]

MCD13 (VR3)

"AD10" D10

[]

38 <D10> 119

[]

MCD12 (VR2)

BGND

[]

39 118

[]

MCD11 (VG7)

"AD9" D9

[]

40 <D9> 117

[]

MCD10 (VG6)

"AD8" D8

[]

41 <D8> 116

[]

MCD9 (VG5)

BVCC

[]

42 115

[]

MCD8 (VG4)

"C/BE0#" BE0#

[]

43 <A0> 114

[]

MCD7 (VG3)

"AD7" D7

[]

44 <D7> 113

[]

MCD6 (VG2)

"AD6" D6

[]

45 <D6> 112

[]

MCD5 (VB7)

"AD5" D5

[]

46 <D5> 111

[]

MCD4 (VB6)

"AD4" D4

[]

47 <D4> 110

[]

MCD3 (VB5)

"AD3" D3

[]

48 <D3> 109

[]

MCD2 (VB4)

"AD2" D2

[]

49 <D2> 108

[]

MVCCC

"AD1" D1

[]

50 <D1> 107

[]

MCD1 (VB3)

"AD0" D0

[]

51 <D0> 106

[]

MCD0 (VB2)

BGND

[]

52 105

[]

MGNDC

Revision 1.2 24 65540 / 545

Pin Diagram

Clock

Group

DAC

Group

Pin names shown indicate VL-Bus connections (Default)

Pin names in brackets <...> indicate ISA-Bus connections (ISA# = 0)

Pin names in quotes "..." indicate PCI-Bus connections (LB# = 0)

Pin names in parentheses indicate alternate functions

65545

Flat Panel VGA Controller

10/30/95

DRAM "C"

Frame Buffer

24-Bit

PC-Video

Interface

Panel

Interface

Group

DRAM "B"

Display Memory Upper 512KB

Bus

Interface

Group

DRAM "A"

Display Memory

Lower 512KB

Configuration Pins

2X# = 0 2X LCLK

OS# = 0 External Oscillator (1=Xtal)

AD# = 0 ENABKL & ACTI are A26,A27

TS# = 0 Enable Clock Test Mode

LV# = 0 Input Threshold Level Control

ACTI = (GPIO) (A26) (VB0)

ENABKL = (GPIO) (A27) (VB1)

†In 2x clock mode, pin 23 becomes CRESET instead of RDYRTN#

†† In Test mode, pin 29 becomes VCLKOUT and pin 30 becomes MCLKOUT

Revision 1.2 25 65540 / 545

Pin List

Pin Name Pin # Dir Drive

A2 179 In —

A3 180 In —

A4 182 In —

A5 183 In —

A6 185 In —

A7 186 In —

A8 187 In —

A9 188 In —

A10 189 In —

A11 190 In —

A12 191 In —

A13 192 In —

A14 193 In —

A15 194 In —

A16 195 In —

A17 (LA17) 196 In —

A18 (LA18) 197 In —

A19 (LA19) 198 In —

A20 (LA20) 199 In —

A21 (LA21) 200 In —

A22 (LA22) "CLK" 201 In —

A23 (LA23) 28 In —

A24 (ROMCS#) "PERR#" 29 I/O 8mA

A25 (IRQ) "SERR#" 30 I/O 8mA

AA0 (CFG0) (LB#) 145 I/O 4mA

AA1 (CFG1) (ISA#) 146 I/O 4mA

AA2 (CFG2) (2X#) 147 I/O 4mA

AA3 (CFG3) 148 I/O 4mA

AA4 (CFG4) 149 I/O 4mA

AA5 (CFG5) (OS#) 150 I/O 4mA

AA6 (CFG6) (AD#) 151 I/O 4mA

AA7 (CFG7) (TS#) 152 I/O 4mA

AA8 (CFG8) (LV#) 153 I/O 4mA

AA9 (32KHZ) (VR0) 154 I/O 4mA

ACTI (A26) (VB0) 53 I/O 8mA

ADS# (ALE) "FRAME#" 22 In —

AGND 56 — —

AVCC 59 — —

BE0# (A0) "C/BE0#" 43 In —

BE1# (BHE#) "C/BE1#" 32 In —

BE2# (A1) "C/BE2#" 21 In —

BE3# (RFSH#) "C/BE3#" 10 In —

BLUE 57 Out —

BGND (Bus) 12 — —

BGND (Bus) 26 — —

BGND (Bus) 39 — —

BGND (Bus) 52 — —

BVCC (Bus) 9 — —

BVCC (Bus) 42 — —

CA0 (P16) 90 Out 4mA

CA1 (P17) 91 Out 4mA

CA2 (P18) 92 Out 4mA

CA3 (P19) 93 Out 4mA

CA4 (P20) 94 Out 4mA

CA5 (P21) 95 Out 4mA

CA6 (P22) 96 Out 4mA

CA7 (P23) 97 Out 4mA

CA8 (VG1) 98 I/O 4mA

CA9 (VG0) 99 I/O 4mA

CASAH#(CASA#) 159 Out 4mA

CASAL# (WEAL#) 160 Out 4mA

CASBH# (CASB#) 125 Out 4mA

CASBL# (WEBL#) 126 Out 4mA

CASCH# (CASC#) (VR7) 103 I/O 4mA

CASCL#

(WECL#)

(VR6) 104 I/O 4mA

CGND0 (Clock) 202 — —

CGND1 (Clock) 208 — —

CVCC0 (Clock) 205 — —

CVCC1 (Clock) 206 — —

Note: Drive = 5V low drive and 3V high drive.

Pin Name Pin # Dir Drive

D0 "AD0" 51 I/O 8mA

D1 "AD1" 50 I/O 8mA

D2 "AD2" 49 I/O 8mA

D3 "AD3" 48 I/O 8mA

D4 "AD4" 47 I/O 8mA

D5 "AD5" 46 I/O 8mA

D6 "AD6" 45 I/O 8mA

D7 "AD7" 44 I/O 8mA

D8 "AD8" 41 I/O 8mA

D9 "AD9" 40 I/O 8mA

D10 "AD10" 38 I/O 8mA

D11 "AD11" 37 I/O 8mA

D12 "AD12" 36 I/O 8mA

D13 "AD13" 35 I/O 8mA

D14 "AD14" 34 I/O 8mA

D15 "AD15" 33 I/O 8mA

D16 (ZWS#) "AD16" 20 I/O 8mA

D17 (MCS16#) "AD17" 19 I/O 8mA

D18 (IOCS16#) "AD18" 18 I/O 8mA

D19 "AD19" 17 I/O 8mA

D20 "AD20" 16 I/O 8mA

D21 "AD21" 15 I/O 8mA

D22 "AD22" 14 I/O 8mA

D23 "AD23" 13 I/O 8mA

D24 "AD24" 8 I/O 8mA

D25 "AD25" 7 I/O 8mA

D26 "AD26" 6 I/O 8mA

D27 "AD27" 5 I/O 8mA

D28 "AD28" 4 I/O 8mA

D29 "AD29" 3 I/O 8mA

D30 "AD30" 2 I/O 8mA

D31 "AD31" 1 I/O 8mA

DGND (Display) 63 — —

DGND (Display) 89 — —

DVCC (Display) 66 — —

ENABKL(A27) (VB1) 54 I/O 8mA

ENAVDD 62 Out 8mA

ENAVEE(ENABKL) 61 Out 8mA

FLM 67 Out 8mA

GREEN 58 Out —

HSYNC 65 Out 12mA

IGND (Internal Logic) 77 — —

IGND (Internal Logic) 184 — —

IVCC (Internal Logic) 80 — —

IVCC (Internal Logic) 181 — —

LCLK (IORD#) "STOP#" 27 In —

LDEV# (IOWR#) "DEVSEL#" 25 I/O 12mA

LRDY# (RDY) "TRDY#" 24 Out 12mA

LP (BLANK#) (DE) 68 Out 8mA

M(BLANK#) (DE) 69 Out 8mA

MAD0 (TSENA#) 162 I/O 2mA

MAD1 (ICTENA#) 163 I/O 2mA

MAD2 164 I/O 2mA

MAD3 165 I/O 2mA

MAD4 166 I/O 2mA

MAD5 167 I/O 2mA

MAD6 168 I/O 2mA

MAD7 169 I/O 2mA

MAD8 170 I/O 2mA

MAD9 171 I/O 2mA

MAD10 172 I/O 2mA

MAD11 173 I/O 2mA

MAD12 174 I/O 2mA

MAD13 175 I/O 2mA

MAD14 176 I/O 2mA

MAD15 177 I/O 2mA

MBD0 127 I/O 2mA

MBD1 128 I/O 2mA

MBD2 129 I/O 2mA

MBD3 130 I/O 2mA

Pin Name Pin # Dir Drive

MBD4 131 I/O 2mA

MBD5 132 I/O 2mA

MBD6 133 I/O 2mA

MBD7 134 I/O 2mA

MBD8 135 I/O 2mA

MBD9 136 I/O 2mA

MBD10 137 I/O 2mA

MBD11 138 I/O 2mA

MBD12 140 I/O 2mA

MBD13 141 I/O 2mA

MBD14 143 I/O 2mA

MBD15 144 I/O 2mA

MCD0 (VB2) 106 I/O 2mA

MCD1 (VB3) 107 I/O 2mA

MCD2 (VB4) 109 I/O 2mA

MCD3 (VB5) 110 I/O 2mA

MCD4 (VB6) 111 I/O 2mA

MCD5 (VB7) 112 I/O 2mA

MCD6 (VG2) 113 I/O 2mA

MCD7 (VG3) 114 I/O 2mA

MCD8 (VG4) 115 I/O 2mA

MCD9 (VG5) 116 I/O 2mA

MCD10 (VG6) 117 I/O 2mA

MCD11 (VG7) 118 I/O 2mA

MCD12 (VR2) 119 I/O 2mA

MCD13 (VR3) 120 I/O 2mA

MCD14 (VR4) 121 I/O 2mA

MCD15 (VR5) 122 I/O 2mA

MGNDA (Memory A) 161 — —

MGNDB (Memory B) 139 — —

MGNDC (Memory C) 105 — —

M/IO# (AEN) "PAR" 31 I/O† 4mA

MVCCA (Memory A) 158 — —

MVCCB (Memory B) 142 — —

MVCCC (Memory C) 108 — —

OEAB# 155 Out 4mA

OEC# (VR1) 100 I/O 4mA

P0 71 Out 8mA

P1 72 Out 8mA

P2 73 Out 8mA

P3 74 Out 8mA

P4 75 Out 8mA

P5 76 Out 8mA

P6 78 Out 8mA

P7 79 Out 8mA

P8 81 Out 8mA

P9 82 Out 8mA

P10 83 Out 8mA

P11 84 Out 8mA

P12 85 Out 8mA

P13 86 Out 8mA

P14 87 Out 8mA

P15 88 Out 8mA

RASA# 156 Out 4mA

RASB# 123 Out 4mA

RASC# (KEY) 101 I/O 4mA

RRTN#<MEMW#>

"IRDY#" 23 In —

RED 60 Out —

RESET# (540 Rev 0=RESET) 207 In —

RSET 55 In —

SHFCLK 70 Out 8mA

STNDBY# 178 In —

VSYNC 64 Out 12mA

WEA# (WEAH#) 157 Out 4mA

WEB# (WEBH#) 124 Out 4mA

WEC#

(WECH#)

(PCLK) 102 Out 4mA

W/R# (MEMR#) "IDSEL" 11 In —

XTALI 203 In —

XTALO 204 Out —

† I/O in 65545 only for PCI, In for 65540

Revision 1.2 26 65540 / 545

Pin Lists

Pin # TypeVCC Plane

IOH IOL

Load 65545 PCI Bus VL-Bus CPU Direct LB ISA Bus

207 In Bus – – – RESET# RESET# RESET# RESET#

25 I/O Bus –12 12 150 DEVSEL# LDEV# LDEV# IOWR#

24 Out Bus –12 12 150 TRDY# LRDY# LRDY# RDY

23 In Bus – – – IRDY# RDYRTN# CRESET MEMW#

11 I/O Bus –4 4 150 IDSEL W/R# W/R# MEMR#

31 I/O Bus –4 4 150 PAR M/IO# M/IO# AEN

22 In Bus – – – FRAME# ADS# ADS# ALE

27 In Bus – – – STOP# LCLK CLK2X IORD#

32 In Bus – – – C/BE1# BE1# BE1# BHE#

10 In Bus – – – C/BE3# BE3# BE3# RFSH#

43 In Bus – – – C/BE0# BE0# BE0# A0

21 In Bus – – – C/BE2# BE2# BE2# A1

179 In Bus – – – – A2 A2 A2

180 In Bus – – – – A3 A3 A3

182 In Bus – – – – A4 A4 A4

183 In Bus – – – – A5 A5 A5

185 In Bus – – – – A6 A6 A6

186 In Bus – – – – A7 A7 A7

187 In Bus – – – – A8 A8 A8

188 In Bus – – – – A9 A9 A9

189 In Bus – – – – A10 A10 A10

190 In Bus – – – – A11 A11 A11

191 In Bus – – – – A12 A12 A12

192 In Bus – – – – A13 A13 A13

193 In Bus – – – – A14 A14 A14

194 In Bus – – – – A15 A15 A15

195 In Bus – – – – A16 A16 A16

196 In Bus – – – – A17 A17 LA17

197 In Bus – – – – A18 A18 LA18

198 In Bus – – – – A19 A19 LA19

199 In Bus – – – – A20 A20 LA20

200 In Bus – – – – A21 A21 LA21

201 In Bus – – – CLK A22 A22 LA22

28 In Bus – – – – A23 A23 LA23

29 I/O Bus –8 8 150 PERR#†† A24†† A24†† ROMCS#††

30 I/O Bus –8 8 150 SERR#†† A25†† A25†† IRQ††

53 I/O Bus –8 8 150 ACTI A26 † A26 † ACTI

54 I/O Bus –8 8 150 ENABKL A27 † A27 † ENABKL

PIN LIST - BUS INTERFACE

Note: IOL/IOH are specified in mA; Load is specified in pF

†These two pins usually function as ACTI and ENABKL, but can be reconfigured as additional address msbs (for 386/486/VL-Bus

only) via configuration bit-6 (see other tables and pin descriptions for more details)

†† In internal clock synthesizer test mode, MCLK is output on A25 and VCLK is output on A24.

LB# ISA# 2X# Bus Configuration

1 1 1 VL-Bus (1x clock) Pin-23 = RDYRTN#

1 1 0 CPU-Direct (2x clock) Pin-23 = CRESET

1 0 1 ISA Bus

1 0 0 -reserved-

0 1 1 PCI Bus (65545 only)

0 1 0 -reserved-

0 0 1 -reserved-

0 0 0 -reserved-

Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)

Revision 1.2 27 65540 / 545

Pin Lists

Pin # Type VCC Plane

IOH IOL

Load 65545 PCI Bus VL-Bus CPU Direct LB ISA Bus

51 I/O Bus –8 8 150 AD0 D0 D0 D0

50 I/O Bus –8 8 150 AD1 D1 D1 D1

49 I/O Bus –8 8 150 AD2 D2 D2 D2

48 I/O Bus –8 8 150 AD3 D3 D3 D3

47 I/O Bus –8 8 150 AD4 D4 D4 D4

46 I/O Bus –8 8 150 AD5 D5 D5 D5

45 I/O Bus –8 8 150 AD6 D6 D6 D6

44 I/O Bus –8 8 150 AD7 D7 D7 D7

41 I/O Bus –8 8 150 AD8 D8 D8 D8

40 I/O Bus –8 8 150 AD9 D9 D9 D9

38 I/O Bus –8 8 150 AD10 D10 D10 D10

37 I/O Bus –8 8 150 AD11 D11 D11 D11

36 I/O Bus –8 8 150 AD12 D12 D12 D12

35 I/O Bus –8 8 150 AD13 D13 D13 D13

34 I/O Bus –8 8 150 AD14 D14 D14 D14

33 I/O Bus –8 8 150 AD15 D15 D15 D15

20 I/O Bus –8 8 150 AD16 D16 D16 ZWS#

19 I/O Bus –8 8 150 AD17 D17 D17 MCS16#

18 I/O Bus –8 8 150 AD18 D18 D18 IOCS16#

17 I/O Bus –8 8 150 AD19 D19 D19 —

16 I/O Bus –8 8 150 AD20 D20 D20 —

15 I/O Bus –8 8 150 AD21 D21 D21 —

14 I/O Bus –8 8 150 AD22 D22 D22 —

13 I/O Bus –8 8 150 AD23 D23 D23 —

8 I/O Bus –8 8 150 AD24 D24 D24 —

7 I/O Bus –8 8 150 AD25 D25 D25 —

6 I/O Bus –8 8 150 AD26 D26 D26 —

5 I/O Bus –8 8 150 AD27 D27 D27 —

4 I/O Bus –8 8 150 AD28 D28 D28 —

3 I/O Bus –8 8 150 AD29 D29 D29 —

2 I/O Bus –8 8 150 AD30 D30 D30 —

1 I/O Bus –8 8 150 AD31 D31 D31 —

PIN LIST - BUS INTERFACE

Note: IOL/IOH are specified in mA; Load is specified in pF

Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)

Revision 1.2 28 65540 / 545

Pin Lists

Pin # Type

IOH IOL

Load Function Alt Alt

145 I/O –4 4 50 AA0 CFG0 –

146 I/O –4 4 50 AA1 CFG1 –

147 I/O –4 4 50 AA2 CFG2 –

148 I/O –4 4 50 AA3 CFG3 –

149 I/O –4 4 50 AA4 CFG4 –

150 I/O –4 4 50 AA5 CFG5 –

151 I/O –4 4 50 AA6 CFG6 –

152 I/O –4 4 50 AA7 CFG7 –

153 I/O –4 4 50 AA8 CFG8 –

154 I/O –4 4 50 AA9 32KHZ VR0

90 Out –4 4 50 CA0 P16 –

91 Out –4 4 50 CA1 P17 –

92 Out –4 4 50 CA2 P18 –

93 Out –4 4 50 CA3 P19 –

94 Out –4 4 50 CA4 P20 –

95 Out –4 4 50 CA5 P21 –

96 Out –4 4 50 CA6 P22 –

97 Out –4 4 50 CA7 P23 –

98 I/O –4 4 50 CA8 – VG1

99 I/O –4 4 50 CA9 – VG0

156 Out –4 4 50 RASA# – –

123 Out –4 4 50 RASB# – –

101 I/O –4 4 50 RASC# – KEY

160 Out –4 4 50 CASAL# WEAL# –

159 Out –4 4 50 CASAH# CASA# –

126 Out –4 4 50 CASBL# WEBL# –

125 Out –4 4 50 CASBH# CASB# –

104 I/O –4 4 50 CASCL# WECL# VR6

103 I/O –4 4 50 CASCH# CASC# VR7

157 Out –4 4 50 WEA# WEAH# –

124 Out –4 4 50 WEB# WEBH# –

102 Out –4 4 50 WEC# WECH# PCLK

155 Out –4 4 50 OEAB# – –

100 I/O –4 4 50 OEC# – VR1

PIN LIST - DISPLAY MEMORY INTERFACE

Note: IOL/IOH are specified in mA; Load is specified in pF

Pin # Type

IOH IOL

Load Function Alt Alt

162 I/O –2 2 30 MAD0

163 I/O –2 2 30 MAD1

164 I/O –2 2 30 MAD2

165 I/O –2 2 30 MAD3

166 I/O –2 2 30 MAD4

167 I/O –2 2 30 MAD5

168 I/O –2 2 30 MAD6

169 I/O –2 2 30 MAD7

170 I/O –2 2 30 MAD8

171 I/O –2 2 30 MAD9

172 I/O –2 2 30 MAD10

173 I/O –2 2 30 MAD11

174 I/O –2 2 30 MAD12

175 I/O –2 2 30 MAD13

176 I/O –2 2 30 MAD14

177 I/O –2 2 30 MAD15

127 I/O –2 2 30 MBD0

128 I/O –2 2 30 MBD1

129 I/O –2 2 30 MBD2

130 I/O –2 2 30 MBD3

131 I/O –2 2 30 MBD4

132 I/O –2 2 30 MBD5

133 I/O –2 2 30 MBD6

134 I/O –2 2 30 MBD7

135 I/O –2 2 30 MBD8

136 I/O –2 2 30 MBD9

137 I/O –2 2 30 MBD10

138 I/O –2 2 30 MBD11

140 I/O –2 2 30 MBD12

141 I/O –2 2 30 MBD13

143 I/O –2 2 30 MBD14

144 I/O –2 2 30 MBD15

106 I/O –2 2 30 MCD0 VB2

107 I/O –2 2 30 MCD1 VB3

109 I/O –2 2 30 MCD2 VB4

110 I/O –2 2 30 MCD3 VB5

111 I/O –2 2 30 MCD4 VB6

112 I/O –2 2 30 MCD5 VB7

113 I/O –2 2 30 MCD6 VG2

114 I/O –2 2 30 MCD7 VG3

115 I/O –2 2 30 MCD8 VG4

116 I/O –2 2 30 MCD9 VG5

117 I/O –2 2 30 MCD10 VG6

118 I/O –2 2 30 MCD11 VG7

119 I/O –2 2 30 MCD12 VR2

120 I/O –2 2 30 MCD13 VR3

121 I/O –2 2 30 MCD14 VR4

122 I/O –2 2 30 MCD15 VR5

Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)

Revision 1.2 29 65540 / 545

Pin Lists

Pin # Type

IOH IOL

Load Function Alt

65 Out –12 12 150 HSYNC –

64 Out –12 12 150 VSYNC –

55 – – – – RSET –

60 Out – – – RED –

58 Out – – – GREEN –

57 Out – – – BLUE –

59 Vcc – – – AVCC –

56 Gnd – – – AGND –

PIN PIST - CRT INTERFACE

Note: IOL/IOH are specified in mA; Load is specified in pF

Pin # Type

IOH IOL

Load Function

80 Vcc – – – IVCC

181 Vcc – – – IVCC

77 Gnd – – – IGND

184 Gnd – – – IGND

9 Vcc – – – BVCC

42 Vcc – – – BVCC

12 Gnd – – – BGND

26 Gnd – – – BGND

39 Gnd – – – BGND

52 Gnd – – – BGND

158 Vcc – – – MVCCA

142 Vcc – – – MVCCB

108 Vcc – – – MVCCC

161 Gnd – – – MGNDA

139 Gnd – – – MGNDB

105 Gnd – – – MGNDC

66 Vcc – – – DVCC

63 Gnd – – – DGND

89 Gnd – – – DGND

PIN LIST - POWER & GROUND

Note: CVCC must equal IVCC

Note: IVCC must equal CVCC

Pin # Type

IOH IOL

Load Function Alt Alt

67 Out –8 8 80 FLM –

68 Out –8 8 80 LP BLANK# DE

69 Out –8 8 80 M BLANK# DE

70 Out –8 8 80 SHFCLK –

71 Out –8 8 80 P0 –

72 Out –8 8 80 P1 –

73 Out –8 8 80 P2 –

74 Out –8 8 80 P3 –

75 Out –8 8 80 P4 –

76 Out –8 8 80 P5 –

78 Out –8 8 80 P6 –

79 Out –8 8 80 P7 –

81 Out –8 8 80 P8 –

82 Out –8 8 80 P9 –

83 Out –8 8 80 P10 –

84 Out –8 8 80 P11 –

85 Out –8 8 80 P12 –

86 Out –8 8 80 P13 –

87 Out –8 8 80 P14 –

88 Out –8 8 80 P15 –

Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)

Pin # Type

IOH IOL

Load Function Alt Alt

62 Out –8 8 80 ENAVDD – –

61 Out –8 8 80 ENAVEEENABKL –

54 I/O –8 8 80 ENABKL A27

VB1

53 I/O –8 8 80 ACTI A26

VB0

178 In – – – STNDBY# – –

PIN LIST - POWER MANAGEMENT

Pin # Type

IOH IOL

Load Function Alt

203 In – – – XTALI –

204 Out –2 2 50 XTALO –

205 Vcc – – – CVCC0 –

206 Vcc – – – CVCC1 –

202 Gnd – – – CGND0 –

208 Gnd – – – CGND1 –

PIN LIST - CLOCK

PIN PIST - PANEL INTERFACE

Revision 1.2 30 65540 / 545

PIN DESCRIPTIONS ISA / CPU Direct / VL-Bus Interface

Pin # Pin Name Type Active Description

207 RESET# In Low

22 ADS# In Low

(ALE) In High

31 M/IO# In Both

(AEN) In High

11 W/R# In Both

(MEMR#) In Low

23 RDYRTN# for 1x clock config In Low

CRESET for 2x clock config In High

(MEMW#) In Low

24 LRDY# Out/OC Low

(RDY) Out/OC High

25 LDEV# Out Low

(IOWR#) In Low

27 LCLK In Both

(IORD#) In Low

Revision 1.2 31 65540 / 545

Reset. For VL-Bus interfaces, connect to RESET#.

For direct CPU local bus interfaces, connect to the

system reset generated by the motherboard system logic

for all peripherals (not the RESET# pin of the

processor). For ISA bus interfaces, RESET must be

inverted before connection to this pin.

Address Strobe. In VL-Bus and CPU local bus inter-

faces indicates valid address and control signal infor-

mation is present. It is used for all decodes and to

indicate the start of a bus cycle.

Memory / IO. In VL-Bus and CPU local bus interfaces

indicates memory or I/O cycle: 1 = memory, 0 = I/O.

Write / Read. This control signal indicates a write

(high) or read (low) operation. It is sampled on the

rising edge of the (internal) 1x CPU clock when ADS#

is active.

Ready Return. Handshaking signal in VL-Bus interface

indicating synchronization of RDY# by the local bus

master / controller to the processor. Upon receipt of

this LCLK-synchronous signal the 65540 / 545 will

stop driving the bus (if a read cycle was active) and

terminate the current cycle.

Local Ready. Driven low during VL-Bus and CPU

local bus cycles to indicate the current cycle should be

completed. This signal is driven high at the end of the

cycle, then tri-stated. In ISA bus interfaces, this signal

is active high and may be connected directly to the ISA

bus RDY pin.

Local Device. In VL-Bus and CPU local bus interfaces,

this pin indicates that the 65540 / 545 owns the current

cycle based on the memory or I/O address which has

been broadcast. For VL-Bus, it is a direct output

reflecting a straight address decode.

Local Clock. In VL-Bus this pin is connected to the

CPU 1x clock. In CPU local bus interfaces it is

connected to the CPU 1x or 2x clock. If the input is a

2x clock, the processor reset signal must be connected

to CRESET (pin 23) for synchronization of the clock

phase.

Pin Descriptions

Note: Pin names in parentheses (...) indicate alternate functions (in this case, ISA bus control)

PIN DESCRIPTIONS ISA / CPU Direct / VL-Bus Interface

(continued)

Pin # Pin Name TypeActive Description

43 BE0# (A0) (BLE#) In Low

32 BE1# (BHE#) In Low

21 BE2# (A1) In Low

10 BE3# (RFSH#) In Low

179 A2 In High

180 A3 In High

182 A4 In High

183 A5 In High

185 A6 In High

186 A7 In High

187 A8 In High

188 A9 In High

189 A10 In High

190 A11 In High

191 A12 In High

192 A13 In High

193 A14 In High

194 A15 In High

195 A16 In High

196 A17 (LA17) In High

197 A18 (LA18) In High

198 A19 (LA19) In High

199 A20 (LA20) In High

200 A21 (LA21) In High

201 A22 (LA22) In High

28 A23 (LA23) In High

29 A24 (ROMCS#) (VOUT) I/O High

30 A25 (IRQ) (MOUT) I/O High

53 A26 (ACTI) (VB0)(GP0) I/O High

54 A27 (ENBKL)(VB1)(GP1) I/O High

Revision 1.2 32 65540 / 545

Byte Enable 0. Indicates data transfer on D7:D0 for the

current cycle. A0 address input in ISA interfaces. In

16-bit local bus interfaces indicates the low order byte at

the current (16-bit) word address is being accessed.

Byte Enable 1. Indicates data transfer on D15:D8 for

the current cycle. In ISA, indicates high order byte at

the current (16-bit) word address is being accessed.

Byte Enable 2. Indicates data transfer on D23:D16 for

the current cycle. A1 address in ISA & 16-bit local bus.

Byte Enable 3. BE3# indicates that data is to be trans-

ferred over the data bus on D31:24 during the current

access. Refresh input in ISA interfaces. Disconnected

in 16-bit local bus interfaces.

System Address Bus. In ISA, VL-Bus, and direct CPU

interfaces, the address pins are connected directly to the

bus. In 386 SX local bus interfaces BE2# is address

input A1, BE0# is BLE#, and BE1# is BHE#. In ISA

bus interfaces BE2# is address A1, BE0# is address

A0, BE1# is BHE#, A17-23 are LA17-23, and A24 is

ROMCS# (indicates valid ROM access to memory

address range 0C0000-0C7FFFh).

Address inputs through A23 are always available; A24-

27 may be optionally used for other functions:

In internal clock synthesizer test mode (TS#=0 at

Reset), A24 becomes VCLK out and A25 becomes

MCLK out.

A25 may alternately be used as a programmable polarity

IRQ output. Set when interrupt on VSYNC is enabled.

Cleared by reprogramming register 11h in the CRT

Controller. See also XR14 bit–7.

For 24-bit RGB Video input, A26-27 may be used as

the two lsbs of the Blue Video. Otherwise, A26 and

A27 may be used as General Purpose I/O pins or as

Activity Indicator and Enable Backlight respectively (see

panel interface pin descriptions and XR5C and XR72

for more details).

Pin Descriptions

Note: Pin names in parentheses (...) indicate alternate functions

PIN DESCRIPTIONS ISA / CPU Direct / VL-Bus Interface

(continued)

Pin # Pin Name Type Active Description

51 D00 I/O High

50 D01 I/O High

49 D02 I/O High

48 D03 I/O High

47 D04 I/O High

46 D05 I/O High

45 D06 I/O High

44 D07 I/O High

41 D08 I/O High

40 D09 I/O High

38 D10 I/O High

37 D11 I/O High

36 D12 I/O High

35 D13 I/O High

34 D14 I/O High

33 D15 I/O High

20 D16 (ZWS#) I/O High

19 D17 (MCS16#) I/O High

18 D18 (IOCS16#) I/O High

17 D19 I/O High

16 D20 I/O High

15 D21 I/O High

14 D22 I/O High

13 D23 I/O High

8 D24 I/O High

7 D25 I/O High

6 D26 I/O High

5 D27 I/O High

4 D28 I/O High

3 D29 I/O High

2 D30 I/O High

1 D31 I/O High

Revision 1.2 33 65540 / 545

System Data Bus.

In 32-bit CPU Local Bus designs these data lines

connect directly to the processor data lines. On the VL-

Bus they connect to the corresponding buffered or

unbuffered data signal.

In ISA bus interfaces, D16-18 become outputs for the

Zero Wait State, Memory Chip Select 16, and I/O Chip

Select 16 respectively. In ISA bus interfaces D19-31

are unused and should be left disconnected.

Pin Descriptions

Note: Pin names in parentheses (...) indicate alternate functions

PIN DESCRIPTIONS PCI Bus Interface

(65545 Only)

Pin # Pin Name Type Active Description

207 RESET# In Low

201 CLK In High

31 PAR I/O High

22 FRAME# In Low

23 IRDY# In Low

24 TRDY# S/TS Low

27 STOP# S/TS Low

25 DEVSEL# S/TS Low

Revision 1.2 34 65540 / 545

Reset. This input is used to bring signals and registers

in the chip to a consistent state. All outputs from the

chip are tri-stated or driven to an inactive state.

Bus Clock. This input provides the timing reference for

all bus transactions. All bus inputs except RESET# and

INTA# are sampled on the rising edge of CLK. CLK

may be any frequency from DC to 33MHz.

Parity. This signal is used to maintain even parity

across AD0-31 and C/BE0-3#. PAR is stable and valid

one clock after the address phase. For data phases PAR

is stable and valid one clock after either IRDY# is

asserted on a write transaction or TRDY# is asserted on

a read transaction. Once PAR is valid, it remains valid

until one clock after the completion of the current data

phase (i.e., PAR has the same timing as AD0-31 but

delayed by one clock). The bus master drives PAR for

address and write data phases; the target drives PAR

for read data phases.

Cycle Frame. Driven by the current master to indicate

the beginning and duration of an access. Assertion

indicates a bus transaction is beginning (while asserted,

data transfers continue); de-assertion indicates the

transaction is in the final data phase.

Initiator Ready. Indicates the bus master's ability to

complete the current data phase of the transaction.

During a write, IRDY# indicates valid data is present on

AD0-31; during a read it indicates the master is

prepared to accept data. A data phase is completed on

any clock when both IRDY# and TRDY# are sampled

asserted (wait cycles are inserted until this occurs).

Target Ready. Indicates the target's ability to complete

the current data phase of the transaction. During a read,

TRDY# indicates that valid data is present on AD0-31;

during a write it indicates the target is prepared to accept

data. A data phase is completed on any clock when

both IRDY# and TRDY# are sampled asserted (wait

cycles are inserted until this occurs).

Stop. Indicates the current target is requesting the

master to stop the current transaction.

Device Select. Indicates the current target has decoded

its address as the target of the current access.

Pin Descriptions

Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before

being released, and are not driven for at least one cycle after being released by the previous device. A pull-up provided by the

bus controller is used to maintain an inactive level between transactions.

PIN DESCRIPTIONS PCI Bus Interface

(65545 Only)

Pin # Pin Name Type Active Description

29 PERR# (VCLKOUT) S/TS Low

30 SERR# (MCLKOUT) OD Low

28 Reserved n/a n/a

179-180 Reserved n/a n/a

182-183 Reserved n/a n/a

185-200 Reserved n/a n/a

Revision 1.2 35 65540 / 545

Parity Error. This signal is for the reporting of data

parity errors (except for Special Cycles where SERR# is

used). The PERR# pin is Sustained Tri-state and is

driven active by the agent receiving the data for two

clocks following the data when a data parity error is

detected. PERR# will be driven high for one clock

before being tri-stated as with all sustained tri-state

signals. PERR# will not be reported until the 65545

has claimed the access by asserting DEVSEL# and

completing the data phase.

System Error. Used to report system errors where the

result will be catastrophic (address parity error, data

parity errors for Special Cycle commands, etc.). This

output is actively driven for a single PCI clock cycle

synchronous to CLK and meets the same setup and hold

time requirements as all other bused signals. SERR# is

not driven high by the 65545 after being asserted; it is

pulled high only by a weak pull-up provided by the

system, so SERR# on the PCI bus may take two or

three clock periods to fully return to an inactive state.

These pins are reserved for future use and should not be

connected. All the pins in this group are tri-stated at all

times in PCI interface mode.

Pin Descriptions

Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before

being released, and are not driven for at least one cycle after being released by the previous device. A central pull-up provided by

the bus controller is used to maintain an inactive level between transactions.

PIN DESCRIPTIONS PCI Bus Interface

(65545 Only)

Pin # Pin Name Type Active Description

51 AD00 I/O High

50 AD01 I/O High

49 AD02 I/O High

48 AD03 I/O High

47 AD04 I/O High

46 AD05 I/O High

45 AD06 I/O High

44 AD07 I/O High

41 AD08 I/O High

40 AD09 I/O High

38 AD10 I/O High

37 AD11 I/O High

36 AD12 I/O High

35 AD13 I/O High

34 AD14 I/O High

33 AD15 I/O High

20 AD16 I/O High

19 AD17 I/O High

18 AD18 I/O High

17 AD19 I/O High

16 AD20 I/O High

15 AD21 I/O High

14 AD22 I/O High

13 AD23 I/O High

8 AD24 I/O High

7 AD25 I/O High

6 AD26 I/O High

5 AD27 I/O High

4 AD28 I/O High

3 AD29 I/O High

2 AD30 I/O High

1 AD31 I/O High

43 C/BE0# In Low

32 C/BE1# In Low

21 C/BE2# In Low

10 C/BE3# In Low

11 IDSEL In High

Revision 1.2 36 65540 / 545

PCI Address / Data Bus

Address and data are multiplexed on the same pins. A

bus transaction consists of an address phase followed

by one or more data phases (both read and write bursts

are allowed by the bus definition).

The address phase is the clock cycle in which FRAME#

is asserted (AD0-31 contain a 32-bit physical address).

For I/O, the address is a byte address, for memory and

configuration, the address is a DWORD address.

During data phases AD0-7 contain the LSB and 24-31

contain the MSB. Write data is stable and valid when

IRDY# is asserted and read data is stable and valid

when TRDY# is asserted. Data is transferred during

those clocks when both IRDY# and TRDY# are

asserted.

Bus Command / Byte Enables. During the address

phase of a bus transaction, these pins define the bus

command (see list above). During the data phase, these

pins are byte enables that determine which byte lanes

carry meaningful data: byte 0 corresponds to AD0-7,

byte 1 to 8-15, byte 2 to 16-23, and byte 3 to 24-31.

Initialization Device Select. Used as a chip select during

configuration read and write transactions.

Pin Descriptions

C/BE3-0 Command Type 65545

0000 Interrupt Acknowledge

0001 Special Cycle

0010 I/O Read 4

0011 I/O Write 4

0100 -reserved-

0101 -reserved-

0110 Memory Read 4

0111 Memory Write 4

1000 -reserved-

1001 -reserved-

1010 Configuration Read 4

1011 Configuration Write 4

1100 Memory Read Multiple

1101 Dual Address Cycle

1110 Memory Read Line

1111 Memory Read & Invalidate

PIN DESCRIPTIONS Display Memory Interface

Pin # Pin Name Type Active Description

145 AA0 (LB#) (CFG0) I/O High

146 AA1 (ISA#) (CFG1) I/O High

147 AA2 (2X#) (CFG2) I/O High

148 AA3 (Reserved)(CFG3) I/O High

149 AA4 (Reserved)(CFG4) I/O High

150 AA5 (OS#) (CFG5) I/O High

151 AA6 (AD#) (CFG6) I/O High

152 AA7 (TS#) (CFG7) I/O High

153 AA8 (LV#) (CFG8) I/O High

154 AA9 (32KHz) (VR0) I/O High

90 CA0 (P16) Out High

91 CA1 (P17) Out High

92 CA2 (P18) Out High

93 CA3 (P19) Out High

94 CA4 (P20) Out High

95 CA5 (P21) Out High

96 CA6 (P22) Out High

97 CA7 (P23) Out High

98 CA8 (VG1) I/O High

99 CA9 (VG0) I/O High

156 RASA# Out Low

123 RASB# Out Low

101 RASC# Out Low

(KEY) In High

160 CASAL# (WEAL#) Out Low

159 CASAH# (CASA#) Out Low

126 CASBL# (WEBL#) Out Low

125 CASBH# (CASB#) Out Low

104 CASCL# (WECL#) (VR6) I/O Both

103 CASCH# (CASC#) (VR7) I/O Both

157 WEA# (WEAH#) Out Low

124 WEB# (WEBH#) Out Low

102 WEC# (WECH#) (PCLK) Out Both

155 OEAB# Out Low

100 OEC# (VR1) I/O Both

Revision 1.2 37 65540 / 545

Address bus for DRAMs A and B.

Please see the configuration table in the Extended

configuration options (XR01 and XR6C).

AA9, alternately, becomes clock input for refresh of

non-self-refresh DRAMs and panel power sequencing

or video input red lsb.

Address bus for DRAM C.

Row address strobe for DRAM A

Row address strobe for DRAM B

Row address strobe for DRAM C

or color key input from external video source

Column address strobe for the DRAM A lower byte

Column address strobe for the DRAM A upper byte

Column address strobe for the DRAM B lower byte

Column address strobe for the DRAM B upper byte

CAS for the DRAM C lower byte or video in red bit-6

CAS for the DRAM C upper byte or video in red bit-7

Write enable for DRAM A

Write enable for DRAM B

Write enable for DRAM C or video in port PCLK out

Output enable for DRAMs A and B

Output enable for DRAM C or video in red bit-1

Pin Descriptions

Note: Pin names in parentheses (...) indicate alternate functions

PIN DESCRIPTIONS Display Memory Interface (continued)

Pin # Pin Name Type Active Description

162 MAD0 (TSENA#) I/O High

163 MAD1 (ICTENA#) I/O High

164 MAD2 I/O High

165 MAD3 I/O High

166 MAD4 I/O High

167 MAD5 I/O High

168 MAD6 I/O High

169 MAD7 I/O High

170 MAD8 I/O High

171 MAD9 I/O High

172 MAD10 I/O High

173 MAD11 I/O High

174 MAD12 I/O High

175 MAD13 I/O High

176 MAD14 I/O High

177 MAD15 I/O High

127 MBD0 I/O High

128 MBD1 I/O High

129 MBD2 I/O High

130 MBD3 I/O High

131 MBD4 I/O High

132 MBD5 I/O High

133 MBD6 I/O High

134 MBD7 I/O High

135 MBD8 I/O High

136 MBD9 I/O High

137 MBD10 I/O High

138 MBD11 I/O High

140 MBD12 I/O High

141 MBD13 I/O High

143 MBD14 I/O High

144 MBD15 I/O High

106 MCD0 (VB2) I/O High

107 MCD1 (VB3) I/O High

109 MCD2 (VB4) I/O High

110 MCD3 (VB5) I/O High

111 MCD4 (VB6) I/O High

112 MCD5 (VB7) I/O High

113 MCD6 (VG2) I/O High

114 MCD7 (VG3) I/O High

115 MCD8 (VG4) I/O High

116 MCD9 (VG5) I/O High

117 MCD10 (VG6) I/O High

118 MCD11 (VG7) I/O High

119 MCD12 (VR2) I/O High

120 MCD13 (VR3) I/O High

121 MCD14 (VR4) I/O High

122 MCD15 (VR5) I/O High

Revision 1.2 38 65540 / 545

Memory data bus for DRAM A (lower 512KB of

display memory)

Memory data bus for DRAM B (upper 512KB)

Memory data bus for DRAM C (Frame Buffer)

When a frame buffer DRAM is not required, this bus

may optionally be used to input up to 24 bits of RGB

data from an external PC-Video subsystem. For the

remaining pins of the 24-bit video input port see the pin

descriptions of DRAM C address, DRAM C control,

AA9, ACTI, and ENABKL. Note that this configu-

ration also provides for additional panel outputs so that

a full 24-bit video input port may be implemented along

with a 24-bit true-color TFT panel (TFT panels never

need DRAM C).

Pin Descriptions

Note: Pin names in parentheses (...) indicate alternate functions.

Note: If ICTENA# is low with RESET# low, a rising edge on XTALI will put the chip into 'In Circuit Test' mode. In ICT mode, all digital

signal pins become inputs which are part of a long path starting at ENAVDD (pin 62) and proceeding to lower pin numbers around the

chip to pin 1 then to pin 208 and ending at VSYNC (pin 64). If all pins in the path are high, the VSYNC output will be high. If any

pin is low, the VSYNC output will be low. Thus the chip can be checked in circuit to determine if all pins are connected properly by

toggling all pins one at a time and observing the effect on VSYNC. XTALI must be toggled last because rising edges on XTALI with

ICTENA# high or RESET# high will exit ICT mode. As a side effect, ICT mode effectively 3-states all pins except VSYNC. If TSENA# is

low with RESET # low, a rising edge on XTALI will 3-state all pins. An XTALI rising edge without the enabling conditions exits 3-state.

PIN DESCRIPTIONS Flat Panel Display Interface

Pin # Pin Name Type Active Description

71 P0 Out High

72 P1 Out High

73 P2 Out High

74 P3 Out High

75 P4 Out High

76 P5 Out High

78 P6 Out High

79 P7 Out High

81 P8 (SHFCLKU) Out High

82 P9 Out High

83 P10 Out High

84 P11 Out High

85 P12 Out High

86 P13 Out High

87 P14 Out High

88 P15 Out High

70 SHFCLK (CL2) (SHFCLKL) Out High

67 FLM Out High

68 LP (CL1) (DE) (BLANK#) Out High

69 M (DE) (BLANK#) Out High

62 ENAVDD Out High

61 ENAVEE (ENABKL) Out High

53 ACTI (GP0)(VB0)(A26) I/O High

54 ENABKL (GP1)(VB1)(A27) I/O High

Revision 1.2 39 65540 / 545

8, 9, 12, or 16-bit flat panel data output. 18-bit and 24-

bit panel interfaces may also be supported (see CA0-7

for P16-23). Refer to the table below for configurations

for various panel types.

Shift Clock. Pixel clock for flat panel data.

First Line Marker. Flat Panel equivalent of VSYNC.

Latch Pulse. Flat Panel equivalent of HSYNC.

M signal for panel AC drive control (may also be called

ACDCLK). May also be configured as BLANK# or as

Display Enable (DE) for TFT Panels (see XR4F bit-6).

Power sequencing controls for panel driver electronics

voltage VDD and panel LCD bias voltage VEE

Activity Indicator and Enable Backlight outputs. May

be configured for other functions (see Extension

Registers XR5C and XR72 and pin descriptions of

MCD0-15 and A26/A27 for more information).

Pin Descriptions

Mono Mono Mono Color Color Color Color STN Color Color Color

6554x 6554x SS DD DD TFT TFT TFT HR STN SS STN SS STN DD STN DD

Pin# Pin Name 8-bit 8-bit 16-bit 9/12/16-bit 18/24-bit 18/24-bit 8-bit (X4bP) 16-bit (4bP) 8-bit (4bP)

16-bit (4bP)

71 P0 – UD3 UD7 B0 B0 B00 R1... R1... UR1... UR0...

72 P1 – UD2 UD6 B1 B1 B01 B1... G1... UG1... UG0...

73 P2 – UD1 UD5 B2 B2 B02 G2... B1... UB1... UB0...

74 P3 – UD0 UD4 B3 B3 B03 R3... R2... UR2... UR1...

75 P4 – LD3 UD3 B4 B4 B10 B3... G2... LR1... LR0...

76 P5 – LD2 UD2 G0 B5 B11 G4... B2... LG1... LG0...

78 P6 – LD1 UD1 G1 B6 B12 R5... R3... LB1... LB0...

79 P7 – LD0 UD0 G2 B7 B13 B5... G3... LR2... LR1...

81 P8 P0 – LD7 G3 G0 G00 SHFCLKU B3... – UG1...

82 P9 P1 – LD6 G4 G1 G01 – R4... – UB1...

83 P10 P2 – LD5 G5 G2 G02 – G4... – UR2...

84 P11 P3 – LD4 R0 G3 G03 – B4... – UG2...

85 P12 P4 – LD3 R1 G4 G10 – R5... – LG1...

86 P13 P5 – LD2 R2 G5 G11 – G5... – LB1...

87 P14 P6 – LD1 R3 G6 G12 – B5... – LR2...

88 P15 P7 – LD0 R4 G7 G13 – R6... – LG2...

90 P16 – – – – R0 R00 – – – –

91 P17 – – – – R1 R01 – – – –

92 P18 – – – – R2 R02 – – – –

93 P19 – – – – R3 R03 – – – –

94 P20 – – – – R4 R10 – – – –

95 P21 – – – – R5 R11 – – – –

96 P22 – – – – R6 R12 – – – –

97 P23 – – – – R7 R13 – – – –

70 SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLKL SHFCLK SHFCLK SHFCLK

Pixels / Clock: 8 8 16 1 1 2 2-2/3 5-1/3 2-2/3 5-1/3

PIN DESCRIPTIONS CRT and Clock Interface

Pin # Pin Name Type Active Description

65 HSYNC Out Both

64 VSYNC Out Both

60 RED Out High

58 GREEN Out High

57 BLUE Out High

55 RSET In n/a

59 AVCC VCC --

56 AGND GND --

203 XTALI (MCLK) I/O High

204 XTALO Out High

205 CVCC0 VCC --

202 CGND0 GND --

206 CVCC1 VCC --

208 CGND1 GND --

Revision 1.2 40 65540 / 545

CRT Horizontal Sync (polarity is programmable)

CRT Vertical Sync (polarity is programmable)

CRT analog video outputs from the internal color palette

DAC.

Set point resistor for the internal color palette DAC. A

270Ω 1% resistor is required between RSET and

AGND.

Analog power and ground pins for noise isolation for

the internal color palette DAC. AVCC should be

isolated from digital VCC as described in the Functional

Description of the internal color palette DAC. AGND

should be common with digital ground but must be

tightly decoupled to AVCC. See the Functional

Description of the internal color palette DAC for further

information.

Crystal In. When the internal clock synthesizer is used,

this pin serves as either the series resonant crystal input

or as the input for an external reference oscillator

(usually 14.31818 MHz). Note that in test mode for the

internal clock synthesizer, MCLK is output on A25 (pin

30) and VCLK is output on A24 (pin 29).

Crystal Out. When the internal oscillator is used, this

pin serves as the series resonant crystal output. When

an external oscillator is used, this pin must be left

disconnected.

Analog power and ground pins for noise isolation for

the internal clock synthesizer. Must be the same as

VCC for internal logic. VCC/GND pair 0 and

VCC/GND pair 1 pins must be carefully decoupled

individually. Refer also to the section on clock ground

layout in the Functional Description. Note that the

CVCC voltage must be the same as the voltage for the

internal logic (IVCC).

Pin Descriptions

Note: Pin names in parentheses (...) indicate alternate functions

Revision 1.2 41 65540 / 545

Pin Descriptions

6554x Pin # Signal Name Signal Status Signal Polarity

67 FLM Forced Low XR54 bit 7

68 LP Forced Low XR54 bit 6

70 SHFCLK Forced Low N/A

69 M Forced Low N/A

71 P0 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

72 P1 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

73 P2 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

74 P3 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

75 P4 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

76 P5 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

78 P6 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

79 P7 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

81 P8 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

82 P9 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

83 P10 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

84 P11 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

85 P12 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

86 P13 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

87 P14 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

88 P15 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

90 P16/CA0 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

91 P17/CA1 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

92 P18/CA2 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

93 P19/CA3 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

94 P20/CA4 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

95 P21/CA5 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

96 P22/CA6 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

97 P23/CA7 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics)

62 ENAVDD Forced Low N/A

61 ENAVEE Forced Low N/A

54 ENABKL/A27 Forced Low N/A

65 HSYNC Forced Low N/A

64 VSYNC Forced Low N/A

53 ACTI/A26 Forced Low N/A

60,58,57 R,G,B Forced Low N/A

Notes:

1These pins are inputs when using the video input port. These pins are driven as outputs when using a frame buffer DRAM.

CRT / Panel Output Signal Status During Standby Mode

6554x Pin # Signal Name Signal Status

156 RASA# Driven Low

123 RASB# Driven Low

101 RASC# Driven Low (see note 1)

157 WEA# Driven High

124 WEB# Driven High

102 WEC# Driven High (see note 1)

160 CASAL# Driven Low

159 CASAH# Driven Low

126 CASBL# Driven Low

125 CASBH# Driven Low

104 CASCL# Driven Low (see note 1)

103 CASCH# Driven Low (see note 1)

155 OEAB# Driven High

100 OEC# Driven High (see note 1)

154-145 AA9-0 Pulled low with weak resistor

99-90 CA9-0 Driven Low

177-162 MAD15-0 Pulled low with weak resistor

144-143,141-140,138-127 MBD15-0 Pulled low with weak resistor

122-109,107-66 MCD15-0 Pulled low with weak resistor (see note 1)

Display Memory Output Signal Status During Standby Mode

Revision 1.2 42 65540 / 545

PIN DESCRIPTIONS Power / Ground and Standby Control

Pin # Pin Name Type Active Description

178 STNDBY# In Low

80 IVCC Vcc –

77 IGND Gnd –

181 IVCC Vcc –

184 IGND Gnd –

9 BVCC Vcc –

12 BGND Gnd –

26 BGND Gnd –

42 BVCC Vcc –

39 BGND Gnd –

52 BGND Gnd –

66 DVCC Vcc –

63 DGND Gnd –

89 DGND Gnd –

158 MVCCA Vcc –

161 MGNDA Gnd –

142 MVCCB Vcc –

139 MGNDB Gnd –

108 MVCCC Vcc – Power

105 MGNDC Gnd –

Standby Control Pin. Pulling this pin to ground places

the 65540 / 545 in Standby Mode.

Power / Ground (Internal Logic). 5V±10% or 3.3V

±0.3V. Note that this voltage must be the same as

CVCC (voltage for internal clock synthesizer).

Power / Ground (Bus Interface). 5V±10% or 3.3V

±0.3V.

Power / Ground (Display Interface). 5V±10% or 3.3V

±0.3V.

Power / Ground (Memory Interface A). 5V±10% or

3.3V ±0.3V.

Power / Ground (Memory Interface B). 5V±10% or

3.3V ±0.3V.

Power / Ground (Memory Interface C). 5V±10% or

3.3V ±0.3V.

Pin Descriptions

Notes:

1The XTALO pin will always be driven except when XR33 bit-2 is set to '1'.

Bus / Clock Output Signal Status During Standby Mode

Signal Status

6554x Pin # Signal Name VL-Bus ISA Bus

204 XTALO Driven (see note 1) Driven (see note 1)

29 ROMCS# / A24 N/A Driven High

30 IRQ / A25 N/A Tri-Stated

53 ACTI / A26 (see previous page) N/A

54 ENABKL / A27 (see previous page) N/A

24 LRDY# / RDY Tri-Stated Tri-Stated

25 LDEV# Driven High N/A

51-44, 41-40,38-33 D0-15 Tri-Stated Tri-Stated

20 D16 / ZWS# Tri-Stated Tri-Stated

19 D17 / MCS16# Tri-Stated Tri-Stated

18 D18 / IOCS16# Tri-Stated Tri-Stated

17-13, 8-1 D19-31 Tri-Stated Tri-Stated

Revision 1.2 43 65540 / 545

I/O Map

Port Address Read Write

102 Global Enable (ISA Bus Only) Global Enable (ISA Bus Only)

3B0 Reserved for MDA/Hercules Reserved for MDA/Hercules

3B1 Reserved for MDA/Hercules Reserved for MDA/Hercules

3B2 Reserved for MDA/Hercules Reserved for MDA/Hercules

3B3 Reserved for MDA/Hercules Reserved for MDA/Hercules

3B4 CRTC Index CRTC Index

3B5 CRTC Data CRTC Data

3B6 Reserved for MDA/Hercules Reserved for MDA/Hercules

3B7 Reserved for MDA/Hercules Reserved for MDA/Hercules

3B8 Hercules Mode Register (MODE) Hercules Mode Register (MODE)

3B9 -- Set Light Pen FF (ignored)

3BA Status Register (STAT) Feature Control Register (FCR)

3BB -- Clear Light Pen FF (ignored)

3BC

3BD

3BE

3BF Hercules Configuration Register (HCFG) Hercules Configuration Register (HCFG)

3C0 Attribute Controller Index / Data Attribute Controller Index / Data

3C1 Attribute Controller Index / Data Attribute Controller Index / Data

3C2 Feature Read Register (FEAT) Miscellaneous Output Register (MSR)

3C3 Video Subsystem Enable (VSE)(LB Only) Video Subsystem Enable (VSE)(LB Only)

3C4 Sequencer Index Sequencer Index

3C5 Sequencer Data Sequencer Data

3C6 Color Palette Mask Color Palette Mask

3C7 Color Palette State Color Palette Read Mode Index

3C8 Color Palette Write Mode Index Color Palette Write Mode Index

3C9 Color Palette Data Color Palette Data

3CA Feature Control Register (FCR) --

3CB -- --

3CC Miscellaneous Output Register (MSR) --

3CD -- --

3CE Graphics Controller Index Graphics Controller Index

3CF Graphics Controller Data Graphics Controller Data

n3D0† 32-Bit DR Register Extensions (65545 only) 32-Bit DR Register Extensions (65545 only)

n3D1† 32-Bit DR Register Extensions (65545 only) 32-Bit DR Register Extensions (65545 only)

n3D2† 32-Bit DR Register Extensions (65545 only) 32-Bit DR Register Extensions (65545 only)

n3D3† 32-Bit DR Register Extensions (65545 only) 32-Bit DR Register Extensions (65545 only)

03D4 CRTC Index CRTC Index

03D5 CRTC Data CRTC Data

03D6 CHIPS™ Extensions Index CHIPS™ Extensions Index

03D7 CHIPS™ Extensions Data CHIPS™ Extensions Data

03D8 CGA Mode Register (MODE) CGA Mode Register (MODE)

03D9 CGA Color Register (COLOR) CGA Color Register (COLOR)

03DA Status Register (STAT) Feature Control Register (FCR)

03DB -- Clear Light Pen FF (ignored)

03DC -- Set Light Pen FF (ignored)

46E8 -- Setup Control (ISA Bus Only)

I/O Map

Color

Mode

Mono

Mode

Reserved for system parallel port

†32-Bit register addresses are of the form 'bnnn nn1b bbbb bb00' where 'bbbbbbbb' is

specified by I/O base register XR07 and 'nnnnn' specifies 1 of 32 DRxx 32-bit registers

ST00 (STAT) Display Status 7 R 3BA 3DA

CLPEN Clear Light Pen Flip Flop 0 W(n/a) 3BB (ignored) 3DB (ignored) ref only: no light pen

SLPEN Set Light Pen Flip Flop 0 W(n/a) 3B9 (ignored) 3DC (ignored) ref only: no light pen

MODE CGA/MDA/Hercules Mode Control 7 R/W 3B8 3D8

COLOR CGA Color Select 6 R/W n/a 3D9 R/W at XR7E also

HCFG Hercules Configuration 2 W 3BF n/a

R 3D6-3D7 index 14 n/a XR14

RX, R0-11 '6845' Registers 0-8 R/W 3B4-3B5 3D4-3D5

XRX, XR0-7F Extension Registers 0-8 R/W 3D6-3D7 3D6-3D7

VSE Video Subsystem Enable 1 W 3C3 if LB 3C3 if LB Disabled by XR70 bit-7

SETUP Setup Control 2 W 46E8 if ISA 46E8 if ISA Disabled by XR70 bit-7

ENABLE Global Enable 1 R/W 102 if ISA 102 if ISA Setup Only in ISA Bus

PR0-17 PCI Configuration 8, 16, 32 R/W System Dependent System Dependent PCI Bus Only

MSR Miscellaneous Output 7 W 3C2 3C2

R 3CC 3CC

FCR Feature Control 3 W 3BA 3DA

R 3CA 3CA

ST00 (FEAT) Feature Read (Input Status 0) 4 R 3C2 3C2

ST01 (STAT) Display Status (Input Status 1) 6 R 3BA 3DA

CLPEN Clear Light Pen Flip Flop 0 W(n/a) 3BB (ignored) 3DB (ignored) Ref only: No light pen

SLPEN Set Light Pen Flip Flop 0 W(n/a) 3B9 (ignored) 3DC (ignored) Ref only: No light pen

DACMASK Color Palette Pixel Mask 8 R/W 3C6 3C6

DACSTATE Color Palette State 2 R 3C7 3C7

DACRX Color Palette Read-Mode Index 8 W 3C7 3C7

DACWX Color Palette Write-Mode Index 8 R/W 3C8 3C8

DACDATA Color Palette Data 0-FF 3x6 R/W 3C9 3C9

SRX, SR0-7 Sequencer 0-8 R/W 3C4-3C5 3C4-3C5

CRX, CR0-3F CRT Controller 0-8 R/W 3B4-3B5 3D4-3D5

GRX, GR0-8 Graphics Controller 0-8 R/W 3CE-3CF 3CE-3CF

ARX, AR0-14 Attributes Controller 0-8 R/W 3C0-3C1 3C0-3C1

XRX, XR0-7F Extension Registers 0-8 R/W 3D6-3D7 3D6-3D7

DR00-DR0C 32-Bit Extension Registers 32 R/W n3D0-n3D3 n3D0-n3D3

Programmable I/O address

Revision 1.2 44 65540 / 545

MSR Miscellaneous Output 7 W 3C2 3C2

FCR Feature Control 3 W 3BA 3DA

ST00 (FEAT) Feature Read (Input Status 0) 4 R 3C2 3C2

ST01 (STAT) Display Status (Input Status 1) 7 R 3BA 3DA

CLPEN Clear Light Pen Flip Flop 0 W(n/a) 3BB (ignored) 3DB (ignored) ref only: no light pen

SLPEN Set Light Pen Flip Flop 0 W(n/a) 3B9 (ignored) 3DC (ignored) ref only: no light pen

SRX, SR0-7 Sequencer 0-8 R/W 3C4-3C5 3C4-3C5

CRX, CR0-3F CRT Controller 0-8 R/W 3B4-3B5 3D4-3D5

GRX, GR0-8 Graphics Controller 0-8 R/W 3CE-3CF 3CE-3CF

ARX, AR0-14 Attributes Controller 0-8 R/W 3C0-3C1 3C0-3C1

XRX, XR0-7F Extension Registers 0-8 R/W 3D6-3D7 3D6-3D7

SRX Sequencer Index 3 VGA/EGA R/W R/W 3C4

SR0 Reset 2 VGA/EGA R/W R/W 3C5

SR1 Clocking Mode 6 VGA/EGA R/W R/W 3C5

SR2 Plane Mask 4 VGA/EGA R/W R/W 3C5

SR3 Character Map Select 6 VGA/EGA R/W R/W 3C5

SR4 Memory Mode 3 VGA/EGA R/W R/W 3C5

SR7 Reset Horizontal Character Counter 0 VGA W n/a 3C5

CRX CRTC Index 6 VGA/EGA R/W R/W 3B4 Mono, 3D4 Color

CR0 Horizontal Total 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR1 Horizontal Display End 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR2 Horizontal Blanking Start 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR3 Horizontal Blanking End 5+2+1 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR4 Horizontal Retrace Start 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR5 Horizontal Retrace End 5+2+1 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR6 Vertical Total 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR7 Overflow 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR8 Preset Row Scan 5+2 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR9 Character Cell Height 5+3 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CRA Cursor Start 5+1 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CRB Cursor End 5+2 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CRC Start Address High 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CRD Start Address Low 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CRE Cursor Location High 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CRF Cursor Location Low 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

LPENH Light Pen High 8 VGA/EGA R R 3B5 Mono, 3D5 Color

LPENL Light Pen Low 8 VGA/EGA R R 3B5 Mono, 3D5 Color

CR10 Vertical Retrace Start 8 VGA/EGA R/W W 3B5 Mono, 3D5 Color

CR11 Vertical Retrace End 4+4 VGA/EGA R/W W 3B5 Mono, 3D5 Color

CR12 Vertical Display End 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR13 Offset 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR14 Underline Row Scan 5+2 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR15 Vertical Blanking Start 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR16 Vertical Blanking End 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR17 CRT Mode Control 7 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR18 Line Compare 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color

CR22 Graphics Controller Data Latches 8 VGA R n/a 3B5 Mono, 3D5 Color

CR24 Attribute Controller Index/Data Latch 1 VGA R n/a 3B5 Mono, 3D5 Color

GRX Graphics Controller Index 4 VGA/EGA R/W R/W 3CE

GR0 Set/Reset 4 VGA/EGA R/W R/W 3CF

GR1 Enable Set/Reset 4 VGA/EGA R/W R/W 3CF

GR2 Color Compare 4 VGA/EGA R/W R/W 3CF

GR3 Data Rotate 5 VGA/EGA R/W R/W 3CF

GR4 Read Map Select 2 VGA/EGA R/W R/W 3CF

GR5 Mode 6 VGA/EGA R/W R/W 3CF

GR6 Miscellaneous 4 VGA/EGA R/W R/W 3CF

GR7 Color Don't Care 4 VGA/EGA R/W R/W 3CF

GR8 Bit Mask 8 VGA/EGA R/W R/W 3CF

ARX Attribute Controller Index 6 VGA/EGA R/W R/W 3C0 (3C1)

AR0-F Internal Palette Regs 0-15 6 VGA/EGA R/W R/W 3C0 (3C1)

AR10 Mode Control 7 VGA/EGA R/W R/W 3C0 (3C1)

AR11 Overscan Color 6 VGA/EGA R/W R/W 3C0 (3C1)

AR12 Color Plane Enable 6 VGA/EGA R/W R/W 3C0 (3C1)

AR13 Horizontal Pixel Panning 4 VGA/EGA R/W R/W 3C0 (3C1)

AR14 Color Select 4 VGA R/W n/a 3C0 (3C1)

Revision 1.2 45 65540 / 545

Reg Register Name Bits Access Port Reset 82C450 64300/310 65510 65530 65535

XRX Extension Index Register 7R/W 3D6 -xxxxxxx 3 3 3 3 3

XR00 Chip Version (65540: v=0; 65545: v=1) 8R/O 3D7 1 1 0 1 v r r r 3 3 3 3 3

XR01 Configuration 8 R/O 3D7 dddddddd 3 3 3 3 3

XR02 CPU Interface Control 1 8R/W 3D7 00000000 3 3 3 3 3

XR03 CPU Interface Control 2 (ROM Intfc) 2 R/W 3D7 - - - - - - 0 x . 3...

XR04 Memory Control 1 4R/W 3D7 - - 0 - - 0 0 0 3 3 3 3 3

XR05 Memory Control 2 (Clock Control) 8 R/W 3D7 00000000 . 3. . 3

XR06 Palette Control (DRAM Intfc) 8R/W 3D7 00000000 . 3 3 3 3

XR07 I/O Base ( 65545 Only ) 8 R/W 3D7 11110100 . 3...

XR08 Linear Addressing Base (Linear Base L) 8R/W 3D7 xxxxxxxx . 3. . 3

XR09 -reserved- (Linear Base H) -- -- 3D7 .3...

XR0A -reserved- (XRAM Mode) -- -- 3D7 .3...

XR0B CPU Paging 5 R/W 3D7 - - 0 0 • 0 0 0 3 3 3 3 3

XR0C Start Address Top 2R/W 3D7 - - - - - - x x 3 3 3 3 3

XR0D Auxiliary Offset 2R/W 3D7 - - - - - - 0 0 3 3 3 3 3

XR0E Text Mode Control 6R/W 3D7 0 0 0 0 0 0 - - 3 3 3 3 3

XR0F Software Flags 0 8R/W 3D7 xxxxxxxx . 3 3 3 3

XR10 Single/Low Map 8R/W 3D7 xxxxxxxx 3 3 3 3 3

XR11 High Map 8R/W 3D7 xxxxxxxx 3 3 3 3 3

XR12 -reserved- -- -- 3D7 . . . . .

XR13 -reserved- -- -- 3D7 . . . . .

XR14 Emulation Mode 8R/W 3D7 0000hh00 3 3 3 3 3

XR15 Write Protect 8R/W 3D7 00000000 3 3 3 3 3

XR16 Vertical Overflow 5 R/W 3D7 • 0 • 0 • 0 0 0 . 3. . 3

XR17 Horizontal Overflow 7 R/W 3D7 •0000000 . 3. . 3

XR18 Alternate H Disp End 8R/W 3D7 xxxxxxxx 3 3 3 3 3

XR19 Alternate H Sync Start (Half-line) 8 R/W 3D7 xxxxxxxx 3 3 3 3 3

XR1A Alternate H Sync End 8R/W 3D7 xxxxxxxx 3 3 3 3 3

XR1B Alternate H Total 8R/W 3D7 xxxxxxxx 3 3 3 3 3

XR1C Alternate Blank Start / H Panel Size 8R/W 3D7 xxxxxxxx 3 3 3 3 3

XR1D Alternate H Blank End 8R/W 3D7 0xxxxxxx 3 3 3 3 3

XR1E Alternate Offset 8R/W 3D7 xxxxxxxx 3 3 3 3 3

XR1F Virtual EGA Switch Register 5R/W 3D7 0 - - - x x x x 3 3 3 3 3

XR20 -reserved- -- -- 3D7 . . . . .

XR21 -reserved- -- -- 3D7 . . . 3.

XR22 -reserved- -- -- 3D7 . . . 3.

XR23 -reserved- -- -- 3D7 . . . 3.

XR24 FP AltMaxScanline 5 R/W 3D7 • • • x x x x x . . 333

XR25 FP AltTxtHVirtPanel Size 8R/W 3D7 x x x x x x x x . . . 3 3

XR26 Alt HSync Start 8R/W 3D7 x x x x x x x x . . . . 3

XR27 -reserved- -- -- 3D7 . . . . .

XR28 Video Interface 5R/W 3D7 0 0 0 0 - - 0 - 3 3 3 3 3

XR29 Half Line Compare 8 R/W 3D7 x x x x x x x x . . . . .

XR2A -reserved- -- -- 3D7 . . . . .

XR2B Software Flags 1 8 R/W 3D7 00000000 3 3 3 3 3

XR2C FLM Delay 8R/W 3D7 x x x x x x x x . . 333

XR2D LP Delay 8 R/W 3D7 x x x x x x x x . . 333

XR2E LP Delay 8 R/W 3D7 x x x x x x x x . . . 3 3

XR2F LP Width 8R/W 3D7 x x x x x x x x . . 333

EXTENSION REGISTER SUMMARY: 00-2F

Revision 1.2 46 65540 / 545

Reset Codes: x = Not changed by RESET (indeterminate on power-up) – = Not implemented (always reads 0)

d = Set from the corresponding data bus pin on falling edge of RESET • = Reserved (read/write, reset to 0)

h = Read-only Hercules Configuration Register Readback bits 0/1 = Reset to 0/1 by trailing edge of reset

r = Chip revision # (starting from 0000)

Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column

Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD)

CHIPS' VGA Product Family

Reg Register Name Bits Access Port Reset 82C450 64300/310 65510 65530 65535

XR30 Clock Divide Control 4R/W 3D7 • • • • x x x x . 3. . 3

XR31 Clock M-Divisor 7 R/W 3D7 • x x x x x x x . 3. . 3

XR32 Clock N-Divisor 7 R/W 3D7 • x x x x x x x . 3. . 3

XR33 Clock Control 7 R/W 3D7 0 0 0 0 • 0 0 0 . 3. . 3

XR34 -reserved- -- -- 3D7 . . . . .

XR35 -reserved- -- -- 3D7 . . . . .

XR36 -reserved- -- -- 3D7 . . . . .

XR37 -reserved- -- -- 3D7 . . . . .

XR38 -reserved- -- -- 3D7 . . . . .

XR39 -reserved- -- -- 3D7 . . . . .

XR3A Color Key 0 8 R/W 3D7 x x x x x x x x . 3. . 3

XR3B Color Key 1 8 R/W 3D7 x x x x x x x x . 3. . 3

XR3C Color Key 2 8 R/W 3D7 x x x x x x x x . 3. . 3

XR3D Color Key Mask 0 8 R/W 3D7 x x x x x x x x . 3. . 3

XR3E Color Key Mask 1 8 R/W 3D7 x x x x x x x x . 3. . 3

XR3F Color Key Mask 2 8 R/W 3D7 x x x x x x x x . 3. . 3

XR40 BitBLT Configuration ( 65545 Only ) 2R/W 3D7 - - - - - - x x . 3...

XR41 -reserved- -- -- 3D7 . . . . .

XR42 -reserved- -- -- 3D7 . . . . .

XR43 -reserved- -- -- 3D7 . . . . .

XR44 Software Flag Register 2 8R/W 3D7 x x x x x x x x . 3 3 3 3

XR45 Software Flag Register 3 8R/W 3D7 x x x x x x x x . . . . 3

XR46 -reserved- -- -- 3D7 . . . . .

XR47 -reserved- -- -- 3D7 . . . . .

XR48 -reserved- -- -- 3D7 . . . . .

XR49 -reserved- -- -- 3D7 . . . . .

XR4A -reserved- -- -- 3D7 . . . . .

XR4B -reserved- -- -- 3D7 . . . . .

XR4C -reserved- -- -- 3D7 . . . . .

XR4D -reserved- -- -- 3D7 . . . . .

XR4E -reserved- -- -- 3D7 . . . . .

XR4F Panel Format 2 5R/W 3D7 x x • • • x x x . . . . 3

XR50 Panel Format 1 8R/W 3D7 x x x x x x x x . . 333

XR51 Display Type 7R/W 3D7 0 0 0 • 0 0 0 0 . . 333

XR52 Power Down Control 8R/W 3D7 0 0 0 0 0 0 0 1 . 3 3 3 3

XR53 Panel Format 3 7R/W 3D7 • 0 0 0 0 0 x 0 . . 333

XR54 Panel Interface 8R/W 3D7 x x x x x x x x . . 333

XR55 H Compensation 6R/W 3D7 x x x x • • x x . . 333

XR56 H Centering 8R/W 3D7 x x x x x x x x . . 333

XR57 V Compensation 8R/W 3D7 x x x x x x x x . . 333

XR58 V Centering 8R/W 3D7 x x x x x x x x . . 333

XR59 V Line Insertion 7R/W 3D7 x x x • x x x x . . 333

XR5A V Line Replication 4R/W 3D7 • • • • x x x x . . 333

XR5B Power Sequencing Delay 8R/W 3D7 1 0 0 0 0 0 0 1 . . 333

XR5C Activity Indicator Control 7R/W 3D7 0 x • x x x x x . . . . 3

XR5D FP Diagnostic 8 R/W 3D7 0 0 0 0 0 0 0 0 . . . . 3

XR5E ACDCLK (M) Control 8R/W 3D7 x x x x x x x x . . 333

XR5F Power Down Mode Refresh 8R/W 3D7 x x x x x x x x . . . 3 3

EXTENSION REGISTER SUMMARY: 30-5F

Revision 1.2 47 65540 / 545

CHIPS' VGA Product Family

Reset Codes: x = Not changed by RESET (indeterminate on power-up) – = Not implemented (always reads 0)

d = Set from the corresponding data bus pin on falling edge of RESET • = Reserved (read/write, reset to 0)

h = Read-only Hercules Configuration Register Readback bits 0/1 = Reset to 0/1 by trailing edge of reset

r = Chip revision # (starting from 0000)

Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column

Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD)

Reg Register Name Bits Access Port Reset 82C450 64300/310 65510 65530 65535

XR60 Blink Rate Control 8R/W 3D7 1 0 0 0 0 0 1 1 . 3 3 3 3

XR61 SmartMap™ Control 8R/W 3D7 x x x x x x x x . . 333

XR62 SmartMap™ Shift Parameter 8R/W 3D7 x x x x x x x x . . 333

XR63 SmartMap™ Color Mapping Control 8R/W 3D7 x 1 x x x x x x . . 333

XR64 FP Alternate Vertical Total 8R/W 3D7 x x x x x x x x . . 333

XR65 FP Alternate Overflow 6R/W 3D7 x x x • • x x x . . 333

XR66 FP Alternate Vertical Sync Start 8R/W 3D7 x x x x x x x x . . 333

XR67 FP Alternate Vertical Sync End 4R/W 3D7 • • • • x x x x . . 333

XR68 FP Vertical Panel Size 8R/W 3D7 x x x x x x x x . . 333

XR69 -reserved- -- -- 3D7 . . . . .

XR6A -reserved- -- -- 3D7 . . . . .

XR6B -reserved- -- -- 3D7 . . . . .

XR6C Programmable Output Drive 5R/W 3D7 • • 0 0 0 0 d • . . 333

XR6D -reserved- -- -- 3D7 . . . . .

XR6E Polynomial FRC Control 8R/W 3D7 1 0 1 1 1 1 0 1 . . 333

XR6F Frame Buffer Control 8R/W 3D7 0 0 0 0 0 0 0 0 . . . 3 3

XR70 Setup / Disable Control 1R/W 3D7 0 - - - - - - - 3 3 3 3 3

XR71 -reserved- (GPIO Control) -- -- 3D7 . 3...

XR72 External Device I/O (GPIO Data) 7R/W 3D7 0 0 0 0 0 0 0 • . 3. . 3

XR73 Miscellaneous Control 6R/W 3D7 0 0 - - 0 0 0 0 . 3. . 3

XR74 -reserved- (Configuration 2) -- -- 3D7 . 3...

XR75 -reserved- (Software Flags 3) -- -- 3D7 . 3...

XR76 -reserved- -- -- 3D7 . . . . .

XR77 -reserved- -- -- 3D7 . . . . .

XR78 -reserved- -- -- 3D7 . . . . .

XR79 -reserved- -- -- 3D7 . . . . .

XR7A -reserved- -- -- 3D7 . . . . .

XR7B -reserved- -- -- 3D7 . . . . .

XR7C -reserved- -- -- 3D7 . . . . .

XR7D Diagnostic 1 R/W 3D7 0 - - - - - - • . . 3 3 .

XR7E CGA/Hercules Color Select 6R/W 3D7 - - x x x x x x 3 3 3 3 3

XR7F Diagnostic 8 R/W 3D7 0 0 x x x x 0 0 3 3 3 3 3

EXTENSION REGISTER SUMMARY: 60-7F

Revision 1.2 48 65540 / 545

CHIPS' VGA Product Family

Reset Codes: x = Not changed by reset (indeterminate on power-up) – = Not implemented (always reads 0)

d = Set from the corresponding data bus pin on trailing edge of reset • = Reserved (read/write, reset to 0)

h = Read-only Hercules Configuration Register Readback bits 0/1 = Reset to 0/1 by trailing edge of reset

r = Chip revision # (starting from 0000)

Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column

Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD)

Reg Group

Bits Access Port Reset

DR00 BitBLT BitBLT Offset 16/32 R/W 83D0-3 - - - - x x x x x x x x x x x x - - - - x x x x x x x x x x x x

DR01 BitBLT BitBLT Pattern ROP 16/32 R/W 87D0-3 - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x

DR02 BitBLT BitBLT BG Color 16/32 R/W 8BD0-3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

DR03 BitBLT BitBLT FG Color 16/32 R/W 8FD0-3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

DR04 BitBLT BitBLT Control 16/32 R/W 93D0-3 - - - - - - - - - - - 0 x x x x x x x x x x x x x x x x x x x x

DR05 BitBLT BitBLT Source 16/32 R/W 97D0-3 - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x

DR06 BitBLT BitBLT Destination 16/32 R/W 9BD0-3 - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x

DR07 BitBLT BitBLT Command 16/32 R/W 9FD0-3 - - - - 0 0 0 0 0 0 0 0 0 0 0 0 - - - - x x x x x x x x x x x x

DR08 Cursor Cursor Control 16/32 R/W A3D0-3 - - - - - - - - - - - - - - - - • • • • 0 0 0 0 0 0 0 • • • 0 0

DR09 Cursor Cursor Color 0-1 16/32 R/W A7D0-3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

DR0A Cursor Cursor Color 2-3 16/32 R/W ABD0-3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

DR0B Cursor Cursor Position 16/32 R/W AFD0-3 x - - - - x x x x x x x x x x x x - - - - x x x x x x x x x x x

DR0C Cursor Cursor Base Address 16/32 R/W B3D0-3 - - - - - - - - - - - - x x x x x x x x x x - - - - - - - - - -

32-BIT EXTENSION REGISTER SUMMARY

Revision 1.2 49 65540 / 545

Reset Codes: x = Not changed by reset (indeterminate on power-up) – = Not implemented (always reads 0)

d = Set from configuration pin on trailing edge of reset • = Not implemented (read/write, reset to 0)

h = Read-only Hercules Configuration Register Readback bits 0/1 = Reset to 0/1 by trailing edge of reset

r = Chip revision # (starting from 0000)

Revision 1.2 50 65540 / 545

Reg Register Name Bits Access Offset Reset

VENID Vendor ID 16 R 00h 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 0

DEVID Device ID 16 R 02h 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0

DEVCTL Device Control 16 R/W 04h - - - - - - 1 0 1 0 0 0 0 0 0 0

DEVSTAT Device Status 16 R/C 06h 0 0 0 0 0 0 0 0 0 - - - - - - -

REV Revision 8 R 08h - - - - - r r r

PRG Programming Interface 8 R 09h 0 0 0 0 0 0 0 0

SUB Sub Class Code 8 R 0Ah 0 0 0 0 0 0 0 0

BASE Base Class Code 8 R 0Bh 0 0 0 0 0 0 1 1

MBASE Memory Base Address 32 R/W 10h x x x x x x x x x x x - - - - - - - - - - - - - - - - - 0 0 0 0

IOBASE I/O Base Address 32 R/W 14h x x x x x x x x x x x x x x x x x x x x x x - - - - - - - - 0 1

PCI CONFIGURATION REGISTER SUMMARY

Note: R = Read, W = Write, C = Clear (1s written to specific bits will clear those bits)

GLOBAL CONTROL (SETUP) REGISTERS

The Setup Control Register and Video Subsystem

Enable registers are used to enable or disable the

VGA. The Setup Control register is also used to

place the VGA in normal or setup mode (the Global

Enable Register is accessible only during Setup

mode). The Setup Control register is used only in

ISA bus interfaces; the Video Subsystem Enable

The various internal 'disable' bits 'OR' together to

provide multiple ways of disabling the chip; all

'disable' bits must be off to enable access to the

chip. When the chip is 'disabled' in this fashion,

only bus access is disabled; other functions remain

operational (memory refresh, display refresh, etc.).

Note: In setup mode in the IBM VGA, the Global

Setup Register (defined as port address 102) actually

occupies the entire I/O space . Only the lower 3 bits

are used to decode and select this register. To avoid

bus conflicts with other peripherals, reads should

only be performed at the 10xh port addresses while

in setup mode. To eliminate potential compatibility

problems in widely varying PC systems, CHIPS'

VGA controllers decode the Global Setup register at

I/O port 102h only.

PCI CONFIGURATION REGISTERS (65545)

For PCI bus configuration in the 65545, ten 16-bit

registers are implemented to allow identification of

the chip, examination of various internal states,

configuration of memory and I/O base addresses,

and control of settings for various modes of

operation. These registers are located at various

offsets into the PCI configuration space which may

be I/O or memory mapped depending on the system

design.

GENERAL CONTROL REGISTERS

Two Input Status Registers read the SENSE function

(Virtual Switch Register or internal RGB comparator

output), pending CRT interrupt, display enable /

horizontal sync output, and vertical retrace / video

output. The Feature Control Register selects the

vertical sync function while the Miscellaneous

Output Register controls I/O address selection, clock

selection, CPU access to display memory, display

memory page selection, and horizontal and vertical

sync polarity.

Revision 1.2 51 65540 / 545

CGA / HERCULES REGISTERS

CGA Mode and Color Select registers are provided

on-chip for emulation of CGA modes. Hercules

Mode and Configuration registers are provided on-

chip for emulation of Hercules mode.

SEQUENCER REGISTERS

The Sequencer Index Register contains a 3-bit index

to the Sequencer Data Registers. The Reset Register

forces an asynchronous or synchronous reset of the

sequencer. The Sequencer Clocking Mode Register

controls master clocking functions, video

enable/disable and selects either an 8 or 9 dot

character clock. A Plane/Map Mask Register enables

the color plane and write protect. The Character

Font Select Register handles video intensity and

character generation and controls the display memory

plane through the character generator select. The

Sequencer Memory Mode Register handles all

memory, giving access by the CPU to 4 / 16 / 32

KBytes, Odd / Even addresses (planes) and writing

of data to display memory.

CRT CONTROLLER REGISTERS

The CRT Controller Index Register contains a 6-bit

index to the CRT Controller Registers. Twenty one

registers control various display functions: hori-

zontal and vertical blanking and sync timing,

panning and scrolling, cursor size and location, light

pen, and text-mode underline.

GRAPHICS CONTROLLER REGISTERS

The Graphics Controller Index Register contains a 4-

bit index to the Graphics Controller Registers. The

Set/Reset Register controls the format of the CPU

data to display memory. It also works with the

Enable Set/Reset Register. Reducing 32 bits of

display data to 8 bits of CPU data is accomplished

by the Color Compare Register. Data Rotate

Registers specify the CPU data bits to be rotated and

subjected to logical operations. The Read Map Select

four plane (16 color) graphics mode. The Graphics

Mode Register controls the write, read, and shift

graphics/text, chaining of odd/even planes, and

display memory mapping. Additional registers

include Color Don't Care and Bit Mask.

Registers

ATTRIBUTE CONTROLLER AND

COLOR PALETTE REGISTERS

The Attribute Controller Index Register contains a 5-

bit index to the Attribute Controller Registers which

consist of a 16-entry color lookup table with 6 bits

per entry plus five additional control registers. A

sixth index register bit is used to enable video. The

Attribute Controller Registers handle color lookup

table mapping, text/graphics mode control, overscan

color selection, and color plane enabling. One

pixels. Another register provides default values to

extend the 6-bit lookup table values to 8 bits for

modes providing less than 8 bits per pixel.

The color palette registers control the interface to the

on-chip color palette. This on-chip palette fully

implements the functions of the VGA-standard

palette (Inmos IMSG176, Brooktree BT471/476, or

equivalent functionality). The color palette primarily

consists of a 256-entry color lookup table (also

sometimes referred to as a CLUT), a mask register,

index registers used to access the CLUT data, and

triple 6 / 8-bit DACs used to drive analog RGB

outputs to a CRT monitor. Each entry in the CLUT

is 18 bits in length (6 bits each for red, green, and

blue) so each CLUT data entry must be accessed

sequentially as 3 separate bytes and each DAC output

operates with 6 bits of resolution. In 24-bpp "True-

Color" modes, the CLUT is bypassed and each DAC

operates with 8-bit resolution.

EXTENSION REGISTERS

The 65540 / 545 defines a set of extension registers

(called "XR's") which are addressed with the 7-bit

Extension Register Index. The I/O port address is

fixed at 3D6-3D7h and read/write access is always

enabled to improve software performance.

The extension registers handle a variety of inter-

facing, compatibility, and display functions as

discussed below. They are grouped into the

following logical groups for discussion purposes:

1. Miscellaneous Registers include the chip

version/revision, configuration, and various

interface control and diagnostic functions.

2. Mapping Registers include paging controls and

base registers for relocation of I/O and memory

blocks.

3. Software Flags Registers provide locations for

BIOS and driver software to store various

temporary variable values on-chip

Revision 1.2 52 65540 / 545

4. Clock Registers control the operation of the on-

chip clock synthesizer

5. Multimedia Registers control the operation of the

video input port color key and mask

6. BitBLT Registers control the operation of the Bit-

Block-Transfer (BitBLT) engine (65545 only) for

graphics acceleration.

7. Backwards Compatibility Registers control

Hercules, MDA, and CGA emulation modes.

Write Protect functions are provided to increase

flexibility in providing backwards compatibility.

8. Alternate Horizontal and Vertical Registers handle

all horizontal and vertical timing, including sync,

blank and offset. These are used for backwards

compatibility.

9. Flat Panel Registers handle all internal logic

specific to driving of flat panel displays.

32-BIT REGISTERS

The 65545 also implements a group of sixteen 32-bit

doubleword extension registers (called "DR's").

These registers are used for control of the high

performance BitBLT and Hardware Cursor

subsystems and may be mapped anywhere in the I/O

and/or memory address space.

For ISA and VL-Bus configurations, the 32-bit

registers take up 32 doubleword locations in the 16-

bit I/O address space (only the first 13 registers are

defined; the remaining locations are reserved). An

8-bit extension register is provided to program the

base address. The address is of the form "bnnn

nn1b bbbb bbxx" (where b specifies the value

programmed into the base register and 'n' selects one

of the 32 register locations). The base register is

typically programmed with '74h' to map the 32-bit

registers to I/O addresses x3D0-x3D3h (unused ports

in the standard VGA I/O address range).

For PCI bus configurations, the 32-bit registers are

mapped to both the memory and I/O address spaces.

The PCI configuration registers contain an I/O base

doublewords) which allows the 32-bit register space

to start on any 1KB boundary in the I/O address

space. In addition, the PCI memory base register

specifies an 8MB memory address space; display

memory is mapped into the lower 2 megabytes and

the 32-bit registers are mapped into the upper 6

megabytes.

Registers

Note: The state of most of the standard VGA registers is undefined at reset. The state at Reset of all registers

specific to the 65540 / 545 (extension registers and 32-bit registers) is summarized in the register summary tables.

Global Control (Setup) Registers

Revision 1.2 53 65540 / 545

Global Control (Setup) Registers

Mnemonic Register Name Index Access I/O Address Page

SETUP Setup Control – W 46E8h (ISA Bus Only) 53

VSE Video Subsystem Enable – W 3C3h (Local Bus Only) 53

ENAB Global Enable – RW 102h (ISA Bus / Setup Mode Only) 54

VIDEO SUBSYSTEM ENABLE REGISTER (VSE)

Write Only at I/O Address 3C3h

SETUP CONTROL REGISTER (SETUP)

Write only at I/O Address 46E8h

This register is effective in ISA bus configuration

only and is not used in local bus or PCI bus

configurations. In ISA bus configuration, this regis-

ter is ignored if XR70 bit-7 is set to 1 (the default is

0).

In local bus configurations, the VGA may be enabled

and disabled using register 3C3. In PCI bus

configurations (65545), the VGA may be enabled

and disabled via the PCI configuration registers.

Setup mode is available only in ISA bus

configuration via this register.

This register is cleared by RESET.

2-0 Reserved (0)

3VGA Enable

0VGA is disabled

1VGA is enabled

4Setup Mode

0VGA is in Normal Mode

1VGA is in Setup Mode

7-5 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (0)

VGA Enable

VGA Setup

Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

VGA Sleep

Reserved (0)

This register is accessible in Local Bus

configurations only. It is ignored in ISA bus

configurations (registers 102h and 46E8h are used in

ISA bus configurations to control VGA enable and

disable). Access to this register may be disabled by

setting XR70 bit-7 to 1 (the default is 0).

This register is cleared by RESET to disable the

VGA. In this state, only register 3C3 is accessible

(the other registers in the VGA I/O address range

will be inaccessible and read or write accesses to

VGA I/O addresses other than 3C3 will be ignored)

until bit-0 of this register is set to 1.

In PCI bus configurations, VGA enable and disable

are controlled via the PCI configuration registers and

this register is ignored.

0VGA Sleep

0VGA is disabled

1VGA is enabled

7-1 Reserved (0)

Global Control (Setup) Registers

Revision 1.2 54 65540 / 545

This register is accessible only in setup mode (46E8

bit-4 = 1). If the VGA is not in setup mode (46E8

bit-4 = 0), attempts to access this register are

ignored.

Bit-0 of this register is cleared by RESET in ISA bus

configurations to disable the VGA (all VGA memory

and I/O addresses except 102h and 46E8h are

ignored). Bit-0 of this register is AND'ed with bit-3

of register 46E8: the VGA is enabled only if both

bits are set. If the VGA is disabled, only register

46E8 is accessible.

0VGA Sleep

0VGA is disabled

1VGA is enabled

7-1 Reserved (0)

GLOBAL ENABLE REGISTER ( ENAB )

Read/Write at I/O Address 102h

D7 D6 D5 D4 D3 D2 D1 D0

VGA Sleep

Reserved (0)

PCI Configuration Registers

Revision 1.2 55 65540 / 545

PCI Configuration Registers

Mnemonic Register Name Offset Access Reset State Page

VENID Vendor ID 00h R 0001 0000 0010 1100 55

DEVID Device ID 02h R 0000 0000 1101 1000 55

DEVCTL Device Control 04h R/W 0000 0010 1000 0000 56

DEVSTAT Device Status 06h R/C 0000 0000 0000 0000 56

REV Revision 08h R 0000 0000 57

PRG Programming Interface 09h R 0000 0000 57

SUB Sub Class Code 0Ah R 0000 0000 57

BASE Base Class Code 0Bh R 0000 0011 57

MBASE Memory Base Address 10h R/W xxxx xxxx xxx0 0000 0000 0000 0000 0000 58

IOBASE I/O Base Address 14h R/W xxxx xxxx xxxx xxxx xxxx xx00 0000 0001 58

VENDOR ID REGISTER (VENID)

Read/Only at PCI Configuration Offset 00h

Byte or Word Accessible

Accessible in PCI Bus Configuration Only

15–0 Vendor ID

Read-Only. Always returns 102Ch (4140d)

15 0

Vendor ID

DEVICE ID REGISTER (DEVID)

Read/Only at PCI Configuration Offset 02h

Byte or Word Accessible

Accessible in PCI Bus Configuration Only

15–0 Device ID

Read-Only. Always returns 00D8h

15 0

Device ID

Note: 'Access' codes are R=Read, W=Write, and C=Clear (writing a 1 to a bit clears that bit)

6–0 Undefined / Reserved ( 0 )

7Fast Back-to-Back Capable ( 1 )

8Data Parity Error Detect (0)

Implemented by bus masters only.

10–9 DEVSEL# Timing

Always responds '10' (Slow)

11 Target Abort Signaled

Set whenever a Target Abort is generated on

the bus. This can happen under the

following conditions:

1) Command/Address cycle parity error

2) Invalid byte enables received

3) VGA core unable to complete a cycle

12 Received Target Abort (0)

Implemented by bus masters only.

13 Master Abort (0)

Implemented by bus masters only.

14 System Error Signaled

Set whenever SERR# is asserted.

15 Parity Error Detected

Set when data parity error is detected even if

PERR# response disabled (DEVCTL bit-6)

DEVICE CONTROL REGISTER ( DEVCTL )

Read/Write at PCI Configuration Offset 04h

Byte or Word Accessible

Accessible in PCI Bus Configuration Only

0I/O Access Enable

When set, the chip will respond to I/O cycles

for addresses within the range specified by

the IOBASE register.

1Memory Access Enable

When set, the chip will respond to memory

cycles for addresses within the range

specified by the MBASE register.

2Bus Master ( Always Reads 0 )

3Special Cycles ( Always Reads 0 )

4Mem Write & Invalidate ( Always Reads 0 )

5Palette Snoop Enable

When set, the chip will not respond to VGA

Palette Accesses. Reads will be ignored but

writes will still update the internal palette.

6PERR# Enable

Set to enable PERR# response for detected

data parity errors.

7Wait Cycle Control ( Always Reads 1 )

8SERR# Enable

Set to enable SERR# response for detected

address / command parity errors. The chip

will also generate a Target Abort.

9Fast Back-to-Back Enable for Masters

(Always Reads 0)

15-10 Undefined / Reserved ( 0 )

PCI Configuration Registers

Revision 1.2 56 65540 / 545

DEVICE STATUS REGISTER ( DEVSTAT )

Read/Only at PCI Configuration Offset 06h

Byte or Word Accessible

Accessible in PCI Bus Configuration Only

15 0

Undefined (0)

Always Reads 1

Always Reads 0

DEVSEL# Timing

(Always Reads 10)

Target Abort Sig'd

Always Reads 0

Sys Err Signaled

Parity Err Detected

15 0

I/O Access Ena

Mem Access Ena

Always Read 0

Palette Snoop Ena

PERR# Enable

Always Reads 1

SERR# Enable

Always Reads 1

Undefined (0)

PCI Configuration Registers

Revision 1.2 57 65540 / 545

REVISION REGISTER ( REV )

Read/Only at PCI Configuration Offset 08h

Byte Accessible

Accessible in PCI Bus Configuration Only

2-0 Chip Revision Code

These bits match XR00 bits 2-0. Revision

codes start at 0 and are incremented for each

silicon revision.

7-3 Reserved (0)

These bits are defined by the PCI 2.0

specification as additional revision code bits.

They always read zero.

SUB CLASS CODE REGISTER ( SUB )

Read/Only at PCI Configuration Offset 0Ah

Byte Accessible

Accessable in PCI Bus Configuration Only

7-0 Sub-Class Code

This register always returns a value of 00h

to indicate "VGA Compatible Controller".

D7 D6 D5 D4 D3 D2 D1 D0

Chip Revision Code

D7 D6 D5 D4 D3 D2 D1 D0

Sub-Class Code

PROGRAMMING INTERFACE REGISTER (PRG)

Read/Only at PCI Configuration Offset 09h

Byte Accessible

Accessable in PCI Bus Configuration Only

7-0 Programming Interface Code

This register always returns a value of 00h

(no special register-level device-independent

interface definition is defined).

D7 D6 D5 D4 D3 D2 D1 D0

Programming

Interface

Code

BASE CLASS CODE REGISTER ( BASE )

Read/Only at PCI Configuration Offset 0Bh

Byte Accessible

Accessable in PCI Bus Configuration Only

7-0 Base Class Code

This register always returns a value of 03h

to indicate base class "Display Controller".

D7 D6 D5 D4 D3 D2 D1 D0

Base Class Code

MEMORY BASE REGISTER ( MBASE )

Read/Write at PCI Configuration Offset 10h

Byte, Word, or DoubleWord Accessible

Accessable in PCI Bus Configuration Only

0Memory / IO Space (0)

Always returns 0 to indicate memory space

2-1 Memory Type (00)

Always return 0 to indicate 32-bit address

3Prefetchable Memory (0)

Always return 0 to prevent prefetching

22-4 Address Mask (0)

Always returns 0 to indicate an 8MB range

31-23 Memory Base Address

R/W in bits 23 and above to indicate an 8MB

address range. The lower 2MB is for video

memory and the rest is for memory mapped

IO. The actual value programmed in this

field determines the start of the range in the

32-bit memory address space. For example:

Value

Programmed Memory Address Range

0: 000000000b Illegal Setting

8MB: 000000001b 00800000h - 00FFFFFFh

16MB: 000000010b 01000000h - 017FFFFFh

24MB: 000000011b 01800000h - 01FFFFFFh

32MB: 000000100b 02000000h - 027FFFFFh

40MB: 000000101b 02800000h - 02FFFFFFh

... ... ...

Note: XR08 provides the same function for

ISA/VL. It is ignored in PCI bus mode.

31 23

4 3 2 1 0

PCI Configuration Registers

Revision 1.2 58 65540 / 545

0 (Memory Space)

00 (32-bit Address)

0 (No Prefetching)

0 (Address Mask)

(8MB Range)

Memory

Base Address

I/O BASE REGISTER ( IOBASE )

Read/Write at PCI Configuration Offset 14h

Byte, Word, or DoubleWord Accessible

Accessable in PCI Bus Configuration Only

0Memory / IO Space (1)

Always returns 1 to indicate I/O space

1Undefined / Reserved (0)

9-2 Address Mask (0)

All bits in in this field return 0 to indicate a

1KB I/O address range

31-10 I/O Base Address

R/W in bits 10 and above to indicate a 1KB

address range for the 32-bit registers (DRxx

registers). The actual value programmed in

this field determines the start of the range in

the 32-bit I/O address space. For example:

Value

Programmed I/O Address Range

000000h Illegal Setting

000001h 00000400h - 000007FFh

000002h 00000800h - 00000BFFh

000003h 00000C00h - 00000FFFh

000004h 00001000h - 000013FFh

... ...

Note: XR07 provides the same function for

ISA/VL. It is ignored in PCI bus mode.

Note: In PCI bus configuration, the DR registers

may also be memory mapped to the upper

megabyte of the 2MB memory space (see

MBASE).

31 10 9 2 1 0

1 (I/O Space)

0 (Reserved)

0 (Address Mask)

(1KB Range)

I/O Base Address

General Control Registers

Revision 1.2 59 65540 / 545

General Control & Status Registers

Mnemonic Register Name Index Access Address Group Page

ST00 Input Status 0 – R 3C2h – 59

ST01 Input Status 1 – R 3BAh/3DAh – 59

FCR Feature Control – W 3BAh/3DAh 5 60

R 3CAh

MSR Miscellaneous Output – W 3C2h 5 60

R 3CCh

INPUT STATUS REGISTER 1 ( ST01 )

Read only at I/O Address 3BAh/3DAh

INPUT STATUS REGISTER 0 ( ST00 )

Read only at I/O Address at 3C2h

3-0 Reserved (0)

4RGB Comparator / Sense

This bit returns the state of the output of the

RGB output comparator or the output of the

Virtual Switch Register (XR1F bit 0, 1, 2,

or 3) if enabled by XR1F bit-7.

6-5 Reserved (0)

7CRT Interrupt Pending

0Indicates no CRT interrupt is pending

1Indicates a CRT interrupt is waiting to

be serviced

0Display Enable/HSYNC Output

The functionality of this bit is controlled by

the Emulation Mode register (XR14 bit-4).

0Indicates DE or HSYNC inactive

1Indicates DE or HSYNC active

2-1 Reserved (0)

3Vertical Retrace/Video

The functionality of this bit is controlled by

the Emulation Mode register (XR14 bit-5).

0Indicates VSYNC or video inactive

1Indicates VSYNC or video active

5-4 Video Feedback 1, 0

These are diagnostic video bits which are

selected via the Color Plane Enable Register.

6Reserved (0)

7VSync Output

The functionality of this bit is controlled by

the Emulation Mode register (XR14 bit-6).

It reflects the active status of the VSYNC

output: 0=inactive, 1=active.

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (0)

RGB Comparator / Sense

Reserved (0)

CRT Interrupt Pending

D7 D6 D5 D4 D3 D2 D1 D0

DE/Hsync Output

Reserved (0)

Vertical Retrace/Video

Video Feedback

Reserved (0)

VSync Output

General Control Registers

Revision 1.2 60 65540 / 545

FEATURE CONTROL REGISTER ( FCR )

Write at I/O Address 3BAh/3DAh

Read at I/O Address 3CAh

Group 5 Protection

1-0 Feature Control

These bits are used internal to the chip in

conjunction with the Configuration Register

(XR01). When enabled by XR01 bits 2-3

and Misc Output Register bits 3-2 = 10,

these bits determine the pixel clock

frequency typically as follows:

FCR1:0 = 00 = 40.000 MHz

FCR1:0 = 01 = 50.350 MHz

FCR1:0 = 10 = User defined

FCR1:0 = 11 = 44.900 MHz

This preserves compatibility with drivers

developed for earlier generation Chips and

Technologies VGA controllers.

2Reserved (0)

3VSync Control

This bit is cleared by RESET.

0VSync output on the VSYNC pin

1Logical 'OR' of VSync and Display

Enable output on the VSYNC pin

This capability is not typically very useful,

but is provided for IBM compatibility.

7-4 Reserved (0)

MISCELLANEOUS OUTPUT REGISTER (MSR)

Write at I/O Address 3C2h

Read at I/O Address 3CCh

Group 5 Protection

This register is cleared by RESET.

0I/O Address Select

This bit selects 3Bxh or 3Dxh as the I/O

address for the CRT Controller registers, the

Feature Control Register (FCR), and Input

Status Register 1 (ST01).

0Select 3Bxh I/O address

1Select 3Dxh I/O address

1RAM Enable

0Prevent CPU access to display memory

1Allow CPU access to display memory

3-2 Clock Select. These bits usually select the

dot clock source for the CRT interface:

MSR3:2 = 00 = Select CLK0

MSR3:2 = 01 = Select CLK1

MSR3:2 = 10 = Select CLK2

MSR3:2 = 11 = Select CLK3

See extension register XR01 bits 2-3

(Configuration) and FCR bits 0-1 for

variations of the above clock selection

mapping. See also XR1F (Virtual Switch

potentially controlled by these bits.

4Reserved (0)

5Page Select. In Odd/Even Memory Map

Mode 1 (GR6), this bit selects the upper or

lower 64 KByte page in display memory for

CPU access: 0=select upper page; 1=select

lower page.

6CRT HSync Polarity. 0=pos, 1=neg

7CRT VSync Polarity. 0=pos, 1=neg

(Blank pin polarity can be controlled via the

Video Interface Register, XR28). XR55

bits 6-7 are used to control H/V sync

polarity instead of these bits if XR51 bit-2 =

1 (display type = flat panel).

D7 D6 D5 D4 D3 D2 D1 D0

Feature Control

Reserved (0)

VSync Control

Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

I/O Address Select

RAM Enable

Clock Select

Reserved (0)

Page Select

HSync Polarity

VSync Polarity

V H Display H Freq V Freq

P P >480 Line Variable

Variable

P P 200 Line 15.7 KHz 60 Hz

N P 350 Line 21.8 KHz 60 Hz

P N 400 Line 31.5 KHz 70 Hz

N N 480 Line 31.5 KHz 60 Hz

CRT Display Sync Polarities

CGA / Hercules Registers

Revision 1.2 61 65540 / 545

CGA / Hercules Registers

Mnemonic Register Name Index Access Address Group Page

MODE CGA/Hercules Mode – R/W 3D8h – 61

COLOR CGA Color Select – R/W 3D9h – 62

HCFG Hercules Configuration – R/W 3BFh – 62

CGA / HERCULES MODE CONTROL

Read/Write at I/O Address 3B8h/3D8h

D7 D6 D5 D4 D3 D2 D1 D0

HiRes Text (CGA only)

Graphics Mode (0=Text)

Monochrome (CGA only)

Video Enable

HiRes Graphics(CGA only)

Text Blink Enable

Reserved (0)

Page Select (Herc only)

2CGA Mono/Color Mode

0Select CGA color mode

1Select CGA monochrome mode

3CGA/Hercules Video Enable

0Blank the screen

1Enable video output

4CGA High Resolution Mode

0Select 320x200 graphics mode

1 Select 640x200 graphics mode

5CGA/Hercules Text Blink Enable

0Disable character blink attribute (blink

attribute bit-7 used to control back-

ground intensity)

1Enable character blink attribute

6Reserved (0)

7Hercules Page Select

0Select the lower part of memory

(starting address B0000h) in Hercules

Graphics Mode

1Select the upper part of the memory

(starting address B8000h) in Hercules

Graphics Mode

This register is effective only in CGA and Hercules

modes. It is accessible if CGA or Hercules

emulation mode is selected or the extension registers

are enabled. If the extension registers are enabled,

the address is determined by the address select in the

Miscellaneous Outputs register. Otherwise the

address is determined by the emulation mode. It is

cleared by RESET.

0CGA 80/40 Column Text Mode

0Select 40 column CGA text mode

1 Select 80 column CGA text mode

1CGA/Hercules Graphics/Text Mode

0Select text mode

1Select graphics mode

CGA / Hercules Registers

Revision 1.2 62 65540 / 545

D7 D6 D5 D4 D3 D2 D1 D0

Color bit-0 (Blue)

Color bit-1 (Green)

Color bit-2 (Red)

Color bit-3 (Intensity)

Intensity Enable

Color Set Select

Reserved (0)

CGA COLOR SELECT REGISTER (COLOR)

Read/Write at I/O Address 3D9h

This register is effective only in CGA modes. It is

accessible if CGA emulation mode is selected or the

extension registers are enabled. This register may

also be read or written as an Extension Register

(XR7E). It is cleared by Reset.

3-0 Color

320x200 4-color: Background Color (color

when the pixel value is 0)

The foreground colors (colors when the

pixel value is 1-3) are determined by bit-5 of

this register.

640x200 2-color:

Foreground Color (color when the pixel

value is 1)

The background color (color when the pixel

value is 0) is black.

4Intensity Enable

Text Mode: Enables intensified

background colors

320x200 4-color: Enables intensified

colors 0-3

640x200 2-color: Don't care

5Color Set Select

This bit selects one of two available CGA

color palettes to be used in 320x200

graphics mode (it is ignored in all other

modes) according to the following table:

Pixel Color Set Color Set

Value 0 1

0 0 Color per bits 0-3 Color per bits 0-3

0 1 Green Cyan

1 0 Red Magenta

1 1 Brown White

7-6 Reserved (0)

This register is effective only in Hercules mode. It is

accessible in Hercules emulation mode or if the

extension registers are enabled. It may be read back

through XR14 bits 2 & 3. It is cleared by Reset.

0Enable Graphics Mode

0Lock the chip in Hercules text mode.

In this mode, the CPU has access only

to memory address range B0000h-

B7FFFh (in text mode the same area

of display memory wraps around 8

times within this range such that

B0000 accesses the same display

memory location as B1000, B2000,

etc.).

1Permit entry to Hercules Graphics

mode

1Enable Memory Page 1

0Prevent setting of the Page Select bit

(bit 7 of the Hercules Mode Control

memory usage to addresses B0000h-

B7FFFh.

1The Page Select bit can be set and the

upper part of display memory

(addresses B8000h - BFFFFh) is

available.

7-2 Reserved (0)

HERCULES CONFIGURATION

Write only at I/O Address 3BFh

D7 D6 D5 D4 D3 D2 D1 D0

Enable Graphics Mode

Enable Memory Page 1

Reserved (0)

Sequencer Registers

Mnemonic Register Name Index Access Address Group Page

SRX Sequencer Index – R/W 3C4h 1 63

SR00 Reset 00h R/W 3C5h 1 63

SR01 Clocking Mode 01h R/W 3C5h 1 64

SR02 Plane/Map Mask 02h R/W 3C5h 1 64

SR03 Character Font 03h R/W 3C5h 1 65

SR04 Memory Mode 04h R/W 3C5h 1 66

SR07 Horizontal Character Counter Reset 07h W 3C5h – 66

This register is cleared by reset.

2-0 Sequencer Index

These bits contain a 3-bit Sequencer Index

value used to access sequencer data registers

at indices 0 through 7.

7-3 Reserved (0)

SEQUENCER RESET REGISTER (SR00)

Read/Write at I/O Address 3C5h

Index 00h

Group 1 Protection

0Asynchronous Reset

0Force asynchronous reset

1Normal operation

Display memory data will be corrupted if

this bit is set to zero.

1Synchronous Reset

0Force synchronous reset

1Normal operation

Display memory data is not corrupted if this

bit is set to zero for a short period of time (a

few tenths of a microsecond). See also

XR0E.

7-2 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Async Reset

Sync Reset

Reserved (0)

SEQUENCER INDEX REGISTER (SRX)

Read/Write at I/O Address 3C4h

D7 D6 D5 D4 D3 D2 D1 D0

Sequencer Index

Reserved (0)

Revision 1.2 63 65540 / 545

SEQUENCER CLOCKING MODE

Read/Write at I/O Address 3C5h

Index 01h

Group 1 Protection

08/9 Dot Clocks

This bit determines whether a character clock

is 8 or 9 dot clocks long.

0Select 9 dots/character clock

1 Select 8 dots/character clock

1Reserved (0)

2Shift Load

0Load video data shift registers every

character clock

1Load video data shift registers every

other character clock

Bit-4 of this register must be 0 for this bit to

be effective.

3Input Clock Divide

0Sequencer master clock output on the

PCLK pin (used for 640 (720) pixel

modes)

1Master clock divided by 2 output on

the PCLK pin (used for 320 (360)

pixel modes)

4Shift 4

0Load video shift registers every 1 or 2

character clocks (depending on bit-2

of this register)

1Load shift registers every 4th character

clock.

5Screen Off

0Normal Operation

1Disable video output and assign all

display memory bandwidth for CPU

accesses

7-6 Reserved (0)

SEQUENCER PLANE/MAP MASK

Read/Write at I/O Address 3C5h

Index 02h

Group 1 Protection

3-0 Color Plane Enable

0Write protect corresponding color

plane

1Allow write to corresponding

color plane.

In Odd/Even and Quad modes, these bits

still control access to the corresponding

color plane.

7-4 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

8/9 Dot Clocks

Reserved (0)

Shift Load

Input Clock Divide

Shift 4

Screen Off

Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Color Plane Enable

Reserved (0)

Sequencer Registers

Revision 1.2 64 65540 / 545

Sequencer Registers

In text modes, bit-3 of the video data's attribute byte

normally controls the foreground intensity. This bit

may be redefined to control switching between char-

acter sets. This latter function is enabled whenever

there is a difference in the values of the Character

Font Select A and the Character Font Select B bits. If

the two values are the same, the character select

function is disabled and attribute bit-3 controls the

foreground intensity.

SR04 bit-1 must be 1 for the character font select

function to be active. Otherwise, only character

fonts 0 and 4 are available.

1-0 High order bits of Character Generator

Select B

3-2 High order bits of Character Generator

Select A

4Low order bit of Character Generator

Select B

5Low order bit of Character Generator

Select A

7-6 Reserved (0)

CHARACTER FONT SELECT

Read/Write at I/O Address 3C5h

Index 03h

Group 1 Protection

The following table shows the display memory plane

selected by the Character Generator Select A and B

bits.

Code Character Generator Table Location

0First 8K of Plane 2

1 Second 8K of Plane 2

2 Third 8K of Plane 2

3 Fourth 8K of Plane 2

4 Fifth 8K of Plane 2

5 Sixth 8K of Plane 2

6 Seventh 8K of Plane 2

7Eighth 8K of Plane 2

where 'code' is:

Character Generator Select A (bits 3, 2, 5) when

bit-3 of the attribute byte is one.

Character Generator Select B (bits 1, 0, 4) when

bit-3 of the attribute byte is zero.

D7 D6 D5 D4 D3 D2 D1 D0

Font Select B bit-1

Font Select B bit-2

Font Select A bit-1

Font Select A bit-2

Font Select B bit-0

Font Select A bit-0

Reserved (0)

Revision 1.2 65 65540 / 545

Sequencer Registers

SEQUENCER MEMORY MODE

Read/Write at I/O Address 3C5h

Index 04h

Group 1 Protection

0Reserved (0)

1Extended Memory

0Restrict CPU access to 4 / 16 / 32

KBytes

1Allow complete access to memory

This bit should normally be 1.

2Odd/Even Mode

0CPU accesses to Odd/Even addresses

are directed to corresponding odd/even

planes

1All planes are accessed simultaneously

(IRGB color)

Bit-3 of this register must be 0 for this bit to

be effective. This bit affects only CPU write

accesses to display memory.

3Quad Four Mode

0CPU addresses are mapped to display

memory as defined by bit-2 of this

1CPU addresses are mapped to display

memory modulo 4. The two low order

CPU address bits select the display

memory plane.

This bit affects both CPU reads and writes

to display memory.

7-4 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (0)

Extended Memory

Odd/Even Mode

Quad Four Mode

Reserved (0)

SEQUENCER HORIZONTAL CHARACTER

COUNTER RESET (SR07)

Read/Write at I/O Address 3C5h

Index 07h

D7 D6 D5 D4 D3 D2 D1 D0

Don't Care

Writing to SR07 with any data will cause the

horizontal character counter to be held reset

(character counter output = 0) until a write to any

other sequencer register with any data value. The

write to any index in the range 0-6 clears the latch

that is holding the reset condition on the character

counter.

The vertical line counter is clocked by a signal

derived from horizontal display enable (which does

not occur if the horizontal counter is held reset).

Therefore, if the write to SR07 occurs during vertical

retrace, the horizontal and vertical counters will both

be set to zero. A write to any other sequencer

reasonable synchronization to an external event via

software control.

This is a standard VGA register which was not

documented by IBM.

Revision 1.2 66 65540 / 545

Revision 1.2 67 65540 / 545

CRT Controller Registers

Mnemonic Register Name Index Access Address Group Page

CRX CRTC Index – R/W 3B4h/3D4h – 68

CR00 Horizontal Total 00h R/W 3B5h/3D5h 0 68

CR01 Horizontal Display Enable End 01h R/W 3B5h/3D5h 0 68

CR02 Horizontal Blank Start 02h R/W 3B5h/3D5h 0 69

CR03 Horizontal Blank End 03h R/W 3B5h/3D5h 0 69

CR04 Horizontal Sync Start 04h R/W 3B5h/3D5h 0 70

CR05 Horizontal Sync End 05h R/W 3B5h/3D5h 0 70

CR06 Vertical Total 06h R/W 3B5h/3D5h 0 71

CR07 Overflow 07h R/W 3B5h/3D5h 0/3 71

CR08 Preset Row Scan 08h R/W 3B5h/3D5h 3 72

CR09 Maximum Scan Line 09h R/W 3B5h/3D5h 2/4 72

CR0A Cursor Start Scan Line 0Ah R/W 3B5h/3D5h 2 73

CR0B Cursor End Scan Line 0Bh R/W 3B5h/3D5h 2 73

CR0C Start Address High 0Ch R/W 3B5h/3D5h – 74

CR0D Start Address Low 0Dh R/W 3B5h/3D5h – 74

CR0E Cursor Location High 0Eh R/W 3B5h/3D5h – 74

CR0F Cursor Location Low 0Fh R/W 3B5h/3D5h – 74

CR10 Vertical Sync Start (See Note 2) 10h W or R/W 3B5h/3D5h 4 75

CR11 Vertical Sync End (See Note 2) 11h W or R/W 3B5h/3D5h 3/4 75

CR10 Lightpen High (See Note 2) 10h R 3B5h/3D5h – 75

CR11 Lightpen Low (See Note 2) 11h R 3B5h/3D5h – 75

CR12 Vertical Display Enable End 12h R/W 3B5h/3D5h 4 76

CR13 Offset 13h R/W 3B5h/3D5h 3 76

CR14 Underline Row 14h R/W 3B5h/3D5h 3 76

CR15 Vertical Blank Start 15h R/W 3B5h/3D5h 4 77

CR16 Vertical Blank End 16h R/W 3B5h/3D5h 4 77

CR17 CRT Mode Control 17h R/W 3B5h/3D5h 3/4 78

CR18 Line Compare 18h R/W 3B5h/3D5h 3 79

CR22 Memory Data Latches 22h R 3B5h/3D5h – 80

CR24 Attribute Controller Toggle 24h R 3B5h/3D5h – 80

Note 1: When MDA or Hercules emulation is enabled, the CRTC I/O address should be set to 3B0h-3B7h by

setting the I/O address select bit in the Miscellaneous Output register (3C2h/3CCh bit-0) to zero. When

CGA emulation is enabled, the CRTC I/O address should be set to 3D0h-3D7h by setting Misc Output

Note 2: In the EGA, all CRTC registers except the cursor (CR0C-CR0F) and light pen (CR10 and CR11)

registers are write-only (i.e., no read back). In both the EGA and VGA, the light pen registers are at

index locations conflicting with the vertical sync registers. This would normally prevent reads and writes

from occurring at the same index. Since the light pen registers are not normally useful, the VGA

provides software control (CR03 bit-7) of whether the vertical sync or light pen registers are readable at

indices 10-11.

CRT Controller Registers

Revision 1.2 68 65540 / 545

CRTC INDEX REGISTER (CRX)

Read/Write at I/O Address 3B4h/3D4h

5-0 CRTC Data Register Index

7-6 Reserved (0)

HORIZONTAL TOTAL REGISTER (CR00)

Read/Write at I/O Address 3B5h/3D5h

Index 00h

Group 0 Protection

This register is used for all VGA and EGA modes.

It is also used for 640 column CGA modes and

MDA/Hercules text mode. In all 320 column CGA

modes and Hercules graphics mode, the alternate

7-0 Horizontal Total

Total number of character clocks per line =

contents of this register + 5. This register

determines the horizontal sweep rate.

HORIZONTAL DISPLAY ENABLE END

Read/Write at I/O Address 3B5h/3D5h

Index 01h

Group 0 Protection

This register is used for all VGA and EGA modes on

CRTs. It is also used for 640 column CGA modes

and MDA/Hercules text mode. In all 320 column

CGA modes and Hercules graphics mode, the

alternate register is used.

7-0 Horizontal Display

Number of Characters displayed per scan

line – 1.

D7 D6 D5 D4 D3 D2 D1 D0

CRTC Index

Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Horizontal Total

D7 D6 D5 D4 D3 D2 D1 D0

Horizontal Display

CRT Controller Registers

HORIZONTAL BLANK START

Read/Write at I/O Address 3B5h/3D5h

Index 02h

Group 0 Protection

This register is used for all VGA and EGA modes.

It is also used for 640 column CGA modes and

MDA/Hercules text mode. In all 320 column CGA

modes and Hercules graphics mode, the alternate

7-0 Horizontal Blank Start

These bits specify the beginning of

horizontal blank in terms of character clocks

from the beginning of the display scan. The

period between Horizontal Display Enable

End and Horizontal Blank Start is the right

side border on screen.

HORIZONTAL BLANK END

Read/Write at I/O Address 3B5h/3D5h

Index 03h

Group 0 Protection

This register is used for all VGA and EGA modes.

It is also used for 640 column CGA modes and

MDA/Hercules text mode. In all 320 column CGA

modes and Hercules graphics mode, the alternate

4-0 Horizontal Blank End

These are the lower 5 bits of the character

clock count used to define the end of

horizontal blank. The interval between the

end of horizontal blank and the beginning of

the display (a count of 0) is the left side

border on the screen. If the horizontal blank

width desired is W clocks, the 5-bit value

programmed in this register = [contents of

CR02 + W] and 1Fh. The most significant

bit is programmed in CR05 bit-7. This bit =

[( CR02 + W) and 20h]/20h.

6-5 Display Enable Skew Control

Defines the number of character clocks that

the Display Enable signal is delayed to

compensate for internal pipeline delays.

7Light Pen Register Enable

This bit must be 1 for normal operation;

when this bit is 0, CRTC registers CR10

and CR11 function as lightpen readback

registers.

D7 D6 D5 D4 D3 D2 D1 D0

H Blank Start

D7 D6 D5 D4 D3 D2 D1 D0

H Blank End

DE Skew Control

Light Pen Register Enable

Revision 1.2 69 65540 / 545

CRT Controller Registers

D7 D6 D5 D4 D3 D2 D1 D0

HORIZONTAL SYNC START

Read/Write at I/O Address 3B5h/3D5h

Index 04h

Group 0 Protection

This register is used for all VGA and EGA modes.

It is also used for 640 column CGA modes and

MDA/Hercules text mode. In all 320 column CGA

modes and Hercules graphics mode, the alternate

7-0 Horizontal Sync Start

These bits specify the beginning of HSync

in terms of Character clocks from the

beginning of the display scan. These bits

also determine display centering on the

screen.

HORIZONTAL SYNC END

Read/Write at I/O Address 3B5h/3D5h

Index 05h

Group 0 Protection

This register is used for all VGA and EGA modes.

It is also used for 640 column CGA modes and

MDA/Hercules text mode. In all 320 column CGA

modes and Hercules graphics mode, the alternate

4-0 Horizontal Sync End

Lower 5 bits of the character clock count

which specifies the end of Horizontal Sync.

If the horizontal sync width desired is N

clocks, then these bits = (N + contents of

CR04) and 1Fh.

6-5 Horizontal Sync Delay

These bits specify the number of character

clocks that the Horizontal Sync is delayed to

compensate for internal pipeline delays.

7Horizontal Blank End Bit 5

This bit is the sixth bit of the Horizontal

Blank End Register (CR03).

D7 D6 D5 D4 D3 D2 D1 D0

Horizontal Sync Start

Horizontal Sync End

Horizontal Sync Delay

H Blank End Bit 5

Revision 1.2 70 65540 / 545

CRT Controller Registers

VERTICAL TOTAL REGISTER (CR06)

Read/Write at I/O Address 3B5h/3D5h

Index 06h

Group 0 Protection

This register is used in all modes.

7-0 Vertical Total

These are the 8 low order bits of a 10-bit

the CRT Controller Overflow Register. The

Vertical Total value specifies the total

number of scan lines (horizontal retrace

periods) per frame.

Programmed Count = Actual Count – 2

OVERFLOW REGISTER (CR07)

Read/Write at I/O Address 3B5h/3D5h

Index 07h

Group 0 Protection on bits 0-3 and bits 5-7

Group 3 Protection on bit 4

This register is used in all modes.

0Vertical Total Bit 8

1Vertical Display Enable End Bit 8

2Vertical Sync Start Bit 8

3Vertical Blank Start Bit 8

4Line Compare Bit 8

5Vertical Total Bit 9

6Vertical Display Enable End Bit 9

7Vertical Sync Start Bit 9

D7 D6 D5 D4 D3 D2 D1 D0

V Total (Scan Lines)

(Lower 8 Bits)

D7 D6 D5 D4 D3 D2 D1 D0

V Total Bit 8

V DE End Bit 8

V Sync Start Bit 8

V Blank Start Bit 8

Line Compare Bit 8

V Total Bit 9

V DE End Bit 9

V Sync Start Bit 9

Revision 1.2 71 65540 / 545

CRT Controller Registers

PRESET ROW SCAN REGISTER (CR08)

Read/Write at I/O Address 3B5h/3D5h

Index 08h

Group 3 Protection

4-0 Start Row Scan Count

These bits specify the starting row scan

count after each vertical retrace. Every

horizontal retrace increments the character

row scan line counter. The horizontal row

scan counter is cleared at maximum row

scan count during active display. This

modes.

6-5 Byte Panning Control

These bits specify the lower order bits for

the display start address. They are used for

horizontal panning in Odd/Even and Quad

modes.

7Reserved (0)

MAXIMUM SCAN LINE REGISTER (CR09)

Read/Write at I/O Address 3B5h/3D5h

Index 09h

Group 2 Protection on bits 0-4

Group 4 Protection on bits 5-7

4-0 Scan Lines Per Row

These bits specify the number of scan lines

in a row:

Programmed Value = Actual Value – 1

5Vertical Blank Start Register Bit 9

6Line Compare Register Bit 9

7Double Scan

0Normal Operation

1Enable scan line doubling

The vertical parameters in the CRT

Controller (even for a split screen) are not

affected, only the CRTC row scan counter

(bits 0-4 of this register) and display

memory addressing screen refresh are

affected.

D7 D6 D5 D4 D3 D2 D1 D0

Start Row Scan Count

Byte Panning Control

Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Scan Lines Per Row

V Blank Start Bit 9

Line Compare Bit 9

Double Scan

Revision 1.2 72 65540 / 545

CRT Controller Registers

CURSOR START SCAN LINE

Read/Write at I/O Address 3B5h/3D5h

Index 0Ah

Group 2 Protection

4-0 Cursor Start Scan Line

These bits specify the scan line of the

character row where the cursor display

begins.

5Cursor Off

0Text Cursor On

1Text Cursor Off

7-6 Reserved (0)

CURSOR END SCAN LINE

Read/Write at I/O Address 3B5h/3D5h

Index 0Bh

Group 2 Protection

4-0 Cursor End Scan Line

These bits specify the scan line of a character

row where the cursor display ends (i.e., last

scan line for the block cursor):

Programmed Value = Actual Value + 1

6-5 Cursor Delay

These bits define the number of character

clocks that the cursor is delayed to

compensate for internal pipeline delay.

7Reserved (0)

Note: If the Cursor Start Line is greater than the

Cursor End Line, then no cursor is generated.

D7 D6 D5 D4 D3 D2 D1 D0

Cursor Start Scan Line

Cursor off

Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Cursor End Scan Line

Cursor Delay

Reserved (0)

Revision 1.2 73 65540 / 545

CRT Controller Registers

START ADDRESS HIGH REGISTER (CR0C)

Read/Write at I/O Address 3B5h/3D5h

Index 0Ch

7-0 Display Start Address Low

This register contains the lower 8 bits of the

display start address. The display start

address points to the memory address

corresponding to the top left corner of the

screen.

7-0 Display Start Address High

This register contains the upper 8 bits of the

display start address. In CGA / MDA /

Hercules modes, this register wraps around

at the 16K, 32K, and 64KByte boundaries

respectively.

CURSOR LOCATION HIGH REGISTER (CR0E)

Read/Write at I/O Address 3B5h/3D5h

Index 0Eh

7-0 Text Cursor Location High

This register contains the upper 8 bits of the

memory address where the text cursor is

active. In CGA / MDA / Hercules modes,

this register wraps around at 16K, 32K, and

64KByte boundaries respectively.

START ADDRESS LOW REGISTER (CR0D)

Read/Write at I/O Address 3B5h/3D5h

Index 0Dh

D7 D6 D5 D4 D3 D2 D1 D0

Text Cursor Address

(Upper 8 bits)

D7 D6 D5 D4 D3 D2 D1 D0

Display Start Address Low

(Lower 8 bits)

D7 D6 D5 D4 D3 D2 D1 D0

Text Cursor Address

(Lower 8 bits)

CURSOR LOCATION LOW REGISTER (CR0F)

Read/Write at I/O Address 3B5h/3D5h

Index 0Fh

7-0 Text Cursor Location Low

This register contains the lower 8 bits of the

memory address where the text cursor is

active. In CGA / MDA / Hercules modes,

this register wraps around at 16K, 32K, and

64KByte boundaries respectively.

D7 D6 D5 D4 D3 D2 D1 D0

Display Start Address High

(Upper 8 bits)

Revision 1.2 74 65540 / 545

CRT Controller Registers

This register is used in all modes. This register is

not readable in MDA/Hercules emulation or when

CR03 bit-7=1.

3-0 Vertical Sync End

The lower 4 bits of the scan line count that

defines the end of vertical sync. If the

vertical sync width desired is N lines, then

bits 3-0 of this register = (CR10 + N) AND

0Fh.

4Vertical Interrupt Clear

0=Clear vertical interrupt generated on the

IRQ output; 1=Normal operation. This bit is

cleared by RESET.

5Vertical Interrupt Enable

0Enable vertical interrupt (default)

1Disable vertical interrupt

This bit is cleared by RESET.

6Select Refresh Type ( Ignored )

7Group Protect 0

This bit is logically ORed with XR15 bit-6

to determine the protection for group 0

registers. This bit is cleared by RESET.

0Enable writes to CR00-CR07

1Disable writes to CR00-CR07

CR07 bit-4 (Line Compare bit-9) is not

affected by this bit.

LIGHTPEN LOW REGISTER (CR11)

Read only at I/O Address 3B5h/3D5h

Index 11h

LIGHTPEN HIGH REGISTER (CR10)

Read only at I/O Address 3B5h/3D5h

Index 10h

Read-only Register loaded at line compare (the light

pen flip-flop is not implemented). Effective only in

MDA and Hercules modes or when CR03 bit-7 = 0.

Read-only Register loaded at line compare (the light

pen flip-flop is not implemented). Effective only in

MDA and Hercules modes or when CR03 bit-7 = 0.

D7 D6 D5 D4 D3 D2 D1 D0

V Sync End

V Interrupt Clear

V Interrupt Enable

Select Refresh Type

Protect CRTC (Group 0)

VERTICAL SYNC END REGISTER (CR11)

Read/Write at I/O Address 3B5h/3D5h

Index 11h

Group 3 Protection for bits 4 and 5

Group 4 Protection for bits 0-3, 6, and 7

VERTICAL SYNC START REGISTER (CR10)

Read/Write at I/O Address 3B5h/3D5h

Index 10h

Group 4 Protection

D7 D6 D5 D4 D3 D2 D1 D0

V Sync Start

(Lower 8 bits)

This register is used in all modes. This register is

not readable in (Line Compare bit-9) MDA/Hercules

emulation or when CR03 bit-7=1.

7-0 Vertical Sync Start

The eight low order bits of a 10-bit register.

The 9th and 10th bits are located in the

CRTC Overflow Register. They define the

scan line position at which Vertical Sync

becomes active.

Revision 1.2 75 65540 / 545

CRT Controller Registers

UNDERLINE LOCATION REGISTER (CR14)

Read/Write at I/O Address 3B5h/3D5h

Index 14h

Group 3 Protection

OFFSET REGISTER (CR13)

Read/Write at I/O Address 3B5h/3D5h

Index 13h

Group 3 Protection

4-0 Underline Position

These bits specify the underline's scan line

position within a character row.

Programmed Value = Actual scan line

number – 1

5Count by 4 for Doubleword Mode

0Frame Buffer Address is incremented

by 1 or 2

1Frame Buffer Address is incremented

by 4 or 2

See CR17 bit-3 for further details.

6Doubleword Mode

0Frame Buffer Address is byte or word

address

1Frame Buffer Address is doubleword

address

This bit is used in conjunction with CR17

bit-6 to select the display memory

addressing mode.

7Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Display Buffer Width

D7 D6 D5 D4 D3 D2 D1 D0

Underline Position

Count by 4

Doubleword Mode

Reserved (0)

7-0 Display Buffer Width. The byte starting

address of the next display row = Byte Start

Address for current row + K* (CR13 +

Z/2), where Z = bit defined in XR0D, K = 2

in byte mode, and K = 4 in word mode.

Byte, word and double word mode is

selected by bit-6 of CR17 and bit-6 of

CR14. A less significant bit than bit-0 of

this register is defined in the Auxiliary Offset

resolution of the bit map width. Byte, word

and doubleword mode affects the translation

of the 'logical' display memory address to

the 'physical' display memory address.

VERTICAL DISPLAY ENABLE END

Read/Write at I/O Address 3B5h/3D5h

Index 12h

Group 4 Protection

D7 D6 D5 D4 D3 D2 D1 D0

V Display Enable End

(Lower 8 bits)

7-0 Vertical Display Enable End

These are the eight low order bits of a 10-bit

the CRT Controller Overflow register. The

actual count = Contents of this register + 1.

Revision 1.2 76 65540 / 545

CRT Controller Registers

D7 D6 D5 D4 D3 D2 D1 D0

VERTICAL BLANK START

Read/Write at I/O Address 3B5h/3D5h

Index 15h

Group 4 Protection

This register is used in all modes.

7-0 Vertical Blank Start

These are the 8 low order bits of a 10-bit

the CRT Controller Overflow and Maximum

Scan Line Registers respectively. Together

these 10 bits define the scan line position

where vertical blank begins. The interval

between the end of the vertical display and

the beginning of vertical blank is the bottom

border on the screen.

VERTICAL BLANK END

Read/Write at I/O Address 3B5h/3D5h

Index 16h

Group 4 Protection

This register is used in all modes.

7-0 Vertical Blank End

These are the 8 low order bits of the scan

line count which specifies the end of Vertical

Blank. If the vertical blank width desired is

Z lines these bits = (Vertical Blank Start + Z)

and 0FFh.

D7 D6 D5 D4 D3 D2 D1 D0

V Blank Start

(Lower 8 bits) V Blank End

(Lower 8 bits)

Revision 1.2 77 65540 / 545

CRT Controller Registers

CRT MODE CONTROL REGISTER (CR17)

Read/Write at I/O Address 3B5h/3D5h

Index 17h

Group 3 Protection for bits 0, 1, and 3-7

Group 4 Protection for bit 2

3Count By Two

0Memory address counter is

incremented every character clock

1Memory address counter is

incremented every two character

clocks, used in conjunction with bit 5

of 0Fh.

Note: This bit is used in conjunction with

CR14 bit-5. The net effect is as follows:

Increment

CR14 CR17 Addressing

Bit-5 Bit-3 Every

0 0 1 CCLK

0 1 2 CCLK

1 0 4 CCLK

1 1 2 CCLK

Note: In Hercules graphics and Hi-res CGA

modes, address increments every two

clocks.

4Reserved (0)

5Address Wrap (effective only in word mode)

0Wrap display memory address at 16

KBytes. Used in IBM CGA mode.

1Normal operation (extended mode).

6Word Mode or Byte Mode

0Select Word Mode. In this mode the

display memory address counter bits

are shifted down by one, causing the

most-significant bit of the counter to

appear on the least-significant bit of

the display memory address output

1Select byte mode

Note: This bit is used in conjunction with

CR14 bit-6 to select byte, word, or double

word memory addressing as follows:

CR14 CR17

Bit-6 Bit-6 Addressing Mode

0 0 Word Mode

0 1 Byte Mode

1 0 Double Word Mode

1 1 Double Word Mode

Display memory addresses are affected as

shown in the table on the following page.

7CRTC Reset

0Force HSYNC and VSYNC inactive.

No other registers or outputs affected.

1Normal Operation

This bit is cleared by RESET.

0Compatibility Mode Support

This bit allows compatibility with the IBM

CGA two-bank graphics mode.

0Character row scan line counter bit 0

is substituted for memory address bit

13 during active display time

1Normal operation, no substitution

takes place

1Select Row Scan Counter

This bit allows compatibility with Hercules

graphics and with any other 4-bank graphics

system.

0Character row scan line counter bit 1

is substituted for memory address bit

14 during active display time

1Normal operation, no substitution

takes place

2Vertical Sync Select

This bit controls the vertical resolution of the

CRT Controller by permitting selection of

the clock rate input to the vertical counters.

When set to 1, the vertical counters are

clocked by the horizontal retrace clock

divided by 2.

D7 D6 D5 D4 D3 D2 D1 D0

Compatibility Mode

Select Row Scan Counter

VSync Select

Count by 2

Reserved (0)

Address Wrap

Word/Byte Mode

CRTC Reset

Revision 1.2 78 65540 / 545

CRT Controller Registers

LINE COMPARE

Read/Write at I/O Address 3B5h/3D5h

Index 18h

Group 3 Protection

7-0 Line Compare Target

These are the low order 8 bits of a 10-bit

the CRT Controller Overflow and Maximum

Scan Line Registers, respectively. This

function. When the scan line counter value

is equal to the contents of this register, the

memory address counter is cleared to 0. The

display memory address counter then

sequentially addresses the display memory

starting at address 0. Each subsequent row

address is generated by the addition of the

Offset Register contents. This register is not

affected by the double scanning bit (CR09

bit 7).

Display memory addresses are affected by CR17 bit

6 as shown in the table below:

Logical Physical Memory Address

Memory Byte Word DoubleWord

Address Mode Mode Mode

MA00 A00 Note 1 Note 2

MA01 A01 A00 Note 3

MA02 A02 A01 A00

MA03 A03 A02 A01

MA04 A04 A03 A02

MA05 A05 A04 A03

MA06 A06 A05 A04

MA07 A07 A06 A05

MA08 A08 A07 A06

MA09 A09 A08 A07

MA10 A10 A09 A08

MA11 A11 A10 A09

MA12 A12 A11 A10

MA13 A13 A12 A11

MA14 A14 A13 A12

MA15 A15 A14 A13

Note 1 = A13 * NOT CR17 bit 5

+ A15 * CR17 bit 5

Note 2 = A12 xor (A14 * XR04 bit 2)

Note 3 = A13 xor (A15 * XR04 bit 2)

D7 D6 D5 D4 D3 D2 D1 D0

Line Compare Target

(Lower 8 bits)

Revision 1.2 79 65540 / 545

CRT Controller Registers

This register may be used to read the state of

Graphics Controller Memory Data Latch 'n', where

'n' is controlled by the Graphics Controller Read

Map Select Register (GR04 bits 0–1) and is in the

range 0–3.

Writes to this register are not decoded and will be

ignored.

This is a standard VGA register which was not

documented by IBM.

MEMORY DATA LATCH

Read only at I/O Address 3B5h/3D5h

Index 22h

D7 D6 D5 D4 D3 D2 D1 D0

Data Latch n Bit 7

Data Latch n Bit 6

Data Latch n Bit 5

Data Latch n Bit 4

Data Latch n Bit 3

Data Latch n Bit 2

Data Latch n Bit 1

Data Latch n Bit 0

Revision 1.2 80 65540 / 545

CRT Controller Registers

ATTRIBUTE CONTROLLER TOGGLE

Read only at I/O Address 3B5h/3D5h

Index 24h

6-0 Reserved (0)

7Index/Data

This bit may be used to read back the state of

the attribute controller index/data latch. This

latch indicates whether the next write to the

attribute controller at 3C0h will be to the

0Next write is to the index

1Next write is to an indexed register

Writes to this register are not decoded and will be

ignored.

This is a standard VGA register which was not

documented by IBM.

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (0)

Index (0) / Data (1)

Revision 1.2 81 65540 / 545

Graphics Controller Registers

Mnemonic Register Name Index Access Address Group Page

GRX Graphics Index – R/W 3CEh 1 81

GR00 Set/Reset 00h R/W 3CFh 1 81

GR01 Enable Set/Reset 01h R/W 3CFh 1 82

GR02 Color Compare 02h R/W 3CFh 1 82

GR03 Data Rotate 03h R/W 3CFh 1 83

GR04 Read Map Select 04h R/W 3CFh 1 83

GR05 Graphics mode 05h R/W 3CFh 1 84

GR06 Miscellaneous 06h R/W 3CFh 1 86

GR07 Color Don't Care 07h R/W 3CFh 1 86

GR08 Bit Mask 08h R/W 3CFh 1 87

Graphics Controller Registers

SET/RESET REGISTER (GR00)

Read/Write at I/O Address 3CFh

Index 00h

Group 1 Protection

The SET/RESET and ENABLE SET/RESET

registers are used to 'expand' 8 bits of CPU data to

32 bits of display memory.

3-0 Set / Reset Planes 3-0

When the Graphics Mode register selects

Write Mode 0, all 8 bits of each display

memory plane are set as specified in the

corresponding bit in this register. The

Enable Set/Reset register (GR01) allows

selection of some of the source of data to be

written to individual planes. In Write Mode

3 (see GR05), these bits determine the color

value.

7-4 Reserved (0)

3-0 4-bit Index to Graphics Controller Registers

7-4 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Set/Reset Bit 0

Set/Reset Bit 1

Set/Reset Bit 2

Set/Reset Bit 3

Reserved (0)

GRAPHICS CONTROLLER

INDEX REGISTER (GRX)

Write only at I/O Address 3CEh

Group 1 Protection

D7 D6 D5 D4 D3 D2 D1 D0

Index to Graphics

Controller Data

Registers

Reserved (0)

Graphics Controller Registers

Revision 1.2 82 65540 / 545

3-0 Color Compare Planes 3-0

This register is used to 'reduce' 32 bits of

memory data to 8 bits for the CPU in 4-

plane graphics mode. These bits provide a

reference color value to compare to data read

from display memory planes 0-3. The Color

Don't Care register (GR07) is used to affect

the result. This register is active only if the

Graphics Mode register (GR05) is set to

Read Mode 1. A match between the

memory data and the Color Compare register

(GR02) (for the bits specified in the Color

Don't Care register) causes a logical 1 to be

placed on the CPU data bus for the

corresponding data bit; a mis-match returns

a logical 0.

7-4 Reserved (0)

ENABLE SET/RESET REGISTER (GR01)

Read/Write at I/O Address 3CFh

Index 01h

Group 1 Protection

3-0 Enable Set / Reset Planes 3-0

This register works in conjunction with the

Set/Reset register (GR00). The Graphics

Mode register must be programmed to Write

Mode 0 in order for this register to have any

effect.

0The corresponding plane is written

with the data from the CPU data bus

1The corresponding plane is set to 0 or

1 as specified in the Set/Reset Register

7-4 Reserved (0)

COLOR COMPARE REGISTER (GR02)

Read/Write at I/O Address 3CFh

Index 02h

Group 1 Protection

D7 D6 D5 D4 D3 D2 D1 D0

Enable Set/Reset Bit 0

Enable Set/Reset Bit 1

Enable Set/Reset Bit 2

Enable Set/Reset Bit 3

Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Color Compare (Plane 0)

Color Compare (Plane 1)

Color Compare (Plane 2)

Color Compare (Plane 3)

Reserved (0)

Graphics Controller Registers

Revision 1.2 83 65540 / 545

2-0 Data Rotate Count

These bits specify the number of bits to

rotate to the right the data being written by

the CPU. The CPU data bits are first

rotated, then subjected to the logical

operation as specified in the Function Select

bit field. The rotate function is active only if

the Graphics Mode register is programmed

for Write Mode 0.

4-3 Function Select

These Function Select bits specify the logical

function performed on the contents of the

processor latches (loaded on a previous

CPU read cycle) before the data is written to

display memory. These bits operate as

follows:

Bit 4 Bit 3 Result

0 0 No change to the Data

0 1 Logical 'AND' between Data

and latched data

1 0 Logical 'OR' between Data

and latched data

1 1 Logical 'XOR' between Data

and latched data

7-5 Reserved (0)

1-0 Read Map Select

This register is also used to 'reduce' 32 bits

of memory data to 8 bits for the CPU in the

4-plane graphics mode. These bits select the

memory plane from which the CPU reads

data in Read Mode 0. In Odd/Even mode,

bit-0 is ignored. In Quad mode, bits 0 and 1

are both ignored.

The four memory maps are selected as

follows:

Bit 1 Bit 0 Map Selected

0 0 Plane 0

0 1 Plane 1

1 0 Plane 2

1 1 Plane 3

7-2 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Read Map Select 0

Read Map Select 1

Reserved (0)

READ MAP SELECT REGISTER (GR04)

Read/Write at I/O Address 3CFh

Index 04h

Group 1 Protection

DATA ROTATE REGISTER (GR03)

Read/Write at I/O Address 3CFh

Index 03h

Group 1 Protection

D7 D6 D5 D4 D3 D2 D1 D0

Rotate Count 0

Rotate Count 1

Rotate Count 2

Function Select

Reserved (0)

Graphics Controller Registers

Revision 1.2 84 65540 / 545

1-0 Write Mode

For 16-bit writes, the operation is repeated

on the lower and upper bytes of CPU data.

1 0 Write Mode

0 0 Write mode 0. Each of the four

display memory planes is written

with the CPU data rotated by the

number of counts in the Rotate

Set/Reset Register is enabled for

any of the four planes. When the

Set/Reset Register is enabled, the

corresponding plane is written

with the data stored in the

Set/Reset Register.

0 1 Write mode 1. Each of the four

display memory planes is written

with the data previously loaded in

the processor latches. These

latches are loaded during all read

operations.

1 0 Write mode 2. The CPU data bus

data is treated as the color value for

the addressed byte in planes 0-3.

All eight pixels in the addressed

byte are modified unless protected

by the Bit Mask register setting. A

logical 1 in the Bit Mask register

sets the corresponding pixel in the

addressed byte to the color

specified on the data bus. A 0 in

the Bit Mask register sets the

corresponding pixel in the

addressed byte to the

corresponding pixel in the

processor latches. The Set/Reset

and Enable Set/Reset registers are

ignored. The Function Select bits

in the Data Rotate register are

used.

1 1 Write mode 3. The CPU data is

rotated then logically ANDed with

the contents of the Bit Mask

the addressed data's bit mask,

while the contents of the Set/Reset

value.

A '0' on the data bus (mask)

causes the corresponding pixel in

the addressed byte to be set to the

corresponding pixel in the

processor latches.

A '1' on the data bus (mask)

causes the corresponding pixel in

the addressed byte to be set to the

color value specified in the

Set/Reset register.

The Enable Set/Reset register is

ignored. The Data Rotate is used.

This write mode can be used to fill

an area with a single color and

pattern.

2Reserved (0)

3Read Mode

0The CPU reads data from one of the

planes as selected in the Read Map

Select register.

1The CPU reads the 8-bit result of the

logical comparison between all eight

pixels in the four display planes and

the contents of the Color Compare and

Color Don't Care registers. The CPU

reads a logical 1 if a match occurs for

each pixel and logical 0 if a mis-match

occurs. In 16-bit read cycles, this

operation is repeated on the lower and

upper bytes.

(Continued on following page)

D7 D6 D5 D4 D3 D2 D1 D0

Write Mode

Reserved (0)

Read Mode

Odd/Even Mode

Shift Register Mode

Reserved (0)

GRAPHICS MODE REGISTER (GR05)

Read/Write at I/O Address 3CFh

Index 05h

Group 1 Protection

Graphics Controller Registers

Revision 1.2 85 65540 / 545

4Odd/Even Mode

0All CPU addresses sequentially access all planes

1Even CPU addresses access planes 0 and 2, while odd CPU addresses access planes 1 and 3. This

option is useful for compatibility with the IBM CGA memory organization.

6-5 Shift Register Mode

These two bits select the data shift pattern used when passing data from the four memory planes through

the four video shift registers. If data bits 0-7 in memory planes 0-3 are represented as M0D0-M0D7,

M1D0-M1D7, M2D0-M2D7, and M3D0-M3D7 respectively, then the data in the serial shift registers is

shifted out as follows:

Last Bit 1st Bit Out-

Shifted Shift Shifted put

65 Out Direction Out to:

00: M0D0 M0D1 M0D2 M0D3 M0D4 M0D5 M0D6 M0D7 Bit 0

M1D0 M1D1 M1D2 M1D3 M1D4 M1D5 M1D6 M1D7 Bit 1

M2D0 M2D1 M2D2 M2D3 M2D4 M2D5 M2D6 M2D7 Bit 2

M3D0 M3D1 M3D2 M3D3 M3D4 M3D5 M3D6 M3D7 Bit 3

01: M1D0 M1D2 M1D4 M1D6 M0D0 M0D2 M0D4 M0D6 Bit 0

M1D1 M1D3 M1D5 M1D7 M0D1 M0D3 M0D5 M0D7 Bit 1

M3D0 M3D2 M3D4 M3D6 M2D0 M2D2 M2D4 M2D6 Bit 2

M3D1 M3D3 M3D5 M3D7 M2D1 M2D3 M2D5 M2D7 Bit 3

1x: M3D0 M3D4 M2D0 M2D4 M1D0 M1D4 M0D0 M0D4 Bit 0

M3D1 M3D5 M2D1 M2D5 M1D1 M1D5 M0D1 M0D5 Bit 1

M3D2 M3D6 M2D2 M2D6 M1D2 M1D6 M0D2 M0D6 Bit 2

M3D3 M3D7 M2D3 M2D7 M1D3 M1D7 M0D3 M0D7 Bit 3

Note: If the Shift Register is not loaded every character clock (see SR01 bits 2&4) then the four 8-bit

shift registers are effectively 'chained' with the output of shift register 1 becoming the input to

shift register 0 and so on. This allows one to have a large monochrome (or 4 color) bit map and

display one portion thereof.

Note: If XR28 bit-4 is set (8-bit video path), GR05 bit-6 must be set to 0:

0x and XR28 bit-4=1: M3D0 M2D0 M1D0 M0D0 Bit 0

M3D1 M2D1 M1D1 M0D1 Bit 1

M3D2 M2D2 M1D2 M0D2 Bit 2

M3D3 M2D3 M1D3 M0D3 Bit 3

M3D4 M2D4 M1D4 M0D4 Bit 4

M3D5 M2D5 M1D5 M0D5 Bit 5

M3D6 M2D6 M1D6 M0D6 Bit 6

M3D7 M2D7 M1D7 M0D7 Bit 7

7Reserved (0)

Graphics Controller Registers

Revision 1.2 86 65540 / 545

MISCELLANEOUS REGISTER (GR06)

Read/Write at I/O Address 3CFh

Index 06h

Group 1 Protection

0Graphics/Text Mode

0Text Mode

1Graphics mode

1Chain Odd/Even Planes

This mode can be used to double the address

space into display memory.

1CPU address bit A0 is replaced by a

higher order address bit. The state of

A0 determines which memory plane is

to be selected:

A0 = 0: select planes 0 and 2

A0 = 1: select planes 1 and 3

0A0 not replaced

3-2 Memory Map Mode

These bits control the mapping of the display

memory into the CPU address space as

follows (also used in extended modes):

Bit 3 Bit 2 CPU Address

0 0 A0000h-BFFFFh

0 1 A0000h-AFFFFh

1 0 B0000h-B7FFFh

1 1 B8000h-BFFFFh

7-4 Reserved (0)

COLOR DON'T CARE REGISTER (GR07)

Read/Write at I/O Address 3CFh

Index 07h

Group 1 Protection

3-0 Ignore Color Plane (3-0)

0This causes the corresponding bit of

the Color Compare register to be a

don't care during a comparison.

1The corresponding bit of the Color

Compare register is enabled for color

comparison. This register is active in

Read Mode 1 only.

7-4 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Graphics/Text Mode

Chain Odd/Even Planes

Memory Map Mode

Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Ignore Color Plane 0

Ignore Color Plane 1

Ignore Color Plane 2

Ignore Color Plane 3

Reserved (0)

Graphics Controller Registers

Revision 1.2 87 65540 / 545

7-0 Bit Mask

This bit mask is applicable to any data

written by the CPU, including that subject to

a rotate, logical function (AND, OR, XOR),

Set/Reset, and No Change. In order to

execute a proper read-modify-write cycle

into displayed memory, each byte must first

be read (and latched by the VGA), the Bit

Mask register set, and the new data then

written. The bit mask applies to all four

planes simultaneously.

0The corresponding bit in each of the

four memory planes is written from

the corresponding bit in the latches

1Unrestricted manipulation of the

corresponding data bit in each of the

four memory planes is permitted

D7 D6 D5 D4 D3 D2 D1 D0

Bit Mask

0=Immune to change

1=Change permitted

BIT MASK REGISTER (GR08)

Read/Write at I/O Address 3CFh

Index 08h

Group 1 Protection

Revision 1.2 88 65540 / 545

Revision 1.2 89 65540 / 545

Attribute Controller and Color Palette Registers

Mnemonic Register Name Index Access Address Group Page

ARX Attribute Index (for 3C0/3C1h) – R/W 3C0h 1 89

AR00-AR0F Attribute Controller Color Data 00-0Fh R/W 3C0h/3C1h 1 90

AR10 Mode Control 10h R/W 3C0h/3C1h 1 90

AR11 Overscan Color 11h R/W 3C0h/3C1h 1 91

AR12 Color Plane Enable 12h R/W 3C0h/3C1h 1 91

AR13 Horizontal Pixel Panning 13h R/W 3C0h/3C1h 1 92

AR14 Pixel Pad 14h R/W 3C0h/3C1h 1 92

DACMASK Color Palette Pixel Mask – R/W 3C6h 6 93

DACSTATE Color Palette State – R 3C7h – 93

DACRX Color Palette Read-Mode Index – W 3C7h 6 94

DACX Color Palette Index (for 3C9h) – R/W 3C8h 6 94

DACDATA Color Palette Data 00-FFh R/W 3C9h 6 94

Attribute Controller and VGA Color Palette Registers

In regular VGA mode, all Attribute Controller

registers are located at the same byte address (3C0h)

in the CPU I/O space. An internal flip-flop controls

the selection of either the Attribute Index or Data

Registers. To select the Index Register, an I/O Read

is executed to address 3BAh/3DAh (Input Status

3C0h, this flip-flop toggles, and the Data Register is

ready to be accessed. Every I/O Write to address

3C0h toggles this flip-flop. The flip-flop does not

have any effect on the reading of the Attribute Con-

troller registers. The Attribute Controller index reg-

ister is always read back at address 3C0h, the data

An option is provided to allow the Attribute

Controller Index register to be mapped to 3C0h and

the Data register to 3C1h to allow word I/O accesses.

Another option allows the Attribute Controller to be

both read and written at either 3C0h or 3C1h (EGA

compatible mode). These optional mappings are

selected by 'CPU Interface Register 1' (XR02[4-3])

and are not standard VGA capabilities.

The VGA color palette is used to further modify the

video color output following the attribute controller

color registers. The color palette logic is contained

on-chip; extension register XR06 is provided to

control various optional capabilities. DAC logic is

provided on-chip to convert the final video output of

the color palette to analog RGB outputs for use in

driving a CRT display. Output comparator logic is

also provided on-chip to duplicate the SENSE

function (see Status Register 0 readable at 3C2h).

ATTRIBUTE INDEX

Read/Write at I/O Address 3C0h

Group 1 Protection

4-0 Attribute Controller Index

These bits point to one of the internal

registers of the Attribute Controller.

5Enable Video

0Disable video, allowing the Attribute

Controller Color registers to be

accessed by the CPU

1Enable video, causing the Attribute

Controller Color registers (AR00-

AR0F) to be inaccessible to the CPU

7-6 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Index to

Attribute Controller

Data Registers

Enable Video

Reserved (0)

Attribute Controller and Color Palette Registers

Revision 1.2 90 65540 / 545

2Enable Line Graphics Character Codes

This bit is dependent on bit 0 of the Override

0Make the ninth pixel appear the same

as the background

1For special line graphics character

codes (0C0h-0DFh), make the ninth

pixel identical to the eighth pixel of the

character. For other characters, the

ninth pixel is the same as the

background.

3Enable Blink/Select Background Intensity

The blinking counter is clocked by the

VSYNC signal. The Blink frequency is

defined in the Blink Rate Control Register

(XR60).

0Disable Blinking and enable text mode

background intensity

1Enable the blink attribute in text and

graphics modes.

4Reserved (0)

5Split Screen Horizontal Panning Mode

0Scroll both screens horizontally as

specified in the Pixel Panning register

1Scroll horizontally only the top screen

as specified in the Pixel panning

6256 Color Output Assembler

06-bits of video (translated from 4-bits

by the internal color palette) are output

every dot clock

1Two 4-bit sets of video data are

assembled to generate 8-bit video data

at half the frequency of the internal dot

clock (256 color mode).

7Video Output 5-4 Select

0Video bits 4 and 5 are generated by the

internal Attribute Controller color

palette registers

1Video bits 4 and 5 are the same as bits

0 and 1 in the Pixel Pad register

(AR14)

ATTRIBUTE CONTROLLER

COLOR REGISTERS (AR00-AR0F)

Read at I/O Address 3C1h

Write at I/O Address 3C0/1h

Index 00-0Fh

Group 1 Protection or XR63 bit-6

5-0 Color Value

These bits are the color value in the

respective attribute controller color register

as pointed to by the attribute index register.

7-6 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Blue

Green

Red

Secondary Blue

Secondary Green

Secondary Red

Reserved (0)

ATTRIBUTE CONTROLLER

MODE CONTROL REGISTER (AR10)

Read at I/O Address 3C1h

Write at I/O Address 3C0/1h

Index 10h

Group 1 Protection

D7 D6 D5 D4 D3 D2 D1 D0

Text/Graphics Mode

Mono/Color Display

Enable Line Graphics

Select Background

Reserved (0)

Horizontal Split Screen

256 Color

Video Output 4-5 Select

0Text/Graphics Mode

0Select text mode

1Select graphics mode

1Monochrome/Color Display

0Select color display attributes

1Select mono display attributes

Attribute Controller and Color Palette Registers

Revision 1.2 91 65540 / 545

OVERSCAN COLOR REGISTER (AR11)

Read at I/O Address 3C1h

Write at I/O Address 3C0/1h

Index 11H

Group 1 Protection

COLOR PLANE ENABLE REGISTER (AR12)

Read at I/O Address 3C1h

Write at I/O Address 3C0/1h

Index 12h

Group 1 Protection

3-0 Color Plane (3-0) Enable

0Force the corresponding color plane

pixel bit to 0 before it addresses the

color palette

1Enable the plane data bit of the

corresponding color plane to pass

5-4 Display Status Select

These bits select two of the eight color

outputs to be read back in the Input Status

output color combinations available on the

status bits are as follows:

Status Register 1

Bit 5 Bit 4 Bit 5 Bit 4

0 0 P2 P0

0 1 P5 P4

1 0 P3 P1

1 1 P7 P6

7-6 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Overscan Color

7-0 Overscan Color

These 8 bits define the overscan (border)

color value. For monochrome displays,

these bits should be zero.

The border color is displayed in the interval

after Display Enable End and before Blank

Start (end of display area; i.e. right side and

bottom of screen) and between Blank End

and Display Enable Start (beginning of

display area; i.e. left side and top of screen).

D7 D6 D5 D4 D3 D2 D1 D0

Color Plane 0 Enable

Color Plane 1 Enable

Color Plane 2 Enable

Color Plane 3 Enable

Display Status Select

Reserved (0)

Attribute Controller and Color Palette Registers

Revision 1.2 92 65540 / 545

ATTRIBUTE CONTROLLER HORIZONTAL

PIXEL PANNING REGISTER (AR13)

Read at I/O Address 3C1h

Write At I/O Address 3C0/1h

Index 13h

Group 1 Protection

3-0 Horizontal Pixel Panning

These bits select the number of pixels to shift

the display horizontally to the left. Pixel

panning is available in both text and graphics

modes. In 9 pixel/character text mode, the

output can be shifted a maximum of 9 pixels.

In 8 pixel/character text mode and all

graphics modes a maximum shift of 8 pixels

is possible. In 256-color mode (output

assembler AR10 bit-6 = 1), bit 0 of this

panning positions per display byte. In Shift

Load 2 and Shift Load 4 modes, register

CR08 provides single pixel resolution for

panning. Panning is controlled as follows:

Number of Pixels Shifted

9-dot 8-dot 256-color

AR13 mode mode mode

0 1 0 0

1 2 1 --

2 3 2 1

3 4 3 --

4 5 4 2

5 6 5 --

6 7 6 3

7 8 7 --

8 0 -- --

7-4 Reserved (0)

ATTRIBUTE CONTROLLER

PIXEL PAD REGISTER (AR14)

Read at I/O Address 3C1h

Write At I/O Address 3C0/1h

Index 14h

Group 1 Protection

D7 D6 D5 D4 D3 D2 D1 D0

Video bit-4 if AR10 bit7=1

Video bit-5 if AR10 bit7=1

Video bit-6 if not 256-color

Video bit-7 if not 256-color

Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Horizontal

Pixel Panning

Reserved (0)

1-0 Video Bits 5-4

These bits are output as video bits 5 and 4

when AR10 bit-7 = 1. They are disabled in

the 256 color mode.

3-2 Video Bits 7-6

These bits are output as video bits 7 and 6 in

all modes except 256-color mode.

7-4 Reserved (0)

Attribute Controller and Color Palette Registers

Revision 1.2 93 65540 / 545

COLOR PALETTE

PIXEL MASK REGISTER (DACMASK)

Read/Write at I/O Address 3C6h

Group 6 Protection

1-0 Palette State 1-0

Status bits indicate the I/O address of the last

CPU write to the Color Palette:

00 The last write was to 3C8h

(write mode)

11 The last write was to 3C7h

(read mode)

7-2 Reserved (0)

To allow saving and restoring the state of the video

subsystem, this register is required since the color

palette index register is automatically incremented

differently depending on whether the index is written

at 3C7h or 3C8h.

COLOR PALETTE

STATE REGISTER (DACSTATE)

Read only at I/O Address 3C7h

The contents of this register are logically ANDed

with the 8 bits of video data coming into the color

palette. Zero bits in this register therefore cause the

corresponding address input to the color palette to be

zero. For example, if this register is programmed

with 7, only color palette registers 0-7 would be

accessible; video output bits 3-7 would be ignored

and all color values would map into the lower 8

locations in the color palette.

D7 D6 D5 D4 D3 D2 D1 D0

Pixel Mask Bit-0

Pixel Mask Bit-1

Pixel Mask Bit-2

Pixel Mask Bit-3

Pixel Mask Bit-4

Pixel Mask Bit-5

Pixel Mask Bit-6

Pixel Mask Bit-7

D7 D6 D5 D4 D3 D2 D1 D0

Palette State 0

Palette State 1

Reserved (0)

Attribute Controller and Color Palette Registers

Revision 1.2 94 65540 / 545

COLOR PALETTE

READ-MODE INDEX REGISTER (DACRX)

Write only at I/O Address 3C7h

Group 6 Protection

COLOR PALETTE

INDEX REGISTER (DACX)

Read/Write at I/O Address 3C8h

Group 6 Protection

The palette index register is used to point to one of

256 palette data registers. Each data register is 18

bits in length (6 bits each for red, green, and blue),

so the data values must be read as a sequence of 3

bytes. After writing the index register (3C7h or

3C8h), data values may be read from or written to

the color palette data register port (3C9h) in

sequence: first red, then green, then blue, then

repeat for the next location if desired (the index is

incremented automatically by the palette logic).

The index may be written at 3C7h and may be read

or written at 3C8h. When the index value is written

to either port, it is written to both the index register

and a 'save' register. The save register (not the index

D7 D6 D5 D4 D3 D2 D1 D0

Color Palette Index 0

Color Palette Index 1

Color Palette Index 2

Color Palette Index 3

Color Palette Index 4

Color Palette Index 5

Color Palette Index 6

Color Palette Index 7

current data register. When the index value is

written to 3C7h (read mode), it is written to both the

index register and the save register, then the index

index value is written to 3C8h (write mode), the

automatic incrementing of the index register does not

occur.

After the third of the three sequential data reads from

(or writes to) 3C9h is completed, the save and index

registers are both automatically incremented by the

palette logic. This allows the entire palette (or any

subset) to be read (written) by writing the index of

the first color in the set, then sequentially reading

(writing) the values for each color, without having to

reload the index every three bytes.

The state of the RGB sequence is not saved; the user

must access each three bytes in an uninterruptible

sequence (or be assured that interrupt service

routines will not access the palette index or data

registers). When the index register is written (at

either port), the RGB sequence is restarted. Data

reads and writes may be intermixed; either reads or

writes increment the palette logic's RGB sequence

counter.

The palette's save register always contains a value

one less than the readable index value if the last

index write was to the 'read mode' port. The state is

saved of which port (3C7h or 3C8h) was last

written; that information is returned on reads from

3C7h.

COLOR PALETTE

DATA REGISTERS (DACDATA 00-FF)

Read/Write at I/O Address 3C9h Index 00h-FFh

Group 6 Protection

D7 D6 D5 D4 D3 D2 D1 D0 Access

1st 2nd 3rd

Red 0 Green 0 Blue 0

Red 1 Green 1 Blue 1

Red 2 Green 2 Blue 2

Red 3 Green 3 Blue 3

Red 4 Green 4 Blue 4

Red 5 Green 5 Blue 5

Reserved (0)

Reset Codes: x = Not changed by reset (indeterminate on power-up) – = Not implemented (always reads 0)

d = Set from the corresponding data bus pin on trailing edge of reset • = Reserved (read/write, reset to 0)

h = Read-only Hercules Configuration Register Readback bits 0/1 = Reset to 0 or 1 by trailing edge of reset

r = Chip revision # (starting from 0000)

Revision 1.2 95 65540 / 545

Extension Registers

Mnemonic Group Extension Register Name Index Access Address Reset Page

XRX -- Extension Index -- R/W 3D6h - x x x x x x x 97

XR00 Misc Chip Version (65540: v=0; 65545: v=1) 00h RO 3D7h 1 1 0 1 v r r r 97

XR01 Misc Configuration 01h RO 3D7h d d d d d d d d 98

XR02 Misc CPU Interface Control 1 02h R/W 3D7h 0 0 0 0 0 0 0 0 99

XR03 Misc CPU Interface Control 2 03h R/W 3D7h - - - - - - 0 x 100

XR04 Misc Memory Control 1 04h R/W 3D7h - - 0 - - 0 0 0 101

XR05 Misc Memory Control 2 05h R/W 3D7h 0 0 0 0 0 0 0 0 102

XR06 Misc Palette Control 06h R/W 3D7h 0 0 0 0 0 0 0 0 103

XR0E Misc Text Mode Control 0Eh R/W 3D7h 0 0 0 0 0 0 - - 106

XR28 Misc Video Interface 28h R/W 3D7h 0 0 0 0 - - 0 - 117

XR29 Misc Half Line Compare 29h R/W 3D7h x x x x x x x x 117

XR70 Misc Setup / Disable Control 70h R/W 3D7h 0 - - - - - - - 150

XR72 Misc External Device I/O 72h R/W 3D7h 0 0 0 0 0 0 0 • 151

XR73 Misc DPMS Control 73h R/W 3D7h 0 0 - - 0 0 0 0 152

XR7D Misc Diagnostic (65545 Only) 7Dh R/W 3D7h 0 - - - - - - - 152

XR7F Misc Diagnostic 7Fh R/W 3D7h 0 0 x x x x 0 0 153

XR07 Mapping I/O Base (65545 Only) 07h R/W 3D7h 1 1 1 1 0 1 0 0 104

XR08 Mapping Linear Addressing Base 08h R/W 3D7h x x x x x x x x 104

XR0B Mapping CPU Paging 0Bh R/W 3D7h - - 0 0 • 0 0 0 105

XR0C Mapping Start Address Top 0Ch R/W 3D7h - - - - - - x x 105

XR10 Mapping Single/Low Map 10h R/W 3D7h x x x x x x x x 108

XR11 Mapping High Map 11h R/W 3D7h x x x x x x x x 108

XR0F Software Flags Software Flags 0 0Fh R/W 3D7h x x x x x x x x 107

XR2B Software Flags Software Flags 1 2Bh R/W 3D7h 0 0 0 0 0 0 0 0 118

XR44 Software Flags Software Flags 2 44h R/W 3D7h x x x x x x x x 127

XR45 Software Flags Software Flags 3 45h R/W 3D7h x x x x x x x x 127

XR14 Compatibility Emulation Mode 14h R/W 3D7h 0 0 0 0 h h 0 0 109

XR15 Compatibility Write Protect 15h R/W 3D7h 0 0 0 0 0 0 0 0 110

XR1F Compatibility Virtual EGA Switch 1Fh R/W 3D7h 0 - - - x x x x 115

XR7E Compatibility CGA/Hercules Color Select 7Eh R/W 3D7h - - x x x x x x 153

XR30 Clock Clock Divide Control 30h R/W 3D7h • • • • x x x x 121

XR31 Clock Clock M-Divisor 31h R/W 3D7h • x x x x x x x 122

XR32 Clock Clock N-Divisor 32h R/W 3D7h • x x x x x x x 122

XR33 Clock Clock Control 33h R/W 3D7h 0 0 0 0 • 0 0 0 123

XR3A MultiMedia Color Key 0 3Ah R/W 3D7h x x x x x x x x 124

XR3B MultiMedia Color Key 1 3Bh R/W 3D7h x x x x x x x x 124

XR3C MultiMedia Color Key 2 3Ch R/W 3D7h x x x x x x x x 125

XR3D MultiMedia Color Key Mask 0 3Dh R/W 3D7h x x x x x x x x 125

XR3E MultiMedia Color Key Mask 1 3Eh R/W 3D7h x x x x x x x x 126

XR3F MultiMedia Color Key Mask 2 3Fh R/W 3D7h x x x x x x x x 126

XR40 BitBLT BitBLT Configuration (65545 Only) 40h R/W 3D7h - - - - - - x x 127

Extension Registers

Reset Codes: x = Not changed by reset (indeterminate on power-up) – = Not implemented (always reads 0)

d = Set from the corresponding data bus pin on trailing edge of reset • = Reserved (read/write, reset to 0)

h = Read-only Hercules Configuration Register Readback bits 0/1 = Reset to 0 or 1 by trailing edge of reset

r = Chip revision # (starting from 0000)

Revision 1.2 96 65540 / 545

Extension Registers

Mnemonic Group Extension Register Name Index Access Address Reset Page

XR0D Alternate Auxiliary Offset 0Dh R/W 3D7h - - - - - - x x 106

XR16 Alternate Vertical Overflow 16h R/W 3D7h • 0 • 0 • 0 0 0 111

XR17 Alternate Horizontal Overflow 17h R/W 3D7h • 0 0 0 0 0 0 0 111

XR18 Alternate Alternate Horizontal Display End 18h R/W 3D7h x x x x x x x x 112

XR19 Alternate Alternate Horizontal Sync Start 19h R/W 3D7h x x x x x x x x 112

XR1A Alternate Alternate Horizontal Sync End 1Ah R/W 3D7h x x x x x x x x 113

XR1B Alternate Alternate Horizontal Total 1Bh R/W 3D7h x x x x x x x x 113

XR1C Alternate Alternate H Blank Start / H Panel Size 1Ch R/W 3D7h x x x x x x x x 114

XR1D Alternate Alternate Horizontal Blank End 1Dh R/W 3D7h 0 x x x x x x x 114

XR1E Alternate Alternate Offset 1Eh R/W 3D7h x x x x x x x x 115

XR24 Alternate Alternate Maximum Scan Line 24h R/W 3D7h • • • x x x x x 116

XR25 Alternate Alternate Text Mode / H Virtual Panel Size 25h R/W 3D7h x x x x x x x x 116

XR26 Alternate Alternate Horizontal Sync Start Register 26h R/W 3D7h x x x x x x x x 116

XR64 Alternate Alternate Vertical Total 64h R/W 3D7h xxxxxxxx 145

XR65 Alternate Alternate Overflow 65h R/W 3D7h x x x • • x x x 145

XR66 Alternate Alternate Vertical Sync Start 66h R/W 3D7h xxxxxxxx 146

XR67 Alternate Alternate Vertical Sync End 67h R/W 3D7h • • • • x x x x 146

XR2C Flat Panel FLM Delay 2Ch R/W 3D7h xxxxxxxx 118

XR2D Flat Panel LP Delay (Comp Enabled) 2Dh R/W 3D7h xxxxxxxx 119

XR2E Flat Panel LP Delay (Comp Disabled) 2Eh R/W 3D7h xxxxxxxx 119

XR2F Flat Panel LP Width 2Fh R/W 3D7h xxxxxxxx 120

XR4F Flat Panel Panel Format 2 4Fh R/W 3D7h x x • • • x x x 128

XR50 Flat Panel Panel Format 1 50h R/W 3D7h xxxxxxxx 129

XR51 Flat Panel Display Type 51h R/W 3D7h 0 0 0 • 0 0 0 0 130

XR52 Flat Panel Power Down Control 52h R/W 3D7h 00000001 131

XR53 Flat Panel Panel Format 3 53h R/W 3D7h • 0 0 0 0 0 x 0 132

XR54 Flat Panel Panel Interface 54h R/W 3D7h xxxxxxxx 133

XR55 Flat Panel Horizontal Compensation 55h R/W 3D7h x x x • • x x x 134

XR56 Flat Panel Horizontal Centering 56h R/W 3D7h xxxxxxxx 135

XR57 Flat Panel Vertical Compensation 57h R/W 3D7h xxxxxxxx 136

XR58 Flat Panel Vertical Centering 58h R/W 3D7h xxxxxxxx 137

XR59 Flat Panel Vertical Line Insertion 59h R/W 3D7h x x x • x x x x 137

XR5A Flat Panel Vertical Line Replication 5Ah R/W 3D7h • • • • x x x x 138

XR5B Flat Panel Panel Power Sequencing Delay 5Bh R/W 3D7h 10000001 138

XR5C Flat Panel Activity Indicator Control 5Ch R/W 3D7h 0 x • x x x x x 139

XR5D Flat Panel FP Diagnostic 5Dh R/W 3D7h 00000000 140

XR5E Flat Panel M (ACDCLK) Control 5Eh R/W 3D7h xxxxxxxx 141

XR5F Flat Panel Power Down Mode Refresh 5Fh R/W 3D7h xxxxxxxx 141

XR60 Flat Panel Blink Rate Control 60h R/W 3D7h 10000011 142

XR61 Flat Panel SmartMap™ Control 61h R/W 3D7h xxxxxxxx 143

XR62 Flat Panel SmartMap™ Shift Parameter 62h R/W 3D7h xxxxxxxx 144

XR63 Flat Panel SmartMap™ Color Mapping Control 63h R/W 3D7h x1xxxxxx 144

XR68 Flat Panel Vertical Panel Size 68h R/W 3D7h xxxxxxxx 147

XR6C Flat Panel Programmable Output Drive 6Ch R/W 3D7h • • 0 0 0 0 d • 147

XR6E Flat Panel Polynomial FRC Control 6Eh R/W 3D7h 10111101 148

XR6F Flat Panel Frame Buffer Control 6Fh R/W 3D7h

00000000

149

Extension Registers (Continued)

Extension Registers

Revision 1.2 97 65540 / 545

EXTENSION INDEX REGISTER (XRX)

Read/Write at I/O Address 3D6h

6-0 Index value used to access the extension

registers

7Reserved (0)

CHIPS VERSION REGISTER (XR00)

Read only at I/O Address 3D7h

Index 00h

7-0 Chip Version - 65540 Chip Versions start at

D0h and are incremented for every silicon

step. 65545 Chip Versions start at D8h and

are incremented for every silicon step.

D7 D6 D5 D4 D3 D2 D1 D0

Index to

Extension Registers

Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Chip Revision

-0=65540, 1=65545

Chip Type (1101)

Extension Registers

Revision 1.2 98 65540 / 545

These bits latch the state of memory address bus A

(AA bus) bits 0-7 on the rising edge of RESET#.

The state of bits 0-7 after RESET# effect chip in-

ternal logic as indicated below. During RESET#,

internal pullups are enabled for AA[7:0] and hence

the status of these bits will be high if no external

pull-down resistors are present on these pins.

This register is not related to the Virtual EGA

Switch register (XR1F).

2-0 CFG2:0 - CPU Bus Type

2 1 0

2X# ISA# LB# Bus Type

L L L Reserved

L L H Reserved

L H L Reserved

L H H CPU Direct (2x LCLK)

(pin-23=CRESET)

H L L Reserved

H L H ISA Bus

H H L PCI Bus (65545 only)

H H H VL-Bus (1x clk)

(pin-23=RDYRTN#)

3CFG3 - Reserved

The pin corresponding to this bit has no

internal hardware function so may be used

for sampling external conditions at reset.

4CFG4 - Reserved

The pin corresponding to this bit must be

sampled high on reset so this bit will always

read back 1.

CONFIGURATION REGISTER (XR01)

Read only at I/O Address 3D7h

Index 01h

5CFG5 - Oscillator Source Select

0External Oscillator drives XTALI (pin

203)

1Internal Oscillator (series resonant

crystal connected to XTALI and

XTALO)

6CFG 6 - A26-A27 Enable

0Pin 53 is A26 (ignore for ISA & PCI)

Pin 54 is A27 (ignore for ISA & PCI)

1Pin 53 is ACTI

Pin 54 is ENABKL

7CFG7 - Internal Clock Test Mode

0Enable internal clock test mode.

Output MCLK on pin-30 (A25) and

VCLK on pin 29 (A24)

1Normal operation: ROMCS#

generated in ISA bus mode

D7 D6 D5 D4 D3 D2 D1 D0

CFG0 / LB#: Bus Type

CFG1 / ISA#: Bus Type

CFG2 / 2X#: Bus Type

CFG3: Reserved

CFG4

: Reserved (do not use)

CFG5 / OS#:

Osc Src Select

CFG6 / AD#: A26-27 Ena

CFG7 / TS#: Clk Test Ena

Extension Registers

Revision 1.2 99 65540 / 545

CPU INTERFACE CTRL REGISTER 1 (XR02)

Read/Write at I/O Address 3D7h

Index 02h

08/16-bit CPU Memory Access

08-bit CPU memory access (default)

116-bit CPU memory access

1Digital Monitor Clock Mode

0Normal (clk 0-1=25,28 MHz)

(default)

1Digital Monitor (clk 0-1=14,16MHz)

14MHz = 56MHz ÷ 4 or 28MHz ÷ 2

16MHz = 50MHz ÷ 3

2Simultaneous Display CRT H Timing Select

0Use XR19,1A,1B for H parameters

1 Use CR04,05,00 for H parameters

4-3 Attribute Controller Mapping

00 Write Index and Data at 3C0h. (8-bit

access only) (default - VGA mapping)

01 Write Index at 3C0h and Data at 3C1h

(8-bit or 16-bit access). Attribute flip-

flop (bit-7) is always reset in this

mode (16-bit mapping)

10 Write Index and Data at 3C0h/3C1h

(8-bit access only) (EGA mapping)

11 Reserved

5I/O Address Decoding

0Decode all 16 bits of I/O address

(default)

1Decode only lower 10 bits of I/O

address. This affects addresses 3B4-

3B5h, 3B8h, 3BAh, 3BFh, 3C0-

3C2h, 3C4-3C5h, 3CE-3CFh, 3D4-

3D5h, and 3D8-3DAh.

6Palette Address Decoding

0External palette registers can be

accessed only at 3C6h-3C9h (default)

1External palette regs can be accessed at

3C6h-3C9h & 83C6h-83C9h

7Attribute Flip-Flop Status (read only)

0 = Index, 1 = Data

D7 D6 D5 D4 D3 D2 D1 D0

Enable 16-bit Mem Access

Digital Monitor Mode

Sim Disp CRT H Timing

Attribute Controller

Mapping

10-bit I/O Address Decode

83C6-83C9 Palette Decode

Attribute FF Status (R/O)

Extension Registers

Revision 1.2 100 65540 / 545

CPU INTERFACE CTRL REGISTER 2 (XR03)

Read/Write at I/O Address 3D7h

Index 03h

0Palette Write Shadow

0Chip responds normally to Palette

Write accesses (LDEV# is returned for

VL-Bus and DEVSEL# is returned for

PCI bus)

1Palette write commands are executed

internally but the chip does not

respond externally (LDEV# is not

returned for VL-Bus and DEVSEL# is

not returned for PCI bus). This

conforms to both VL-Bus and PCI

bus "Palette Shadowing" requirements

as it forces the access to be passed on

to the ISA bus where add-in cards

may be shadowing the VGA color

palette data. This bit should normally

be set to 1.

1DR Register Access Enable

032-Bit DRxx register access Disabled

(Default)

1DRxx registers accessible at I/O port

defined by XR07.

3-2 Reserved (0)

4ISA Bus Palette Access RDY Response

0Hold off the CPU using RDY for

palette accesses (read or write to 3C6-

3C9h).

1Do not hold off the CPU using RDY

for palette accesses (read or write to

3C6-3C9h)

The internal RAMDAC has a minimum

specification for time between accesses. A

faster CPU is more likely to violate this

specification, so it is normally required to

add delay between accesses in software.

D7 D6 D5 D4 D3 D2 D1 D0

Palette Write Shadow

DR Access Ena (545 only)

Reserved (0)

Palette RDY Response

Diagnostic (Set to 0)

Reserved (0)

This bit may be set to 0 to effectively create a

CPU-transparent delay, however this is not

compatible with some systems: some

systems ignore RDY for palette accesses, so

for those systems, this bit must be set to 1.

5Diagnostic ( R/W but should be set to 0 )

7-6 Reserved (0)

Extension Registers

Revision 1.2 101 65540 / 545

MEMORY CONTROL REGISTER 1 (XR04)

Read/Write at I/O Address 3D7h

Index 04h

D7 D6 D5 D4 D3 D2 D1 D0

Memory Configuration

Memory Wraparound Ctrl

Reserved (0)

Write Buffer Enable

Reserved (0)

1-0 Memory Configuration

00 32-bit memory data path. Memory

data bus is on MAD15-0 & MBD15-0

(DRAMs A and B). If frame acceler-

ation is enabled and embedded frame

buffer is selected, the data will be

stored in both DRAMs A and B. An

external frame buffer can be enabled

on DRAM C with this setting.

01 16-bit data path (DRAM A only).

The memory data bus is on MAD15-0.

If frame acceleration is enabled and

embedded frame buffer is selected, the

data will be restricted to storage in

DRAM A only. An external frame

buffer can be enabled on DRAM C

with this setting.

10 32-bit memory data path. Memory

data bus is on MAD15-0 & MCD15-0

(DRAMs A & C). DRAM C cannot

be used as an external frame buffer

with this setting, but programming can

select between this setting and '01' to

switch the function of DRAM C

between use as display memory and

use as an external frame buffer.

11 Reserved

DRAM A must always be present and if that

is the only DRAM present, setting 01 must

be used. DRAM B may optionally be

present and if it is, setting 00 may be used

(either 00 or 01 may be programmed with

DRAMs A & B physically present). If all

three DRAMs are present, setting 00 would

normally be used (00, 01, and 10 are all

allowable). Setting 10 would be used where

only two DRAMs (A and C) are physically

present (this field is set to 10 to use both

DRAMs as 1MB of display memory and set

to 01 to use DRAM A as 512KB of display

memory and DRAM C as an external frame

buffer).

2Memory Wraparound Control

This bit enables bits 16-17 of the CRT

Controller address counter (default = 0 on

reset).

0Disable CRTC addr counter bits 16-17

1Enable CRTC addr counter bits 16-17

4-3 Reserved (0)

5CPU Memory Write Buffer

0Disable CPU memory write buffer

(default)

1Enable CPU memory write buffer

7-6 Reserved (0)

Extension Registers

0Disable Long CPU Cycles

0Enable long CPU cycles (default on

RESET). This puts as many CPU

cycles as possible into one RAS cycle.

1Disable long CPU cycles.

1CPU-Mem Access CAS# Cycle Ctrl (545)

2Display Mem Access CAS# Cycle Ctrl (545)

Bit-1 affects accesses to display memory

initiated by the 65545 for display refresh.

Bit-2 affects CPU accesses to display

memory in the 65545. Both bits are defined

as follows:

0 3-MCLK CAS# cycle (2 low, 1 high)

for all read or write accesses (default)

14-MCLK CAS# cycle (3 low, 1 high)

for all read accesses and for the first

CAS# cycle of page-mode write

accesses (following cycles are 2L/1H)

These bits may be set to create looser

memory timing (e.g., for 3.3V operation, to

allow use of cheaper DRAMs, etc.). 4-

MCLK CAS cycles are not supported in the

65540.

3Asymmetric Address for DRAMs A & B

0Symmetric 256Kx16 DRAM is used

(9-bit RAS/CAS addresses) (default)

1Asymmetric 256Kx16 DRAM is used

(10-bit RAS/8-bit CAS address)

Asymmetric address DRAMs should not be

used (and this bit should not be set to one) if

AA9 is used as a 32KHz clock input (see

XR33 bit-6) or if 24-bit PC-Video interface

is enabled (see bit-7 of this register). See

also XR6F bit-2 (address symmetry control

for DRAM C).

4CAS# / WE# Select for DRAMs A & B

02-CAS# / 1-WE# 256Kx16 DRAM

configuration is used (default)

11 CAS# and 2 WE# 256Kx16 DRAM

configuration is used

5 CAS# / WE# Select for DRAM C

This bit is effective when XR6F[7]=1.

02 CAS# and 1 WE# configuration

256Kx16 DRAM is used (default)

11 CAS# and 2 WE# configuration

256Kx16 DRAM is used

6PC Video Interface Enable

0Disable PC Video Interface (default)

1Enable PC Video interface on DRAM

'C' pins (MCD15-0, RASC#,

CASCH#, CASCL#, and WEC#). If

bit-7 of this register is set to 1, OEC#,

AA9, ACTI, ENABKL, and CA8-9

also serve as PC Video Interface pins.

An external frame buffer cannot be

used in this configuration.

7PC Video Interface Control

018-bit PC Video interface

1 24-bit PC Video interface

Note: When this bit is set to 1, AA9,

ENABKL, ACTI pins are used for video

inputs therefore they lose their alternate

functions. When this bit is set to 1, a 24-bit

panel interface is also available (CA0-7

become P16-23). This bit should not be set

to 1 if the AD# (A26-27 enable) or EC#

(external clock) configuration bits are

asserted low at reset (since this enables

ACTI and ENABKL to perform alternate

functions).

MEMORY CONTROL REGISTER 2 (XR05)

Read/Write at I/O Address 3D7h

Index 05h

D7 D6 D5 D4 D3 D2 D1 D0

Disable Long CPU Cycles

CPU Access CAS# Ctrl

Display Access CAS# Ctrl

DRAM CAS# Address

Memory CAS/WE Select

Frame Buffr CAS/WE Slct

PC Video Interface Enable

PC Video Interface Width

Revision 1.2 102 65540 / 545

Extension Registers

0Pixel Data Pin Diagnostic Output Mode

0Normal operation. Pixel data (P15:0)

pins output flat panel pixel data

(default on Reset).

1Output CRT pixel data on pixel data

pins P0-7 and output various internal

signals on pixel data pins P8-15 for

diagnostic purposes.

1Internal DAC Disable

This bit affects the DAC analog outputs.

0Enable internal DAC (default on

Reset). DAC analog outputs (R, G,

B) will be active and HSYNC and

VSYNC signals are driven (Default on

reset).

1Disable internal DAC. The DAC

analog outputs (R, G, B) will be 3-

stated. Setting this bit forces power

down of the internal DAC. HSYNC

and VSYNC are forced inactive if

XR5D[6] is 0 and will be driven if

XR5D[6] is 1.

3-2 Display Mode Color Depth

00 4 or 8 bits-per-pixel (default on reset)

01 16 bpp (5-5-5) (Targa compatible)

10 24 bpp (true color)

11 16 bpp (5-6-5) (XGA compatible)

4PC Video Color Key Enable

0Disable PC Video Overlay (default on

reset)

1Enable PC Video Overlay on color key

5 Bypass Internal VGA Palette

0Use internal VGA palette (Default on

reset).

1Bypass internal VGA palette which

will be powered down if DAC is

disabled.

7-6 Color Reduction Select

These bits are effective in flat panel mode.

These bits select the algorithm used to

reduce 24-bit or 18-bit color data to 8-bit or

6-bit color data for monochrome panels.

00 NTSC weighting algorithm (default on

reset)

01 Equivalent weighting algorithm

10 Green only

11 Color (no reduction). This setting

should be used when driving color

panels.

PALETTE CONTROL REGISTER (XR06)

Read/Write at I/O Address 3D7h

Index 06h

D7 D6 D5 D4 D3 D2 D1 D0

Pixel Out Diagnostic Mode

Internal DAC Disable

Display Mode Color Depth

PC Video Color Key Enble

Bypass Internal Palette

FP Color Reduction Select

Revision 1.2 103 65540 / 545

Extension Registers

LINEAR ADDRESSING BASE REGISTER (XR08)

Read/Write at I/O Address 3B7h/3D7h

Index 08h

Revision 1.2 104 65540 / 545

D7 D6 D5 D4 D3 D2 D1 D0

7-0 Linear Address Base

In VL-Bus configuration, if linear

addressing is enabled (XR0B[4]=1), these 8

bits are compared to A[27:20] to determine

the base address of the 1MB of display

memory in the 256MB VL-Bus address

space (normally the VL address space is

4GB, but only 28 bits of address are de-

coded by the chip). For example, if the

video memory is to be placed at 12MB

(0C00000-0CFFFFFh), this register should

be programmed to '00001100b'. Note that

as a result, programming this register to 0 is

typically not useful.

If A26-27 are not available (used for ACTI

and ENABKL if Configuration Register

XR01 bit-6 = 1) then bits 6-7 of this register

are ignored and only A20-25 are compared

against bits 0-5 of this register to determine

the base address for the linear frame buffer

in the VL-Bus / 486 CPU memory space.

Similarly, if A25 and/or A24 are not

available (see configuration bits 3, 4, and 7),

bits 5 and/or 4 are also ignored. In ISA bus

configuration, address inputs A24-27 are

never available, so bits 4-7 of this register

are ignored and A20-23 are compared

against bits 0-3 of this register to determine

the base address for the linear frame buffer

in the 16MB ISA memory space.

In PCI bus configuration, this register is

ignored. The PCI Configuration MBASE

for the linear frame buffer in the 4GB (full

32-bit address) PCI memory address space.

Linear Address Base

I/O BASE REGISTER (XR07)

Read/Write at I/O Address 3D7h

Index 07h

D7 D6 D5 D4 D3 D2 D1 D0

I/O Base for 32-Bit Regs

(65545 only)

7–0 I/O Base for 32-Bit Registers (65545 only)

In ISA and VL-Bus configuration, these bits

determine the I/O range for the Doubleword

Hardware Cursor & BitBLT registers

(DRxx). The value programmed here is

matched against CPU addresses A15 & A8-

2. Address A9 must equal 1 and A14-10

select one of 32 DR registers. For example,

a programmed value of 074h (011101 00b)

would result in this DR register mapping:

DRxx: nxxx xx1n nnnn nn00b

DR00: 03D0h = 0000 0011 1101 0000b

DR01: 07D0h = 0000 0111 1101 0000b

DR02: 0BD0h = 0000 1011 1101 0000b

DR03: 0FD0h = 0000 1111 1101 0000b

DR04: 13D0h = 0001 0011 1101 0000b

DR05: 17D0h = 0001 0111 1101 0000b

DR06: 1BD0h = 0001 1011 1101 0000b

DR07: 1FD0h = 0001 1111 1101 0000b

DR08: 23D0h = 0010 0011 1101 0000b

DR09: 27D0h = 0010 0111 1101 0000b

DR0A: 2BD0h = 0010 1011 1101 0000b

DR0B: 2FD0h = 0010 1111 1101 0000b

DR0C: 33D0h = 0011 0011 1101 0000b

The DRxx registers are enabled for access

by setting XR03[1]. They are disabled

following Reset. The programmer should

write this register before enabling access to

the DRxx registers.

In PCI bus configuration, this register is

ignored. The PCI Configuration IOBASE

for the 32-bit registers in the PCI I/O space.

Note that for PCI bus configuration only,

the 32-bit registers may also be memory

mapped: MBASE defines a 2MB memory

space with frame buffer memory mapped

into the lower megabyte and the 32-bit

registers mapped into the upper megabyte.

Extension Registers

Revision 1.2 105 65540 / 545

CPU PAGING REGISTER (XR0B)

Read/Write at I/O Address 3D7h

Index 0Bh

D7 D6 D5 D4 D3 D2 D1 D0

Memory Mapping Mode

Single/Dual Map

CPU Address Divide by 4

Extended Text Mode (545)

Linear Addressing Enable

Reserved (0)

0Memory Mapping Mode

0Normal Mode (VGA compatible)

(default on Reset)

1Extended Mode (mapping for > 256

KByte memory configurations)

1CPU Single/Dual Mapping

0CPU uses only a single map to access

the extended video memory space

(default on Reset)

1CPU uses two maps to access the

extended video memory space. The

base addresses for the two maps are

defined in the Low Map Register

(XR10) and High Map Register

(XR11).

2CPU Address Divide by 4

0Disable divide by 4 for CPU

addresses (default on Reset)

1Enable divide by 4 for CPU

addresses. This allows the video

memory to be accessed sequentially in

mode 13. In addition, all video

memory is available in mode 13 by

setting this bit.

3Extended Text Mode ( 65545 only )

Set to enable text font 'scrambling' in plane

2. Setting this bit improves text mode

performance in single-DRAM configurations

(with the proper BIOS support for font

load/reload functions). This bit should be

set in single DRAM configurations only.

This bit is supported in the 65545 only; it

should be programmed to 0 in the 65540.

START ADDRESS TOP REGISTER (XR0C)

Read/Write at I/O Address 3D7h

Index 0Ch

1-0 Start Address Top

These bits defines the high order bits for the

Display Start Address when 512 KBytes or

more of memory is used (see XR04 bits

1–0).

7-2 Reserved (0)

D7 D6 D5 D4 D3 D2 D1 D0

Start Address Top

Reserved (0)

4Linear Addressing Enable

0Standard VGA (A0000 - BFFFF)

memory space decoded on-chip using

A17-19 (default on Reset)

1Linear Addressing Enabled. See

XR08 (Linear Addressing Base) for

base address selection. Ignored in

PCI bus configuration (see DEVCTL).

7-5 Reserved (0)

Extension Registers

Revision 1.2 106 65540 / 545

0Offset Register LSB

This bit provides finer granularity to the

display memory address offset when word

and doubleword modes are used. This bit is

used with the regular Offset register (CR13).

1Alternate Offset Register LSB

This bit provides finer granularity to the

display memory address offset when word

and doubleword modes are used. This bit is

used with the Alternate Offset register

(XR1E).

7-2 Reserved (0)

AUXILIARY OFFSET REGISTER (XR0D)

Read/Write at I/O Address 3D7h

Index 0Dh

D7 D6 D5 D4 D3 D2 D1 D0

LSB of Offset (CR13)

LSB of Alt Offset (XR1E)

Reserved (0)

TEXT MODE CONTROL REGISTER (XR0E)

Read/Write at I/O Address 3D7h

Index 0Eh

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (0)

Cursor Blink Disable

Cursor Style

Alt Cursor Start (65545)

Sync Reset Ignore

This register is effective for both CRT and flat panel

text modes.

1-0 Reserved (0)

2Cursor Mode

0Blinking (default on Reset).

1Non-blinking

3Cursor Style

0Replace (default on Reset)

1Exclusive-Or

6-4 Alternate Cursor Start (65545 Only)

When the alternate CRTC registers are

active, this field may be set to specify the

Cursor Start Scan Line instead of CR0A bits

0-4 (this field specifies alternate bits 0-2

with bits 3-4 assumed to be 0).

VGA software typically changes the shape

of the cursor frequently between underline

and block styles. This field allows the

cursor style to be fixed (typically to 'block'

for improved readability on panels).

7Synchronous Reset Ignore

When this bit is set, the chip will ignore

SR00 bit-1 (Synchronous Reset) and will

remain in normal operation. Synchronous

reset is a holdover from the original VGA

which is no longer required. VGA

software, however, performs synchronous

resets frequently, creating the possibility for

display memory corruption if the chip is left

in the synchronous reset state for too long.

The 65540 / 545 display memory sequencer

does not need to be periodically reset, so this

bit is provided to prevent potential display

memory corruption problems. For absolute

VGA compatibility, this bit may be set to 0.

Extension Registers

Revision 1.2 107 65540 / 545

SOFTWARE FLAGS REGISTER 0 (XR0F)

Read/Write at I/O Address 3D7h

Index 0Fh

This register contains eight read-write bits which

have no internal hardware function. All bits are

reserved for use by BIOS and driver software. For

reference, the functions of the bits of this register are

currently defined as follows:

1-0 Memory Size

00 256KB

01 512KB

1x 1MB

2-3 Reserved (0)

4Hi Color / True Color

0Current mode is not hi-/true-color

mode

1Current mode is hi-color / true-color

mode

5Packed-Pixel Mode Dot Clock

0Use default dot clock in packed-pixel

modes

1Use 40MHz dot clock in packed-pixel

modes

This bit is used for high resolution panels in

panel mode only.

6Interlace Select

0Set mode 24h, 34h, 72h/75h or 7Eh

interlaced

1Set mode 24h, 34h, 72h/75h or 7Eh

non-interlaced

7Text Compensation Enable / Disable

0Tall font disabled

1 Tall font enabled

See also XR2B, XR44, XR45 for definition of other

software flags registers.

D7 D6 D5 D4 D3 D2 D1 D0

Memory Size

Reserved (0)

Hi / True Color Select

Packed Pixel Dot Clock

Interlace Select

Text Compensation Enable

Extension Registers

Revision 1.2 108 65540 / 545

This register effects CPU memory address mapping.

7-0 High Map Base Address Bits 17-10

These bits define the Higher Map base

address in dual map modes (XR0B bit-1=1).

The memory map starts on a 1K boundary in

planar modes and on a 4K boundary in

packed pixel modes. This register controls

the CPU window into display memory

based on the contents of GR06 bits 3-2 as

follows:

GR06 bits 3-2 High Map

00 B0000-BFFFF

01 A8000-AFFFF

10 Don't care

11 Don't care

HIGH MAP REGISTER (XR11)

Read/Write at I/O Address 3D7h

Index 11h

SINGLE/LOW MAP REGISTER (XR10)

Read/Write at I/O Address 3D7h

Index 10h

D7 D6 D5 D4 D3 D2 D1 D0

Single or Lower Map

Base Address Bits 17-10

This register effects CPU memory address mapping.

7-0 Single / Low Map Base Address Bits 17-10

These bits define the base address in single

map mode (XR0B bit-1 = 0), or the lower

map base address in dual map mode (XR0B

bit-1 = 1). The memory map starts on a 1K

boundary in planar modes and on a 4K

boundary in packed pixel modes. In case of

dual mapping, this register controls the CPU

window into display memory based on the

contents of GR06 bits 3-2 as follows:

GR06

Bits 3-2 Low Map

00 A0000-AFFFF

01 A0000-A7FFF

10 B0000-B7FFF Single mapping only

11 B8000-BFFFF Single mapping only

D7 D6 D5 D4 D3 D2 D1 D0

Higher Map

Base Address Bits 17-10

Extension Registers

Revision 1.2 109 65540 / 545

6VSync Status Mode

0Prevent VSync status from appearing

at bit 7 of Input Status Register 1 (I/O

Address 3BAh/3DAh). Normally

used for CGA, EGA, and VGA

modes.

1Enable VSync status to appear as bit-7

of Input Status Register 1 (I/O

Address 3BAh/3DAh). Normally

used for MDA/Hercules mode.

7Interrupt Output Function

This bit controls the function of the interrupt

output pin (IRQ):

Interrupt State Bit-7=0 Bit-7=1

Disabled 3-state 3-state

Enabled, Inactive 3-state Low

Enabled, Active 3-state High

1-0 Emulation Mode

00 VGA mode (default on Reset)

01 CGA mode

10 MDA/Hercules mode

11 EGA mode

3-2 Hercules Configuration Register (3BFh)

readback (read only)

4Display Enable Status Mode

0Select Display Enable status to appear

at bit 0 of Input Status register 1 (I/O

Address 3BAh/3DAh) (default on

reset). Normally used for CGA,

EGA, and VGA modes.

1 Select HSync status to appear at bit 0

of Input Status register 1 (I/O Address

3BAh/3DAh). Normally used for

MDA / Hercules mode.

5Vertical Retrace Status Mode

0Select Vertical Retrace status to appear

at bit 3 of Input Status register 1 (I/O

Address 3BAh/3DAh) (default on

Reset). Normally used for CGA,

EGA, and VGA modes.

1 Select Video to appear at bit 3 of Input

Status register 1 (I/O Address

3BAh/3DAh). Normally used for

MDA / Hercules mode.

D7 D6 D5 D4 D3 D2 D1 D0

Emulation Mode

Herc Config (read only)

DE Status Mode

V Retrace Status Mode

VSync Status Mode

Interrupt Polarity

EMULATION MODE REGISTER (XR14)

Read/Write at I/O Address 3D7h

Index 14h

Extension Registers

Revision 1.2 110 65540 / 545

6Write Protect Group 0 Registers

This bit affects CR0-7 (except CR07 bit-4).

This bit is logically ORed with CR11 bit-7.

7Write Protect AR11

This bit is ORed with bit-0, therefore writing

to AR11 is possible only if both bit-0 and

bit-7 are 0. This feature is used for write

protection of the overscan color. This is

important in order to keep application

software from changing the border color

while still permitting the attribute controller

to be changed for the addressable portion of

the display. Overscan is increasingly

becoming an ergonomics requirement and

this bit will ensure software compatibility.

This register controls write protection for various

groups of registers as shown. 0 = unprotected

(default on Reset), 1= protected.

0Write Protect Group 1 Registers

This bit affects the Sequencer registers

(SR00-04), Graphics Controller registers

(GR00-08), and Attribute Controller

registers (AR00-14).

Note that AR11 is also protected by bit-7

which is ORed with this bit.

1Write Protect Group 2 Registers

This bit affects CR09 bits 0-4, CR0A, and

CR0B.

2Write Protect Group 3 Registers

This bit affects CR07 bit-4, CR08, CR11

bits 5-4, CR13, CR14, CR17 bits 0-1 and

bits 3-7, and CR18.

3Write Protect Group 4 Registers

This bit affects CR09 bits 5-7, CR10, CR11

bits 0-3 and bits 6-7, CR12, CR15, CR16,

and CR17 bit-2.

4Write Protect Group 5 Registers

This bit affects the Miscellaneous Output

5Write Protect Group 6 Registers

This bit affects the VGA color palette

registers (3C6h-3C9h). If this bit is set, all

VGA color palette registers are write

protected.

WRITE PROTECT REGISTER (XR15)

Read/Write at I/O Address 3D7h

Index 15h

D7 D6 D5 D4 D3 D2 D1 D0

Wr Protect Group 1 Regs

Wr Protect Group 2 Regs

Wr Protect Group 3 Regs

Wr Protect Group 4 Regs

Wr Protect Group 5 Regs

Wr Protect Group 6 Regs

Wr Protect Group 0 Regs

Wr Protect AR11

Extension Registers

Revision 1.2 111 65540 / 545

VERTICAL OVERFLOW REGISTER (XR16)

Read/Write at I/O Address 3D7h

Index 16h

This register is used for both normal and alternate

vertical parameters.

0Vertical Total Bit-10

1Vertical Display End Bit-10

2Vertical Sync Start Bit-10

3Reserved (R/W)

4Vertical Blank Start Bit-10

5Reserved (R/W)

6Line Compare Bit-10

7Reserved (R/W)

HORIZONTAL OVERFLOW REGISTER (XR17)

Read/Write at I/O Address 3D7h

Index 17h

This register is used for both normal and alternate

horizontal parameters.

0Horizontal Total Bit-8

1Horizontal Display End Bit-8

2Horizontal Sync Start Bit-8

3Horizontal Sync End Bit-5

4Horizontal Blank Start Bit-8

5Horizontal Blank End Bit-6

6Line Compare Bit-10

7Reserved (R/W)

D7 D6 D5 D4 D3 D2 D1 D0

Horizontal Total Bit 8

Horizontal Disp End Bit 8

Horizontal Sync Start Bit 8

Horizontal Sync End Bit 5

Horizontal Blank Strt Bit 8

Horizontal Blank End Bit 6

Line Compare Bit 10

Reserved (R/W)

D7 D6 D5 D4 D3 D2 D1 D0

Vertical Total Bit 10

Vertical Display End Bit 10

Vertical Sync Start Bit 10

Reserved (R/W)

Vertical Blank Start Bit 10

Reserved (R/W)

Line Compare Bit 10

Reserved (R/W)

Extension Registers

Revision 1.2 112 65540 / 545

ALTERNATE HORIZONTAL

DISPLAY END REGISTER (XR18)

Read/Write at I/O Address 3D7h

Index 18h

This register is used in flat panel and CRT CGA text

and graphics modes, and Hercules graphics mode.

7-0 Alternate Horizontal Display End

This register specifies the number of

characters displayed per scan line, similar to

CR01.

Programmed Value = Actual Value – 1

Note: This register is used in emulation modes only.

It is not used in CRT or flat panel VGA

modes.

D7 D6 D5 D4 D3 D2 D1 D0

Alternate H Display End

ALTERNATE HORIZONTAL SYNC START

Read/Write at I/O Address 3D7h

Index 19h

This register is used in all flat panel modes with

horizontal compression disabled, to set the horizontal

sync start. This register is also used in CRT CGA

text and graphics modes, and Hercules graphics

mode.

7-0 Alternate Horizontal Sync Start

These bits specify the beginning of the

HSync in terms of character clocks from the

beginning of the display scan. Similar to

CR04.

Programmed Value = Actual Value – 1

D7 D6 D5 D4 D3 D2 D1 D0

FP HSync Start

Extension Registers

Revision 1.2 113 65540 / 545

This register is used in all flat panel modes with

horizontal compression disabled, CRT CGA text and

graphics modes, and Hercules graphics mode.

4-0 Alternate Horizontal Sync End

Lower 5 bits of the character clock count

which specifies the end of horizontal sync.

Similar to CR05. If the horizontal sync

width desired is N clocks, then programmed

value is:

(N + Contents of XR19) ANDed with 01F Hex

6-5 CRT Alternate Horizontal Sync Delay

See CR05 for description

7Reserved (0)

ALTERNATE HORIZONTAL SYNC END

Read/Write at I/O Address 3D7h

Index 1Ah

D7 D6 D5 D4 D3 D2 D1 D0

FP H Sync End

Alternate H Sync Delay

Reserved (0)

ALTERNATE HORIZONTAL TOTAL REGISTER

(XR1B)

Read/Write at I/O Address 3D7h

Index 1Bh

D7 D6 D5 D4 D3 D2 D1 D0

FP H Total

This register is used in all flat panel modes with

horizontal compression disabled, CRT CGA text and

graphics modes, and Hercules graphics mode.

7-0 Alternate Horizontal Total

This register contents are the total number of

character clocks per line. Similar to CR00.

Programmed Value = Actual Value – 5

Extension Registers

Revision 1.2 114 65540 / 545

ALTERNATE HORIZONTAL BLANK START /

HORIZONTAL PANEL SIZE REGISTER (XR1C)

Read/Write at I/O Address 3D7h

Index 1Ch

The value in this register is the Horizontal Panel Size

in all Flat Panel Modes. In CRT mode, it is used for

CGA text and graphics and Hercules graphics

modes.

7-0 FP Horizontal Panel Size

Horizontal panel size is programmed in

terms of number of 8-bit (graphics/text) or

9-bit (text) characters. For double drive flat

panels the actual horizontal panel size must

be a multiple of two character clocks.

Programmed Value = Actual Value – 1

7-0 CRT Alternate Horizontal Blank Start

See CR02 for description

Programmed Value = Actual Value – 1

D7 D6 D5 D4 D3 D2 D1 D0

H Blank Start

(Horizontal Panel Size)

D7 D6 D5 D4 D3 D2 D1 D0

ALTERNATE HORIZONTAL BLANK END

Read/Write at I/O Address 3D7h

Index 1Dh

H Blank End

DE Skew Control

Split Screen Enhance

Bits 0-6 of this register are used in CRT CGA text

and graphics modes and CRT Hercules graphics

mode. Bit 7 of this register is used for all CRT and

flat panel modes.

4-0 CRT Alternate Horizontal Blank Start

See CR03 for description

6-5 CRT Alternate Display Enable Skew Control

See CR03 for description

7Line Compare Fix

This bit affects all CRT and FP text modes.

This bit is 0 on reset.

0Internal Line Compare (split screen)

flag is not delayed so that the Vertical

Row Counter is reset too early which

in text mode causes the first scanline

of the first character row following

split screen to be skipped (not dis-

played). This is IBM VGA com-

patible.

1Internal Line Compare (split screen)

flag is delayed so that the Vertical

Row Counter is reset properly which

in text mode causes the first scanline

of the first character row following

split screen to be displayed.

Note: This register is used in emulation modes only.

It is not used in CRT or flat panel VGA

modes.

Extension Registers

Revision 1.2 115 65540 / 545

ALTERNATE OFFSET REGISTER (XR1E)

Read/Write at I/O Address 3D7h

Index 1Eh

This register is used in all flat panel modes, CRT

CGA text and graphics modes and Hercules graphics

mode.

7-0 Alternate Offset

See CR13 for description

Programmed Value = Actual Value – 1

D7 D6 D5 D4 D3 D2 D1 D0

Alternate

Display Buffer

Width

VIRTUAL EGA SWITCH REGISTER (XR1F)

Read/Write at I/O Address 3D7h

Index 1Fh

3-0 Virtual Switch Register

If bit-7 is '1', then one of these four bits is

read back in Input Status Register 0 (3C2h)

bit 4. The selected bit is determined by

Miscellaneous Output Register (3C2h) bits

3-2 as follows:

Misc 3-2 XR1F Bit Selected

00 bit-3

01 bit-2

10 bit-1

11 bit-0

6-4 Reserved (0)

7Sense Select

0Select the output of the internal RGB

comparator (Sense) for readback in

Input Status Register 0 bit-4 (default

on Reset).

1Select one of bits 3-0 for readback in

Input Status Register 0 bit-4.

D7 D6 D5 D4 D3 D2 D1 D0

Virtual EGA Switches

Reserved (0)

Sense Select

Extension Registers

Revision 1.2 116 65540 / 545

ALTERNATE MAXIMUM

SCANLINE REGISTER (XR24)

Read/Write at I/O Address 3D7h

Index 24h

This register is used in flat panel text mode when

TallFont is enabled during vertical compensation.

4-0 Alternate Maximum Scanlines (AMS)

Programmed Value = number of scanlines

minus one per character row of TallFont

Double scanned lines, inserted lines, and

replicated lines are not counted.

7-5 Reserved (R/W)

D7 D6 D5 D4 D3 D2 D1 D0

Alternate Max Scanlines

Reserved (R/W)

ALTERNATE HORIZONTAL SYNC START

OFFSET REGISTER (XR26)

Read/Write at I/O Address 3D7h

Index 26h

This register is used in flat panel mode.

7-0 Horizontal Sync Start Offset

This value is added to CR04 ( Horizontal

Sync Start) when XR02 bit 2 is set to '1'.

D7 D6 D5 D4 D3 D2 D1 D0

Alt H Sync Start Offset

ALTERNATE TEXT MODE / HORIZONTAL

VIRTUAL PANEL SIZE REGISTER (XR25)

Read/Write at I/O Address 3D7h

Index 25h

D7 D6 D5 D4 D3 D2 D1 D0

AltText Mode

H Virtual Panel Size

This register is used in flat panel 9-dot text modes.

7-0 Alternate Text Mode

Horizontal Virtual Panel Size

Programmed Value = 9/8 [XR1C + 1] – 1

Extension Registers

Revision 1.2 117 65540 / 545

VIDEO INTERFACE REGISTER (XR28)

Read/Write at I/O Address 3D7h

Index 28h

68-Bit Video Pixel Panning

This bit is effective for both CRT and flat

panel when the 8-bit video data path is

selected (bit-4 = 1).

0AR13 bits 2-1 are used to control pixel

panning (default on Reset)

1AR13 bits 2-0 are used to control pixel

panning

7Tall Font Replication

0Tall font replicates lines 1, 9 and 12

1Tall font replicates line 0 twice and

line 15 once

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (0)

Blank#/DE Select

Reserved (0)

256-Color Video Path

Interlace Mode

8-Bit Video Pixel Panning

Tall Font Replication

0Reserved (0)

1Blank / Display Enable Select

This bit is effective in CRT mode only. In

flat panel mode, XR54 bit-1 controls

BLANK# functionality.

0BLANK# controls color palette

blanking (default on reset)

1Display Enable controls color palette

blanking

Note: This bit also controls the functionality

of pins 68 or 69 when BLANK# / DE is

selected for output instead of the default

function (M is normally output on pin 69

and LP is normally output on pin 68 but this

can be changed by XR4F bits 6 and 7

respectively). See also XR54 bits 0 and 1.

3-2 Reserved (0)

4256-Color Video Path

This bit is effective for both CRT and flat

panel in 256-color modes other than mode

13 (i.e., Super VGA modes).

04-bit video data path (default on reset)

18-bit video data path (horizontal pixel

panning is controlled by bit-6)

Note: GR05 bit-5 must be 0 if this bit is set

5Interlace Video

This bit is effective only for CRT graphics

mode. This bit should be programmed to 0

for flat panel. In interlace mode XR29 holds

the half-line positioning of VSync for odd

frames.

0Non-interlaced video (default on reset)

1Interlaced video

HALF LINE COMPARE REGISTER (XR29)

Read/Write at I/O Address 3D7h

Index 29h

In Interlaced mode CRT operation, this register is

used to generate the Half Line Compare Signal.

7-0 CRT Half-Line Value

In CRT interlaced video mode this value is

used to generate the 'half-line compare'

signal that controls the positioning of the

VSync for odd frames.

D7 D6 D5 D4 D3 D2 D1 D0

Half-Line Compare

SOFTWARE FLAGS REGISTER 1 (XR2B)

Read/Write at I/O Address 3D7h

Index 2Bh

This register contains eight read-write bits which

have no internal hardware function. All bits are

reserved for use by BIOS and driver software. For

reference, the functions of the bits of this register are

currently defined as follows:

7-0 Display Mode

These bits are used by the BIOS to store the

current display mode number.

See also XR0F, XR44, XR45 for definition of other

software flags registers.

D7 D6 D5 D4 D3 D2 D1 D0

Revision 1.2 118 65540 / 545

FLM DELAY REGISTER (XR2C)

Read/Write at I/O Address 3D7h

Index 2Ch

This register is used only in flat panel mode when

XR2F bit-7=0. The First Line Marker (FLM) signal

is generated from an internal FP VSync active edge

with a delay specified by this register. The FLM

pulse width is always one line for SS panels and two

lines for DD panels.

7-0 FLM Delay (VDelay)

These bits define the number of HSyncs

between the internal VSync and the rising

edge of FLM.

D7 D6 D5 D4 D3 D2 D1 D0

FLM Delay

Flag 0

Flag 1

Flag 2

Flag 3

Flag 4

Flag 5

Flag 6

Flag 7

Extension Registers

Revision 1.2 119 65540 / 545

This register is used only in flat panel mode when

XR2F bit-6 = 0 and graphics mode horizontal

compression is enabled. The LP output is generated

from the FP Blank inactive edge with a delay

specified by XR2F bit-5 and the value in this

XR2F.

7-0 LP Delay

These bits define the number of character

clocks between the FP Blank inactive edge

and the rising edge of the LP output in flat

panel mode with 9-dot text mode forced to

8-dot text. The msb (bit 8) of this parameter

is XR2F bit-5.

Programmed Value = Actual Value – 1

Note: For DD panels without frame acceleration,

the programmed value should be doubled.

LP DELAY REGISTER (CMPR ENABLED) (XR2D)

Read/Write at I/O Address 3D7h

Index 2Dh

D7 D6 D5 D4 D3 D2 D1 D0

LP Delay

(graphics mode horizontal

compression enabled)

This register is used only in flat panel mode when

XR2F bit-6 = 0 and 9-dot text mode is used. The

LP output is generated from the FP Blank inactive

edge with a delay specified by XR2F bit-4 and the

value in this register. The LP pulse width is

specified in register XR2F.

7-0 LP Delay

These bits define the number of character

clocks between the FP Blank inactive edge

and the rising edge of the LP output in flat

panel 9-dot text modes. The msb (bit 8) of

this parameter is XR2F bit-4.

Programmed Value = Actual Value – 1

Note: For DD panels without frame acceleration,

the programmed value should be doubled.

LP DELAYREGISTER (CMPR DISABLED) (XR2E)

Read/Write at I/O Address 3D7hIndex 2Eh

D7 D6 D5 D4 D3 D2 D1 D0

LP Delay

(graphics mode horizontal

compression disabled)

Extension Registers

Revision 1.2 120 65540 / 545

LP WIDTH REGISTER (XR2F)

Read/Write at I/O Address 3D7h

Index 2Fh

This register is used only in flat panel mode. This

LP output pulse in flat panel mode.

3-0 LP Width (HWidth)

These bits define the width of LP output

pulse in terms of number of character (8-dot

only) clocks in flat panel mode.

Programmed Value = Actual Value – 1

4LP Delay (XR2E) Bit 8

This bit is the msb of the LP Delay

parameter for 9-dot text modes.

5LP Delay (XR2D) Bit 8

This bit is the msb of the LP Delay

parameter for graphics mode with horizontal

compression disabled.

6LP Delay Disable

0 LP Delay Enable: XR2D and XR2F

bit-5 (or XR2E and XR2F bit-4) are

used to delay the LP active edge with

respect to the FP Blank inactive edge.

1LP Delay Disable: LP active edge will

coincide with the FP Blank inactive

edge.

7FLM Delay Disable

0FLM Delay Enable: XR2C is used to

delay the external FLM active edge

with respect to the internal FP VSync

active edge.

1FLM Delay Disable: the external FLM

active edge will coincide with the in-

ternal FLM active edge.

D7 D6 D5 D4 D3 D2 D1 D0

LP Width

LP Delay (XR2E) Bit-8

LP Delay (XR2D) Bit-8

LP Delay Disable

FLM Delay Disable

CLOCK DIVIDE CONTROL REGISTER (XR30)

Read/Write at I/O Address 3D7h

Index 30h

The three clock data registers (XR30-XR32) are

programmed with the loop parameters to be loaded

into the clock synthesizer. The Memory and Video

clock VCO's both have programmable registers.

Which of the VCO's is currently selected for

programming is determined by the Clock Register

Program Pointer (XR33[5]).

The data written to this register is calculated based on

the reference frequency, the desired output

frequency, and characteristic VCO constraints as

described in the Functional Description.

Data is written to registers XR30, and XR31

followed by a write to XR32. The completion of the

write to XR32 causes data from all three registers is

transferred to the VCO register file simultaneously.

This prevents wild fluctuations in the VCO output

during intermediate stages of a clock programming

sequence.

0Reference Divisor Select

Selects the reference pre-scale factor:

0Divide by 4

1 Divide by 1

3–1 Post Divisor Select

Selects the post-divide factor:

000 Divide by 1

001 Divide by 2

010 Divide by 4

011 Divide by 8

100 Divide by 16

101 Divide by 32

110 Divide by 64

111 Divide by 128

7–4 Reserved (R/W)

D7 D6 D5 D4 D3 D2 D1 D0

Reference Divisor Select

VCO Post Divide

Reserved (R/W)

Revision 1.2 121 65540 / 545

Extension Registers

CLOCK N-DIVISOR REGISTER (XR32)

Read/Write at I/O Address 3D7h

Index 32h

The three clock data registers (XR30-XR32) are

programmed with the loop parameters to be loaded

into the clock synthesizer. The Memory and Video

clock VCO's both have programmable registers.

Which of the VCO's is currently selected for

programming is determined by the Clock Register

Program Pointer (XR33[5]).

The data written to this register is calculated based on

the reference frequency, the desired output

frequency, and characteristic VCO constraints as

described in the Functional Description.

Data is written to registers XR30, and XR31

followed by a write to XR32. The completion of the

write to XR32 causes data from all three registers is

transferred to the VCO register file simultaneously.

This prevents wild fluctuations in the VCO output

during intermediate stages of a clock programming

sequence.

6–0 VCO N-Divisor

N-Divisor value calculated for the desired

output frequency.

7Reserved (R/W)

D7 D6 D5 D4 D3 D2 D1 D0

N-Divisor

Reserved (R/W)

Revision 1.2 122 65540 / 545

Extension Registers

CLOCK M-DIVISOR REGISTER (XR31)

Read/Write at I/O Address 3D7h

Index 31h

The three clock data registers (XR30-XR32) are

programmed with the loop parameters to be loaded

into the clock synthesizer. The Memory and Video

clock VCO's both have programmable registers.

Which of the VCO's is currently selected for

programming is determined by the Clock Register

Program Pointer (XR33[5]).

The data written to this register is calculated based on

the reference frequency, the desired output

frequency, and characteristic VCO constraints as

described in the Functional Description.

Data is written to registers XR30, and XR31

followed by a write to XR32. The completion of the

write to XR32 causes data from all three registers is

transferred to the VCO register file simultaneously.

This prevents wild fluctuations in the VCO output

during intermediate stages of a clock programming

sequence.

6–0 VCO M-Divisor

M-Divisor value calculated for the desired

output frequency.

7Reserved (R/W)

D7 D6 D5 D4 D3 D2 D1 D0

M-Divisor Value

Reserved (R/W)

Revision 1.2 123 65540 / 545

5Clock Register Program Pointer

This bit determines which of the VCO's is

being programmed. Following a write to

XR32 the data contained in XR32:30 is

synchronously transferred to the appropriate

VCO counter latch.

0VCLK VCO selected

1MCLK VCO selected

6Power Sequencing Reference Clock

0Use RCLK (reference clock) divided

by 384 as panel power sequencing

reference clock and Standby Mode

display memory refreshes. For

RCLK=14.31818 MHz, panel power

sequencing clock would be 37.5 KHz

(default).

1Use AA9 pin as 32 KHz clock input

for panel power sequencing reference

clock and Standby Mode display

memory refreshes. Asymmetric

DRAM option (XR05[3]=1) should

not be enabled in this case.

7Clock Mode Control

0Clock 0 and Clock 1 default to 25.175

and 28.322 MHz respectively.

1Clock 0 and Clock 1 default to 31.5

MHz and 35.5 MHz.

Extension Registers

CLOCK CONTROL REGISTER (XR33)

Read/Write at I/O Address 3D7h

Index 33h

D7 D6 D5 D4 D3 D2 D1 D0

VCLK VCO Powerdown

MCLK VCO Powerdown

Oscillator Powerdown

Reserved (R/W)

Video Clock Select

CLK Reg Program Pointer

Power Sequencing Clock

Clock Mode Control

0VCLK VCO Powerdown

0VCLK VCO Enabled (default)

1VCLK VCO Disabled

This bit is only effective if XR01[4] = 1.

1MCLK VCO Powerdown

0MCLK VCO Enabled (default)

1MCLK VCO Disabled

This bit is only effective if XR01[4] = 1.

2Oscillator Powerdown

0OSC Enabled (default)

1OSC Disabled

This bit is only effective if XR01[5] = 1 and

XR33[6] = 1.

3Reserved (R/W)

4Video Clock Select

0If XR01[4] = 1 (internal clock

source), use output of VCLK VCO as

video clock otherwise if XR04[4] = 0,

use RCLK input as video clock

(default).

1If XR01[4] = 1 (internal clock

source), use output of MCLK VCO

divided by 2 as the video clock;

otherwise if XR01[4]=0, then use

MCLK input divided by 2 as the video

clock.

COLOR KEY REGISTER 0 (XR3A)

Read/Write at I/O Address 3D7h

Index 3Ah

7-0 Color Compare Data 0

These bits are compared to the least signif-

icant 8 bits of the background video stream.

If a match occurs on all enabled bits (see

Color Compare Mask Register XR3D) and

the key is enabled (XR06[4]), external

video is sent to the screen. External video is

input on the MCD15:0, CASCH# and

CASCL# pins (and CA8-9, ACTI,

ENABKL, AA9, and OEC# if 24-bit

external video input is enabled

(XR05[7]=1)). The logical masking and

compare operations are described in the

functional description.

The color comparison occurs before the

RAMDAC. In 4BPP and 8BPP modes

using palette LUT data, the LUT index is

used in the comparison, not the 18BPP LUT

data.

D7 D6 D5 D4 D3 D2 D1 D0

Color Compare Data 0

Revision 1.2 124 65540 / 545

COLOR KEY REGISTER 1 (XR3B)

Read/Write at I/O Address 3D7h

Index 3Bh

7-0 Color Compare Data 1

These bits are compared to bits 15:8 of the

background video stream. If a match occurs

on all enabled bits (see Color Compare Mask

(XR06[4]), external video is sent to the

screen. External video is input on the

MCD15:0, CASCH# and CASCL# pins

(and CA8-9, ACTI, ENABKL, AA9, and

OEC# if 24-bit external video input is

enabled (XR05[7]=1)). The logical masking

and compare operations are described in the

functional description. This register should

be masked from participating in the

comparison in 4BPP and 8BPP modes.

This is accomplished by setting Color Mask

D7 D6 D5 D4 D3 D2 D1 D0

Color Compare Data 1

Extension Registers

COLOR KEY REGISTER 2 (XR3C)

Read/Write at I/O Address 3D7h

Index 3Ch

7-0 Color Compare Data 2

These bits are compared to bits 23:16 of the

background video stream. If a match occurs

on all enabled bits (see Color Compare Mask

(XR06[4]), external video is sent to the

screen. External video is input on the

MCD15:0, CASCH# and CASCL# pins

(and CA8-9, ACTI, ENABKL, AA9, and

OEC# if 24-bit external video input is

enabled (XR05[7]=1)). The logical masking

and compare operations are described in the

functional description. This register should

be masked from participating in the

comparison in 4BPP, 8BPP and 16BPP

modes. It should only be used in 24BPP

modes. This is accomplished by setting

Color Mask Register 2 (XR3F) = 0FFh.

D7 D6 D5 D4 D3 D2 D1 D0

Color Compare Data 2

Revision 1.2 125 65540 / 545

COLOR KEY MASK REGISTER 0 (XR3D)

Read/Write at I/O Address 3D7h

Index 3Dh

7-0 Color Compare Mask 0

This register is used to select which bits of

the background video data stream are used in

the comparison with the Color Compare Data

23:0. This register controls bits 7:0.

0Data does participate in compare

operation

1Data does not participate in compare

operation (masked)

D7 D6 D5 D4 D3 D2 D1 D0

Color Compare Mask 0

Extension Registers

COLOR KEY MASK REGISTER 1 (XR3E)

Read/Write at I/O Address 3D7h

Index 3Eh

7-0 Color Compare Mask 1

This register is used to select which bits of

the background video data stream are used in

the comparison with the Color Compare Data

23:0. This register controls bits 7:0.

0Data does participate in compare

operation

1Data does not participate in compare

operation (masked)

D7 D6 D5 D4 D3 D2 D1 D0

Color Compare Mask 1

Revision 1.2 126 65540 / 545

COLOR KEY MASK REGISTER 2 (XR3F)

Read/Write at I/O Address 3D7h

Index 3Fh

7-0 Color Compare Mask 2

This register is used to select which bits of

the background video data stream are used in

the comparison with the Color Compare Data

23:0. This register controls bits 7:0.

0Data does participate in compare

operation

1Data does not participate in compare

operation (masked)

D7 D6 D5 D4 D3 D2 D1 D0

Color Compare Mask 2

Extension Registers

Revision 1.2 127 65540 / 545

BitBLT CONFIG REGISTER (XR40) (65545 Only)

Read/Write at I/O Address 3D7h

Index 40h

1–0 BitBLT Draw Mode ( 65545 only )

The 65545 supports two color depths in its

drawing engine:

00 Reserved

01 8BPP

10 16BPP

11 Reserved

Note: 24BPP is handled in 8BPP mode.

There is no nibble mode access for

4BPP modes.

7–2 Reserved ( 0 )

D7 D6 D5 D4 D3 D2 D1 D0

BitBLT Draw Mode

Reserved (0)

This register contains eight read-write bits which

have no internal hardware function. All bits are

reserved for use by BIOS and driver software. For

reference, the functions of the bits of this register are

currently defined as follows:

7-0 Flags ( Reserved )

See also XR0F, XR2B, XR44 for definition of other

software flags registers.

SOFTWARE FLAGS REGISTER 2 (XR44)

Read/Write at I/O Address 3D7h

Index 44h

D7 D6 D5 D4 D3 D2 D1 D0

Set Panel Type

Optimal Compensation Ena

Reserved (0)

3-0 Set Panel Type ( 40K BIOS Only )

00 Panel #1

01 Panel #2

02 Panel #3

03 Panel #4

04 Panel #5

05 Panel #6

06 Panel #7

07 Panel #8

08-0F Reserved

4 Optimal Compensation Enable

0Disable optimal compensation

1Enable optimal compensation

7-5 Reserved ( 0 )

See also XR0F, XR2B, XR45 for definition of other

software flags registers.

This register contains eight read-write bits which

have no internal hardware function. All bits are

reserved for use by BIOS and driver software. For

reference, the functions of the bits of this register are

currently defined as follows:

SOFTWARE FLAGS REGISTER 3 (XR45)

Read/Write at I/O Address 3D7h

Index 45h

D7 D6 D5 D4 D3 D2 D1 D0

Flag 0

Flag 1

Flag 2

Flag 3

Flag 4

Flag 5

Flag 6

Flag 7

Extension Registers

PANEL FORMAT REGISTER 2 (XR4F)

Read/Write at I/O Address 3D7h

Index 4Fh

This register is used only in flat panel mode.

2-0 Bits Per Pixel Selection

The value in this field, along with the dither

and FRC settings, determines gray / color

levels produced: No FRC

# of msbs Gray / Gray /

Used Color Color

to Generate Levels Levels

Gray / Color without with

Levels Dithering Dithering

001 1 2 5

010 2 4 13

011 3 8 29

100 4 16 61

101 5 32 125

110 6 64 253

111 8 256 n/a

2-Frame FRC

(Color TFT or Monochrome Panels)

# of msbs Gray / Gray /

Used Color Color

to Generate Levels Levels

Gray / Color without with

Levels Dithering Dithering

010 1 3 9

011 2 5 25

100 3 15 57

101 4 31 121

Revision 1.2 128 65540 / 545

16-Frame FRC

(Color or Monochrome STN Panels)

# of msbs Gray / Gray /

Used Color Color

to Generate Levels Levels

Gray / Color without with

Levels Dithering Dithering

001 1 2 5

010 2 4 13

011 3 8 29

100 4 16 61

The setting programmed into this field deter-

mines how many most-significant color-bits

/ pixel are used to generate flat panel video

data. In general, 8 bits of monochrome data

or 8 bits/color of RGB color data enter the

flat panel logic for every dot clock. Not all

of these bits, however, are used to generate

output colors / gray scales, depending on the

type of panel used, graphics / text mode, and

the gray-scaling algorithm chosen (the actual

number of bits used is indicated in the table

above). If the VGA palette is used then a

maximum of 6 bits/pixel (bits 7-2) (setting

'110') should be used. If the VGA palette is

bypassed then a maximum of 8 bits/pixel

(bits 7-0) (setting '111) may be used. With

2-frame and 16-frame FRC, settings not

listed in the tables above are undefined.

Also note that settings which achieve higher

gray / color levels may not necessarily

produce acceptable display quality on some

(or any) currently available panels. This

document contains recommended settings

for various popular panels that Chips &

Technologies has found to produce

acceptable results with those panels.

Customers may modify these settings to

achieve a better match with their require-

ments.

3-5 Reserved (R/W)

6 M Pin Select

0M signal goes to the M pin (default on

reset)

1 FP Display Enable (FP Blank#) signal

goes to the M pin. Polarity is

controlled by XR54[0].

7 LP Pin Select

0FP HSync (LP) signal goes to the LP

pin. Polarity is controlled by

XR54[6] (default on reset).

1 FP Display Enable (FP Blank#) signal

goes to the LP pin. Polarity is

controlled by XR54[0].

D7 D6 D5 D4 D3 D2 D1 D0

Bits Per Pixel

Reserved (R/W)

M Functionality Select

LP Functionality Select

Extension Registers

PANEL FORMAT REGISTER 1 (XR50)

Read/Write at I/O Address 3D7h

Index 50h

This register is used only in flat panel mode.

1-0 Frame Rate Control ( FRC )

FRC is gray scale simulation on a frame-by-

frame basis to generate shades of gray or

color on panels that do not support gener-

ation of gray / color levels internally.

00 No FRC. This setting may be used

with all panels, especially for panels

which can generate shades of gray /

color internally.

01 16-frame FRC. This setting may be

used for Color STN or Monochrome

panels. One to four bits/pixel output

to the panel are possible and therefore

this setting is used only with panels

which do not support internal gray

scaling. This setting is used to

simulate 16 gray / color levels per

pixel. The bits per pixel are specified

by XR4F[2-0]; valid values are 001,

010, 011, and 100.

10 2-frame FRC. This setting may be

used for Color TFT or Monochrome

panels. One to four bits/pixel output

to the panel are possible and therefore

this setting can also be used with

panels that support internal gray

scaling. Number of input bits used

(specified in XR4F[2-0]) are one more

than the number of output bits.

Therefore, valid values for XR4F[2-0]

are 010, 011, 100, and 101.

11 Reserved

3-2 Dither Enable

00 Disable dithering

01 Enable dithering for 256-color modes

(AR10 bit-6 = 1 or XR28 bit 4 = 1)

10 Enable dithering for all modes

11 Reserved

Revision 1.2 129 65540 / 545

6-4 Clock Divide ( CD )

These bits specify the frequency ratio

between the dot clock and the flat panel shift

clock (SHFCLK) signal.

000 Shift Clock Freq = Dot Clock Freq.

This setting is used to output 1 pixel

per shift clock with a maximum of 8

bpp (bits/pixel) for single drive

monochrome panels. For double drive

color panels, this setting is used to

output 2 2/3 4-bit pack pixels. FRC

and dithering may be enabled.

001 Shift Clk Freq = 1/2 Dot Clock Freq.

This setting is used to output 2 pixels

per shift clock with a maximum of 8

bits/pixel for single drive monochrome

panels and 4 bpp for single drive color

panels. For double drive color panels,

this setting is used to output 5-1/3 4-

bit pack pixels. FRC and dithering

can be enabled.

010 Shift Clk Freq = 1/4 Dot Clock Freq.

This setting is used to output 4 pixels

per shift clock with a maximum of 4

bpp for single drive mono panels and

2 bits/pixel for single drive color

panels. For single drive color panels

this setting is used to output 5-1/3 4-

bit pack pixels. For double drive

monochrome panels, this setting is

used to output 8 pixels per shift clock

with 1 bit/pixel. FRC and dithering

can be enabled.

011 Shift Clk Freq = 1/8 Dot Clock Freq.

This setting is used to output 8 pixels

per shift clock with a maximum of 2

bpp for single drive mono panels and

1 bit/pixel for single drive color

panels. For double drive mono

panels, this setting is also used to

output 16 pixels per shift clock with 1

bit/pixel. FRC and dithering can be

enabled.

100 Shift Clk Freq = 1/16 Dot Clock Freq.

This setting is used to output 16 pixels

per shift clock with maximum of 1

bit/pixel for single drive monochrome

panels. Dithering can also be enabled.

7TFT Panel Data Width

This bit is effective only when TFT (active

matrix) panels are used (XR50 bits 1-0=10).

016-bit color TFT interface (565 RGB)

1 24-bit color TFT interface (888 RGB)

D7 D6 D5 D4 D3 D2 D1 D0

Frame Rate Control

Dither Enable

Clock Divide

TFT Panel Data Width

Extension Registers

1-0 Panel Type (PT)

These bits are effective for flat panel only.

00 Single Panel Single Drive (SS)

01 Reserved

10 Reserved

11 Dual Panel Double Drive (DD)

2Display Type (DT)

This bit is effective for CRT and flat panel.

This bit also controls the BLANK# output.

0CRT display (default on reset)

BLANK# outputs CRT Blank

1FP (Flat Panel) display

BLANK# outputs FP Blank

Note: There is no pin dedicated to output of

BLANK#. Therefore this bit is ignored if

BLANK# is not selected to be output on

either the M or LP output pins.

3 Shift Clock Divide

This bit is effective for flat panel only.

0Shift Clock to Dot Clock relationship

expressed by XR50[6-4].

1In this mode, the Shift Clock is further

divided by 2 and different video data

is valid on the rising and falling edges

of Shift Clock.

4Reserved (R/W)

5Shift Clock Mask (SM)

This bit is effective for flat panel only.

0 Allow shift clock output to toggle

outside the display enable interval

1Force the shift clock output low

outside the display enable interval

6Enable FP Compensation (EFCP)

This bit is effective for flat panel only. It

enables flat panel horizontal and vertical

compensation depending on panel size,

current display mode, and contents of the

compensation registers.

0Disable FP compensation

1Enable FP compensation

7LP During Vertical Blank

This bit should be set only for SS panels

which require FP HSync (LP) to be active

during vertical blank time when XR54 bit-1

= 0 (e.g., Plasma / EL panels). This bit

should be reset when using non-SS panels

or when XR54 bit-1 = 1.

0FP HSync (LP) is generated from

internal FP Blank inactive edge

1FP HSync (LP) is generated from

internal FP Horizontal Blank inactive

edge

DISPLAY TYPE REGISTER (XR51)

Read/Write at I/O Address 3D7h

Index 51h

D7 D6 D5 D4 D3 D2 D1 D0

Panel Type

Display Type

Shift Clock Divide

Reserved (R/W)

Shift Clock Mask

Enable FP Compensation

LP During V Blank

Revision 1.2 130 65540 / 545

Extension Registers

2-0 FP Normal Refresh Count

These bits specify the number of memory re-

fresh cycles to be performed per scanline. A

minimum value of 1 should be programmed

in this register.

3Panel Off Mode

This bit provides a software alternative to

enter Panel Off mode. Note that Panel Off

mode will be effective in both CRT and flat

panel modes of operation.

0 Normal mode (default on reset)

1Panel Off mode

In Panel Off mode, the CRT / FP display

memory interface is inactive but CPU

interface and display memory refresh are still

active. The internal RAMDAC is also

inactive.

4 Software Standby Mode

This bit provides an alternative way to enter

the Standby mode. When this bit is set, the

chip enters Standby mode. To exit Standby

mode, when this bit is set, the STNDBY#

pin must be asserted and then reasserted.

This bit will also be reset when the

STNDBY# pin goes active (low).

0Normal Mode (default on reset)

1Standby Mode

5Standby and Panel Off Control

This bit is effective in Flat Panel Mode

during Standby and Panel Off modes

(XR52[3] = 1 or (XR52[4] = 1 or

STNDBY#, pin 178 is active (low)).

0Video data and/or flat panel control

signals are driven inactive (default on

reset).

1Video data and flat panel control

signals pins are tri-stated with a weak

internal pull-down.

Note: XR61 bit-7 controls the inactive level

for video data in text mode; XR63 bit-7

controls the inactive level for video data in

graphics mode:

0 = low when inactive

1 = high when inactive

Note: This bit does not affect the HSYNC

and VSYNC pins. In Standby and Panel Off

modes, HSYNC and VSYNC will be driven

low.

6Standby Refresh Control

This bit is effective only in Standby mode

(STNDBY# pin low). Standby mode is

effective for both CRT and flat panel modes.

In Standby mode, CPU interface to display

memory and internal registers is inactive.

The CRT / FP display memory interface,

video data and timing signals, and internal

RAMDAC are inactive (all CRT and flat

panel video control and data pins are 3-

stated). Display memory refresh is

controlled by this bit.

0Self-Refresh DRAM support.

1Display memory refresh frequency is

derived from the 32KHz input or

RCLK (14.31818MHz Reference

Clock) divided per the value in XR5F.

7CRT Mode Control

This bit is effective in CRT mode only (non-

simultaneous CRT and flat panel) (XR51

bit-2 = 0).

0Video data and flat panel control

signals are 3-stated with weak internal

pull-down (default on reset).

1Video data and flat panel control

signals are inactive.

POWER DOWN CONTROL REGISTER (XR52)

Read/Write at I/O Address 3D7h

Index 52h

D7 D6 D5 D4 D3 D2 D1 D0

Normal Refresh Count

Panel Off Mode

Software Standby Mode

Standby/Panel Off Control

Standby Refresh Control

CRT Mode Control

Revision 1.2 131 65540 / 545

Extension Registers

0Disable AR10 Bit-2

0Use AR10 bit-2 for Line Graphics

control (default on Reset).

1Use XR53 bit-1 instead of AR10 bit-2

for Line Graphics control

1Alternate Line Graphics Character Control

This bit is effective only if bit-0 = 1.

0Ninth pixel of line graphics character

is set to the background color

1Ninth pixel of line graphics character

is identical to the eighth pixel

2FRC Option 1 (always program to 1)

3FRC Option 2 (always program to 1)

5-4 Color STN Pixel Packing

This field determines the type of pixel

packing (the RGB pixel output sequence) for

color STN panels. These bits should be

programmed only when color STN panels

are used. These bits must be programmed to

00 for monochrome panels or color TFT

panels.

00 3-bit Pack. XR50 bits 6-4 can be

000, 001, or 010.

01 4-bit Pack. For SS Color STN

panels, XR50 bits 6-4 can be 000,

001, or 010. For DD panels, XR50

bits 6-4 may be set to 000 or 001.

10 Reserved

11 Extended 4-bit Pack. XR50 bits 6-4

must be programmed to 001. This

setting may be used for 8-bit interface

Color STN SS panels only.

6FRC Option 3

This bit affects 2-frame FRC only

0FRC data changes every frame

1FRC data changes every other frame

7Reserved (R/W)

PANEL FORMAT REGISTER 3 (XR53)

Read/Write at I/O Address 3D7h

Index 53h

Revision 1.2 132 65540 / 545

D7 D6 D5 D4 D3 D2 D1 D0

Disable AR10 bit-2

Alt Line Gr Char Code Ctrl

FRC Option 1

FRC Option 2

Color STN Pixel Packing

FRC Option 3

Reserved (R/W)

Extension Registers

This register is used only in flat panel modes.

0FP Blank Polarity

This bit controls the polarity of the

BLANK# pin in flat panel mode. In CRT

mode, XR28 bit-0 controls polarity of the

BLANK# pin.

0Positive polarity

1Negative polarity

1 FP Blank Select

This bit controls the BLANK# pin output in

flat panel mode. In CRT mode, XR28 bit-1

controls the BLANK# output. This bit also

affects operation of the flat panel video

logic, generation of the FP HSync (LP)

pulse signals, and masking of the Shift

Clock.

0The BLANK# pin outputs both FP

Vertical and Horizontal Blank. In

480-line DD panels, this option will

generate exactly 240 FP HSync (LP)

pulses.

1The BLANK# pin outputs only FP

Horizontal Blank. During FP Vertical

Blank, the flat panel video logic will

be active, the FP HSync (LP) pulse

will be generated, and Shift Clock can

not be masked. Note however that

Shift Clock can still be masked during

FP Horizontal Blank.

Note: The signal polarity selected by bit-0 is

applicable for either selection.

3-2 FP Clock Select Bits 1-0

Select flat panel dot clock source. These bits

are used instead of Miscellaneous Output

See description of MSR bits 3-2.

5-4 FP Feature Control Bits 1-0

Select flat panel dot clock source. These bits

are used instead of Feature Control Register

(FCR) bits 1-0 in flat panel mode. See des-

cription of FCR bits 1-0.

6FP HSync (LP) Polarity

This bit controls the polarity of the flat panel

HSync (LP) pin.

0Positive polarity

1Negative polarity

7FP VSync (FLM) Polarity

This bit controls the polarity of the flat panel

VSync (FLM) pin.

0Positive polarity

1Negative polarity

PANEL INTERFACE REGISTER (XR54)

Read/Write at I/O Address 3D7h

Index 54h

D7 D6 D5 D4 D3 D2 D1 D0

FP Blank Polarity

FP Blank Select

FP Clock Select

FP Feature Control

FP LP Polarity

FP FLM Polarity

Revision 1.2 133 65540 / 545

Extension Registers

This register is used only in flat panel modes when

flat panel compensation is enabled (XR51 bit-6 = 1).

0Enable Horizontal Compensation (EHCP)

0Disable horizontal compensation

1Enable horizontal compensation

1Enable Automatic Horizontal Centering

(EAHC) (effective only if bit-0 is 1)

0Enable non-automatic horizontal cen-

tering. The Horizontal Centering

border. If no centering is desired then

the Horizontal Centering Register can

be programmed to 0.

1Enable automatic horizontal centering.

Horizontal left and right borders will

be computed automatically.

2 Enable Text Mode Horizontal Compression

(ETHC) (this bit is effective only if bit-0 is 1

in flat panel text mode). Setting this bit will

turn on text mode horizontal compression re-

gardless of horizontal display width or

horizontal panel size.

0Text mode horizontal compression off

1Text mode horizontal compression on.

8-dot text mode is forced when 9-dot

text mode is specified (SR01 bit-0 = 0

or Hercules text).

Note: This bit affects the horizontal pixel

panning logic. When text mode horizontal

compression is active, programming 9-bit

panning will result in 8-bit panning.

4-3 Reserved (R/W)

5Enable Automatic Horizontal Doubling

(EAHD) (this bit is effective if bit-0 is 1)

0Disable Automatic Horizontal Dou-

bling. Horizontal doubling will only

be performed for flat panels when

SR01 bit-3 = 1 in any emulation mode

or when 3B8/3D8 bit-0 & 3B8/3D8

bit-4 = 0 in CGA emulation.

1Enable Automatic Horizontal Dou-

bling. Horizontal doubling will be

performed for flat panels when SR01

bit-3 = 1 in any emulation mode or

when 3B8/3D8 bit-0 & 3B8/3D8 bit-4

= 0 in CGA emulation or when the

Horizontal Display width (CR01) is

equal to or less than half of the

Horizontal Panel Size (XR18).

6Alternate CRT HSync Polarity

0Positive

1 Negative

7Alternate CRT VSync Polarity

0Positive

1 Negative

Note: bits 6 and 7 above are used in flat

panel mode (XR51 bit-2 = 1) instead of

MSR bits 6 and 7). This is primarily used

for simultaneous CRT / Flat Panel display.

HORIZONTAL COMPENSATION REGISTER

(XR55)

Read/Write at I/O Address 3D7h

Index 55h

D7 D6 D5 D4 D3 D2 D1 D0

Ena H Compensation

Ena H Auto Centering

Ena H Compression

Reserved (R/W)

Ena Auto H Doubling

Alternate HSync Polarity

Alternate VSync Polarity

Revision 1.2 134 65540 / 545

Extension Registers

This register is used only in flat panel modes when

non-automatic horizontal centering is enabled.

7-0 Horizontal Left Border (HLB)

Programmed Value (in character clocks)

= Width of Left Border – 1

HORIZONTAL CENTERING REGISTER (XR56)

Read/Write at I/O Address 3D7h

Index 56h

Revision 1.2 135 65540 / 545

D7 D6 D5 D4 D3 D2 D1 D0

Left Border

Extension Registers

This register is used only in flat panel modes when

flat panel compensation is enabled.

0 Enable Vertical Compensation (EVCP)

0Disable vertical compensation

1Enable vertical compensation

1 Enable Automatic Vertical Centering

(EAVC)

This bit is effective only if bit-0 is 1.

0Enable non-automatic vertical

centering. The Vertical Centering

border. If no centering is desired then

the Vertical Centering Register can be

programmed to 0.

1Enable automatic vertical centering.

Vertical top and bottom borders will

be computed automatically.

2 Enable Text Mode Vertical Stretching

(ETVS)

This bit is effective only if bit-0 is 1.

0Disable text mode vertical stretching;

graphics mode vertical stretching is

used if enabled.

1Enable text mode vertical stretching

4-3 Text Mode Vertical Stretching (TVS1-0)

These bits are effective if bits 2 and 0 are 1.

00 Double Scanning (DS) and Line

Insertion (LI) with the following

priority: DS+LI, DS, LI.

01 Double Scanning (DS) and Line

Insertion (LI) with the following

priority: DS+LI, LI, DS.

10 Double Scanning (DS) and TallFont

(TF) with the following priority:

DS+TF, DS, TF.

11 Double Scanning (DS) and TallFont

(TF) with the following priority:

DS+TF, TF, DS.

5Enable Vertical Stretching (EVS)

This bit is effective only if bit-0 is 1.

0Disable vertical stretching

1Enable vertical stretching

6Vertical Stretching (VS)

Vertical Stretching can be enabled in both

text and graphics modes. This bit is

effective only if bits 5 and 0 are 1.

0Double Scanning (DS) and Line

Replication (LR) with the following

priority: DS+LR, DS, LR.

1Double Scanning (DS) and Line

Replication (LR) with the following

priority: DS+LR, LR, DS.

7Disable Fast Centering

This bit is effective only if XR58[1-0] = 11.

0Enable Fast Centering

1Disable Fast Centering

D7 D6 D5 D4 D3 D2 D1 D0

Enable V Compensation

Enable Auto V Centering

Enable Text V Stretching

Text V Stretch Method

Enable Gr V Stretching

Gr V Stretch Method

Disable Fast Centering

Revision 1.2 136 65540 / 545

VERTICAL COMPENSATION REGISTER (XR57)

Read/Write at I/O Address 3D7h

Index 57h

Extension Registers

Revision 1.2 137 65540 / 545

This register is used only in flat panel modes when

non-automatic vertical centering is enabled.

7-0 Vertical Top Border LSBs (VTB7-0)

Programmed value:

Top Border Height (in scan lines) – 1

This register contains the eight least signif-

icant bits of the programmed value of the

Vertical Top Border (VTB). The two most

significant bits are in the Vertical Line

Insertion Register (XR59).

VERTICAL LINE INSERTION REGISTER (XR59)

Read/Write at I/O Address 3D7h

Index 59h

This register is used only in flat panel text mode

when vertical line insertion is enabled.

3-0 Vertical Line Insertion Height (VLIH3-0)

Programmed Value:

Number of Insertion Lines – 1

The value programmed in this register - 1 is

the number of lines to be inserted between

the rows. Insertion lines are never double

scanned even if double scanning is enabled.

Insertion lines use the background color.

4Reserved (0)

6-5 Vertical Top Border MSBs (VTB9-8)

This register contains the two most signif-

icant bits of the programmed value of the

Vertical Top Border (VTB). The eight least

significant bits are in the Vertical Centering

7Hardware Line Replication

This bit is effective in text mode when Line

Replication is selected (XR57[2] = 1).

Hardware line replication, when enabled,

replicates lines to display a 19-line character

from a 16-line font as specified in XR28 bit-

0Normal text mode line replication

1Hardware line replication is enabled

D7 D6 D5 D4 D3 D2 D1 D0

V Line Insertion Height

Reserved (0)

Top Border Bits 8-9

Hardware Line Replication

VERTICAL CENTERING REGISTER (XR58)

Read/Write at I/O Address 3D7h

Index 58h

D7 D6 D5 D4 D3 D2 D1 D0

Top Border LSBs

Extension Registers

Revision 1.2 138 65540 / 545

This register is used only in flat panel text or

graphics modes when vertical line replication is

enabled.

3-0 Vertical Line Replication Height (VLRH)

Programmed Value = Number of Lines

Between Replicated Lines – 1

Double scanned lines are also counted.

In other words, if this field is programmed

with '7', every 8th line will be replicated.

7-4 Reserved (R/W)

VERTICAL LINE REPLICATION REGISTER

(XR5A)

Read/Write at I/O Address 3D7h

Index 5Ah

D7 D6 D5 D4 D3 D2 D1 D0

Line Replication Height

Reserved (R/W)

PANEL POWER SEQUENCING

DELAY REGISTER (XR5B)

Read/Write at I/O Address 3D7h

Index 5Bh

D7 D6 D5 D4 D3 D2 D1 D0

Delay on Power Down

Delay on Power Up

This register is used only in flat panel modes. The

generation of the clock for panel power sequencing

logic is controlled by XR33[6]. The delay intervals

below assume a 37.5 KHz clock generated by the

internal clock synthesizer. If the 32KHz input is

used, the delay intervals should be scaled accord-

ingly.

3-0 Power Down Delay

Programmable value of panel power-

sequencing during power down. This value

can be programmed up to 459 milliseconds

in increments of 29 milliseconds. A value of

0 is undefined.

7-4 Power Up Delay

Programmable value of panel power

sequencing during power up. This value can

be programmed up to 54 milliseconds in

increments of 3.4 milliseconds. A value of

0 is undefined.

Extension Registers

Revision 1.2 139 65540 / 545

This register is used to control Activity timer

functionality. The activity timer is an internal

counter that starts counting from a value

programmed into this register (see bits 0-4 below)

and is reset back to that count by read or write

accesses to graphics memory or I/O. If no accesses

occur, the counter counts till the end of its

programmed interval and activates either the

ENABKL pin or Panel Off mode (as selected by bit-

6 below). The timer count does not have to be

reloaded once programmed and the timer enabled:

any access to the chip with the timer timed out

(ENABKL active or Panel Off mode active) will

reset the timer and the ENABKL pin de-activated (or

Panel Off mode exited, whichever is selected). The

activity timer uses the same clock as power

sequencing which is controlled by XR33[6]. The

delay intervals below assume a 35.7 KHz clock, if

an external 32KHz input is used, the delay is scaled

accordingly.

4-0 Activity Timer Count

For a 35.7 KHz clock the counter

granularity is approximately 25.6 seconds.

The minimum programmed value of 1

results in 25.6 second delay and the

maximum count of 32 results in a delay of

13.7 minutes. If the clock input on pin 154

(AA9) is other than 32 KHz, the delay

should be scaled accordingly.

5Reserved (R/W)

ACTIVITY TIMER CONTROL REGISTER (XR5C)

Read/Write at I/O Address 3D7h

Index 5Ch

D7 D6 D5 D4 D3 D2 D1 D0

Activity Timer Count

Reserved (R/W)

Activity Timer Action

Enable Activity Timer

6Activity Timer Action

0When the activity timer count is

reached, the ENABKL pin is activated

(driven low to turn the backlight off)

1When the activity timer count is

reached, Panel Off mode is entered.

7Enable Activity Timer

0Disable activity timer (default on reset)

1Enable activity timer

See also XR5D bit-2.

Extension Registers

Revision 1.2 140 65540 / 545

518-bit Color TFT Test Mode

0Disable 18-bit color TFT test mode

(default on reset)

1Enable 18-bit color TFT test mode

6Prevent HSYNC and VSYNC Deactivation

0Allow HSYNC and VSYNC to be

deactivated when XR06[1] = 1

(default on reset)

1Prevents HSYNC and VSYNC from

being deactivated when XR06[1] = 1.

7Enable Palette Powerdown in Bypass Mode

0Disable VGA palette powerdown

when XR06[5]=1

1 Enable VGA palette powerdown when

XR06[5]=1 and XR06[1]=1

FP DIAGNOSTIC REGISTER (XR5D)

Read/Write at I/O Address 3D7h

Index 5Dh

D7 D6 D5 D4 D3 D2 D1 D0

Enable Palette Powerdown

Enable Access in PNLOFF

Enable Activity Timer Test

Force 16-bit Local Bus

Disable Vertical Comp

18-bit Color Test Mode

HSync/VSync Deactivation

Enable Palette Powerdown

0Enable Panel-Off VGA Palette Powerdown

0Disable VGA Palette powerdown in

Panel Off Mode (default on reset)

1Enable VGA Palette powerdown in

Panel Off mode

1Enable Panel-Off VGA Palette Access

This bit is effective when bit 0=1 or bit 7=1.

0Disable CPU access to VGA Palette in

Panel Off Mode (default on reset)

1Enable CPU access to VGA Palette in

Panel Off Mode

2Enable Activity Timer Test

0Disable Activity Timer test mode

(default on reset)

1Enable Activity Timer test mode

3Force 16-Bit Local Bus

This bit is effective when 32-bit local bus

and 16-bit memory interface are used during

font load.

0Do not force 16-bit local bus when

loading font (default on reset)

1Force 16-bit local bus when loading

font

4Disable Vertical Compensation

0Vertical compensation can be enabled

in all cases (default on reset)

1Disable vertical compensation if

Vertical Display Enable End equals

Vertical Panel Size.

Extension Registers

Revision 1.2 141 65540 / 545

7-0 Power Down Refresh Frequency

These bits define the frequency of memory

refresh cycles in power down (standby)

mode (STNDBY# pin low). CAS-Before-

RAS (CBR) refresh cycles are performed.

If XR52 bit-6 = 1, the interval between two

refresh cycles is determined by bits 0-3 of

this register per the table below. Bits 4-7 of

this register are reserved for future use in

this mode (and should be programmed to 0).

3 2 1 0Approximate Refresh Interval

0 0 0 0 16 usec / cycle

0 0 0 1 47 usec / cycle

0 0 1 0 63 usec / cycle

0 0 1 1 78 usec / cycle

0 1 0 0 94 usec / cycle

0 1 0 1 109 usec / cycle

0 1 1 0 125 usec / cycle

0 1 1 1 141 usec / cycle

1 0 0 0 156 usec / cycle

These refresh intervals assume a 32 KHz

clock. If the internal clock is used, the

refresh interval is scaled accordingly.

If XR52 bit-6 = 0, a value of 0 causes no

refresh to be performed. Self-Refresh

DRAMs should be used in this case.

POWER DOWN REFRESH REGISTER (XR5F)

Read/Write at I/O Address 3D7h

Index 5Fh

D7 D6 D5 D4 D3 D2 D1 D0

Power Down Refresh Freq

M (ACDCLK) CONTROL REGISTER (XR5E)

Read/Write at I/O Address 3D7h

Index 5Eh

This register is used only in flat panel mode.

6-0 M ( ACDCLK ) Count ( ACDCNT )

These bits define the number of HSyncs

between adjacent phase changes on the M

(ACDCLK) output. These bits are effective

only when bit 7 = 0 and the contents of this

Programmed Value = Actual Value – 2

7 M ( ACDCLK ) Control

0The M (ACDCLK) phase changes

depending on bits 0-6 of this register

1The M (ACDCLK) phase changes

every frame if the frame accelerator is

not used. If the frame accelerator is

used, the M (ACDCLK) phase

changes every other frame.

If XR4F bit-6 is programmed to one to enable flat

panel DE / BLANK# to be output on the M

(ACDCLK) pin, the contents of this register will be

ignored.

D7 D6 D5 D4 D3 D2 D1 D0

M (ACDCLK) Count

M (ACDCLK) Control

Extension Registers

Revision 1.2 142 65540 / 545

BLINK RATE CONTROL REGISTER (XR60)

Read/Write at I/O Address 3D7h

Index 60h

This register is used in all modes.

5-0 Cursor Blink Rate

These bits specify the cursor blink period in

terms of number of VSyncs (50% duty

cycle). In text mode, the character blink

period and duty cycle is controlled by bits 7-

6 of this register. These bits default to

000011 (decimal 3) on reset which

corresponds to eight VSyncs per cursor

blink period per the following formula (four

VSyncs on and four VSyncs off):

Programmed Value = (Actual Value) / 2 – 1

Note: In graphics mode, the pixel blink

period is fixed at 32 VSyncs per cursor blink

period with 50% duty cycle (16 on and 16

off).

7-6 Character Blink Duty Cycle

These bits specify the character blink (also

called 'attribute blink') duty cycle in text

mode.

Character Blink

7 6 Duty Cycle

0 0 50%

0 1 25%

1 0 50% (default on Reset)

1 1 75%

For setting 00, the character blink period is

equal to the cursor blink period. For all

other settings, the character blink period is

twice the cursor blink period (character blink

is twice as slow as cursor blink).

D7 D6 D5 D4 D3 D2 D1 D0

Cursor Blink Rate

Char Blink Duty Cycle

Extension Registers

This register is used in flat panel text mode only.

0SmartMap™ Enable

0Disable SmartMap™, use color

lookup table and use internal

RAMDAC palette if enabled (XR06

bit-2 = 1).

1Enable SmartMap™, bypass both

color lookup table and internal

RAMDAC palette in flat panel text

mode. Although color lookup table is

bypassed, translation of 4 bits/pixel

data to 6 bits/pixel data is still

performed depending on AR10 bit-1

(monochrome / color display) as

follows:

Output AR10 bit-1 = 0 AR10 bit-1 = 1

Out0 In0 In0

Out1 In1 In1

Out2 In2 In2

Out3 In3 In0+In1+In2+In3

Out4 In3 In3

Out5 In3 In3

Note: This bit does not affect CRT text /

graphics mode or flat panel graphics mode;

i.e.: the color lookup table is always used,

and similarly the internal RAMDAC palette

is used if enabled.

4-1 SmartMap™ Threshold

These bits are used only in flat panel text

mode when SmartMap™ is enabled (bit-0 =

1). They define the minimum difference

between the foreground and background

colors. If the difference is less than this

threshold, the colors are separated by adding

and subtracting the shift values (XR62) to

the foreground and background colors.

However, if the foreground and background

color values are the same, then the color

values are not adjusted.

5SmartMap™ Saturation

This bit is used only in flat panel text mode

when SmartMap™ is enabled (bit-0 = 1). It

selects the clamping level after the color

addition/subtraction.

0The color result is clamped to the

maximum and minimum values (0Fh

and 00h respectively)

1The color result is computed modulo

16 (no clamping)

6Text Enhancement

This bit is used only in flat panel text mode.

0Normal text

1Text attribute 07h and 0Fh are

reversed to maximize the brightness of

the normal DOS prompt

Note: This bit should be set to 0 if XR63[6]

is set to 1. Conversely, if this bit is

set to 1, XR63[6] should be set to 0.

7Text Video Output Polarity (TVP)

This bit is effective for flat panel text mode

only.

0Normal polarity

1Inverted polarity

Note: Graphics video output polarity is

controlled by XR63 bit-7 (GVP).

SMARTMAP™ CONTROL REGISTER (XR61)

Read/Write at I/O Address 3D7h

Index 61h

Revision 1.2 143 65540 / 545

D7 D6 D5 D4 D3 D2 D1 D0

SmartMap™ Enable

SmartMap™ Threshold

SmartMap™ Saturation

Text Enhancement

Text Video Output Polarity

Extension Registers

Revision 1.2 144 65540 / 545

This register is used in flat panel text mode when

SmartMap™ is enabled (XR61 bit-0 = 1).

3-0 Foreground Shift

These bits define the number of levels that

the foreground color is shifted when the

foreground and background colors are closer

than the SmartMap™ Threshold (XR61 bits

1-4). If the foreground color is "greater"

than the background color, then this field is

added to the foreground color. If the

foreground color is "smaller" than the

background color, then this field is sub-

tracted from the foreground color.

7-4 Background Shift

These bits define the number of levels that

the background color is shifted when the

foreground and background colors are closer

than the SmartMap™ Threshold (XR61 bits

1-4). If the background color is "greater"

than the foreground color, then this field is

added to the background color. If the

background color is "smaller" than the

foreground color, then this field is sub-

tracted from the background color.

SMARTMAP™ COLOR MAPPING CONTROL

Read/Write at I/O Address 3D7h

Index 63h

5-0 Color Threshold

These bits are effective for monochrome

(XR51 bit-5 = 1) single/double drive flat

panel with 1 bit/pixel (XR50 bits 4-5 = 11)

without FRC (XR50 bits 0-1 = 11). They

specify the color threshold used to reduce 6-

bit video to 1-bit video color. Color values

equal to or greater than the threshold are

mapped to 1 and color values less than the

threshold are mapped to 0.

6 New Text Enhancement

If set this bit enables new text enhancement

that does not affect the CRT display. If this

bit is set to 1, the old text enhancement bit

(XR61[6]) must be set to 0. Conversely, if

XR61[6] is 1 then this bit should be set to 0.

Reset defaults this bit to 1.

7 Graphics Video Output Polarity (GVP)

This bit is effective for CRT and flat panel

graphics mode only.

0Normal polarity

1Inverted polarity

Note: Text video output polarity is

controlled by XR61 bit-7 (TVP).

D7 D6 D5 D4 D3 D2 D1 D0

Color Threshold

New Text Enhancement

Gr Video Output Polarity

SMARTMAP™ SHIFT PARAMETER

Read/Write at I/O Address 3D7h

Index 62h

D7 D6 D5 D4 D3 D2 D1 D0

Foreground Shift

Background Shift

Extension Registers

Revision 1.2 145 65540 / 545

This register is used in all flat panel modes.

7-0 FP Alternate Vertical Total

The contents of this register are 8 low order

bits of a 10-bit value. Bits 9 and 10 are

defined in XR65. The vertical total value

specifies the total number of scan lines per

frame. Similar to CR06.

Programmed Value = Actual Value _ 2

FP ALTERNATE OVERFLOW

Read/Write at I/O Address 3D7h

Index 65h

This register is used in all flat panel modes.

0FP Alternate Vertical Total Bit-8

1FP Vertical Panel Size Bit-8

2FP Alternate Vertical Sync Start Bit-8

3Reserved (R/W)

4 Reserved (R/W)

5FP Alternate Vertical Total Bit-9

6FP Vertical Panel Size Bit-9

7FP Alternate Vertical Sync Start Bit-9

FP ALTERNATE VERTICAL TOTAL

Read/Write at I/O Address 3D7h

Index 64h

D7 D6 D5 D4 D3 D2 D1 D0

FP Alternate V Total

D7 D6 D5 D4 D3 D2 D1 D0

FP Alt V Total Bit-8

FP V Panel Size Bit-8

FP Alt VSync Start Bit-8

Reserved (R/W)

FP Alt V Total Bit-9

FP Alt Panel Size Bit-9

FP Alt VSync Start Bit-9

Extension Registers

Revision 1.2 146 65540 / 545

This register is used in all flat panel modes.

7-0 FP Alternate Vertical Sync Start

The contents of this register are the 8 low

order bits of a 10-bit value. Bits 9 and 10

are defined in XR65. This value defines the

scan line position at which vertical sync

becomes active. Similar to CR10.

Programmed Value = Actual Value – 1

FP ALTERNATE VERTICAL SYNC END

Read/Write at I/O Address 3D7h

Index 67h

This register is used in all flat panel modes.

3-0 FP Alternate Vertical Sync End

The lower 4 bits of the scan line count that

defines the end of vertical sync. Similar to

CR11. If the vertical sync width desired is

N lines, the programmed value is:

(contents of XR66 + N) ANDed with 0FH

7-4 Reserved (R/W)

FP ALTERNATE VERTICAL SYNC START

Read/Write at I/O Address 3D7h

Index 66h

D7 D6 D5 D4 D3 D2 D1 D0

FP Alternate VSync Start

D7 D6 D5 D4 D3 D2 D1 D0

FP Alt VSync End

Reserved (R/W)

Extension Registers

Revision 1.2 147 65540 / 545

This register is used in all flat panel modes.

7-0 Vertical Panel Size

The contents of this register define the

number of scan lines per frame.

Programmed Value = Actual Value – 1

Panel size bits 8-9 are defined in overflow

Note: Programming lower drive for 3.3V

operation results in lower than rated output

drive. Programming higher output drive for

5V operation results in higher than rated

output drive.

VERTICAL PANEL SIZE REGISTER (XR68)

Read/Write at I/O Address 3B7h/3D7h

Index 68h

D7 D6 D5 D4 D3 D2 D1 D0

Vertical Panel Size

PROGRAMMABLE OUTPUT DRIVE REGISTER

(XR6C)

Read/Write at I/O Address 3B7h/3D7h

Index 6Ch

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (R/W)

CFG8/LV#: Vcc Select

Flat Panel Output Drive

Bus Interface Output Drive

Mem Intfc A&B Out Drive

Mem Intfc C Out Drive

Reserved (R/W)

This register is used to control the output drive of the

bus, video, and memory interface pins.

0Reserved (R/W)

1CFG8 / LV# - Internal Logic Vcc Selection

This bit determines pad input threshold. On

the trailing edge of reset, this bit will latch

the state of AA8 pin (CFG8).

0 VCC for internal logic (IVCC) is 3.3V

1 VCC for internal logic (IVCC) is 5V

(Default)

2Flat Panel Interface Output Drive Select

0Lower drive (Default) (Use for

DVCC=5V)

1Higher drive (Use for DVCC=3.3V)

3Bus Interface Output Drive Select

0Higher drive (Default) (Use for

BVCC=3.3V)

1Lower drive (Use for BVCC=5V)

4Memory Interface A&B Output Drive Select

This bit affects memory interface groups A

& B control pins: RASB#, CASBH#,

CASBL#, WEB#, OEB#, MAD[15:0] and

MBD[15:0]

0Lower drive (Default) (Use for

MVCCA/B=5V)

1Higher drive (Use for

MVCCA/B=3.3V)

5Memory Interface C Output Drive Select

This bit affects memory interface group C

control pins: RASC#, CASCH#, CASCL#,

WEC#, OEC#, and MCD15:0.

0Lower drive (Default) (Use for

MVCCC=5V)

1Higher drive (Use for MVCCC=3.3V)

7-6 Reserved (R/W)

Extension Registers

Revision 1.2 148 65540 / 545

This register is effective in flat panel mode when

polynomial FRC is enabled (see XR50 bits 0-1). It

is used to control the FRC polynomial counters. The

values in the counters determine the offset in rows

and columns of the FRC count. These values are

usually determined by trial and error.

3-0 Polynomial 'N' value

7-4 Polynomial 'M' value

This register defaults to '10111101' on reset.

POLYNOMIAL FRC CONTROL REGISTER

(XR6E)

Read/Write at I/O Address 3D7h

Index 6Eh

D7 D6 D5 D4 D3 D2 D1 D0

Polynomial 'N' Value

Polynomial 'M' Value

Extension Registers

Revision 1.2 149 65540 / 545

FRAME BUFFER CONTROL REGISTER (XR6F)

Read/Write at I/O Address 3D7h

Index 6Fh

This register is effective in flat panel mode only.

0Frame Buffer Enable

This bit is used to enable frame buffer

operation (external or embedded). Frame

buffering is required for DD panel operation.

For SS panel operation (LCD, Plasma or

EL), frame buffering is not required so this

bit should be set to 0.

0Disable frame buffer (default)

1Enable frame buffer

Since the 65540 and 65545 have the ability

to embed frame buffer data in display

memory, enabling frame buffering does not

mean that an external DRAM frame buffer

chip is required (see bit-7 of this register to

set the frame buffer method).

1Frame Accelerator Enable

Frame acceleration may be used for panels

with vertical refresh rate specifications above

110 Hz to reduce the dot clock rate. For

panels with vertical refresh rate specifica-

tions below 110 Hz, Frame Acceleration will

violate panel specifications and should not

be used.

This bit should be programmed to 0 when

the Frame Buffer is disabled (bit-0 of this

this bit is set to 1, bit-0 of this register must

be set to 1 and a DD panel must be used

(XR51[1-0], Panel Type, must be set to 11).

0Disable frame accelerator (default)

1Enable frame accelerator

D7 D6 D5 D4 D3 D2 D1 D0

2Asymmetric Address for DRAM C

064Kx16 DRAM (8-bit RAS and CAS

address)

1Symmetric or Asymmetric 256Kx16

DRAM (9-bit RAS and CAS address

or 10 bit RAS and 8 bit CAS

addresses)

This bit is effective only if bit 7=1. Either

Symmetric or Asymmetric DRAMs may be

used.

5-3 Frame Buffer Refresh Count

These bits are effective only if bit 7=1.

6Frame Buffer Lines / Page

01 line per DRAM page

12 lines per DRAM page

This bit is effective only if bit 7=1.

Note: 65540 only, should be programmed

with 0 in the 65545.

7Frame Buffer Method

0Embedded Frame Buffer. Frame

buffer data is stored in display

memory (DRAM A or DRAMs A & B

depending on the setting of XR04 bits

0-1)

1 External Frame Buffer. DRAM "C" is

used exclusively for frame buffer data.

Note: This bit can be set to 1 only when

XR04[1-0] (Memory Configuration) is set to

either 00 (Display Memory in DRAMs A &

B) or 01 (Display Memory in DRAM A).

Frame Buffer Enable

Frame Accelerator Enable

DRAM C Asym addr select

Frame Buffer Refrsh Count

Frame Buffer Lines/Page

Frame Buffer Method

Extension Registers

Revision 1.2 150 65540 / 545

SETUP / DISABLE CONTROL REGISTER (XR70)

Read/Write at I/O Address 3D7h

Index 70h

6-0 Reserved (0)

73C3 / 46E8 Register Disable

0In local bus configuration, port 3C3h

works as defined to provide control of

VGA disable. In ISA bus config-

uration, port 46E8h works as defined

to provide control of VGA disable and

setup mode.

1In local bus configuration, writes to

I/O port 3C3 have no effect. In ISA

bus configuration, writes to I/O port

46E8h have no effect (the VGA

remains enabled and will not go into

setup mode).

Note: Writes to register 46E8 are only

effective in ISA bus configurations (46E8 is

ignored in local bus configurations

independent of the state of this bit). Writes

to 3C3 are only effective in local bus config-

urations (3C3 is ignored in ISA bus config-

urations independent of the state of this bit).

In PCI bus configuration (65545), this

disabled except for the PCI configuration

registers and the PCI configuration registers

control VGA access.

Reads from ports 3C3 and 46E8h have no effect

independent of the programming of this register

(both 3C3 and 46E8h are write-only registers).

This register is cleared by reset.

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (0)

3C3/46E8 Register Disable

Extension Registers

Revision 1.2 151 65540 / 545

5GPIO1 ( ENABKL ) Data

This bit always reads back the status of the

ENABKL pin (pin 54). When ENABKL is

configured as general purpose output

(XR72[7-6]=11), this bit determines the data

output on the ENABKL pin.

7-6 GPIO1 ( ENABKL ) Pin Control

This bit is effective only when XR01[4]=1,

XR50[7]=0, and XR05[7-6]≠11.

00 Pin 54 is used to output ENABKL

(enable backlight) (default on reset)

01 Reserved

10 Pin 54 is general purpose input 1

(GPIO1)

11 Pin 54 is general purpose output 1

(GPIO1)

See also XR5C "Activity Timer Control Register".

The activity timer may be used to activate ENABKL

or to evoke Panel Off mode after a specified time

interval.

EXTERNAL DEVICE I/O REGISTER (XR72)

Read/Write at I/O Address 3D7h

Index 72h

D7 D6 D5 D4 D3 D2 D1 D0

0Reserved (R/W)

1ENAVEE Pin Control

0Pin 61 is used as Enable VEE

(ENAVEE) output (default on reset)

1Pin 61 is used as Enable Backlight

(ENABKL) output

2GPIO0 ( ACTI ) Data

This bit always reads back the state of the

ACTI pin (pin 53). When ACTI is

configured as general purpose output

(XR72[4-3]=11) this bit determines the data

output on ACTI pin.

4-3 GPIO0 ( ACTI ) Pin Control

This bit is effective only when XR01[4]=1,

XR50[7]=0, and XR05[7-6]≠11.

00 Pin 53 is ACTI output (default on

reset). ACTI goes high during valid

VGA memory or I/O read or write

operations that are recognized by the

chip.

01 Reserved

10 Pin 53 is general purpose input 0

(GPIO0)

11 Pin 53 is general purpose output 0

(GPIO0)

Reserved (R/W)

ENAVEE Pin Control

GPIO0 (ACTI) Data

GPIO0 (ACTI) Pin Control

GPIO1 (ENABKL) Data

GPIO1 (ENABKL) Pin Ctrl

Extension Registers

Revision 1.2 152 65540 / 545

This register is provided to allow the controller to

independently shut down either or both of the

HSYNC and VSYNC outputs. This capability

allows the controller to signal a CRT monitor to enter

power-saving states per the VESA DPMS (Display

Power Management Signaling) Standard. The

DPMS states are:

H V Power Management State

Active Active Normal Operation

Inactive Active Standby (Quick Recovery) Opt

Active Inactive Suspend (Max Power Savings)

Inactive Inactive Off (Autorecovery is optional)

0 HSYNC Data

If bit-1 of this register is programmed to 1,

the state of this bit (XR73[0]) will be output

on HSYNC (pin 65).

1 HSYNC Control

Determines whether bit-0 of this register or

internal CRTC horizontal sync information

is output on HSYNC (pin 65).

0CRTC HSYNC is output (Default)

1XR73[0] is output

2 VSYNC Data

If bit-3 of this register is programmed to 1,

the state of this bit (XR73[2]) will be output

on VSYNC (pin 64).

3 VSYNC Control

Determines whether bit-2 of this register or

internal CRTC vertical sync information is

output on VSYNC (pin 64).

0CRTC VSYNC is output (Default)

1XR73[2] is output

7-4 Reserved (0)

DPMS CONTROL REGISTER (XR73)

Read/Write at I/O Address 3D7h

Index 73h

D7 D6 D5 D4 D3 D2 D1 D0

HSYNC Data

HSYNC Control

VSYNC Data

VSYNC Control

Reserved (0)

DIAGNOSTIC REGISTER (XR7D) (65545 Only)

Read/Only at I/O Address 3D7h

Index 72h

D7 D6 D5 D4 D3 D2 D1 D0

6-0 Reserved (0)

7BitBLT Clock Control ( 65545 Only )

0BitBLT logic receives a continuous

running memory clock

1The clock to the BitBLT logic is shut

off

Reserved (0)

BitBLT Clock Control

Extension Registers

Revision 1.2 153 65540 / 545

This I/O address is mapped to the same register as

I/O address 3D9h. This alternate mapping effec-

tively provides a color select register for Hercules

mode. Writes to this register will change the copy at

3D9h. The copy at 3D9h is visible only in CGA

emulation or when the extension registers are

enabled. The copy at XR7E is visible when the

extension registers are enabled.

5-0 See Register 3D9

7-6 Reserved (0)

DIAGNOSTIC REGISTER (XR7F)

Read/Write at I/O Address 3D7h

Index 7Fh

03-State Control Bit 0

0Normal outputs (default on reset)

13-state system bus and display output

pins: HSYNC, VSYNC, FLM, LP,

M, SHFCLK, P0-15, LDEV#, and

LRDY#.

13-State Control Bit 1

0Normal outputs (default on reset)

13-state memory output pins: RASA#,

RASB#, RASC#, CASAL#,

CASAH#, CASBL#, CASBH#,

CASCL#, CASCH#, WEA#, WEB#,

WEC#, OEAB#, OEC#, AA0-9, and

CA0-9.

5-2 Test Function

These bits are used for internal testing of the

chip when bit-6 = 1.

6Test Function Enable

This bit enables bits 5-2 for internal testing.

0Disable test function bits (default)

1Enable test function bits

7Special Test Function

This bit is used for internal testing and

should be set to 0 (default to 0 on reset) for

normal operation.

D7 D6 D5 D4 D3 D2 D1 D0

3-State Control

Test Function

Test Function Enable

Special Test Function

CGA / HERC COLOR SELECT REGISTER (XR7E)

Read/Write at I/O Address 3D7h

Index 7Eh

D7 D6 D5 D4 D3 D2 D1 D0

Color Bit-0 (Blue)

Color Bit-1 (Green)

Color Bit-2 (Red)

Color Bit-3 (Intensity)

Intensity Enable

Color Set Select

Reserved (0)

Extension Registers

Revision 1.2 154 65540 / 545

Revision 1.2 155 65540 / 545

32-Bit Registers

MnemonicGroup Register Name Access Type Address Reset Page

DR00 BitBLT BitBLT Offset 16/32-bit R/W 83D0-3 - - - - x x x x x x x x x x x x - - - - x x x x x x x x x x x x 156

DR01 BitBLT BitBLT Pattern ROP 16/32-bit R/W 87D0-3 - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x 156

DR02 BitBLT BitBLT BG Color 16/32-bit R/W 8BD0-3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 157

DR03 BitBLT BitBLT FG Color 16/32-bit R/W 8FD0-3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 157

DR04 BitBLT BitBLT Control 16/32-bit R/W 93D0-3 - - - - - - - - - - - 0 x x x x x x x x x x x x x x x x x x x x 158

DR05 BitBLT BitBLT Source 16/32-bit R/W 97D0-3 - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x 159

DR06 BitBLT BitBLT Destination 16/32-bit R/W 9BD0-3 - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x 159

DR07 BitBLT BitBLT Command 16/32-bit R/W 9FD0-3 - - - - 0 0 0 0 0 0 0 0 0 0 0 0 - - - - x x x x x x x x x x x x 160

DR08 Cursor Cursor Control 16/32-bit R/W A3D0-3 - - - - - - - - - - - - - - - - • • • • 0 0 0 0 0 0 0 • • • 0 0 161

DR09 Cursor Cursor Color 0-1 16/32-bit R/W A7D0-3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 162

DR0A Cursor Cursor Color 2-3 16/32-bit R/W ABD0-3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 162

DR0B Cursor Cursor Position 16/32-bit R/W AFD0-3 x - - - - x x x x x x x x x x x x - - - - x x x x x x x x x x x 163

DR0C Cursor Cursor Base Address 16/32-bit R/W B3D0-3 - - - - - - - - - - - - x x x x x x x x x x - - - - - - - - - - 164

32-Bit Registers

( 65545 Only )

Reset Codes: x = Not changed by RESET (indeterminate on power-up) – = Not implemented (always reads 0)

d = Set from the corresponding pin on falling edge of RESET • = Not implemented (read/write, reset to 0)

h = Read-only Hercules Configuration Register Readback bits 0/1 = Reset to 0 or 1 by falling edge of RESET

r = Chip revision # (starting from 0000)

BitBLT OFFSET REGISTER (DR00)

Write at I/O Address 83D0–83D3h

Read at I/O Address 83D0–83D3h

Word or DoubleWord Accessible

11–0 Source Offset

This value is added to the start address of the

Source BitBLT to calculate the starting

position for the next line.

15–12 Reserved (0)

27–16 Destination Offset

This value is added to the start address of the

Destination BitBLT to calculate the starting

position for the next line.

31–28 Reserved (0)

3128 27 16 1512 11 0

32-Bit Registers

Revision 1.2 156 65540 / 545

Source Offset

Reserved (0)

Destination Offset

Reserved (0)

BitBLT PATTERN ROP REGISTER (DR01)

Write at I/O Address 87D0–87D3h

Read at I/O Address 87D0–87D3h

Word or DoubleWord Accessible

20–0 Pattern Pointer

Address of Pattern Size - aligned 8 Pixel x 8

line pattern. For an 8BPP pattern

(occupying 8 bits / pixel * 8 pixels / line * 8

lines / pattern) the pattern must be aligned on

a 64 byte (16 DWord) boundary. For a

16BPP pattern (occupying 16bits / pixel * 8

pixels / line * 8 lines / pattern) the pattern

must be aligned on a 128byte (32 DWord)

boundary. For monochrome patterns (1 Bit

/ pixel * 8 pixels / line * 8 lines / pattern) the

pattern must be aligned on an 8 byte (2

DWord) boundary. The lower bits of the

Pattern Pointer are read/write, however the

Drawing Engine forces them to zero for

drawing operations.

31–21 Reserved (0)

31 21 20 0

Pattern Pointer

Reserved (0)

Warning: Do not read t his egister

while a BitBLT is active.

BitBLT BACKGROUND COLOR

Write at I/O Address 8BD0–8BD3h

Read at I/O Address 8BD0–8BD3h

Word or DoubleWord Accessible

15–0 Background Color

This register contains the background color

data used during opaque mono-color expan-

sions.

All 16 bits must be written regardless of

pixel depth. If the drawing engine is

operating at 8BPP, then the same data

should be duplicated in bits 31:24, 23:16,

15:8, and 7:0. For 16BPP the data is dupli-

cated twice.

31–16 Duplicate of 15-0

31 0

32-Bit Registers

Revision 1.2 157 65540 / 545

Background Color

BitBLT FOREGROUND COLOR

Write at I/O Address 8FD0–8FD3h

Read at I/O Address 8FD0–8FD3h

Word or DoubleWord Accessible

15–0 Foreground / Solid Color

This register contains the color data used

during solid paint operations. It also is used

as the foreground color during mono-color

expansions.

All 16 bits must be written regardless of

pixel depth. If the drawing engine is

operating at 8BPP, then the same data

should be duplicated in bits 31:24, 23:16,

15:8, and 7:0. For 16BPP the data is dupli-

cated twice.

31–16 Duplicate of 15-0

31 0

Foreground Color

Warning: Only bits 15-0 are used. They are

duplicated in bits 31-16 when this

Warning: Only bits 15-0 are used. They are

duplicated in bits 31-16 when this

7–0 ROP

Raster Operation as defined by Microsoft

Windows. All logical operations of Source,

Pattern, and Destination Data are supported.

8INC_Y

Determines BitBLT Y-direction:

0Decrement (Bottom to Top)

1Increment (Top to Bottom)

9INC_X

Determines BitBLT X-direction:

0Decrement (Right to Left)

1Increment (Left to Right)

10 Source Data

Selects variable data or color register data:

1Source is FG Color Reg (DR03)

0Source data selected by DR04[14]

11 Source Depth

Selects between monochrome and color

source data. This allows BitBLTs to either

transfer source data directly to the screen or

perform a font expansion (INC_X=1 only):

0Source is Color

1Source is Mono (Font expansion)

32-Bit Registers

Revision 1.2 158 65540 / 545

BitBLT CONTROL REGISTER (DR04)

Write at I/O Address 93D0–93D3h

Read at I/O Address 93D0–93D3h

Word or DoubleWord Accessible

12 Pattern Depth

Selects between monochrome and color

pattern data. This allows the pattern register

to operate either as a full pixel depth 8x8

pattern for use by the ROP, or as an 8x8

monochrome pattern:

0Pattern is Color

1Pattern is Monochrome

13 Background

The 65540 / 545 supports both transparent

and opaque backgrounds for monochrome

patterns and font expansion:

0BG is Opaque (BG Color Reg DR02)

1BG is Transparent (Unchanged)

15–14 BitBLT Source / Destination

The 65540 / 545 only supports its local

display memory as the destination for

BitBLT operations. The source may be

either display memory or system memory

(CPU):

15 14 BitBLT Source ––> Dest

0 0 Screen ––> Screen (Dest)

0 1 System ––> Screen (Dest)

1 0 Reserved

1 1 Reserved

18–16 Pattern Seed

Determines the starting row of the 8x8

pattern for the current BitBLT. A pattern is

typically required to be destination aligned.

The 65540 / 545 can determine the x-

alignment from the destination address

however the y-alignment must be generated

by the programmer. These three bits

determine which row of the pattern is output

on the first line of the BitBLT. Incrementing

and decrementing are controlled by bit

DR04[8].

19 Solid Pattern

1 = Solid Pattern (Brush)

0 = Bitmap Pattern

20 BitBLT Status ( Read Only )

0BitBLT Engine Idle

1BitBLT Active - do not write BitBLT

regs

23–21 Reserved (0)

27–24 Buffer Status

# of DWords that can be written to the chip:

0000 Buffer Full

0001 1 Space available in the queue

... ...

1111 15 Spaces available in the queue

31–25 Reserved (0)

3127 23 20 1916 15 8 7 0

ROP

INC_X, INC_Y

Source Data

Source Depth

Pattern Depth

Background

BitBLT Src/Dst

Pattern Seed

Solid Pattern

BitBLT Status

Reserved (0)

Buffer Status

Reserved (0)

BitBLT SOURCE REGISTER (DR05)

Write at I/O Address 97D0–97D3h

Read at I/O Address 97D0–97D3h

Word or DoubleWord Accessible

20–0 Source Address

Address of Byte aligned source block.

31–21 Reserved (0)

31 21 20 0

32-Bit Registers

Revision 1.2 159 65540 / 545

Source Address

Reserved (0)

BitBLT DESTINATION REGISTER (DR06)

Write at I/O Address 9BD0–9BD3h

Read at I/O Address 9BD0–9BD3h

Word or DoubleWord Accessible

20–0 Destination Address

Address of Byte aligned destination block.

31–21 Reserved (0)

31 21 20 0

Destination Addr

Reserved (0)

Warning: Do not read this register

while a BitBLT is active.

Warning: Do not read this register

while a BitBLT is active.

11–0 Bytes Per Line

Number of bytes to be transferred per line

15–12 Reserved (0)

27–16 Lines Per Block

Height in lines of the block to be transferred

31–28 Reserved (0)

32-Bit Registers

Revision 1.2 160 65540 / 545

BitBLT COMMAND REGISTER (DR07)

Write at I/O Address 9FD0–9FD3h

Read at I/O Address 9FD0–9FD3h

Word or DoubleWord Accessible

3128 27 16 1512 11 0

Bytes per Line

Reserved (0)

Lines per Block

Reserved (0)

Warning: Do not attempt to perform a CPU

read/write to display memory while a

BitBLT is active.

CURSOR/POP-UP CONTROL REGISTER (DR08)

Write at I/O Address A3D0–A3D3h

Read at I/O Address A3D0–A3D3h

Word or DoubleWord Accessible

1-0 Cursor / Pop-Up Menu Enable

This bit enables the hardware cursor. The

cursor will be enabled/disabled in the frame

following the current active frame

(synchronized to vertical blank).

00 Both Disabled

01 32x32 Cursor Enable

10 64x64 Cursor Enable

11 Pop-Up Menu Enable

4–2 Reserved (R/W)

Must be programmed to 0.

5Upper Left Corner ( ULC ) Select

The cursor is set relative to either the Upper

Left Corner (ULC) of the active display or

of the overscan region. When set relative to

the active display (BLANK#) the cursor will

not be visible in the overscan area. When

relative to Display Enable, the cursor may

appear in the overscan region. All x,y

positioning is relative to the selected ULC.

0ULC is BLANK# (x=0, y=0 corre-

sponds to the top left of the panel)

1ULC is Display Enable (x=0, y=0

corresponds to the top left of the

image)

31 16 1512 1110 9 8 7 6 5 4 2 1 0

32-Bit Registers

Revision 1.2 161 65540 / 545

Cursor Enable

Resrvd (must be 0)

ULC Select

Test

Pop-up Width

X Zoom

Y Zoom

Auto Zoom

Reserved (R/W)

Reserved (0)

7-6 Test

8Pop-Up Menu Width

0One bpp. Menu width = 128 pixels.

This also forces a height of 128 lines.

CC0 and CC1 (DR09) determine

menu colors.

1Two bpp. Menu width = 64 pixels.

CC0-3 (DR09 and DR0A) determine

menu colors.

9X Zoom (Manual)

0No pixel replication.

1Replicate pixels in the horizontal

direction. No pixel replication takes

place in CRT interlace mode and for

32x32 cursor.

10 Y Zoom (Manual)

0No pixel replication.

1Replicate pixels in the vertical

direction. No pixel replication takes

place in CRT mode and for 32x32

cursor.

11 Auto Zoom

0Auto zoom off

1Replicate pixels in high resolution

modes. No pixel replication takes

place in CRT interlace mode and for

32x32 cursor.

15–12 Reserved (R/W)

31–16 Reserved (0)

Refer to the Functional Description section of this

document for additional information on

programming of the Hardware Cursor feature.

CURSOR/POP-UP COLOR 0-1 REGISTER (DR09)

Write at I/O Address A7D0–A7D3h

Read at I/O Address A7D0–A7D3h

Word or DoubleWord Accessible

Cursor Colors 0 and 1 are 16-bit high color values

consisting of 5 bits of Red, 6 bits of Green, and 5

bits of Blue. Colors 0 and 1 may be accessed either

as two 16-bit registers or as a single 32-bit register.

A write to this register immediately affects the cursor

color displayed.

4–0 CC0 - Blue

Cursor Color 0 Blue value

10–5 CC0 - Green

Cursor Color 0 Green value

15–11 CC0 - Red

Cursor Color 0 Red value

20–16 CC1 - Blue

Cursor Color 1 Blue value

26–21 CC1 - Green

Cursor Color 1 Green value

31–27 CC1 - Red

Cursor Color 1 Red value

31 27 26 21 20 16 15 11 10 5 4 0

32-Bit Registers

Revision 1.2 162 65540 / 545

CC0 - Blue

CC0 - Green

CC0 - Red

CC1 - Blue

CC1 - Green

CC1 - Red

CURSOR/POP-UP COLOR 2-3 REGISTER (DR0A)

Write at I/O Address ABD0–ABD3h

Read at I/O Address ABD0–ABD3h

Word or DoubleWord Accessible

Cursor Colors 2 and 3 are 16-bit high color values

consisting of 5 bits of Red, 6 bits of Green, and 5

bits of Blue. Colors 2 and 3 may be accessed either

as two 16-bit registers or as a single 32-bit register.

Colors 2 and 3 are only used when the Cursor is in

Pop-Up Mode. A write to this register immediately

affects the cursor color displayed.

4–0 CC2 - Blue

Cursor Color 2 Blue value

10–5 CC2 - Green

Cursor Color 2 Green value

15–11 CC2 - Red

Cursor Color 2 Red value

20–16 CC3 - Blue

Cursor Color 3 Blue value

26–21 CC3 - Green

Cursor Color 3 Green value

31–27 CC3 - Red

Cursor Color 3 Red value

31 27 26 21 20 16 15 11 10 5 4 0

CC2 - Blue

CC2 - Green

CC2 - Red

CC3 - Blue

CC3 - Green

CC3 - Red

CURSOR/POP-UP POSITION REGISTER (DR0B)

Write at I/O Address AFD0–AFD3h

Read at I/O Address AFD0–AFD3h

Word or DoubleWord Accessible

10–0 X Offset

Cursor X-position. The cursor position is

calculated as the signed offset (in pixels)

between the Upper Left Corner (ULC) of the

screen (as defined by BLANK#) and the

Upper Left Corner of the cursor. X Offset

is the magnitude portion of the signed offset

of the cursor position in the horizontal axis.

This magnitude in combination with the X

SIGN bit (15) form the signed offset of the

cursor in the X direction.

The X OFFSET and X SIGN may be

written as a 16-bit quantity with bits 14-11

ignored.

The range for the ULC of the cursor is:

–2047 <= X-Position <= 2047

14–11 Reserved (0)

15 X Sign

Sign associated with the X OFFSET

magnitude which together form the signed

offset of the cursor in the X direction.

3130 27 26 16 1514 11 10 0

32-Bit Registers

Revision 1.2 163 65540 / 545

X Offset

Reserved (0)

X SIGN

Y Offset

Reserved (0)

Y SIGN

26–16 Y Offset

Cursor Y-position. The cursor position is

calculated as the signed offset (in pixels)

between the Upper Left Corner (ULC) of the

screen (as defined by BLANK#) and the

Upper Left Corner of the cursor. Y Offset is

the magnitude portion of the signed offset of

the cursor position in the vertical axis. This

magnitude in combination with the Y SIGN

bit (31) form the signed offset of the cursor

in the Y direction.

The Y OFFSET and Y SIGN may be written

as a 16-bit quantity with bits 30-27 ignored.

The range for the ULC of the cursor is:

–2047 <= Y-Position <= 2047

30–27 Reserved (0)

31 Y Sign

Sign associated with the Y OFFSET

magnitude which together form the signed

offset of the cursor in the Y direction.

In pop-up menu mode negative values are

not supported.

CURSOR/POP-UP BASE ADDRESS (DR0C)

Write at I/O Address B3D0–B3D3h

Read at I/O Address B3D0–B3D3h

Word or DoubleWord Accessible

9–0 Reserved (0)

19–10 Base Address

Base address for cursor / pop-up data in

display memory. Bit 10 (address lsb)

should be programmed to 0 when the

128x128 pop-up menu is being displayed.

Defines a byte address in display memory as

seen by the CPU.

31–20 Reserved (0)

Refer to the Functional Description section of this

document for additional information on

programming of the Hardware Cursor feature.

31 20 19 10 9 0

32-Bit Registers

Revision 1.2 164 65540 / 545

Reserved (0)

Base Address

Reserved (0)

Functional Blocks

The 65540 / 545 contains 5 major functional blocks

including the standard VGA core (Sequencer,

Attribute controller, Graphics Controller, and CRT

Controller), a BitBLT engine (65545 only),

Hardware Cursor (65545 only), Palette DAC, and

Clock Synthesizer. There are also other subsystems

such as the bus and memory interfaces which are

transparent to both the user and software

programmer. While in standard VGA modes only

the VGA core, Palette DAC, and clock synthesizer

are active.

Bus Interface

Two major buses are directly supported by the 65540

and 65545: Industry Standard Architecture (ISA),

and VESA Local Bus (VL-Bus); the 65545 also

supports the PCI Bus. Direct interfaces to popular

80486DX, 80486DX2, 80486SX, and 80386DX

processors are supported by both chips. Connection

to 16-bit PI bus and other 32-bit system buses such

as EISA and Micro Channel (MC) are possible with

external logic but are not inherently supported.

ISA Interface

The 65540 / 545 operates as a 16-bit slave device on

the ISA bus. It maps its display memory into the

standard VGA address range (0A0000-0BFFFFh).

The VGA BIOS ROM is decoded in the 32KByte

space at 0C0000-0C7FFFh (an output is available on

the ROMCS# pin for ROM chip selection). Address

lines LA23:17 are required for decoding MEMCS16#

hence these addresses are latched internally by ALE.

The remaining addresses (SA16:0) are accepted from

the system without internal latching. The 65540 /

545 supports 16-bit memory and I/O cycles.

Whenever possible the 65540 / 545 executes zero

wait state memory cycles by asserting ZWS#. It

does not generate MEMCS16# or ZWS# on ROM

accesses. Memory may be mapped as a single linear

frame buffer anywhere in the 16 MByte ISA memory

space on a 512K/1MByte boundary (depending on

the amount of display memory installed - see

XR0B[4]). The 16-bit bus extension signals

MEMR# and MEMW# are used for memory control

since mapping above the 1MByte boundary is

permitted. For ISA compatibility the IRQ pin

operates as an active high level-triggered interrupt.

VL-Bus Interface

The 65540 / 545 operates as a 32-bit target on the

VL-Bus. It has an optimized direct pin-to-pin

connection for all VL-Bus signals to eliminate

external components. Up to 28 bits of the 32-bit VL-

Bus address may be decoded on-chip permitting

location of the linear frame buffer anywhere in a

256MByte address space. Optionally, the upper 4

address bits may be decoded externally to support the

full 32-bit, 4GB VL-Bus address space. Zero wait

state read accesses are not permitted, however, the

65540 / 545 will terminate a read cycle in the second

T2 if the data is available. Burst cycles are not

supported.

Direct Processor Interface

The 65540 / 545 can interface directly to all 32-bit

x86-architecture processors. Its full non-multiplexed

28-bit address makes it simple to connect to the

CPU. On valid 65540 / 545 accesses it will generate

LDEV# which is monitored by the system logic

controller. This interface is essentially the same as

the VL-Bus interface with the exception that both 1x

and 2x CPU clocks are acceptable. When using a 2x

clock the CPU Reset must be connected to the 65540

/ 545 CRESET input for phase coherency. The

65540 / 545 does not support pipelined mode in its

386 processor interface.

PCI Interface

The 65545 also supports a full 32-bit PCI bus

interface as defined by PCI Interface Specification

Revision 2.0. All features required of a non-bus-

master 'target' device are implemented on-chip with

no external glue logic required. Read/Write cycles

are supported for Memory, I/O, and Configuration

address spaces. Burst accesses are not supported.

Interrupt capability is provided for vertical interrupts.

Refer to the PCI Pin Descriptions and Configuration

Registers sections for further information.

Functional Description

Revision 1.2 165 65540 / 545

System Interface

Memory Architecture

The 65540 / 545 supports both 512K and 1MB

configurations for display memory plus an additional

512K for an optional external frame buffer. Frame

buffering is required for support of simultaneous

display on CRTs and DD panels, however, the

65540 / 545 has the ability to embed frame buffer

data in display memory. Since this uses some of the

available memory bandwidth, the 65540 / 545 also

supports an additional DRAM for use as an external

frame buffer for improved performance.

The 65540 / 545 implements a 32-bit wide data bus

for display memory and 16-bit for the optional

external frame buffer. The memory data buses are

named 'A', 'B', and 'C' in groups of 16 bits. 'A'

holds the lower 512K of display memory, 'B'

normally holds the upper 512K of display memory in

1MB configurations and 'C' is normally used for the

external frame buffer (if used). The chip may,

however, be optionally programmed to put the upper

half of display memory in DRAM 'C' instead (i.e.,

'C' may be programmed to hold either display

memory or external frame buffer data). When an

external frame buffer is not required, 'C' may also be

used as an input port for external video data (to

implement overlay of live video over VGA output for

example) and to provide additional panel interface

data bits beyond the basic 16 (for TFT panels with

18-bit or 24-bit data interfaces since TFT panels are

single panels and never require frame buffering).

There are separate groups of RAS, CAS, and WE

pins for each of the three DRAMs (A, B, and C).

There are only two OE pins and two address buses

however, one for A and B and another for C.

Configuration initialization data is latched from

memory address pins AA0-8 (the address bus for

DRAMs A and B) at the end of reset. These bits are

readable in XR01[0-7] and XR6C[1] respectively.

The 65540 and 65545 support all VGA text and

graphics modes (planar, packed pixel, odd/even

chain modes, etc.) but the storage locations of the

data (i.e., the locations and bit positions in the

DRAMs) does not correspond to the original VGA

which implemented 256KB of display memory as 4

physical 'planes' of 64KB (using two 64Kx4

DRAMs to implement each 'plane' with separate

address buses for planes 0-1 and 2-3). In other

words, no assumptions should be made regarding

the correspondence of the data pins on the display

memory data bus of the 65540 / 545 to traditional

VGA 'plane' concepts. For example, text data is still

stored in 'plane' 0, attribute data in 'plane' 1, and

font data in 'plane' 2, but due to the extensive use of

page-mode cycles and the use of a single address bus

for display memory data, where those planes are

physically located in the DRAMs is much different.

In addition, the 65540 / 545 make extensive use of

internal FIFOs to improve performance. As a result

the read / write activity on the DRAM interface pins

at any point in time corresponds only approximately

to system bus and CRT / panel output activity at that

time.

Memory Chip Requirements

The 65540 / 545 is designed to use 256K x 4 or

256K x 16 DRAMs. Fast-page-mode capability is

required. Either 'CAS-Before-RAS' or 'Self-

Refresh' DRAMs may be used. Both dual-CAS#

(default) and dual-WE# types of 256Kx16 DRAMs

are supported. DRAMs with 'symmetrical' address

inputs (A0-8) are supported by default, but the chip

can be configured to support 'asymmetrical' address

(A0-9) DRAMs. The BIOS can test the DRAMs to

detect the type of DRAM used and program the chip

accordingly.

The 65540 / 545 can generate Page Mode Read, Page

Mode Write, and Page Mode Read-Modify-Write

cycles. CAS-before-RAS Refresh and Self-Refresh

cycles are also supported. The memory interface is

optimized for 40ns page mode cycles but is flexible

and can be tuned for any speed DRAM.

The 65540 / 545 supports various DRAM speeds.

The maximum frequency of the 65540 / 545 is 75

MHz. The recommended maximum memory clock

frequency for various DRAM based on commonly

available DRAM specifications is as follows:

DRAM Speed Memory Clock Frequency*

100 ns 50.000 MHz

80 ns 57.000 MHz

70 ns 65.000 MHz

* DRAM AC timing parameters varies among

different DRAM manufacturers therefore please

check with DRAM specifications and 65540 / 545

memory timing.

Functional Description

Revision 1.2 166 65540 / 545

Display Memory Interface

Functional Description

Revision 1.2 167 65540 / 545

÷N

÷4M

Phase

Detector Charge

Pump VCO

Internal

Loop Filter

post-VCO divider select

Phase-Locked Loop Oscillator

Reference 7PSN ÷2P

XR30[0]

XR30[3:1]

XR31[6:0]

XR32[6:0]

CLK

Clock Synthesizer

Clock Synthesizer PLL Block Diagram

VGA CLK0 = 25.175MHz

VGA CLK1 = 28.322MHz

CLK2 = Programmable

MCLK = Programmable

XR32:30

MISC Output Reg[3:2]

CLKSEL1:0

VCLK Synthesizer

MCLK Synthesizer

VCLK Register Table

MCLK Register Table

An integrated clock synthesizer supports all pixel

clock (VCLK) and memory clock (MCLK)

frequencies which may be required by the 65540 /

545. Each of the two clock synthesizer phase lock

loops may be programmed to output frequencies

ranging between 1MHz and the maximum specified

operating frequency for that clock in increments not

exceeding 0.5%. The frequencies are generated by

an 18-bit divisor word. This value contains divisor

fields for the Phase Lock Loop (PLL), Voltage

Controlled Oscillator (VCO) and Pre/Post Divide

Control blocks. The divisor word for both

synthesizers is programmable via Clock Control

Registers XR30-32.

MCLK Operation

Normal operational frequencies for MCLK are

between 50MHz and 68MHz. Refer to the Electrical

Specifications for maximum frequencies at 3.3V and

5V (the maximum frequency at 3.3V will be slightly

lower). Normal MCLK operational frequencies are

defined by the display memory sequencer parameters

described in the Memory Timing section. The

frequency selected is also dependent upon the AC

characteristics of the display memories connected to

the 65540 / 545. A typical match is between industry

standard 70ns access memories and a 65MHz

MCLK. The MCLK output defaults to 60MHz on

reset and is fully programmable. This initial value is

conservative enough not to violate slow DRAM

parameters but not so slow as to cause a system

timeout on CPU accesses. The MCLK frequency

must always equal or exceed the host clock (CCLK)

frequency.

Clock Synthesizer Register Structure

VCLK Operation

The VCLK output typically ranges between 19MHz

and 65MHz. VCLK has a table of three frequencies

from which to select a frequency. This is required

for VGA compatibility. CLK0 and CLK1 are fixed

at the VGA compatible frequencies of 25.175MHz

and 28.322MHz respectively. These values can not

be changed unlike CLK2 which is fully program-

mable. The active frequency is chosen by clock

select bits MSR[3:2].

Programming the Clock Synthesizer

The desired output frequency is defined by an 18-bit

value programmed in XR30-32. The 65540 / 545 has

two programmable clock synthesizers; one for

memory (MCLK) and one for video (VCLK). They

are both programmed by writing the divisor values to

XR30-32. The clock to be programmed is selected

by the Clock Register Program Pointer XR33[5].

The output frequency of each of the clock synthe-

sizers is based on the reference frequency (FREF) and

the 4 programmed fields:

Field # Bits

Prescale N (PSN) XR30[0] (÷1 or ÷4)

M counter (M') XR31[6:0] (M' = M - 2)

N counter (N’) XR32[6:0] (N' = N - 2)

Post Divisor (P) XR30[3:1] (÷2P; 0 ≤ P ≤ 5)

FOUT =

The frequency of the Voltage Controlled Oscillator

(FVCO) is determined by these fields as follows:

FVCO =

where FREF = Reference frequency (between 4 MHz

- 20 MHz; typically 14.31818 MHz)

Note: If a reference frequency other than 14.31818

MHz is used, then the frequencies loaded on

RESET will not be correct.

PPost Divisor

000 1

001 2

010 4

011 8

100 16

101 32

Programming Constraints

There are five primary programming constraints the

programmer must be aware of:

4 MHz ≤ FREF ≤ 20 MHz

150 KHz ≤ FREF/(PSN * N) ≤ 2 MHz

48 MHz < FVCO ≤ 220 MHz

3 ≤ M ≤ 127

3 ≤ N ≤ 127

The constraints have to do with trade-offs between

optimum speed with lowest noise, VCO stability,

and factors affecting the loop equation.

The value of FVCO must remain between 48 MHz

and 220 MHz inclusive. Therefore, for output

frequencies below 48 MHz, FVCO must be brought

into range by using the post-VCO Divisor.

To avoid crosstalk between the VCO's, the VCO

frequencies should not be within 0.5% of each other

nor should their harmonics be within 0.5% of the

other's fundamental frequency.

The 65540 / 545 clock synthesizers will seek the

new frequency as soon as it is loaded following a

write to XR32. Any change in the post-divisor will

take affect immediately. There is a possibility that

the output may glitch during this transition of post

divide values. Because of this, the programmer may

wish to hold the post-divisor value constant across a

range of frequencies (eg. changing MCLK from the

reset value of 50MHz to 72MHz). There is also the

consideration of changing from a low frequency

VCO value with a post-divide ÷1 (eg. 50MHz) to a

high frequency ÷4 (eg. 220MHz). Although the

beginning and ending frequencies are close together,

the intermediate frequencies may cause the 65540 /

545 to fail in some environments. In this example

there will be a short-lived time frame during which

the output frequency will be in the neighborhood of

12.5MHz. The bus interface may not function

correctly if the MCLK frequency falls below a

certain value. Register and memory accesses which

are synchronized to MCLK may be so slow as to

violate bus timing and cause a watchdog timer error.

Programmers should time-out the system (CPU) for

approximately 10ms after writing XR32 before

accessing the VGA again. This will ensure that

accesses do not occur to the VGA while the clocks

are in an indeterminate state.

Note: On reset the MCLK is initialized to a 60MHz

output with a post divisor = 2 (FVCO = 120MHz).

Functional Description

Revision 1.2 168 65540 / 545

FREF * 4 * M

PSN * N * 2P

FREF * 4 * M

PSN * N

Programming Example

The following is an example of the calculations

which are performed:

Derive the proper programming word for a 25.175

MHz output frequency using a 14.31818 MHz refer-

ence frequency:

Since 25.175 MHz < 48 MHz, double it to 50.350

MHz to get FVCO in its valid range. Set the post

divide field (P) to 001.

Prescaling PSN = 4

The result:

FVCO = 50.350 = (14.31818 x 4 x M/4 x N)

M/N = 3.51655

Several choices for M and N are available:

M N FVCO Error

109 31 50.344 -0.00300

102 29 50.360 +0.00500

Choose (M, N) = (109,31) for best accuracy.

Prescaling PSN = 1

The result:

FVCO = 50.350 = (14.31818 x 4 x M/1 x N)

M/N = 0.879127

M N FVCO Error

80 91 50.349 -0.00050

FREF/(PSN x N) = 157.3KHz

Therefore M/N = 80/91 with PSN = 1 is even better

than with PSN = 4.

XR30 = 0000010b (02h)

XR31 = 80 - 2 = 78 (4Eh)

XR32 = 91 - 2 = 89 (59h)

PCB Layout Considerations

Clock synthesizers, like most analog components,

must be isolated from the digital noise which exists

on a PCB power plane. Care must be taken not to

route any high frequency digital signals in close

proximity to the analog sections. Inside the

65540/545, the clocks are physically located in the

lower left corner of the chip surrounded by low

frequency input and output pins. This helps

minimize both internally and externally coupled

noise.

The memory clock and video clock power pins on

the 65540/545 each require similar RC filtering to

isolate the synthesizers from the VCC plane and

from each other. The filter circuit for each CVCCn /

CGNDn pair is shown below:

The suggested method for layout assumes a multi-

layer board including VCC and GND planes. All

ground connections should be made as close to the

pin / component as possible. The CVCC trace

should route from the 65540/545 through the pads of

the filter components. The trace should NOT be

connected to the filter components by a stub. All

components (particularly the initial 0.1µF capacitor)

should be placed as close as possible to the

65540/545.

CGNDn

CVCCn

GND

10Ω

47µF0.1µF 0.1µF

+5V

Functional Description

Revision 1.2 169 65540 / 545

A19

A20

A21

A22

CGND0

XTALI

XTALO

CVCC0

CVCC1

RESET#

CGND1

C1 C3

GND

VCC

GND

NOTE: Do

not connect

Vcc here.

Force the

trace

through the

decoupling

cap pad.

Always pass the Vcc trace through the decoupling cap pad. Do not leave a stub as shown here.

Designator Value

C1,C3,C4,C6,C7 0.1µF

C2,C5 47µF

R1,R2 10Ω

The 65540 / 545 integrates a VGA compatible triple

6-bit lookup table (LUT) and high speed 6/8-bit

DACs. Additionally the internal color palette DAC

supports true-color bypass modes displaying color

depths up to 24bpp (8-8-8). The palette DAC can

switch between true-color data and LUT data on a

pixel by pixel basis. Thus, video overlays may be

any arbitrary shape and can lie on any pixel

boundary. The hardware cursor is also a true-color

bitmap which may overlay both video and graphics

on any pixel boundary.

The internal palette DAC register I/O addresses and

functionality are 100% compatible with the VGA

standard. In all bus interfaces the palette DAC

automatically controls accesses to its registers to

avoid data overrun. This is accomplished by holding

RDY in the ISA configuration and by delaying

LRDY# for VL-Bus and direct processor interfaces.

For compatibility with the VL-Bus Specification the

65540 / 545 may be disabled from responding to

palette writes (although it will perform them) so that

an adapter card on a slow (ISA) bus which is

shadowing the palette LUT may see the access. The

65540 / 545 always responds to palette read accesses

so it is still possible for the shadowing adapter to

become out of phase with the internal modulo-3

RGB pointer. It is presumed that this will not be a

problem with well-behaved software.

Extended display modes may be selected in the

Palette Control Register (XR06). Two 16bpp

formats are supported: 5-5-5 Targa format and 5-6-5

XGA format.

Functional Description

Revision 1.2 170 65540 / 545

VGA Color Palette DAC

Triple 6-bit

LUT

LUT Pixel Data

Red

Green

Blue

Hardware Cursor

External RGB Video

(565, 666, or 888)

High Color Pixel Data Triple

6/8-bit

DAC

VGA Color Palette DAC Data Flow

Bit Block Transfer

The 65545 integrates a Bit Block Transfer (BitBLT)

Engine which is optimized for operation in a

Microsoft Windows environment. The BitBLT

engine supports system-to-screen and screen-to-

screen memory data transfers. It handles

monochrome to color data expansion using either

system or screen data sources. Color depths of 8

and 16bpp are supported in the expansion logic.

Integrated with the screen and system BitBLT data

streams is a 3-operand raster-op (ROP) block. This

ROP block includes an independent 8x8 pixel (mono

or color) pattern. Color depths of 8 and 16bpp are

supported by the pattern array. All possible logical

combinations of Source (system or screen data),

Destination (screen data), and Pattern data are

available.

The BitBLT and ROP subsystems have been archi-

tected for compatibility with the standard Microsoft

Windows BitBLT parameter block. The source and

destination screen widths are independently program-

mable. This permits expansion of a compressed off-

screen bitmap transparent to the software driver. The

BitBLT Control Register (DR04) uses the same

raster-op format as the Microsoft Windows ROP so

no translation is required. All 256 Windows defined

ROPs are available.

All possible overlaps of source and destination data

are handled by controlling the direction of the

BitBLT in the x and y directions. As shown below

there are eight possible directions for a screen-to-

screen BitBLT (no change in position is a subset of

all eight). Software must determine the overlap, if

any, and set the INC_X and INC_Y bits accord-

ingly. This is only critical if the source and desti-

nation actually overlap. For most BitBLTs this will

not be the case. In BitBLTs where INC_X is a

'don't care' it should be set to 1 (proceed from left to

right). This will increase the performance in some

cases.

Functional Description

Revision 1.2 171 65540 / 545

BitBLT Engine ( 65545 only )

INC_X = X; INC_Y = 0 INC_X = X; INC_Y = 0

INC_X = 0; INC_Y = X INC_X = 1; INC_Y = X

INC_X = X; INC_Y = 1 INC_X = X; INC_Y = 1

INC_X = X; INC_Y = 1

INC_X = X; INC_Y = 0

Source

Dest

Source

Dest

Source Dest

Source

Dest

Source

Dest

Source

Dest

Source

Dest

Source

Dest

Arrows indicate

appropriate direction for

BitBLT progression so

that destination overlap

does not corrupt data.

Possible BitBLT Orientations With Overlap

Sample Screen-to-Screen Transfer

Below is an example of how a screen-to-screen

BitBLT operation is traditionally performed. The

source and destination blocks both appear on the

visible region of the screen and have the same

dimensions. The BitBLT is to be a straight source

copy with no raster operation. The memory address

space is 2MBytes and display resolution is 1024 x

768. The size of the block to be transferred is 276

horizontal x 82 vertical pixels (114h x 52h). The

coordinates of the upper left corner (ULC) of the

source block is 25h,30h. The ULC coordinates of

the destination block are 157h,153h. Because the

source and destination blocks do not overlap, the

INC_X and INC_Y BitBLT direction bits are not

important. We will assume that INC_X = 1,

INC_Y = 0, and the BitBLT will proceed one scan

line at a time from the lower left corner of the source

moving to the right and then from the bottom to the

top.

The source and destination offsets are both the same

as the screen width (400h):

BitBLT Offset Register (DR00) = 04000400h

The Pattern ROP Register does not need to be

programmed since there is no pattern involved.

Neither the Foreground Color nor Background Color

involve a color expansion or rectangle solid color

paint. The BitBLT Control Register contains the

most individual fields to be set:

ROP = Source Copy = 0CCh

INC_Y = 0 (Bottom to Top)

INC_X = 1 (Left to Right)

Source Data = Variable Data = 0

Source Depth = Source is Color = 0

Pattern Depth = Don't Care = 0

Background = Don't Care = 0

BitBLT = Screen-to-Screen = 00

Pattern Seed = Don't Care = 000

BitBLT Control Register (DR04) = 002CCh

Since the BitBLT will be starting in the lower left

corner (LLC) of the source rectangle, the start

address for the source data is calculated as:

Functional Description

Revision 1.2 172 65540 / 545

25h,30h114h

52h

400h (1024)

300h

(768)

157h,153h

26Ah, 1A4h

000000h

00C025h

054D57h

Dest

138h,81h

Source

00C025h

Line 1

Line 2

Line 3

Line 52h

1FFFFFh

00C425h

00C825h

00C538h

00C138h

00C938h

Source

Destination

020425h

020538h

2EDh

400h

1024 x 768 x 8BPP

0C0000h

Off-Screen

Memory

06926Ah

Screen-to-Screen BitBLT

(81h * 400h) + 25h = 020425h

BitBLT Source Register (DR05) = 020425h

Similarly, the LLC of the destination register calcu-

lated as:

(1A4h * 400H) + 157h = 069157h

BitBLT Destination Register (DR06) = 069157h

To begin any BitBLT the Command Register must be

written. This register contains key information about

the size of the current BitBLT which must be written

for all BitBLT operations:

Lines per Block = 52h

Bytes per line = 114h (Current example 8bpp)

Command Register (DR07) = 00520114h

After the Command Register (XR07) is written the

BitBLT engine performs the requested operation.

The status of the BitBLT operation may be read in

DR04[20] (read only bit). This is necessary to

determine when the BitBLT is finished so that

another BitBLT may be issued. No reads or writes

of the display memory by the CPU are permitted

while the BitBLT engine is active.

In the present example the BitBLT source and desti-

nation blocks have the same width as the display. As

can be seen below each scan line is transferred from

source to destination. Alignment is handled by the

BitBLT engine without assistance from software.

Compressed Screen-to-Screen Transfer

Next we consider an example of how a screen-to-

screen BitBLT operation is performed when the

source and destination blocks have different widths

(pitch). This type of BitBLT is commonly used to

store bitmaps efficiently in offscreen memory or

when recovering a saved bitmap from offscreen

memory.

The 65545 display memory consists of a single linear

frame buffer. The number of bytes per scan line and

lines displayed changes with resolution and pixel

depth. For simplification, the concepts of pixels,

Functional Description

Revision 1.2 173 65540 / 545

BitBLT Data Transfer

000000h

00C025h

054D57h

Dest

Source

00C025h

Line 1

Line 2

Line 3

Line 52h

1FFFFFh

00C425h

00C825h

00C538h

00C138h

00C938h

020425h

020538h

2EDh

400h

0C0000h

Off-Screen

Memory

069269h

000000h

00C025h

054D57h

Dest

Source

1FFFFFh

020538h

0C0000h

Off-Screen

Memory

069269h

054D57h Line 1

Line 2

Line 3

Line 52h

055157h

055557h

05526Ah

054E6Ah

05566Ah

069157h

06926Ah

lines, and columns are foreign to the BitBLT engine.

Instead, the 65545 operates on groups of bytes

(rows) which are separated by the width of the

screen. The 65545 permits separation between the

row lengths to be different for source and destination

bitmaps. For efficient use of offscreen memory we

may assume that the "width" of the screen is the

same as the width of the data.

Below is an example of how a screen-to-screen

BitBLT operation is performed with the destination

data efficiently compressed into the offscreen area.

The reverse operation is also valid to recreate the

original block on the visible screen. Once again the

BitBLT is to be a straight source copy with the

source block in the same location as the previous

example. The destination block is to be located

beginning at the first byte of off-screen memory.

Because the source and destination blocks do not

overlap the INC_X and INC_Y BitBLT direction bits

are not important. We will assume that INC_X = 1,

INC_Y = 1 and the BitBLT will proceed one scan

line at a time from the upper left corner of the source

moving to the right and then from the top to the

bottom.

The source offset is the same as the screen width

(400h) and the destination offset is the same as the

source block width (114h):

BitBLT Offset Register (DR00) = 01140400h

The Pattern ROP Register does not need to be

programmed since there is no pattern involved.

Neither the Foreground Color nor Background Color

color expansion. The BitBLT Control Register

contains the following bit fields:

ROP = Source Copy = 0CCh

INC_Y = 1 (Top to Bottom)

INC_X = 1 (Left to Right)

Source Data = Variable Data = 0

Source Depth = Source is Color = 0

Pattern Depth = Don't Care = 0

Background = Don't Care = 0

BitBLT = Screen --> Screen = 00

Functional Description

Revision 1.2 174 65540 / 545

Differential Pitch BitBLT Data Transfer

000000h

00C025h

Source

00C025h

Line 1

Line 2

Line 3

Line 52h

1FFFFFh

00C425h

00C825h

00C538h

00C138h

00C938h

020425h

020538h

2EDh

400h

0C0000h

Off-Screen

Memory

000000h

00C025h

Source

1FFFFFh

020538h

0C0000h

Off-Screen

Memory

0C0228h

Line 1

Line 2

Line 3

Line 52h

0C0000h

0C0227h

0C0113h

0C0114h

0C0336h

0C5754h

0C5867h

Source

Destination

Dest

Source

Dest

Pattern Seed = Don't Care = 000

BitBLT Control Register (DR04) = 003CCh

Since the BitBLT will be beginning in the ULC of

the source rectangle, the start address for the source

data is calculated as:

(30h * 400h) + 25h = 0C025h

BitBLT Source Register (DR05) = 0C025h

Similarly, the ULC of the destination register calcu-

lated as (Number of scan lines * Bytes per scan line):

300h * 400h = 0C0000h

BitBLT Destination Register (DR06) = 0C0000h

As in the previous example the Command Register

must be written to begin the BitBLT. This register

contains the size of the current BitBLT which must

be written for all BitBLT operations:

Lines per Block = 52h

Bytes per line = 114h (Current example 8bpp)

Command Register (DR07) = 00520114h

System-to-Screen BitBLTs

When performing a system-to-screen BitBLT the

source rotation information is passed in the BitBLT

Source Address and Source Offset registers. The 2

LSbits of the Source Address register indicate the

alignment. For example if the system data resides at

system address 0413456h then the processor pointer

should be set to 0413454h (doubleword aligned) and

the Source address register is written with xxxxx2h.

When the end of the scan line is reached (the number

of bytes programmed in the Command Register have

been written) any remaining bytes in the last

doubleword written to the 65545 are discarded. The

2 LSbits of the Source Offset Register are then added

to the 2 LSbits of the Source Address Register to

determine the starting byte alignment for the first

doubleword of the next scanline. This process is

continued until all scanlines are completed. The most

common case will be a doubleword aligned bitmap in

system memory in which case the 2 Lbits of the

Source Address Register are zero. It is also common

for bitmaps to be stored with each scanline

doubleword aligned (Source Offset Register =

xxxxx0h). Once the Command Register is written

and the BitBLT operation has begun the 65545 will

wait for data to be sent to its memory address space.

Any write to a valid 65545 memory address, either in

the VGA space or linear address space if enabled,

will be recognized as BitBLT source data and will be

routed to the correct address by the BitBLT engine.

This enables the programmer to set up a destination

pointer into the video address window (doubleword

aligned) and simply perform a REP MOVSD. Any

unused data in the last word/doubleword write will

be discarded by the BitBLT Engine.

For system-to-screen monochrome (font) expansions

the data is handled on a scanline by scanline basis.

As with the system-to-screen BitBLT with ROP, this

type of transfer uses the 2 LSbits of the source

address register to determine the beginning byte

index into the first doubleword. On subsequent

scanlines the source offset register is added to the

current scanline byte index to determine the indexing

for the start of the next scan line. Monochrome data

is taken from bit 7 through bit 0, byte 0 through 3

and expanded left to right in video memory (NOTE:

monochrome source only supports left to right

operation). At the end of the first scanline any

remaining data in the active doubleword is flushed

and the byte pointer for the starting byte in the next

doubleword (for the next scanline) is calculated by

adding 2 LSbits of the source offset to the starting

byte position in the previous scanline. Monochrome

expansion then continues bit 7 through 0 incre-

menting byte (after byte 3 bit 0 a new doubleword

begins at byte 0: bit 7) until the scanline is complete.

Note that the number of bytes programmed into the

Command register references the number of

expanded bytes written; not the number of bytes to

be expanded.

Functional Description

Revision 1.2 175 65540 / 545

Functional Description

Revision 1.2 176 65540 / 545

The 65545 supports four types of cursors:

32 x 32 x 2bpp (and/xor)

64 x 64 x 2bpp (and/xor)

64 x 64 x 2bpp (4-color)

128 x 128 x 1bpp (2-color)

The first two hardware cursor types indicated as

'and/xor' above follow the MS Windows™

AND/XOR cursor data plane structure which

provides for two colors plus 'transparent'

(background color) and 'inverted' (background color

inverted). The last two types in the list above are

also referred to as 'Pop-Ups' because they are

typically used to implement pop-up menu

capabilities. Hardware cursor / pop-up data is stored

in display memory, allowing multiple cursor values

to be stored and selected rapidly. The two or four

colors specified by the values in the hardware cursor

data arrays are stored in on-chip registers as high-

color (5-6-5) values independent of the on-chip color

lookup tables (i.e., Attribute Controller and VGA

Color Palette).

The hardware cursor can overlay either graphics or

video data on a pixel by pixel basis. It may be

positioned anywhere within screen resolutions up to

2048x2048 pixels. 64x64 'and/xor' cursors may

also be optionally doubled in size to 128 pixels either

horizontally and/or vertically by pixel replication.

Hardware cursor screen position, type, color, and

base address of the cursor data array in display

memory may be controlled via the 32-bit 'DR'

extension registers.

Hardware Cursor Programming

Once the 32-bit extension registers are enabled

(XR03[1]=1), the cursor registers (DR08-DR0C)

may be accessed. DR08 controls the cursor type and

X/Y zoom (H/V pixel replication). It also enables the

hardware cursor to appear on the screen. DR09 and

DR0A specify up to four 16-bit RGB (5-6-5) cursor

color values. DR0B specifies the cursor position on

screen in X-Y coordinates (number of pixels from

the left and top edges of the addressable portion of

the display). DR0C specifies the address in display

memory where the cursor data array is stored. A 10-

bit base address may be specified allowing cursor

data patterns to be stored in any of 1024 different

locations in the maximum 1MB of display memory.

Each cursor storage area takes up 1024 bytes of

display memory which is exactly large enough to

hold a 64x64x2 cursor pattern.

Cursor Data Array Format and Layout

Cursor data is stored in display memory as shown:

32x32 2bpp Cursor

Offset Line Plane 0 Plane 1 Plane 2 Plane 3

000h 0 A7-0 X7-0 A15-8 X15-8

004h 0 A23-16 X23-16 A31-24 X31-24

008h 1 A7-0 X7-0 A15-8 X15-8

00Ch 1 A23-16 X23-16 A31-24 X31-24

... ... ... ... ... ...

0FCh 31 A23-16 X23-16 A31-24 X31-24

64x64 2bpp Cursor / Pop-Up

Offset Line Plane 0 Plane 1 Plane 2 Plane 3

000h 0 A7-0 X7-0 A15-8 X15-8

004h 0 A23-16 X23-16 A31-24 X31-24

008h 0 A39-32 X39-32 A47-40 X47-40

00Ch 0 A55-48 X55-48 A63-56 X63-56

010h 1 A7-0 X7-0 A15-8 X15-8

014h 1 A23-16 X23-16 A31-24 X31-24

... ... ... ... ... ...

3FCh 63 A55-48 X55-48 A63-56 X63-56

128x128 1bpp Pop-Up

Offset Line Plane 0 Plane 1 Plane 2 Plane 3

000h 0 P7-0 P15-8 P23-16 P31-24

004h 0 P39-32 P47-40 P55-48 P63-56

008h 0 P71-64 P79-72 P87-80 P95-88

00Ch 0 P103-96 P111-104 P119-112 P127-120

010h 1 P7-0 P15-8 P23-16 P31-24

014h 1 P39-32 P47-40 P55-48 P63-56

... ... ... ... ... ...

7FCh 127 P103-96 P111-104 P119-112 P127-120

A7/X7 is the left-most pixel of the cursor pattern

displayed on the screen for all cursor types. Note

that 32x32 cursors take up 256 bytes each (the upper

3/4 of the 1KB space allocated for each cursor

storage location in display memory is unused).

128x128 cursors (pop-ups) take up 2KB each, so

require A10 of the base address to be set to 0.

Cursor data array elements map as follows:

Ann Xnn And/Xor Type 4-Color Type

0 0 Color 0 Color 0

0 1 Color 1 Color 1

1 0 Transparent Color 2

1 1 Inverted Color 3

where colors 0 and 1 are defined by DR09 and colors

2 and 3 are defined by DR0A. Each pixel in 2-color

(1bpp) cursors (pop-ups) may be either color 0 or

color 1.

Functional Description

Revision 1.2 177 65540 / 545

Hardware Cursor ( 65545 only )

Revision 1.2 178 65540 / 545

Display Memory Base Address Formation

The address bits in the cursor base address register

DR0C are aligned so they are in the proper position

corresponding to the CPU address required to write

to display memory. However, there are two

methods of addressing display memory, VGA-style

and 'Linear Frame Buffer' style, so the actual CPU

address for loading a cursor data array must be

constructed differently depending on the addressing

method used. If VGA addressing is used, the lower

16-bits of DR0C may be used as an offset into the

64KB VGA address space (starting at either

0A0000h or 0B0000h depending on whether the

VGA is set for text mode or graphics mode). DR0C

bits 16-19 would then be used to control the VGA's

paging mechanism to set the 64KB CPU aperture

into display memory to the correct location for

storing the cursor pattern (see XR0B, XR10, and

XR11). If 'linear frame buffer' addressing is used,

the entire 1MB of display memory can be accessed

directly and the base value in DR0C may be used

directly as a 24-bit offset into a programmable 1MB

space in system memory (specified in the Linear

Addressing Base register XR08).

VGA Controller Programming

In order to copy the cursor data pattern to the

controller, the VGA controller must be properly

programmed for 32-bit direct access to all 4 planes.

Proper programming for the controller consists of

putting the controller in either 'text' or 'graphics'

mode and then setting the following registers as

indicated:

SR04 =0Eh Sequencer Memory Mode

SR02 =0Fh Sequencer Plane Mask

GR05 =00h Graphics Controller Mode

GR06 =04h (text mode) Graphics Controller Misc

=05h (gr mode) Graphics Controller Misc

XR0B=x5h Paging Control

This sets up the VGA controller to allow 32-bit direct

access to all 4 planes of all 1MB of display memory

in a linear fashion. It also sets the VGA memory

aperture to a 64KB space at 0A0000h independent of

initial graphics or text mode settings.

Copying Cursor Data to Display Memory

Once the base address for the cursor data pattern in

display memory has been determined and the VGA

has been properly programmed, the cursor data

pattern may be copied from system memory to

display memory. The following program sequence

shows an example of one method which may be

used:

es:edi = display memory base address for cursor

ds:si = address of AND array in system memory

ds:bx = address of XOR array in system memory

MOV AL, [SI+1]

MOV AH, [BX+1]

SHL EAX,16

MOV AL, [SI]

MOV AH, [BX]

STOSD

Setting the Cursor Position, Type, and Base Address

Following storage of the cursor data array in display

memory, the location of the cursor in display

memory is set via the Cursor Base Address register

(DR0C) and the X-Y coordinates for positioning the

cursor are written to the Cursor Position Register

(DR0B). The cursor type and X/Y zoom (H/V pixel

replication) factors are then set and the cursor

enabled via the Cursor Control Register (DR08).

To update the cursor position, a 32-bit write (or two

16-bit writes) are performed to the Cursor Position

on the next frame (synchronized to VSync).

When the cursor changes shape, it should normally

be disabled, reprogrammed as described above, and

then re-enabled. Alternately, a new shape may be

stored in a different location in display memory, the

cursor screen XY location updated (via DR0B), then

the new cursor selected as the active cursor (by

reprogramming the base register DR0C). Cursor

base register changes are also synchronized to VSync

to avoid glitching of the cursor on the display.

Overview

A number of extension registers in the 65540 / 545

control the panel interface, including the functions of

the interface pins and the timing sequences produced

for compatibility with various types of panels. Some

key registers of interest for panel interfacing are:

XR1C H Panel Size (# of characters – 1)

XR68 V Panel Size (# of scan lines – 1) bits 0-7

(XR65[1]=Vsize bit-8, XR65[6]=bit-9)

XR4F Panel Format 2 (Bits/pixel,M/LP function)

XR50 Panel Format 1 (FRC,dither,clkdiv,VAM)

XR51 Display Type (Panel type,clk/LP control)

XR53 Panel Format 3 (FRC opt,pixel packing)

XR54 Panel Interface (FLM/LP Control)

XR5E M (ACDCLK) Control

XR6F Frame Buffer Control

This section summarizes the function of the various

fields of the above registers as they pertain to panel

interfacing. Detailed timing diagrams are shown for

output of data and control sequences to a variety of

panel types. The 65540 / 545 highly configurable

controllers can interface to virtually all existing

monochrome LCD, EL, and Plasma panels and all

color LCD STN and TFT panels. The panel types

supported are:

Single panel-Single drive (SS) Monochrome

1pixel/clock, 8 bits/pixel

2pixels/clock,8 bits/pixel

4pixels/clock,4 bits/pixel

8pixels/clock,2 bit/pixel

16 pixels/clock,1 bit/pixel

Dual panel-Double drive (DD) Monochrome

8pixels/clock,1 bit/pixel

16 pixels/clock,1 bit/pixel

Single panel-Single drive (SS) Color TFT

1pixel/clock, 16 bit/pixel 5-6-5 RGB

1pixel/clock, 24 bit/pixel 8-8-8 RGB

2pixels/clock,12 bit/pixel 4-4-4 RGB

Single panel-Single drive (SS) Color STN

2 2/3 pixels/clock,3 bit/pixel 1-1-1 RGB

5 1/3 pixels/clock,3 bit/pixel 1-1-1 RGB

Dual panel-Double drive (DD) Color STN

2 2/3 pixels/clock,3 bit/pixel 1-1-1 RGB

5 1/3 pixels/clock,3 bit/pixel 1-1-1 RGB

Revision 1.2 179 65540 / 545

Panel Size

The horizontal panel size register (XR1C) is an 8-bit

in units of 8-pixel characters (e.g., a 640x480 panel

is 80 'characters' wide so XR1C would be

programmed with 79 decimal). The vertical panel

size register is programmed with the panel height

(minus one) in scan lines (independent of single or

dual panel type). The programmed value is 10 bits

in size with the 8 lsbs in XR68 and the overflow in

XR65 bits 1 and 6. The maximum panel resolution

supported is 2048 x 1024.

Panel Type

The panel type (PT) is determined by XR51 bits 1-0:

00 Single panel-Single drive (SS)

11 Dual panel-Double drive (DD)

For DD panels, XR6F bit-0 (Frame Buffer Enable)

and/or bit-1 (Frame Accelerator Enable) must also be

set (either external or embedded may be used).

TFT Panel Data Width

XR50 bit-7 controls output width for TFT panels:

016-bit color TFT panel interface (565 RGB)

124-bit color TFT panel interface (888 RGB)

Flat Panel Timing

Display Quality Settings

Frame Rate Control (FRC)

The 65540 / 545 provides 2 and 16 level FRC to

generate multiple gray / color levels. FRC selection

is determined by XR50 bits 1-0:

00 No FRC

01 16-frame FRC (color or mono STN panels)

10 2-frame FRC (color TFT or mono panels)

Three options are provided for FRC control:

FRC option 1 (XR53[2]) (always set to 1)

FRC option 2 (XR53[3]) (always set to 1)

FRC option 3 (XR53[6]) (for 2-frame FRC only):

0FRC data changes every frame

1FRC data changes every other frame

A setting of 0 typically results in better display

quality, but panels with an internal 'M' signal

typically recommend this bit be set to 1 for longer

panel life.

XR6E is also provided for FRC polynomial control.

The values of the 'm' and 'n' parameters are

typically set by trial and error (recommended settings

are given elsewhere in this manuals for selected

panels as derived by Chips and Technologies).

Dither

The 65540 / 545 also provides Dither capability to

generate multiple gray / color levels. Dither selection

is determined by XR50 bits 3-2:

00 No Dither

01 Enable Dither for 256-color modes only

10 Enable Dither for all modes

M Signal Timing

control the timing of the M (sometimes called

ACDCLK) signal. XR5E bit-7 selects between two

types of timing control:

0Use XR5E bits 0-6 to determine M signal

timing (bits 0-6 are programmed with the

number of HSYNCs between phase changes

minus 2)

1M phase changes every frame if the frame

buffer is used, otherwise the phase changes

every other frame

XR4F bit-6 controls the M pin output. If set, the M

pin will output flat panel BLANK# / Display Enable

(DE) instead of the normal M signal (and XR5E will

be ignored).

Revision 1.2 180 65540 / 545

Gray / Color Levels

Gray / color levels are selected via XR4F bits 2-0

(somewhat misleading called 'Bits Per Pixel'):

No FRC

# of msbs Used Gray / Gray / Color

to Generate Color Levels with

Gray/Color Levels Levels Dithering

001 1 2 5

010 2 4 13

011 3 8 29

100 4 16 61

101 5 32 125

110 6 64 253

111 8 256 n/a

2-Frame FRC

(Color TFT or Monochrome Panels)

# of msbs Used Gray / Gray / Color

to Generate Color Levels with

Gray/Color Levels Levels Dithering

010 1 3 9

011 2 5 25

100 3 15 57

101 4 31 121

16-Frame FRC

(Color or Monochrome STN Panels)

# of msbs Used Gray / Gray / Color

to Generate Color Levels with

Gray/Color Levels Levels Dithering

001 1 2 5

010 2 4 13

011 3 8 29

100 4 16 61

The setting programmed into XR4F bits 0-2 above

determines how many most-significant color-bits /

pixel are used to generate flat panel video data. In

general, 8 bits of monochrome data or 8 bits/color of

RGB color data enter the flat panel logic for every

dot clock. Not all of these bits, however, are used to

generate output colors / gray scales, depending on

the type of panel used, graphics / text mode, and the

gray-scaling algorithm chosen (the actual number of

bits used is indicated in the table above). Also note

that settings which achieve higher gray / color levels

may not necessarily produce acceptable display

quality on some (or any) currently available panels.

This document contains recommended settings for

various popular panels that Chips & Technologies

has found to produce acceptable results with those

panels. Customers may modify these settings to

achieve a better match with their requirements.

Flat Panel Timing

Pixels Per Shift Clock

The 65540 / 545 can be programmed to output 1, 2,

4, 8, or 16 pixels per shift clock. This is achieved

by programming the frequency ratio between the dot

clock and the shift clock. The shift clock divide

(CD) is set by XR50 bits 6-4. For monochrome

panels, the valid settings are:

Pixels Per Pixels Per

Shift Shift Clock Shift Clock

Clock without Frm Acc with Frm Acc

000 Dot clk 1 2

001 Dclk / 2 2 4

010 Dclk / 4 4 8

011 Dclk / 8 8 16

100 Dclk / 16 16 n/a

Pixels 8-Bit Valid 16-Bit Valid

Per Shift Panel Outputs Panel Outputs

Clock Interface (8-bit) Interface (16-bit)

18bpp P8-15 8bpp P8-15

24bpp P8-15 (8-11 1st) 8bpp P0-15

42bpp P8-15 (8-9 1st) 4bpp P0-15

81bpp P1,3,5,... (1 1st) 2bpp P0-15

16 n/a n/a 1bpp P0-15

The pixel on the lowest numbered output pin is

always the first pixel output (the pixel shown first on

the left side of the screen). For example, for 8 pixels

per clock, 1bpp on an 8-bit interface, P1 is the first

pixel, P3 is the second, etc. For 16 pixels per clock,

1bpp on a 16-bit interface, P0 is the first pixel, P1 is

the second, etc. For 4 pixels per clock, 2bpp on an

8-bit interface, P8-9 is the first pixel, P10-11 is the

second, etc.

Revision 1.2 181 65540 / 545

The number of bits per pixel is determined as

follows:

1bpp: Bits/Pixel=000 or 001 or

16-Frame FRC or

2-Frame FRC with Bits/Pixel=010

2bpp: Not 1bpp and CD=011 (8 Pixels/Clock)

4bpp: Not 1bpp and CD=010 (4 Pixels/Clock)

8bpp: Not 1bpp and CD=001 (2 Pixels/Clock) or

Not 1bpp and CD=000 (1 Pixels/Clock)

Valid Color TFT panel shift clock divide settings are:

Pixels

per TFT TFT "B0-n" "G0-n" "R0-n"

Shift Output Output Panel Panel Panel

Clock Width Format Outputs Outputs Outputs

000 1 16 5-6-5 P0-4 P5-10 P11-15

24 8-8-8 P0-7 P8-15 P16-23

001 2 24 4-4-4 P0-3 P8-11 P16-19

P4-7 P12-15 P20-23

For 2 pixels/shift clock, the first pixel output is on

P0-3, 8-11, and 16-19.

For Color STN, valid shift clock divide settings are:

Pixels Per Clock Pixels Per Clock

without with

Frame Acceleration Frame Acceleration

SS or DD Panels DD Panels Only

000 1 2

001 2 4

010 4 n/a

For Color STN data, pixel output sequences are

controlled by the 'Color STN Pixel Packing' bits

(XR53[5-4]) described on the following page

(packing may be selected as '3-Bit Pack', '4-Bit

Pack', or 'Extended 4-Bit Pack' sometimes referred

to in this document as 3bP, 4bP, and X4bP). All

cases in the above table can use 3-Bit Pack or 4-Bit

Pack. Extended 4-Bit Pack is only used for the

single case of 2 pixels per shift clock without frame

acceleration. Pixel Packing is not used for

EL/Plasma, Monochrome DD, or Color TFT panels

so the pixel packing bits should be set to 00 for all

panels except color STN.

Shift Clock Divide

The above clock divide ('CD') bits (XR50 bits 6-4)

affect both shift clock and data out. XR51[3] (Shift

Clock Divide or SD) may be set so that only the shift

clock (and not the video data) is further divided by

two beyond the setting of XR50 bits 6-4. This has

the effect of causing a new pixel to be output on

every clock edge (i.e., both rising and falling) in-

stead of just every falling clock edge (the first pixel

output on every scan line will be on the rising edge).

Extended 4-Bit Pack for Color STN panels requires

that the SD bit (XR51[3]) be set to 1. In all other

cases in the Color STN table above, either setting

may be used.

Flat Panel Timing

24bit 24bit 16bit 8bit 16bit 16bit 16bit

Color Color Color Mono Mono Mono Mono

Pix/clk: 1 2 1 1 2 4 8

CD: 000 001 000 000 001 010 011

P0 B0n B4n B3n – G0n G4n G6n

P1 B1n B5n B4n – G1n G5n G7n

P2 B2n B6n B5n – G2n G4n+1 G6n+1

P3 B3n B7n B6n – G3n G5n+1 G7n+1

P4 B4n B4n+1 B7n G0n† G0n+1 G4n+2 G6n+2

P5 B5n B5n+1 G2n G1n† G1n+1 G5n+2 G7n+2

P6 B6n B6n+1 G3n G2n† G2n+1 G4n+3 G6n+3

P7 B7n B7n+1 G4n G3n† G3n+1 G5n+3 G7n+3

P8 G0n G4n G5n G0n G4n G6n G6n+4

P9 G1n G5n G6n G1n G5n G7n G7n+4

P10 G2n G6n G7n G2n G6n G6n+1 G6n+5

P11 G3n G7n R3n G3n G7n G7n+1 G7n+5

P12 G4n G4n+1 R4n G4n G4n+1 G6n+2 G6n+6

P13 G5n G5n+1 R5n G5n G5n+1 G7n+2 G7n+6

P14 G6n G6n+1 R6n G6n G6n+1 G6n+3 G6n+7

P15 G7n G7n+1 R7n G7n G7n+1 G7n+3 G7n+7

P16 R0n R4n – – – – –

P17 R1n R5n – – – – –

P18 R2n R6n – – – – –

P19 R3n R7n – – – – –

P20 R4n R4n+1 – – – – –

P21 R5n R5n+1 – – – – –

P22 R6n R6n+1 – – – – –

P23 R7n R7n+1 – – – – –

† For information only, not recommended for panel connections

Color STN Pixel Packing ( Pixel Output Order )

For color STN panels, pixel packing must be

selected via XR53 bits 5-4:

Packing CD Settings Allowable

00 3-Bit Pack SS: 000, 001, or 010

DD: 000, 001 (010 w/o FA)

01 4-Bit Pack SS: 000, 001, or 010

DD: 000, 001 (010 w/o FA)

11 Ext'd 4-Bit Pack SS: 001 (8bit panels only)

These settings are valid for color STN panels only

(these bits must be set to 00 for monochrome and

color TFT panels).

Pixel output order for 3-Bit Pack STN-SS panels

without frame acceleration:

The pixel sequence for 3-bit Pack repeats with either

1, 2, or 4 pixels every shift clock edge depending on

the setting of the clock divide (CD) field. The pixel

sequence for 4-bit Pack repeats with 8 pixels every 3

shift clock edges. The sequence for Extended 4-Bit

Pack repeats with 16 pixels every 6 shift clock

edges. Extended 4-bit Pack is used only for 8-bit

color STN-SS panels. It is not used for color STN

DD panels or for 16-bit color STN interfaces.

4b Pack, CD=001 Ext'd 4b Pack, CD=001

Shift Clock Edge Shift Clock Edge

1st 2nd 3rd 4th 1st 2nd 3rd 4th 5th 6th 7th

P0 R1 B3 G6 ... R1 G1 G6 B6 B11 R12 ...

P1 G1 R4 B6 ... B1 R2 R7 G7

G12

B12 ...

P2 B1 G4 R7 ... G2 B2 B7 R8

R13

G13 ...

P3 R2 B4 G7 ... R3 G3 G8 B8 B13 R14 ...

P4 G2 R5 B7 ... B3 R4 R9 G9

G14

B14 ...

P5 B2 G5 R8 ... G4 B4 B9 R10

R15

G15 ...

P6 R3 B5 G8 ... R5 G5 G10 B10 B15 R16 ...

P7 G3 R6 B8 ... B5 R6 R11 G11

G16

B16 ...

CD=000 (1p/clk) CD=001 (2p/clk) CD=010 (4p/clk)

ShfClk Edge Shift Clock Edge Shift Clock Edge

1st 2nd 3rd 4th 1st 2nd 3rd 4th 1st 2nd 3rd 4th

P0 – – – ... ...

P1 R1 R2 R3 ... R1 R3 R5 ... R1 R5 R9 ...

P2 G1 G2 G3 ... G1 G3 G5 ... G1 G5 G9 ...

P3 B1 B2 B3 ... B1 B3 B5 ... B1 B5 B9 ...

P4 – – – – – – – – –

P5 – – – R2 R4 R6 ... R2 R6 R10 ...

P6 – – – G2 G4 G6 ... G2 G6 G10 ...

P7 – – – B2 B4 B6 ... B2 B6 B10 ...

P8 – – – – – – ...

P9 – – – – – – R3 R7 R11 ...

P10 – – – – – – G3 G7 G11 ...

P11 – – – – – – B3 B7 B11 ...

P12 – – – – – – – – –

P13 – – – – – – R4 R8 R12 ...

P14 – – – – – – G4 G8 G12 ...

P15 – – – – – – B4 B8 B12 ...

Revision 1.2 182 65540 / 545

Pixel output order for 4-Bit Pack 8-bit STN DD

panels:

The pixel sequence repeats with 8 pixels (4 for each

of the upper and lower panels) every 3 shift clock

edges. Clock divide must be set to 000 with Frame

Acceleration and 001 without Frame Acceleration.

Pixel output order for 16-bit STN panels (4bit Pack):

For STN-SS panels the pixel sequence repeats with

16 pixels every 3 shift clock edges (5-1/3 pixels per

shift clock edge). Clock divide must be set to 010.

For STN-DD panels the pixel sequence repeats with

16 pixels (8 for each of the upper and lower panels)

every 3 shift clock edges (2-2/3 pixels per shift clock

edge per panel). Clock divide must be set to 001

with Frame Acceleration and 010 without Frame

Acceleration.

STN-SS Panels

Shift Clock Edge

1st 2nd 3rd 4th

P0 R1 G6 B11 ...

P1 G1 B6 R12 ...

P2 B1 R7 G12 ...

P3 R2 G7 B12 ...

P4 G2 B7 R13 ...

P5 B2 R8 G13 ...

P6 R3 G8 B13 ...

P7 G3 B8 R14 ...

P8 B3 R9 G14 ...

P9 R4 G9 B14 ...

P10 G4 B9 R15 ...

P11 B4 R10G15 ...

P12 R5 G10B15 ...

P13 G5 B10R16 ...

P14 B5

R11

G16 ...

P15 R6

G11

B16 ...

Shift Clock Edge

1st 2nd 3rd 4th

Upper:

P0 R1 G2 B3 ...

P1 G1 B2 R4 ...

P2 B1 R3 G4 ...

P3 R2 G3 B4 ...

Lower:

P4 R1 G2 B3 ...

P5 G1 B2 R4 ...

P6 B1 R3 G4 ...

P7 R2 G3 B4 ...

Flat Panel Timing

STN-DD Panels

Shift Clock Edge

1st 2nd 3rd 4th

Upper:

P0 R1 B3 G6 ...

P1 G1 R4 B6 ...

P2 B1 G4 R7 ...

P3 R2 B4 G7 ...

P8 G2 R5 B7 ...

P9 B2 G5 R8 ...

P10 R3 B5 G8 ...

P11 G3 R6 B8 ...

Lower:

P4 R1 B3 G6 ...

P5 G1 R4 B6 ...

P6 B1 G4 R7 ...

P7 R2 B4 G7 ...

P12 G2 R5 B7 ...

P13 B2 G5 R8 ...

P14 R3 B5 G8 ...

P15 G3 R6 B8 ...

Output Signal Timing

LP Signal Timing

LP output polarity is controlled by XR54[6]

(0=positive, 1=negative). Setting XR4F bit-7,

however, causes the LP pin to output flat panel

BLANK# / DE instead of the normal LP signal (and

all other LP timing control parameters will be

ignored). Some panels (e.g., Plasma and EL)

require LP to be active during vertical blank time.

XR51[7] may be set to enable this. Otherwise LP

pulses are not generated during vertical blank.

FLM Output Signal Timing

FLM signal output polarity is controlled by XR54[7]

(0=positive, 1=negative).

BLANK# / DE Output Signal Timing

The polarity of the BLANK# / DE output (if selected

for output on M, LP, or FLM as indicated above)

may be controlled by XR54[0] (0=positive,

1=negative). XR54[1] selects whether BLANK# /

DE outputs both H and V (0) or just H (1).

XR51[2] selects whether BLANK# / DE is generated

from CRT Blank or Flat Panel Blank.

SHFCLK Output Signal Timing

XR51[5] (Shift Clock Mask or SM) may be set to

force the shift clock output low outside the display

enable interval.

Revision 1.2 183 65540 / 545

Pixel Timing Diagrams

Pixel output timing sequences are shown for the

following panel configurations:

1) SS Monochrome Plasma / EL

Single Panel-Single Drive (Panel Type = 00)

Plasma/EL Panel

2 pixels/shift clock, 4 bits/pixel (CD = 001)

2) DD Monochrome LCD

Dual Panel-Double Drive (Panel Type = 11)

Monochrome LCD Panel

8 pixels/shiftclk, 1bit/pixel, CD = 011

(010 with FB)

16 pixels/shiftclk, 1bit/pixel, CD = 100

(011 with FB)

3) SS Color TFT LCD

Single Panel-Single Drive (Panel Type = 00)

Color TFT LCD Panel

4/5/6/8 bits/color/pixel (12/16/18/24 bits total)

1 pixel/shift clock, 16-bit 5-6-5 RGB, CD=000

1 pixel/shift clock, 24-bit 8-8-8 RGB, CD=000

2 pixels/shift clock, 24-bit 4-4-4 RGB, CD=001

4) SS Color STN LCD

Single Panel-Single Drive (Panel Type = 00)

Color STN LCD Panel

1 bit/color/pixel (3 bits total) 1-1-1 RGB

1 pixel/shiftclk (3bit), CD=000

2 pixels/shiftclk (6bit), CD=001

2-2/3 pixels/shift clock (8bit), CD=010

5-1/3 pixels/shift clock (8bit), CD=010, SD=1

5-1/3 pixels/shift clock (16bit), CD=010

5) DD Color STN LCD

Dual Panel-Dual Drive (Panel Type = 11)

Color STN LCD Panel

All timings = 1 bit/color/pixel (3 bits total) RGB

2-2/3 pixels/shift clock (8-bit), CD=001

5-1/3 pixels/shift clock (16-bit), CD=010

Flat Panel Timing

(1,1)

–1 (3,1)

–1

SHFCLK

(1,1)

–2 (3,1)

–2

(1,1)

–4 (3,1)

–4

P10

(637,1)

–1 (639,1)

–1

(637,1)

–2 (639,1)

–2

(637,1)

–4 (639,1)

–4

(637,480)

–1 (639,480)

–1

(637,480)

–2 (639,480)

–2

(637,480)

–4 (639,480)

–4

(1,1)

–8 (3,1)

–8

P11 (637,1)

–8 (639,1)

–8 (637,480)

–8 (639,480)

–8

(2,1)

–1 (4,1)

–1

P12 (638,1)

–1 (640,1)

–1 (638,480)

–1 (640,480)

–1

(2,1)

–2 (4,1)

–2

P13 (638,1)

–2 (640,1)

–2 (638,480)

–2 (640,480)

–2

(2,1)

–4 (4,1)

–4

P14 (638,1)

–4 (640,1)

–4 (638,480)

–4 (640,480)

–4

(2,1)

–8 (4,1)

–8

P15 (638,1)

–8 (640,1)

–8 (638,480)

–8 (640,480)

–8

BLANK#

SHFCLK

FLM

P8-15

320 Clks / H 320 Clks / H

(1,1)...(640,1) (1,2)...(640,2)

480 Data Transfer Cycles / V

320 Clks / H

(1,480)...(640,480)

SHFCLK

(Plasma)

(EL †)

† EL panels use the rising edge of SHFCLK to clock in panel data, so the SHFCLK

output from the 65540 / 545 must be inverted prior to driving the panel

Panel Timing - Monochrome 16-Gray-Level EL / Plasma 8-Bit Interface

Revision 1.2 184 65540 / 545

Flat Panel Timing

(1,1) (5,1)

SHFCLK

P0 (2,1) (6,1)

P1 (3,1) (7,1)

(633,1) (637,1)

(634,1) (638,1)

(635,1) (639,1)

(633,240) (637,240)

(634,240) (638,240)

(635,240) (639,240)

(4,1) (8,1)

P3 (636,1) (640,1) (636,240) (640,240)

(1,241) (5,241)

P4 (633,241) (637,241) (633,480) (637,480)

(2,241) (6,241)

P5 (634,241) (638,241) (634,480) (638,480)

(3,241) (7,241)

P6 (635,241) (639,241) (635,480) (639,480)

(4,241) (8,241)

P7 (636,241) (640,241) (636,480) (640,480)

BLANK#

SHFCLK

FLM

P0-7

160 Clks / H 160 Clks / H

(1,1)...(640,1) (1,2)...(640,2)

240 Data Transfer Cycles / V

160 Clks / H

(1,240)...(640,240)

(1,241)...(640,241) (1,242)...(640,242) (1,480)...(640,480)

Panel Output Pixel Order - 640 x 480

(No FA) DCLK

(FA) DCLK

(640 x 480)

(640 x 480) (640 x 480) (640 x 480)

Panel Output Timing - 640 x 480 Monochrome DD 8-Bit (1 Bit / Pixel, 8 Pixels / Shift Clock)

(UD3)

(UD2)

(UD1)

(UD0)

(LD3)

(LD2)

(LD1)

(LD0)

(SHFCLK x 8)

(SHFCLK x 4)

FA = Frame Accelerator (Imbedded or External)

CD = 011

CD = 010

Panel Timing - Monochrome LCD DD 8-Bit Interface

Revision 1.2 185 65540 / 545

Flat Panel Timing

(1,1)

SHFCLK

P0 (2,1)

P1 (3,1)

(1009,384)

(1010,384)

(1011,384)

(4,1)

P3 (1012,384)

(1,385)

P8 (1009,768)

(2,385)

P9 (1010,768)

(3,385)

P10 (1011,768)

(4,385)

P11 (1012,768)

BLANK#

SHFCLK

FLM

P0-15

256 Clks / H 256 Clks / H

(1,1)...(1024,1) (1,2)...(1024,2)

384 Data Transfer Cycles / V

256 Clks / H

(1,384)...(1024,384)

(1,385)...(1024,385) (1,386)...(1024,386) (1,768)...(1024,768)

(5,1)

P4 (6,1)

P5 (7,1)

(1013,384)

(1014,384)

(1015,384)

(8,1)

P7 (1016,384)

(5,385)

P12 (1013,768)

(6,385)

P13 (1014,768)

(7,385)

P14 (1015,768)

(8,385)

P15 (1016,768)

Pixel Output Pixel Order - 1024 x 768

Panel Output Timing - 1024 x 768 Monochrome DD 16-Bit (1 Bit / Pixel, 16 Pixels / Shift Clock)

(No FA) DCLK

(FA) DCLK

(SHFCLK x 16)

(SHFCLK x 8)

(UD7)

(UD6)

(UD5)

(UD4)

(UD3)

(UD2)

(UD1)

(UD0)

(LD7)

(LD6)

(LD5)

(LD4)

(LD3)

(LD2)

(LD1)

(LD0)

FA = Frame Accelerator (Embedded or External)

CD = 011

CD = 100

(1024 x 768) (1024 x 768) (1024 x 768)

(1024 x 768)

(9,1)

(10,1)

(11,1)

(12,1)

(13,1)

(14,1)

(15,1)

(16,1)

(9,385)

(10,385)

(11,385)

(12,385)

(13,385)

(14,385)

(15,385)

(16,385)

Panel Timing - Monochrome LCD DD 16-Bit Interface

Revision 1.2 186 65540 / 545

Flat Panel Timing

SHFCLK

DCLK

G0(1) G1(1)

G0(0) G1(0)

G0(2) G1(2) G0(1)

G0(0)

B1(2)

G2(1)

G2(0)

B3(2)

CD: 000 (1 Pixel / Clock) 001 (2 Pixels / Clock)

FRC: 10 (2 Frame) 10 (2-Frame)

Bits / Pixel: 110 (6 bits/pixel) 011 (3 bits/pixel)

P0 B0(0) B1(0) B0(0) B2(0)

P1 B0(1) B1(1) B0(1) B2(1)

G1(2)

G1(1)

G3(2)

G3(1)

G1(0)

G0(2)

G3(0)

G2(2)

G0(5)

G0(4)

G0(3)

R0(0)

G1(5)

G1(4)

G1(3)

R1(0)

P11

P10

B0(4) B1(4) B1(1) B3(1)

B0(2)

B0(3)

B1(2)

B1(3) B1(0)

B0(2)

B3(0)

B2(2)

R0(1)

R0(0)

R2(1)

R2(0)R0(1)

R0(2)

R1(1)

R1(2)

P13

P12

R1(1)

R1(0)

R3(1)

R3(0)R0(3)

R0(4)

R1(3)

R1(4)

P15

P14

Data Width: 16-Bit † 16-Bit †

Pixel Format: 5-6-5 RGB 2-3-3 RGB

† Panels with 9 or 12-bit data interfaces would use this setting and only connect to the msbs of each color

Panel Timing - Color LCD TFT 9 / 12 / 16-Bit Interface

Revision 1.2 187 65540 / 545

Flat Panel Timing

SHFCLK

DCLK

B0(6) B1(6)

B0(5) B1(5)

B0(7) B1(7) B1(3)

B1(2)

B1(1)

B3(3)

B3(2)

B3(1)

CD: 000 (1 Pixel / Clock) 001 (2 Pixels / Clock)

FRC: 00 (no FRC) 10 (2-Frame)

Bits / Pixel: 111(8 bits/pixel) 100/101 (4 or 5 bits/pixel)

P0 B0(0) B1(0) B0(0) B2(0)

P1 B0(1) B1(1) B0(1) B2(1)

G0(3)

G0(2)

G2(3)

G2(2)

G0(1)

G0(0)

G2(1)

G2(0)

G0(2)

G0(1)

G0(0)

G0(3)

G1(2)

G1(1)

G1(0)

G1(3)

P11

P10

B0(4) B1(4) B1(0) B3(0)

B0(2)

B0(3)

B1(2)

B1(3) B0(3)

B0(2)

B2(3)

B2(2)

G1(1)

G1(0)

G3(1)

G3(0)G0(4)

G0(5)

G1(4)

G1(5)

P13

P12

G1(3)

G1(2)

G3(3)

G3(2)G0(6)

G0(7)

G1(6)

G1(7)

P15

P14

Data Width: 24-Bit † 24-Bit †

R0(3)

R0(2)

R2(3)

R2(2)

R0(1)

R0(0)

R2(1)

R2(0)

R0(2)

R0(1)

R0(0)

R0(3)

R1(2)

R1(1)

R1(0)

R1(3)

P19

P18

P17

P16

R1(1)

R1(0)

R3(1)

R3(0)R0(4)

R0(5)

R1(4)

R1(5)

P21

P20

R1(3)

R1(2)

R3(3)

R3(2)R0(6)

R0(7)

R1(6)

R1(7)

P23

P22

Pixel Format: 8-8-8 RGB 4-4-4 RGB

† Panels with 18-bit data interfaces would use this setting and only connect to the msbs of each color

Panel Timing - Color LCD TFT 18 / 24-Bit Interface

Revision 1.2 188 65540 / 545

Flat Panel Timing

Revision 1.2 189 65540 / 545

Flat Panel Timing

SHFCLKL

DCLK

SHFCLKU

(Pin 70)

CD: 010 (5-1/3 Pixels / Clock)

FRC: 01 (16-Frame)

G10

R10

B10

R12

B12

G13

R14

B14

G15

R16

B11

G12

R13

B13

G14

R15

B15

P7 B5 R6 R11 B16G16G11

PT: 00 (SS Panel)

Pixel Packing: 11 (Extended 4-Bit Pack)

(Pin 81)

16 Pixels are

transferred

every 16 dot clocks

(6 shift clock edges)

IDCLK

IDCLK/2

100 (4 bits / pixel)Bits / Pixel:

Frame Buffer / Acceleration: Disabled / Disabled

Panel Timing - Color LCD STN 8-Bit ( Extended 4-Bit Pack ) Interface

010 (5-1/3 Pixels / Clock)

SHFCLK

DCLK

P12

P11

P10

P14

P13

P15

R10

G10

B10

R11

G15

B15

R16

G14

B14

R15

B19

R20

G20

B20

R21

G21

CD:

Bits / Pixel: 100 (4 bits / pixel)

PT: 00 (SS Panel)

Pixel Packing: 01 (4-Bit Pack)

G16 B21

G30

B30

R31

G31

B31

R32

G32

R25

G25

B25

R26

G26

B26

R27

R6 G11 B16 B32G27R22

B12

R13

G13

B13

B11

R12

G12

R17

G17

B17

R18

G18

B18

R19

B27

R28

G28

B28

R29

G29

B29

G22

B22

R23

G23

B23

R24

G24

G3 B8 R14 R30B24G19

FRC: 01 (16-Frame)

Frame Buffer / Acceleration: Disabled / Disabled

IDCLK

(IDCLK/2)

Revision 1.2 190 65540 / 545

Flat Panel Timing

Panel Pixel Timing - Color LCD STN 16-Bit ( 4-Bit Pack ) Interface

DCLK

R(1,241)

G(1,241)

B(1,241)

R(2,241)

R(5,241)

G(5,241)

B(5,241)

R(6,241)

R(2,1)

B(1,1)

G(1,1)

R(1,1)

G(3,241)

R(3,241)

B(2,241)

G(2,241)

G(2,1)

B(2,1)

R(3,1)

G(3,1)

B(4,241)

G(4,241)

R(4,241)

B(3,241)

B(3,1)

R(4,1)

G(4,1)

B(4,1)

R(5,1)

G(5,1)

B(5,1)

R(6,1)

G(6,241)

B(6,241)

R(7,241)

G(7,241)

G(6,1)

B(6,1)

R(7,1)

G(7,1)

8 Pixels (4 each for the upper and lower panels) are transferred every 4 Dot Clocks (3 Shift Clock Edges)

(IDCLK)

CD: 000 (2-2/3 Pixels / Clock)

FRC: 01 (16-Frame)

PT: 11 (DD Panel)

Pixel Packing: 01 (4-Bit Pack)

Bits / Pixel: 100 (4 bits/pixel)

Enabled/Enabled

Frame Buffer/Acceleration:

SHFCLK

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Panel Pixel Timing - Color LCD STN-DD 8-Bit ( 4-Bit Pack ) Interface - With Frame Acceleration

DCLK

R(1,241)

G(1,241)

B(1,241)

R(2,241) G(3,241)

R(3,241)

B(2,241)

G(2,241)

B(4,241)

G(4,241)

R(4,241)

B(3,241) R(5,241)

G(5,241)

B(5,241)

R(6,241)

G(6,241)

B(6,241)

R(7,241)

G(7,241)

R(2,1)

B(1,1)

G(1,1)

R(1,1) G(2,1)

B(2,1)

R(3,1)

G(3,1)

B(3,1)

R(4,1)

G(4,1)

B(4,1)

R(5,1)

G(5,1)

B(5,1)

R(6,1)

G(6,1)

B(6,1)

R(7,1)

G(7,1)

CD: 001 (2-2/3 Pixels / Clock)

FRC: 01 (16-Frame)

PT: 11 (DD Panel)

Pixel Packing: 01 (4-Bit Pack)

8 Pixels (4 each for the upper and lower panels) are transferred every 8 Dot Clocks (3 Shift Clock Edges)

IDCLK

SHFCLK

(IDCLK/2)

Bits / Pixel: 100 (4 bits/pixel)

Enabled/Disabled

Frame Buffer/Acceleration:

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Panel Pixel Timing - Color LCD STN-DD 8-Bit ( 4-Bit Pack ) Interface - Without Frame Acceleration

DCLK

R(13,241)

G(13,241)

B(13,241)

R(14,241)

R(13,1)

G(13,1)

B(13,1)

R(14,1)

B(11,241)

R(12,241)

G(12,241)

B(12,241)

P14

P10

P11

P12

P13

P15

G(2,241)

B(2,241)

R(3,241)

G(3,241) R(6,241)

B(5,241)

G(5,241)

R(5,241)

B(8,241)

G(8,241)

R(8,241)

B(7,241) G(10,241)

B(10,241)

R(11,241)

G(11,241)

G(3,1)

R(3,1)

B(2,1)

G(2,1) R(5,1)

G(5,1)

B(5,1)

R(6,1)

B(7,1)

R(8,1)

G(8,1)

B(8,1)

G(10,1)

B(10,1)

R(11,1)

G(11,1)

CD: 001 (5-1/3 Pixels / Clock)

FRC: 01 (16-Frame)

PT: 11 (DD Panel)

Pixel Packing: 01 (4-Bit Pack)

R(1,241)

G(1,241)

B(1,241)

R(2,241) B(4,241)

G(4,241)

R(4,241)

B(3,241)

G(7,241)

R(7,241)

B(6,241)

G(6,241) R(9,241)

G(9,241)

B(9,241)

R(10,241)

R(2,1)

B(1,1)

G(1,1)

R(1,1) B(3,1)

R(4,1)

G(4,1)

B(4,1)

G(6,1)

B(6,1)

R(7,1)

G(7,1)

R(9,1)

G(9,1)

B(9,1)

R(10,1)

B(11,1)

R(12,1)

G(12,1)

B(12,1)

16 Pixels (8 each for the upper and lower panels) are transferred every 8 Dot Clocks (3 Shift Clock Edges)

IDCLK

(IDCLK /2)

SHFCLK

Bits / Pixel: 100 (4 bits / pixel)

Enabled / Enabled

Frame Buffer / Acceleration:

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Flat Panel Timing

Panel Pixel Timing - Color LCD STN-DD 16-Bit ( 4-Bit Pack ) Interface - With Frame Acceleration

DCLK

16 Pixels (8 each for the upper and lower panels) are transferred every 16 Dot Clocks (3 Shift Clock Edges)

IDCLK

(IDCLK /4)

SHFCLK

P14

P10

P11

P12

P13

P15

G(2,241)

B(2,241)

R(3,241)

G(3,241) B(8,241)

G(8,241)

R(8,241)

B(7,241)

G(3,1)

B(7,1)

R(8,1)

G(8,1)

B(8,1)

CD: 010 (5-1/3 Pixels / Clock)

FRC: 01 (16-Frame)

PT: 11 (DD Panel)

Pixel Packing: 01 (4-Bit Pack)

P7 G(7,241)

R(7,241)

B(6,241)

G(6,241)

R(3,1)

B(2,1)

G(2,1)

R(1,241)

G(1,241)

B(1,241)

R(2,241)

R(2,1)

B(1,1)

G(1,1)

R(1,1)

R(6,241)

B(5,241)

G(5,241)

R(5,241)

R(5,1)

G(5,1)

B(5,1)

R(6,1)

B(4,241)

G(4,241)

R(4,241)

B(3,241)

B(3,1)

R(4,1)

G(4,1)

B(4,1)

G(6,1)

B(6,1)

R(7,1)

G(7,1)

Bits / Pixel: 100 (4 bits / pixel)

IDCLK /2

Frame Buffer/Acceleration: Enabled/Disabled

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Flat Panel Timing

Panel Pixel Timing - Color LCD STN-DD 16-Bit (4-Bit Pack) Interface - Without Frame Acceleration

GENERAL PROGRAMMING HINTS

The values presented in this section make certain

assumptions about the operating environment. The

flat panel clock ('dot clock') is assumed to be

generated by the internal clock synthesizer. The

values programmed into the SmartMap™ control

registers (XR61 and XR62) give a threshold of 3

with foreground and background shift of 3 but

SmartMap™ is turned off. To enable it, set XR61

bit-0 = 1. The 65540 and 65545 provide

programmability of the gray scaling algorithm by

adjusting 'm' and 'n' polynomial values in extended

The horizontal parameter values presented here are

the minimum required for each panel type. For high

resolution panels, these parameters may be changed

to suit the panel size. The horizontal values equal

the number of characters clocks output per line. In

dual drive panels this value includes both panels.

Therefore, the horizontal values are double those

expected.

Due to pipelining of the horizontal counters, certain

sync or blank values may result in no display.

Generally, the horizontal blank start must equal the

display end and the blank end must equal the

horizontal total. The horizontal sync start and end

values have a wide range of acceptable values. The

65540 / 545 also has the versatility to program an

LP delay to aid in interfacing to panels with a wide

variety of timing requirements.

In order to program the 65540 / 545 for simulta-

neous display, two FLM signals are required. The

first shorter FLM will match the normal FLM

frequency as the data is displayed on the first half of

the CRT display data. The second FLM will be

longer to allow for the CRT blank time. The FLM

delay is programmed in XR2C and should be equal

to the CRT blank time — FLM front porch — FLM

width.

For flat panel types and sizes not presented here,

start with the parameters for a panel that most

closely resembles the target panel. Adjust the flat

panel configuration registers as needed and adjust

the horizontal and vertical parameters as needed.

Adaption to a non-standard panel is usually a trial

and error process.

These parameters are recommended by Chips and

Technologies, Inc. for the 65540 / 545. They have

been tested on several different flat panel displays.

Customers should feel free to test other register

values to improve the screen appearance or to

customize the 65540 / 545 for other flat panel

displays.

Programming

Revision 1.2 195 65540 / 545

Programming and Parameters

Revision 1.2 196 65540 / 545

EXTENSION REGISTER VALUES

The 65540 / 545 controller can be programmed for a wide variety of flat panels, compensation techniques and

backwards compatibility. The following pages provide the following 65540 / 545 Extension Register Value

tables:

Extension

Table Registers Display Type Description Panels

#1 Minimum Parameters for Initial Boot (Analog CRT VGA Mode)

#2 Additional Parameters for Emulation Modes

#3 Additional 640x480 Monochrome LCD-DD (Panel Mode Only)...............Epson EG-9005F-LS

Citizen G6481L-FF

Sharp LM64P80

Sanyo LCM-6494-24NTK

Hitachi LMG5364XUFC

#4 Additional 640x480 Monochrome LCD-DD (Simultaneous Mode Display)

#5 Additional 640x480 Color TFT LCD (Panel Mode Only)..........................Hitachi TX26D02VC2AA

Sharp LQ9D011

Toshiba LTM-09C015-1

#6 Additional 640x480 Color TFT LCD (Simultaneous Mode Display)

#7 Additional 640x480 Color STN-SS LCD - 4-Bit Pack ...............................Sanyo LM-CK53-22NEZ

(Panel Mode & Simultaneous Mode Display) Sanyo LCM5327-24NAK

Sanyo LCM5330

#8 Additional 640x480 Color STN-SS LCD - Extended 4-Bit Pack ...............Sharp LM64C031

#9 Additional 640x480 Color STN-DD LCD - 16-Bit Interface......................Sharp LM64C08P

(Panel & Simultaneous Mode Display) Sanyo LCM5331-22NTK

Hitachi LMG9721XUFC

Toshiba TLX-8062S-C3X

Optrex DMF-50351NC-FW

#10 Additional 640x480 16 Internal Gray Scale Plasma....................................Matsushita S804

#11 Additional 640x480 16 Internal Gray Scale EL ..........................................Sharp LJ64ZU50

Table #1 specifies the minimum Extension Register values required for the 65540 / 545 to boot to VGA

mode on an analog CRT monitor.

Table #2 specifies the additional Extension Register values required for emulation of EGA, CGA, MDA

and Hercules backwards compatibility modes. The registers in Table #2 should be used in

conjunction with the registers specified in Table #1. For registers listed in both tables, use the

values in Table #2 (shown in bold text).

Tables #3-11 specify the additional Extension Register values required to support various panels. The registers

in Tables #3-11 should be used in conjunction with the registers specified in Table #1 (and

optionally Table #2). For registers listed in more than one table, use the values in Tables #3-11

(shown in bold text).

Programming

Revision 1.2 197 65540 / 545

Table #1 - Parameters for Initial Boot

Initial Boot-Up Extension Register Values for VGA Display on an Analog CRT Monitor

XR02 01 CPU Interface Control 1

XR04 A1 Memory Control 1 Note 1

XR05 00 Memory Control 2

XR06 00 Palette Control

XR08 00 Linear Addressing Base

XR0B 00 CPU Paging

XR0C 00 Start Address Top

XR0D 00 Auxiliary Offset

XR0E 80 Text Mode Control

XR0F 10 Software Flags 0 Note 2

XR10 00 Single/Low Map

XR11 00 High Map

XR14 00 Emulation Mode

XR15 00 Write Protect

XR16 00 Vertical Overflow

XR17 00 Horizontal Overflow

XR1E 00 Alternate Offset

XR1F 00 Virtual EGA Switch

XR24 12 Alternate Max Scanline

XR25 59 Horizontal Virtual Panel Size

XR28 80 Video Interface

XR29 4C Half Line Compare

XR2B 00 Software Flags 1 Note 2

XR30 03 Clock Divide Control (Initialize Memory Clock)

XR31 6B Clock M-Divisor (Initialize Memory Clock)

XR32 3C Clock N-Divisor (Initialize Memory Clock)

XR33 20 Clock Control (Initialize Memory Clock)

XR30 03 Clock Divide Control (Initialize Clock 2)

XR31 4E Clock M-Divisor (Initialize Clock 2)

XR32 59 Clock N-Divisor (Initialize Clock 2)

XR33 00 Clock Control (Initialize Clock 2)

XR44 10 Software Flags 2 Note 2

XR45 00 Software Flags 3 Note 2

XR51 63 Display Type

XR52 40 Power Down Control

XR53 00 Panel Format 3

XR54 32 Panel Interface

XR5F 06 Power Down Mode Refresh

XR60 88 Blink Rate Control

XR61 2E SmartMap™ Control

XR62 07 SmartMap™ Shift Parameter

XR63 41 SmartMap™ Color Mapping Control

XR70 80 Setup / Disable Control

XR72 24 External Device I/O

Note: 1) Memory Control Register 1 is automatically re-programmed with the proper display memory

configuration by the BIOS

2) The Software Flag Registers are used by the BIOS and should not be re-programmed

Programming

Revision 1.2 198 65540 / 545

Table #2 - Parameters for Emulation Modes

Extension Register Values for CRT-Only, Panel-Only, & Simultaneous CRT / Panel Display

XR14 00 Emulation Mode EGA Emulation

XR15 18 Write Protect EGA Emulation

XR14 01 Emulation Mode CGA Emulation

XR15 0D Write Protect CGA Emulation

XR18 27 Alternate Horizontal Display Enable End CGA Emulation

XR19 2B Alternate Horizontal Retrace Start CGA Emulation

XR1A A0 Alternate Horizontal Retrace End CGA Emulation

XR1B 2D Alternate Horizontal Total CGA Emulation

XR1C 28 Alternate Horizontal Blanking Start CGA Emulation

XR1D 10 Alternate Horizontal Blanking End CGA Emulation

XR1E 14 Alternate Offset CGA Emulation

XR7E 30 CGA / Hercules Color Select CGA Emulation

XR14 52 Emulation Mode MDA Emulation

XR15 0D Write Protect MDA Emulation

XR7E 0F CGA / Hercules Color Select MDA Emulation

XR0D 02 Auxiliary Offset Hercules Emulation

XR14 52 Emulation Mode Hercules Emulation

XR15 0D Write Protect Hercules Emulation

XR18 59 Alternate Horizontal Display Enable End Hercules Emulation

XR19 60 Alternate Horizontal Retrace Start Hercules Emulation

XR1A 8F Alternate Horizontal Retrace End Hercules Emulation

XR1B 6E Alternate Horizontal Total Hercules Emulation

XR1C 5C Alternate Horizontal Blanking Start Hercules Emulation

XR1D 31 Alternate Horizontal Blanking End Hercules Emulation

XR1E 16 Alternate Offset Hercules Emulation

XR7E 0F CGA / Hercules Color Select Hercules Emulation

Note: 1) Bold text indicates registers with values different from those shown in Table #1

2) Non-bold text indicates additional registers (not included in Table #1)

Programming

Revision 1.2 199 65540 / 545

Table #3 - Parameters for 640x480 Monochrome LCD-DD Panels (Panel Mode Only)

Extension Register Values for Epson EG9005F-LS

Citizen G6481L-FF

Sharp LM64P80

Sanyo LCM-6494-24NTK

Hitachi LMG5364XUFC

XR06 02 Palette Control Disable Internal DAC

XR19 57 Alternate Horizontal Sync Start

XR1A 19 Alternate Horizontal Sync End

XR1B 59 Alternate Horizontal Total

XR1C 4F Horizontal Panel Size

XR2C 04 FLM Delay

XR2D 50 LP Delay (CMPR enabled)

XR2E 50 LP Delay (CMPR disabled)

XR2F 00 LP Width

XR4F 44 Panel Format 2

XR50 25 Panel Format 1

XR51 67 Display Type

XR52 41 Power Down Control

XR53 0C Panel Format 3

XR54 3A Panel Interface

XR55 E5 Horizontal Compensation

XR56 00 Horizontal Centering

XR57 1B Vertical Compensation

XR58 00 Vertical Centering

XR59 84 Vertical Line Insertion

XR5A 00 Vertical Line Replication

XR5B 8F Power Sequencing Delay

XR5D 10 FP Diagnostic

XR5E 80 M (ACDCLK) Control

XR64 E4 Alternate Vertical Total

XR65 07 Alternate Overflow

XR66 E0 Alternate Vertical Sync Start

XR67 01 Alternate Vertical Sync End

XR68 DF Vertical Panel Size

XR6C 00 Programmable Output Drive

XR6E 26 Polynomial FRC Control Register Optimize for best display quality

XR6F 1B Frame Buffer Control

Note: 1) Bold text indicates registers with values different from those shown in Table #1

2) Non-bold text indicates additional registers (not included in Table #1)

Programming

Revision 1.2 200 65540 / 545

Table #4 - Parameters for 640x480 Monochrome LCD-DD Panels (Simultaneous Mode Display)

Extension Register Values for Epson EG9005F-LS

Citizen G6481L-FF

Sharp LM64P80

Sanyo LCM-6494-24NTK

Hitachi LMG5364XUFC

XR19 55 Alternate Horizontal Sync Start

XR1A 00 Alternate Horizontal Sync End

XR1B 5F Alternate Horizontal Total

XR1C 4F Horizontal Panel Size

XR2C 21 FLM Delay

XR2D 50 LP Delay (CMPR enabled)

XR2E 50 LP Delay (CMPR disabled)

XR2F 00 LP Width

XR4F 44 Panel Format 2

XR50 25 Panel Format 1

XR51 67 Display Type

XR52 41 Power Down Control

XR53 0C Panel Format 3

XR54 3A Panel Interface

XR55 E5 Horizontal Compensation

XR56 00 Horizontal Centering

XR57 1B Vertical Compensation

XR58 00 Vertical Centering

XR59 84 Vertical Line Insertion

XR5A 00 Vertical Line Replication

XR5B 8F Power Sequencing Delay

XR5D 10 FP Diagnostic

XR5E 80 M (ACDCLK) Control

XR64 0B Alternate Vertical Total

XR65 26 Alternate Overflow

XR66 EA Alternate Vertical Sync Start

XR67 0C Alternate Vertical Sync End

XR68 DF Vertical Panel Size

XR6C 02 Programmable Output Drive

XR6E 26 Polynomial FRC Control Register Optimize For LCD

XR6F 1B Frame Buffer Control

Note: 1) Bold text indicates registers with values different from those shown in Table #1

2) Non-bold text indicates additional registers (not included in Table #1)

Programming

Revision 1.2 201 65540 / 545

Table #5 - Parameters for 640x480 Color TFT Panels (Panel Mode Only)

Extension Register Values for Hitachi TX26D02VC2AA

Sharp LQ9D011 (set to accommodate the DE signal)

Toshiba LTM-09C015-1

XR06 C2 Palette Control Color Reduction

XR19 56 Alternate Horizontal Sync Start

XR1A 13 Alternate Horizontal Sync End

XR1B 5F Alternate Horizontal Total

XR1C 4F Horizontal Panel Size

XR2C 04 FLM Delay

XR2D 4F LP Delay (CMPR enabled)

XR2E 4F LP Delay (CMPR disabled)

XR2F 0F LP Width

XR4F 44 Panel Format 1

XR50 02 Panel Format 2

XR51 C4 Display Type

XR52 41 Power Down Control

XR53 0C Panel Format 3

XR54 FA Panel Interface Set to F9 for Toshiba color panels

XR55 E5 Horizontal Compensation

XR56 00 Horizontal Centering

XR57 1B Vertical Compensation

XR58 00 Vertical Centering

XR59 84 Vertical Line Insertion

XR5A 00 Vertical Line Replication

XR5B 8F Power Sequencing Delay

XR5D 10 FP Diagnostic

XR5E 80 M(ACDCLK) Control

XR64 01 Alternate Vertical Total

XR65 26 Alternate Overflow

XR66 DF Alternate Vertical Sync Start

XR67 0C Alternate Vertical Sync End

XR68 DF Vertical Panel Size

XR6C 02 Programmable Output Drive

XR6E BD Polynomial FRC Control Optimize for best display quality

XR6F 00 Frame Buffer Control

Note: 1) Bold text indicates registers with values different from those shown in Table #1

2) Non-bold text indicates additional registers (not included in Table #1)

Programming

Revision 1.2 202 65540 / 545

Table #6 - Parameters for 640x480 Color TFT Panels ( Simultaneous Mode Display )

Extension Register Values for Hitachi TX26D02VC2AA

Sharp LQ9D011 (set to accommodate the DE signal)

Toshiba LTM-09C015-1

XR06 C0 Palette Control Color Reduction

XR19 55 Alternate Horizontal Sync Start

XR1A 00 Alternate Horizontal Sync End

XR1B 5F Alternate Horizontal Total

XR1C 4F Horizontal Panel Size

XR2C 00 FLM Delay

XR2D 4F LP Delay (CMPR enabled)

XR2E 4F LP Delay (CMPR disabled)

XR2F 0F LP Width

XR4F 44 Panel Format 2

XR50 02 Panel Format 1

XR51 C4 Display Type

XR52 41 Power Down Control

XR53 0C Panel Format 3

XR54 FA Panel Interface Set to F9 for Toshiba color panels

XR55 E5 Horizontal Compensation

XR56 00 Horizontal Centering

XR57 1B Vertical Compensation

XR58 00 Vertical Centering

XR59 84 Vertical Line Insertion

XR5A 00 Vertical Line Replication

XR5B 8F Power Sequencing Delay

XR5D 10 FP Diagnostic

XR5E 80 M (ACDCLK) Control

XR64 0C Alternate Vertical Total

XR65 26 Alternate Overflow

XR66 EA Alternate Vertical Sync Start

XR67 0C Alternate Vertical Sync End

XR68 DF Vertical Panel Size

XR6C 02 Programmable Output Drive

XR6E BD Polynomial FRC Control Optimize for best display quality

XR6F 00 Frame Buffer Control

Note: 1) Bold text indicates registers with values different from those shown in Table #1

2) Non-bold text indicates additional registers (not included in Table #1)

Programming

Revision 1.2 203 65540 / 545

Table #7 - Parameters for 640x480 Color STN-SS Panels with 16-Bit Interface 4-Bit Pack

(Panel & Simultaneous Mode Display)

Extension Register Values for Sanyo LM-CK53-22NEZ

Sanyo LCM5327-24NAK

Sanyo LCM5330

XR06 C2 Palette Control C0 for Simultaneous Display

XR19 56 Alternate Horizontal Sync Start 55 for Simultaneous Display

XR1A 19 Alternate Horizontal Sync End 00 for Simultaneous Display

XR1B 59 Alternate Horizontal Total 5F for Simultaneous Display

XR1C 4F Horizontal Panel Size

XR2C 04 FLM Delay 22 for Simultaneous Display

XR2D 5C LP Delay (CMPR enabled) 62 for Simultaneous Display

XR2E 5C LP Delay (CMPR disabled) 62 for Simultaneous Display

XR2F 5C LP Width 60 for Simultaneous Display

XR4F 44 Panel Format 1

XR50 25 Panel Format 2

XR51 C4 Display Type

XR52 41 Power Down Control

XR53 1C Panel Format 3

XR54 3A Panel Interface

XR55 E5 Horizontal Compensation

XR56 00 Horizontal Centering

XR57 1B Vertical Compensation

XR58 00 Vertical Centering

XR59 84 Vertical Line Insertion

XR5A 00 Vertical Line Replication

XR5B 8F Power Sequencing Delay

XR50 10 Panel Format 1

XR5E 80 M (ACDCLK) Control

XR64 E4 Alternate Vertical Total 0B for Simultaneous Display

XR65 07 Alternate Overflow 26 for Simultaneous Display

XR66 E1 Alternate Vertical Sync Start EA for Simultaneous Display

XR67 02 Alternate Vertical Sync End 0C for Simultaneous Display

XR68 DF Vertical Panel Size

XR6C 02 Programmable Output Drive

XR6E 61 Polynomial FRC Control Optimize for best display quality

XR6F 00 Frame Buffer Control

Note: 1) Bold text indicates registers with values different from those shown in Table #1

2) Non-bold text indicates additional registers (not included in Table #1)

Programming

Revision 1.2 204 65540 / 545

Table #8 - Parameters for 640x480 Color STN-SS Panels with 8-Bit Interface (Extended 4-Bit Pack)

Extension Register Values for Sharp LM64C031

XR06 C2 Palette Control C0 simultaneous mode

XR19 56 Alternate Horizontal Sync Start 55 simultaneous mode

XR1A 00 Alternate Horizontal Sync End

XR1B 59 Alternate Horizontal Total 5F simultaneous mode

XR1C 4F Horizontal Panel Size

XR2C 02 FLM Delay 2B simultaneous mode

XR2D 50 LP Delay (CMPR enabled)

XR2E 50 LP Delay (CMPR disabled)

XR2F 00 LP Width

XR4F 44 Panel Format 2

XR50 15 Panel Format 1

XR51 6C Display Type

XR52 41 Power Down Control

XR53 3C Panel Format 3

XR54 3A Panel Interface

XR55 E5 Horizontal Compensation

XR56 00 Horizontal Centering

XR57 1B Vertical Compensation

XR58 00 Vertical Centering

XR59 84 Vertical Line Insertion

XR5A 00 Vertical Line Replication

XR5B 8F Power Sequencing Delay

XR5D 10 FP Diagnostic

XR5E 80 M (ACDCLK) Control

XR64 E8 Alternate Vertical Total 15 simultaneous mode

XR65 07 Alternate Overflow 26 simultaneous mode

XR66 E1 Alternate Vertical Sync Start EA simultaneous mode

XR67 02 Alternate Vertical Sync End 0C simultaneous mode

XR68 DF Vertical Panel Size

XR6C 02 Programmable Output Drive

XR6E 36 Polynomial FRC Control Optimize for best display quality

XR6F 00 Frame Buffer Control

Note: 1) Bold text indicates registers with values different from those shown in Table #1

2) Non-bold text indicates additional registers (not included in Table #1)

Programming

Revision 1.2 205 65540 / 545

Table #9 - Parameters for 640x480 Color STN-DD Panels with 16-Bit Interface with Frame Acceleration

(Panel & Simultaneous Mode Display)

Extension Register Values for Sharp LM64C08P

Sanyo LCM5331-22NTK

Hitachi LMG9721XUFC

Toshiba TLX-8062S-C3X

Optrex DMF-50351NC-FW

XR06 C2 Palette Control

XR19 57 Alternate Horizontal Sync Start

XR1A 19 Alternate Horizontal Sync End

XR1B 59 Alternate Horizontal Total

XR1C 4F Horizontal Panel Size

XR2C 15 FLM Delay 22 for no frame acceleration

XR2D 50 LP Delay (CMPR enabled) 9E for no frame acceleration

XR2E 50 LP Delay (CMPR disabled)

XR2F 00 LP Width

XR4F 04 Panel Format 1

XR50 25 Panel Format 2 35 for no frame acceleration

XR51 67 Display Type

XR52 41 Power Down Control

XR53 1C Panel Format 3

XR54 3A Panel Interface

XR55 E5 Horizontal Compensation

XR56 00 Horizontal Centering

XR57 1B Vertical Compensation

XR58 00 Vertical Centering

XR59 1F Vertical Line Replication

XR5A 00 Vertical Line Replication

XR5B 8F Power Sequencing Delay

XR5D 10 FP Diagnostic

XR5E 80 M (ACDCLK) Control

XR64 0B Alternate Vertical Total

XR65 07 Alternate Overflow

XR66 EA Alternate Vertical Sync Start

XR67 0C Alternate Vertical Sync End

XR68 DF Vertical Panel Size

XR6C 02 Programmable Output Drive

XR6E 33 Polynomial FRC Control Optimize for best display quality.

XR6F 1B Frame Buffer Control 9F for external frame buffer with frame

acceleration. 99 for external frame buffer

without frame acceleration.

Note: 1) Bold text indicates registers with values different from those shown in Table #1

2) Non-bold text indicates additional registers (not included in Table #1)

Programming

Revision 1.2 206 65540 / 545

Table #10 - Parameters for 640x480 Plasma Panels with 16 Internal Gray Levels

Extension Register Values for Matsushita S804

XR19 60 Alternate Horizontal Sync Start

XR1A 00 Alternate Horizontal Sync End

XR1B 60 Alternate Horizontal Total

XR1C 4F Horizontal Panel Size

XR2C 04 FLM Delay

XR2D 62 LP Delay (CMPR enabled)

XR2E 6D LP Delay (CMPR disabled)

XR2F 08 LP Width

XR4F 04 Panel Format 1

XR50 17 Panel Format 2

XR51 C4 Display Type

XR52 41 Power Down Control

XR53 0C Panel Format 3

XR54 39 Panel Interface

XR55 E5 Horizontal Compensation

XR56 00 Horizontal Centering

XR57 1B Vertical Compensation

XR58 00 Vertical Centering

XR59 84 Vertical Line Insertion

XR5A 00 Vertical Line Replication

XR5B 8F Power Sequencing Delay

XR5D 10 FP Diagnostic

XR5E 80 M (ACDCLK) Control

XR64 0D Alternate Vertical Total

XR65 26 Alternate Overflow

XR66 E8 Alternate Vertical Sync Start

XR67 0A Alternate Vertical Sync End

XR68 DF Vertical Panel Size

XR6C 02 Programmable Output Drive

XR6E 0D Polynomial FRC Control Optimize for best display quality

XR6F 00 Frame Buffer Control

Note: 1) Bold text indicates registers with values different from those shown in Table #1

2) Non-bold text indicates additional registers (not included in Table #1)

Programming

Revision 1.2 207 65540 / 545

Table # 11 - Parameters for 640x480 EL Panels with 16 Internal Gray Levels

Extension Register Values for Sharp LJ64ZU50

XR19 52 Alternate Horizontal Sync Start

XR1A 15 Alternate Horizontal Sync End

XR1B 54 Alternate Horizontal Total

XR1C 4F Horizontal Panel Size

XR2C 0C FLM Delay

XR2D 4F LP Delay (CMPR enabled)

XR2E 4E LP Delay (CMPR disabled)

XR2F 81 LP Width

XR4F 04 Panel Format 1

XR50 17 Panel Format 2

XR51 44 Display Type

XR52 41 Power Down Control

XR53 0C Panel Format 3

XR54 F9 Panel Interface

XR55 E5 Horizontal Compensation

XR56 00 Horizontal Centering

XR57 1B Vertical Compensation

XR58 00 Vertical Centering

XR59 84 Vertical Line Insertion

XR5A 00 Vertical Line Replication

XR5B 8F Power Sequencing Delay

XR5D 10 FP Diagnostic

XR5E 80 M (ACDCLK) Control

XR64 F0 Alternate Vertical Total

XR65 07 Alternate Overflow

XR66 E5 Alternate Vertical Sync Start

XR67 05 Alternate Vertical Sync End

XR68 DF Vertical Panel Size

XR6C 02 Programmable Output Drive

XR6E 9D Polynomial FRC Control Optimize for best display quality

XR6F 00 Frame Buffer Control

Note: 1) Bold text indicates registers with values different from those shown in Table #1

2) Non-bold text indicates additional registers (not included in Table #1)

Programming

Revision 1.2 208 65540 / 545

Programming

This section includes schematic examples showing various 65540 / 65545 interfaces. The schematics are divided

into into three main groups:

1) System Bus Interface

•ISA (PC/AT) Bus (16-bit)

•VL-Bus / 486 CPU-Direct Local Bus (1x Clock) (32-bit)

• PCI Local Bus (32-bit)

2) Display Memory Interface

3) CRT / Panel / Video Interface

To design a system around the 65540 or 65545, one schematic page would be selected from each of the groups

above.

Selection of a bus interface for the VGA controller is generally dictated by the type of bus and CPU available in the

system. If performance is a concern, however, and a 386 or 486 CPU is being used, a local bus interface should

be considered and linear addressing support should be implemented. Linear addressing improves performance in

GUI environments such as Windows™ by allowing the software used to access display memory (typically the

Windows Driver) to be more efficient. Clock connections are shown as part of the bus interface diagrams. A

14.31818 MHz reference crystal is shown, although if a clean source of 14.31818 MHz is available in the system,

it may be input on XTALI and the crystal would then not be required.

Generally, 256Kx16 DRAMs would be used for display memory, although, if desired, the memory interface may

be designed to use 256Kx4's instead. 256Kx16 DRAMs come in two types: one write enable (WE#) with two

CAS# inputs (one for the high byte and one for the low byte) or one CAS# input with two write enables (one for

the high byte and one for the low byte). Either variety of DRAM may be used (default is to the 2-CAS variety with

a programming option in the 65540 / 545 to change the memory control outputs for compatibility with either type).

CHIPS' BIOS is able to detect which type is connected and program the controller accordingly. It is also possible

to lay out a PCB to allow either type to be used. The memory interface diagram also shows how to interface the

6554x to CHIPS' PC-Video products to provide live video overlay capability.

An interface diagram is included showing connections to a standard CRT display. Panel interfaces, however, are

not as standardized (generally every panel interface is different). To show how to interface to a wide variety of

commonly available panels, the interface diagram in this section shows the connections used on CHIPS' DK

(Development Kit) Printed Circuit Board from the 6554x chip to connectors defined by CHIPS on that board. In

the following section of this document, examples are included showing connections from those DK board

connectors to a number of typical panels. The DK board connectors are used to simplify evaluation of the 6554x

with various panels; a real system would not typically use the connectors shown, but would instead interface

directly to the connector(s) used by the panel manufacturer.

Revision 1.2 209 65540 / 545

Application Schematic Examples

Use as ACTI

Use as ROMCS# if required

14.31818

MHz

+5V = B3, B29, D16

GND = B1, B10,B31,D18

Use as ENABKL

A02

A03

A04

A05

A06

A07

A08

A09

C11

C12

C13

C14

C15

C16

C17

C18

B28

B02

B19

C01

A11

B13

B14

C10

C09

A10

B04

D02

D01

33 ohm

0.01uF

C02

C03

C04

C05

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

B08 D15

D14

D13

D12

D11

D10

A11

A10

BE2#

BE0#

A16

A15

A14

A13

A12

A17

A18

A19

LRDY#

LDEV#

W/R#

A25

RRTN#

LCLK

BE3#

BE1#

RESET#

A24

65540

65545

ADS#

A20

A21

A22

A23

D23

D22

D21

D20

D19

D18

D17

D16

D27

D26

D25

D24

D31

D30

D29

D28

Bus

Interface

XTALI

XTALO

A26

A27

M/IO#

Default

(CRST) <MEMW#>

<A1>

<A0>

<RFSH#>

<BHE#>

<A11>

<A10>

<A9>

<A8>

<A7>

<A6>

<A5>

<A4>

<A3>

<A2>

<A16>

<A15>

<A14>

<A13>

<A12>

<LA17>

<LA18>

<LA19>

<IRQ>

<ROMCS#>

<LA20>

<LA21>

<LA22>

<LA23>

(ACTI)

(ENABKL)

<IOWR#>

<RDY>

<IORD#>

<MEMR#>

<AEN>

<ALE>

ISA Bus

"PAR"

"FRAME#"

PCI Bus

"IRDY#"

"DEVSEL#"

"TRDY#"

"STOP#"

"IDSEL"

"SERR#"

"PERR#"

"Reserved"

"CLK"

"Reserved"

"C/BE3#"

"C/BE2#"

"C/BE1#"

"C/BE0#"

"AD31"<Reserved>

<IOCS16#>

<MCS16#>

<ZWS#>

<D15>

<D14>

<D13>

<D12>

<D11>

<D10>

<D9>

<D8>

<D7>

<D6>

<D5>

<D4>

<D3>

<D2>

<D1>

<D0>

"AD15"

"AD14"

"AD13"

"AD12"

"AD11"

"AD10"

"AD9"

"AD8"

"AD7"

"AD6"

"AD5"

"AD4"

"AD3"

"AD2"

"AD1"

"AD0"

"AD23"

"AD22"

"AD21"

"AD20"

"AD19"

"AD18"

"AD17"

"AD16"

"AD27"

"AD26"

"AD25"

"AD24"

"AD30"

"AD29"

"AD28"

Names

Indicate

VL-Bus

or 1x/2x

486 CPU

Direct

(2XCLK)

Local Bus

(65545 Only)

RESET

33D15 34D14 35D13 36D12 37D11 38D10 40D09 41D08 44D07 45D06 46D05 47D04 48D03 49D02 50D01 51D00

198A19 197A18 196A17 195A16 194A15 193A14 192A13 191A12 190A11 189A10 188A9 187A8 186A7 185A6 183A5 182A4 180A3 179A2

21A1

43A0

207

32BHE#

23MEMW#

11MEMR#

25IOWR#

27IORD#

31AEN

10RFSH#

24RDY

22ALE

199LA20 200LA21 201LA22 28LA23

20ZWS# 19MEMCS16# 18IOCS16# 17

203

204

30IRQ9 53

Revision 1.2 210 65540 / 545

Application Schematic Examples

NOTE: The 6554x may be configured for ISA operation by connecting pin

146 (AA1/ISA#) to GND via a 4.7K resistor.

NOTE: Can use external 14.31818MHz oscillator into XTALI (with XTALO

not connected) by connecting pin 150 (AA5/OC#) to GND via a

4.7K resistor.

NOTE: Additional data output drive may be enabled by programming

XR6C bit 3=0.

Circuit Example

6554x ISA Bus Interface

To Local Bus Control Logic

or ACTI

or ENABKL

196pin PQFP

486 S-Series 14.31818 MHz

Cx486S/S2

486DX/SX

To Systems Logic

CPU-P1

CPU-N2

CPU-N1

CPU-H2

CPU-M3

CPU-J2

CPU-L2

CPU-L3

CPU-F2

CPU-D1

CPU-E3

CPU-C1

CPU-G3

CPU-D2

CPU-K3

CPU-F3

CPU-K15

CPU-J15

CPU-F16

CPU-N17

CPU-C3

CPU-S17

CPU-N16

CPU-J3

CPU-D3

CPU-C2

CPU-B1

CPU-A1

CPU-B2

CPU-A2

CPU-A4

CPU-A6

CPU-B6

CPU-C7

CPU-C6

CPU-C8

CPU-A8

CPU-C9

CPU-B8

CPU-Q14

CPU-R15

CPU-S16

CPU-Q12

CPU-S15

CPU-Q13

CPU-R13

CPU-Q11

CPU-S13

CPU-R12

CPU-S7

CPU-Q10

CPU-S5

CPU-R7

CPU-Q9

CPU-Q3

CPU-R5

CPU-Q4

CPU-Q8

CPU-Q5

CPU-Q7

CPU-S3

CPU-F17

CPU-J16

CPU-??

VL-B31

VL-A31

VL-B33

VL-A32

VL-B34

VL-A33

VL-B35

VL-A34

VL-B36

VL-A36

VL-B37

VL-A37

VL-B39

VL-B40

VL-B24

VL-A23

VL-B25

VL-A25

VL-B26

VL-A26

VL-B27

VL-A28

VL-B28

VL-A29

VL-B30

VL-A30

VL-A41

VL-A39

VL-A44

VL-A42

VL-B44

VL-A45

VL-B45

VL-B56

VL-B42

VL-B48

VL-A48

VL-A49

VL-A09

VL-B10

VL-A08

VL-B08

VL-A07

VL-B07

VL-A06

VL-B05

VL-A05

VL-B04

VL-A04

VL-B03

VL-A02

VL-B02

VL-A20

VL-B19

VL-A19

VL-B18

VL-A18

VL-B17

VL-A16

VL-B16

VL-A15

VL-B15

VL-A14

VL-B13

VL-A13

VL-B12

VL-A11

VL-B11

VL-A01

VL-B01

CPU-133

CPU-120

CPU-123

CPU-145

CPU-111

CPU-17

CPU-18

CPU-20

CPU-23

CPU-25

CPU-26

CPU-27

CPU-29

CPU-31

CPU-32

CPU-35

CPU-37

CPU-38

CPU-39

CPU-41

CPU-42

CPU-117

CPU-115

CPU-44

CPU-45

CPU-46

CPU-47

CPU-48

CPU-51

CPU-53

CPU-55

CPU-59

CPU-61

CPU-63

CPU-65

CPU-67

CPU-69

CPU-71

CPU-74

CPU-146

CPU-150

CPU-152

CPU-154

CPU-158

CPU-159

CPU-161

CPU-113

CPU-116

CPU-163

CPU-165

CPU-172

CPU-174

CPU-176

CPU-178

CPU-180

CPU-181

CPU-183

CPU-189

CPU-191

CPU-193

CPU-2

CPU-3

CPU-4

CPU-5

CPU-7

CPU-8

CPU-9

D15

D14

D13

D12

D11

D10

A11

A10

BE2#

BE0#

A16

A15

A14

A13

A12

A17

A18

A19

LRDY#

LDEV#

W/R#

A25

RRTN#

LCLK

BE3#

BE1#

RESET#

A24

65540

65545

ADS#

A20

A21

A22

A23

D23

D22

D21

D20

D19

D18

D17

D16

D27

D26

D25

D24

D31

D30

D29

D28

Bus

Interface

XTALI

XTALO

A26

A27

M/IO#

Default

(CRST) <MEMW#>

<A1>

<A0>

<RFSH#>

<BHE#>

<A11>

<A10>

<A9>

<A8>

<A7>

<A6>

<A5>

<A4>

<A3>

<A2>

<A16>

<A15>

<A14>

<A13>

<A12>

<LA17>

<LA18>

<LA19>

<IRQ>

<ROMCS#>

<LA20>

<LA21>

<LA22>

<LA23>

(ACTI)

(ENABKL)

<IOWR#>

<RDY>

<IORD#>

<MEMR#>

<AEN>

<ALE>

ISA Bus

"PAR"

"FRAME#"

PCI Bus

"IRDY#"

"DEVSEL#"

"TRDY#"

"STOP#"

"IDSEL"

"SERR#"

"PERR#"

"Reserved"

"CLK"

"Reserved"

"C/BE3#"

"C/BE2#"

"C/BE1#"

"C/BE0#"

"AD31"<Reserved>

<IOCS16#>

<MCS16#>

<ZWS#>

<D15>

<D14>

<D13>

<D12>

<D11>

<D10>

<D9>

<D8>

<D7>

<D6>

<D5>

<D4>

<D3>

<D2>

<D1>

<D0>

"AD15"

"AD14"

"AD13"

"AD12"

"AD11"

"AD10"

"AD9"

"AD8"

"AD7"

"AD6"

"AD5"

"AD4"

"AD3"

"AD2"

"AD1"

"AD0"

"AD23"

"AD22"

"AD21"

"AD20"

"AD19"

"AD18"

"AD17"

"AD16"

"AD27"

"AD26"

"AD25"

"AD24"

"AD30"

"AD29"

"AD28"

Names

Indicate

VL-Bus

or 1x/2x

486 CPU

Direct

(2XCLK)

Local Bus

(65545 Only)

CPUCLK

MIO#

RDY#

SYSRESET#

33D15D15 34D14D14 35D13D13 36D12D12 37D11D11 38D10D10 40D09D09 41D08D08 44D07D07 45D06D06 46D05D05 47D04D04 48D03D03 49D02D02 50D01D01 51D00D00

198A19A19 197A18A18 196A17A17 195A16A16 194A15A15 193A14A14 192A13A13 191A12A12 190A11A11 189A10A10 188A09 187A08 186A07 185A06 183A05 182A04 180A03 179A02

21BE2#BE2#

43BE0#BE0#

29A24A24

207RESET#

32BE1#BE1#

23RDYRTN#

11W/R#W/R#

25LDEV#

27LCLK

31M/IO#

10BE3#BE3#

24LRDY#

22ADS#ADS#

199A20A20 200A21A21 201A22A22 28A23A23

20D16D16 19D17D17 18D18D18 17D19D19 16D20D20 15D21D21 14D22D22 13D23D23 8D24D24 7D25D25 6D26D26 5D27D27 4D28D28 3D29D29 2D30D30 1D31D31

203

204

30A25A25 53A26A26 54A27A27

Application Schematic Examples

Revision 1.2 211 65540 / 545

Circuit Example

6554x VL-Bus / 486

CPU Direct Local

Bus Interface

Use as ACTI & ENABKL

14.318 MHz

n/c

65545

IVcc

Pins

PCI-A15

PCI-A26

PCI-A34

PCI-B35

PCI-B39

PCI-A41

PCI-A40

PCI-B16

PCI-B20

PCI-A20

PCI-B21

PCI-A22

PCI-B23

PCI-A23

PCI-B24

PCI-A25

PCI-B27

PCI-A28

PCI-B29

PCI-A29

PCI-B30

PCI-A31

PCI-B32

PCI-A32

PCI-A44

PCI-B45

PCI-A46

PCI-B47

PCI-A47

PCI-B48

PCI-A49

PCI-B52

PCI-B53

PCI-A54

PCI-B55

PCI-A55

PCI-B56

PCI-A57

PCI-B58

PCI-A58

PCI-B26

PCI-B33

PCI-B44

PCI-A52

PCI-A10

PCI-A16

PCI-B19

PCI-A59

PCI-B59

PCI-B03

PCI-B17

PCI-A18

PCI-B22

PCI-A24

PCI-B28

PCI-A30

PCI-B34

PCI-A35

PCI-A37

PCI-B38

PCI-A42

PCI-B46

PCI-A48

PCI-B49

PCI-A56

PCI-B57

PCI-A05

PCI-B05

PCI-B06

PCI-A08

PCI-A61

PCI-B61

PCI-A62

PCI-B62

PCI-A12

PCI-B12

PCI-A13

PCI-B13

PCI-A50

PCI-B50

PCI-A51

PCI-B51

PCI-A21

PCI-B25

PCI-A27

PCI-B31

PCI-A33

PCI-B36

PCI-A39

PCI-B41

PCI-B43

PCI-A45

PCI-A53

PCI-B54

PCI-B60

PCI-A60

PCI-A17

PCI-B18

PCI-A01

PCI-B02

PCI-A03

PCI-B04

PCI-A04

PCI-A07

PCI-B07

PCI-A06

PCI-A02

PCI-B01

PCI-B37

PCI-A38

PCI-A36

PCI-A43

PCI-B40

PCI-B42

PCI-B09

PCI-B11

PCI-A09

PCI-B10

PCI-A11

PCI-A14

PCI-B14

PCI-A19

PCI-B15

PCI-B08

D15

D14

D13

D12

D11

D10

A11

A10

BE2#

BE0#

A16

A15

A14

A13

A12

A17

A18

A19

LRDY#

LDEV#

W/R#

A25

RRTN#

LCLK

BE3#

BE1#

RESET#

A24

65545

ADS#

A20

A21

A22

A23

D23

D22

D21

D20

D19

D18

D17

D16

D27

D26

D25

D24

D31

D30

D29

D28

Bus

Interface

XTALI

XTALO

A26

A27

M/IO#

Default

(CRST) <MEMW#>

<A1>

<A0>

<RFSH#>

<BHE#>

<A11>

<A10>

<A9>

<A8>

<A7>

<A6>

<A5>

<A4>

<A3>

<A2>

<A16>

<A15>

<A14>

<A13>

<A12>

<LA17>

<LA18>

<LA19>

<IRQ>

<ROMCS#>

<LA20>

<LA21>

<LA22>

<LA23>

(ACTI)

(ENABKL)

<IOWR#>

<RDY>

<IORD#>

<MEMR#>

<AEN>

<ALE>

ISA Bus

"PAR"

"FRAME#"

PCI Bus

"IRDY#"

"DEVSEL#"

"TRDY#"

"STOP#"

"IDSEL"

"SERR#"

"PERR#"

"Reserved"

"CLK"

"Reserved"

"C/BE3#"

"C/BE2#"

"C/BE1#"

"C/BE0#"

"AD31"<Reserved>

<IOCS16#>

<MCS16#>

<ZWS#>

<D15>

<D14>

<D13>

<D12>

<D11>

<D10>

<D9>

<D8>

<D7>

<D6>

<D5>

<D4>

<D3>

<D2>

<D1>

<D0>

"AD15"

"AD14"

"AD13"

"AD12"

"AD11"

"AD10"

"AD9"

"AD8"

"AD7"

"AD6"

"AD5"

"AD4"

"AD3"

"AD2"

"AD1"

"AD0"

"AD23"

"AD22"

"AD21"

"AD20"

"AD19"

"AD18"

"AD17"

"AD16"

"AD27"

"AD26"

"AD25"

"AD24"

"AD30"

"AD29"

"AD28"

Names

Indicate

VL-Bus

or 1x/2x

486 CPU

Direct

(2XCLK)

Local Bus

Keyway

REQ64#

ACK64#

REQ#

GNT#

+3.3V

TMS

TCK

TDO

TDI

SDONE

SBO#

LOCK#

+V-I/O

+5V

+5V+5V

+5V

+5V+5V

+5V

+12V

–12V

PRSNT2#

PRSNT1#

Reserved

TRST#

INTD#

INTC#

INTB#

INTA#

33AD15 34AD14 35AD13 36AD12 37AD11 38AD10 40AD09 41AD08 44AD07 45AD06 46AD05 47AD04 48AD03 49AD02 50AD01 51AD00

198

197

196

195

194

193

192

191

190

189

188

187

186

185

183

182

180

179

199

200

21C/BE2#

43C/BE0#

29PERR#

207RST#

32C/BE1#

23IRDY#

11IDSEL

25DEVSEL#

27STOP#

31PAR

10C/BE3#

24TRDY#

22FRAME#

201CLK

20AD16 19AD17 18AD18 17AD19 16AD20 15AD21 14AD22 13AD23 8AD24 7AD25 6AD26 5AD27 4AD28 3AD29 2AD30 1AD31

203

204

30SERR# 53

Application Schematic Examples

Revision 1.2 212 65540 / 545

Circuit Example

65545 Interface to

PCI Local Bus

NOTE: Can use external

14.31818MHz

oscillator into

XTALI (with

XTALO not

connected) by

connecting pin

150 (AA5/OC#)

to GND via a

4.7K resistor.

Revision 1.2 213 65540 / 545

Application Schematic Examples

n/c

DRAM "C" Not Installed

16 / 18 / 24-Bit PC-Video

16 / 18 / 24-Bit TFT Panels

No ACTI feature w/24-bit

No ENABKL feature w/24-bit

26-bit VL-Bus address range

with 18 / 24-bit PC-Video

(up to 28-bit w/16-bit video)

J3 DK PCB

Panel

Connector

J2 DK PCB

PC-Video

Connector

DRAM

"C"

Optional

DRAM

"B"

Optional

DRAM

"A"

Used for improving performance

with color DD STN panels

in simultaneous display mode

(PC-Video port not available &

panel interface limited to 16-bit

when DRAM "C" is used)

Provides base 512KB embedded

frame buffer & display memory

Provides additional 512KB embedded

frame buffer & display memory

RAS

WE DRAM

D15:0

A8:0

256K

CU x16

RAS

WE DRAM

D15:0

A8:0

256K

CU x16

RAS

WE DRAM

D15:0

A8:0

256K

CU x16

MCD15-0

RASC#

CASCH#

CA8-0

WEC#

65540 / 545

CASBH#

CASBL#

CASCL#

MAD15-0

RASA#

CASAH#

AA8-0

WEA#

CASAL#

(VR5-2,VG7-2,VB7-2)

OEC#

(CASA#)

(WEAL#)

(WEAH#)

(CASC#)

(WECL#)

(WECH#)

RASB#

(KEY)

(VG1,P23-16)

(CFG8-0)

WEB#

(WEBL#)

(CASB#)

OEAB#

(WEBL#)

(VR7)

(VR6)

(PCLK)

(VR1)

MBD15-0

ACTI(VB0) ENABKL(VB1) (A26)

(A27)(GPIO0)

(GPIO1)

AA9(VR0) CA9(VG0)

VSYNC

HSYNC

J3–49

J3–48

J3–46

J3–45

J3–43

J3–42

J3–40

J3–39

J2–42

J2–44

J2–46

J2–48

J2–6

J2–50

J2–41

J2–43

J2–45

J2–47

J2–49

J2–5J2–8

J2–10

J2–12

J2–14

J2–16

J2–11

J2–13

J2–7

J2–9

J2–15

P16

P17

P18

P19

P20

P21

P22

P23

J2–18 J2–17J2–20

J2–22

J2–24

J2–26

J2–28

J2–23

J2–25

J2–19

J2–21

J2–27

J2–30 J2–29J2–32

J2–34

J2–36

J2–38

J2–40

J2–35

J2–37

J2–31

J2–33

J2–39

VR2

VR3

VR4

VR5

VG2

VG3

VG4

VG5

VG6

VG7

VB2

VB3

VB4

VB5

VB6

VB7

VG1

J2–4

J2–2 J2–1

J2–3

VB2

VB3

VB4

VB5

VB6

VB7

VG2

VG3

VG4

VG5

VG6

VG7

VR2

VR3

VR4

VR5

VG1

P16

P17

P18

P19

P20

P21

P22

P23

156

159

160

157

125

126

123

124

155

VB0

VB1

VG0

HSYNC

101

KEY

VSYNC

102

PCLK

100

VR1

104

VR6

103

VR7

154

VR0

Reserved

Circuit Example

Display Memory / PC-Video Circuit

The following bits effect the

DRAM / PC-Video interface:

Display Int Ext

Mem FB FB

XR04[1-0] 00 A&B A&B Opt

01 A A Opt

10 A&C A n/a

11 ---- Reserved ----

XR6F[7] 0=FB in DRAMs A/B

1=FB in DRAM C

XR6F[2] 0=Sym Addr (C)

1=Asym Addr (C)

XR05[3] 0=Sym Addr (A/B)

1=Asym Addr (A/B)

XR05[4] 0=2C/1W (A/B)

1=1C/2W (A/B)

XR05[5] 0=2C/1W (C)

1=1C/2W (C)

XR05[6] PC-Video Port Enable

XR05[7] 0=18-bit PC-Video

1=24-bit PC-Video

XR6C[4] 2x Output Drive (A/B)

XR6C[5] 2x Output Drive (C)

Revision 1.2 214 65540 / 545

Application Schematic Examples

15K

J1 = CRT Analog Video 15-Pin Connector

(LD3)

(LD2)

(LD1)

(LD0)

(UD3)

(UD2)

(UD1)

(UD0)

150, 2%

uF 0.1 0.047

4.7 uH

1% RL

n/c

(MS0) n/c

Rset

(BLANK#) (DE)

J5 = DK PCB

26-Pin Connector

(BLANK#) (DE)

J3 = DK PCB

50-Pin Connector

n/c

From System Power Control Circuitry

(Tie high if not used)

Panel Power

Control Circuitry

To System Power Control Circuitry (Leave unconnected if not used)

270 Ω

(MS2) n/c

(MS1)ACTI**

(MS3)ENABKL*

Note: DDC2CLK*

DDCDAT** 5V

Digital Ground

Analog Ground

J1-1

J1-2

J1-3

J1-6

J1-7

J1-8

J1-10

J1-5

J1-9

J1-15

J1-11

J1-12

J1-4

J3-25

J3-24

J3-22

J3-21

J3-19

J3-18

J3-16

J3-15

J1-13

J1-14

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

220pF

.001uF

J5-19

J5-21

J5-23

J5-25

J5-11

J5-13

J5-15

J5-17

J3-39

J3-40 J5-14

J5-16

J5-18

J5-20

J5-22

J5-24

J5-7

J5-26

J3-13

J3-7

J3-10

J3-11

J5-9

J5-1

J5-5

J5-3

J5-2J3-8

J5-4J3-5

J5-8

J5-12

J5-6

J3-1

J3-3 J5-10J3-2

J3-4

J3-42

J3-43

J3-45

J3-46

J3-48

J3-49

P11

P10

ENAVDD

(BLANK#)

FLM

SHFCLK

STNDBY#

HSYNC

VSYNC

(DE)

ENABKL

RSET

AVCC

AGND

65540

Flat Panel

VGA Controller

ENAVEE

P15

P14

P13

P12

(GPIO1)*

(BLANK#) (DE)

(ENABKL)

(GPIO0)** ACTI

(A27)

(A26)

65545

(P17)

(P16)

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

(P19)

(P18)

(P21)

(P20)

(P23)

(P22)

(DDC1CLK)

+5V

HSYNC

VSYNC

DE DE

VEESAFE VEESAFE

12VSAFE 12VSAFE

VDDSAFE VDDSAFE

Reserved

ENABKL ENABKL

71 P0 P0

72 P1 P1

73 P2 P2

74 P3 P3

75 P4 P4

76 P5 P5

78 P6 P6

79 P7 P7

68 LP LP

67 FLM FLM

69 M M

70 SHFCLK SHFCLK

178

81 P8

82 P9

83 P10

84 P11

85 P12

86 P13

87 P14

88 P15

90 P16

91 P17

92 P18

93 P19

94 P20

95 P21

96 P22

97 P23

65540 / 545 CRT / Panel Interface Circuit

Rset= 5.4* Rload Rload = RL * 75

RL + 75

For RL=75: Rset=202Ω

For RL=150: Rset=270Ω

This section includes schematic examples showing how to connect the 65540 / 545 to various flat panel displays.

Plasma / EL Panels Panel

Panel Panel Panel Panel Panel Data Gray

Mfr Part Number Resolution Technology Drive Interface Transfer Levels Page

1) Matsushita S804 640x480 Plasma SS 8-bit 2 Pixels/Clk 16 217

2) Sharp LJ64ZU50 640x480 EL SS 8-bit 2 Pixels/Clk 16 218

Monochrome LCD Panels Panel

Panel Panel Panel Panel Panel Data Gray

Mfr Part Number Resolution Technology Drive Interface Transfer Levels Page

3) Epson EG-9005F-LS 640x480 LCD DD 8-bit 8 Pixels/Clk 2 219

4) Citizen G6481L-FF 640x480 LCD DD 8-bit 8 Pixels/Clk 2 220

5) Sharp LM64P80 640x480 LCD DD 8-bit 8 Pixels/Clk 2 221

6) Sanyo LCM-6494-24NTK 640x480 LCD DD 8-bit 8 Pixels/Clk 2 222

7) Hitachi LMG5364XUFC 640x480 LCD DD 8-bit 8 Pixels/Clk 2 223

8) Sanyo LCM-5491-24NAK 1024x768 LCD DD 16-bit 16 Pixels/Clk 2 224

9) Epson ECM-A9071 1024x768 LCD DD 16-bit 16 Pixels/Clk 2 225

Active Color Panels Panel Panel Panel Panel Panel Data Panel

Mfr Part Number Resolution Technology Drive Interface Transfer Colors Page

10) Hitachi TM26D50VC2AA 640x480 TFT LCD SS 9-bit 1 Pixel/Clk 512 226

11) Sharp LQ9D011 640x480 TFT LCD SS 9-bit 1 Pixel/Clk 512 227

12) Toshiba LTM-09C015-1 640x480 TFT LCD SS 9-bit 1 Pixel/Clk 512 228

13) Sharp LQ10D311 640x480 TFT LCD SS 18-bit 1 Pixel/Clk 256K 229

14) Sharp LQ10DX01 1024x768 TFT LCD SS 18-bit 2 Pixels/Clk 512 230

Passive Color Panels Panel Panel Panel Panel Panel Data Panel

Mfr Part Number Resolution Technology Drive Interface Transfer Colors Page

15) Sanyo LM-CK53-22NEZ 640x480 STN LCD SS 16-bit 5-1/3 Pixels/Clk 8 231

16) Sanyo LCM5327-24NAK 640x480 STN LCD SS 16-bit 5-1/3 Pixels/Clk 8 232

17) Sharp LM64C031 640x480 STN LCD SS 8-bit 2-2/3 Pixels/Clk 8 233

18) Kyocera KCL6448 640x480 STN LCD DD 8-bit 2-2/3 Pixels/Clk 8 234

19) Hitachi LMG9720XUFC 640x480 STN LCD DD 8-bit 2-2/3 Pixels/Clk 8 235

20) Sharp LM64C08P 640x480 STN LCD DD 16-bit 5-1/3 Pixels/Clk 8 236

21) Sanyo LCM5331-22NTK 640x480 STN LCD DD 16-bit 5-1/3 Pixels/Clk 8 237

22) Hitachi LMG9721XUFC 640x480 STN LCD DD 16-bit 5-1/3 Pixels/Clk 8 238

23) Toshiba TLX-8062S-C3X 640x480 STN LCD DD 16-bit 5-1/3 Pixels/Clk 8 239

24) Optrex DMF-50351NC-FW 640x480 STN LCD DD 16-bit 5-1/3 Pixels/Clk 8 240

Glossary:

SS = Single Panel Single Scan

DD = Dual Panel Dual Scan

TFT = Thin Film Transistor ('Active Matrix')

STN = Super Twist Nematic ('Passive Matrix')

Revision 1.2 215 65540 / 545

Panel Interface Examples

J 5

M 1 2 DE

FLM 3 4 ENABKL

LP 5 6 VDDSAFE (+5V)

GND 7 8 VDDSAFE (+5V)

SHFCLK 9 10 +12 VSAFE

UD0 11 12 VEESAFE

UD1 13 14 GND

UD2 15 16 GND (-12V TO -45V)

UD3 17 18 GND or

LD0 19 20 GND (+12V TO +45V)

LD1 21 22 GND

LD2 23 24 GND

LD3 25 26 GND

Revision 1.2 216 65540 / 545

J 3

[+5V] VDDSAFE 1 2 +12 VSAFE

VEESAFE 3 4 Reserved

ENABKL 5 6 GND

M 7 8 DE

GND 9 10 LP

FLM 11 12 GND

SHFCLK 13 14 GND

P0 15 16 P1

GND 17 18 P2

P3 19 20 GND

P4 21 22 P5

GND 23 24 P6

P7 25 26 GND

P8 27 28 P9

GND 29 30 P10

P11 31 32 GND

P12 33 34 P13

GND 35 36 P14

P15 37 38 GND

P16 39 40 P17

GND 41 42 P18

P19 43 44 GND

P20 45 46 P21

GND 47 48 P22

P23 49 50 GND

DK6554x DK6554x Mono Mono Mono Color Color Color Color Color Color Color

6554x 6554x 26-Pin 50-Pin SS DD DD TFT TFT TFT HiRes STN STN STN DD STN DD

Pin# Pin Name Connector Connector 8-bit 8-bit 16-bit 9/12/16-bit 18/24-bit 18/24-bit 8-bit 16-bit 8-bit 16-bit

Pixels Transferred Per Shift Clock: 8 8 16 1 1 2 2-2/3 5-1/3 2-2/3 5-1/3

71 P0 17 15 – UD3 UD7 B0 B0 B00 R1... R1... UR1... UR1...

72 P1 15 16 – UD2 UD6 B1 B1 B01 B1... G1... UG1... UG1...

73 P2 13 18 – UD1 UD5 B2 B2 B02 G2... B1... UB1... UB1...

74 P3 11 19 – UD0 UD4 B3 B3 B03 R3... R2... UR2... UR2...

75 P4 25 21 – LD3 UD3 B4 B4 B10 B3... G2... LR1... LR1...

76 P5 23 22 – LD2 UD2 G0 B5 B11 G4... B2... LG1... LG1...

78 P6 21 24 – LD1 UD1 G1 B6 B12 R5... R3... LB1... LB1...

79 P7 19 25 – LD0 UD0 G2 B7 B13 B5... G3... LR2... LR2...

81 P8 – 27 P0 – LD7 G3 G0 G00 SHFCLKU B3... – UG2...

82 P9 – 28 P1 – LD6 G4 G1 G01 – R4... – UB2...

83 P10 – 30 P2 – LD5 G5 G2 G02 – G4... – UR3...

84 P11 – 31 P3 – LD4 R0 G3 G03 – B4... – UG3...

85 P12 – 33 P4 – LD3 R1 G4 G10 – R5... – LG2...

86 P13 – 34 P5 – LD2 R2 G5 G11 – G5... – LB2...

87 P14 – 36 P6 – LD1 R3 G6 G12 – B5... – LR3...

88 P15 – 37 P7 – LD0 R4 G7 G13 – R6... – LG3...

90 P16 – 39 – – – – R0 R00 – – – –

91 P17 – 40 – – – – R1 R01 – – – –

92 P18 – 42 – – – – R2 R02 – – – –

93 P19 – 43 – – – – R3 R03 – – – –

94 P20 – 45 – – – – R4 R10 – – – –

95 P21 – 46 – – – – R5 R11 – – – –

96 P22 – 48 – – – – R6 R12 – – – –

97 P23 – 49 – – – – R7 R13 – – – –

54/61 ENABKL 4 5 ENABKLENABKLENABKL ENABKL ENABKL ENABKL ENABKL ENABKLENABKL

ENABKL

70 SHFCLK 9 13 SHFCLK SHFCLKSHFCLK SHFCLK SHFCLK SHFCLK SHFCLKLSHFCLK SHFCLK

SHFCLK

69 M 1 7 M M M M M M M M M M

68 LP 5 10 LP LP LP LP LP LP LP LP LP LP

67 FLM 3 11 FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM

68/69 DE 2 8 DE DE DE DE DE DE DE DE DE DE

– VDDSAFE 6, 8 1 – – – – – – – – – –

–+12VSAFE 10 2 – – – – – – – – – –

– VEESAFE 12 3 – – – – – – – – – –

– GND 7,14, 6,9,12,14, – – – – – – – – – –

16,18, 17,20,23,26,

20,22, 29,32,35,38,

24,26 41,44,47,50

Panel Interface Examples

DEVELOPMENT KIT (DK) PRINTED CIRCUIT BOARD CONNECTOR SUMMARY

J 2

GND 1 2 [DPCLK]

GND 3 4 [BLANK#]

GND 5 6 VR7

GND 7 8 VR6

GND 9 10 VR5

VR1 11 12 VR4

VR0 13 14 VR3

GND 15 16 VR2

GND 17 18 VG7

GND 19 20 VG6

GND 21 22 VG5

VG1 23 24 VG4

VG0 25 26 VG3

GND 27 28 VG2

GND 29 30 VB7

GND 31 32 VB6

GND 33 34 VB5

VB1 35 36 VB4

VB0 37 38 VB3

GND 39 40 VB2

GND 41 42 HSYNC

[Reserved] 43 44 VSYNC

GND 45 46 KEY

GND 47 48 PCLK

GND 49 50 [Reserved]

Development Board

Panel Connectors

Development

Board

PC-Video

Connector

Panel

VSYNC

HSYNC

GND

Matsushita S804

GND

DISPTMG

CLOCK#

+5V

GND

+12V

n/c

(+5V)

(±12 to ±45)

n/c

(ACDCLK)

(VS)

(HS)

DK6554x

PCB

Connector

DATA-O3

DATA-O2

DATA-O1

DATA-O0

DATA-E0

DATA-E1

DATA-E2

DATA-E3

n/c

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

FLM

SHFCLK

BLANK#/DE

PNL8

PNL10

PNL14

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

Reserved

ENABKL

VEESAFE

PNL11

PNL9

PNL15

PNL13

PNL12

GND

VDDSAFE

+12VSAFE

6554x Interface - Matsushita S804 ( 640x480 16-Gray Level Plasma Panel )

Revision 1.2 217 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0] 00

Clock Divide (CD) XR50[6-4] 001

Shiftclk Div (SD) XR51[3] 0

Gray/Color Levels XR4F[2-0] 100

TFT Data Width XR50[7] 0 n/a

STN Pixel Packing XR53[5-4] 00 n/a

Frame Accel Ena XR6F[1] 0 Disabled

Output Signal Timing

Shift Clock Mask (SM) XR51[5] 0

LP Delay Disable XR2F[6] 0

LP Delay (CMPR ena) XR2F/2D 062h

LP Delay (CMPR disa) XR2F/2E 06Dh

LP Pulse Width XR2F[3-0] 8h

LP Polarity XR54[6] 0

LP Blank XR4F[7] 0

LP Active during V XR51[7] 1

FLM Delay Disable XR2F[7] 0

FLM Delay XR2C 04h

FLM Polarity XR54[7] 0

Blank#/DE Polarity XR54[0] 1

Blank#/DE H-Only XR54[1] 0

Blank#/DE CRT/FP XR51[2] 1

Alt Hsync Start (CR04) XR19 60h

Alt Hsync End (CR05) XR1A 00h

Alt H Total (CR00) XR1B 60h

Alt V Total (CR06) XR65/64 20Dh

Alt Vsync Start (CR10) XR65/66 1E8h

Alt Vsync End (CR11) XR67[3-0] 0Ah

Alt Hsync Polarity XR55[6] 1

Alt Vsync Polarity XR55[7] 1

Display Quality Recommendations

FRC XR50[1-0] 00 No FRC

FRC Option 1 XR53[2] 1 Set to 1

FRC Option 2 XR53[3] 1 Set to 1

FRC Option 3 XR53[6] 0

FRC Polynomial XR6E[7-0] n/a

Dither XR50[3-2] 01

M Phase Change XR5E[7] n/a

M Phase Change Count XR5E[6-0] n/a

Compensation Typical Settings

H Compensation XR55[0] 1

V Compensation XR57[0] 1

Fast Centering Disable XR57[7] 0

H AutoCentering XR55[1] 0

V AutoCentering XR57[1] 1

H Centering XR56 00h

V Centering XR59/58 000h

H Text Compression XR55[2] 1

H AutoDoubling XR55[5] 1

V Text Stretching XR57[2] 1

V Text Stretch Mode XR57[4-3] 11

V Stretching XR57[5] 0

V Stretching Mode XR57[6] 0

V Line Insertion Height XR59[3-0] 0Fh

V H/W Line Replication

XR59[7] 0

V Line Repl Height XR5A[3-0] 0

Programming Recommendations/Requirements

n/c

D13

D00

D01

D03

D10

D02

D11

D12

(+5V)

(±12 to ±45)

n/c

(ACDCLK)

(VS)

(HS)

CKD

GND

Panel

Connector

Sharp LJ64ZU50

DK6554x

PCB

Connector

V.D.

GND

H.D.

GND

n/c

B10

A10

B13

A13

B12

A12

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

PNL9

PNL11

PNL12

PNL13

PNL14

VDDSAFE

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

FLM

SHFCLK

GND

+12VSAFE

VEESAFE

PNL3

PNL2

PNL1

PNL0

PNL7

PNL6

PNL5

PNL4

PNL10

PNL8

PNL15

6554x Interface - Sharp LJ64ZU50 ( 640x480 16-Gray Level EL Panel )

Revision 1.2 218 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0] 00

Clock Divide (CD) XR50[6-4] 001

Shiftclk Div (SD) XR51[3] 0

Gray/Color Levels XR4F[2-0] 100

TFT Data Width XR50[7] 0 n/a

STN Pixel Packing XR53[5-4] 00 n/a

Frame Accel Ena XR6F[1] 0 Disabled

Output Signal Timing

Shift Clock Mask (SM) XR51[5] 0

LP Delay Disable XR2F[6] 0

LP Delay (CMPR ena) XR2F/2D 04Fh

LP Delay (CMPR disa) XR2F/2E 04Eh

LP Pulse Width XR2F[3-0] 01h

LP Polarity XR54[6] 1

LP Blank XR4F[7] 0

LP Active during V XR51[7] 1

FLM Delay Disable XR2F[7] 1

FLM Delay XR2C 0Ch

FLM Polarity XR54[7] 1

Blank#/DE Polarity XR54[0] 1

Blank#/DE H-Only XR54[1] 0

Blank#/DE CRT/FP XR51[2] 1

Alt Hsync Start (CR04) XR19 52h

Alt Hsync End (CR05) XR1A 15h

Alt H Total (CR00) XR1B 54h

Alt V Total (CR06) XR65/64 1F0h

Alt Vsync Start (CR10) XR65/66 1E5h

Alt Vsync End (CR11) XR67[3-0] 0Eh

Alt Hsync Polarity XR55[6] 1

Alt Vsync Polarity XR55[7] 1

Display Quality Recommendations

FRC XR50[1-0] 00 No FRC

FRC Option 1 XR53[2] 1 Set to 1

FRC Option 2 XR53[3] 1 Set to 1

FRC Option 3 XR53[6] 0

FRC Polynomial XR6E[7-0] n/a

Dither XR50[3-2] 01

M Phase Change XR5E[7] n/a

M Phase Change Count XR5E[6-0] n/a

Compensation Typical Settings

H Compensation XR55[0] 1

V Compensation XR57[0] 1

Fast Centering Disable XR57[7] 0

H AutoCentering XR55[1] 0

V AutoCentering XR57[1] 0

H Centering XR56 00h

V Centering XR59/58 000h

H Text Compression XR55[2] 1

H AutoDoubling XR55[5] 1

V Text Stretching XR57[2] 0

V Text Stretch Mode XR57[4-3] 11

V Stretching XR57[5] 0

V Stretching Mode XR57[6] 0

V Line Insertion Height XR59[3-0] 0Fh

V H/W Line Replication

XR59[7] 0

V Line Repl Height XR5A[3-0] 0

Programming Recommendations/Requirements

VLCD

LD0

LD1

LD2

LD3

UD3

UD2

UD1

UD0

VSS

VDD

DIN

YSCL

XSCL

Epson EG-9005F-LS

Panel

Connector

n/c

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

–19V

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

VEESAFE

VDDSAFE

FLM

SHFCLK

GND

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

+12VSAFE

6554x Interface - Epson EG-9005F-LS ( 640x480 Monochrome LCD DD Panel )

Revision 1.2 219 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

+28V VO

VAA

n/c

(+5V)

(±12 to ±45)

n/c

(ACDCLK)

(VS)

(HS)

DK6554x

PCB

Connector

DISPOFF#

Panel

Connector

Citizen G6481L-FF

VSS

VDD

UD0

UD1

UD2

UD3

LD3

LD2

LD1

LD0

LOAD

FRAME

n/c

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

+12VSAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

VDDSAFE

SHFCLK

GND

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

FLM

VEESAFE

6554x Interface - Citizen G6481L-FF ( 640x480 Monochrome LCD DD Panel )

Revision 1.2 220 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

n/c

(+5V)

(±12 to ±45)

n/c

(ACDCLK)

(VS)

(HS)

DK6554x

PCB

Connector

–18V

DU0

DL0

DL1

DL2

DL3

DU1

DU2

DU3

Panel

Connector

CP1

CP2

VEE

VSS

Sharp LM64P80

DISP

VDD

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

PNL0

PNL1

PNL4

PNL5

PNL6

PNL7

VDDSAFE

SHFCLK

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

FLM

GND

+12VSAFE

VEESAFE

PNL2

PNL3

6554x Interface - Sharp LM64P80 ( 640x480 Monochrome LCD DD Panel )

Revision 1.2 221 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0] 11 DD

Clock Divide (CD) XR50[6-4] 010 Dclk / 4

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0] 100

16Level (61w/dith)

TFT Data Width XR50[7] 0 n/a

STN Pixel Packing XR53[5-4] 0 n/a

Frame Accel Ena XR6F[1] 1 Enabled

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6] 0 Enabled

LP Delay (CMPR ena) XR2F/2D 050h

LP Delay (CMPR disa) XR2F/2E 050h

LP Pulse Width XR2F[3-0] 0h

LP Polarity XR54[6]

LP Blank XR4F[7] 0

LP Active during V XR51[7]

FLM Delay Disable XR2F[7] 0 Enabled

FLM Delay XR2C 04h 4 lines

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19 57h

Alt Hsync End (CR05) XR1A 19h

Alt H Total (CR00) XR1B 59h

Alt V Total (CR06) XR65/64 1E4h

Alt Vsync Start (CR10) XR65/66 1E0h

Alt Vsync End (CR11) XR67[3-0] 1

Alt Hsync Polarity XR55[6] 1 Negative

Alt Vsync Polarity XR55[7] 1 Negative

Display Quality Recommendations

FRC XR50[1-0] 01 16-Frame FRC

FRC Option 1 XR53[2] 1 Set to 1

FRC Option 2 XR53[3] 1 Set to 1

FRC Option 3 XR53[6] 0 n/a

FRC Polynomial XR6E[7-0] 26h

Dither XR50[3-2] 01 256-color modes

M Phase Change XR5E[7] 1 Every other frame

M Phase Change Count XR5E[6-0] 00h n/a

Compensation Typical Settings

H Compensation XR55[0] 1 Enabled

V Compensation XR57[0] 1 Enabled

Fast Centering Disable XR57[7] 0 Enabled

H AutoCentering XR55[1] 0 Disabled

V AutoCentering XR57[1] 1 Enabled

H Centering XR56 00h No left border

V Centering XR59/58 000h No top border

H Text Compression XR55[2] 1 Enabled

H AutoDoubling XR55[5] 1 Enabled

V Text Stretching XR57[2] 0 Disabled

V Text Stretch Mode XR57[4-3] 11 DS+TF,TF,DS

V Stretching XR57[5] 0 Disabled

V Stretching Mode XR57[6] 0 n/a

V Line Insertion Height XR59[3-0] 0Fh 16 – 1

V H/W Line Replication

XR59[7] 0 Disabled

V Line Repl Height XR5A[3-0] 0 n/a

Programming Recommendations/Requirements

n/c

n/c NC

n/c VO

VEE

VDD

VSS

LD3

LD2

LD1

LD0

UD3

UD2

UD1

UD0

FLM

CL1

CL2

Connector

Panel

–23V

n/c

(+5V)

(±12 to ±45)

n/c

(ACDCLK)

(VS)

(HS)

DK6554x

PCB

Connector

DISPOFF#

Sanyo LCM-6494-24NTK

CN1-8

CN1-9

CN1-10

CN1-11

CN2-12

CN2-13

CN2-14

CN2-15

CN1-5

CN2-18

CN1-2

CN1-6

CN2-19

CN2-20

CN2-16

CN2-25

CN2-17

CN2-23

CN2-22

CN2-24

CN1-7

CN2-21

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

CN1-4

CN1-3

CN1-1

PNL3

PNL2

PNL1

PNL0

PNL7

PNL6

PNL5

PNL4

VDDSAFE

SHFCLK

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

+12VSAFE

VEESAFE

GND

FLM

6554x Interface - Sanyo LCM-6494-24NTK ( 640x480 Monochrome LCD DD Panel )

Revision 1.2 222 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

–23V

Hitachi LMG5364XUFC

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

LOAD

Panel

Connector

VDD

VSS

FRAME

VEE

UD0

UD1

UD2

UD3

LD0

LD1

LD2

LD3

DISPOFF#

n/c

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

PNL1

VEESAFE

PNL0

PNL3

PNL2

PNL4

PNL5

PNL7

PNL6

VDDSAFE

FLM

SHFCLK

GND

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

+12VSAFE

6554x Interface - Hitachi LMG5364XUFC ( 640x480 Monochrome LCD DD Panel )

Revision 1.2 223 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

VSS1

+36V

(UD3)

(UD2)

(UD1)

(UD0)

(LD3)

(LD2)

(LD1)

(LD0)

(UD7)

(UD6)

(UD5)

(UD4)

(LD7)

(LD6)

(LD5)

(LD4)

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

VEE

VDD

Connector

Panel

Sanyo LCM-5491-24NAK

LD5

LD4

LD6

LD7

UD4

UD5

UD6

UD7

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

FLM

CL1

CL2

VSS2

VEE

VSS2

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

VEESAFE

FLM

VDDSAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

SHFCLK

+12VSAFE

PNL7

GND

6554x Interface - Sanyo LCM-5491-24NAK ( 1024x768 LCD DD Panel )

Revision 1.2 224 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 7Fh (1024 / 8) – 1

Panel Height XR65/68 2FFh 768 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

VDDH

(UD3)

(UD2)

(UD1)

(UD0)

(LD3)

(LD2)

(LD1)

(LD0)

(UD7)

(UD6)

(UD5)

(UD4)

(LD7)

(LD6)

(LD5)

(LD4)

(±12 to ±45)

VSS

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(+5V)

n/c

VSS

VDD

Connector

Panel

VSS

Epson ECM-A9071

LD7

LD6

LD5

LD4

LD3

LD2

LD1

LD0

UD7

UD6

UD5

UD4

UD3

UD2

UD1

UD0

DIN

XSCL

VSS

VDD

VDDH

DISP

+V†

† Voltage not specified in panel data sheet; contact panel manufacturer

for more information.

B16

B11

B10

B12

B13

B14

B15

B17

B18

B19

B20

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

A10

FLM

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

SHFCLK

+12VSAFE

GND

VDDSAFE

VEESAFE

6554x Interface - Epson A9071 ( 1024x768 LCD DD Panel )

Revision 1.2 225 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 7Fh (1024 / 8) – 1

Panel Height XR65/68 2FFh 768 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

GND

n/c

(B0)

(B1)

(B2)

(B3)

(B4)

(G0)

(G1)

(G2)

(R4)

(R3)

(R2)

(R1)

(R0)

(G4)

(G5)

(G3)

GND

DCLK

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

Hitachi TM26D50VC2AA

VDD

HREV

GND

DOTE

Panel

Connector

VSYNC

HSYNC

DTMG

n/c

–24V

VR1

VR2

VR3

VEE

BLC

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

FLM

VEESAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

+12VSAFE

GND

SHFCLK

VDDSAFE

6554x Interface - Hitachi TM26D50VC2AA ( 640x480 512-Color TFT LCD Panel )

Revision 1.2 226 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0] 00

Clock Divide (CD) XR50[6-4] 000

Shiftclk Div (SD) XR51[3] 0

Gray/Color Levels XR4F[2-0] 100

TFT Data Width XR50[7] 0 n/a

STN Pixel Packing XR53[5-4] 00 n/a

Frame Accel Ena XR6F[1] 0 Disabled

Output Signal Timing

Shift Clock Mask (SM) XR51[5] 0

LP Delay Disable XR2F[6] 0

LP Delay (CMPR ena) XR2F/2D 04Fh

LP Delay (CMPR disa) XR2F/2E 04Fh

LP Pulse Width XR2F[3-0] 0Fh

LP Polarity XR54[6] 1

LP Blank XR4F[7] 0

LP Active during V XR51[7] 1

FLM Delay Disable XR2F[7] 0

FLM Delay XR2C 04h

FLM Polarity XR54[7] 1

Blank#/DE Polarity XR54[0] 1

Blank#/DE H-Only XR54[1] 1

Blank#/DE CRT/FP XR51[2] 1

Alt Hsync Start (CR04) XR19 56h

Alt Hsync End (CR05) XR1A 13h

Alt H Total (CR00) XR1B 5Fh

Alt V Total (CR06) XR65/64 201h

Alt Vsync Start (CR10) XR65/66 1DFh

Alt Vsync End (CR11) XR67[3-0] 5h

Alt Hsync Polarity XR55[6] 1

Alt Vsync Polarity XR55[7] 1

Display Quality Recommendations

FRC XR50[1-0] 10

FRC Option 1 XR53[2] 1 Set to 1

FRC Option 2 XR53[3] 1 Set to 1

FRC Option 3 XR53[6] 0

FRC Polynomial XR6E[7-0] n/a

Dither XR50[3-2] 01

M Phase Change XR5E[7] n/a

M Phase Change Count XR5E[6-0] n/a

Compensation Typical Settings

H Compensation XR55[0] 1

V Compensation XR57[0] 1

Fast Centering Disable XR57[7] 0

H AutoCentering XR55[1] 0

V AutoCentering XR57[1] 0

H Centering XR56 00h

V Centering XR59/58 000h

H Text Compression XR55[2] 1

H AutoDoubling XR55[5] 1

V Text Stretching XR57[2] 1

V Text Stretch Mode XR57[4-3] 11

V Stretching XR57[5] 0

V Stretching Mode XR57[6] 0

V Line Insertion Height XR59[3-0] 0Fh

V H/W Line Replication

XR59[7] 0

V Line Repl Height XR5A[3-0] 0

Programming Recommendations/Requirements

n/c

TST

VCC

GND

VCC

GND

VSYNC

Connector

Panel

Sharp LQ9D011

(+5V)

(±12 to ±45)

n/c

(ACDCLK)

(VS)

(HS)

DK6554x

PCB

Connector

GND

ENAB

HSYNC

GND

(G3)

(G5)

(G4)

(R4)

(R3)

(R2)

(R1)

(R0)

(G2)

(G1)

(G0)

(B4)

(B3)

(B2)

(B1)

(B0)

n/c

CN1-2

CN1-1

CN1-4

CN2-1

CN1-12

CN2-4

CN2-3

CN2-2

CN2-6

CN1-7

CN1-6

CN1-5

CN1-11

CN1-10

CN1-9

CN1-13

CN1-14

CN1-15

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

CN2-5

CN1-8

CN1-3

CN1-8

FLM

VDDSAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

Reserved

ENABKL

SHFCLK

GND

+12VSAFE

VEESAFE

BLANK#/DE

6554x Interface - Sharp LQ9D011 ( 640x480 512-Color TFT LCD Panel )

Revision 1.2 227 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0] 00

Clock Divide (CD) XR50[6-4] 000

Shiftclk Div (SD) XR51[3] 0

Gray/Color Levels XR4F[2-0] 100

TFT Data Width XR50[7] 0 n/a

STN Pixel Packing XR53[5-4] 00 n/a

Frame Accel Ena XR6F[1] 0 Disabled

Output Signal Timing

Shift Clock Mask (SM) XR51[5] 0

LP Delay Disable XR2F[6] 0

LP Delay (CMPR ena) XR2F/2D 04Fh

LP Delay (CMPR disa) XR2F/2E 04Fh

LP Pulse Width XR2F[3-0] 0Fh

LP Polarity XR54[6] 1

LP Blank XR4F[7] 0

LP Active during V XR51[7] 1

FLM Delay Disable XR2F[7] 0

FLM Delay XR2C 04h

FLM Polarity XR54[7] 1

Blank#/DE Polarity XR54[0] 1

Blank#/DE H-Only XR54[1] 1

Blank#/DE CRT/FP XR51[2] 1

Alt Hsync Start (CR04) XR19 56h

Alt Hsync End (CR05) XR1A 13h

Alt H Total (CR00) XR1B 5Fh

Alt V Total (CR06) XR65/64 201h

Alt Vsync Start (CR10) XR65/66 1DFh

Alt Vsync End (CR11) XR67[3-0] 5h

Alt Hsync Polarity XR55[6] 1

Alt Vsync Polarity XR55[7] 1

Display Quality Recommendations

FRC XR50[1-0] 10

FRC Option 1 XR53[2] 1 Set to 1

FRC Option 2 XR53[3] 1 Set to 1

FRC Option 3 XR53[6] 0

FRC Polynomial XR6E[7-0] n/a

Dither XR50[3-2] 01

M Phase Change XR5E[7] n/a

M Phase Change Count XR5E[6-0] n/a

Compensation Typical Settings

H Compensation XR55[0] 1

V Compensation XR57[0] 1

Fast Centering Disable XR57[7] 0

H AutoCentering XR55[1] 0

V AutoCentering XR57[1] 0

H Centering XR56 00h

V Centering XR59/58 000h

H Text Compression XR55[2] 1

H AutoDoubling XR55[5] 1

V Text Stretching XR57[2] 1

V Text Stretch Mode XR57[4-3] 11

V Stretching XR57[5] 0

V Stretching Mode XR57[6] 0

V Line Insertion Height XR59[3-0] 0Fh

V H/W Line Replication

XR59[7] 0

V Line Repl Height XR5A[3-0] 0

Programming Recommendations/Requirements

n/c

(R0)

(R1)

(R2)

(R3)

(R4)

(G4)

(G5)

(G3)

(G2)

(G1)

(G0)

(B4)

(B3)

(B2)

(B1)

(B0) n/c

n/c

(+5V)

(±12 to ±45)

n/c

(ACDCLK)

(VS)

(HS)

DK6554x

PCB

Connector

GND

NCLK

Toshiba LTM-09C015-1

GND

ENAB

GND

Connector

Panel

n/c

VDD

CN1-2

CN1-1

CN2-9

CN1-12

CN2-7

CN1-6

CN2-1

CN2-3

CN2-5

CN1-8

CN2-2

CN2-4

CN2-10

CN1-15

CN2-8

CN2-6

CN1-14

CN1-10

CN1-4

CN1-7

CN1-5

CN1-3

CN1-13

CN1-11

CN1-9

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

VDDSAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

FLM

SHFCLK

GND

+12VSAFE

VEESAFE

6554x Interface - Toshiba LTM-09C015-1 ( 640x480 512-Color TFT LCD Panel )

Revision 1.2 228 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0] 00

Clock Divide (CD) XR50[6-4] 000

Shiftclk Div (SD) XR51[3] 0

Gray/Color Levels XR4F[2-0] 100

TFT Data Width XR50[7] 0 n/a

STN Pixel Packing XR53[5-4] 00 n/a

Frame Accel Ena XR6F[1] 0 Disabled

Output Signal Timing

Shift Clock Mask (SM) XR51[5] 0

LP Delay Disable XR2F[6] 0

LP Delay (CMPR ena) XR2F/2D 04Fh

LP Delay (CMPR disa) XR2F/2E 04Fh

LP Pulse Width XR2F[3-0] 0Fh

LP Polarity XR54[6] 1

LP Blank XR4F[7] 0

LP Active during V XR51[7] 1

FLM Delay Disable XR2F[7] 0

FLM Delay XR2C 04h

FLM Polarity XR54[7] 1

Blank#/DE Polarity XR54[0] 1

Blank#/DE H-Only XR54[1] 0

Reqd for this panel

Blank#/DE CRT/FP XR51[2] 1

Alt Hsync Start (CR04) XR19 56h

Alt Hsync End (CR05) XR1A 13h

Alt H Total (CR00) XR1B 5Fh

Alt V Total (CR06) XR65/64 201h

Alt Vsync Start (CR10) XR65/66 1DFh

Alt Vsync End (CR11) XR67[3-0] 5h

Alt Hsync Polarity XR55[6] 1

Alt Vsync Polarity XR55[7] 1

Display Quality Recommendations

FRC XR50[1-0] 10

FRC Option 1 XR53[2] 1 Set to 1

FRC Option 2 XR53[3] 1 Set to 1

FRC Option 3 XR53[6] 0

FRC Polynomial XR6E[7-0] n/a

Dither XR50[3-2] 01

M Phase Change XR5E[7] n/a

M Phase Change Count XR5E[6-0] n/a

Compensation Typical Settings

H Compensation XR55[0] 1

V Compensation XR57[0] 1

Fast Centering Disable XR57[7] 0

H AutoCentering XR55[1] 0

V AutoCentering XR57[1] 0

H Centering XR56 00h

V Centering XR59/58 000h

H Text Compression XR55[2] 1

H AutoDoubling XR55[5] 1

V Text Stretching XR57[2] 1

V Text Stretch Mode XR57[4-3] 11

V Stretching XR57[5] 0

V Stretching Mode XR57[6] 0

V Line Insertion Height XR59[3-0] 0Fh

V H/W Line Replication

XR59[7] 0

V Line Repl Height XR5A[3-0] 0

Programming Recommendations/Requirements

n/c

TST

GND

Panel

Connector

VSYNC

HSYNC

GND

ENAB

VCC

GND

VCC

TST

Sharp LQ10D311

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

CN1-2

CN1-1

CN1-3

CN1-4

CN2-1

CN1-12

CN2-5

CN1-8

CN2-3

CN2-2

CN2-6

CN3-4

CN3-8

CN3-12

CN3-13

CN3-14

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

CN2-4

CN3-2

CN3-1

CN1-9

CN3-7

CN3-6

CN3-11

CN1-13

CN1-14

CN3-3

CN1-5

CN1-6

CN1-7

CN3-5

CN1-10

CN1-11

CN1-15

CN3-10

CN3-9

FLM

VDDSAFE

PNL0

PNL1

PNL8

PNL9

PNL16

PNL17

PNL19

BLANK#/DE

Reserved

ENABKL

SHFCLK

+12VSAFE

VEESAFE

GND

PNL18

PNL13

PNL12

PNL11

PNL4

PNL5

PNL6

PNL20

PNL21

PNL22

PNL23

PNL10

PNL14

PNL15

PNL7

PNL3

PNL2

6554x Interface - Sharp LQ10D311 ( 640x480 256K-Color TFT LCD Panel )

Revision 1.2 229 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

Use separate +12V source, not +12VSAFE

(sequenced), for panel VDD (panel VDD

must be active before panel VCC)

n/c

(odd pixel red msb)

(odd pixel red lsb)

(even pixel red lsb)

(even pixel red msb)

(odd pixel blue lsb)

(odd pixel blue msb)

(even pixel blue lsb)

(even pixel blue msb)

(odd pixel green lsb)

(odd pixel green msb)

(even pixel green lsb)

(even pixel green msb)

n/c

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

B00

B01

B02

B10

B11

B12

G00

G01

G02

G10

G11

G12

R01

R02

R10

R11

R12

R00

+5V

+12V VDD

VDD

TEST3

TEST2

TEST1

VCC

GND

Sharp LQ10DX01

GND

VCC

HSYNC

VSYNC

Connector

Panel

GND

n/c

CN1-12

CN1-9

CN1-21

CN2-1

CN2-2

CN2-4

CN2-6

CN2-13

CN1-17

CN1-18

CN1-15

CN1-8

CN2-14

CN2-9

CN1-14

CN1-20

CN1-1

CN2-8

CN2-7

CN2-5

CN2-3

CN2-15

CN2-10

CN2-11

CN2-12

CN1-7

CN1-3

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

CN1-6

CN1-5

CN1-4

CN1-2

CN1-11

CN1-10

CN1-19

CN1-16

CN1-13

FLM

VDDSAFE

PNL0

PNL2

PNL3

PNL4

PNL6

PNL7

PNL8

PNL9

PNL12

PNL13

PNL15

PNL16

PNL20

PNL23

PNL18

BLANK#/DE

Reserved

ENABKL

SHFCLK

GND

+12VSAFE

VEESAFE

PNL22

PNL21

PNL19

PNL17

PNL11

PNL10

PNL5

PNL1

PNL14

6554x Interface - Sharp LQ10DX01 ( 1024x768 512-Color TFT LCD Panel )

Revision 1.2 230 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 7Fh (1024 / 8) – 1

Panel Height XR65/68 2FFh 768 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

CL2

n/c

(+5V)

(±12 to ±45)

n/c

(ACDCLK)

(VS)

(HS)

DK6554x

PCB

Connector (LCM 5330)

Sanyo

UD7

LD7

UD6

LD6

UD5

LD5

UD4

LD4

UD3

LD3

UD2

LD2

UD1

LD1

UD0

LD0

VEE

VDD

Connector

Panel

FLM

CL1

VEE

DISP

+38V

VSS

GND

LM-CK53-22NEZ

n/c

(R1...)

(G1...)

(R6...)

(B5...)

(G5...)

(R5...)

(B4...)

(G4...)

(R4...)

(B3...)

(G3...)

(R3...)

(B2...)

(G2...)

(R2...)

(B1...)

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

FLM

PNL0

PNL2

PNL4

PNL5

PNL6

PNL7

PNL8

PNL9

PNL10

PNL11

PNL13

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

+12VSAFE

SHFCLK

PNL14

PNL12

PNL3

PNL1

GND

VEESAFE

VDDSAFE

6554x Interface - Sanyo LM-CK53-22NEZ ( LCM 5330 ) ( 640x480 Color STN LCD Panel )

Revision 1.2 231 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

n/c +36V

n/c

(+5V)

(±12 to ±45)

n/c

(ACDCLK)

(VS)

(HS)

DK6554x

PCB

Connector Sanyo LCM-5327-24NAK

DISPOFF

UD1

LD1

UD0

LD0

UD7

LD7

UD6

LD6

VEE

VDD

Connector

Panel

FLM

CL1

CL2

VSS1

VSS2

VEE

VSS2

UD3

LD3

UD2

LD2

LD4

UD4

LD5

UD5

(R1...)

(G1...)

(R6...)

(B5...)

(G5...)

(R5...)

(B4...)

(G4...)

(R4...)

(B3...)

(G3...)

(R3...)

(B2...)

(G2...)

(R2...)

(B1...)

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

FLM

VEESAFE

VDDSAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL9

PNL10

PNL11

PNL13

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

Reserved

SHFCLK

GND

+12VSAFE

ENABKL

BLANK/DE#

PNL14

PNL12

6554x Interface - Sanyo LCM5327-24NAK ( 640x480 Color STN LCD Panel )

Revision 1.2 232 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

n/c NC

VSS

XCKU

XCKL

VDD

VSS

Connector

Panel

Sharp LM64C031

VEE

Connector

PCB

DK6554x

(SCL)

(HS)

(VS)

(ACDCLK)

(SCH)

n/c

(±12 to ±45)

(+5V)

n/c

+32V

n/c

(R1...)

(B1...)

(G2...)

(R3...)

(B3...)

(G4...)

(R5...)

(B5...)

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

FLM

VDDSAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

SHFCLK

+12VSAFE

VEESAFE

GND

6554x Interface - Sharp LM64C031 ( 640x480 Color STN LCD Panel )

Revision 1.2 233 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

n/c

(+5V)

(±12 to ±45)

n/c

(ACDCLK)

(VS)

(HS)

DK6554x

PCB

Connector

DISP#

VDD

LD3

LD2

LD1

LD0

FRM

HD0

HD1

HD2

HD3

LOAD

FRM

GND

Panel

Connector

Kyocera KCL6448

(UR1...)

(UG1...)

(UB1...)

(UR2...)

(LR1...)

(LG1...)

(LB1...)

(LR2...)

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

FLM

VDDSAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

SHFCLK

GND

+12VSAFE

VEESAFE

6554x Interface - Kyocera KCL6448 ( 640x480 Color STN-DD LCD Panel )

Revision 1.2 234 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

Hitachi LMG9720XUFC

+27V

UD3

CL2

CL1

FLM

Panel

Connector

VDD

VSS

VEE

UD0

UD1

UD2

LD0

LD1

LD2

LD3

DISPOFF#

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL9

PNL10

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

SHFCLK

GND

+12VSAFE

FLM

VDDSAFE

VEESAFE

6554x Interface - Hitachi LMG9720XUFC ( 640x480 Color STN-DD LCD Panel )

Revision 1.2 235 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

VSS

Sharp LM64C08P

VSS

VDD

DISP

VEE

Connector

Panel

XCK

DL4

DL5

DL6

DL7

DU4

DU5

DU6

DU7

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

+25V

n/c

(UR2...)

(UB1...)

(UR1...)

(UG1...)

(LR1...)

(LG1...)

(LB1...)

(LR2...)

(UG2...)

(UB2...)

(UR3...)

(UG3...)

(LG2...)

(LB2...)

(LR3...)

(LG3...)

CN1-3

CN1-1

CN1-2

CN1-7

CN1-6

CN1-8

CN2-17

CN2-18

CN2-19

CN2-20

CN1-5

CN1-4

CN1-14

CN1-15

CN2-21

CN2-22

CN2-23

CN2-24

CN2-1

CN2-10

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

CN2-25

CN2-16

CN1-13

CN1-12

CN1-9

CN1-10

CN1-11

FLM

VDDSAFE

PNL0

PNL1

PNL4

PNL5

PNL6

PNL7

PNL11

PNL12

PNL13

PNL14

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

SHFCLK

+12VSAFE

VEESAFE

GND

PNL2

PNL3

PNL10

PNL9

PNL8

6554x Interface - Sharp LM64C08P ( 640x480 Color STN-DD LCD Panel )

Revision 1.2 236 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0] 0BAh ** Important **

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

+30V

Panel

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

Sanyo LCM-5331-22NTK

UD3

CL1

FLM

UD7

LD0

CL2

VSS

UD6

UD5

UD4

UD1

UD2

UD0

LD2

LD1

LD3

LD4

LD5

LD6

LD7

VSS

VDD

VEE

ConnectorConnector

Single

(Panel Spec) (Prototypes)

Dual

DISPOFF#

n/c

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

CN1-2

CN1-1

CN1-4

CN2-17

CN1-6

CN1-7

CN1-5

CN2-16

CN2-18

CN2-19

CN2-20

CN2-21

CN2-22

CN2-23

CN1-12

CN1-13

CN1-14

CN1-15

CN1-8

CN1-9

CN1-10

CN1-11

CN2-25

CN2-24

CN2-27

CN2-26

CN2-28

CN2-29

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

+12VSAFE

PNL7

PNL6

PNL3

PNL2

PNL1

PNL0

FLM

PNL14

SHFCLK

PNL15

PNL13

PNL12

PNL11

PNL10

PNL9

PNL8

VEESAFE

GND

VDDSAFE

PNL4

PNL5

6554x Interface - Sanyo LCM-5331-22NTK ( 640x480 Color STN-DD LCD Panel )

Revision 1.2 237 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

UD7

UD6

UD5

UD4

LD7

LD6

LD5

LD4

VSS

Hitachi LMG9721XUFC

UD3

CL2

CL1

FLM

Panel

Connector

VDD

VSS

VEE

UD0

UD1

UD2

LD0

LD1

LD2

LD3

DISPOFF#

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

+V†

† Voltage not specified in panel data sheet; contact panel manufacturer

for more information.

CN1-8

CN1-9

CN1-10

CN1-11

CN1-12

CN1-13

CN1-14

CN1-15

CN1-3

CN1-1

CN1-6

CN1-5

CN1-2

CN1-4

CN1-7

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

CN2-5

CN2-10

CN2-1

CN2-2

CN2-3

CN2-4

CN2-6

CN2-7

CN2-8

CN2-9

VDDSAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL10

PNL12

PNL14

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

SHFCLK

+12VSAFE

VEESAFE

FLM

GND

PNL11

PNL9

PNL15

PNL13

6554x Interface - Hitachi LMG9721XUFC ( 640x480 Color STN-DD LCD Panel )

Revision 1.2 238 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

+24.5V

DISP

GND

SCP

Toshiba TLX-8062S-C3X

Panel

Connector

VDD

VEE

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

LD4

LD5

LD6

LD7

UD4

UD5

UD6

UD7

CN1-12

CN1-13

CN1-14

CN1-15

CN2-6

CN2-7

CN2-8

CN2-9

CN1-3

CN1-1

CN1-6

CN1-5

CN1-2

CN1-4

CN1-7

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

CN1-8

CN1-9

CN1-10

CN1-11

CN2-2

CN2-3

CN2-4

CN2-5

CN2-1

CN2-10

VDDSAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL10

PNL12

PNL14

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

SHFCLK

+12VSAFE

VEESAFE

FLM

PNL11

PNL9

PNL15

PNL13

GND

6554x Interface - Toshiba TLX-8062S-C3X ( 640x480 Color STN-DD LCD Panel )

Revision 1.2 239 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

VSS

DL3

DL2

DL1

DL0

DL4

DL5

DL6

DL7

DU0

DU1

DU2

DU3

DU4

DU5

DU6

DU7

VCC

Optrex DMF-50351NC-FW

FLM

Panel

Connector

VSS

VEE

DISPOFF#

Connector

PCB

DK6554x

(HS)

(VS)

(ACDCLK)

n/c

(±12 to ±45)

(+5V)

n/c

+V†

† Voltage not specified in panel data sheet; contact panel manufacturer

for more information.

CN1-12

CN1-13

CN1-14

CN1-15

CN2-6

CN2-7

CN2-8

CN2-9

CN1-3

CN1-1

CN1-6

CN1-5

CN1-2

CN1-4

CN1-7

J3-29

J3-26

J3-32

J3-35

J3-38

J3-41

J3-44

J3-47

J3-15

J3-16

J3-18

J3-19

J3-21

J3-22

J3-24

J3-25

J3-50

J3-23

J3-27

J3-28

J3-30

J3-31

J3-33

J3-34

J3-36

J3-37

J3-2

J3-3

J3-1

J3-40

J3-39

J3-42

J3-43

J3-46

J3-45

J3-48

J3-49

J3-4

J3-7

J3-8

J3-11

J3-10

J3-13

J3-5

J3-14

J3-12

J3-6

J3-9

J3-20

J3-17

CN1-8

CN1-9

CN1-10

CN1-11

CN2-2

CN2-3

CN2-4

CN2-5

CN2-1

CN2-10

VDDSAFE

PNL0

PNL1

PNL2

PNL3

PNL4

PNL5

PNL6

PNL7

PNL8

PNL10

PNL13

PNL15

PNL16

PNL20

PNL17

PNL21

PNL19

PNL23

PNL18

PNL22

BLANK#/DE

Reserved

ENABKL

SHFCLK

+12VSAFE

VEESAFE

FLM

PNL11

PNL9

PNL14

PNL12

GND

6554x Interface - Optrex DMF-50351NC-FW ( 640x480 Color STN-DD LCD Panel )

Revision 1.2 240 65540 / 545

Panel Interface Examples

Parameter Register Value Comment

Panel Width XR1C 4Fh (640 / 8) – 1

Panel Height XR65/68 1DFh 480 – 1

Panel Type XR51[1-0]

Clock Divide (CD) XR50[6-4]

Shiftclk Div (SD) XR51[3]

Gray/Color Levels XR4F[2-0]

TFT Data Width XR50[7]

STN Pixel Packing XR53[5-4]

Frame Accel Ena XR6F[1]

Output Signal Timing

Shift Clock Mask (SM) XR51[5]

LP Delay Disable XR2F[6]

LP Delay (CMPR ena) XR2F/2D

LP Delay (CMPR disa) XR2F/2E

LP Pulse Width XR2F[3-0]

LP Polarity XR54[6]

LP Blank XR4F[7]

LP Active during V XR51[7]

FLM Delay Disable XR2F[7]

FLM Delay XR2C

FLM Polarity XR54[7]

Blank#/DE Polarity XR54[0]

Blank#/DE H-Only XR54[1]

Blank#/DE CRT/FP XR51[2]

Alt Hsync Start (CR04) XR19

Alt Hsync End (CR05) XR1A

Alt H Total (CR00) XR1B

Alt V Total (CR06) XR65/64

Alt Vsync Start (CR10) XR65/66

Alt Vsync End (CR11) XR67[3-0]

Alt Hsync Polarity XR55[6]

Alt Vsync Polarity XR55[7]

Display Quality Recommendations

FRC XR50[1-0]

FRC Option 1 XR53[2]

FRC Option 2 XR53[3]

FRC Option 3 XR53[6]

FRC Polynomial XR6E[7-0]

Dither XR50[3-2]

M Phase Change XR5E[7]

M Phase Change Count XR5E[6-0]

Compensation Typical Settings

H Compensation XR55[0]

V Compensation XR57[0]

Fast Centering Disable XR57[7]

H AutoCentering XR55[1]

V AutoCentering XR57[1]

H Centering XR56

V Centering XR59/58

H Text Compression XR55[2]

H AutoDoubling XR55[5]

V Text Stretching XR57[2]

V Text Stretch Mode XR57[4-3]

V Stretching XR57[5]

V Stretching Mode XR57[6]

V Line Insertion Height XR59[3-0]

V H/W Line Replication

XR59[7]

V Line Repl Height XR5A[3-0]

Programming Recommendations/Requirements

Electrical Specifications

Symbol Parameter Min Typ Max Units

PDPower Dissipation – – 1 W

VCC Supply Voltage – 0.5 – 7.0 V

VIInput Voltage – 0.5 – VCC+0.5 V

VOOutput Voltage – 0.5 – VCC+0.5 V

TOP Operating Temperature (Ambient) – 25 – 85 ° C

STG

Storage Temperature – 40 – 125 ° C

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.

Functional operation should be restricted to the conditions described under Normal Operating Conditions.

65540 / 545 ABSOLUTE MAXIMUM CONDITIONS

65540 / 545 DAC CHARACTERISTICS (Under Normal Operating Conditions Unless Noted Otherwise)

Symbol Parameter Notes Min Typ Max Units

VOOutput Voltage IO ≤ 10 mA 1.5 – – V

IOOutput Current VO ≤ 1V @ 37.5Ω Load 21 – – mA

Full Scale Error – – ± 5 %

DAC to DAC Correlation – 1.27 – %

DAC Linearity ± 2 – – LSB

Full Scale Settling Time – – 28 nS

Rise Time 10% to 90% – – 6 nS

Glitch Energy – – 200 pVsec

Comparator Sensitivity – 50 – mV

11/11/93

Electrical Specifications

Symbol Parameter Min Typ Max Units

VCC Supply Voltage (5V ± 10%) 4.5 5 5.5 V

VCC Supply Voltage (3.3V ± 10%) 3.1 3.3 3.6 V

Ambient Temperature 0 – 70 ° C

65540 / 545 NORMAL OPERATING CONDITIONS

Revision 1.2 241 65540 / 545

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Revision 1.2 242 65540 / 545

Electrical Specifications

65540 / 545 DC CHARACTERISTICS (Under Normal Operating Conditions Unless Noted Otherwise)

Symbol Parameter Output Pins DC Test Conditions MinUnits

IOL Output Low Drive H/VSYNC, LDEV#, LRDY#, ROMCS#, IRQ V OUT=VOL, VCC=4.5V 12 mA

FLM, LP, M, P0-15, SHFCLK, D0-31 VOUT=VOL, VCC=4.5V 8 mA

ENAVEE, ENAVDD, ENABKL, ACTI VOUT=VOL, VCC=4.5V 8 mA

RASA#, CASAH/L#, WEA#, PAR (65545 only) VOUT=VOL, VCC=4.5V 4 mA

RASB#, CASBH/L#, WEB#, OEAB#, AA0-9 VOUT=VOL, VCC=4.5V 4 mA

RASC#, CASCH/L#, WEC#, OEC#, CA0-9 VOUT=VOL, VCC=4.5V 4 mA

All other outputs VOUT=VOL, VCC=4.5V 2 mA

IOH Output High Drive H/VSYNC, LDEV#, LRDY#, ROMCS#, IRQ V OUT=VOH, VCC=4.5V 12 mA

FLM, LP, M, P0-15, SHFCLK, D0-31 VOUT=VOL, VCC=4.5V 8 mA

ENAVEE, ENAVDD, ENABKL, ACTI VOUT=VOH, VCC=4.5V 8 mA

RASA#, CASAH/L#, WEA#, PAR (65545 only) V OUT=VOH, VCC=4.5V 4 mA

RASB#, CASBH/L#, WEB#, OEAB#, AA0-9 VOUT=VOH, VCC=4.5V 4 mA

RASC#, CASCH/L#, WEC#, OEC#, CA0-9 VOUT=VOH, VCC=4.5V 4 mA

All other outputs V

OUT=VOH, VCC=4.5V 2 mA

Symbol Parameter Notes Min Typ Max Units

ICCDE Power Supply Current 0°C, 5.5V, 68 MHz, DAC on, 65540 – 180 230 mA

ICCDO Power Supply Current 0°C, 5.5V, 68 MHz, DAC off, 65540 – 140 200 mA

ICCDO Power Supply Current 0°C, 3.3V, 62 MHz, DAC off, 65540 – 78 132 mA

ICCDE Power Supply Current 0°C, 5.5V, 68 MHz, DAC on, 65545 – TBD TBD mA

ICCDO Power Supply Current 0°C, 5.5V, 68 MHz, DAC off, 65545 – TBD TBD mA

ICCDO Power Supply Current 0°C, 3.3V, 56 MHz, DAC off, 65545 – TBD TBD mA

ICCS Power Supply Current 0°C, 5.5V, Standby†, 65540 – – 200 µA

ICCS Power Supply Current 0°C, 5.5V, Standby†, 65545 – – TBD µA

IIL Input Leakage Current – 100 – +100 uA

IOZ Output Leakage Current High Impedance – 100 – +100 uA

VIL Input Low Voltage All input pins – 0.5 – 0.8 V

VOL Output Low Voltage Under max load per table below (5V) – – 0.5 V

VOL Output Low Voltage Under max load per table below (3.3V) – – 0.5 V

VOH Output High Voltage Under max load per table below (5V) VCC– 0.5 – – V

VOH Output High Voltage Under max load per table below (3.3V) 2.4 – – V

VIH Input High Voltage All pins except XTALI 2.0 – VCC+0.5 V

Input High Voltage All pins except XTALI 2.0 – V

CC+0.5 V

65540 / 545 DC DRIVE CHARACTERISTICS (Under Normal Operating Conditions Unless Noted Otherwise)

Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)

Note:†Standby power was measured using Self Refresh DRAMs with all chip inputs driven to inactive levels and outputs not

connected (or connected to typical external loads).

Note:Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Electrical Specifications

Revision 1.2 243 65540 / 545

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

65540 / 545 AC TEST CONDITIONS (Under Normal Operating Conditions Unless Noted Otherwise)

Output Output

Capacitive

Output Pins Low Voltage High Voltage Load

All 12mA and 8mA outputs plus PAR for PCI bus in the 65545 VOL 2.4V 80pF

All Other 4mA output pads VOL 2.4V 50pF

All Other 2mA output pads V

2.4V 30pF

Symbol Parameter Notes Min Typ Max Units

FREF Reference Frequency (±100 ppm) 1 14.31818 60 MHz

TREF Reference Clock Period 1/FREF 16.6 69.84128 1000 nS

HI /TREF Reference Clock Duty Cycle 25 – 75 %

65540 / 65545 AC TIMING CHARACTERISTICS - REFERENCE CLOCK

Reference Clock Timing

TREF

Reference Clock Input

THI

Electrical Specifications

Revision 1.2 244 65540 / 545

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Clock Timing

TCH TCL

VCLK

TMH TML

MCLK

Symbol Parameter Notes Min Typ Max Units

TCVCLK Period (5V) 68 MHz 14.7 – – nS

TCVCLK Period (3.3V) 56 MHz 17.6 – – nS

TCH VCLK High Time 0.45TC– 0.55TCnS

TCL VCLK Low Time 0.45TC– 0.55TCnS

TMMCLK Period (5V) 68 MHz 14.7 – – nS

TMMCLK Period (3.3V) 56 MHz 17.6 – – nS

TMH MCLK High Time 0.45TM– 0.55TMnS

TML MCLK Low Time 0.45TM– 0.55TMnS

TRF Clock Rise / Fall – – 5 nS

–MCLK Frequency for 100 ns DRAMs (5V) – 50.350 – MHz

–MCLK Frequency for 80 ns DRAMs (5V) – 56.644 – MHz

–MCLK Frequency for 70 ns DRAMs (5V) – 65 – MHz

65540 / 545 AC TIMING CHARACTERISTICS - CLOCK GENERATOR

Electrical Specifications

Revision 1.2 245 65540 / 545

65540 / 545 AC TIMING CHARACTERISTICS - RESET

RESET#

TRES

Configuration Lines

AA0-AA8

TIPR

VCC

Initial Power-Up Reset Reset with Chip Operating

and Power Stable

TORS

Valid

14.318 MHz

TRSO

TCSU TCHD

TRSR

Bus Output Pins

TCSU TCHD

TRSR

(from external oscillator)

Reset Timing

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Symbol Parameter Notes Min Max Units

TIPR Reset Active Time from Power Stable See Note 1 5 – mS

TORS Reset Active Time from Ext. Osc. Stable See Note 2 0 – nS

TRES Reset Active Time with Power Stable See Note 3 2 – mS

TRSR Reset Rise Time Reset fall time is non-critical – 20 nS

TRSO Reset Active to Output Float Delay – 40 nS

TCSU Configuration Setup Time See Note 4 20 – nS

CHD

Configuration Hold Time 5 – nS

Note 1: This parameter includes time for internal voltage stabilization of all sections of the chip, startup and stabilization of the

internal clock synthesizer, and setting of all internal logic to a known state.

Note 2: The external oscillator input is optional, it may be selected by XR01 bit 5.

Note 3: This parameter includes time for the internal clock synthesizer to reset to its default frequency and time to set all internal logic

to a known state. It assumes power is stable and the internal clock synthesizer is already operating at some stable frequency.

Note 4: Setup time to latch the state of the configuration bits reliably into XR01 and XR6C is specified by this parameter. Changes

in some configuration bits may take longer to stabilize inside the chip (such as internal clock synthesizer-related bits 4 and 5).

It is therefore recommended that configuration bit setup time be TRES (2mS) to insure that the chip is in a completely stable

state when Reset goes inactive.

Revision 1.2 246 65540 / 545

Symbol Parameter Notes Min Max Units

TLCP Local Bus Clock Period (33MHz) 0.1% stability at 2.0V / 0.8V 30 30 nS

TLCH Local Bus Clock High Time 12 – nS

TLCL Local Bus Clock Low Time 12 – nS

TLCR Local Bus Clock Rise Time – 3 nS

TLCF Local Bus Clock Fall Time – 3 nS

—Local Bus Clock Slew Rate 1 4 V / nS

TCRS CPU Reset Setup Time to Local Bus Clock For 2x Clock Sync 2 – nS

CRH

CPU Reset Hold Time from Local Bus Clock For 2x Clock Sync 5 – nS

Electrical Specifications

65540 / 65545 AC TIMING CHARACTERISTICS - LOCAL BUS CLOCK ( 33 MHz )

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Local Bus '2x' Clock Synchronization Timing

TCRS

TCRH

CRESET†

CCLK / LCLK

(2x Bus Clock

Configuration)

† 65540/545 CRESET to CCLK timing should match CPU RESET to CLK2 timing of the CPU.

Local Bus Clock Timing

CCLK / LCLK

TLCP

TLCH

TLCL

TLCR TLCF

Note: VL-Bus timing is compatible with VL-Bus Specification 2.0.

Revision 1.2 247 65540 / 545

Electrical Specifications

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Symbol Parameter Notes Min Max Units

TADS Setup Time - A2-31, BEn#, M/IO#, W/R# 7 – nS

TASS Setup Time - ADS# 7 – nS

TDWS Setup Time - D0-31 (Write) 7 – nS

TRRS Setup Time - RDYRTN# 5 – nS

TADH Hold Time - A2-31, BEn#, M/IO#, W/R# 2 – nS

TASH Hold Time - ADS# 2 – nS

TDWH Hold Time - D0-31 (Write) 2 – nS

RRH

Hold Time - RDYRTN# 2 – nS

65540 / 65545 AC TIMING CHARACTERISTICS - LOCAL BUS INPUT SETUP & HOLD (33 MHz)

TASS

CCLK / LCLK TDWH

D31-0 (Write)

RDYRTN#

ADS#

BEn#, A31-2

M/IO#, W/R#

TDWS

TRRS TRRH

TASH

TADS TADH

Local Bus Input Setup & Hold Timing

Electrical Specifications

Revision 1.2 248 65540 / 545

Symbol Parameter Notes CL Max Min Max Units

TDAV Bus Clock to Output Valid - D0-31 (Read) 125pF 3 18 nS

RDV

Bus Clock to Output Valid - LRDY# 100pF 3 14 nS

65540 / 65545 AC TIMING CHARACTERISTICS - LOCAL BUS OUTPUT VALID ( 33 MHz )

Local Bus Output Valid Timing

CCLK / LCLK

TDAV

Valid N

min max

Valid N+1LRDY#

D31-0 (Read)

min max

TRDV

Valid N

Valid N+1

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Symbol Parameter Notes CL Max Min Max Units

TDAF Float Delay - D0-31 (Read) 125pF – 20 nS

RDF

Float Delay - LRDY# Driven high before floating 100pF – 30 nS

65540 / 65545 AC TIMING CHARACTERISTICS - LOCAL BUS FLOAT DELAY (33MHz)

Local Bus Output Float Delay Timing

CCLK / LCLK TDAF

D31-0 (Read) Valid N

LRDY#

TRDF

Revision 1.2 249 65540 / 545

Electrical Specifications

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Symbol Parameter Notes Min Typ Max Units

LDV

Address to LDEV# change 3 – 20 nS

65540 / 65545 AC TIMING CHARACTERISTICS - VL-BUS LDEV#

VL-Bus LDEV# Timing

LDEV# TLDV

ValidAddress

TLDV

Electrical Specifications

Revision 1.2 250 65540 / 545

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Symbol Parameter Notes Min Max Units

TFRS FRAME# Setup to CLK 7 – nS

TCMS C/BE#[3:0] (Bus CMD) Setup to CLK 7 – nS

TCMH C/BE#[31:0] (Bus CMD) Hold from CLK 2 – nS

TBES C/BE#[3:0] (Byte Enable) Setup to CLK 7 – nS

TBEH C/BE#[3:0] (Byte Enable) Hold from CLK 2 – nS

TADS AD[31:0] (Address) Setup to CLK 7 – nS

TADH AD[31:0] (Address) Hold from CLK 2 – nS

TDAD AD[31:0] (Data) Valid from CLK Read Cycles – 11 nS

TDAS AD[31:0] (Data) Setup to CLK Write Cycles 7 – nS

TDAH AD[31:0] (Data) Hold from CLK 2 – nS

TTZH TRDY# High Z to High from CLK – 11 nS

TTHL TRDY# Active from CLK – 11 nS

TTLH TRDY# Inactive from CLK – 11 nS

TTHZ TRDY# High before High Z 1 1 CLK

TDZL DEVSEL# Active from CLK – 11 nS

TDLH DEVSEL# Inactive from CLK – 11 nS

TDHZ DEVSEL# High before High Z 1 1 CLK

TISC IRDY# Setup to CLK 7 – nS

IHC IRDY# Hold from CLK 2 – nS

65540 / 545 AC TIMING CHARACTERISTICS - PCI BUS FRAME

Electrical Specifications

Revision 1.2 251 65540 / 545

Hi-Z

CLK

FRAME#

Read AD[31:0]

TFRS

Hi-Z

1 2 3 4

Hi-Z

IRDY#

Hi-Z Command Byte Enables

TBES

TCMS TCMH TBEH

C/BE#[3:0] Byte Enables Hi-Z

DEVSEL#

Bus

Turnaround

Bus

Turnaround

TTHZ

TTZH

TIHCTISC

TTLHTTHL

Hi-Z Hi-Z

TDLHTDZL

Hi-Z Hi-Z

TRDY# Hi-Z Hi-ZBus

Turnaround

Bus

Turnaround

Bus

Turnaround

TDHZ

Bus

Turnaround

TDAD

Read DataAddress

TADS TADH TDAH

Hi-Z

Write AD[31:0] Bus

Turnaround

TADS TADH TDAH

Write DataAddress Hi-ZHi-Z

TDAS

Read

Turnaround

Write Data

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

PCI Bus Frame Timing

Note: The above diagram shows a typical PCI bus cycle. PCI bus read cycles require a bus turn-around cycle between address output

and data input on AD31:0. PCI bus write cycles do not require this bus turnaround cycle so the write data is available from the

bus master immediately after address output (in clock cycle 2 instead of clock cycle 3).

Electrical Specifications

Revision 1.2 252 65540 / 545

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Symbol Parameter Notes Min Max Units

TSZH STOP# High Z to High from CLK – 11 nS

TSHL STOP# Active from CLK – 11 nS

TSLH STOP# Inactive from CLK – 11 nS

SHZ STOP# High before High Z 1 1 CLK

TSHZ

TSLHTSZH

CLK

STOP#

TSHL

High Z

65540 / 545 AC TIMING CHARACTERISTICS - PCI BUS STOP

PCI Bus Stop Timing

Electrical Specifications

Revision 1.2 253 65540 / 545

Symbol Parameter Notes Min Typ Max Units

TCPW Command Strobe Pulse Width 6Tm – – nS

TCHR Command Strobe Hold from Ready 0 – – nS

TNXT Command Strobe Inactive to Next Strobe 3Tm – – nS

TALE Address Setup to ALE Inactive 29 – – nS

TASC Address Setup to Command Strobe 30 – – nS

TICS Address to IOCS16# & MEMCS16# Delay – – 2Tm nS

TRSR Read Data Setup to Ready Mem Accesses Only 25 – – nS

TRPW RDY Pulse Width Mem Accesses Only 0 – 100Tm nS

TAHC Address Hold to Command Strobe 20 – – nS

TRDH Read Data Hold from Command Strobe 10 – – nS

TRDZ Read Data Tri-Stated from Command Strobe – – 30 nS

TWDD Write Data Delay from Command Strobe – – 20 nS

TWDH Write Data Hold from Command Strobe 10 – – nS

TRLC RDY Low Delay from Command Strobe (+5V) Mem Accesses Only – – 40 nS

RLC

RDY Low Delay from Command Strobe (+3.3V) Mem Accesses Only – – 55 nS

65540 / 65545 AC TIMING CHARACTERISTICS - ISA BUS

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

TAHC

Command Strobe

IORD#, IOWR#

MEMR#, MEMW#

TCPW TNXTTASC

RFSH#, AEN,

A0-19, BHE#

Data (Read)

Data (Write)

TRSR

TWDD TWDH

TRDZ

TRDH

RDY

TRLC TRPW TCHR

IOCS16#, MCS16#

TICS

TALE

ALE

ISA Bus Timing

Electrical Specifications

Revision 1.2 254 65540 / 545

65540 / 65545 AC TIMING CHARACTERISTICS - DRAM READ / WRITE

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Symbol Parameter Notes Min Max Units

TRC Read/Write Cycle Time 12Tm – 5 – nS

TRAS RAS# Pulse Width 8Tm – 5 – nS

TRP RAS# Precharge 4Tm – 3 – nS

TCRP CAS# to RAS# Precharge 4Tm – 5 – nS

TCSH CAS# Hold from RAS# 5Tm – 2 – nS

TRCD RAS# to CAS# Delay 3Tm – 5 – nS

TRSH RAS# Hold from CAS# 2Tm – 5 – nS

TCP CAS# Precharge Tm – 5 – nS

TCAS CAS# Pulse Width 2Tm – 5 – nS

TASR Row Address Setup to RAS# Tm – 5 – nS

TASC Column Address Setup to CAS# 2Tm – 8 – nS

TRAH Row Address Hold from RAS# Tm – 2 – nS

TCAH Column Address Hold from CAS# Tm – 2 – nS

TCAC Data Access Time from CAS# XR05[2-1]=0 (3MCLK CAS Cycle) – 2Tm – 5 nS

XR05[2-1]=1 (4MCLK CAS Cycle) – 3Tm – 5 nS

TRAC Data Access Time from RAS# XR05[2-1]=0 (3MCLK CAS Cycle) – 5Tm – 2 nS

XR05[2-1]=1 (4MCLK CAS Cycle) – 6Tm – 2 nS

TDS Write Data Setup to CAS# Tm – 5 – nS

TDH Write Data Hold from CAS# Tm – 2 – nS

TPC CAS Cycle Time 3Tm – 1 – nS

TWS WE# Setup to CAS# 1Tm – 5 – nS

WE# Hold from CAS# 2Tm – 5 – nS

DRAM Page Mode Read Cycle Timing

Revision 1.2 255 65540 / 545

Electrical Specifications

TCAH TASR

TASC

TRAS

ColumnColumn

RAS#

CAS#

Address

WE#

TRP

TRC

TCRP TRCD

TCAS TCAS

TPC TRSH

TCP

TCSH

TASR TRAH TCAH TASC

RowRow

TCAC

Data

TCAC

Read Read

High Z High Z

High Z TRAC

Note: The above diagrams represent typical page mode cycles. The number of actual CAS cycles may vary.

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

DRAM Page Mode Write Cycle Timing

TCSH

TCAH

TDH

TASR

TDSTDS

Write Data

TWH

TWS

TDH

RAS#

CAS#

Address

WE#

Data

TRP

TCRP TRCD

TCAS TCAS

TPC TRSH

TCP

TASR TRAH TASC TASC TCAH

TRAS TRC

ColumnRow Row

Write Data

Column

Electrical Specifications

Revision 1.2 256 65540 / 545

65545 AC TIMING CHARACTERISTICS - DRAM READ / MODIFY / WRITE

Symbol Parameter Notes Min Max Units

TRRMW RAS# Pulse Width 16Tm – 5 – nS

TCRMW CAS# Pulse Width 6Tm – 5 – nS

TAWD Col Address to WE# Delay 6Tm – 8 – nS

TRWD RAS# to WE# Delay 7Tm – 5 – nS

TCPWD CAS# Precharge to WE# Delay 5Tm – 5 – nS

TOEZ Output Turnoff Delay from OE# – Tm nS

TOEW OE# Write Data Delay Tm + 3 – nS

TOER OE# Read Data Delay XR05[1] = 0 (3 MCLK CAS Cycle) – 2Tm – 5 nS

OER

OE# Read Data Delay XR05[1] = 1 (4 MCLK CAS Cycle) – 3Tm – 5 nS

Note: Read Modify Write timing for 65545 only.

DRAM Page Mode Read Modify Write Cycle Timing

Note: The above diagrams represent typical page mode cycles. The number of actual CAS cycles may vary.

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

ColumnColumn

Write

TCAC

TCP

TRWD

OE#

Data

TCPWD

RAS#

CAS#

Address

TCAH

TCRP TRCD TCRMW TCRMW

TASR TRAH TASC TASC TCAH

TRRMW

Row Row

TAWD

WE#

TOEZ TDS TDH

TOER

TOEW

Write

TCAC

TDS TDH

TOER

TOEZ

TOEW

Read

CAS-Before-RAS ( CBR ) DRAM Refresh Cycle Timing

Electrical Specifications

Revision 1.2 257 65540 / 545

TRAS

TCHRTCSR

RAS#

CAS#

Symbol Parameter Notes Min Typ Max Units

TCHR RAS# to CAS# Delay Tm = 15.4 @ 65 MHz 5Tm – 5 – – nS

TCSR CAS# to RAS# Delay Normal Operation Tm – 5 – – nS

Standby Mode 2Tm – 5 – – nS

RAS

RAS# Pulse Width 5Tm = 89 ns (56 MHz) or 77 ns (65 MHz) 5Tm – 5 – – nS

65540 / 65545 AC TIMING CHARACTERISTICS - CBR REFRESH

TRASS

TRPC TCHS

RAS#

CAS#

TRP TRPS

TCSR

TCPN

Address

Dout High Z

'Self-Refresh DRAM' Refresh Cycle Timing

65540 / 65545 AC TIMING CHARACTERISTICS - SELF REFRESH

Note: Upon exiting self-refresh mode, the 65540 / 65545 will perform a complete set of CBR refresh cycles before resuming normal

DRAM activity. The duration of the burst refresh will equal the panel power sequencing delay, programmed in XR5B bits 7-4.

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Symbol Parameter Notes Min Typ Max Units

TRASS RAS# Pulse Width for Self-Refresh 100 – – µS

TRP RAS# Precharge 4Tm – 3 – – nS

TRPS RAS# Precharge for Self-Refresh 10Tm – – nS

TRPC RAS# to CAS# Delay 3Tm – 5 – – nS

TCSR CAS# to RAS# Delay Normal Operation Tm – 5 – – nS

Standby Mode 2Tm – 5 – – nS

TCHS CAS# Hold Time 0 – – nS

CPN

CAS# Precharge Tm – 5 – – nS

CRT Output Timing

Electrical Specifications

Revision 1.2 258 65540 / 545

Symbol Parameter Notes Min Max Units

TSYN HSYNC, VSYNC delay from VCLK in – 50 nS

TSYN HSYNC, VSYNC delay from VCLK in (3.3V) – 80 nS

TSD VCLK in to SHFCLK delay – 30 nS

SD VCLK in to SHFCLK delay (3.3V) – 50 nS

VCLK in TSYN

HSYNC, VSYNC out

SHFCLK out

TSD

65540 / 545 AC TIMING CHARACTERISTICS - CRT OUTPUT TIMING

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Symbol Parameter Notes Min Max Units

TPVS Video Data setup to PCLK 12 – nS

PVH

Video Data hold to PCLK 0 – nS

65540 / 545 AC TIMING CHARACTERISTICS - PC VIDEO TIMING

PC Video Timing

PCLK

HSYNC

VSYNC

TPVH

Video Data TPVS

Last

Line

Data

Transfer

First

Line

Data

Transfer

Second

Line

Data

Transfer

TDH

TDSU

TL2S

TFSU TFSH

TS2L

Data

SHFCLK

FLM

Flat Panel Vertical Refresh

FLM

TDLY

Electrical Specifications

Revision 1.2 259 65540 / 545

Symbol Parameter Notes Min Max Units

TDSU Panel Data Setup to SHFCLK 5 – nS

TDH Panel Data Hold to SHFCLK 10 – nS

TDLY Panel Data Delay from SHFCLK 10 – nS

TL2S SHFCLK Allowance Time from LP Tc – nS

TS2L LP Allowance Time from SHFCLK Tc – nS

TFSU FLM Setup Time 8 Tc – nS

FSH FLM Hold Time 8 Tc – nS

65540 / 545 AC TIMING CHARACTERISTICS - PANEL OUTPUT TIMING

Panel Output Timing

Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.

Electrical specifications contained herein are preliminary and subject to change without notice.

Revision 1.2 260 65540 / 545

Electrical Specifications

208-Pin

Plastic Flat Pack

Height

4.07 (0.160)

Maximum

Seating Plane

Body Size 28.0 ±0.1 (1.102 ±0.004)

Footprint 30.6 ±0.4 (1.205 ±0.016)

Pin 1

DIMENSIONS:

mm (in)

Clearance

0.25 (0.010)

Minimum

Body Size 28.0 ±0.1 (1.102 ±0.004)

Footprint 30.6 ±0.4 (1.205 ±0.016)

Lead Length

0.5 ±0.2

(0.020 ±0.008)

0.50 (0.0197)

Lead Pitch

(0.008 ±0.004)

Lead Width

0.20 ±0.10

F6554x R

XXXXXXX

YYWW CCCCCC

LLLLLLL

CHIPS Part No. and Revision

Vendor Mask Identifier

Date Code and Country of Assembly

Lot Code (Optional)

Mechanical Specifications

Revision 1.2 261 65540 / 545

Title: 65540 / 545 Data Sheet

Publication No.: DS170.2

Stock No.: 010170-002

Revision No.: 1.2

Date: 10/30/95

Chips and Technologies, Inc.

2950 Zanker Road

San Jose, California 95134

Phone: 408-434-0600

FAX: 408-894-2080