PCA9450CHNY - NXP SEMICONDUCTORS - Datasheet.Directory

PCA9450

Power management IC for i.MX 8M application processor

family

Rev. 2.1 — 7 December 2020 Product data sheet

1 General description

PCA9450 is a single chip Power Management IC (PMIC) specifically designed to

support i.MX 8M family processor in both 1 cell Li-Ion and Li-polymer battery portable

application and 5 V adapter non-portable applications. It supports various memory types

(DDR4/LPDDR4/DDR3L, etc.) via system UBOOT configuration, which does not require

hardware change.

The device provides six high efficiency step-down regulators, five LDOs, one 400 mA

load switch, 2-channel level translator and 32.768 kHz crystal oscillator driver.

Three buck regulators support Dynamic Voltage Scaling (DVS) feature along with

programmable ramping up and down time and those buck regulators support remote

sense to compensate IR drop to load from buck regulator. This device is characterized

across -40 °C to 105 °C ambient temperature range.

Six step-down regulators are designed to provide power for i.MX 8M application

processor and DRAM memory. Two LDOs, LDO1 and LDO2, feature very low quiescent

current to provide power for Secure Non-Volatile Storage (SNVS) since these LDOs are

always ON when input voltage is valid.

PCA9450 integrates logic translator which is a 2-bit, dual supply translating transceiver

with auto direction sensing. It enables bidirectional voltage level translation. It can be

used as I2C level translator. 400 mA load switch is to supply 3.3 V power supply to SD

card, which has internal discharge resistor.

PCA9450 has three versions: PCA9450AA is companion PMIC for (i.MX 8M Mini),

PCA9450B is companion PMIC for i.MX 8M Nano and PCA9450C is companion PMIC

for i.MX 8M Plus.

The PCA9450 is offered in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch.

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

2 Features and benefits

•Six high-efficiency step-down regulators

–Three 3 A buck regulators with DVS feature and remote sense

– PCA9450AA – Three 3 A buck regulators

– PCA9450B – Two 3 A buck regulators

– PCA9450C – 6 A dual-phase buck regulator and 3 A buck regulator

•One 3 A buck regulator

•Two 2 A buck regulators

•Five linear regulators

–Two 10 mA LDOs

–One 150 mA LDO

–One 200 mA LDO

–One 300 mA LDO

•Support various memory types: DDR4/LPDDR4/DDR3L via system UBOOT

configuration, no hardware change required

•400 mA load switch with built-in active discharge resistor

•32.768 kHz crystal oscillator driver and buffer output

•Two channel logic level translator

•Power control IO

–Power ON/OFF control

–Standby/run mode control

•Fm+ 1 MHz I2C-bus interface

•ESD protection

–Human Body Model (HBM) : +/- 2000 V

–Charged Device Model (CDM) : +/-500 V

•7 mm x 7 mm, 56-pin HVQFN with 0.4 mm pitch

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

3 Applications

•IoT Devices

•Tablet

•Electronic Point of Sale (ePOS)

•Industrial application

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

4 Ordering information

Package

Type number Topside

marking

AP platform

Name Description Version

PCA9450AAHN PCA9450AA i.MX 8M Mini HVQFN56 thermal enhanced very thin quad flat

package; no leads; 56 terminals; 0.4 mm

pitch, 7 mm x 7 mm x 0.85 mm body

SOT949-6

PCA9450BHN PCA9450B i.MX 8M Nano HVQFN56 thermal enhanced very thin quad flat

package; no leads; 56 terminals; 0.4 mm

pitch, 7 mm x 7 mm x 0.85 mm body

SOT949-6

PCA9450CHN PCA9450C i.MX 8M Plus HVQFN56 thermal enhanced very thin quad flat

package; no leads; 56 terminals; 0.4 mm

pitch, 7 mm x 7 mm x 0.85 mm body

SOT949-6

Table 1. Ordering information

Type number Orderable part

number

Package Packing method Minimum order

quantity

Temperature range

PCA9450AAHN PCA9450AAHNY HVQFN56 REEL 13" Q1 DP 2000 -40 °C to +105 °C

PCA9450BHN PCA9450BHNY HVQFN56 REEL 13" Q1 DP 2000 -40 °C to +105 °C

PCA9450CHN PCA9450CHNY HVQFN56 REEL 13" Q1 DP 2000 -40 °C to +105 °C

Table 2. Ordering options

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

5 Block diagram

aaa-035069

PCA9450

SBIAS, REF,

UVLO,

TSHDN

BUCK2

0.85 V

3 A

INT LDO

VINT

PMIC_RST_B

PMIC_ON_REQ

PMIC_STBY_REQ

NVCC_SNVS

LDO1

WDOG_B

RTC_RESET_B

POR_B

LDO1

DVS

PGND

INB26

LX2

10 µF

22 µF

0.47 µH

R_SNSP2

VSYS

(1)

VDD_ARM

100 kΩ

100 kΩ4.7 kΩ4.7 kΩ

VSYS

SYS

1 µF

LDO1

NVCC_1V8

BUCK5

NVCC_1V8

BUCK5

SCL

l2C

INTERFACE

SDA

IRQ_B

4.7 kΩ4.7 kΩ

SCLL

VINT SWIN

SDAL

4.7 kΩ4.7 kΩ

X-tal

LDO1

MUX

3V3 V

BUCK4

SDAH

SCLH

32.768 kHz

X-TAL DRIVER

LDO1

1.8 V

10 mA

XTAL_IN

INL1

LDO1

LDO2

LDO3

LDO4

LDO5

SD_VSEL

SYS

XTAL_OUT

CLK_32K_OUT

l2C LEVEL

TRANSLATOR

4.7 µF

NVCC_SNVS

1 µF

LDO2

0.85 V

10 mA

VDD_SNVS

1 µF

LDO3

1.8 V

300 mA

VDDA_1V8

2.2 µF

LDO4

0.9 V

200 mA

VDD_PHY_0V9

1 µF

LDO5

3.3 V/1.8 V

150 mA

NVCC_SD2

1 µF

BUCK1

0.85 V

3 A

DUAL

PHASE

CONFIG

PCA9450C

DVS

PGND

INB13

LX1

10 µF

22 µF

0.47 µH

R_SNSP1

VSYS

VDD_SOC

BUCK3

0.85 V

3 A

ON/OFF

CONTROL

AND

I2C

DVS

PGND

INB13

LX3

10 µF

0.47 µH

R_SNSP3_CFG

VSYS

VDD_V/GPU

VDD_DRAM

22 µF

BUCK4

3.3 V

3 A

PGND

INB45

LX4

10 µF

22 µF

0.47 µH

BUCK4FB

VSYS

NVCC_3V3

BUCK5

1.8 V

2 A

BUCK6

1.1 V

2 A

PGND

INB45

LX5

4.7 µF

22 µF

0.47 µH

BUCK5FB

VSYS

NVCC_1V8

LOAD SW

DRIVER

PGND

INB26

LX6

4.7 µF

1 µF

0.47 µH

BUCK6FB

SWIN

SWOUT

SW_EN

EPAGND

VSYS

BUCK 4

NVCC_DR AM

SD_CARD

22 µF

(1) This capacitor is decoupling capacitor in MCU side.

Figure 1. Block diagram

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

6 Pinning information

6.1 Pinning

aaa-035701

PMIC_STBY_REQ

PMIC_ON_REQ

R_SNSP1

SDA

SCL

Figure 2. PCA9450 pin map – Top View

6.2 Pin description

Pin description

Symbol Pin Type Description

LDO4 1 P LDO4 output. Bypass with a 1 µF to Ground.

LDO2 2 P LDO2 output. Bypass with a 1 µF to Ground.

LDO1 3 P LDO1 output. Bypass with a 1 µF to Ground.

VINT 4 P Internal Power supply output pin. Bypass with 1 µF to

Ground.

AGND 5 GND

Analog ground pin. It should be connected to ground

plane through Via. Do not short to EP directly on top

layer

Table 3. Pin description

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Pin description

Symbol Pin Type Description

RTC_RESET_B 6 DO

Reset output pin. It is High-Z after both LDO1 and

LDO2 voltage are good. It is internally pulled up with

LDO1 power rail

CLK_32K_OUT 7 DO 32.768 kHz clock CMOS output with LDO1 power rail.

PMIC_RST_B 8 DI

PMIC reset input pin. It is internally pulled up with

LDO1 power rail. Once it is asserted low, PMIC

performs reset.

POR_B 9 DO Power On reset output pin. Open drain output requiring

external pull up resistor.

XTAL_IN 10 AI 32.768 kHz crystal oscillator input, tie to GND if X-tal is

not used

XTAL_OUT 11 AO 32.768 kHz crystal oscillator output, leave floating if X-

tal is not used

SW_EN 12 DI Load switch enable input pin. It has internal 1.5 MΩ pull

down resistor.

IRQ_B 13 DO Open drain output to indicate Interrupt issued. It

requires external pull up resistor.

BUCK5FB 14 AI BUCK5 output voltage sensing pin. If BUCK5 is not

used, tie to INB45.

LX5 15 P BUCK5 switching node. If BUCK5 is not used, leave it

floating.

INB45 16,17,18 P BUCK4 / BUCK5 Input pins. Bypass with 10 µF and

4.7 μF to Ground

LX4 19,20 P BUCK4 switching node. If BUCK4 is not used, leave

them floating.

BUCK4FB 21 AI BUCK4 output voltage sensing pin. If BUCK4 is not

used, tie to INB45.

SWIN 22 P

Load switch input pin. Bypass with a 1 µF to Ground.

Leave it floating if not used (must connect to BUCK4,

3.3 V, if I2C level translator is used).

SWOUT 23 P Load switch output pin. Bypass with a 1 µF to Ground.

Leave it floating if not used.

SDAH 24 DIO Level translator high voltage IO pin, SDA referenced to

SWIN, 3.3 V

SCLH 25 DO Level translator high voltage IO pin, SCL referenced to

SWIN, 3.3 V

SDAL 26 DIO Level translator low voltage IO pin, SDA referenced to

VINT, 1.8 V

SCLL 27 DO Level translator low voltage IO pin, SCL referenced to

VINT, 1.8 V

WDOG_B 28 DI Active low watchdog reset input pin from application

processor.

Table 3. Pin description...continued

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Pin description

Symbol Pin Type Description

SD_VSEL 29 DI

LDO5 voltage selection input pin. LDO5 output is 3.3 V

when it is driven low and 1.8 V when driven high. VSEL

pin should be tied low or high. Do not leave it floating.

R_SNSP3_CFG 30 AI

BUCK3 output voltage remote sense pin in

PCA9450AA.

Logic input pin in PCA9450B/C. This pin should be tied

to SYS in PCA9450B, where BUCK3 is disabled. This

pin is tied to GND in PCA9450C, where BUCK1 and

BUCK3 are configured as dual phase buck regulator.

LX3 31,32 P

BUCK3 switching node

If BUCK3 is not used by shorting R_SNSP3_CFG to

VSYS, leave LX3 pins floating.

INB13 33,34,35 P BUCK1 / BUCK3 Input. Bypass with two 10 µF to

Ground

LX1 36,37 P BUCK1 switching node. Leave it floating if not used.

R_SNSP1 38 AI BUCK1 output voltage remote sensing pin. Tie to

INB13 if not used.

PMIC_ON_REQ 39 DI PMIC ON input from Application processor. When it is

asserted high, the device starts power on sequence.

PMIC_STBY_REQ 40 DI Standby mode input from Application processor. When

it is asserted high, device enters STANDBY mode.

SCL 41 DI I2C serial clock pin

SDA 42 DIO I2C serial data pin

BUCK_AGND 43 GND

Buck reference GND for BUCK1,2,3. It should be

connected to ground plane through Via. Do not short to

EP directly on top layer

R_SNSP2 44 AI BUCK2 output voltage remote sensing pin. Tie to

INB26 if not used.

LX2 45,46 P BUCK2 switching node. Leave them floating if not

used.

INB26 47,48,49 P BUCK2 / BUCK6 Input. Bypass with 10 µF and 4.7 µF

to Ground

LX6 50,51 P BUCK6 switching node. Leave it floating if not used.

BUCK6FB 52 AI BUCK6 output voltage sensing pin. Tie to INB26 if not

used.

VSYS 53 P Internal power input. Bypass with a 1 µF to Ground

LDO3 54 P LDO3 output. Bypass with a 2.2 µF to Ground.

LDO5 55 P LDO5 output. Bypass with a 1 µF to Ground.

INL1 56 P Power input pin for LDO1, LDO2, LDO3, LDO4 and

LDO5. Bypass with a 4.7 µF to Ground.

EP GND Exposed PAD. All buck PGNDs are internally

connected.

Table 3. Pin description...continued

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

7 Functional description

7.1 Features

The PCA9450 is a power management integrated circuit (PMIC) designed to be the

primary power management for NXP application processors, i.MX 8M Mini, Nano and

Plus.

•Buck regulators

–BUCK1, BUCK2, BUCK3 : 0.6 V to 2.1875 V, 12.5 mV step, 3000 mA

–BUCK4 : 0.6 V to 3.4 V, 25 mV step, 3000 mA

–BUCK5, BUCK6 : 0.6 V to 3.4 V, 25 mV step, 2000 mA

–Dynamic Voltage scaling on BUCK1, BUCK2 and BUCK3

–Support remote sensing on BUCK1, BUCK2 and BUCK3

–BUCK1-BUCK3 configurable as a 6 A dual phase regulator (PCA9450C)

–Monitor fault condition

•LDO regulators

–LDO1, 1.6 V to 1.9 V, 3.0 V to 3.3 V 100 mV step, 10 mA

–LDO2, 0.8 V to 1.15 V with 50 mV step,10 mA

–LDO3, 0.8 V to 3.3 V with 100 mV step, 300 mA

–LDO4, 0.8 V to 3.3 V with 100 mV step, 200 mA

–LDO5, 0.8 V to 3.3 V with 100 mV step, 150 mA, Voltage selection through SD_VSEL

–Monitor fault condition

•Support various memory types: DDR4/LPDDR4/DDR3L via system UBOOT

configuration, no hardware change required

•400 mA Load switch for SD card

–Built-in OCP protection

–GPIO/I2C control

–Built-in Active discharge resistor

•Two Channel logic level translator

•32.768 kHz Crystal Oscillator driver

–Mux output with internal 32 kHz output

•Protection and Monitoring: Soft start, Power Rails Fault detection, UVLO, Thermal

Shutdown

•Configurable reset behavior from WDOGB, PMIC_RST_B and SW_RST Register

•Power control IO

–PMIC_ON_REQ, PMIC_STBY_REQ

•Fm+ 1 MHz I2C-bus interface

•Type3 PCB applicable

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

7.2 Functional diagram

aaa-035702

Regulators

PCA9450 Functional Internal Block diagram

LDO1

(1.6 V-1.9 V, 3.0 V-3.3 V,

100 mV Step)

10 mA

LDO2

(0.85 V to 1.15 V,

50 mV Step)

10 mA

LDO3

(0.8 V to 3.3 V,

100 mV Step)

300 mA

LDO4

(0.8 V to 3.3 V,

100 mV Step)

200 mA

LDO5

(1.8 V to 3.3 V,

100 mV Step)

150 mA

BUCK1

(0.6 V to 2.1875 V,

12.5 mV Step)

3000 mA, 0.85 V

DVS

BUCK2

(0.6 V to 2.1875 V,

12.5 mV Step)

3000 mA, 0.85 V

DVS

BUCK3

(0.6 V to 2.1875 V,

12.5 mV Step)

3000 mA, 0.85 V

DVS

BUCK4

(0.6 V to 3.4 V,

25 mV Step)

3000 mA, 3.3 V

BUCK5

(0.6 V to 3.4 V,

25 mV Step)

2000 mA, 1.8 V

BUCK6

(0.6 V to 3.4 V,

25 mV Step)

2000 mA, 1.1 V

Lin

Thermal Warning / Protection

UVLO Current limit

400 mA load switch

AP logic control

I2C communication

Internal Bias

Power on sequence / Timing

32 kHz Osc driver / Buffer

Figure 3. PCA9450 functional block diagram

The PCA9450 is a single chip Power Management IC (PMIC) specifically designed to

support i.MX 8M family processor in both 1 cell Li-Ion and Li-polymer battery portable

application and 5 V adapter non-portable applications.

PCA9450 is provided in three versions: PCA9450AA, PCA9450B and PCA9450C

depending on target application processor. Table 4 shows the selection guide.

Part number AP Platform BUCK1 BUCK3 LDO4 R_SNSP3_CFG

PCA9450AA i.MX 8M Mini 3 A for SOC

(ON by default)

3 A for VPU/GPU/

DRAM

(ON by default)

0.9 V for VDDA

(ON by default)

R_SNSP3_CFG is feedback

of BUCK 3

PCA9450B i.MX 8M Nano

3 A for SOC /

VPU/GPU/DRAM

(ON by default)

Disabled OFF by default R_SNSP3_CFG = VSYS

PCA9450C i.MX 8M Plus

6 A Dual phase for SOC/VPU/GPU/

DRAM

(ON by default)

OFF by default R_SNSP3_CFG = GND

Table 4. PCA9450 selection guide

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

7.3 Power modes

PCA9450 has eight power modes: OFF, READY, SNVS, RUN, STADNBY, PWRDN,

PWRUP and FAULT_SD. Figure 4 shows the state transition diagram showing the

conditions to enter and exit each state.

aaa-035703

PMIC_STBY_REQ = L

OFF

SNVS

Run

STANDBY

Ready

PWRDN Seq PWRUP Seq

VSYS_POR = 0

VSYS_POR = 1

VSYS_UVLO = 0VSYS_UVLO = 1

PMIC_ON_REQ = L

Or Cold Reset

PMIC_ON_REQ = H

PMIC_STBY_REQ = H

PMIC_ON_REQ = L

Or Cold reset

Any

State

VSYS_POR = 1

VSYS_UVLO = 1

FAULT_SD

VR_FLT

THSD = 0 or LDO1/2 FLT Clear

VR_FLT Clear

Figure 4. Power States Diagram

7.3.1 Off mode

PCA9450 enters OFF mode from any state when VSYS falls below VSYS_POR threshold.

All regulators are off and all registers get reset in this mode.

7.3.2 READY mode

PCA9450 enters READY mode from OFF mode when VSYS is higher than VSYS_POR.

Internal LDO VINT is enabled and loads Multiple Time Program (MTP) data to registers.

Once MTP loading is done, it is ready to transition to SNVS mode.

7.3.3 SNVS mode

PCA9450 enters Secure Non-Volatile Storage mode (SNVS) when VSYS exceeds

VSYS_UVLO threshold. LDO1 and LDO2 are powered up and 32.768 kHz buffer starts

running. RTC_RESET_B is pulled high in tRTC_RST after both LDO1 and LDO2 voltage

come up.

PMIC_ON_REQ input is masked until RTC_RESET_B is released. PCA9450 starts

power up sequence if PMIC_ON_REQ is asserted high in this mode.

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035704

NVCC_SNVS

VDD_SNVS

LDO1

LDO2

VSYS UVLO

tSNVS_PU

tSTEP

tRTC_Tran

t32K_EN

RTC_RESET_B

OFF SNVS OFFMode

UVLO

CLK_32K_OUT

Int RC Osc

X-tal Osc

POR

VINT

POR

Ready

tRTC_RST

Figure 5. SNVS mode ON/OFF sequence

Time Description Value

tSNVS_PU Time to LDO1 turn on from VSYS UVLO detected 20 ms

tSTEP Time to LDO2 ON from LDO1 POK 2 ms

tRTC_RST Time to RTC_RESET_B release from LDO2 POK 20 ms

T32K_EN Time to 32k buffer Enable from LDO2 POK 10 ms

tRTC_Tran Time to transition to Xtal output from RC osc after

RTC_RESET_B release

1 sec

Table 5. SNVS mode

7.3.4 PWRUP mode

After RTC_RESET_B is released in SNVS mode, it starts power up with pre-defined

sequence when PMIC_ON_REQ is asserted high for longer than debounce time,

tON_DEB, which is programmable in PWR_CTRL reg. BUCK1 begins turning ON at first

and then each power rail is followed with tstep after POK of predecessor power rail.

During PWRUP mode, PMIC_STBY_REQ signal is masked until POR_B is released. The

PWRUP mode ends up releasing POR_B and PCA9450 is transitioned to RUN mode.

Figure 6 shows Power on sequence of PCA9450AA.

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035706

VDD_DRAM

VDD_G/VPU

BUCK3

PHY_0P9

LDO4

VDD_SOC

VDDA_1P8

VDDA_DRAM

NVCC_1V8

NVCC_3V3

NVCC_DRAM

POR_B

BUCK1

LDO3

BUCK5

BUCK4

BUCK6

PMIC_STBY_REQ

PMIC_ON_REQ

VDD_ARM

BUCK2

NVCC_SD2

LDO5

SNVS RUN SNVSMode

Masked

PWRDN

POK

Masked

PWRUP

tON_DEB

LDO4/BUCK3 is MTP programmable to be selected in power up/down sequence.

Figure 6. PCA9450AA power ON/OFF sequence

BUCK3 and LDO4 are OFF by default in PCA9450B and PCA9450C. Those regulators

are removed in the power up sequence, shown in Figure 7.

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035707

BUCK1

LDO3

BUCK5

BUCK4

BUCK6

BUCK2

LDO5

Masked Masked

POK

tON_DEB

LDO4/BUCK3 is MTP programmable to be selected in power up/down sequence.

Figure 7. PCA9450B/C power ON/OFF sequence

Time Description Value

tON_DEB Time to power-on start from PMIC_ON_REQ high 20 ms

tSTEP Time to next power rail ON from prev rail POK 2 ms

tPORB Time to POR_B release from the last rail POK 20 ms

tOFF_STEP Time to next power rail off from prev rail off 8 ms

tOFF_DEB Time to POR_B low from PMIC_ON_REQ falling 120 μs

Table 6. PWRUP mode

If any of regulators doesn’t generate POK within tFLT_SH_PU after receiving digital enable

during PWRUP mode, it is transitioned to Fault_SD mode.

7.3.5 PWRDN mode

When PMIC_ON_REQ is low for tOFF_DEB in RUN or STANDBY mode, PCA9450 enters

PWRDN mode. It starts with pulling down POR_B and then turning off each power rail in

tOFF_STEP and transitions to SNVS mode.

7.3.6 RUN mode

PCA9450 operates in RUN mode when PMIC_ON_REQ is driven high and

PMIC_STBY_REQ is driven low. BUCK1, BUCK2 and BUCK3 output voltage are set

to BUCK1OUT_DVS0, BUCK2OUT_DVS0 and BUCK3OUT_DVS0 register value,

respectively, when PRESET_EN bit in DVS123_DVS register is set to “0”. When

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

PMIC_STBY_REQ is asserted high in this mode, it is transitioned to STANDBY mode.

PMIC_ON_REQ is asserted low, it moves to PWRDN mode.

7.3.7 STANDBY mode

PCA9450 transitions to STANDBY mode from RUN mode when both PMIC_ON_REQ

and PMIC_STBY_REQ are driven high. BUCK1 and BUCK3 output voltage is set to

BUCK1OUT_DVS1 and BUCK3OUT_DVS1 and BUCK2 are turned off when DVS_CTRL

bit in each BUCKx_CTRL register is configured to 1.

If PMIC_ON_REQ is asserted low, then it transitions to PWRDN mode. If

PMIC_STBY_REQ is driven low, then it transitions to RUN mode.

aaa-035708

PHY_0P9

LDO4

VDD_DRAM

VDD_G/VPU

BUCK3

VDD_SOC

VDDA_1P8

VDDA_DRAM

NVCC_1V8

NVCC_3V3

NVCC_DRAM

POR_B

BUCK1

LDO3

BUCK5

BUCK4

BUCK6

PMIC_STBY_REQ

PMIC_ON_REQ

VDD_ARM

BUCK2

NVCC_SD2

LDO5

RUN

Mode

DVS1

tOFF_Step

Figure 8. PCA9450AA mode transition

X : Don’t care

Power mode VSYS PMIC_ON_REQ PMIC_STBY_REQ

OFF VSYS < VSYS_POR X X

READY VSYS > VSYS_POR X X

SNVS VSYS > VSYS_UVLO Low X

STANDBY VSYS > VSYS_UVLO High High

Table 7. Power modes summary

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

X : Don’t care

Power mode VSYS PMIC_ON_REQ PMIC_STBY_REQ

RUN VSYS > VSYS_UVLO High Low

Table 7. Power modes summary...continued

7.3.8 FAULT_SD

PCA9450 has three types of fault sources.

1. Thermal shutdown : Transition to SNVS mode or READY mode after FAULT_SD

mode.

When junction temperature reaches TJSHDN, it enters FAULT_SD mode after tFLT_THSD

where regulators are turned off simultaneously. It stays at FAULT_SD until junction

temperature falls below TJSHDN. If the temperature drops below TJSHDN, then it moves

to READY state if any of LDO1 and LDO2 fault is triggered when thermal shutdown

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

happens, and it moves to SNVS mode if neither LDO1 or LDO2 fault is triggered when

thermal shutdown happens.

aaa-035710

NVCC_SNVS

VDD_SNVS

LDO1

LDO2

VSYS

RTC_RESET_B

CLK_32K_OUT

Int RC Osc

X-tal Osc

PHY_0P9

LDO4

VDD_DRAM

VDD_G/VPU

BUCK3

VDD_SOC

VDDA_1P8

VDDA_DRAM

NVCC_1V8

NVCC_3V3

NVCC_DRAM

POR_B

BUCK1

LDO3

BUCK5

BUCK4

BUCK6

VDD_ARM

BUCK2

NVCC_SD2

LDO5

Mode Any state FAULT_SD

Thermal

Shutdown

Event

NOTE1

SNVS

tFLT_THSD

Tj < TJSHDN

Note 1 : If LDO1/LDO2 triggers fault condition when junction temperature reaches thermal shutdown

threshold, LDO1/LDO2/RTC_RESETB/CLK_32K_OUT is turned off. Otherwise, they are kept on.

Figure 9. PCA9450 FAULT_SD from Thermal shutdown

Time Description Value

tFLT_THSD Time to reset released from Fault event 120 μs

Table 8. tFLT_THSD

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

2. Voltage regulator fault during power up: Transition to READY mode after

FAULT_SD mode.

Any POK of voltage regulators doesn’t come up within tFLT_SD_PU after regulator is

enabled during power up sequence. It stops power-up sequence and then moves to

FAULT_SD where all regulators are turned off. It stays at FAULT_SD for tFLT_SD_STAY

and transitions to READY state.

3. Voltage regulator fault in STANDBY and RUN MODE: Move to FAULT_SD mode in

tFLT_SD_WAIT after Fault is detected. Transition to SNVS mode or READY mode from

FAULT_SD mode when fault is removed.

During RUN and STANDBY mode, VR Fault status bit in VRFLT1_STS and

VRFLT2_STS registers is latched to “1” when corresponding regulator voltage falls

below POK threshold for tDEB_POKB, or POK doesn’t go high within tFLT_POK_MSK after

regulator is enabled.

If the fault status bit is masked in VRFLT1_MASK and VRFLT2_MASK registers,

it doesn’t enter FAULT_SD mode. Instead, PCA9450 stays at current mode. If the

fault register bit is unmasked, it starts tFLT_SD_WAIT timer. Application processor can

determine to enter FAULT_SD mode or not, by masking the VR Fault status bit in

VRFLTx_MASK registers before the timer expires. PCA9450 enters FAULT_SD mode

when the timer expires. PCA9450 stays in FAULT_SD mode for tFLT_SD_STAY.

aaa-035711

RUN/STANDBY

Mode

FAULT EVENT

INT

AP receives

INT Unmask fault register bit or Clear

the status bit when fault is cleared

RUN/STANDBY

Mode

FAULT EVENT

INT

AP receives

INT

FAULT_SD

tFLT_SD_WAIT starts

AP doesn't take an action until

timer is expired

Figure 10. PCA9450 Fault event

PCA9450 moves to READY mode after FAULT_SD mode if the regulator fault is caused

by LDO1 or LDO2. Otherwise, it moves to SNVS mode after FAULT_SD.

If either LDO1 or LDO2 has fault in SNVS mode, then it enters FAULT_SD mode

regardless of VRFLT1 Mask bit.

PCA9450 doesn’t enter FAULT_SD mode from load switch overcurrent fault.

Product data sheet Rev. 2.1 — 7 December 2020

18 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035712

NVCC_SNVS

VDD_SNVS

LDO1

LDO2

VSYS

RTC_RESET_B

CLK_32K_OUT

Int RC Osc

X-tal Osc

PHY_0P9

LDO4

VDD_DRAM

VDD_G/VPU

BUCK3

VDD_SOC

VDDA_1P8

VDDA_DRAM

NVCC_1V8

NVCC_3V3

NVCC_DRAM

POR_B

BUCK1

LDO3

BUCK5

BUCK4

BUCK6

VDD_ARM

BUCK2

NVCC_SD2

LDO5

Mode Any state FAULT_SD

VR_FLT event

NOTE1

SNVS

tFLT_SD_WAIT

tFLT_SD_STAY VR_FLT Clear

Note 1 : If VR fault is caused by LDO1 or LDO2, then LDO1/LDO2/

RCT_REST_B/CLK_32K_OUT is turned OFF, otherwise, they are kept on.

Figure 11. PCA9450 FAULT_SD from VR Fault except LDO1/LDO2 in RUN/STANDBY

Time Description Value

tFLT_SD_WAIT Time to reset released from Fault event 100 ms

Table 9. tFLT_SD_WAIT

Product data sheet Rev. 2.1 — 7 December 2020

19 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

7.4 PMIC reset

PCA9450 has three reset input sources: WDOG_B pin, PMIC_RST_B pin and I2C reset

bit.

The reset behavior is configured in RESET_CTRL register for WDOG_B pin and

PMIC_RST_B pin. I2C reset behavior is configured in SW_RST register.

0x08 – RESET_CTRL Reset Type S

Bit Name Type Reset Description

7:6 WDOG_B_CFG R/W 00

When WDOG_B is asserted to L, PMIC behavior

00b = WDOG_B reset is disabled

01b = Warm Reset, POR_B pin is asserted low for 20 ms

10b = Cold Reset, All voltage regulators are recycled except LDO1/

LDO2

11b = Cold Reset, All voltage regulators are recycled

5:4 PMIC_RST_CFG R/W 10

When PMIC_RST_B is asserted to L, PMIC behavior

00b = PMIC_RST_B reset is disabled

01b = Warm Reset, POR_B pin is asserted low for 20 ms

10b = Cold Reset, All voltage regulators are recycled except

LDO1/LDO2

11b = Reserved

Table 10. 0x08 – RESET_CTRL

0x06 – SW_RST Reset Type O

Bit Name Type Reset Description

7:0 SW_RST R/W 0x00

Software reset register. This register read back to “0x00” right after

writing the value.

0x00 = No action

0x05 = Reset all registers to default value

0x14 = Cold reset (Power recycle all regulators except LDO1, LDO2

and CLK_32K_OUT)

0x35 = Warm Reset (Toggle POR_B for 20 ms)

0x64 = Cold reset (Power recycle all regulators)

Others = No action

Table 11. 0x06 – SW_RST

WDOG_B is asserted low, and gets reset depending on WDOG_B_CFG bit configuration.

When the bits are set to 2b00, the reset by WDOG_B pin is disabled. If the bits are set

to 2b01, warm reset is performed, where POR_B is pulled low for 20 ms and resets I2C

O type registers to default value keeping power rails remaining ON. If the bits are set to

2b11, it performs Cold reset, where all voltage regulators except LDO1 and LDO2 are

power recycled and I2C O type registers get reset to default value.

When PMIC_RST_B is asserted low, it also gets reset depending on PMIC_RST_CFG

bits configuration. When the bits are set to 2b00, any reset by PMIC_RST_B pin is

disabled. If the bits are set to 2b01, warm reset is performed, in which pulling POR_B low

for 20 ms and reset I2C O type registers to default value keeping power rails remaining

ON.

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Cold reset event is generated by either of I2C reset, WDOG_B falling edge or

PMIC_RST_B falling edge after debounce time. Once it is detected, POR_B is pulled

low and takes power down sequence. For cold reset from WDOG_B and I2C reset,

PCA9450 stays at RESET for tRESTART and then starts power on sequence even though

WDOG_B pin is still low. For cold reset from PMIC_RST_B, tRESTART timer starts after

PMIC_RST_B is asserted high; in other words, PCA9450 starts power on sequence in

tRESTART after PMIC_RST_B pin is released high.

aaa-035713

PHY_0P9

LDO4

VDD_DRAM

VDD_G/VPU

BUCK3

VDD_SOC

VDDA_1P8

VDDA_DRAM

NVCC_1V8

NVCC_3V3

NVCC_DRAM

POR_B

BUCK1

LDO3

BUCK5

BUCK4

BUCK6

Cold Reset

Sources

VDD_ARM

BUCK2

NVCC_SD2

LDO5

RUN/

STANDBY RESET

Mode PWRDN PWRUP

LDO1/2 tRESTART

tPOR_B

RUN/

STANDBY

POK

Note: BUCK3 and LDO4 are removed in Power ON/OFF sequence in PCA9450B/C

Figure 12. PCA9450AA Cold reset

Time Description Value

tRESTART Time to power ON seq from end of power OFF seq

during cold reset

250 ms

Table 12. tRESTART

Product data sheet Rev. 2.1 — 7 December 2020

21 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035715

PHY_0P9LDO4

VDD_DRAM

VDD_G/VPU

BUCK3

VDD_SOC

VDDA_1P8

VDDA_DRAM

NVCC_1V8

NVCC_3V3

NVCC_DRAM

POR_B

BUCK1

LDO3

BUCK5

BUCK4

BUCK6

Warm Reset

source

VDD_ARM

BUCK2

NVCC_SD2

LDO5

RUN/

STANDBY

Mode Reset

RUN/

STANDBY

All regulator output

goes to default voltage

tRESET

Figure 13. Warm reset

Time Description Value

tRESET POR_B low time at Warm reset 20 ms

Table 13. tRESET

7.5 Regulator control in each power mode

Table 14 shows PCA9450AA regulator ON/OFF control in each power mode by default. It

can be reconfigured through I2C registers.

Power Rail Default Voltage OFF SNVS STANDBY RUN

LDO1 NVCC_SNVS 1.8 V OFF ON ON ON

LDO2 VDD_SNVS 0.85 V OFF ON ON ON

BUCK1 VDD_SOC 0.85 V OFF OFF ON ON

BUCK3

VDD_DRAM

VDD_GPU VDD_

VPU

0.85 V OFF OFF ON ON

LDO4 PHY_0P9 0.9 V OFF OFF ON ON

Table 14. PCA9450AA Regulator Control summary

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Power Rail Default Voltage OFF SNVS STANDBY RUN

BUCK2 VDD_ARM 0.85 V OFF OFF OFF ON

LDO3 VDDA_1P8 1.8 V OFF OFF ON ON

BUCK5 NVCC_1V8 1.8 V OFF OFF ON ON

BUCK6 NVCC_DRAM 1.1 V OFF OFF ON ON

BUCK4 NVCC_3V3 3.3 V OFF OFF ON ON

LDO5 NVCC_SD2 3.3 V / 1.8 V OFF OFF ON ON

Table 14. PCA9450AA Regulator Control summary...continued

Table 15 shows PCA9450B/PCA9450C regulator ON/OFF control in each power mode

by default. It can be reconfigured through I2C registers.

Power Rail Default Voltage OFF SNVS STANDBY RUN

LDO1 NVCC_SNVS 1.8 V OFF ON ON ON

LDO2 VDD_SNVS 0.85 V OFF ON ON ON

BUCK1

VDD_SOC VDD_

DRAM VDD_GPU

VDD_VPU

0.85 V OFF OFF ON ON

LDO4 0.9 V OFF OFF OFF OFF

BUCK2 VDD_ARM 0.85 V OFF OFF OFF ON

LDO3 VDDA_1P8 1.8 V OFF OFF ON ON

BUCK5 NVCC_1V8 1.8 V OFF OFF ON ON

BUCK6 NVCC_DRAM 1.1 V OFF OFF ON ON

BUCK4 NVCC_3V3 3.3 V OFF OFF ON ON

LDO5 NVCC_SD2 3.3 V / 1.8 V OFF OFF ON ON

Table 15. PCA9450B/PCA9450C Regulator Control summary

7.6 Regulator summary

The PCA9450 features six buck regulators, five linear regulators and one load switch to

supply voltage rails powering the application processor and peripheral devices. The buck

regulators are supplied directly from the main input supply. The input to all of the buck

regulators must be tied to VSYS, whether they are powered on or off.

7.6.1 BUCK regulator

The PCA9450AA has six high-efficiency low Iq buck regulators. Each buck regulator

features soft start and overcurrent protection. Buck regulator operates in two modes:

PFM and PWM mode. It automatically transitions from PFM to PWM mode when FPWM

bit is set to “0”. Internal active discharge resistor is installed in each buck regulator output

to discharge voltage on output capacitors when regulator is off. It is configurable through

I2C register. Table 16 shows buck regulator summary.

BUCK1 and BUCK3 are configured as dual-phase buck regulator in PCA9450C and

provide up to 6 A. Table 17 shows PCA9450C buck summary.

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

BUCK# INPUT PIN Default VOUT

[V] VOUT range [V] Step size

[mV]

Default ON/

OFF

Current rating

[mA]

BUCK1 INB13 0.85 0.6 - 2.1875 12.5 ON 3000

BUCK2 INB26 0.85 0.6 - 2.1875 12.5 ON 3000

BUCK3 INB13 0.85 0.6 - 2.1875 12.5 ON 3000

BUCK4 INB45 3.3 0.6 - 3.4 25 ON 3000

BUCK5 INB45 1.8 0.6 - 3.4 25 ON 2000

BUCK6 INB26 1.1 0.6 - 3.4 25 ON 2000

Table 16. PCA9450AA Buck Summary

Buck# INPUT PIN Default VOUT

[V] VOUT range [V] Step size

[mV]

Default ON/

OFF

Current rating

[mA]

BUCK1 INB13 0.85 0.6 - 2.1875 12.5 ON 6000

BUCK2 INB26 0.85 0.6 - 2.1875 12.5 ON 3000

BUCK4 INB45 3.3 0.6 - 3.4 25 ON 3000

BUCK5 INB45 1.8 0.6 - 3.4 25 ON 2000

BUCK6 INB26 1.1 0.6 - 3.4 25 ON 2000

Table 17. PCA9450C Buck Summary

7.6.1.1 Dynamic voltage scaling

BUCK1, BUCK2 and BUCK3 support DVS (Dynamic Voltage Scaling). If PRESET_EN bit

in BUCK123_DVS register is set to 1, BUCK1/BUCK2/BUCK3 outputs are controlled by

Bx_DVS_PRESET bits in BUCK123_DVS. It enables those buck outputs to be controlled

by writing one register at a time.

If PRESET_EN bit is set to 0, those buck regulators outputs are determined by

BUCKxOUT_DVS0 and BUCKxOUT_DVS1 depending on PMIC_STBY_REQ

pin. When PMIC_STBY_REQ is asserted low, each buck output voltage is

determined by BUCKxOUT_DVS0 register, if the PMIC_STBY_REQ is asserted high,

BUCKxOUT_DVS1 register is selected as each buck output voltage. Figure 14 shows the

DVS voltage section diagram.

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035716

BUCK1, 2, 3

BUCKxOUT_DVS0

BUCK1, 2, 3

BUCKxOUT_DVS1

DVS0 : PMIC_STBY_REQ = L

DVS1 : PMIC_STBY_REQ = H

BUCKx Output

I2C

programmable

Bx_DVS_PRESET

0x0C Reg

HPRESET_EN

In 0x0C Reg

Min

Selection

BUCKxOUT_LIMIT

PMIC_STBY_REQ

Figure 14. DVS functional diagram

The programmable voltage ramp-up and ramp-down are applied during the DVS voltage

transition. The ramp rate is configured by RAMP[7:6] bits in each BUCKxCTRL registers.

DVS1

DVS

[

]

[

]

aaa-035718

Figure 15. DVS timing

7.6.1.2 BUCK output voltage limiting

Application processor may accidentally write higher voltage than absolute maximum

voltage rating of its power input, which may cause significant damage on application

processor. PCA9450 has registers to limit the maximum voltage to prevent such an

incident.

BUCK1, BUCK2 and BUCK3 maximum output are limited by BUCKxOUT_LIMIT,

respectively. Even if buck output is configured to higher than the limit voltage configured

in BUCKxOUT_LIMIT register, the actual buck output is clamped to the limiting voltage

set by BUCKxOUT_LIMIT register.

7.6.1.3 Dual-phase configuration

BUCK1 and BUCK3 are configured as dual phase buck in PCA9450C by connecting

R_SNSP3_CFG pin to GND, where this dual phase buck regulator is controlled

through BUCK1 registers. All BUCK3 registers are not responsive under dual-phase

configuration.

When R_SNSP3_CFG pin is tied to INB13 in PCA9450B, BUCK3 is disabled. BUCK1

supplies VDD_SOC/VDD_VPU/VDD_GPU/VDD_DRAM in i.MX 8M Nano application

processor.

Product data sheet Rev. 2.1 — 7 December 2020

25 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035719

10 F

22 F

0.47 H

BUCK1

Dual

Phase

Ctrl

i.MX8

Nano

PCA9450B

DVS INB13 SYS

SYS

VDD_SOC

VDD_VPU

VDD_GPU

VDD_DRAM

LX1

R_SNSP1

BUCK3

DVS INB13

LX3

R_SNSP3_CFG

10 F

22 F

0.47 H

22 F

0.47 H

BUCK1

Dual

Phase

Ctrl

i.MX8

Plus

PCA9450C

DVS INB13 SYS

SYS

VDD_SOC

VDD_VPU

VDD_GPU

VDD_DRAM

LX1

R_SNSP1

BUCK3

DVS INB13

LX3

R_SNSP3_CFG

Figure 16. BUCK1/3 configuration

7.6.2 LDO and load switch

The PCA9450 has five LDOs and one load switch. LDO1 and LDO2 are supposed to

supply SNVS core in application processor. These two LDOs feature ultra-low quiescent

current, 2 μA typical, since they are always ON when VSYS is valid.

For all LDO and the load switch, each has designated active discharge resistor

configurable through I2C.

LDO# INPUT PIN Default VOUT

[V] VOUT range [V] Step size

[mV]

Default ON/

OFF

Current rating

[mA]

LDO1 INL1 1.8 1.6-1.9, 3.0-3.3 100 ON 10

LDO2 INL1 0.85 0.8 – 1.15 50 ON 10

LDO3 INL1 1.8 0.8 - 3.3 100 ON 300

LDO4 INL1 0.9 0.8 - 3.3 100 ON [1] 200

LDO5 INL1 3.3/1.8 1.8 - 3.3 100 ON 150

SW SWIN - - - OFF 400

Table 18. LDO summary

[1] ON by default in PCA9450AA, OFF by default in PCA9450B and PCA9450C

7.7 32 kHz Crystal Oscillator Driver

The PCA9450 consists of a crystal oscillator driver with an external load capacitor

and CLK_32K_OUT buffer referenced to LDO1 voltage. When VSYS exceeds POR

threshold and internal power VINT is good, internal 32 kHz oscillator and 32.768 kHz

crystal oscillator start oscillating. Crystal oscillator typically takes few seconds to be

stabilized. PCA9450 outputs the internal 32 kHz RC oscillator initially, while internal

counter counts crystal oscillator output in tRTC_Tran after RTC_RESET_B is released. If

the counter reaches 100, then CLK_32K_OUT buffer input is switched to the external

crystal oscillator from internal 32 kHz oscillator. Clock stretch is applied during this clock

source transition to prevent unwanted glitch. If external 32.768 kHz crystal oscillator is

not populated, CLK_32K_OUT pin outputs 32 kHz clock from internal 32 kHz oscillator.

For more detailed information on selecting crystal oscillator and load capacitance, refer to

Section 9.2.2.

Product data sheet Rev. 2.1 — 7 December 2020

26 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035720

tRTC_Tran

RTC_RESET_B COUNT

VINT

LDO1

32K Osc

MUX

CLOCK

STRETCH

XTAL_IN

XTAL_OUT

CLK_32K_OUT

32.768K Xtal

Figure 17. 32 kHz Crystal oscillator driver block diagram

7.8 Load switch

PCA9450 integrates 400 mA load switch which is used to supply SD card VDD. SWIN

is connected to BUCK4 output, 3.3 V, in this application. It is enabled by SW_EN pin or

SW_EN[1:0] bits in LOADSW_CTRL register. It has soft start feature to reduce inrush

current during turn-on. This load switch has overcurrent protection and short circuit

protection by monitoring voltage difference between SWIN and SWOUT. When the switch

current exceeds overcurrent threshold (IOC) for overcurrent debounce time (tOC_DEB),

SW_OCP bit in VRFLT1_STS register is set to 1 and the fault behavior is determined by

SW_OC[1:0] configuration in LOADSW_CTRL register. When the switch current exceeds

short-circuit current threshold (ISC), SW_OCP bit in VRFLT1_STS register is set to 1 and

switch is turned off right away.

aaa-035721

80 FF

SW_OC

SW_SC

SWOUT

SWIN

3.3 V

from Buck4

SW_EN

DRIVER

I2C

Figure 18. Load switch internal block diagram

7.9 I2C level translator

PCA9450 I2C level translator is a "switch" type voltage translator, and employs two key

circuits to enable voltage translation:

Product data sheet Rev. 2.1 — 7 December 2020

27 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

1. A pass-gate transistor (N-channel) that ties the ports together.

2. An output edge-rate accelerator that detects and accelerates rising edges on the I/O

pins.

The gate bias voltage of the pass gate transistor (T3) is set at approximately one

threshold voltage above the VCC level of the low-voltage side. During a LOW-to-HIGH

transition the output one-shot accelerates the output transition by switching on the PMOS

transistors (T1, T2) bypassing the 10 kΩ pull-up resistors and increasing current drive

capability. The one-shot is activated once the input transition reaches approximately

VCCI/2; it is de-activated approximately 50 ns after the output reaches VCCO/2. During

the acceleration time the driver output resistance is between approximately 50 Ω and

70 Ω. To avoid signal contention and minimize dynamic ICC, the user should wait for

the one-shot circuit to turn off before applying a signal in the opposite direction. Pull-up

resistors are included in the device for DC current sourcing capability.

aaa-035722

GATE BIAS

ONE

SHOT

ONE

SHOT

10 kΩ

(SCLL)

(SCLH)

VCCA

(VINT)

VCCB

(SWIN)

T1 T2

10 kΩ

Figure 19. Architecture of I2C Level translator (One channel)

Each A port I/O has an internal 10 kΩ pull-up resistor to VCCA, and each B port I/O

has an internal 10 kΩ pull-up resistor to VCCB. If a smaller value of pull-up resistor is

required, an external resistor must be added parallel to the internal 10 kΩ, affecting the

VOL level. When Level translator is disabled through I2C, the internal pull up resistors

are disconnected.

PCA9450 I2C Level translator is controlled by I2C register, CONFIG2 Reg. When it is

configured to disabled, all I/Os assume the high-impedance OFF-state. The enable

time (ten) indicates the amount of time the user must allow for one one-shot circuitry to

become operational after it is enabled.

7.10 Interrupt management

The IRQ_B pin is an interface to the software-controlled system that indicates any

interrupt bit status change of INT1 register. The IRQ_B pin is pulled low when any

unmasked interrupt bit status is changed and it is released high once application

processor reads INT1 register.

The INT1 bits are latched to 1 whenever corresponding STATUS1 bits are changed

and the latch is cleared when the INT1 register is read. The INT1_MASK bits are used

to enable or disable individual interrupt bits of INT1 register. The STATUS1 register

indicates the current status and is not latched.

Product data sheet Rev. 2.1 — 7 December 2020

28 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035723

PWRONI

WDOGBI

RSVD

VR_FLT1I

VR_FLT2I

LOWVSYSI

INT

PWRONS

WDOG_BS

RSVD

VR_FLT1_S

VR_FLT2_S

LOWVSYS_S

THERM_105S THERM_105I

SW_OCP

RSVD

BUCK6_FLT

BUCK5_FLT

BUCK4_FLT

BUCK3_FLT

BUCK2_FLT

BUCK1_FLT

VRFLT1_STS

RSVD

LDO5_FLT

LDO4_FLT

LDO3_FLT

LDO2_FLT

LDO1_FLT THERM_125S THERM_125I

105°C

Die

Temp 125°C

PMIC_ON_REQ

VSYS

VSYS UVLO + Delta

WDOG_B

RSVD

BUCK6_FLT_M

BUCK5_FLT_M

BUCK4_FLT_M

BUCK3_FLT_M

BUCK2_FLT_M

BUCK1_FLT_M

VRFLT1_MASK

RSVD

LDO5_FLT_M

LDO4_FLT_M

LDO3_FLT_M

LDO2_FLT_M

LDO1_FLT_M

Deb

Figure 20. Interrupt diagram

Product data sheet Rev. 2.1 — 7 December 2020

29 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

8 Software interface

PCA9450 implements I2C-bus slave interface and it interfaces with the host system.

The host processor can issue commands, monitor status and receive response through

this bus. A detailed description of the I2C-bus specification, with applications, is given in

UM10204, “I2C-bus specification and user manual” [Ref. 4]. PCA9450 supports I2C-bus

data transfers in Standard-mode (100 kbit/s), Fast-mode (400 kbit/s) and Fast-mode plus

(1 Mbit/s).

The I2C address at Power-On Reset is shown in Table 19

7-bit Slave Address 8-bit Write Address 8-bit Read Address

0x25, 0b 010 0101 0x4A, 0b 0100 1010 0x4B, 0b 0100 1011

Table 19. PCA9450 I2C Slave Address

I2C register reset type

Type S1 : Reset condition = VSYS < VSYS_POR

Type S : Reset condition = VSYS < VSYS_UVLO

Type O : Reset condition = (VSYS < VSYS_UVLO) || (Cold Reset) || (Warm Reset) ||

(Falling edge of PMIC_ON_REQ) || (SW_RST) || (FAULT_SD)

Product data sheet Rev. 2.1 — 7 December 2020

30 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

8.1 Register map

Description

Add Name B7 B6 B5 B4 B3 B2 B1 B0 R/W Reset

Type

Reset

Value

0x00 Device_ID CHIP_ID RSVD R S 0x11

0x01 INT1 PWERONI WDOGBI RSVD VR_FLT1I VR_FLT2I LOWVSYSI THERM_

105I

THERM_

125I R/C S 0x00

0x02 INT1_MSK PWRONI_M WDOGB_M RSVD VR_FLT1_M VR_FLT2_M LOWVSYS_

THERM_

105_M

THERM_

125_M R/W S 0xFF

0x03 STATUS1 PWRONS WDOGBS RSVD VR_FLT1S VR_FLT2S LOWV

SYSS

THERM_

105S

THERM_

125S R S 0x00

0x04 STATUS2 RSVD RSVD RSVD RSVD POWER_STATUS R S1 0x00

0x05 PWRON_STAT PWRON WDOG SW_RST PMIC_RST RSVD RSVD RSVD RSVD R/C S 0x00

0x06 SW_RST SW_RST R/W O 0x00

0x07 PWR_CTRL Ton_Deb Toff_Deb Tstep Toff_step Trestart R/W S 0x4C

0x08 RESET_CTRL WDOGB_CFG PMIC_RST_CFG RSVD T_PMIC_RST_DEB R/W S 0x21

0x09 CONFIG1 LOW_VSYS VSYS_UVLO RSVD RSVD tFLT_

SD_WAIT

THERM_

SD_DIS R/W S1 0x50

0x0A CONFIG2 RSVD RSVD RSVD RSVD RSVD RSVD I2C_LT_EN R/W O 0x00

0x0C BUCK123_DVS PRESET_

EN B3_DVS_PRESET B1_DVS_PRESET B2_DVS_PRESET R/W O 0xA9

0x0D BUCK1OUT_LIMIT RSVD B1_LIMIT R/W O 0x1C

0x0E BUCK2OUT_LIMIT RSVD B2_LIMIT R/W O 0x20

0x0F BUCK3OUT_LIMIT RSVD B3_LIMIT R/W O 0x1C

0x10 BUCK1CTRL RAMP RSVD DVS_CTRL BUCK1AD FPWM B1_ENMODE R/W O 0x49

0x11 BUCK1OUT_DVS0 RSVD B1_DVS0 R/W O 0x14

0x12 BUCK1OUT_DVS1 RSVD B1_DVS1 R/W O 0x14

0x13 BUCK2CTRL RAMP RSVD DVS_CTRL BUCK2AD FPWM B2_ENMODE R/W O 0x4A

0x14 BUCK2OUT_DVS0 RSVD B2_DVS0 R/W O 0x14

Table 20. Register map

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Description

Add Name B7 B6 B5 B4 B3 B2 B1 B0 R/W Reset

Type

Reset

Value

0x15 BUCK2OUT_DVS1 RSVD B2_DVS1 R/W O 0x14

0x16 BUCK3CTRL RAMP RSVD DVS_CTRL BUCK3AD FPWM B3_ENMODE R/W O 0x49

0x17 BUCK3OUT_DVS0 RSVD B3_DVS0 R/W O 0x14

0x18 BUCK3OUT_DVS1 RSVD B3_DVS1 R/W O 0x14

0x19 BUCK4CTRL RSVD RSVD RSVD RSVD BUCK4AD FPWM B4_ENMODE R/W O 0x09

0x1A BUCK4OUT RSVD B4_OUT R/W O 0x6C

0x1B BUCK5CTRL RSVD RSVD RSVD RSVD BUCK5AD FPWM B5_ENMODE R/W O 0x09

0x1C BUCK5OUT RSVD B5_OUT R/W O 0x30

0x1D BUCK6CTRL RSVD RSVD RSVD RSVD BUCK6AD FPWM B6_ENMODE R/W O 0x09

0x1E BUCK6OUT RSVD B6_OUT R/W O 0x14

0x20 LDO_AD_CTRL LDO1_AD LDO2_AD LDO3_AD LDO4_AD LDO5_AD RSVD RSVD RSVD R/W O 0xF8

0x21 LDO1CTRL ENMODE RSVD RSVD RSVD L1_OUT R/W O 0xC2

0x22 LDO2CTRL ENMODE RSVD RSVD RSVD L2_OUT R/W O 0xC1

0x23 LDO3CTRL ENMODE RSVD L3_OUT R/W O 0x4A

0x24 LDO4CTRL ENMODE RSVD L4_OUT R/W O 0x41

0x25 LDO5CTRL_L ENMODE RSVD RSVD L5_OUT_L R/W O 0x4F

0x26 LDO5CTRL_H RSVD RSVD RSVD RSVD L5_OUT_H R/W O 0x00

0x27 RSVD RSVD R/W O 0x00

0x28 RSVD RSVD R/W O 0x00

0x29 RSVD RSVD R/W O 0x00

0x2A LOADSW_CTRL SW_AD RSVD RSVD SW_SC SW_OC SWEN R/W O 0x85

0x2B VRFLT1_STS SW_OCP RSVD BUCK6_

FLT BUCK5_FLT BUCK4_FLT BUCK3_

FLT

BUCK2_

FLT BUCK1_FLT R/W/C S 0x00

0x2C VRFLT2_STS RSVD RSVD RSVD LDO5_FLT LDO4_FLT LDO3_FLT LDO2_FLT LDO1_FLT R/W/C S 0x00

Table 20. Register map...continued

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Description

Add Name B7 B6 B5 B4 B3 B2 B1 B0 R/W Reset

Type

Reset

Value

0x2D VRFLT1_MASK RSVD RSVD BUCK6_

FLT_M

BUCK5_

FLT_M

BUCK4_

FLT_M

BUCK3_

FLT_M

BUCK2_

FLT_M

BUCK1_

FLT_M R/W S 0x3F

0x2E VRFLT2_MASK RSVD RSVD RSVD LDO5_

FLT_M

LDO4_

FLT_M

LDO3_

FLT_M

LDO2_

FLT_M

LDO1_

FLT_M R/W S 0x1F

Table 20. Register map...continued

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

8.2 Register details

8.2.1 0x00 Device_ID

The device identification code stores a unique identifier for each version and/or revision

of a PCA9450, so that the connected processor recognizes it automatically.

0x00 – Device_ID Reset Type S

Bit Name Type Reset Description

7:4 CHIP_ID R 0001

Chip ID

0001b = PCA9450AA

0011b = PCA9450B, PCA9450C

3:0 RSVD R 0001 Reserved

Table 21. 0x00 Device_ID

8.2.2 0x01 INT1

Interrupt source register. Either of unmasked register bits is set to 1, IRQ_B pin is pulled

low. This register is Read and Clear.

0x01 – INT1 Reset Type S

Bit Name Type Reset Description

7 PWRONI R/C 0

PWRON interrupt bit

0b = PWRONS bit has not been changed

1b = PWRONS bit has been changed

6 WDOGBI R/C 0

WDOGB interrupt bit

0b = WDOG_BS bit has not been changed

1b = WDOG_BS bit has been changed

5 RSVD R/C 0 Reserved

4 VR_FLT1I R/C 0

Voltage regulator Group1 Fault interrupt

0b = VR_FLT1S bit has not been changed

1b = VR_FLT1S bit has been changed

3 VR_FLT2I R/C 0

Voltage regulator Group2 Fault interrupt

0b = VR_FLT2S bit has not been changed

1b = VR_FLT2S bit has been changed

2 LOWVSYSI R/C 0

Low-SYS Voltage interrupt bit

0b = LOWVSYSS bit has not been changed

1b = LOWVSYSS bit has been changed

1 THERM_105I R/C 0

Die temperature 105 °C interrupt

0b = THERM_105S bit has not been changed

1b = THERM_105S bit has been changed

0 THERM_125I R/C 0

Die temperature 125 °C interrupt

0b = THERM_125S bit has not been changed

1b = THERM_125S bit has been changed

Table 22. 0x01 INT1

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

8.2.3 0x02 INT1_MSK

The INT1_MSK register enables the masking (disabling) of the different interrupt signals

of register INT1. When unmasked, interrupt events trigger the IRQB pin to be pulled low

when the matching flag bit in the register INT1 is set.

0x02 – INT1_MSK Reset Type S

Bit Name Type Reset Description

7 PWRON_M R/W 1

PWRONI interrupt mask bit

0b = Enable PWRONI interrupt

1b = Mask PWRONI interrupt

6 WDOGB_M R/W 1

WDOGBI interrupt mask bit

0b = Enable WDOGBI interrupt

1b = Mask WDOGBI interrupt

5 RSVD R/W 1 Reserved

4 VR_FLT1_M R/W 1

VR_FLT1I interrupt mask bit

0b = Enable VR_FLT1I interrupt

1b = Mask VR_FLT1I interrupt

3 VR_FLT2_M R/W 1

VR_FLT2I interrupt mask bit

0b = Enable VR_FLT2I interrupt

1b = Mask VR_FLT2I interrupt

2 LOWVSYS_M R/W 1

LOWVINI interrupt mask bit

0b = Enable LOWVINI interrupt

1b = Mask LOWVINI interrupt

1 THERM_105_M R/W 1

THERM_105 interrupt mask bit

0b = Enable THERM_105 interrupt

1b = Mask THERM_105 interrupt

0 THERM_125_M R/W 1

THERM_125 interrupt mask bit

0b = Enable THERM_125 interrupt

1b = Mask THERM_125 interrupt

Table 23. 0x02 INT1_MSK

8.2.4 0x03 STATUS1

STATUS1 register show current status. Any status bit change set corresponding interrupt

bit to 1.

0x03 – STATUS1 Reset Type S

Bit Name Type Reset Description

7 PWRONS R 0

PMIC_ON_REQ pin status after debounce time

0b = PMIC_ON_REQ pin is low

1b = PMIC_ON_REQ pin is high

6 WDOG_BS R 0

WDOG_B pin status

0b = WDOG_B pin is low

1b = WDOG_B pin is high

5 RSVD R 0 Reserved

Table 24. 0x03 STATUS1

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x03 – STATUS1 Reset Type S

Bit Name Type Reset Description

4 VR_FLT1S R 0

Voltage Regulator Fault status, See 0x2B Register.

0b = All voltage regulators are OK

1b = Either of voltage regulators is in Fault state

3 VR_FLT2S R 0

Voltage Regulator POK status, See 0x2C Registers.

0b = All voltage regulators are OK

1b = Either of voltage regulators is in Fault state

2 LOWVSYSS R 0

VSYS low voltage status

0b = VSYS > Low VSYS threshold

1b = VSYS ≤ Low VSYS threshold

1 THERM_105S R 0

Die temperature 105 °C status

0b = Die temperature is below 105 °C

1b = Die temperature is above 105 °C

0 THERM_125S R 0

Die temperature 125 °C status

0b = Die temperature is below 125 °C

1b = Die temperature is above 125 °C

Table 24. 0x03 STATUS1...continued

8.2.5 0x04 STATUS2

STATUS2 register shows current PCA9450 power status.

0x04 – STATUS2 Reset Type S1

Bit Name Type Reset Description

7:4 RSVD R 0000 Reserved

3:0 POWER_STATUS R 0000

Current PCA9450 power status

0000b = OFF

0001b = READY

0010b = SNVS

0011b = PWRUP

0100b = RUN

0101b = STANDBY

0110b = PWRDN

0111b = WARM RESET

1000b = COLD RESET

1001b = FAULT Shutdown

1010b – 1111b = Reserved

Table 25. 0x04 STATUS2

8.2.6 0x05 PWRON_STAT

Power ON source register. It is latched to 1 until the bit is read back.

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x05 – PWRON_STAT Reset Type S

Bit Name Type Reset Description

7 PWRON R/C 0 1b = Power ON triggered by PMIC_ON_REQ. This bit will be set right

after completing power up sequence.

6 WDOG R/C 0 1b = This bit is set after cold reset by WDOGB pin

5 SW_RST R/C 0 1b = This bit is set after cold reset by SW_RST bit

4 PMIC_RST R/C 0 1b = This bit is set after cold reset by PMIC_RST_B

3 RSVD R/C 0 Reserved

2 RSVD R/C 0 Reserved

1 RSVD R/C 0 Reserved

0 RSVD R/C 0 Reserved

Table 26. 0x05 PWRON_STAT

8.2.7 0x06 SW_RST

Software reset register through I2C.

0x06 – SW_RST Reset Type O

Bit Name Type Reset Description

7:0 SW_RST R/W 0x00

Software reset register. This register is read back to “0x00” right after

writing the value.

0x00 = No action

0x05 = Reset all registers to default value

0x14 = Cold reset (Power recycle all regulators except LDO1, LDO2

and CLK_32K_OUT)

0x35 = Warm Reset (Toggle POR_B for 20 ms)

0x64 = Cold reset (Power recycle all regulators)

Others = No action

Table 27. 0x06 SW_RST

8.2.8 0x07 PWR_CTRL

Debounce timer configuration register

0x07 – PWR_CTRL Reset Type S

Bit Name Type Reset Description

7:6 Ton_Deb R/W 01

Debounce time for PMIC_ON_REQ high.

00b = 120 μs

01b = 20 ms

10b = 100 ms

11b = 750 ms

5 Toff_Deb R/W 0

Debounce time for PMIC_ON_REQ is asserted low

0b = 120 μs

1b = 2 ms

Table 28. 0x07 PWR_CTRL

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x07 – PWR_CTRL Reset Type S

Bit Name Type Reset Description

4:3 Tstep R/W 01

Time step configuration during power on sequence

00b = 1 ms

01b = 2 ms

10b = 4 ms

11b = 8 ms

2:1 Toff_step R/W 10

Time step configuration during power down sequence

00b = 2 ms

01b = 4 ms

10b = 8 ms

11b = 16 ms

0 Trestart R/W 0

Time to stay regulators off during Cold reset

0b = 250 ms

1b = 500 ms

Table 28. 0x07 PWR_CTRL...continued

8.2.9 0x08 RESET_CTRL

Reset behavior configuration register through WDOG_B and PMIC_RST_B pin.

0x08 – RESET_CTRL Reset Type S

Bit Name Type Reset Description

7:6 WDOG_B_CFG R/W 00

When WDOG_B is asserted to low, PMIC reset behavior

00b = WDOG_B reset is disabled

01b = Warm Reset, POR_B pin is asserted low for 20 ms

10b = Cold Reset, All voltage regulators are recycled except LDO1/

LDO2

11b = Cold Reset, All voltage regulators are recycled

5:4 PMIC_RST_CFG R/W 10

When PMIC_RST_B is asserted to low, PMIC reset behavior

00b = PMIC_RST_B reset is disabled

01b = Warm Reset, POR_B pin is asserted low for 20 ms

10b = Cold Reset, All voltage regulators are recycled except

LDO1/LDO2

11b = Cold Reset, All voltage regulators are recycled

3 RSVD R/W 0 Reserved

2:0 T_PMIC_RST_DEB R/W 001

PMIC_RST_B debounce time

000b = 10 ms

001b = 50 ms

010b = 100 ms

011b = 500 ms

100b = 1 sec

101b = 2 sec

110b = 4 sec

111b = 8 sec

Table 29. 0x08 RESET_CTRL

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

8.2.10 0x09 CONFIG1

VSYS_UVLO and LOW VSYS configuration register

0x09 – CONFIG1 Reset Type S1

Bit Name Type Reset Description

7:6 LOW_VSYS R/W 01

Low VSYS threshold above VSYS_UVLO

00b = 100 mV

01b = 200 mV

10b = 300 mV

11b = 400 mV

5:4 VSYS_UVLO R/W 01

VSYS UVLO Rising threshold

00b = 2.85 V

01b = 3.0 V

10b = 3.15 V

11b = 3.3 V

3:2 RSVD R/W 00 Reserved

1 tFLT_SD_WAIT R/W 0

Wait time for AP action when regulator fault occurs

0b = 100 ms

1b = 120 μs

0 THERM_SD_DIS R/W 0

Thermal shutdown disable bit

0b = Enable Thermal shutdown

1b = Disable Thermal shutdown

Table 30. 0x09 CONFIG1

8.2.11 0x0A CONFIG2

I2C Level translator control register

0x0A – CONFIG2 Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:4 RSVD R/W 000 Reserved

3:2 RSVD R/W 00 Reserved

1:0 I2C_LT_EN R/W 00

I2C level translator enable

00b = Forced Disable

01b = Enable only when STANDBY and RUN mode

10b = Enable only when RUN mode

11b = Forced enable

Table 31. 0x0A CONFIG2

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

8.2.12 0x0C BUCK123_DVS

BUCK1, BUCK2, BUCK3 DVS control register with preset value

0x0C – BUCK123_DVS Reset Type O

Bit Name Type Reset Description

7 PRESET_EN R/W 1

BUCK123 output voltage selection

0b = BUCK voltage is determined by each BUCKxOUT_DVS0 or

BUCKxOUT_DVS1.

1b = BUCK voltage is determined by Bx_DVS_PRESET bits.

6:5 B3_DVS_PRESET R/W 01

BUCK3 (VPU/GPU) Preset voltage option, only for PCA9450AA.

00b = 0.8 V

01b = 0.85 V

10b = 0.9 V

11b = 0.95 V

4:3 B1_DVS_PRESET R/W 01

BUCK1 (SOC) Preset voltage option

00b = 0.8 V

01b = 0.85 V

10b = 0.9 V

11b = 0.95 V

2:0 B2_DVS_PRESET R/W 001

BUCK2 (ARM) Preset voltage option

000b = 0.8 V

001b = 0.85 V

010b = 0.9 V

011b = 0.95 V

100b – 111b = 1.0 V

Table 32. 0x0C BUCK123_DVS

8.2.13 0x0D BUCK1OUT_LIMIT

BUCK1 output voltage limit register

0x0D – BUCK1OUT_LIMIT Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B1_LIMIT R/W 001

1100

BUCK1 output voltage limit

Programmable from 0.60 V to 2.1875 V in 12.5 mV step

Default = 0.95 V

Table 33. 0x0D BUCK1OUT_LIMIT

8.2.14 0x0E BUCK2OUT_LIMIT

BUCK2 output voltage limit register

0x0E – BUCK2OUT_LIMIT Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

Table 34. 0x0E BUCK2OUT_LIMIT

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x0E – BUCK2OUT_LIMIT Reset Type O

Bit Name Type Reset Description

6:0 B2_LIMIT R/W 010

0000

BUCK2 output voltage limit

Programmable from 0.60 V to 2.1875 V in 12.5 mV step

Default = 1.00 V

Table 34. 0x0E BUCK2OUT_LIMIT...continued

8.2.15 0x0F BUCK3OUT_LIMIT

BUCK3 output voltage limit register. This register is only for PCA9450AA

0x0F – BUCK3OUT_LIMIT Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B3_LIMIT R/W 001

1100

BUCK3 output voltage limit

Programmable from 0.60 V to 2.1875 V in 12.5 mV step

Default = 0.95 V

Table 35. 0x0F BUCK3OUT_LIMIT

8.2.16 0x10 BUCK1CTRL

BUCK1 control register for Ramp, DVS control, Active discharge, FPWM and Enable.

0x10 – BUCK1CTRL Reset Type O

Bit Name Type Reset Description

7:6 RAMP R/W 01

BUCK1 DVS speed

00b = 25 mV / 1 μs

01b = 25 mV / 2 μs

10b = 25 mV / 4 μs

11b = 25 mV / 8 μs

5 RSVD R/W 0 Reserved

4 DVS_CTRL R/W 0

DVS Control configuration

0b = BUCK voltage is determined by BUCK1VOUT_DVS0 register

regardless of PMIC_STBY_REQ

1b = DVS control through PMIC_STBY_REQ

3 BUCK1AD R/W 1

BUCK1 Active discharge

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

2 FPWM R/W 0

Forced PWM mode

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

1:0 B1_ENMODE R/W 01

BUCK1 enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

Table 36. 0x10 BUCK1CTRL

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

8.2.17 0x11 BUCK1OUT_DVS0

BUCK1 DVS output voltage at PMIC_STBY_REQ = L

0x11 – BUCK1OUT_DVS0 Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B1_DVS0 R/W 001

0100

BUCK1 DVS0 Output voltage

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 12

Default = 0.85 V

Table 37. 0x11 BUCK1OUT_DVS0

8.2.18 0x12 BUCK1OUT_DVS1

BUCK1 DVS output voltage at PMIC_STBY_REQ = H

0x12 – BUCK1OUT_DVS1 Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B1_DVS1 R/W 001

0100

BUCK1 DVS1 Output voltage

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 12

Default = 0.85 V

Table 38. 0x12 BUCK1OUT_DVS1

8.2.19 0x13 BUCK2CTRL

BUCK2 control register for Ramp, DVS control, Active discharge, FPWM and Enable.

0x13 – BUCK2CTRL Reset Type O

Bit Name Type Reset Description

7:6 RAMP R/W 01

BUCK2 DVS speed

00b = 25 mV / 1 μs

01b = 25 mV / 2 μs

10b = 25 mV / 4 μs

11b = 25 mV / 8 μs

5 RSVD R/W 0 Reserved

4 DVS_CTRL R/W 0

DVS Control configuration

0b = BUCK voltage is determined by BUCK2VOUT_DVS0 register

regardless of PMIC_STBY_REQ

1b = DVS control through PMIC_STBY_REQ

3 BUCK2AD R/W 1

BUCK2 Active discharge

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

2 FPWM R/W 0

Forced PWM mode

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

Table 39. 0x13 BUCK2CTRL

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x13 – BUCK2CTRL Reset Type O

Bit Name Type Reset Description

1:0 B2_ENMODE R/W 10

BUCK2 enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

Table 39. 0x13 BUCK2CTRL...continued

8.2.20 0x14 BUCK2OUT_DVS0

BUCK2 DVS output voltage at PMIC_STBY_REQ = L

0x14 – BUCK2OUT_DVS0 Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B2_DVS0 R/W 001

0100

BUCK2 DVS0 Output voltage

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45

Default = 0.85 V

Table 40. 0x14 BUCK2OUT_DVS0

8.2.21 0x15 BUCK2OUT_DVS1

BUCK2 DVS output voltage at PMIC_STBY_REQ = H

0x15 – BUCK2OUT_DVS1 Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B2_DVS1 R/W 001

0100

BUCK2 DVS1 Output voltage

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45

Default = 0.85 V

Table 41. 0x15 BUCK2OUT_DVS1

8.2.22 0x16 BUCK3CTRL

BUCK3 control register for Ramp, DVS control, Active discharge, FPWM and Enable.

The registers related to BUCK3 are only for PCA9450AA.

0x16 – BUCK3CTRL Reset Type O

Bit Name Type Reset Description

7:6 RAMP R/W 01

BUCK3 DVS speed

00b = 25 mV / 1 μs

01b = 25 mV / 2 μs

10b = 25 mV / 4 μs

11b = 25 mV / 8 μs

5 RSVD R/W 0 Reserved

Table 42. 0x16 BUCK3CTRL

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x16 – BUCK3CTRL Reset Type O

Bit Name Type Reset Description

4 DVS_CTRL R/W 0

DVS Control configuration

0b = BUCK voltage is determined by BUCK3VOUT_DVS0 register

regardless of PMIC_STBY_REQ

1b = DVS control through PMIC_STBY_REQ

3 BUCK3AD R/W 1

BUCK3 Active discharge

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

2 FPWM R/W 0

Forced PWM mode

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

1:0 B3_ENMODE R/W 01

BUCK3 enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

Table 42. 0x16 BUCK3CTRL...continued

8.2.23 0x17 BUCK3OUT_DVS0

BUCK3 DVS output voltage at PMIC_STBY_REQ = L

0x17 – BUCK3OUT_DVS0 Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B3_DVS0 R/W 001

0100

BUCK3 DVS0 Output voltage

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45

Default = 0.85 V

Table 43. 0x17 BUCK3OUT_DVS0

8.2.24 0x18 BUCK3OUT_DVS1

BUCK3 DVS output voltage a PMIC_STBY_REQ = H

0x18 – BUCK3OUT_DVS1 Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B3_DVS1 R/W 001

0100

BUCK3 DVS1 Output voltage

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45

Default = 0.85 V

Table 44. 0x18 BUCK3OUT_DVS1

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Code Voltage Code Voltage Code Voltage Code Voltage

0x00 0.6000 V 0x20 1.0000 V 0x40 1.4000 V 0x60 1.8000 V

0x01 0.6125 V 0x21 1.0125 V 0x41 1.4125 V 0x61 1.8125 V

0x02 0.6250 V 0x22 1.0250 V 0x42 1.4250 V 0x62 1.8250 V

0x03 0.6375 V 0x23 1.0375 V 0x43 1.4375 V 0x63 1.8375 V

0x04 0.6500 V 0x24 1.0500 V 0x44 1.4500 V 0x64 1.8500 V

0x05 0.6625 V 0x25 1.0625 V 0x45 1.4625 V 0x65 1.8625 V

0x06 0.6750 V 0x26 1.0750 V 0x46 1.4750 V 0x66 1.8750 V

0x07 0.6875 V 0x27 1.0875 V 0x47 1.4875 V 0x67 1.8875 V

0x08 0.7000 V 0x28 1.1000 V 0x48 1.5000 V 0x68 1.9000 V

0x09 0.7125 V 0x29 1.1125 V 0x49 1.5125 V 0x69 1.9125 V

0x0A 0.7250 V 0x2A 1.1250 V 0x4A 1.5250 V 0x6A 1.9250 V

0x0B 0.7375 V 0x2B 1.1375 V 0x4B 1.5375 V 0x6B 1.9375 V

0x0C 0.7500 V 0x2C 1.1500 V 0x4C 1.5500 V 0x6C 1.9500 V

0x0D 0.7625 V 0x2D 1.1625 V 0x4D 1.5625 V 0x6D 1.9625 V

0x0E 0.7750 V 0x2E 1.1750 V 0x4E 1.5750 V 0x6E 1.9750 V

0x0F 0.7875 V 0x2F 1.1875 V 0x4F 1.5875 V 0x6F 1.9875 V

0x10 0.8000 V 0x30 1.2000 V 0x50 1.6000 V 0x70 2.0000 V

0x11 0.8125 V 0x31 1.2125 V 0x51 1.6125 V 0x71 2.0125 V

0x12 0.8250 V 0x32 1.2250 V 0x52 1.6250 V 0x72 2.0250 V

0x13 0.8375 V 0x33 1.2375 V 0x53 1.6375 V 0x73 2.0375 V

0x14 0.8500 V 0x34 1.2500 V 0x54 1.6500 V 0x74 2.0500 V

0x15 0.8625 V 0x35 1.2625 V 0x55 1.6625 V 0x75 2.0625 V

0x16 0.8750 V 0x36 1.2750 V 0x56 1.6750 V 0x76 2.0750 V

0x17 0.8875 V 0x37 1.2875 V 0x57 1.6875 V 0x77 2.0875 V

0x18 0.9000 V 0x38 1.3000 V 0x58 1.7000 V 0x78 2.1000 V

0x19 0.9125 V 0x39 1.3125 V 0x59 1.7125 V 0x79 2.1125 V

0x1A 0.9250 V 0x3A 1.3250 V 0x5A 1.7250 V 0x7A 2.1250 V

0x1B 0.9375 V 0x3B 1.3375 V 0x5B 1.7375 V 0x7B 2.1375 V

0x1C 0.9500 V 0x3C 1.3500 V 0x5C 1.7500 V 0x7C 2.1500 V

0x1D 0.9625 V 0x3D 1.3625 V 0x5D 1.7625 V 0x7D 2.1625 V

0x1E 0.9750 V 0x3E 1.3750 V 0x5E 1.7750 V 0x7E 2.1750 V

0x1F 0.9875 V 0x3F 1.3875 V 0x5F 1.7875 V 0x7F 2.1875 V

Table 45. BUCK1, BUCK2, BUCK3 Output voltage table

8.2.25 0x19 BUCK4CTRL

BUCK4 control register for Active discharge, FPWM and Enable.

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x19 – BUCK4CTRL Reset Type O

Bit Name Type Reset Description

7:4 RSVD R/W 0000 Reserved

3 BUCK4AD R/W 1

BUCK4 Active discharge

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

2 FPWM R/W 0

Forced PWM mode

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

1:0 B4_ENMODE R/W 01

BUCK4 enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

Table 46. 0x19 BUCK4CTRL

8.2.26 0x1A BUCK4OUT

BUCK4 output voltage configuration register

0x1A – BUCK4OUT Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B4_OUT R/W 110

1100

BUCK4 Output voltage

Programmable from 0.60 V to 3.40 V in 25 mV step. Table 52

Default = 3.3 V

Table 47. 0x1A BUCK4OUT

8.2.27 0x1B BUCK5CTRL

BUCK5 control register for Active discharge, FPWM and Enable.

0x1B – BUCK5CTRL Reset Type O

Bit Name Type Reset Description

7:4 RSVD R/W 0000 Reserved

3 BUCK5AD R/W 1

BUCK5 Active discharge

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

2 FPWM R/W 0

Forced PWM mode

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

1:0 B5_ENMODE R/W 01

BUCK5 enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

Table 48. 0x1B BUCK5CTRL

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

8.2.28 0x1C BUCK5OUT

BUCK5 output voltage configuration register

0x1C – BUCK5OUT Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B5_OUT R/W 011

0000

BUCK5 Output voltage

Programmable from 0.60 V to 3.40 V in 25 mV step. Table 52

Default = 1.8 V

Table 49. 0x1C BUCK5OUT

8.2.29 0x1D BUCK6CTRL

BUCK6 control register for Active discharge, FPWM and Enable.

0x1D – BUCK6OUT Reset Type O

Bit Name Type Reset Description

7:4 RSVD R/W 0000 Reserved

3 BUCK6AD R/W 1

BUCK6 Active discharge

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

2 FPWM R/W 0

Forced PWM mode

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

1:0 B6_ENMODE R/W 01

BUCK6 enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

Table 50. 0x1D BUCK6CTRL

8.2.30 0x1E BUCK6OUT

BUCK6 output voltage configuration register

0x1E – BUCK6CTRL Reset Type O

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6:0 B6_OUT R/W 001

0100

BUCK6 Output voltage

Programmable from 0.60 V to 3.40 V in 25 mV step. Table 52

Default = 1.1 V

Table 51. 0x1E BUCK6OUT

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Code Voltage Code Voltage Code Voltage Code Voltage

0x00 0.600 V 0x20 1.400 V 0x40 2.200 V 0x60 3.000 V

0x01 0.625 V 0x21 1.425 V 0x41 2.225 V 0x61 3.025 V

0x02 0.650 V 0x22 1.450 V 0x42 2.250 V 0x62 3.050 V

0x03 0.675 V 0x23 1.475 V 0x43 2.275 V 0x63 3.075 V

0x04 0.700 V 0x24 1.500 V 0x44 2.300 V 0x64 3.100 V

0x05 0.725 V 0x25 1.525 V 0x45 2.325 V 0x65 3.125 V

0x06 0.750 V 0x26 1.550 V 0x46 2.350 V 0x66 3.150 V

0x07 0.775 V 0x27 1.575 V 0x47 2.375 V 0x67 3.175 V

0x08 0.800 V 0x28 1.600 V 0x48 2.400 V 0x68 3.200 V

0x09 0.825 V 0x29 1.625 V 0x49 2.425 V 0x69 3.225 V

0x0A 0.850 V 0x2A 1.650 V 0x4A 2.450 V 0x6A 3.250 V

0x0B 0.875 V 0x2B 1.675 V 0x4B 2.475 V 0x6B 3.275 V

0x0C 0.900 V 0x2C 1.700 V 0x4C 2.500 V 0x6C 3.300 V

0x0D 0.925 V 0x2D 1.725 V 0x4D 2.525 V 0x6D 3.325 V

0x0E 0.950 V 0x2E 1.750 V 0x4E 2.550 V 0x6E 3.350 V

0x0F 0.975 V 0x2F 1.775 V 0x4F 2.575 V 0x6F 3.375 V

0x10 1.000 V 0x30 1.800 V 0x50 2.600 V 0x70 3.400 V

0x11 1.025 V 0x31 1.825 V 0x51 2.625 V 0x71 3.400 V

0x12 1.050 V 0x32 1.850 V 0x52 2.650 V 0x72 3.400 V

0x13 1.075 V 0x33 1.875 V 0x53 2.675 V 0x73 3.400 V

0x14 1.100 V 0x34 1.900 V 0x54 2.700 V 0x74 3.400 V

0x15 1.125 V 0x35 1.925 V 0x55 2.725 V 0x75 3.400 V

0x16 1.150 V 0x36 1.950 V 0x56 2.750 V 0x76 3.400 V

0x17 1.175 V 0x37 1.975 V 0x57 2.775 V 0x77 3.400 V

0x18 1.200 V 0x38 2.000 V 0x58 2.800 V 0x78 3.400 V

0x19 1.225 V 0x39 2.025 V 0x59 2.825 V 0x79 3.400 V

0x1A 1.250 V 0x3A 2.050 V 0x5A 2.850 V 0x7A 3.400 V

0x1B 1.275 V 0x3B 2.075 V 0x5B 2.875 V 0x7B 3.400 V

0x1C 1.300 V 0x3C 2.100 V 0x5C 2.900 V 0x7C 3.400 V

0x1D 1.325 V 0x3D 2.125 V 0x5D 2.925 V 0x7D 3.400 V

0x1E 1.350 V 0x3E 2.150 V 0x5E 2.950 V 0x7E 3.400 V

0x1F 1.375 V 0x3F 2.175 V 0x5F 2.975 V 0x7F 3.400 V

Table 52. BUCK4, BUCK5, BUCK6 Output voltage table

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

8.2.31 0x20 LDO_AD_CTRL

LDO active discharge resistor configuration register

0x20 – LDO_AD_CTRL Reset Type O

Bit Name Type Reset Description

7 LDO1_AD R/W 1

LDO1 Active discharge enable

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

6 LDO2_AD R/W 1

LDO2 Active discharge enable

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

5 LDO3_AD R/W 1

LDO3 Active discharge enable

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

4 LDO4_AD R/W 1

LDO4 Active discharge enable

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

3 LDO5_AD R/W 1

LDO5 Active discharge enable

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

2 RSVD R/W 0 Reserved

1 RSVD R/W 0 Reserved

0 RSVD R/W 0 Reserved

Table 53. 0x20 LDO_AD_CTRL

8.2.32 0x21 LDO1CTRL

LDO1 control register for enable and voltage

0x21 – LDO1CTRL Reset Type O

Bit Name Type Reset Description

7:6 ENMODE R/W 11

LDO1 Enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

* When LDO1 is turned off, PCA9450/A transitions to READY mode

5:3 RSVD R/W 000 Reserved

Table 54. 0x21 LDO1CTRL

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x21 – LDO1CTRL Reset Type O

Bit Name Type Reset Description

2:0 L1_OUT R/W 010

LDO1 output voltage

Programmable from 1.6 V – 1.9 V, 3.0 V – 3.3 V in 100 mV step

000b = 1.6 V

001b = 1.7 V

010b = 1.8 V

011b = 1.9 V

100b = 3.0 V

101b = 3.1 V

110b = 3.2 V

111b = 3.3 V

Table 54. 0x21 LDO1CTRL...continued

8.2.33 0x22 LDO2CTRL

LDO2 control register for enable and voltage

0x22 – LDO2CTRL Reset Type O

Bit Name Type Reset Description

7:6 ENMODE R/W 11

LDO2 Enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

* When LDO2 is turned off, PCA9450/A transitions to READY mode

5:3 RSVD R/W 000 Reserved

2:0 L2_OUT R/W 001

LDO2 output voltage

Programmable from 0.8 V to 1.15 V in 50 mV step

000b = 0.8 V

001b = 0.85 V

010b = 0.9 V

011b = 0.95 V

100b = 1.0 V

101b = 1.05 V

110b = 1.1 V

111b = 1.15 V

Table 55. 0x22 LDO2CTRL

8.2.34 0x23 LDO3CTRL

LDO3 control register for enable and voltage

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x23 – LDO3CTRL Reset Type O

Bit Name Type Reset Description

7:6 ENMODE R/W 01

LDO3 Enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

5 RSVD R/W 0 Reserved

4:0 L3_OUT R/W 0 1010 LDO3 output voltage

Programmable from 0.8 V to 3.3 V in 100 mV step, see Table 57

Table 56. 0x23 LDO3CTRL

0x00 : 0.80 V 0x8 : 1.60 V 0x10 : 2.40 V 0x18 : 3.20 V

0x01 : 0.90 V 0x9 : 1.70 V 0x11 : 2.50 V 0x19 : 3.30 V

0x02 : 1.00 V 0xA : 1.80 V 0x12 : 2.60 V 0x1A : 3.30 V

0x03 : 1.10 V 0xB : 1.90 V 0x13 : 2.70 V 0x1B : 3.30 V

0x04 : 1.20 V 0xC : 2.00 V 0x14 : 2.80 V 0x1C : 3.30 V

0x05 : 1.30 V 0xD : 2.10 V 0x15 : 2.90 V 0x1D : 3.30 V

0x06 : 1.40 V 0xE : 2.20 V 0x16 : 3.00 V 0x1E : 3.30 V

0x07 : 1.50 V 0xF : 2.30 V 0x17 : 3.10 V 0x1F : 3.30 V

Table 57. LDO3 output voltage

8.2.35 0x24 LDO4CTRL

LDO4 control register for enable and voltage

0x24 – LDO4CTRL Reset Type O

Bit Name Type Reset Description

7:6 ENMODE R/W 01

LDO4 Enable mode

00b = OFF (PCA9450B/PCA9450C)

01b = ON by PMIC_ON_REQ = H (PCA9450AA)

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

5 RSVD R/W 0 Reserved

4:0 L4_OUT R/W 0 0001 LDO4 output voltage

Programmable from 0.8 V to 3.3 V in 100 mV step, see Table 59

Table 58. 0x24 LDO4CTRL

0x00 : 0.80 V 0x8 : 1.60 V 0x10 : 2.40 V 0x18 : 3.20 V

0x01 : 0.90 V 0x9 : 1.70 V 0x11 : 2.50 V 0x19 : 3.30 V

0x02 : 1.00 V 0xA : 1.80 V 0x12 : 2.60 V 0x1A : 3.30 V

Table 59. LDO4 output voltage

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x03 : 1.10 V 0xB : 1.90 V 0x13 : 2.70 V 0x1B : 3.30 V

0x04 : 1.20 V 0xC : 2.00 V 0x14 : 2.80 V 0x1C : 3.30 V

0x05 : 1.30 V 0xD : 2.10 V 0x15 : 2.90 V 0x1D : 3.30 V

0x06 : 1.40 V 0xE : 2.20 V 0x16 : 3.00 V 0x1E : 3.30 V

0x07 : 1.50 V 0xF : 2.30 V 0x17 : 3.10 V 0x1F : 3.30 V

Table 59. LDO4 output voltage...continued

8.2.36 0x25 LDO5CTRL_L

LDO5 control register for enable and voltage when SD_VSEL is low

0x25 – LDO5CTRL_L Reset Type O

Bit Name Type Reset Description

7:6 ENMODE R/W 01

LDO5 Enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

5:4 RSVD R/W 00 Reserved

3:0 L5_OUT_L R/W 1111 LDO5 output voltage when SD_VSEL = Low

Programmable from 1.8 V to 3.3 V in 100 mV step, see Table 61

Table 60. 0x25 LDO5CTRL_L

0x00 : 1.80 V 0x4 : 2.20 V 0x8 : 2.60 V 0xC : 3.00 V

0x01 : 1.90 V 0x5 : 2.30 V 0x9 : 2.70 V 0xD : 3.10 V

0x02 : 2.00 V 0x6 : 2.40 V 0xA : 2.80 V 0xE : 3.20 V

0x03 : 2.10 V 0x7 : 2.50 V 0xB : 2.90 V 0xF : 3.30 V

Table 61. LDO5 output voltage when SD_VSEL = Low

8.2.37 0x26 LDO5CTRL_H

LDO5 control register for enable and voltage when SD_VSEL is High

0x26 – LDO5CTRL_H Reset Type O

Bit Name Type Reset Description

7:6 RSVD R/W 00 Reserved

5:4 RSVD R/W 00 Reserved

3:0 L5_OUT_H R/W 0000 LDO5 output voltage when SD_VSEL = High

Programmable from 1.8 V to 3.3 V in 100 mV step, see Table 63

Table 62. 0x26 LDO5CTRL_H

0x00 : 1.80 V 0x4 : 2.20 V 0x8 : 2.60 V 0xC : 3.00 V

Table 63. LDO5 output voltage when SD_VSEL = High

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x01 : 1.90 V 0x5 : 2.30 V 0x9 : 2.70 V 0xD : 3.10 V

0x02 : 2.00 V 0x6 : 2.40 V 0xA : 2.80 V 0xE : 3.20 V

0x03 : 2.10 V 0x7 : 2.50 V 0xB : 2.90 V 0xF : 3.30 V

Table 63. LDO5 output voltage when SD_VSEL = High...continued

8.2.38 0x2A LOADSW_CTRL

Load switch control register for active discharge, short/over current and enable

0x2A – LOADSW_CTRL Reset Type O

Bit Name Type Reset Description

7 SW_AD R/W 1

Load switch active discharge

0b = Always disable active discharge resistor

1b = Enable active discharge resistor when it is OFF

6:5 RSVD R/W 00 Reserved

4 SW_SC R/W 0

When switch detects short circuit current

0b = Turned OFF and set SWEN[1:0] are set to 00b automatically

1b = Turned off and restart in 100 ms

3:2 SW_OC R/W 01

When load switch detects over current

00b = Turned OFF and set SWEN[1:0] are set to 00b automatically

01b = Turned off and restart in 100 ms

10b, 11b = stay ON

1:0 SWEN R/W 01

SW Enable control

00b = Forced OFF

01b = Enabled by SW_EN pin

10b = Forced ON

11b = Forced ON

Table 64. 0x2A LOADSW_CTRL

8.2.39 0x2B VRFLT1_STS

Voltage regulator fault status register. It is latched to 1 once corresponding regulator

detects fault. If the bit is overwritten to 1, the corresponding bit is newly updated by

current status.

0x2B – VRFLT1_STS Reset Type S

Bit Name Type Reset Description

7 SW_OCP R/W/C 0

Load SW OCP status, deglitched with tDEB_POKB_SW

0 = Load SW doesn’t exceed current limit or is OFF

1 = Load SW exceeded current limit

6 RSVD R/W/C 0 Reserved

5 BUCK6_FLT R/W/C 0

BUCK6 Fault status, deglitched with tDEB_POKB

0b = BUCK6 output is good or BUCK6 is OFF

1b = BUCK6 output falls below 80 % of target

Table 65. 0x2B VRFLT1_STS

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x2B – VRFLT1_STS Reset Type S

Bit Name Type Reset Description

4 BUCK5_FLT R/W/C 0

BUCK5 Fault status, deglitched with tDEB_POKB

0b = BUCK5 output is good or BUCK5 is OFF

1b = BUCK5 output falls below 80 % of target

3 BUCK4_FLT R/W/C 0

BUCK4 Fault status, deglitched with tDEB_POKB

0b = BUCK4 output is good or BUCK4 is OFF

1b = BUCK4 output is below 80 %

2 BUCK3_FLT R/W/C 0

BUCK3 Fault status, deglitched with tDEB_POKB

0b = BUCK3 output is good or BUCK3 is OFF

1b = BUCK3 output falls below 80 % of target

1 BUCK2_FLT R/W/C 0

BUCK2 Fault status, deglitched with tDEB_POKB

0b = BUCK2 output is good or BUCK2 is OFF

1b = BUCK2 output falls below 80 % of target

0 BUCK1_FLT R/W/C 0

BUCK1 Fault status, deglitched with tDEB_POKB

0b = BUCK1 output is good or BUCK1 is OFF

1b = BUCK1 output falls below 80 % of target

Table 65. 0x2B VRFLT1_STS...continued

8.2.40 0x2C VRFLT2_STS

Voltage regulator fault status register. It is latched to 1 once corresponding regulator

detects fault. If the bit is overwritten to 1, the corresponding bit is newly updated by

current status.

0x2C – VRFLT2_STS Reset Type S

Bit Name Type Reset Description

7:5 RSVD R/W/C 000 Reserved

4 LDO5_FLT R/W/C 0

LDO5 Fault status, deglitched with tDEB_POKB

0b = LDO5 output is good or LDO5 is OFF

1b = LDO5 output falls below 80 % of target

3 LDO4_FLT R/W/C 0

LDO4 Fault status, deglitched with tDEB_POKB

0b = LDO4 output is good or LDO4 is OFF

1b = LDO4 output falls below 80 % of target

2 LDO3_FLT R/W/C 0

LDO3 Fault status, deglitched with tDEB_POKB

0b = LDO3 output is good or LDO3 is OFF

1b = LDO3 output falls below 80 % of target

1 LDO2_FLT R/W/C 0

LDO2 Fault status, deglitched with tDEB_POKB

0b = LDO2 output is good or LDO2 is OFF

1b = LDO2 output falls below 80 % of target

0 LDO1_FLT R/W/C 0

LDO1 Fault status, deglitched with tDEB_POKB

0b = LDO1 output is good or LDO1 is OFF

1b = LDO1 output falls below 80 % of target

Table 66. 0x2C VRFLT2_STS

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

8.2.41 0x2D VRFLT1_MASK

VR fault mask bit. Once the bit is masked, PCA9450 doesn’t enter Fault shutdown even if

fault condition of corresponding regulator happens

0x2D – VRFLT1_MASK Reset Type S

Bit Name Type Reset Description

7 RSVD R/W 0 Reserved

6 RSVD R/W 0 Reserved

5 BUCK6_FLT_M R/W 1

BUCK6 FLT mask

0b = Unmask

1b = Masked

4 BUCK5_FLT_M R/W 1

BUCK5 FLT mask

0b = Unmask

1b = Masked

3 BUCK4_FLT_M R/W 1

BUCK4 FLT mask

0b = Unmask

1b = Masked

2 BUCK3_FLT_M R/W 1

BUCK3 FLT mask

0b = Unmask

1b = Masked

1 BUCK2_FLT_M R/W 1

BUCK2 FLT mask

0b = Unmask

1b = Masked

0 BUCK1_FLT_M R/W 1

BUCK1 FLT mask

0b = Unmask

1b = Masked

Table 67. 0x2D VRFLT1_MASK

8.2.42 0x2E VRFLT2_MASK

VR fault mask bit. Once the bit is masked, PCA9450 doesn’t enter Fault shutdown even if

fault condition of corresponding regulator happens

0x2E – VRFLT2_MASK Reset Type S

Bit Name Type Reset Description

7 RSVD R/W/C 0 Reserved

6 RSVD R/W/C 0 Reserved

5 RSVD R/W/C 0 Reserved

4 LDO5_FLT_M R/W 1

LDO5 FLT mask

0b = Unmask

1b = Masked

3 LDO4_FLT_M R/W 1

LDO4 FLT mask

0b = Unmask

1b = Masked

Table 68. 0x2E VRFLT2_MASK

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

0x2E – VRFLT2_MASK Reset Type S

Bit Name Type Reset Description

2 LDO3_FLT_M R/W 1

LDO3 FLT mask

0b = Unmask

1b = Masked

1 LDO2_FLT_M R/W 1

LDO2 FLT mask

0b = Unmask

1b = Masked

0 LDO1_FLT_M R/W 1

LDO1 FLT mask

0b = Unmask

1b = Masked

Table 68. 0x2E VRFLT2_MASK...continued

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

9 Application design-in information

9.1 Reference schematic

9.1.1 PCA9450AA reference schematic

PCA9450AA reference schematic with i.MX 8M Mini is illustrated in Figure 21.

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035724

PCA9450AA

i.MX 8M

Mini

SBIAS, REF,

UVLO,

TSHDN

BUCK2

0.85 V

3 A

INT LDO

VINT

PMIC_RST_B

PMIC_ON_REQ

PMIC_STBY_REQ

NVCC_SNVS

LDO1

WDOG_B

RTC_ RESET_B

POR_B

LDO1

DVS

PGND

INB26

LX 2

(1)

C11

10 µF

C12

22 µF

0.47 µH

R_SNSP2

VSYS

VDD_ARM

100 kΩ

4.7 kΩ

VSYS

SYS

1 µF

LDO1

NVCC_1V8

BUCK5

NVCC_1V8

BUCK5

SCL

l2C

INTERFACE

SDA

IRQ_B

4.7 kΩ

SCLL

VINT SWIN

SDAL

4.7 kΩ

X1, X-tal

C4 LDO1

MUX

3V3 V

BUCK4

SDAH

SCLH

32.768 kHz

X-TAL DRIVER

LDO1

1.8 V

10 mA

XTAL_IN

INL1

LDO1

LDO2

LDO3

LDO4

LDO5

IN BUCK4

SD_VSEL

SYS

XTAL_OUT

CLK_32K_OUTRTC_XTALI

l2C LEVEL

TRANSLATOR

4.7 µF

NVCC_SNVS

1 µF

LDO2

0.8 V

10 mA

VDD_SNVS

1 µF

LDO3

1.8 V

300 mA

VDDA

2.2 µF

LDO4

0.9 V

200 mA

VDD_MIPI_0P9

VDD_MIPI_1P2

1 µF

LDO5

3.3 V/1.8 V

150 mA

LDO

1.2 V

150 mA

NVCC_SD2

C10

1 µF

BUCK1

0.85 V

3 A

DUAL

PHASE

CONFIG

PCA9450

DVS

PGND

INB13

LX1

C13

10 µF

C14

22 µF

0.47 µH

R_SNSP1

VSYS

VDD_SOC

BUCK3

0.85 V

3 A

ON/OFF

CONTROL

AND

I2C

i.MX 8M

Mini

DVS

PGND

INB13

LX3

C15

10 µF

0.47 µH

R_SNSP3_CFG

VSYS VDD_VPU

VDD_GPU

VDD_DRAM

C16

22 µF

BUCK4

3.3 V

3 A

PGND

INB45

LX4

C17

10 µF

C18

22 µF

0.47 µH

BUCK4FB

VSYS

NVCC_3V3

BUCK5

1.8 V

2 A

BUCK6

1.1 V

2 A

PGND

INB45

LX5

C19

4.7 µF

C20

22 µF

0.47 µH

BUCK5FB

VSYS

NVCC_1V8

LOAD SW

DRIVER

PGND

INB26

LX6

C21

4.7 µF

C23

1 µF

C24

1 µF

0.47 µH

BUCK6FB

SWIN

SWOUT

SW_EN

EPAGND

VSYS

BUCK 4

NVCC_DRAM

SD_CARD SD_CARD

C22

22 µF

BUCK_AGND

(1) This capacitor is decoupling capacitor in MCU side.

Figure 21. PCA9450AA application schematic

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

9.1.2 PCA9450B reference schematic

PCA9450B reference schematic with i.MX 8M Nano is illustrated in Figure 22.

aaa-035725

PCA9450B

i.MX 8M

Nano

SBIAS, REF,

UVLO,

TSHDN

BUCK2

0.85 V

3 A

INT LDO

VINT

PMIC_RST_B

PMIC_ON_REQ

PMIC_STBY_REQ

NVCC_SNVS

LDO1

WDOG_B

RTC_ RESET_B

POR_B

LDO1

DVS

PGND

INB26

LX2

(1)

C11

10 µF

C12

22 µF

0.47 µH

R_SNSP2

VSYS

VDD_ARM

100 kΩ

4.7 kΩ

VSYS

SYS

1 µF

LDO1

NVCC_1V8

BUCK5

NVCC_1V8

BUCK5

SCL

l2C

INTERFACE

SDA

IRQ_B

4.7 kΩ

SCLL

VINT SWIN

SDAL

4.7 kΩ

X1, X-tal

C4 LDO1

MUX

3V3 V

BUCK4

SDAH

SCLH

32.768 kHz

X-TAL DRIVER

LDO1

1.8 V

10 mA

XTAL_IN

INL1

LDO1

LDO2

LDO3

LDO4

LDO5

SD_VSEL

SYS

XTAL_OUT

CLK_32K_OUTRTC_ XTALI

l2C LEVEL

TRANSLATOR

4.7 µF

NVCC_SNVS

1 µF

LDO2

0.8 V

10 mA

VDD_SNVS

1 µF

LDO3

1.8 V

300 mA

VDDA

2.2 µF

LDO4

0.9 V

200 mA

VDD_MIPI_1P2

1 µF

LDO5

3.3 V/1.8 V

150 mA

NVCC_SD2

VDD_MIPI_0P9

C10

1 µF

BUCK1

0.85 V

3 A

DUAL

PHASE

CONFIG

PCA9450

DVS

PGND

INB13

LX1

C13

10 µF

C14

22 µF

0.47 µH

R_SNSP1

VSYS VDD_SOC

VDD_VPU

VDD_GPU

VDD_DRAM

BUCK3

0.85 V

3 A

ON/OFF

CONTROL

AND

I2C

i.MX 8M

Nano

DVS

PGND

INB13

LX3

R_SNSP3_CFG

VSYS

BUCK4

3.3 V

3 A

PGND

INB45

LX4

C17

10 µF

C18

22 µF

0.47 µH

BUCK4FB

VSYS

NVCC_3V3

BUCK5

1.8 V

2 A

BUCK6

1.1 V

2 A

PGND

INB45

LX5

C19

4.7 µF

C20

22 µF

0.47 µH

BUCK5FB

VSYS

NVCC_1V8

LOAD SW

DRIVER

PGND

INB26

LX6

C21

4.7 µF

C23

1 µF

C24

1 µF

0.47 µH

BUCK6FB

SWIN

SWOUT

SW_EN

EPAGND

VSYS

BUCK 4

NVCC_DRAM

SD_CARD SD_CARD

C22

22 µF

BUCK_AGND

(1) This capacitor is decoupling capacitor in MCU side.

Figure 22. PCA9450B application schematic

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

9.1.3 PCA9450C reference schematic

PCA9450C reference schematic with i.MX 8M Plus is illustrated in Figure 23

aaa-035726

PCA9450C

i.MX 8M

Plus

SBIAS, REF,

UVLO,

TSHDN

BUCK2

0.85 V

3 A

INT LDO

VINT

PMIC_RST_B

PMIC_ON_REQ

PMIC_STBY_REQ

NVCC_SNVS

LDO1

WDOG_B

RTC_RESET_B

POR_B

LDO1

DVS

PGND

INB26

LX2

(1)

C11

10 µF

C12

22 µF

0.47 µH

R_SNSP2

VSYS

VDD_ARM

100 kΩ

4.7 kΩ

VSYS

SYS

1 µF

LDO1

NVCC_1V8

BUCK5

NVCC_1V8

BUCK5

SCL

l2C

INTERFACE

SDA

IRQ_B

4.7 kΩ

SCLL

VINT SWIN

SDAL

4.7 kΩ

X1, X-tal

C4 LDO1

MUX

3V3 V

BUCK4

SDAH

SCLH

32.768 kHz

X-TAL DRIVER

LDO1

1.8 V

10 mA

XTAL_IN

INL1

LDO1

LDO2

LDO3

LDO4

LDO5

SD_VSEL

SYS

XTAL_OUT

CLK _32K_OUTRTC_XTALI

l2C LEVEL

TRANSLATOR

4.7 µF

NVCC_SNVS

1 µF

LDO2

0.8 V

10 mA

1 µF

LDO3

1.8 V

300 mA

VDDA

2.2 µF

LDO4

0.9 V

200 mA

1 µF

LDO5

3.3 V/1.8 V

150 mA

NVCC_SD2

C10

1 µF

BUCK1

0.85 V

3 A

DUAL

PHASE

CONFIG

PCA9450

DVS

PGND

INB13

LX1

C13

10 µF

C14

22 µF

0.47 µH

R_SNSP1

VSYS VDD_SOC

VDD_VPU

VDD_GPU

VDD_DRAM

BUCK3

0.85 V

3 A

ON/OFF

CONTROL

AND

I2C

i.MX 8M

Plus

DVS

PGND

LX3

R_SNSP3_CFG

BUCK4

3.3 V

3 A

PGND

INB45

LX4

C17

10 µF

C18

22 µF

0.47 µH

BUCK4FB

VSYS

NVCC_3V3

BUCK5

1.8 V

2 A

BUCK6

1.1 V

2 A

PGND

INB45

LX5

C19

4.7 µF

C20

22 µF

0.47 µH

BUCK5FB

VSYS

NVCC_1V8

LOAD SW

DRIVER

PGND

INB26

LX6

C21

4.7 µF

C23

1 µF

C24

1 µF

0.47 µH

BUCK6FB

SWIN

SWOUT

SW_EN

EPAGND

VSYS

BUCK 4

NVCC_DRAM

SD_CARD SD_CARD

C22

22 µF

BUCK_AGND

INB13

C15

10 µF

0.47 µH

VSYS

C16

22 µF

(1) This capacitor is decoupling capacitor in MCU side.

Figure 23. PCA9450C application schematic

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

9.2 Typical application

Please follow the recommendations below for your schematic/PCB layout design:

• 1 μF bypass capacitor on VINT and VSYS, located as close as possible to those pins to

ground

• Input capacitors must be present on the INB and INL supplies if used

• Output inductors and capacitors must be used on the outputs of the BUCK converters if

used

• Output capacitors must be used on the outputs of the LDOs

9.2.1 Buck regulators

9.2.1.1 Inductor selection for buck converters

Each of the converters on PCA9450 typically uses a 0.47 μH output inductor which

has to be rated for its DC resistance and saturation current. The DC resistance of the

inductance influences directly the efficiency of the converter. Therefore, an inductor with

lowest DC resistance must be selected for highest efficiency.

Equation 1 calculates the maximum inductor current under static load conditions. The

saturation current of the inductor must be rated higher than the maximum inductor

current as calculated with Equation 2. This is needed because during heavy load

transient the inductor current rises above the calculated value.

(1)

(2)

Where

•f = switching frequency (2 MHz)

•L = Inductance

•ΔIL = Peak to peak inductor ripple current

•IL.max = Maximum inductor current

A conservative approach is to select the inductor current rating just for the maximum

switch current of the PCA9450

Table 69 shows possible inductors list.

Buck Vendor Part number Size DCR [mΩ] Isat [A] Itemp [A]

Sunlord WPN252012HR47MT 2520 29 5.6 4.0

BUCK1, BUCK2,

BUCK3, BUCK4 Murata 1239AS-H-R47M 2520 39 3.8 3.7

BUCK5, BUCK6 Sunlord WPN201610UR47MT 2016 28 5.0 4.1

Table 69. Tested inductor list

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Buck Vendor Part number Size DCR [mΩ] Isat [A] Itemp [A]

Murata 1286AS-H-R47M 2016 52 3.4 3.2

Table 69. Tested inductor list...continued

9.2.1.2 Output capacitor selection for buck converters

The fast response adaptive constant ON time control scheme of the buck converters

implemented on PCA9450 allows the use of a single typical 22 µF ceramic capacitor for

each converter output without compromising on output overshoot/undershoot voltage

ripple during heavy load transients. Ceramic capacitors having low ESR values have the

lowest output voltage ripple and are recommended.

If ceramic output capacitors are used, the capacitor RMS ripple current rating always

meets the application requirements. Just for completeness, the RMS ripple current is

calculated in Equation 3.

(3)

At nominal load current, the inductive converters operate in PWM mode. The overall

output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR

plus the voltage ripple caused by charging and discharging the output capacitor:

(4)

Where

•The highest output voltage ripple occurs at the highest input voltage Vin.

At light load currents, the converters operate in PFM mode and the output voltage

ripple is dependent on the output capacitor value. The output voltage ripple is set by the

internal comparator delay and the external capacitor. The typical output voltage ripple is

less than 1 % of the nominal output voltage.

9.2.1.3 Input capacitor selection for buck converters

Low ESR input capacitor is highly recommended for best input voltage filtering and

minimizing the interference with other circuits caused by high input voltage spikes

because of the nature of buck converter. Each DC-DC converter requires a 10 μF

ceramic input capacitor on its input pins. The input capacitor could be increased without

any limit for better input voltage filtering.

9.2.2 Crystal oscillator

9.2.2.1 Crystal selection

The most important parameters when choosing a crystal are:

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

• Crystal's required effective load capacitance (typically 6 pF to 15 pF)

• Crystal's ESR (typically 30 kΩ to 100 kΩ)

• Tolerance (typically 5 ppm to 30 ppm)

All of these crystal parameters can usually be found in the crystal datasheet.

9.2.2.2 Effective load capacitance

The crystal oscillator (see Figure 24) uses two load capacitors, CL1 and CL2, as load

for the crystal. These capacitors generate, together with the crystal's inductance, the

required 180° phase shift of the feedback loop.

aaa-035750

XTAL_IN

180°

XTAL_OUT

32.768 kHz

Xtal

CL2 CL2_P

CL1

CL1_P

Figure 24. Crystal oscillator

From the view of the crystal, these capacitors are a serial connection through GND.

Hence, if using two equal capacitors, the values of these capacitors must be twice the

required load capacitance. It is also important to consider PCB parasitic capacitances for

the calculation of the necessary capacitors according to Equation 5.

(5)

Where:

•C’L1 = CL1 + CL1_P, CL1_P is PCB parasitic capacitance.

•C’L2 = CL2 + CL2_P , CL2_P is PCB parasitic capacitance.

When using equal capacitors for CL1 and CL2 and a symmetric layout with equal parasitic

capacitance on both crystal pins, the effective load capacitance is shown in Equation 6.

(6)

Example:

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Crystal requires 12 pF load.

Parasitic capacitance per pin is 2 pF.

CL1 = (2 × CLoad) – CL1_P = (2 × 12 pF) – 2 pF = 22 pF

CL2 = CL1 = 22 pF

9.2.2.3 Frequency tuning

The crystal oscillator frequency is very much dependent on the load capacitance that is

connected. Therefore, measuring the oscillator frequency gives a good indication if the

load capacitors that are used match the crystal requirements. This measurement also

automatically includes the parasitic PCB and pin capacitances of the application.

It is strongly recommended not to measure the oscillator frequency directly at the crystal

pins. The capacitance at the crystal pins is in the range of 10 pF, and the impedance on

this signal line is several megaohms. A typical passive probe has a capacitance in the

range of 10 pF and an input impedance of approximately 10 MΩ. Both values are in the

range of the oscillator characteristics and heavily influence the behavior of the crystal

oscillators. Instead, it is recommended to measure frequency at CLK_32K_OUT pin.

Assuming the crystal itself has no tolerance, too low a capacitive load results in a higher

oscillator frequency than expected and, vice versa, the frequency is lower than the

nominal value, if the load is too high. Therefore, if the oscillation frequency is too high,

the value of load capacitors must be increased. When too low frequency is measured,

it is necessary to decrease the value of the load capacitors. Comparing the finally

optimized capacitors with the crystal data sheet value for load capacitance gives the

parasitic capacitance added by the PCB layout and pins.

9.3 Layout guide

Layout guide is shown in Figure 25.

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

aaa-035727

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

WOU

)

(

)

(

)

µH

(

(0603)

(

)

(

)

(0603)

Figure 25. PCA9450 layout

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

10 Limiting values

(Absolute maximum ratings)

Explanation Pin Conditions Min Max Unit

VSYS, INB13, INB26, INB45, INL1,

SWIN -0.5 +6.0 V

SWOUT -0.5 SWIN + 0.5 V

LX1, LX3 -0.5 INB13 + 0.5 V

LX2, LX6 -0.5 INB26 + 0.5 V

LX4, LX5 -0.5 INB45 + 0.5 V

R_SNSP1, R_SNSP2, R_SNSP3_

CFG -0.5 VSYS + 0.5 V

BUCK_AGND, AGND -0.5 +0.5 V

BUCK4FB, BUCK5FB, BUCK6FB -0.5 VSYS + 0.5 V

LDO1, LDO2, LDO3, LDO4, LDO5 -0.5 VINL1 + 0.5 V

XTAL_IN, XTAL_OUT -0.5 VSYS + 0.5 V

RTC_RESET_B, PMIC_RST_B,

CLK_32K_OUT -0.5 LDO1 + 0.5 V

PMIC_ON_REQ, POR_B PMIC_

STBY_REQ, WDOG_B, IRQ_B,

SCL, SDA, SD_VSEL, SW_EN

-0.5 VSYS + 0.5 V

SCLH, SDAH -0.5 SWIN + 0.5 V

SCLL, SDAL -0.5 VINT + 0.5 V

Voltage range

(with respect to

EP)

VINT -0.5 +2.0 V

LX1, LX2, LX3, LX4 RMS current 5.0 A

LX5, LX6 RMS current 4.0 AOutput Current

SWIN, SWOUT RMS current 0.5 A

Junction

temperature -40 +150 °C

HBM (JESD22-001) -2 +2 kV

VESD All pins CDM (JESD22-C101E) -500 +500 V

Table 70. Limiting values

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

11 Recommended operating conditions

Explanation Pin Conditions Min Max Unit

VSYS, INL1 2.7 5.5 V

INB13, INB26, INB45 2.7 5.5 V

Voltage range (with

respect to EP)

SWIN 2.7 5.5 V

Junction

temperature -40 +125 °C

Ambient

temperature -40 +105 °C

Table 71. Recommended Operating Conditions

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

12 Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient [1] [2] 32.1 °C/W

Table 72. Thermal characteristics

[1] Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal

performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an

application-specific environment

[2] Thermal test board meets JEDEC specification for this package (JESD51-9)

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13 Electrical characteristics

13.1 Top level parameter

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, Tamb= -40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

Quiescent Current

LDO1 and LDO2 are ON and

no load, other regulators are

OFF, CLK_32K_OUT enabled,

PMIC_ON_REQ = L, Tamb= 25 °C

23 50 μA

IQ_SNVS VSYS SNVS Current LDO1 and LDO2 are ON and

no load, other regulators are

OFF, CLK_32K_OUT enabled,

PMIC_ON_REQ = L, Tamb= -40 °C

~105 °C

23 120 μA

IQ_STADNDBY VSYS Standby current

LDO1, LDO2, LDO3, LDO4, LDO5,

BUCK1, BUCK3, BUCK4, BUCK5,

BUCK6 are ON and no load. PMIC_

ON_REQ = H, PMIC_STBY_REQ =

220 350 μA

VSYS

VSYS_UVLO VSYS UVLO VSYS Rising 2.85 3.0 3.15 V

VSYS_UVLO_H VSYS UVLO Hysteresis VSYS Falling 200 mV

VSYS_POR VSYS POR VSYS Rising 2.2 2.4 2.6 V

VSYS_POR_H VSYS POR Hysteresis VSYS Falling 200 mV

VINT

Internal Power supply

LDO VSYS = 3.8 V 1.7 1.8 1.9 V

Low VSYS

VLOW_VSYS Low VSYS Low VSYS threshold above

VSYS_UVLO, LOW_VSYS [7:6] = 01b 150 200 250 mV

VLOW_VSYS_

HYS

Low VSYS Hysteresis 110 mV

Thermal Shutdown

TJSHDN Thermal Shutdown Tj Rising, 15 °C hysteresis 150 °C

TJ105 Thermal interrupt1 Tj Rising, 15 °C hysteresis 95 105 125 °C

TJ125 Thermal interrupt2 Tj Rising, 15 °C hysteresis 115 125 145 °C

Logic and Control signals

VIL Input Low level

PMIC_ON_REQ, PMIC_STBY_

REQ, WDOG_B, SD_VSEL, SW_

EN, PMIC_RST_B

0.4 V

Table 73. Top level parameter

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, Tamb= -40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

VIH Input High level

PMIC_ON_REQ, PMIC_STBY_

REQ, WDOG_B, SD_VSEL, SW_

EN, PMIC_RST_B

1.4 V

ILEAK

Logic Input leakage

current

PMIC_ON_REQ, PMIC_STBY_

REQ, WDOG_B, SD_VSEL:

VLogic = 5.5 V, VSYS = 5.5 V

-0.5 +0.5 μA

RPD

Internal Pull-down

resistor SW_EN 1.2 MΩ

VOL Output Low level RTC_RESET_B, IRQB, POR_B, IOL

= 6 mA 0.4 V

RPU Internal Pull-up resistor RTC_RESET_B, PMIC_RST_B to

LDO1 100 KΩ

Logic signal (PCA9450B/ PCA9450C)

VIL Input Low level R_SNSP3_CFG 0.4 V

VIH Input High level R_SNSP3_CFG 1.4 V

ILEAK

Logic Input leakage

current

R_SNSP3_CFG

VLogic = 5.5 V, VSYS = 5.5 V -1 +1 μA

Timing spec

tDEB_POKB

Debounce time of

regulator POKB 320 400 480 μs

tDEB_POKB_SW

Debounce time of Load

SW POKB 240 300 360 μs

tDEB_WDOGB

Debounce time of

WDOG_B 90 120 150 μs

tDEB_PMIC_

RST_B

Debounce time of

PMIC_RST_B T_PMIC_RST_DEB[2:0] = 001b 40 50 60 ms

tSNVS_PU

Time to 90 % of LDO1

from VSYS UVLO

detected

16 20 24 ms

tRTC_RST

Time to RTC_RESET_B

release from LDO2 POK 16 20 24 ms

t32K_EN

Time to 32K buffer

enable from LDO2 POK 8 10 12 ms

tRTC_TRAN

Time to transition to Xtal

osc after RTC_RESET_

B release

0.8 1 1.2 sec

tON_DEB

PMIC_ON_REQ high

debounce time Programmable, Ton_Deb[1:0] = 01b 16 20 24 ms

tSTEP

Time step to turn on

each regulator Programmable, Tstep[1:0] = 01b 1.6 2 2.4 ms

tOFF_STEP

Time step to turn off

each regulator Programmable, Toff_step[1:0] = 10b 6 8 10 ms

Table 73. Top level parameter...continued

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, Tamb= -40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

tOFF_DEB

PMIC_ON_REQ low

debounce time Programmable, Toff_Deb = 0b 90 120 150 μs

tPORB

Time from LDO5 POK to

POR_B release during

Power on seq

16 20 24 ms

tFLT_SD_PU

Fault time to POK after

regulator enable during

power up sequence

At power up sequence 8 10 12 ms

tFLT_POK_MSK

POK mask time when

regulator is enabled at

RUN/Standby mode

1.6 2 2.4 ms

tFLT_THSD

Time to enter FAULT_

SD when thermal Fault

occurs

170 210 250 μs

tFLT_SD_STAY

Time to stay at FAULT_

SD to move other mode 80 100 120 ms

tFLT_SD_WAIT

Wait time to enter

FAULT_SD after fault

interrupt

At Standby and Run mode,

programmable, tFLT_SD_WAIT =

0b1

80 100 120 ms

tRESTART

Wait time to start power

up after power down at

cold reset

Programmable, Trestart = 0b 200 250 300 ms

tWRESET

POR_B low time at

Warm reset 16 20 24 ms

Table 73. Top level parameter...continued

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.2 I2C level translator

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, Tamb= -40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

VDDH Operating voltage Internally tied to SWIN 2.7 5.5 V

IVDDH Shutdown current SWIN = 3.3 V, I2C_LT_EN bit = 0b 1 5 μA

IVDDH Active current SWIN = 3.3 V, I2C_LT_EN bit = 1b,

SCLL, SDAL = 1.8 V 60 90 μA

IVDDH Active current SWIN = 3.3 V, I2C_LT_EN bit = 1b,

SCLL, SDAL = 0 V 715 850 μA

VIH High level input voltage SWIN = 3.3 V, I2C_LT_EN bit = 1b VINT –

0.2 V

VIL Low level input voltage SWIN = 3.3 V, I2C_LT_EN bit = 1b 0.15 V

VOH High level output voltage SWIN = 3.3 V, I2C_LT_EN bit = 1b,

IOL = 20 μA

0.75 *

SWIN V

VOL Low level output voltage SWIN = 3.3 V, I2C_LT_EN bit = 1b,

IOL = 1 mA 0.4 V

CI/O

[1] Input Output

capacitance SWIN = 3.3 V 5 pF

tPHL

[1] High to Low propagation

delay

SWIN = 3.3 V, SCL/SDA to SCLH/

SDAH 4.0 4.7 ns

tPLH

[1] Low to High propagation

delay

SWIN = 3.3 V, SCL/SDA to SCLH/

SDAH 5.0 6.8 ns

tPHL

[1] High to Low propagation

delay

SWIN = 3.3 V, SCLH/SDAH to SCL/

SDA 4.0 4.5 ns

tPLH

[1] Low to High propagation

delay

SWIN = 3.3 V, SCLH/SDAH to SCL/

SDA 4.0 4.5 ns

ten

[1] Enable time SWIN = 3.3 V, from I2C enable 100 μs

fdata

[1] Data rate 20 Mbps

Table 74. I2C level translator

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

72 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.3 BUCK1 (PCA9450AA/PCA9450B)

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK1 = 0.85 V, COUT = 22 μF, Tamb= -40 °C ~

+105 °C

Symbol Parameter Conditions Min Typ Max Unit

VINB13 Input voltage range INB13 pin 2.85 5.5 V

IShutdown Shutdown current Regulator disabled, VINB13 = 5.0 V 0.1 μA

IQQuiescent current Regulator enabled, No load, No

switching 20 μA

IOUT_MAX Max Output Current 3000 mA

VBUCK1

Programmable Output

voltage range I2C programmable, 12.5 mV step 0.6 2.1875 V

VINB13 = 3.8 V, VBUCK1_OUT = 0.85 V,

IOUT = 0 A, FPWM mode, 25 °C -0.6 +0.6 %

VBUCK1_OUT

DC Output Voltage

Accuracy VINB13 = 3.8 V, VBUCK1_OUT = 0.85 V,

IOUT = 0 A, FPWM mode

-2 +2 %

ΔVOUT(ΔVINB)

[1] DC Line regulation VINB13 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V

ΔVOUT(ΔIOUT)

[1] DC Load regulation 0 mA < IOUT < IOUT_MAX, VBUCK1_OUT

= 0.85 V 3 mV/A

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

IOUT changes 0 to IOUT_MAX (1 A/μs

slope), VBUCK1_OUT = 0.85 V 50 mV

ΔVOUT

[1] Output voltage Ripple FPWM mode 10 mV

fSW

Switching Frequency in

CCM 2 MHz

High Side P-FET RDSON

VINB13 = 3.8 V, including bonding

wire 87 mΩ

RDSON

Low Side N-FET RDSON

VINB13 = 3.8 V, including bonding

wire 45 mΩ

High side current limit VINB13 = 3.8 V 4.0 4.5 5.0 A

ILIM Low side current limit VINB13 = 3.8 V 2.5 3.0 3.7 A

tSTART

[1] Startup time EN rising to 90 % of output voltage 250 500 μs

VRAMP

[1] Output voltage slew rate Programmable, RAMP[1:0] = 01b 12.5 mV/μs

Vsoft_strup

[1] Soft-start slew rate 12.5 mV/μs

RDIS

Output Active Discharge

Resistance 100 150 Ω

POK Output Power good 85 95 %

L[1] Inductor value 0.47 µH

COUT

[1] Output capacitance Minimum nominal capacitance 22 μF

Table 75. BUCK1 (PCA9450AA/PCA9450B)

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.4 Dual Phase BUCK1 (PCA9450C)

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK1 = 0.85 V, COUT = 44 μF, Tamb= -40 °C ~

+105 °C

Symbol Parameter Conditions Min Typ Max Unit

VINB13 Input voltage range INB13 pin 2.85 5.5 V

IShutdown Shutdown current Regulator disabled, VINB13 = 5.0 V 0.2 μA

IQQuiescent current Regulator enabled, No load, No

switching 20 μA

IOUT_MAX Max Output Current 6000 mA

VBUCK1

Programmable Output

voltage range I2C programmable, 12.5 mV step 0.6 2.1875 V

VINB13 = 3.8 V, VBUCK1_OUT = 0.85 V,

IOUT = 0 A, FPWM mode, 25 °C -0.6 +0.6 %

VBUCK1_OUT

DC Output Voltage

Accuracy VINB13 = 3.8 V, VBUCK1_OUT = 0.85 V,

IOUT = 0 A, FPWM mode

-2 +2 %

ΔVOUT(ΔVINB)

[1] DC Line regulation VINB13 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V

ΔVOUT(ΔIOUT)

[1] DC Load regulation 0 mA < IOUT < IOUT_MAX, VBUCK1_OUT

= 0.85 V 3 mV/A

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

IOUT changes 0 to IOUT_MAX (1 A/μs

slope), VBUCK3_OUT = 0.85 V 50 mV

ΔVOUT

[1] Output voltage Ripple FPWM mode 10 mV

fSW

Switching Frequency in

CCM 2 MHz

High Side P-FET RDSON VINB13 = 3.8 V, including bonding wire 87 mΩ

RDSON Low Side N-FET RDSON VINB13 = 3.8 V, including bonding wire 45 mΩ

High side current limit VINB13 = 3.8 V, each phase 4.0 4.5 5.0 A

ILIM Low side current limit VINB13 = 3.8 V, each phase 2.5 3.0 3.7 A

tSTART

[1] Startup time EN rising to 90 % of output voltage 250 500 μs

VRAMP

[1] Output voltage slew rate Programmable, RAMP[1:0] = 01b 12.5 mV/μs

Vsoft_strup

[1] Soft-start slew rate 12.5 mV/μs

POK Output Power good 75 85 95 %

RDIS

Output Active Discharge

Resistance One phase buck 100 150 Ω

L[1] Inductor value Each phase 0.47 µH

COUT

[1] Output capacitance Minimum nominal capacitance 44 μF

Table 76. Dual Phase BUCK1 (PCA9450C)

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.5 BUCK2

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK2 = 0.85 V, COUT = 22 μF, Tamb= -40 °C ~

+105 °C

Symbol Parameter Conditions Min Typ Max Unit

VINB26 Input voltage range INB26 pin 2.85 5.5 V

IShutdown Shutdown current Regulator disabled, VINB26 = 5.0 V 0.1 μA

IQQuiescent current Regulator enabled, No load, No

switching 20 μA

IOUT_MAX Max Output Current 3000 mA

VBUCK2

Programmable Output

voltage range I2C programmable, 12.5 mV step 0.6 2.1875 V

VINB26 = 3.8 V, VBUCK2_OUT =

0.85 V, IOUT = 0A, FPWM mode,

25 °C

-0.6 +0.6 %

VBUCK2_OUT

DC Output Voltage

Accuracy VINB26 = 3.8 V, VBUCK2_OUT =

0.85 V, IOUT = 0A, FPWM mode

-2 +2 %

ΔVOUT(ΔVINB)

[1] DC Line regulation VINB26 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V

ΔVOUT(ΔIOUT)

[1] DC Load regulation 0 mA < IOUT < IOUT_MAX,

VBUCK2_OUT = 0.85 V 3 mV/A

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

IOUT changes 0 to IOUT_MAX (1 A/μs

slope), VBUCK2_OUT = 0.85 V 50 mV

ΔVOUT

[1] Output voltage Ripple FPWM mode 10 mV

fSW

Switching Frequency in

CCM 2 MHz

High Side P-FET RDSON

VINB26 = 3.8 V, including bonding

wire 87 mΩ

RDSON

Low Side N-FET RDSON

VINB26 = 3.8 V, including bonding

wire 45 mΩ

High side current limit VINB26 = 3.8 V 4.0 4.5 5.0 A

ILIM Low side current limit VINB26 = 3.8 V 2.5 3.0 3.7 A

tSTART

[1] Startup time EN rising to 90 % of output voltage 250 500 μs

VRAMP

[1] Output voltage slew rate Programmable, RAMP[1:0] = 01b 12.5 mV/μs

Vsoft_strup

[1] Soft-start slew rate 12.5 mV/μs

POK Output Power good 75 85 95 %

RDIS

Output Active Discharge

Resistance 100 150 Ω

L[1] Inductor value 0.47 µH

COUT

[1] Output capacitance Minimum nominal capacitance 22 μF

Table 77. BUCK2

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.6 BUCK3 (PCA9450AA)

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK3 = 0.85 V, COUT = 22 μF, Tamb= -40 °C ~

+105 °C

Symbol Parameter Conditions Min Typ Max Unit

VINB13 Input voltage range INB13 pin 2.85 5.5 V

IShutdown Shutdown current Regulator disabled, VINB13 = 5.0 V 0.1 μA

IQQuiescent current Regulator enabled, No load, No

switching 20 μA

IOUT_MAX Max Output Current 3000 mA

VBUCK3

Programmable Output

voltage range I2C programmable, 12.5 mV step 0.6 2.1875 V

VINB13 = 3.8 V, VBUCK3_OUT = 0.85 V,

IOUT = 0 A, FPWM mode, 25 °C -0.6 +0.6 %

VBUCK3_OUT

DC Output Voltage

Accuracy VINB13 = 3.8 V, VBUCK3_OUT = 0.85 V,

IOUT = 0 A, FPWM mode

-2 +2 %

ΔVOUT(ΔVINB)

[1] DC Line regulation VINB13 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V

ΔVOUT(ΔIOUT)

[1] DC Load regulation 0 mA < IOUT < IOUT_MAX, VBUCK3_OUT

= 0.85 V 3 mV/A

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

IOUT changes 0 to IOUT_MAX (1 A/μs

slope), VBUCK3_OUT = 0.85 V 50 mV

ΔVOUT

[1] Output voltage Ripple FPWM mode 10 mV

fSW

Switching Frequency in

CCM 2 MHz

High Side P-FET RDSON

VINB13 = 3.8 V, including bonding

wire 87 mΩ

RDSON

Low Side N-FET RDSON

VINB13 = 3.8 V, including bonding

wire 45 mΩ

High side current limit VINB13 = 3.8 V 4.0 4.5 5.0 A

ILIM Low side current limit VINB13 = 3.8 V 2.5 3.0 3.7 A

tSTART

[1] Startup time EN rising to 90 % of output voltage 250 500 μs

VRAMP

[1] Output voltage slew rate Programmable, RAMP[1:0] = 01b 12.5 mV/μs

Vsoft_strup

[1] Soft-start slew rate 12.5 mV/μs

POK Output Power good 75 85 95 %

RDIS

Output Active Discharge

Resistance 100 150 Ω

L[1] Inductor value 0.47 µH

COUT

[1] Output capacitance Minimum nominal capacitance 22 μF

Table 78. BUCK3 (PCA9450AA)

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.7 BUCK4

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK4 = 3.3 V, COUT = 22 μF, Tamb= -40 °C ~

+105 °C

Symbol Parameter Conditions Min Typ Max Unit

VINB45 Input voltage range INB45 pin 2.85 5.5 V

IShutdown Shutdown current Regulator disabled, VINB45 = 5.0 V 0.1 μA

IQQuiescent current Regulator enabled, No load, No

switching 20 μA

IOUT_MAX Max Output Current 3000 mA

VBUCK4

Programmable Output

voltage range I2C programmable, 25 mV step 0.6 3.4 V

VINB45 = 3.8 V, VBUCK4_OUT = 3.3 V,

IOUT = 0 A, FPWM mode, 25 °C -0.5 +0.5 %

VBUCK4_OUT

DC Output Voltage

Accuracy VINB45 = 3.8 V, VBUCK4_OUT = 3.3 V,

IOUT = 0 A, FPWM mode

-2 +2 %

ΔVOUT(ΔVINB)

[1] DC Line regulation VINB45 = 4 V to 5 V, IOUT= IOUT_MAX 2 mV/V

ΔVOUT(ΔIOUT)

[1] DC Load regulation 0 mA < IOUT < IOUT_MAX,

VBUCK4_OUT = 3.3 V 6 mV/A

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

IOUT changes 0 to IOUT_MAX (1 A/μs

slope), VBUCK4_OUT = 3.3 V 160 mV

ΔVOUT

[1] Output voltage Ripple FPWM mode 10 mV

fSW

Switching Frequency in

CCM 2 MHz

High Side P-FET RDSON

VINB45 = 3.8 V, including bonding

wire 87 mΩ

RDSON

Low Side N-FET RDSON

VINB45 = 3.8 V, including bonding

wire 45 mΩ

High side current limit VINB45 = 3.8 V 4.0 4.5 5.0 A

ILIM Low side current limit VINB45 = 3.8 V 2.5 3.0 3.7 A

tSTART

[1] Startup time EN rising to 90 % of output voltage 250 500 μs

Vsoft_strup

[1] Soft-start slew rate 12.5 mV/μs

POK Output Power good 75 85 95 %

RDIS

Output Active Discharge

Resistance 100 150 Ω

L[1] Inductor value 0.47 µH

COUT

[1] Output capacitance Minimum nominal capacitance 22 μF

Table 79. BUCK4

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.8 BUCK5

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK5 = 1.8 V, COUT = 22 μF, Tamb= -40 °C ~

+105 °C

Symbol Parameter Conditions Min Typ Max Unit

VINB45 Input voltage range INB45 pin 2.85 5.5 V

IShutdown Shutdown current Regulator disabled, VINB45 = 5.0 V 0.1 μA

IQQuiescent current Regulator enabled, No load, No

switching 20 μA

IOUT_MAX Max Output Current 2000 mA

VBUCK5

Programmable Output

voltage range I2C programmable, 25 mV step 0.6 3.4 V

VINB45 = 3.8 V, VBUCK5_OUT = 1.8 V,

IOUT = 0 A, FPWM mode, 25 °C -0.5 +0.5 %

VBUCK5_OUT

DC Output Voltage

Accuracy VINB45 = 3.8 V, VBUCK5_OUT = 1.8 V,

IOUT = 0 A, FPWM mode

-2 +2 %

ΔVOUT(ΔVINB)

[1] DC Line regulation VINB45 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V

ΔVOUT(ΔIOUT)

[1] DC Load regulation 0 mA < IOUT < IOUT_MAX,

VBUCK5_OUT = 1.8 V 7 mV/A

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

IOUT changes 0 to IOUT_MAX (1 A/μs

slope), VBUCK5_OUT = 1.8 V 50 mV

ΔVOUT

[1] Output voltage Ripple FPWM mode 22 mV

fSW

Switching Frequency in

CCM 2 MHz

High Side P-FET

RDSON

VINB45 = 3.8 V, including bonding

wire 130 mΩ

RDSON Low Side N-FET

RDSON

VINB45 = 3.8 V, including bonding

wire 70 mΩ

High side current limit VINB45 = 3.8 V 3.0 3.5 4.0 A

ILIM Low side current limit VINB45 = 3.8 V 1.5 2 2.7 A

tSTART

[1] Startup time EN rising to 90 % of output voltage 250 500 μs

Vsoft_strup

[1] Soft-start slew rate 12.5 mV/μs

POK Output Power good 75 85 95 %

RDIS

Output Active

Discharge Resistance 100 150 Ω

L[1] Inductor value 0.47 µH

COUT

[1] Output capacitance Minimum nominal capacitance 22 μF

Table 80. BUCK5

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.9 BUCK6

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK6 = 1.1 V, COUT = 22 μF, Tamb= -40 °C to

+105 °C

Symbol Parameter Conditions Min Typ Max Unit

VINB26 Input voltage range INB26 pin 2.85 5.5 V

IShutdown Shutdown current Regulator disabled, VINB26 = 5.0 V 0.1 μA

IQQuiescent current Regulator enabled, No load, No

switching 20 μA

IOUT_MAX Max Output Current 2000 mA

VBUCK6

Programmable Output

voltage range I2C programmable, 25 mV step 0.6 3.4 V

VINB26 = 3.8 V, VBUCK6_OUT = 1.1 V,

IOUT = 0 A, FPWM mode, 25 °C -0.8 +0.8 %

VBUCK6_OUT

DC Output Voltage

Accuracy VINB26 = 3.8 V, VBUCK6_OUT = 1.1 V,

IOUT = 0 A, FPWM mode

-2 +2 %

ΔVOUT(ΔVINB)

[1] DC Line regulation VINB26 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V

ΔVOUT(ΔIOUT)

[1] DC Load regulation 0 mA < IOUT < IOUT_MAX,

VBUCK6_OUT = 1.1 V 6 mV/A

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

IOUT changes 0 to IOUT_MAX (1 A/μs

slope), VBUCK6_OUT = 1.1 V 50 mV

ΔVOUT

[1] Output voltage Ripple FPWM mode 18 mV

fSW

Switching Frequency in

CCM 2 MHz

High Side P-FET RDSON

VINB26 = 3.8 V, including bonding

wire 130 mΩ

RDSON

Low Side N-FET RDSON

VINB26 = 3.8 V, including bonding

wire 70 mΩ

High side current limit VINB26 = 3.8 V 3.0 3.5 4.0 A

ILIM Low side current limit VINB26 = 3.8 V 1.5 2 2.7 A

tSTART

[1] Startup time EN rising to 90 % of output voltage 250 500 μs

Vsoft_strup

[1] Soft-start slew rate 12.5 mV/μs

POK Output Power good 75 85 95 %

RDIS

Output Active Discharge

Resistance 100 150 Ω

L[1] Inductor value 0.47 µH

COUT

[1] Output capacitance Minimum nominal capacitance 22 μF

Table 81. BUCK6

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.10 LDO1

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VLDO1 = 1.8 V, CINL1 = 4.7 μF, COUT = 1 μF, Tamb=

-40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

VIN Input voltage range INL1 pin 2.85 5.5 V

IQQuiescent current Regulator enabled, No load 2 μA

IOUT_MAX

Maximum Output DC

Current VIN > 2.85 V, VLDO1 = 1.8 V 10 mA

ILIMIT Short Current Limit Output shorted to GND 30 60 mA

VDO Dropout Voltage IOUT = IOUT_MAX, VIN = 3.2 V,

L1_OUT[2:0]= 0x7, 3.3 V 35 60 mV

Nominal output voltage I2C Programmable, 100 mV step 1.6 3.3 V

Default voltage 1.8 VVLDO1

DC accuracy VLDO1 = 1.8 V, ILoad = 5 mA -3 3 %

VNOISE

[1] Output noise f = 10 Hz to 10 kHz, IOUT = 10 %

of IMAX, VLDO1 = 1.8 V 400 μV

ΔVOUT(ΔVINL) DC Line regulation VLDO1 +0.3 V < VIN < 5.5 V,

IOUT(LDO1) = 10 % of IOUT_MAX

0.2 0.5 %/V

ΔVOUT(ΔIOUT) DC Load regulation VIN = VLDO1 +0.3 V to 5.5 V,

0 mA < IOUT < IOUT_MAX

0.5 1 %

ΔVOUT(ΔVINL)

[1] Transient Line

Response

VLDO1 +0.3 V < VIN < 5.5 V,

IOUT(LDO1) = 10 % of IOUT_MAX, tr =

10 μs

0.5 %/V

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

VIN = VLDO1 +0.3 V to 5.5 V,

1 mA < IOUT < IOUT_MAX , tr =

10 μs, VLDO1 = 1.8 V

-3 3 %

PSRR[1] Power Supply Rejection

ratio

f = 10 Hz to 10 kHz, IOUT = 10 %

of IOUT_MAX

45 dB

Vsoft_strup

[1] Soft-start slew rate IOUT = 0 mA, 10 % to 90 % of

VLDO1

15 mV/μs

Vov_srtup

[1] Overshoot at startup IOUT = 0 mA 10 mV

tEN

[1] Enable time EN rising to 90 % of output

voltage 150 μs

POK Output Power good Percentage of VLDO1 configuration 75 85 92 %

RDIS

Active Discharge

Resistance 100 150 Ω

COUT

[1] Output capacitance Minimum nominal capacitance 1 μF

Table 82. LDO1

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.11 LDO2

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VLDO2 = 0.85 V, CINL1 = 4.7 μF, COUT = 1 μF, Tamb=

-40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

VIN Input voltage range INL1 pin 2.85 5.5 V

IQQuiescent current Regulator enabled, No load 2 μA

IOUT_MAX

Maximum Output DC

Current VIN > 2.8 V, VLDO2 = 0.8 V 10 mA

ILIMIT Short Current Limit Output shorted to GND 30 60 mA

VDO Dropout Voltage IOUT = IOUT_MAX, 35 60 mV

Nominal output voltage I2C Programmable, 50 mV step 0.8 1.5 V

Default voltage 0.85 VVLDO2

DC accuracy VLDO2 = 0.8 V, ILoad = 5 mA -3 3 %

VNOISE

[1] Output noise f = 10 Hz to 10 kHz, IOUT = 10 % of

IMAX, VLDO2 = 0.8 V 400 μV

ΔVOUT(ΔVINL) DC Line regulation VLDO2 +0.3 V < VIN < 5.5 V,

IOUT(LDO2) = 10 % of IOUT_MAX

0.2 0.5 %/V

ΔVOUT(ΔIOUT) DC Load regulation VIN = VLDO2 +0.3 V to 5.5 V,

0 mA < IOUT < IOUT_MAX

0.5 1 %

ΔVOUT(ΔVINL)

[1] Transient Line Response

VLDO2 +0.3 V < VIN < 5.5 V,

IOUT(LDO2) = 10 % of IOUT_MAX, tr =

10 μs

0.5 %/V

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

VIN = VOUT +0.3 V to 5.5 V,

1 mA < IOUT < IOUT_MAX , tr = 10 μs,

VLDO2 = 0.8 V

-3 3 %

PSRR[1] Power Supply Rejection

ratio

f = 10 Hz to 10 kHz, IOUT = 10 % of

IOUT_MAX

60 dB

Vsoft_strup

[1] Soft-start slew rate IOUT = 0 mA, 10 % to 90 % of

VLDO2

15 mV/μs

Vov_srtup

[1] Overshoot at startup IOUT = 0 mA 10 mV

tEN

[1] Enable time EN rising to 90 % of output voltage 100 μs

POK Output Power good Percentage of VLDO2 configuration 75 85 92 %

RDIS

Active Discharge

Resistance 100 150 Ω

COUT

[1] Output capacitance Minimum nominal capacitance 1 μF

Table 83. LDO2

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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13.12 LDO3

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VLDO3 = 1.8 V, CINL1 = 4.7 μF, COUT = 2.2 μF, Tamb=

-40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

VIN Input voltage range INL1 2.85 5.5 V

IShutdown Shutdown current Regulator disabled, VIN = 5.0 V 0.1 μA

IQQuiescent current Regulator enabled, No load 15 μA

IOUT_MAX

Maximum Output DC

Current VIN > 2.8 V, VLDO3 = 1.8 V 300 mA

ILIMIT Short Current Limit Output shorted to GND 310 480 mA

VDO Dropout Voltage IOUT = IOUT_MAX, VIN = 3.2 V,

L3_OUT[4:0] = 0x1F, 3.3 V 70 100 mV

Nominal output voltage I2C Programmable, 100 mV step 0.8 3.3 V

Default voltage 1.8 VVLDO3

DC accuracy VLDO3 = 1.8 V, ILoad = 5 mA -3 3 %

VNOISE Output noise f = 10 Hz to 10 kHz, IOUT = 10 % of

IMAX, VLDO3 = 1.8 V 150 μV

ΔVOUT(ΔVINL) DC Line regulation VLDO3 +0.3 V < VIN < 5.5 V,

IOUT(LDO3) = 10 % of IOUT_MAX

0.2 0.5 %/V

ΔVOUT(ΔIOUT) DC Load regulation VIN = VLDO3 +0.3 V to 5.5 V,

0 mA < IOUT < IOUT_MAX

0.6 %

ΔVOUT(ΔVINL)

[1] Transient Line

Response

VLDO3 +0.3 V < VIN < 5.5 V,

IOUT(LDO3) = 10 % of IOUT_MAX, tr =

10 μs

0.5 %/V

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

VIN = VLDO3 +0.3 V to 5.5 V,

1 mA < IOUT < IOUT_MAX , tr = 10 μs,

VLDO3 = 1.8 V, Tamb= 25 °C

-3 3 %

PSRR[1] Power Supply Rejection

ratio

f = 10 Hz to 10 kHz, IOUT = 10 % of

IOUT_MAX

55 dB

Vsoft_strup

[1] Soft-start slew rate IOUT = 0 mA, 10 % to 90 % of

VLDO3

15 mV/μs

Vov_srtup

[1] Overshoot at startup IOUT = 0 mA 10 mV

tEN

[1] Enable time EN rising to 90 % of output voltage 150 μs

POK Output Power good Percentage of VLDO3 configuration 75 85 92 %

RDIS

Active Discharge

Resistance 100 150 Ω

COUT

[1] Output capacitance Minimum nominal capacitance 2.2 μF

Table 84. LDO3

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.13 LDO4

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VLDO4 = 0.9 V, CINL1 = 4.7 μF, COUT = 1 μF, Tamb=

-40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

VIN Input voltage range INL1 2.85 5.5 V

IShutdown Shutdown current Regulator disabled, VIN = 5.0 V 0.1 μA

IQQuiescent current Regulator enabled, No load 15 μA

IOUT_MAX

Maximum Output DC

Current VIN > 2.8, VLDO4 = 0.9 V 200 mA

ILIMIT Short Current Limit Output shorted to GND 210 330 mA

VDO Dropout Voltage IOUT = IOUT_MAX, VIN = 3.2 V,

L4_OUT[4:0] = 0x1F, 3.3 V 60 100 mV

Nominal output voltage I2C Programmable, 100 mV step 0.8 3.3 V

Default voltage 0.9 VVLDO4

DC accuracy VLDO4 = 0.9 V, ILoad = 5 mA -3 3 %

VNOISE Output noise f = 10 Hz to 10 kHz, IOUT = 10 % of

IMAX, VLDO4 = 0.9 V 150 μV

ΔVOUT(ΔVINL) DC Line regulation VLDO4 +0.3 V < VIN < 5.5 V,

IOUT(LDO4) = 10 % of IOUT_MAX

0.2 0.5 %/V

ΔVOUT(ΔIOUT) DC Load regulation VIN = VLDO4 +0.3 V to 5.5 V,

0 mA < IOUT < IOUT_MAX

0.9 %

ΔVOUT(ΔVINL)

[1] Transient Line Response

VLDO4 +0.3 V < VIN < 5.5 V,

IOUT(LDO4) = 10 % of IOUT_MAX, tr =

10 μs

0.5 %/V

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

VIN = VLDO4 +0.3 V to 5.5 V,

1 mA < IOUT < IOUT_MAX , tr = 10 μs,

VLDO4 = 0.9 V, Tamb= 25 °C

-4 4 %

PSRR[1] Power Supply Rejection

ratio

f = 10 Hz to 10 kHz, IOUT = 10 % of

IOUT_MAX

60 dB

Vsoft_strup

[1] Soft-start slew rate IOUT = 0 mA, 10 % to 90 % of VLDO4 20 mV/μs

Vov_srtup

[1] Overshoot at startup IOUT = 0 mA 10 mV

tEN

[1] Enable time EN rising to 90 % of output voltage 100 μs

POK Output Power good Percentage of VLDO4 configuration 75 85 92 %

RDIS

Active Discharge

Resistance 100 150 Ω

COUT

[1] Output capacitance Minimum nominal capacitance 1 μF

Table 85. LDO4

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.14 LDO5

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VLDO5 = 3.3 V, CINL1 = 4.7 μF, COUT = 1 μF, Tamb=

-40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

INL1 pin 2.85 5.5 V

VIN Input voltage range INL1 pin, when VLDO5 = 3.3 V VLDO5 +

VDO

5.5 V

IShutdown Shutdown current Regulator disabled, VIN = 5.0 V 0.1 μA

IQQuiescent current Regulator enabled, No load 15 μA

IOUT_MAX

Maximum Output DC

Current

VIN > VLDO5 + VDO(MAX), VLDO5 =

3.3 V 150 mA

ILIMIT Short Current Limit Output shorted to GND 160 280 mA

VDO Dropout Voltage IOUT = IOUT_MAX, VIN = 3.2 V,

L5_OUT_L[3:0] = 0xF, 3.3 V 50 100 mV

Nominal output voltage I2C Programmable, 100 mV step 1.8 3.3 V

SD_VSEL = Low 3.3 V

Default voltage SD_VSEL = High 1.8 V

VLDO5

DC accuracy VLDO5 = 1.8 V, ILoad = 5 mA -3 3 %

VNOISE Output noise f = 10 Hz to 10 kHz, IOUT = 10 % of

IMAX, VLDO5 = 3.3 V 300 μV

ΔVOUT(ΔVINL) DC Line regulation VLDO5 +0.3 V < VIN < 5.5 V,

IOUT(LDO5) = 10 % of IOUT_MAX

0.2 0.5 %/V

ΔVOUT(ΔIOUT) DC Load regulation VIN = VLDO5 +0.3 V to 5.5 V,

0 mA < IOUT < IOUT_MAX

0.3 %

ΔVOUT(ΔVINL)

[1] Transient Line

Response

VLDO5 +0.3 V < VIN < 5.5 V,

IOUT(LDO5) = 10 % of IOUT_MAX

0.5 %/V

ΔVOUT(ΔIOUT)

[1] Transient Load

Response

VIN = VLDO5 +0.3 V to 5.5 V,

1 mA < IOUT < IOUT_MAX , tr = 10 μs,

VLDO5 = 3.3 V, Tamb= 25 °C

-3 3 %

PSRR[1] Power Supply Rejection

ratio

f = 10 Hz to 10 kHz, IOUT = 10 % of

IOUT_MAX

50 dB

Vsoft_strup

[1] Soft-start slew rate IOUT = 0 mA, 10 % to 90 % of VLDO5 15 mV/μs

Vov_srtup

[1] Overshoot at startup IOUT = 0 mA 10 mV

tEN

[1] Enable time EN rising to 90 % of output voltage 200 μs

POK Output Power good Percentage of VLDO5 configuration 75 85 92 %

RDIS

Active Discharge

Resistance 100 150 Ω

COUT

[1] Output capacitance Minimum nominal capacitance 1 μF

Table 86. LDO5

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.15 Load SW

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VSWIN = 3.8 V, CSWIN = CSWOUT = 1 μF, Tamb= -40 °C

~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

VSWIN Input voltage range SWIN 2.8 5.5 V

IQQuiescent current Switch enabled, No load, VSWIN =

3.3 V 5 8 μA

ISHDN Shut down current SWEN = 0 V, VSWIN = 3.3 V 1 2.5 μA

IOC

[1] OverCurrent Threshold 450 800 mA

ISC

[1] Short circuit current

threshold 2 A

RDSON Switch ON resistance VSWIN = 3.3 V, ILOAD = 200 mA,

including bonding wire resistance 150 210 mΩ

tEN

[1] Enable time Time to SWOUT 10 % from EN pin

high, VSWIN = 3.3 V 90 120 μs

tON

[1] Output rise time CL = 10 μF, VSWIN = 3.3 V, SWOUT

10 % to 90 % 200 500 μs

RDIS

Active Discharge

Resistance SWEN = 0 V 80 120 Ω

Table 87. Load SW

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.16 32 kHz Xtal driver

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8, Tamb= -40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

fOSC_32K Clock frequency Internal Oscillator 29 32.77 36 kHz

fCLK

[1] Clock frequency External 32.768 kHz crystal

oscillator 32.768 kHz

tRTCSTB

[1] Oscillator stabilization

time 1000 ms

Duty[1] Output Duty cycle External 32.768 kHz crystal

oscillator 30 50 70 %

VOL Output Low level IOL = 1 mA 0.4 V

VOH Output High level VLDO1 = 1.8 V, IOL = 1 mA 1.6 V

Table 88. 32 kHz Xtal driver

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.17 I2C-bus interface and logic I/O

Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8, Tamb= -40 °C ~ +105 °C

Symbol Parameter Conditions Min Typ Max Unit

SCL, SDA

fI2C I2C Clock frequency - - 1 MHz

VIH High-level Input voltage SCL, SDA; VSYS= 3.0 V to 5.5 V 1.2 - - V

VIL Low-level Input voltage SCL, SDA; VSYS= 3.0 V to 5.5 V - - 0.4 V

Vhys

Hysteresis of Schmitt

trigger inputs 0.01 - - V

VOL Low-level output voltage SDA, Iload = 20 mA, VSYS = 3.0 V

to 5.5 V 0 - 0.4 V

tHD,STA

[1] Hold time (repeated)

START condition

Fast mode plus; After this period,

the

first clock pulse is generated

0.26 - - µs

tLOW

[1] LOW period of I2C clock Fast mode plus 0.5 - - µs

tHIGH

[1] HIGH period of I2C clock Fast mode plus 0.26 - - µs

tSU,STA

[1] Setup time (repeated)

START condition Fast mode plus 0.26 - - µs

tHD,DAT

[1] Data Hold time Fast mode plus 0 - - µs

tSU,DAT

[1] Data Setup time Fast mode plus 50 - - ns

tr [1]

Rise time of I2C_SCL

and

I2C_SDA signals

Fast mode plus - - 120 ns

tf [1] Fall time of I2C_SCL and

I2C_SDA signals Fast mode plus - - 120 ns

tSU,STO

[1] Setup time for STOP

condition Fast mode plus 0.26 - - µs

tBUF

[1] Bus free time between

STOP and START

condition

Fast mode plus 0.5 - - µs

tVD,DAT

[1] Data valid time Fast mode plus - 0.45 µs

tVD,ACK

[1] Data valid acknowledge

time Fast mode plus - 0.45 µs

tSP

[1] Pulse width of spikes that

must be suppressed by

input filter

0 - 50 ns

Table 89. I2C-bus interface and logic I/O

[1] Guaranteed by design

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

14 Package outline

Figure 26. Package outline HVQFN56 (SOT949-6)

Product data sheet Rev. 2.1 — 7 December 2020

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Power management IC for i.MX 8M application processor family

Figure 27. Package outline HVQFN56 (SOT949-6)

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Figure 28. PCB Design Guidelines – Solder Mask Opening Pattern

Product data sheet Rev. 2.1 — 7 December 2020

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Power management IC for i.MX 8M application processor family

Figure 29. PCB Design Guidelines - I/O PADS AND SODERABLE AREA

Product data sheet Rev. 2.1 — 7 December 2020

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Power management IC for i.MX 8M application processor family

Figure 30. PCB Design Guidelines – Solder Paste Stencil

Product data sheet Rev. 2.1 — 7 December 2020

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Power management IC for i.MX 8M application processor family

15 Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9450 v2.1 20201207 Product data sheet - PCA9450 v2.0

Modifications: •Table 3: Updated description for pin 22 SWIN

•Table 20: Device_ID Register “Reset Value” changed from “0x10” to “0x11”

•Table 21: RSVD bit changed from “0000” to “0001”

PCA9450 v2.0 20200924 Product data sheet - PCA9450 v1.0

Modifications: •Replaced "PCA9450A" with "PCA9450AA" throughout

•Table 79: Added POK information

•Table 86: Updated conditions for VIN and IOUT_MAX

•Figure 1: Corrected LDO3 capacitor value; added footnote

•Figure 21, Figure 22: Added footnote

•Figure 23: Corrected LDO2, added footnote

•Figure 5: Corrected VINT

•Section 7.3.7: Corrected paragraph 1

•Section 9.2.1.1: Corrected equations (1) and (2)

PCA9450 v1.0 20191119 Product data sheet - -

Table 90. Revision history

Product data sheet Rev. 2.1 — 7 December 2020

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Power management IC for i.MX 8M application processor family

16 Legal information

16.1 Data sheet status

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product

development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

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of any products or rework charges) whether or not such damages are based

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legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

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Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Product data sheet Rev. 2.1 — 7 December 2020

94 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Tables

Tab. 1. Ordering information ..........................................4

Tab. 2. Ordering options ................................................4

Tab. 3. Pin description ...................................................6

Tab. 4. PCA9450 selection guide ................................10

Tab. 5. SNVS mode .................................................... 12

Tab. 6. PWRUP mode .................................................14

Tab. 7. Power modes summary .................................. 15

Tab. 8. tFLT_THSD ......................................................17

Tab. 9. tFLT_SD_WAIT ................................................19

Tab. 10. 0x08 – RESET_CTRL ..................................... 20

Tab. 11. 0x06 – SW_RST ............................................. 20

Tab. 12. tRESTART ....................................................... 21

Tab. 13. tRESET ............................................................22

Tab. 14. PCA9450AA Regulator Control summary ........22

Tab. 15. PCA9450B/PCA9450C Regulator Control

summary ..........................................................23

Tab. 16. PCA9450AA Buck Summary ...........................24

Tab. 17. PCA9450C Buck Summary .............................24

Tab. 18. LDO summary ................................................. 26

Tab. 19. PCA9450 I2C Slave Address .......................... 30

Tab. 20. Register map ...................................................31

Tab. 21. 0x00 Device_ID ...............................................34

Tab. 22. 0x01 INT1 ........................................................34

Tab. 23. 0x02 INT1_MSK .............................................. 35

Tab. 24. 0x03 STATUS1 ................................................35

Tab. 25. 0x04 STATUS2 ................................................36

Tab. 26. 0x05 PWRON_STAT ....................................... 37

Tab. 27. 0x06 SW_RST ................................................ 37

Tab. 28. 0x07 PWR_CTRL ............................................37

Tab. 29. 0x08 RESET_CTRL ........................................ 38

Tab. 30. 0x09 CONFIG1 ............................................... 39

Tab. 31. 0x0A CONFIG2 ............................................... 39

Tab. 32. 0x0C BUCK123_DVS ......................................40

Tab. 33. 0x0D BUCK1OUT_LIMIT ................................ 40

Tab. 34. 0x0E BUCK2OUT_LIMIT ................................ 40

Tab. 35. 0x0F BUCK3OUT_LIMIT .................................41

Tab. 36. 0x10 BUCK1CTRL .......................................... 41

Tab. 37. 0x11 BUCK1OUT_DVS0 ................................. 42

Tab. 38. 0x12 BUCK1OUT_DVS1 .................................42

Tab. 39. 0x13 BUCK2CTRL .......................................... 42

Tab. 40. 0x14 BUCK2OUT_DVS0 .................................43

Tab. 41. 0x15 BUCK2OUT_DVS1 .................................43

Tab. 42. 0x16 BUCK3CTRL .......................................... 43

Tab. 43. 0x17 BUCK3OUT_DVS0 .................................44

Tab. 44. 0x18 BUCK3OUT_DVS1 .................................44

Tab. 45. BUCK1, BUCK2, BUCK3 Output voltage

table .................................................................45

Tab. 46. 0x19 BUCK4CTRL .......................................... 46

Tab. 47. 0x1A BUCK4OUT ............................................46

Tab. 48. 0x1B BUCK5CTRL ..........................................46

Tab. 49. 0x1C BUCK5OUT ........................................... 47

Tab. 50. 0x1D BUCK6CTRL ..........................................47

Tab. 51. 0x1E BUCK6OUT ............................................47

Tab. 52. BUCK4, BUCK5, BUCK6 Output voltage

table .................................................................48

Tab. 53. 0x20 LDO_AD_CTRL ......................................49

Tab. 54. 0x21 LDO1CTRL .............................................49

Tab. 55. 0x22 LDO2CTRL .............................................50

Tab. 56. 0x23 LDO3CTRL .............................................51

Tab. 57. LDO3 output voltage ....................................... 51

Tab. 58. 0x24 LDO4CTRL .............................................51

Tab. 59. LDO4 output voltage ....................................... 51

Tab. 60. 0x25 LDO5CTRL_L .........................................52

Tab. 61. LDO5 output voltage when SD_VSEL =

Low .................................................................. 52

Tab. 62. 0x26 LDO5CTRL_H ........................................ 52

Tab. 63. LDO5 output voltage when SD_VSEL =

High ................................................................. 52

Tab. 64. 0x2A LOADSW_CTRL .................................... 53

Tab. 65. 0x2B VRFLT1_STS ......................................... 53

Tab. 66. 0x2C VRFLT2_STS .........................................54

Tab. 67. 0x2D VRFLT1_MASK ......................................55

Tab. 68. 0x2E VRFLT2_MASK ......................................55

Tab. 69. Tested inductor list .......................................... 61

Tab. 70. Limiting values ................................................ 66

Tab. 71. Recommended Operating Conditions ............. 67

Tab. 72. Thermal characteristics ................................... 68

Tab. 73. Top level parameter ........................................ 69

Tab. 74. I2C level translator .......................................... 72

Tab. 75. BUCK1 (PCA9450AA/PCA9450B) .................. 73

Tab. 76. Dual Phase BUCK1 (PCA9450C) ................... 74

Tab. 77. BUCK2 .............................................................75

Tab. 78. BUCK3 (PCA9450AA) .....................................76

Tab. 79. BUCK4 .............................................................77

Tab. 80. BUCK5 .............................................................78

Tab. 81. BUCK6 .............................................................79

Tab. 82. LDO1 ............................................................... 80

Tab. 83. LDO2 ............................................................... 81

Tab. 84. LDO3 ............................................................... 82

Tab. 85. LDO4 ............................................................... 83

Tab. 86. LDO5 ............................................................... 84

Tab. 87. Load SW ......................................................... 85

Tab. 88. 32 kHz Xtal driver ........................................... 86

Tab. 89. I2C-bus interface and logic I/O ........................87

Tab. 90. Revision history ...............................................93

Product data sheet Rev. 2.1 — 7 December 2020

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NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Figures

Fig. 1. Block diagram ................................................... 5

Fig. 2. PCA9450 pin map – Top View .......................... 6

Fig. 3. PCA9450 functional block diagram ................. 10

Fig. 4. Power States Diagram .................................... 11

Fig. 5. SNVS mode ON/OFF sequence ..................... 12

Fig. 6. PCA9450AA power ON/OFF sequence .......... 13

Fig. 7. PCA9450B/C power ON/OFF sequence ......... 14

Fig. 8. PCA9450AA mode transition ...........................15

Fig. 9. PCA9450 FAULT_SD from Thermal

shutdown ......................................................... 17

Fig. 10. PCA9450 Fault event ...................................... 18

Fig. 11. PCA9450 FAULT_SD from VR Fault except

LDO1/LDO2 in RUN/STANDBY ...................... 19

Fig. 12. PCA9450AA Cold reset ...................................21

Fig. 13. Warm reset ......................................................22

Fig. 14. DVS functional diagram .................................. 25

Fig. 15. DVS timing ...................................................... 25

Fig. 16. BUCK1/3 configuration ....................................26

Fig. 17. 32 kHz Crystal oscillator driver block

diagram ............................................................27

Fig. 18. Load switch internal block diagram ................. 27

Fig. 19. Architecture of I2C Level translator (One

channel) ...........................................................28

Fig. 20. Interrupt diagram ............................................. 29

Fig. 21. PCA9450AA application schematic ................. 58

Fig. 22. PCA9450B application schematic ................... 59

Fig. 23. PCA9450C application schematic ................... 60

Fig. 24. Crystal oscillator ..............................................63

Fig. 25. PCA9450 layout .............................................. 65

Fig. 26. Package outline HVQFN56 (SOT949-6) ......... 88

Fig. 27. Package outline HVQFN56 (SOT949-6) ......... 89

Fig. 28. PCB Design Guidelines – Solder Mask

Opening Pattern .............................................. 90

Fig. 29. PCB Design Guidelines - I/O PADS AND

SODERABLE AREA ........................................91

Fig. 30. PCB Design Guidelines – Solder Paste

Stencil ..............................................................92

Product data sheet Rev. 2.1 — 7 December 2020

97 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

Contents

1 General description ............................................ 1

2 Features and benefits .........................................2

3 Applications .........................................................3

4 Ordering information .......................................... 4

5 Block diagram ..................................................... 5

6 Pinning information ............................................ 6

6.1 Pinning ............................................................... 6

6.2 Pin description ................................................... 6

7 Functional description ........................................9

7.1 Features .............................................................9

7.2 Functional diagram .......................................... 10

7.3 Power modes ...................................................11

7.3.1 Off mode ..........................................................11

7.3.2 READY mode .................................................. 11

7.3.3 SNVS mode .....................................................11

7.3.4 PWRUP mode ................................................. 12

7.3.5 PWRDN mode ................................................. 14

7.3.6 RUN mode .......................................................14

7.3.7 STANDBY mode .............................................. 15

7.3.8 FAULT_SD ....................................................... 16

7.4 PMIC reset .......................................................20

7.5 Regulator control in each power mode ............ 22

7.6 Regulator summary ......................................... 23

7.6.1 BUCK regulator ............................................... 23

7.6.1.1 Dynamic voltage scaling ..................................24

7.6.1.2 BUCK output voltage limiting ...........................25

7.6.1.3 Dual-phase configuration .................................25

7.6.2 LDO and load switch ....................................... 26

7.7 32 kHz Crystal Oscillator Driver .......................26

7.8 Load switch ......................................................27

7.9 I2C level translator .......................................... 27

7.10 Interrupt management ..................................... 28

8 Software interface ............................................. 30

8.1 Register map ................................................... 31

8.2 Register details ................................................34

8.2.1 0x00 Device_ID ............................................... 34

8.2.2 0x01 INT1 ........................................................ 34

8.2.3 0x02 INT1_MSK .............................................. 35

8.2.4 0x03 STATUS1 ................................................ 35

8.2.5 0x04 STATUS2 ................................................ 36

8.2.6 0x05 PWRON_STAT ........................................36

8.2.7 0x06 SW_RST .................................................37

8.2.8 0x07 PWR_CTRL ............................................ 37

8.2.9 0x08 RESET_CTRL .........................................38

8.2.10 0x09 CONFIG1 ................................................ 39

8.2.11 0x0A CONFIG2 ............................................... 39

8.2.12 0x0C BUCK123_DVS ...................................... 40

8.2.13 0x0D BUCK1OUT_LIMIT .................................40

8.2.14 0x0E BUCK2OUT_LIMIT ................................. 40

8.2.15 0x0F BUCK3OUT_LIMIT ................................. 41

8.2.16 0x10 BUCK1CTRL ...........................................41

8.2.17 0x11 BUCK1OUT_DVS0 ................................. 42

8.2.18 0x12 BUCK1OUT_DVS1 ................................. 42

8.2.19 0x13 BUCK2CTRL ...........................................42

8.2.20 0x14 BUCK2OUT_DVS0 ................................. 43

8.2.21 0x15 BUCK2OUT_DVS1 ................................. 43

8.2.22 0x16 BUCK3CTRL ...........................................43

8.2.23 0x17 BUCK3OUT_DVS0 ................................. 44

8.2.24 0x18 BUCK3OUT_DVS1 ................................. 44

8.2.25 0x19 BUCK4CTRL ...........................................45

8.2.26 0x1A BUCK4OUT ............................................ 46

8.2.27 0x1B BUCK5CTRL .......................................... 46

8.2.28 0x1C BUCK5OUT ............................................47

8.2.29 0x1D BUCK6CTRL .......................................... 47

8.2.30 0x1E BUCK6OUT ............................................ 47

8.2.31 0x20 LDO_AD_CTRL ...................................... 49

8.2.32 0x21 LDO1CTRL ............................................. 49

8.2.33 0x22 LDO2CTRL ............................................. 50

8.2.34 0x23 LDO3CTRL ............................................. 50

8.2.35 0x24 LDO4CTRL ............................................. 51

8.2.36 0x25 LDO5CTRL_L ......................................... 52

8.2.37 0x26 LDO5CTRL_H .........................................52

8.2.38 0x2A LOADSW_CTRL .....................................53

8.2.39 0x2B VRFLT1_STS ......................................... 53

8.2.40 0x2C VRFLT2_STS ......................................... 54

8.2.41 0x2D VRFLT1_MASK ...................................... 55

8.2.42 0x2E VRFLT2_MASK ...................................... 55

9 Application design-in information ................... 57

9.1 Reference schematic ....................................... 57

9.1.1 PCA9450AA reference schematic ................... 57

9.1.2 PCA9450B reference schematic ......................59

9.1.3 PCA9450C reference schematic ..................... 60

9.2 Typical application ........................................... 61

9.2.1 Buck regulators ................................................61

9.2.1.1 Inductor selection for buck converters ............. 61

9.2.1.2 Output capacitor selection for buck

converters ........................................................ 62

9.2.1.3 Input capacitor selection for buck

converters ........................................................ 62

9.2.2 Crystal oscillator .............................................. 62

9.2.2.1 Crystal selection .............................................. 62

9.2.2.2 Effective load capacitance ............................... 63

9.2.2.3 Frequency tuning .............................................64

9.3 Layout guide .................................................... 64

10 Limiting values .................................................. 66

11 Recommended operating conditions .............. 67

12 Thermal characteristics ....................................68

13 Electrical characteristics ..................................69

13.1 Top level parameter .........................................69

13.2 I2C level translator .......................................... 72

13.3 BUCK1 (PCA9450AA/PCA9450B) ...................73

13.4 Dual Phase BUCK1 (PCA9450C) ....................74

13.5 BUCK2 ............................................................. 75

13.6 BUCK3 (PCA9450AA) ..................................... 76

13.7 BUCK4 ............................................................. 77

13.8 BUCK5 ............................................................. 78

13.9 BUCK6 ............................................................. 79

13.10 LDO1 ................................................................80

13.11 LDO2 ................................................................81

13.12 LDO3 ................................................................82

13.13 LDO4 ................................................................83

13.14 LDO5 ................................................................84

Product data sheet Rev. 2.1 — 7 December 2020

98 / 99

NXP Semiconductors PCA9450

Power management IC for i.MX 8M application processor family

13.15 Load SW ..........................................................85

13.16 32 kHz Xtal driver ............................................ 86

13.17 I2C-bus interface and logic I/O ........................ 87

14 Package outline .................................................88

15 Revision history ................................................ 93

16 Legal information .............................................. 94

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 December 2020

Document identifier: PCA9450