PCA9450 Power management IC for i.MX 8M application processor family Rev. 2.1 -- 7 December 2020 1 Product data sheet General description PCA9450 is a single chip Power Management IC (PMIC) specifically designed to support i.MX 8M family processor in both 1 cell Li-Ion and Li-polymer battery portable application and 5 V adapter non-portable applications. It supports various memory types (DDR4/LPDDR4/DDR3L, etc.) via system UBOOT configuration, which does not require hardware change. The device provides six high efficiency step-down regulators, five LDOs, one 400 mA load switch, 2-channel level translator and 32.768 kHz crystal oscillator driver. Three buck regulators support Dynamic Voltage Scaling (DVS) feature along with programmable ramping up and down time and those buck regulators support remote sense to compensate IR drop to load from buck regulator. This device is characterized across -40 C to 105 C ambient temperature range. Six step-down regulators are designed to provide power for i.MX 8M application processor and DRAM memory. Two LDOs, LDO1 and LDO2, feature very low quiescent current to provide power for Secure Non-Volatile Storage (SNVS) since these LDOs are always ON when input voltage is valid. PCA9450 integrates logic translator which is a 2-bit, dual supply translating transceiver with auto direction sensing. It enables bidirectional voltage level translation. It can be 2 used as I C level translator. 400 mA load switch is to supply 3.3 V power supply to SD card, which has internal discharge resistor. PCA9450 has three versions: PCA9450AA is companion PMIC for (i.MX 8M Mini), PCA9450B is companion PMIC for i.MX 8M Nano and PCA9450C is companion PMIC for i.MX 8M Plus. The PCA9450 is offered in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch. PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 2 Features and benefits * Six high-efficiency step-down regulators - Three 3 A buck regulators with DVS feature and remote sense - PCA9450AA - Three 3 A buck regulators - PCA9450B - Two 3 A buck regulators - PCA9450C - 6 A dual-phase buck regulator and 3 A buck regulator * One 3 A buck regulator * Two 2 A buck regulators * Five linear regulators - Two 10 mA LDOs - One 150 mA LDO - One 200 mA LDO - One 300 mA LDO * Support various memory types: DDR4/LPDDR4/DDR3L via system UBOOT configuration, no hardware change required * 400 mA load switch with built-in active discharge resistor * 32.768 kHz crystal oscillator driver and buffer output * Two channel logic level translator * Power control IO - Power ON/OFF control - Standby/run mode control 2 * Fm+ 1 MHz I C-bus interface * ESD protection - Human Body Model (HBM) : +/- 2000 V - Charged Device Model (CDM) : +/-500 V * 7 mm x 7 mm, 56-pin HVQFN with 0.4 mm pitch PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 2 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 3 Applications * * * * PCA9450 Product data sheet IoT Devices Tablet Electronic Point of Sale (ePOS) Industrial application All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 3 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 4 Ordering information Table 1.Ordering information Type number Topside marking AP platform PCA9450AAHN PCA9450AA PCA9450BHN PCA9450CHN Package Name Description Version i.MX 8M Mini HVQFN56 thermal enhanced very thin quad flat package; no leads; 56 terminals; 0.4 mm pitch, 7 mm x 7 mm x 0.85 mm body SOT949-6 PCA9450B i.MX 8M Nano HVQFN56 thermal enhanced very thin quad flat package; no leads; 56 terminals; 0.4 mm pitch, 7 mm x 7 mm x 0.85 mm body SOT949-6 PCA9450C i.MX 8M Plus HVQFN56 thermal enhanced very thin quad flat package; no leads; 56 terminals; 0.4 mm pitch, 7 mm x 7 mm x 0.85 mm body SOT949-6 Table 2.Ordering options Type number Orderable part number Package Packing method Minimum order Temperature range quantity PCA9450AAHN PCA9450AAHNY HVQFN56 REEL 13" Q1 DP 2000 -40 C to +105 C PCA9450BHN PCA9450BHNY HVQFN56 REEL 13" Q1 DP 2000 -40 C to +105 C PCA9450CHN PCA9450CHNY HVQFN56 REEL 13" Q1 DP 2000 -40 C to +105 C PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 4 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 5 Block diagram VSYS SYS 1 F VINT PCA9450 INT LDO 1 F INB26 DVS SBIAS, REF, UVLO, TSHDN 10 F LX2 BUCK2 0.85 V 3A LDO1 PMIC_RST_B VSYS 0.47 H VDD_ARM (1) 22 F PGND R_SNSP2 PMIC_ON_REQ PMIC_STBY_REQ INB13 DVS 10 F LX1 WDOG_B NVCC_SNVS LDO1 LDO1 BUCK1 0.85 V 3A 100 k RTC_RESET_B DUAL PHASE CONFIG IN PCA9450C POR_B NVCC_1V8 BUCK5 4.7 k 4.7 k VDD_SOC (1) 22 F PGND R_SNSP1 INB13 DVS 10 F 100 k LX3 SCL l2C INTERFACE SDA VSYS 0.47 H BUCK3 0.85 V 3A IRQ_B VSYS VDD_V/GPU VDD_DRAM 0.47 H (1) 22 F PGND R_SNSP3_CFG NVCC_1V8 BUCK5 VINT 4.7 k INB45 SCLL SDAL 3V3 V BUCK4 4.7 k SWIN 4.7 k l2C LEVEL TRANSLATOR ON/OFF CONTROL AND I2C REGISTER 4.7 k SDAH VSYS 10 F LX4 BUCK4 3.3 V 3A 0.47 H NVCC_3V3 22 F PGND BUCK4FB SCLH XTAL_IN X-tal INB45 32.768 kHz X-TAL DRIVER XTAL_OUT VSYS 4.7 F 0.47 H LX5 LDO1 CLK_32K_OUT BUCK5 1.8 V 2A MUX INL1 SYS 4.7 F NVCC_SNVS LDO1 1 F VDD_SNVS LDO2 1 F VDDA _1V8 VDD_PHY_0V9 LDO4 LDO4 0.9 V 200 mA 1 F NVCC_SD2 LDO5 1 F PGND BUCK5FB INB26 VSYS 4.7 F LX6 LDO2 0.85 V 10 mA LDO3 1.8 V 300 mA 2.2 F 22 F LDO1 1.8 V 10 mA LDO3 NVCC_1V8 0.47 H NVCC_DRAM BUCK6 1.1 V 2A 22 F PGND BUCK6FB SWIN LOAD SW DRIVER 1 F SWOUT BUCK 4 SD_CARD 1 F LDO5 3.3 V/1.8 V 150 mA SW_EN SD_VSEL AGND EP aaa-035069 (1) This capacitor is decoupling capacitor in MCU side. Figure 1.Block diagram PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 5 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 6 Pinning information 6.1 Pinning INL1 LDO5 LDO3 VSYS BUCK6FB LX6 LX6 INB26 INB26 INB26 LX2 LX2 R_SNSP2 BUCK_AGND 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PCA9450 LDO4 1 42 SDA LDO2 2 41 SCL LDO1 3 40 PMIC_STBY_REQ VINT 4 39 PMIC_ON_REQ AGND 5 38 R_SNSP1 RTC_RESET_B 6 37 LX1 CLK_32K_OUT 7 36 LX1 PMIC_RST_B 8 35 INB13 POR_B 9 34 INB13 EP 22 23 24 25 26 27 28 SWIN SWOUT SDAH SCLH SDAL SCLL WDOG_B 21 SD_VSEL 20 29 LX4 14 BUCK4FB BUCK5FB 19 R_SNSP3_CFG 18 LX3 30 LX4 31 13 INB45 12 IRQ_B 17 SW_EN 16 LX3 INB45 INB13 32 INB45 33 11 15 10 LX5 XTAL_IN XTAL_OUT aaa-035701 Figure 2.PCA9450 pin map - Top View 6.2 Pin description Table 3.Pin description Pin description PCA9450 Product data sheet Symbol Pin Type Description LDO4 1 P LDO4 output. Bypass with a 1 F to Ground. LDO2 2 P LDO2 output. Bypass with a 1 F to Ground. LDO1 3 P LDO1 output. Bypass with a 1 F to Ground. VINT 4 P Internal Power supply output pin. Bypass with 1 F to Ground. AGND 5 GND Analog ground pin. It should be connected to ground plane through Via. Do not short to EP directly on top layer All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 6 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 3.Pin description...continued Pin description PCA9450 Product data sheet Symbol Pin Type Description RTC_RESET_B 6 DO Reset output pin. It is High-Z after both LDO1 and LDO2 voltage are good. It is internally pulled up with LDO1 power rail CLK_32K_OUT 7 DO 32.768 kHz clock CMOS output with LDO1 power rail. PMIC_RST_B 8 DI PMIC reset input pin. It is internally pulled up with LDO1 power rail. Once it is asserted low, PMIC performs reset. POR_B 9 DO Power On reset output pin. Open drain output requiring external pull up resistor. XTAL_IN 10 AI 32.768 kHz crystal oscillator input, tie to GND if X-tal is not used XTAL_OUT 11 AO 32.768 kHz crystal oscillator output, leave floating if Xtal is not used SW_EN 12 DI Load switch enable input pin. It has internal 1.5 M pull down resistor. IRQ_B 13 DO Open drain output to indicate Interrupt issued. It requires external pull up resistor. BUCK5FB 14 AI BUCK5 output voltage sensing pin. If BUCK5 is not used, tie to INB45. LX5 15 P BUCK5 switching node. If BUCK5 is not used, leave it floating. INB45 16,17,18 P BUCK4 / BUCK5 Input pins. Bypass with 10 F and 4.7 F to Ground LX4 19,20 P BUCK4 switching node. If BUCK4 is not used, leave them floating. BUCK4FB 21 AI BUCK4 output voltage sensing pin. If BUCK4 is not used, tie to INB45. SWIN 22 P Load switch input pin. Bypass with a 1 F to Ground. Leave it floating if not used (must connect to BUCK4, 2 3.3 V, if I C level translator is used). SWOUT 23 P Load switch output pin. Bypass with a 1 F to Ground. Leave it floating if not used. SDAH 24 DIO Level translator high voltage IO pin, SDA referenced to SWIN, 3.3 V SCLH 25 DO Level translator high voltage IO pin, SCL referenced to SWIN, 3.3 V SDAL 26 DIO Level translator low voltage IO pin, SDA referenced to VINT, 1.8 V SCLL 27 DO Level translator low voltage IO pin, SCL referenced to VINT, 1.8 V WDOG_B 28 DI Active low watchdog reset input pin from application processor. All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 7 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 3.Pin description...continued Pin description Symbol Pin Type Description SD_VSEL 29 DI LDO5 voltage selection input pin. LDO5 output is 3.3 V when it is driven low and 1.8 V when driven high. VSEL pin should be tied low or high. Do not leave it floating. R_SNSP3_CFG 30 AI BUCK3 output voltage remote sense pin in PCA9450AA. Logic input pin in PCA9450B/C. This pin should be tied to SYS in PCA9450B, where BUCK3 is disabled. This pin is tied to GND in PCA9450C, where BUCK1 and BUCK3 are configured as dual phase buck regulator. LX3 31,32 P BUCK3 switching node If BUCK3 is not used by shorting R_SNSP3_CFG to VSYS, leave LX3 pins floating. INB13 33,34,35 P BUCK1 / BUCK3 Input. Bypass with two 10 F to Ground LX1 36,37 P BUCK1 switching node. Leave it floating if not used. R_SNSP1 38 AI BUCK1 output voltage remote sensing pin. Tie to INB13 if not used. PMIC_ON_REQ 39 DI PMIC ON input from Application processor. When it is asserted high, the device starts power on sequence. PMIC_STBY_REQ 40 DI Standby mode input from Application processor. When it is asserted high, device enters STANDBY mode. SCL 41 DI I2C serial clock pin SDA 42 DIO I2C serial data pin BUCK_AGND 43 GND Buck reference GND for BUCK1,2,3. It should be connected to ground plane through Via. Do not short to EP directly on top layer R_SNSP2 44 AI BUCK2 output voltage remote sensing pin. Tie to INB26 if not used. LX2 45,46 P BUCK2 switching node. Leave them floating if not used. INB26 47,48,49 P BUCK2 / BUCK6 Input. Bypass with 10 F and 4.7 F to Ground LX6 50,51 P BUCK6 switching node. Leave it floating if not used. BUCK6FB 52 AI BUCK6 output voltage sensing pin. Tie to INB26 if not used. VSYS 53 P Internal power input. Bypass with a 1 F to Ground LDO3 54 P LDO3 output. Bypass with a 2.2 F to Ground. LDO5 55 P LDO5 output. Bypass with a 1 F to Ground. INL1 56 P Power input pin for LDO1, LDO2, LDO3, LDO4 and LDO5. Bypass with a 4.7 F to Ground. GND Exposed PAD. All buck PGNDs are internally connected. EP PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 8 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 7 Functional description 7.1 Features The PCA9450 is a power management integrated circuit (PMIC) designed to be the primary power management for NXP application processors, i.MX 8M Mini, Nano and Plus. * Buck regulators - BUCK1, BUCK2, BUCK3 : 0.6 V to 2.1875 V, 12.5 mV step, 3000 mA - BUCK4 : 0.6 V to 3.4 V, 25 mV step, 3000 mA - BUCK5, BUCK6 : 0.6 V to 3.4 V, 25 mV step, 2000 mA - Dynamic Voltage scaling on BUCK1, BUCK2 and BUCK3 - Support remote sensing on BUCK1, BUCK2 and BUCK3 - BUCK1-BUCK3 configurable as a 6 A dual phase regulator (PCA9450C) - Monitor fault condition * LDO regulators - LDO1, 1.6 V to 1.9 V, 3.0 V to 3.3 V 100 mV step, 10 mA - LDO2, 0.8 V to 1.15 V with 50 mV step,10 mA - LDO3, 0.8 V to 3.3 V with 100 mV step, 300 mA - LDO4, 0.8 V to 3.3 V with 100 mV step, 200 mA - LDO5, 0.8 V to 3.3 V with 100 mV step, 150 mA, Voltage selection through SD_VSEL pin - Monitor fault condition * Support various memory types: DDR4/LPDDR4/DDR3L via system UBOOT configuration, no hardware change required * 400 mA Load switch for SD card - Built-in OCP protection - GPIO/I2C control - Built-in Active discharge resistor * Two Channel logic level translator * 32.768 kHz Crystal Oscillator driver - Mux output with internal 32 kHz output * Protection and Monitoring: Soft start, Power Rails Fault detection, UVLO, Thermal Shutdown * Configurable reset behavior from WDOGB, PMIC_RST_B and SW_RST Register * Power control IO - PMIC_ON_REQ, PMIC_STBY_REQ 2 * Fm+ 1 MHz I C-bus interface * Type3 PCB applicable PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 9 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 7.2 Functional diagram PCA9450 Functional Internal Block diagram 32 kHz buffer Regulators 32 kHz Osc driver / Buffer Linear Regulator Bias / Timing Internal Bias Power on sequence / Timing Logic Control AP logic control I2C communication I2C Level Translator Protection BUCK1 (0.6 V to 2.1875 V, 12.5 mV Step) 3000 mA, 0.85 V DVS LDO2 (0.85 V to 1.15 V, 50 mV Step) 10 mA BUCK2 (0.6 V to 2.1875 V, 12.5 mV Step) 3000 mA, 0.85 V DVS LDO3 (0.8 V to 3.3 V, 100 mV Step) 300 mA BUCK3 (0.6 V to 2.1875 V, 12.5 mV Step) 3000 mA, 0.85 V DVS BUCK4 (0.6 V to 3.4 V, 25 mV Step) 3000 mA, 3.3 V LDO5 (1.8 V to 3.3 V, 100 mV Step) 150 mA Thermal Warning / Protection UVLO LDO1 (1.6 V-1.9 V, 3.0 V-3.3 V, 100 mV Step) 10 mA LDO4 (0.8 V to 3.3 V, 100 mV Step) 200 mA I 2C Level Translator Current limit Switching Regulator BUCK5 (0.6 V to 3.4 V, 25 mV Step) 2000 mA, 1.8 V BUCK6 (0.6 V to 3.4 V, 25 mV Step) 2000 mA, 1.1 V Load Switch 400 mA load switch aaa-035702 Figure 3.PCA9450 functional block diagram The PCA9450 is a single chip Power Management IC (PMIC) specifically designed to support i.MX 8M family processor in both 1 cell Li-Ion and Li-polymer battery portable application and 5 V adapter non-portable applications. PCA9450 is provided in three versions: PCA9450AA, PCA9450B and PCA9450C depending on target application processor. Table 4 shows the selection guide. Table 4.PCA9450 selection guide Part number AP Platform BUCK1 BUCK3 LDO4 R_SNSP3_CFG PCA9450AA i.MX 8M Mini 3 A for SOC (ON by default) 3 A for VPU/GPU/ DRAM (ON by default) 0.9 V for VDDA (ON by default) R_SNSP3_CFG is feedback of BUCK 3 PCA9450B i.MX 8M Nano 3 A for SOC / VPU/GPU/DRAM (ON by default) Disabled OFF by default R_SNSP3_CFG = VSYS PCA9450C i.MX 8M Plus 6 A Dual phase for SOC/VPU/GPU/ DRAM (ON by default) OFF by default R_SNSP3_CFG = GND PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 10 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 7.3 Power modes PCA9450 has eight power modes: OFF, READY, SNVS, RUN, STADNBY, PWRDN, PWRUP and FAULT_SD. Figure 4 shows the state transition diagram showing the conditions to enter and exit each state. VSYS_POR = 1 Any State VSYS_UVLO = 1 OFF VSYS_POR = 0 VSYS_POR = 1 THSD = 0 or LDO1/2 FLT Clear Ready VSYS_UVLO = 1 VSYS_UVLO = 0 VR_FLT Clear SNVS PMIC_ON_REQ = H PWRDN Seq PWRUP Seq VR_FLT FAULT_SD PMIC_ON_REQ = L Or Cold Reset Run PMIC_STBY_REQ = L PMIC_ON_REQ = L Or Cold reset VR_FLT PMIC_STBY_REQ = H STANDBY VR_FLT aaa-035703 Figure 4.Power States Diagram 7.3.1 Off mode PCA9450 enters OFF mode from any state when VSYS falls below VSYS_POR threshold. All regulators are off and all registers get reset in this mode. 7.3.2 READY mode PCA9450 enters READY mode from OFF mode when VSYS is higher than VSYS_POR. Internal LDO VINT is enabled and loads Multiple Time Program (MTP) data to registers. Once MTP loading is done, it is ready to transition to SNVS mode. 7.3.3 SNVS mode PCA9450 enters Secure Non-Volatile Storage mode (SNVS) when VSYS exceeds VSYS_UVLO threshold. LDO1 and LDO2 are powered up and 32.768 kHz buffer starts running. RTC_RESET_B is pulled high in tRTC_RST after both LDO1 and LDO2 voltage come up. PMIC_ON_REQ input is masked until RTC_RESET_B is released. PCA9450 starts power up sequence if PMIC_ON_REQ is asserted high in this mode. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 11 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family VSYS UVLO UVLO POR POR VINT tSNVS_PU LDO1 NVCC_SNVS LDO2 tSTEP VDD_SNVS Int RC Osc X-tal Osc tRTC_RST RTC_RESET_B tRTC_Tran t32K_EN CLK_32K_OUT Mode OFF Ready SNVS OFF aaa-035704 Figure 5.SNVS mode ON/OFF sequence Table 5.SNVS mode Time Description Value tSNVS_PU Time to LDO1 turn on from VSYS UVLO detected 20 ms tSTEP Time to LDO2 ON from LDO1 POK 2 ms tRTC_RST Time to RTC_RESET_B release from LDO2 POK 20 ms T32K_EN Time to 32k buffer Enable from LDO2 POK 10 ms tRTC_Tran Time to transition to Xtal output from RC osc after RTC_RESET_B release 1 sec 7.3.4 PWRUP mode After RTC_RESET_B is released in SNVS mode, it starts power up with pre-defined sequence when PMIC_ON_REQ is asserted high for longer than debounce time, tON_DEB, which is programmable in PWR_CTRL reg. BUCK1 begins turning ON at first and then each power rail is followed with tstep after POK of predecessor power rail. During PWRUP mode, PMIC_STBY_REQ signal is masked until POR_B is released. The PWRUP mode ends up releasing POR_B and PCA9450 is transitioned to RUN mode. Figure 6 shows Power on sequence of PCA9450AA. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 12 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Masked PMIC_STBY_REQ PMIC_ON_REQ BUCK1 VDD_SOC BUCK3 VDD_DRAM VDD_G/VPU LDO4 BUCK2 LDO3 BUCK5 tstep tOFF_Step POK tstep tOFF_Step POK tstep tOFF_Step POK tstep NVCC_1V8 NVCC_3V3 tOFF_Step POK tstep VDDA_1P8 VDDA_DRAM BUCK4 LDO5 POK VDD_ARM NVCC_DRAM tOFF_DEB tON_DEB PHY_0P9 BUCK6 Masked POK tstep tOFF_Step POK tstep tOFF_Step POK tstep NVCC_SD2 tOFF_Step POK tOFF_Step tPOR_B POR_B Mode tOFF_Step SNVS PWRUP RUN PWRDN SNVS aaa-035706 LDO4/BUCK3 is MTP programmable to be selected in power up/down sequence. Figure 6.PCA9450AA power ON/OFF sequence BUCK3 and LDO4 are OFF by default in PCA9450B and PCA9450C. Those regulators are removed in the power up sequence, shown in Figure 7. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 13 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Masked PMIC_STBY_REQ PMIC_ON_REQ BUCK1 BUCK2 LDO3 BUCK5 POK tstep VDD_ARM NVCC_3V3 tOFF_Step POK tstep NVCC_1V8 BUCK4 tOFF_Step POK tstep VDDA_1P8 VDDA_DRAM NVCC_DRAM LDO5 tON_DEB VDD_SOC VDD_DRAM VDD_G/VPU BUCK6 Masked tOFF_DEB tOFF_Step POK tstep POK tstep tOFF_Step POK tstep NVCC_SD2 tOFF_Step POK tOFF_Step tPOR_B POR_B Mode tOFF_Step SNVS PWRUP PWRDN RUN SNVS aaa-035707 LDO4/BUCK3 is MTP programmable to be selected in power up/down sequence. Figure 7.PCA9450B/C power ON/OFF sequence Table 6.PWRUP mode Time Description Value tON_DEB Time to power-on start from PMIC_ON_REQ high 20 ms tSTEP Time to next power rail ON from prev rail POK 2 ms tPORB Time to POR_B release from the last rail POK 20 ms tOFF_STEP Time to next power rail off from prev rail off 8 ms tOFF_DEB Time to POR_B low from PMIC_ON_REQ falling 120 s If any of regulators doesn't generate POK within tFLT_SH_PU after receiving digital enable during PWRUP mode, it is transitioned to Fault_SD mode. 7.3.5 PWRDN mode When PMIC_ON_REQ is low for tOFF_DEB in RUN or STANDBY mode, PCA9450 enters PWRDN mode. It starts with pulling down POR_B and then turning off each power rail in tOFF_STEP and transitions to SNVS mode. 7.3.6 RUN mode PCA9450 operates in RUN mode when PMIC_ON_REQ is driven high and PMIC_STBY_REQ is driven low. BUCK1, BUCK2 and BUCK3 output voltage are set to BUCK1OUT_DVS0, BUCK2OUT_DVS0 and BUCK3OUT_DVS0 register value, respectively, when PRESET_EN bit in DVS123_DVS register is set to "0". When PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 14 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family PMIC_STBY_REQ is asserted high in this mode, it is transitioned to STANDBY mode. PMIC_ON_REQ is asserted low, it moves to PWRDN mode. 7.3.7 STANDBY mode PCA9450 transitions to STANDBY mode from RUN mode when both PMIC_ON_REQ and PMIC_STBY_REQ are driven high. BUCK1 and BUCK3 output voltage is set to BUCK1OUT_DVS1 and BUCK3OUT_DVS1 and BUCK2 are turned off when DVS_CTRL bit in each BUCKx_CTRL register is configured to 1. If PMIC_ON_REQ is asserted low, then it transitions to PWRDN mode. If PMIC_STBY_REQ is driven low, then it transitions to RUN mode. PMIC_STBY_REQ PMIC_ON_REQ BUCK1 VDD_SOC BUCK3 VDD_DRAM VDD_G/VPU LDO4 tOFF_DEB DVS0 DVS0 DVS1 DVS0 DVS0 DVS1 LDO3 tOFF_Step DVS1 tOFF_Step PHY_0P9 DVS0 BUCK2 DVS1 VDD_ARM tOFF_Step DVS0 tOFF_Step DVS1 = OFF VDDA_1P8 VDDA_DRAM BUCK5 NVCC_1V8 BUCK6 NVCC_DRAM BUCK4 NVCC_3V3 LDO5 NVCC_SD2 tOFF_Step tOFF_Step tOFF_Step tOFF_Step tOFF_Step POR_B Mode RUN STANDBY RUN STANDBY PWRDN SNVS aaa-035708 Figure 8.PCA9450AA mode transition Table 7.Power modes summary X : Don't care PCA9450 Product data sheet Power mode VSYS PMIC_ON_REQ PMIC_STBY_REQ OFF VSYS < VSYS_POR X X READY VSYS > VSYS_POR X X SNVS VSYS > VSYS_UVLO Low X STANDBY VSYS > VSYS_UVLO High High All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 15 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 7.Power modes summary...continued X : Don't care Power mode VSYS PMIC_ON_REQ PMIC_STBY_REQ RUN VSYS > VSYS_UVLO High Low 7.3.8 FAULT_SD PCA9450 has three types of fault sources. 1. Thermal shutdown : Transition to SNVS mode or READY mode after FAULT_SD mode. When junction temperature reaches TJSHDN, it enters FAULT_SD mode after tFLT_THSD where regulators are turned off simultaneously. It stays at FAULT_SD until junction temperature falls below TJSHDN. If the temperature drops below TJSHDN, then it moves to READY state if any of LDO1 and LDO2 fault is triggered when thermal shutdown PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 16 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family happens, and it moves to SNVS mode if neither LDO1 or LDO2 fault is triggered when thermal shutdown happens. Tj < TJSHDN Thermal Shutdown Event tFLT_THSD VSYS NOTE1 LDO1 NVCC_SNVS LDO2 VDD_SNVS NOTE1 Int RC Osc X-tal Osc NOTE1 RTC_RESET_B CLK_32K_OUT BUCK1 VDD_SOC BUCK3 VDD_DRAM VDD_G/VPU PHY_0P9 LDO4 VDD_ARM BUCK2 LDO3 VDDA_1P8 VDDA_DRAM BUCK5 NVCC_1V8 BUCK6 NVCC_DRAM BUCK4 NVCC_3V3 LDO5 NVCC_SD2 POR_B Mode Any state FAULT_SD SNVS aaa-035710 Note 1 : If LDO1/LDO2 triggers fault condition when junction temperature reaches thermal shutdown threshold, LDO1/LDO2/RTC_RESETB/CLK_32K_OUT is turned off. Otherwise, they are kept on. Figure 9.PCA9450 FAULT_SD from Thermal shutdown Table 8.tFLT_THSD Time Description Value tFLT_THSD Time to reset released from Fault event 120 s PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 17 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 2. Voltage regulator fault during power up: Transition to READY mode after FAULT_SD mode. Any POK of voltage regulators doesn't come up within tFLT_SD_PU after regulator is enabled during power up sequence. It stops power-up sequence and then moves to FAULT_SD where all regulators are turned off. It stays at FAULT_SD for tFLT_SD_STAY and transitions to READY state. 3. Voltage regulator fault in STANDBY and RUN MODE: Move to FAULT_SD mode in tFLT_SD_WAIT after Fault is detected. Transition to SNVS mode or READY mode from FAULT_SD mode when fault is removed. During RUN and STANDBY mode, VR Fault status bit in VRFLT1_STS and VRFLT2_STS registers is latched to "1" when corresponding regulator voltage falls below POK threshold for tDEB_POKB, or POK doesn't go high within tFLT_POK_MSK after regulator is enabled. If the fault status bit is masked in VRFLT1_MASK and VRFLT2_MASK registers, it doesn't enter FAULT_SD mode. Instead, PCA9450 stays at current mode. If the fault register bit is unmasked, it starts tFLT_SD_WAIT timer. Application processor can determine to enter FAULT_SD mode or not, by masking the VR Fault status bit in VRFLTx_MASK registers before the timer expires. PCA9450 enters FAULT_SD mode when the timer expires. PCA9450 stays in FAULT_SD mode for tFLT_SD_STAY. tFLT_SD_WAIT starts FAULT EVENT INT Mode AP receives INT Unmask fault register bit or Clear the status bit when fault is cleared RUN/STANDBY RUN/STANDBY tFLT_SD_WAIT starts FAULT EVENT INT Mode AP receives INT AP doesn't take an action until timer is expired RUN/STANDBY FAULT_SD aaa-035711 Figure 10.PCA9450 Fault event PCA9450 moves to READY mode after FAULT_SD mode if the regulator fault is caused by LDO1 or LDO2. Otherwise, it moves to SNVS mode after FAULT_SD. If either LDO1 or LDO2 has fault in SNVS mode, then it enters FAULT_SD mode regardless of VRFLT1 Mask bit. PCA9450 doesn't enter FAULT_SD mode from load switch overcurrent fault. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 18 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family tFLT_SD_STAY VR_FLT event VR_FLT Clear tFLT_SD_WAIT VSYS NOTE1 LDO1 NVCC_SNVS LDO2 VDD_SNVS NOTE1 Int RC Osc X-tal Osc NOTE1 RTC_RESET_B CLK_32K_OUT BUCK1 VDD_SOC BUCK3 VDD_DRAM VDD_G/VPU PHY_0P9 LDO4 BUCK2 LDO3 VDD_ARM VDDA_1P8 VDDA_DRAM BUCK5 NVCC_1V8 BUCK6 NVCC_DRAM BUCK4 NVCC_3V3 LDO5 NVCC_SD2 POR_B Mode Any state FAULT_SD SNVS aaa-035712 Note 1 : If VR fault is caused by LDO1 or LDO2, then LDO1/LDO2/ RCT_REST_B/CLK_32K_OUT is turned OFF, otherwise, they are kept on. Figure 11.PCA9450 FAULT_SD from VR Fault except LDO1/LDO2 in RUN/STANDBY Table 9.tFLT_SD_WAIT Time Description Value tFLT_SD_WAIT Time to reset released from Fault event 100 ms PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 19 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 7.4 PMIC reset PCA9450 has three reset input sources: WDOG_B pin, PMIC_RST_B pin and I2C reset bit. The reset behavior is configured in RESET_CTRL register for WDOG_B pin and PMIC_RST_B pin. I2C reset behavior is configured in SW_RST register. Table 10.0x08 - RESET_CTRL Reset Type 0x08 - RESET_CTRL Bit 7:6 5:4 Type Name R/W WDOG_B_CFG R/W PMIC_RST_CFG S Reset Description 00 When WDOG_B is asserted to L, PMIC behavior 00b = WDOG_B reset is disabled 01b = Warm Reset, POR_B pin is asserted low for 20 ms 10b = Cold Reset, All voltage regulators are recycled except LDO1/ LDO2 11b = Cold Reset, All voltage regulators are recycled 10 When PMIC_RST_B is asserted to L, PMIC behavior 00b = PMIC_RST_B reset is disabled 01b = Warm Reset, POR_B pin is asserted low for 20 ms 10b = Cold Reset, All voltage regulators are recycled except LDO1/LDO2 11b = Reserved Table 11.0x06 - SW_RST 0x06 - SW_RST Bit 7:0 Name SW_RST Reset Type Type R/W O Reset Description 0x00 Software reset register. This register read back to "0x00" right after writing the value. 0x00 = No action 0x05 = Reset all registers to default value 0x14 = Cold reset (Power recycle all regulators except LDO1, LDO2 and CLK_32K_OUT) 0x35 = Warm Reset (Toggle POR_B for 20 ms) 0x64 = Cold reset (Power recycle all regulators) Others = No action WDOG_B is asserted low, and gets reset depending on WDOG_B_CFG bit configuration. When the bits are set to 2b00, the reset by WDOG_B pin is disabled. If the bits are set to 2b01, warm reset is performed, where POR_B is pulled low for 20 ms and resets I2C O type registers to default value keeping power rails remaining ON. If the bits are set to 2b11, it performs Cold reset, where all voltage regulators except LDO1 and LDO2 are power recycled and I2C O type registers get reset to default value. When PMIC_RST_B is asserted low, it also gets reset depending on PMIC_RST_CFG bits configuration. When the bits are set to 2b00, any reset by PMIC_RST_B pin is disabled. If the bits are set to 2b01, warm reset is performed, in which pulling POR_B low for 20 ms and reset I2C O type registers to default value keeping power rails remaining ON. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 20 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Cold reset event is generated by either of I2C reset, WDOG_B falling edge or PMIC_RST_B falling edge after debounce time. Once it is detected, POR_B is pulled low and takes power down sequence. For cold reset from WDOG_B and I2C reset, PCA9450 stays at RESET for tRESTART and then starts power on sequence even though WDOG_B pin is still low. For cold reset from PMIC_RST_B, tRESTART timer starts after PMIC_RST_B is asserted high; in other words, PCA9450 starts power on sequence in tRESTART after PMIC_RST_B pin is released high. Cold Reset Sources LDO1/2 tRESTART BUCK1 VDD_SOC BUCK3 VDD_DRAM VDD_G/VPU LDO4 BUCK2 LDO3 BUCK5 LDO5 NVCC_SD2 tstep tOFF_Step BUCK6 NVCC_DRAM POK tstep tOFF_Step NVCC_1V8 POK tstep tOFF_Step VDDA_1P8 VDDA_DRAM POK tstep tOFF_Step VDD_ARM NVCC_3V3 POK tOFF_Step PHY_0P9 BUCK4 POK tOFF_Step POK tstep tOFF_Step POK tstep tOFF_Step POK tstep POR_B Mode POK tstep tOFF_Step RUN/ STANDBY PWRDN RESET tPOR_B RUN/ STANDBY PWRUP aaa-035713 Note: BUCK3 and LDO4 are removed in Power ON/OFF sequence in PCA9450B/C Figure 12.PCA9450AA Cold reset Table 12.tRESTART Time Description Value tRESTART Time to power ON seq from end of power OFF seq during cold reset 250 ms PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 21 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Warm Reset source BUCK1 VDD_SOC BUCK3 VDD_DRAM VDD_G/VPU LDO4 All regulator output goes to default voltage PHY_0P9 BUCK2 VDD_ARM VDDA_1P8 VDDA_DRAM LDO3 BUCK5 NVCC_1V8 BUCK6 NVCC_DRAM BUCK4 NVCC_3V3 LDO5 NVCC_SD2 tRESET POR_B Mode RUN/ STANDBY RUN/ STANDBY Reset aaa-035715 Figure 13.Warm reset Table 13.tRESET Time Description Value tRESET POR_B low time at Warm reset 20 ms 7.5 Regulator control in each power mode Table 14 shows PCA9450AA regulator ON/OFF control in each power mode by default. It can be reconfigured through I2C registers. Table 14.PCA9450AA Regulator Control summary Power Rail Default Voltage OFF SNVS STANDBY RUN LDO1 NVCC_SNVS 1.8 V OFF ON ON ON LDO2 VDD_SNVS 0.85 V OFF ON ON ON BUCK1 VDD_SOC 0.85 V OFF OFF ON ON BUCK3 VDD_DRAM VDD_GPU VDD_ 0.85 V VPU OFF OFF ON ON LDO4 PHY_0P9 OFF OFF ON ON PCA9450 Product data sheet 0.9 V All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 22 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 14.PCA9450AA Regulator Control summary...continued Power Rail Default Voltage OFF SNVS STANDBY RUN BUCK2 VDD_ARM 0.85 V OFF OFF OFF ON LDO3 VDDA_1P8 1.8 V OFF OFF ON ON BUCK5 NVCC_1V8 1.8 V OFF OFF ON ON BUCK6 NVCC_DRAM 1.1 V OFF OFF ON ON BUCK4 NVCC_3V3 3.3 V OFF OFF ON ON LDO5 NVCC_SD2 3.3 V / 1.8 V OFF OFF ON ON Table 15 shows PCA9450B/PCA9450C regulator ON/OFF control in each power mode by default. It can be reconfigured through I2C registers. Table 15.PCA9450B/PCA9450C Regulator Control summary Power Rail Default Voltage OFF SNVS STANDBY RUN LDO1 NVCC_SNVS 1.8 V OFF ON ON ON LDO2 VDD_SNVS 0.85 V OFF ON ON ON BUCK1 VDD_SOC VDD_ DRAM VDD_GPU 0.85 V VDD_VPU OFF OFF ON ON 0.9 V OFF OFF OFF OFF LDO4 BUCK2 VDD_ARM 0.85 V OFF OFF OFF ON LDO3 VDDA_1P8 1.8 V OFF OFF ON ON BUCK5 NVCC_1V8 1.8 V OFF OFF ON ON BUCK6 NVCC_DRAM 1.1 V OFF OFF ON ON BUCK4 NVCC_3V3 3.3 V OFF OFF ON ON LDO5 NVCC_SD2 3.3 V / 1.8 V OFF OFF ON ON 7.6 Regulator summary The PCA9450 features six buck regulators, five linear regulators and one load switch to supply voltage rails powering the application processor and peripheral devices. The buck regulators are supplied directly from the main input supply. The input to all of the buck regulators must be tied to VSYS, whether they are powered on or off. 7.6.1 BUCK regulator The PCA9450AA has six high-efficiency low Iq buck regulators. Each buck regulator features soft start and overcurrent protection. Buck regulator operates in two modes: PFM and PWM mode. It automatically transitions from PFM to PWM mode when FPWM bit is set to "0". Internal active discharge resistor is installed in each buck regulator output to discharge voltage on output capacitors when regulator is off. It is configurable through I2C register. Table 16 shows buck regulator summary. BUCK1 and BUCK3 are configured as dual-phase buck regulator in PCA9450C and provide up to 6 A. Table 17 shows PCA9450C buck summary. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 23 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 16.PCA9450AA Buck Summary BUCK# INPUT PIN Default VOUT [V] VOUT range [V] Step size [mV] Default ON/ OFF Current rating [mA] BUCK1 INB13 0.85 0.6 - 2.1875 12.5 ON 3000 BUCK2 INB26 0.85 0.6 - 2.1875 12.5 ON 3000 BUCK3 INB13 0.85 0.6 - 2.1875 12.5 ON 3000 BUCK4 INB45 3.3 0.6 - 3.4 25 ON 3000 BUCK5 INB45 1.8 0.6 - 3.4 25 ON 2000 BUCK6 INB26 1.1 0.6 - 3.4 25 ON 2000 Table 17.PCA9450C Buck Summary Buck# INPUT PIN Default VOUT [V] VOUT range [V] Step size [mV] Default ON/ OFF Current rating [mA] BUCK1 INB13 0.85 0.6 - 2.1875 12.5 ON 6000 BUCK2 INB26 0.85 0.6 - 2.1875 12.5 ON 3000 BUCK4 INB45 3.3 0.6 - 3.4 25 ON 3000 BUCK5 INB45 1.8 0.6 - 3.4 25 ON 2000 BUCK6 INB26 1.1 0.6 - 3.4 25 ON 2000 7.6.1.1 Dynamic voltage scaling BUCK1, BUCK2 and BUCK3 support DVS (Dynamic Voltage Scaling). If PRESET_EN bit in BUCK123_DVS register is set to 1, BUCK1/BUCK2/BUCK3 outputs are controlled by Bx_DVS_PRESET bits in BUCK123_DVS. It enables those buck outputs to be controlled by writing one register at a time. If PRESET_EN bit is set to 0, those buck regulators outputs are determined by BUCKxOUT_DVS0 and BUCKxOUT_DVS1 depending on PMIC_STBY_REQ pin. When PMIC_STBY_REQ is asserted low, each buck output voltage is determined by BUCKxOUT_DVS0 register, if the PMIC_STBY_REQ is asserted high, BUCKxOUT_DVS1 register is selected as each buck output voltage. Figure 14 shows the DVS voltage section diagram. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 24 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Bx_DVS_PRESET 0x0C Reg 1 BUCK1, 2, 3 BUCKxOUT_DVS0 Min Selection L I2C programmable BUCKx Output 0 BUCKxOUT_LIMIT BUCK1, 2, 3 BUCKxOUT_DVS1 H PRESET_EN In 0x0C Reg PMIC_STBY_REQ DVS0 : PMIC_STBY_REQ = L DVS1 : PMIC_STBY_REQ = H aaa-035716 Figure 14.DVS functional diagram The programmable voltage ramp-up and ramp-down are applied during the DVS voltage transition. The ramp rate is configured by RAMP[7:6] bits in each BUCKxCTRL registers. PMIC_STBY_REQ BUCKx DVS0 DVS1 RAMP[7:6] Internal control with RAMP[7:6] 10us DVS1 BUCK output depending on Load aaa-035718 Figure 15.DVS timing 7.6.1.2 BUCK output voltage limiting Application processor may accidentally write higher voltage than absolute maximum voltage rating of its power input, which may cause significant damage on application processor. PCA9450 has registers to limit the maximum voltage to prevent such an incident. BUCK1, BUCK2 and BUCK3 maximum output are limited by BUCKxOUT_LIMIT, respectively. Even if buck output is configured to higher than the limit voltage configured in BUCKxOUT_LIMIT register, the actual buck output is clamped to the limiting voltage set by BUCKxOUT_LIMIT register. 7.6.1.3 Dual-phase configuration BUCK1 and BUCK3 are configured as dual phase buck in PCA9450C by connecting R_SNSP3_CFG pin to GND, where this dual phase buck regulator is controlled through BUCK1 registers. All BUCK3 registers are not responsive under dual-phase configuration. When R_SNSP3_CFG pin is tied to INB13 in PCA9450B, BUCK3 is disabled. BUCK1 supplies VDD_SOC/VDD_VPU/VDD_GPU/VDD_DRAM in i.MX 8M Nano application processor. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 25 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family PCA9450B PCA9450C INB13 DVS LX1 0.47 H BUCK1 3A Dual Phase Ctrl SYS VDD_SOC VDD_VPU 10 F VDD_GPU VDD_DRAM DVS BUCK1 3A R_SNSP1 i.MX8 Nano INB13 DVS SYS EN Dual Phase Ctrl DVS LX3 BUCK3 3A EN SYS 10 F 22 F EN INB13 BUCK3 3A EN R_SNSP3_CFG LX1 0.47 H VDD_SOC VDD_VPU VDD_GPU VDD_DRAM 22 F R_SNSP1 i.MX8 Plus INB13 LX3 SYS 0.47 H 22 F R_SNSP3_CFG aaa-035719 Figure 16.BUCK1/3 configuration 7.6.2 LDO and load switch The PCA9450 has five LDOs and one load switch. LDO1 and LDO2 are supposed to supply SNVS core in application processor. These two LDOs feature ultra-low quiescent current, 2 A typical, since they are always ON when VSYS is valid. For all LDO and the load switch, each has designated active discharge resistor configurable through I2C. Table 18.LDO summary LDO# INPUT PIN Default VOUT [V] VOUT range [V] Step size [mV] Default ON/ OFF Current rating [mA] LDO1 INL1 1.8 1.6-1.9, 3.0-3.3 100 ON 10 LDO2 INL1 0.85 0.8 - 1.15 50 ON 10 LDO3 INL1 1.8 0.8 - 3.3 100 ON 300 [1] LDO4 INL1 0.9 0.8 - 3.3 100 ON LDO5 INL1 3.3/1.8 1.8 - 3.3 100 ON 150 SW SWIN - - - OFF 400 [1] 200 ON by default in PCA9450AA, OFF by default in PCA9450B and PCA9450C 7.7 32 kHz Crystal Oscillator Driver The PCA9450 consists of a crystal oscillator driver with an external load capacitor and CLK_32K_OUT buffer referenced to LDO1 voltage. When VSYS exceeds POR threshold and internal power VINT is good, internal 32 kHz oscillator and 32.768 kHz crystal oscillator start oscillating. Crystal oscillator typically takes few seconds to be stabilized. PCA9450 outputs the internal 32 kHz RC oscillator initially, while internal counter counts crystal oscillator output in tRTC_Tran after RTC_RESET_B is released. If the counter reaches 100, then CLK_32K_OUT buffer input is switched to the external crystal oscillator from internal 32 kHz oscillator. Clock stretch is applied during this clock source transition to prevent unwanted glitch. If external 32.768 kHz crystal oscillator is not populated, CLK_32K_OUT pin outputs 32 kHz clock from internal 32 kHz oscillator. For more detailed information on selecting crystal oscillator and load capacitance, refer to Section 9.2.2. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 26 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family XTAL_IN VINT 32K Osc 32.768K Xtal XTAL_OUT RTC_RESET_B tRTC_Tran MUX COUNT LDO1 CLK_32K_OUT CLOCK STRETCH aaa-035720 Figure 17.32 kHz Crystal oscillator driver block diagram 7.8 Load switch PCA9450 integrates 400 mA load switch which is used to supply SD card VDD. SWIN is connected to BUCK4 output, 3.3 V, in this application. It is enabled by SW_EN pin or SW_EN[1:0] bits in LOADSW_CTRL register. It has soft start feature to reduce inrush current during turn-on. This load switch has overcurrent protection and short circuit protection by monitoring voltage difference between SWIN and SWOUT. When the switch current exceeds overcurrent threshold (IOC) for overcurrent debounce time (tOC_DEB), SW_OCP bit in VRFLT1_STS register is set to 1 and the fault behavior is determined by SW_OC[1:0] configuration in LOADSW_CTRL register. When the switch current exceeds short-circuit current threshold (ISC), SW_OCP bit in VRFLT1_STS register is set to 1 and switch is turned off right away. SW_OC SW_SC from Buck4 3.3 V SWOUT SWIN F 80 F DRIVER SW_EN I2C aaa-035721 Figure 18.Load switch internal block diagram 2 7.9 I C level translator 2 PCA9450 I C level translator is a "switch" type voltage translator, and employs two key circuits to enable voltage translation: PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 27 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 1. A pass-gate transistor (N-channel) that ties the ports together. 2. An output edge-rate accelerator that detects and accelerates rising edges on the I/O pins. The gate bias voltage of the pass gate transistor (T3) is set at approximately one threshold voltage above the VCC level of the low-voltage side. During a LOW-to-HIGH transition the output one-shot accelerates the output transition by switching on the PMOS transistors (T1, T2) bypassing the 10 k pull-up resistors and increasing current drive capability. The one-shot is activated once the input transition reaches approximately VCCI/2; it is de-activated approximately 50 ns after the output reaches VCCO/2. During the acceleration time the driver output resistance is between approximately 50 and 70 . To avoid signal contention and minimize dynamic ICC, the user should wait for the one-shot circuit to turn off before applying a signal in the opposite direction. Pull-up resistors are included in the device for DC current sourcing capability. VCCA (VINT) VCCB (SWIN) T1 ONE SHOT ONE SHOT 10 k T2 10 k GATE BIAS T3 A (SCLL) B (SCLH) aaa-035722 Figure 19.Architecture of I2C Level translator (One channel) Each A port I/O has an internal 10 k pull-up resistor to VCCA, and each B port I/O has an internal 10 k pull-up resistor to VCCB. If a smaller value of pull-up resistor is required, an external resistor must be added parallel to the internal 10 k, affecting the VOL level. When Level translator is disabled through I2C, the internal pull up resistors are disconnected. PCA9450 I2C Level translator is controlled by I2C register, CONFIG2 Reg. When it is configured to disabled, all I/Os assume the high-impedance OFF-state. The enable time (ten) indicates the amount of time the user must allow for one one-shot circuitry to become operational after it is enabled. 7.10 Interrupt management The IRQ_B pin is an interface to the software-controlled system that indicates any interrupt bit status change of INT1 register. The IRQ_B pin is pulled low when any unmasked interrupt bit status is changed and it is released high once application processor reads INT1 register. The INT1 bits are latched to 1 whenever corresponding STATUS1 bits are changed and the latch is cleared when the INT1 register is read. The INT1_MASK bits are used to enable or disable individual interrupt bits of INT1 register. The STATUS1 register indicates the current status and is not latched. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 28 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family VRFLT1_MASK VRFLT1_STS RSVD SW_OCP RSVD RSVD BUCK6_FLT_M BUCK6_FLT BUCK5_FLT_M BUCK5_FLT BUCK4_FLT_M BUCK4_FLT BUCK3_FLT_M BUCK3_FLT BUCK2_FLT_M BUCK2_FLT BUCK1_FLT_M BUCK1_FLT VRFLT2_MASK VRFLT2_STS RSVD RSVD RSVD RSVD RSVD RSVD LDO5_FLT_M LDO5_FLT LDO4_FLT_M LDO4_FLT LDO3_FLT_M LDO3_FLT LDO2_FLT_M LDO2_FLT LDO1_FLT_M LDO1_FLT STATUS1 INT1 PMIC_ON_REQ Deb PWRONS PWRONI WDOG_B Deb WDOG_BS WDOGBI RSVD RSVD VR_FLT1_S VR_FLT1I VR_FLT2_S VR_FLT2I LOWVSYS_S LOWVSYSI THERM_105S THERM_105I THERM_125S THERM_125I INT1 MASK INT VSYS VSYS UVLO + Delta 105C Die Temp 125C aaa-035723 Figure 20.Interrupt diagram PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 29 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 8 Software interface PCA9450 implements I2C-bus slave interface and it interfaces with the host system. The host processor can issue commands, monitor status and receive response through this bus. A detailed description of the I2C-bus specification, with applications, is given in UM10204, "I2C-bus specification and user manual" [Ref. 4]. PCA9450 supports I2C-bus data transfers in Standard-mode (100 kbit/s), Fast-mode (400 kbit/s) and Fast-mode plus (1 Mbit/s). The I2C address at Power-On Reset is shown in Table 19 Table 19.PCA9450 I2C Slave Address 7-bit Slave Address 8-bit Write Address 8-bit Read Address 0x25, 0b 010 0101 0x4A, 0b 0100 1010 0x4B, 0b 0100 1011 I2C register reset type Type S1 : Reset condition = VSYS < VSYS_POR Type S : Reset condition = VSYS < VSYS_UVLO Type O : Reset condition = (VSYS < VSYS_UVLO) || (Cold Reset) || (Warm Reset) || (Falling edge of PMIC_ON_REQ) || (SW_RST) || (FAULT_SD) PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 30 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 8.1 Register map Table 20.Register map Description Add Name 0x00 Device_ID 0x01 INT1 0x02 INT1_MSK 0x03 STATUS1 PWRONS WDOGBS RSVD VR_FLT1S 0x04 STATUS2 RSVD RSVD RSVD RSVD 0x05 PWRON_STAT PWRON WDOG SW_RST PMIC_RST 0x06 SW_RST 0x07 PWR_CTRL Ton_Deb 0x08 RESET_CTRL WDOGB_CFG PMIC_RST_CFG RSVD 0x09 CONFIG1 LOW_VSYS VSYS_UVLO RSVD RSVD 0x0A CONFIG2 RSVD RSVD RSVD 0x0C BUCK123_DVS PRESET_ EN 0x0D BUCK1OUT_LIMIT RSVD 0x0E BUCK2OUT_LIMIT 0x0F BUCK3OUT_LIMIT 0x10 BUCK1CTRL 0x11 BUCK1OUT_DVS0 RSVD 0x12 BUCK1OUT_DVS1 RSVD 0x13 BUCK2CTRL 0x14 BUCK2OUT_DVS0 PCA9450 Product data sheet B7 B5 B6 B4 B3 B2 B1 CHIP_ID B0 RSVD R/W Reset Type Reset Value R S 0x11 LOWVSYSI THERM_ 105I THERM_ 125I R/C S 0x00 LOWVSYS_ M THERM_ 105_M THERM_ 125_M R/W S 0xFF LOWV SYSS THERM_ 105S THERM_ 125S R S 0x00 R S1 0x00 R/C S 0x00 R/W O 0x00 R/W S 0x4C T_PMIC_RST_DEB R/W S 0x21 tFLT_ SD_WAIT R/W S1 0x50 R/W O 0x00 R/W O 0xA9 B1_LIMIT R/W O 0x1C RSVD B2_LIMIT R/W O 0x20 RSVD B3_LIMIT R/W O 0x1C R/W O 0x49 B1_DVS0 R/W O 0x14 B1_DVS1 R/W O 0x14 R/W O 0x4A R/W O 0x14 PWERONI WDOGBI PWRONI_M WDOGB_M RSVD RSVD VR_FLT1I VR_FLT2I VR_FLT1_M VR_FLT2_M VR_FLT2S POWER_STATUS RSVD RSVD RSVD RSVD SW_RST RSVD RAMP RAMP RSVD Toff_Deb RSVD B3_DVS_PRESET RSVD RSVD Tstep RSVD B1_DVS_PRESET DVS_CTRL DVS_CTRL Trestart Toff_step BUCK1AD BUCK2AD I2C_LT_EN B2_DVS_PRESET FPWM FPWM B2_DVS0 All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 THERM_ SD_DIS B1_ENMODE B2_ENMODE (c) NXP B.V. 2020. All rights reserved. 31 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 20.Register map...continued Description Add Name 0x15 BUCK2OUT_DVS1 0x16 BUCK3CTRL 0x17 BUCK3OUT_DVS0 RSVD 0x18 BUCK3OUT_DVS1 RSVD 0x19 BUCK4CTRL RSVD 0x1A BUCK4OUT RSVD 0x1B BUCK5CTRL RSVD 0x1C BUCK5OUT RSVD 0x1D BUCK6CTRL RSVD 0x1E BUCK6OUT RSVD 0x20 LDO_AD_CTRL LDO1_AD 0x21 LDO1CTRL 0x22 B7 B6 B5 R/W Reset Type Reset Value R/W O 0x14 R/W O 0x49 B3_DVS0 R/W O 0x14 B3_DVS1 R/W O 0x14 R/W O 0x09 R/W O 0x6C R/W O 0x09 R/W O 0x30 R/W O 0x09 R/W O 0x14 R/W O 0xF8 B4 B3 RSVD B2 B1 B0 B2_DVS1 RSVD RAMP RSVD RSVD DVS_CTRL RSVD BUCK3AD BUCK4AD FPWM B3_ENMODE FPWM B4_ENMODE B4_OUT RSVD RSVD RSVD BUCK5AD FPWM B5_ENMODE B5_OUT RSVD RSVD RSVD BUCK6AD FPWM B6_ENMODE B6_OUT LDO3_AD LDO4_AD LDO5_AD ENMODE RSVD RSVD RSVD L1_OUT R/W O 0xC2 LDO2CTRL ENMODE RSVD RSVD RSVD L2_OUT R/W O 0xC1 0x23 LDO3CTRL ENMODE RSVD L3_OUT R/W O 0x4A 0x24 LDO4CTRL ENMODE RSVD L4_OUT R/W O 0x41 0x25 LDO5CTRL_L ENMODE RSVD RSVD L5_OUT_L R/W O 0x4F 0x26 LDO5CTRL_H RSVD RSVD L5_OUT_H R/W O 0x00 0x27 RSVD RSVD R/W O 0x00 0x28 RSVD RSVD R/W O 0x00 0x29 RSVD RSVD R/W O 0x00 0x2A LOADSW_CTRL SW_AD RSVD RSVD R/W O 0x85 0x2B VRFLT1_STS SW_OCP RSVD BUCK6_ FLT 0x2C VRFLT2_STS RSVD RSVD RSVD PCA9450 Product data sheet RSVD LDO2_AD RSVD SW_SC SW_OC BUCK5_FLT BUCK4_FLT LDO5_FLT RSVD LDO4_FLT RSVD SWEN BUCK3_ FLT BUCK2_ FLT BUCK1_FLT R/W/C S 0x00 LDO3_FLT LDO2_FLT LDO1_FLT R/W/C S 0x00 All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 RSVD (c) NXP B.V. 2020. All rights reserved. 32 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 20.Register map...continued Add Name 0x2D 0x2E Description R/W Reset Type Reset Value BUCK1_ FLT_M R/W S 0x3F LDO1_ FLT_M R/W S 0x1F B7 B6 B5 B4 B3 B2 B1 B0 VRFLT1_MASK RSVD RSVD BUCK6_ FLT_M BUCK5_ FLT_M BUCK4_ FLT_M BUCK3_ FLT_M BUCK2_ FLT_M VRFLT2_MASK RSVD RSVD RSVD LDO5_ FLT_M LDO4_ FLT_M LDO3_ FLT_M LDO2_ FLT_M PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 33 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 8.2 Register details 8.2.1 0x00 Device_ID The device identification code stores a unique identifier for each version and/or revision of a PCA9450, so that the connected processor recognizes it automatically. Table 21.0x00 Device_ID Reset Type 0x00 - Device_ID Bit Name Type Reset Description 7:4 CHIP_ID R 0001 Chip ID 0001b = PCA9450AA 0011b = PCA9450B, PCA9450C 3:0 RSVD R 0001 Reserved S 8.2.2 0x01 INT1 Interrupt source register. Either of unmasked register bits is set to 1, IRQ_B pin is pulled low. This register is Read and Clear. Table 22.0x01 INT1 Reset Type 0x01 - INT1 S Bit Name Type Reset Description 7 PWRONI R/C 0 PWRON interrupt bit 0b = PWRONS bit has not been changed 1b = PWRONS bit has been changed 6 WDOGBI R/C 0 WDOGB interrupt bit 0b = WDOG_BS bit has not been changed 1b = WDOG_BS bit has been changed 5 RSVD R/C 0 Reserved 4 VR_FLT1I R/C 0 Voltage regulator Group1 Fault interrupt 0b = VR_FLT1S bit has not been changed 1b = VR_FLT1S bit has been changed 3 VR_FLT2I R/C 0 Voltage regulator Group2 Fault interrupt 0b = VR_FLT2S bit has not been changed 1b = VR_FLT2S bit has been changed 2 LOWVSYSI R/C 0 Low-SYS Voltage interrupt bit 0b = LOWVSYSS bit has not been changed 1b = LOWVSYSS bit has been changed 1 THERM_105I R/C 0 Die temperature 105 C interrupt 0b = THERM_105S bit has not been changed 1b = THERM_105S bit has been changed 0 THERM_125I R/C 0 Die temperature 125 C interrupt 0b = THERM_125S bit has not been changed 1b = THERM_125S bit has been changed PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 34 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 8.2.3 0x02 INT1_MSK The INT1_MSK register enables the masking (disabling) of the different interrupt signals of register INT1. When unmasked, interrupt events trigger the IRQB pin to be pulled low when the matching flag bit in the register INT1 is set. Table 23.0x02 INT1_MSK Reset Type 0x02 - INT1_MSK Bit Name Type Reset Description 7 PWRON_M R/W 1 PWRONI interrupt mask bit 0b = Enable PWRONI interrupt 1b = Mask PWRONI interrupt 6 WDOGB_M R/W 1 WDOGBI interrupt mask bit 0b = Enable WDOGBI interrupt 1b = Mask WDOGBI interrupt 5 RSVD R/W 1 Reserved 4 VR_FLT1_M R/W 1 VR_FLT1I interrupt mask bit 0b = Enable VR_FLT1I interrupt 1b = Mask VR_FLT1I interrupt 3 VR_FLT2_M R/W 1 VR_FLT2I interrupt mask bit 0b = Enable VR_FLT2I interrupt 1b = Mask VR_FLT2I interrupt 2 LOWVSYS_M R/W 1 LOWVINI interrupt mask bit 0b = Enable LOWVINI interrupt 1b = Mask LOWVINI interrupt 1 THERM_105_M R/W 1 THERM_105 interrupt mask bit 0b = Enable THERM_105 interrupt 1b = Mask THERM_105 interrupt 1 THERM_125 interrupt mask bit 0b = Enable THERM_125 interrupt 1b = Mask THERM_125 interrupt 0 THERM_125_M R/W S 8.2.4 0x03 STATUS1 STATUS1 register show current status. Any status bit change set corresponding interrupt bit to 1. Table 24.0x03 STATUS1 Reset Type 0x03 - STATUS1 S Bit Name Type Reset Description 7 PWRONS R 0 PMIC_ON_REQ pin status after debounce time 0b = PMIC_ON_REQ pin is low 1b = PMIC_ON_REQ pin is high 6 WDOG_BS R 0 WDOG_B pin status 0b = WDOG_B pin is low 1b = WDOG_B pin is high 5 RSVD R 0 Reserved PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 35 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 24.0x03 STATUS1...continued Reset Type 0x03 - STATUS1 S Bit Name Type Reset Description 4 VR_FLT1S R 0 Voltage Regulator Fault status, See 0x2B Register. 0b = All voltage regulators are OK 1b = Either of voltage regulators is in Fault state 3 VR_FLT2S R 0 Voltage Regulator POK status, See 0x2C Registers. 0b = All voltage regulators are OK 1b = Either of voltage regulators is in Fault state 2 LOWVSYSS R 0 VSYS low voltage status 0b = VSYS > Low VSYS threshold 1b = VSYS Low VSYS threshold 1 THERM_105S R 0 Die temperature 105 C status 0b = Die temperature is below 105 C 1b = Die temperature is above 105 C 0 THERM_125S R 0 Die temperature 125 C status 0b = Die temperature is below 125 C 1b = Die temperature is above 125 C 8.2.5 0x04 STATUS2 STATUS2 register shows current PCA9450 power status. Table 25.0x04 STATUS2 Reset Type 0x04 - STATUS2 Bit Name Type Reset Description 7:4 RSVD R 0000 Reserved 0000 Current PCA9450 power status 0000b = OFF 0001b = READY 0010b = SNVS 0011b = PWRUP 0100b = RUN 0101b = STANDBY 0110b = PWRDN 0111b = WARM RESET 1000b = COLD RESET 1001b = FAULT Shutdown 1010b - 1111b = Reserved 3:0 POWER_STATUS R S1 8.2.6 0x05 PWRON_STAT Power ON source register. It is latched to 1 until the bit is read back. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 36 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 26.0x05 PWRON_STAT Reset Type 0x05 - PWRON_STAT S Bit Name Type Reset Description 7 PWRON R/C 0 1b = Power ON triggered by PMIC_ON_REQ. This bit will be set right after completing power up sequence. 6 WDOG R/C 0 1b = This bit is set after cold reset by WDOGB pin 5 SW_RST R/C 0 1b = This bit is set after cold reset by SW_RST bit 4 PMIC_RST R/C 0 1b = This bit is set after cold reset by PMIC_RST_B 3 RSVD R/C 0 Reserved 2 RSVD R/C 0 Reserved 1 RSVD R/C 0 Reserved 0 RSVD R/C 0 Reserved 8.2.7 0x06 SW_RST Software reset register through I2C. Table 27.0x06 SW_RST Reset Type 0x06 - SW_RST Bit 7:0 Name Type SW_RST R/W O Reset Description 0x00 Software reset register. This register is read back to "0x00" right after writing the value. 0x00 = No action 0x05 = Reset all registers to default value 0x14 = Cold reset (Power recycle all regulators except LDO1, LDO2 and CLK_32K_OUT) 0x35 = Warm Reset (Toggle POR_B for 20 ms) 0x64 = Cold reset (Power recycle all regulators) Others = No action 8.2.8 0x07 PWR_CTRL Debounce timer configuration register Table 28.0x07 PWR_CTRL Reset Type 0x07 - PWR_CTRL Bit Name Type Reset Description S 7:6 Ton_Deb R/W 01 Debounce time for PMIC_ON_REQ high. 00b = 120 s 01b = 20 ms 10b = 100 ms 11b = 750 ms 5 Toff_Deb R/W 0 Debounce time for PMIC_ON_REQ is asserted low 0b = 120 s 1b = 2 ms PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 37 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 28.0x07 PWR_CTRL...continued Reset Type 0x07 - PWR_CTRL Bit 4:3 Name Type Tstep R/W S Reset Description 01 Time step configuration during power on sequence 00b = 1 ms 01b = 2 ms 10b = 4 ms 11b = 8 ms 2:1 Toff_step R/W 10 Time step configuration during power down sequence 00b = 2 ms 01b = 4 ms 10b = 8 ms 11b = 16 ms 0 Trestart R/W 0 Time to stay regulators off during Cold reset 0b = 250 ms 1b = 500 ms 8.2.9 0x08 RESET_CTRL Reset behavior configuration register through WDOG_B and PMIC_RST_B pin. Table 29.0x08 RESET_CTRL Reset Type 0x08 - RESET_CTRL Bit 7:6 Name WDOG_B_CFG Type R/W S Reset Description 00 When WDOG_B is asserted to low, PMIC reset behavior 00b = WDOG_B reset is disabled 01b = Warm Reset, POR_B pin is asserted low for 20 ms 10b = Cold Reset, All voltage regulators are recycled except LDO1/ LDO2 11b = Cold Reset, All voltage regulators are recycled 5:4 PMIC_RST_CFG R/W 10 When PMIC_RST_B is asserted to low, PMIC reset behavior 00b = PMIC_RST_B reset is disabled 01b = Warm Reset, POR_B pin is asserted low for 20 ms 10b = Cold Reset, All voltage regulators are recycled except LDO1/LDO2 11b = Cold Reset, All voltage regulators are recycled 3 RSVD R/W 0 Reserved 001 PMIC_RST_B debounce time 000b = 10 ms 001b = 50 ms 010b = 100 ms 011b = 500 ms 100b = 1 sec 101b = 2 sec 110b = 4 sec 111b = 8 sec 2:0 T_PMIC_RST_DEB PCA9450 Product data sheet R/W All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 38 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 8.2.10 0x09 CONFIG1 VSYS_UVLO and LOW VSYS configuration register Table 30.0x09 CONFIG1 Reset Type 0x09 - CONFIG1 Bit 7:6 Name Type LOW_VSYS R/W S1 Reset Description 01 Low VSYS threshold above VSYS_UVLO 00b = 100 mV 01b = 200 mV 10b = 300 mV 11b = 400 mV 5:4 VSYS_UVLO R/W 01 VSYS UVLO Rising threshold 00b = 2.85 V 01b = 3.0 V 10b = 3.15 V 11b = 3.3 V 3:2 RSVD R/W 00 Reserved 1 tFLT_SD_WAIT R/W 0 Wait time for AP action when regulator fault occurs 0b = 100 ms 1b = 120 s 0 THERM_SD_DIS R/W 0 Thermal shutdown disable bit 0b = Enable Thermal shutdown 1b = Disable Thermal shutdown 8.2.11 0x0A CONFIG2 I2C Level translator control register Table 31.0x0A CONFIG2 Reset Type 0x0A - CONFIG2 O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6:4 RSVD R/W 000 Reserved 3:2 RSVD R/W 00 Reserved 00 I2C level translator enable 00b = Forced Disable 01b = Enable only when STANDBY and RUN mode 10b = Enable only when RUN mode 11b = Forced enable 1:0 I2C_LT_EN PCA9450 Product data sheet R/W All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 39 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 8.2.12 0x0C BUCK123_DVS BUCK1, BUCK2, BUCK3 DVS control register with preset value Table 32.0x0C BUCK123_DVS Reset Type 0x0C - BUCK123_DVS Bit 7 6:5 4:3 2:0 Name Type PRESET_EN R/W B3_DVS_PRESET B1_DVS_PRESET B2_DVS_PRESET R/W R/W R/W O Reset Description 1 BUCK123 output voltage selection 0b = BUCK voltage is determined by each BUCKxOUT_DVS0 or BUCKxOUT_DVS1. 1b = BUCK voltage is determined by Bx_DVS_PRESET bits. 01 BUCK3 (VPU/GPU) Preset voltage option, only for PCA9450AA. 00b = 0.8 V 01b = 0.85 V 10b = 0.9 V 11b = 0.95 V 01 BUCK1 (SOC) Preset voltage option 00b = 0.8 V 01b = 0.85 V 10b = 0.9 V 11b = 0.95 V 001 BUCK2 (ARM) Preset voltage option 000b = 0.8 V 001b = 0.85 V 010b = 0.9 V 011b = 0.95 V 100b - 111b = 1.0 V 8.2.13 0x0D BUCK1OUT_LIMIT BUCK1 output voltage limit register Table 33.0x0D BUCK1OUT_LIMIT Reset Type 0x0D - BUCK1OUT_LIMIT O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6:0 B1_LIMIT R/W 001 1100 BUCK1 output voltage limit Programmable from 0.60 V to 2.1875 V in 12.5 mV step Default = 0.95 V 8.2.14 0x0E BUCK2OUT_LIMIT BUCK2 output voltage limit register Table 34.0x0E BUCK2OUT_LIMIT Reset Type 0x0E - BUCK2OUT_LIMIT Bit Name Type Reset Description 7 RSVD R/W 0 Reserved PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 O (c) NXP B.V. 2020. All rights reserved. 40 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 34.0x0E BUCK2OUT_LIMIT...continued Reset Type 0x0E - BUCK2OUT_LIMIT O Bit Name Type Reset Description 6:0 B2_LIMIT R/W 010 0000 BUCK2 output voltage limit Programmable from 0.60 V to 2.1875 V in 12.5 mV step Default = 1.00 V 8.2.15 0x0F BUCK3OUT_LIMIT BUCK3 output voltage limit register. This register is only for PCA9450AA Table 35.0x0F BUCK3OUT_LIMIT Reset Type 0x0F - BUCK3OUT_LIMIT O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6:0 B3_LIMIT R/W 001 1100 BUCK3 output voltage limit Programmable from 0.60 V to 2.1875 V in 12.5 mV step Default = 0.95 V 8.2.16 0x10 BUCK1CTRL BUCK1 control register for Ramp, DVS control, Active discharge, FPWM and Enable. Table 36.0x10 BUCK1CTRL Reset Type 0x10 - BUCK1CTRL Bit Name Type Reset Description 7:6 RAMP R/W 01 BUCK1 DVS speed 00b = 25 mV / 1 s 01b = 25 mV / 2 s 10b = 25 mV / 4 s 11b = 25 mV / 8 s 5 RSVD R/W 0 Reserved O 4 DVS_CTRL R/W 0 DVS Control configuration 0b = BUCK voltage is determined by BUCK1VOUT_DVS0 register regardless of PMIC_STBY_REQ 1b = DVS control through PMIC_STBY_REQ 3 BUCK1AD R/W 1 BUCK1 Active discharge 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 0 Forced PWM mode 0b = Automatic PFM and PWM mode transition 1b = Forced PWM mode 01 BUCK1 enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON 2 1:0 FPWM B1_ENMODE PCA9450 Product data sheet R/W R/W All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 41 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 8.2.17 0x11 BUCK1OUT_DVS0 BUCK1 DVS output voltage at PMIC_STBY_REQ = L Table 37.0x11 BUCK1OUT_DVS0 Reset Type 0x11 - BUCK1OUT_DVS0 O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved R/W 001 0100 BUCK1 DVS0 Output voltage Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 12 Default = 0.85 V 6:0 B1_DVS0 8.2.18 0x12 BUCK1OUT_DVS1 BUCK1 DVS output voltage at PMIC_STBY_REQ = H Table 38.0x12 BUCK1OUT_DVS1 Reset Type 0x12 - BUCK1OUT_DVS1 O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6:0 B1_DVS1 R/W 001 0100 BUCK1 DVS1 Output voltage Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 12 Default = 0.85 V 8.2.19 0x13 BUCK2CTRL BUCK2 control register for Ramp, DVS control, Active discharge, FPWM and Enable. Table 39.0x13 BUCK2CTRL Reset Type 0x13 - BUCK2CTRL Bit Name Type Reset Description 7:6 RAMP R/W 01 BUCK2 DVS speed 00b = 25 mV / 1 s 01b = 25 mV / 2 s 10b = 25 mV / 4 s 11b = 25 mV / 8 s 5 RSVD R/W 0 Reserved O 4 DVS_CTRL R/W 0 DVS Control configuration 0b = BUCK voltage is determined by BUCK2VOUT_DVS0 register regardless of PMIC_STBY_REQ 1b = DVS control through PMIC_STBY_REQ 3 BUCK2AD R/W 1 BUCK2 Active discharge 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 2 FPWM R/W 0 Forced PWM mode 0b = Automatic PFM and PWM mode transition 1b = Forced PWM mode PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 42 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 39.0x13 BUCK2CTRL...continued Reset Type 0x13 - BUCK2CTRL Bit 1:0 Name Type B2_ENMODE R/W O Reset Description 10 BUCK2 enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON 8.2.20 0x14 BUCK2OUT_DVS0 BUCK2 DVS output voltage at PMIC_STBY_REQ = L Table 40.0x14 BUCK2OUT_DVS0 Reset Type 0x14 - BUCK2OUT_DVS0 O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6:0 B2_DVS0 R/W 001 0100 BUCK2 DVS0 Output voltage Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45 Default = 0.85 V 8.2.21 0x15 BUCK2OUT_DVS1 BUCK2 DVS output voltage at PMIC_STBY_REQ = H Table 41.0x15 BUCK2OUT_DVS1 Reset Type 0x15 - BUCK2OUT_DVS1 O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6:0 B2_DVS1 R/W 001 0100 BUCK2 DVS1 Output voltage Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45 Default = 0.85 V 8.2.22 0x16 BUCK3CTRL BUCK3 control register for Ramp, DVS control, Active discharge, FPWM and Enable. The registers related to BUCK3 are only for PCA9450AA. Table 42.0x16 BUCK3CTRL Reset Type 0x16 - BUCK3CTRL Bit Name Type Reset Description 7:6 RAMP R/W 01 BUCK3 DVS speed 00b = 25 mV / 1 s 01b = 25 mV / 2 s 10b = 25 mV / 4 s 11b = 25 mV / 8 s 5 RSVD R/W 0 Reserved PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 O (c) NXP B.V. 2020. All rights reserved. 43 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 42.0x16 BUCK3CTRL...continued Reset Type 0x16 - BUCK3CTRL Bit Name Type Reset Description O 4 DVS_CTRL R/W 0 DVS Control configuration 0b = BUCK voltage is determined by BUCK3VOUT_DVS0 register regardless of PMIC_STBY_REQ 1b = DVS control through PMIC_STBY_REQ 3 BUCK3AD R/W 1 BUCK3 Active discharge 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 2 FPWM R/W 0 Forced PWM mode 0b = Automatic PFM and PWM mode transition 1b = Forced PWM mode 01 BUCK3 enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON 1:0 B3_ENMODE R/W 8.2.23 0x17 BUCK3OUT_DVS0 BUCK3 DVS output voltage at PMIC_STBY_REQ = L Table 43.0x17 BUCK3OUT_DVS0 Reset Type 0x17 - BUCK3OUT_DVS0 O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6:0 B3_DVS0 R/W 001 0100 BUCK3 DVS0 Output voltage Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45 Default = 0.85 V 8.2.24 0x18 BUCK3OUT_DVS1 BUCK3 DVS output voltage a PMIC_STBY_REQ = H Table 44.0x18 BUCK3OUT_DVS1 Reset Type 0x18 - BUCK3OUT_DVS1 O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved R/W 001 0100 BUCK3 DVS1 Output voltage Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45 Default = 0.85 V 6:0 B3_DVS1 PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 44 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 45.BUCK1, BUCK2, BUCK3 Output voltage table Code Voltage Code Voltage Code Voltage Code Voltage 0x00 0.6000 V 0x20 1.0000 V 0x40 1.4000 V 0x60 1.8000 V 0x01 0.6125 V 0x21 1.0125 V 0x41 1.4125 V 0x61 1.8125 V 0x02 0.6250 V 0x22 1.0250 V 0x42 1.4250 V 0x62 1.8250 V 0x03 0.6375 V 0x23 1.0375 V 0x43 1.4375 V 0x63 1.8375 V 0x04 0.6500 V 0x24 1.0500 V 0x44 1.4500 V 0x64 1.8500 V 0x05 0.6625 V 0x25 1.0625 V 0x45 1.4625 V 0x65 1.8625 V 0x06 0.6750 V 0x26 1.0750 V 0x46 1.4750 V 0x66 1.8750 V 0x07 0.6875 V 0x27 1.0875 V 0x47 1.4875 V 0x67 1.8875 V 0x08 0.7000 V 0x28 1.1000 V 0x48 1.5000 V 0x68 1.9000 V 0x09 0.7125 V 0x29 1.1125 V 0x49 1.5125 V 0x69 1.9125 V 0x0A 0.7250 V 0x2A 1.1250 V 0x4A 1.5250 V 0x6A 1.9250 V 0x0B 0.7375 V 0x2B 1.1375 V 0x4B 1.5375 V 0x6B 1.9375 V 0x0C 0.7500 V 0x2C 1.1500 V 0x4C 1.5500 V 0x6C 1.9500 V 0x0D 0.7625 V 0x2D 1.1625 V 0x4D 1.5625 V 0x6D 1.9625 V 0x0E 0.7750 V 0x2E 1.1750 V 0x4E 1.5750 V 0x6E 1.9750 V 0x0F 0.7875 V 0x2F 1.1875 V 0x4F 1.5875 V 0x6F 1.9875 V 0x10 0.8000 V 0x30 1.2000 V 0x50 1.6000 V 0x70 2.0000 V 0x11 0.8125 V 0x31 1.2125 V 0x51 1.6125 V 0x71 2.0125 V 0x12 0.8250 V 0x32 1.2250 V 0x52 1.6250 V 0x72 2.0250 V 0x13 0.8375 V 0x33 1.2375 V 0x53 1.6375 V 0x73 2.0375 V 0x14 0.8500 V 0x34 1.2500 V 0x54 1.6500 V 0x74 2.0500 V 0x15 0.8625 V 0x35 1.2625 V 0x55 1.6625 V 0x75 2.0625 V 0x16 0.8750 V 0x36 1.2750 V 0x56 1.6750 V 0x76 2.0750 V 0x17 0.8875 V 0x37 1.2875 V 0x57 1.6875 V 0x77 2.0875 V 0x18 0.9000 V 0x38 1.3000 V 0x58 1.7000 V 0x78 2.1000 V 0x19 0.9125 V 0x39 1.3125 V 0x59 1.7125 V 0x79 2.1125 V 0x1A 0.9250 V 0x3A 1.3250 V 0x5A 1.7250 V 0x7A 2.1250 V 0x1B 0.9375 V 0x3B 1.3375 V 0x5B 1.7375 V 0x7B 2.1375 V 0x1C 0.9500 V 0x3C 1.3500 V 0x5C 1.7500 V 0x7C 2.1500 V 0x1D 0.9625 V 0x3D 1.3625 V 0x5D 1.7625 V 0x7D 2.1625 V 0x1E 0.9750 V 0x3E 1.3750 V 0x5E 1.7750 V 0x7E 2.1750 V 0x1F 0.9875 V 0x3F 1.3875 V 0x5F 1.7875 V 0x7F 2.1875 V 8.2.25 0x19 BUCK4CTRL BUCK4 control register for Active discharge, FPWM and Enable. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 45 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 46.0x19 BUCK4CTRL Reset Type 0x19 - BUCK4CTRL O Bit Name Type Reset Description 7:4 RSVD R/W 0000 Reserved 3 BUCK4AD R/W 1 BUCK4 Active discharge 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 2 FPWM R/W 0 Forced PWM mode 0b = Automatic PFM and PWM mode transition 1b = Forced PWM mode 01 BUCK4 enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON 1:0 B4_ENMODE R/W 8.2.26 0x1A BUCK4OUT BUCK4 output voltage configuration register Table 47.0x1A BUCK4OUT Reset Type 0x1A - BUCK4OUT O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6:0 B4_OUT R/W 110 1100 BUCK4 Output voltage Programmable from 0.60 V to 3.40 V in 25 mV step. Table 52 Default = 3.3 V 8.2.27 0x1B BUCK5CTRL BUCK5 control register for Active discharge, FPWM and Enable. Table 48.0x1B BUCK5CTRL Reset Type 0x1B - BUCK5CTRL Bit Name Type Reset Description 7:4 RSVD R/W 0000 Reserved O 3 BUCK5AD R/W 1 BUCK5 Active discharge 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 2 FPWM R/W 0 Forced PWM mode 0b = Automatic PFM and PWM mode transition 1b = Forced PWM mode 01 BUCK5 enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON 1:0 B5_ENMODE PCA9450 Product data sheet R/W All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 46 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 8.2.28 0x1C BUCK5OUT BUCK5 output voltage configuration register Table 49.0x1C BUCK5OUT Reset Type 0x1C - BUCK5OUT O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved R/W 011 0000 BUCK5 Output voltage Programmable from 0.60 V to 3.40 V in 25 mV step. Table 52 Default = 1.8 V 6:0 B5_OUT 8.2.29 0x1D BUCK6CTRL BUCK6 control register for Active discharge, FPWM and Enable. Table 50.0x1D BUCK6CTRL Reset Type 0x1D - BUCK6OUT O Bit Name Type Reset Description 7:4 RSVD R/W 0000 Reserved 3 BUCK6AD R/W 1 BUCK6 Active discharge 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 2 FPWM R/W 0 Forced PWM mode 0b = Automatic PFM and PWM mode transition 1b = Forced PWM mode 01 BUCK6 enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON 1:0 B6_ENMODE R/W 8.2.30 0x1E BUCK6OUT BUCK6 output voltage configuration register Table 51.0x1E BUCK6OUT Reset Type 0x1E - BUCK6CTRL O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved R/W 001 0100 BUCK6 Output voltage Programmable from 0.60 V to 3.40 V in 25 mV step. Table 52 Default = 1.1 V 6:0 B6_OUT PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 47 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 52.BUCK4, BUCK5, BUCK6 Output voltage table Code Voltage Code Voltage Code Voltage Code Voltage 0x00 0.600 V 0x20 1.400 V 0x40 2.200 V 0x60 3.000 V 0x01 0.625 V 0x21 1.425 V 0x41 2.225 V 0x61 3.025 V 0x02 0.650 V 0x22 1.450 V 0x42 2.250 V 0x62 3.050 V 0x03 0.675 V 0x23 1.475 V 0x43 2.275 V 0x63 3.075 V 0x04 0.700 V 0x24 1.500 V 0x44 2.300 V 0x64 3.100 V 0x05 0.725 V 0x25 1.525 V 0x45 2.325 V 0x65 3.125 V 0x06 0.750 V 0x26 1.550 V 0x46 2.350 V 0x66 3.150 V 0x07 0.775 V 0x27 1.575 V 0x47 2.375 V 0x67 3.175 V 0x08 0.800 V 0x28 1.600 V 0x48 2.400 V 0x68 3.200 V 0x09 0.825 V 0x29 1.625 V 0x49 2.425 V 0x69 3.225 V 0x0A 0.850 V 0x2A 1.650 V 0x4A 2.450 V 0x6A 3.250 V 0x0B 0.875 V 0x2B 1.675 V 0x4B 2.475 V 0x6B 3.275 V 0x0C 0.900 V 0x2C 1.700 V 0x4C 2.500 V 0x6C 3.300 V 0x0D 0.925 V 0x2D 1.725 V 0x4D 2.525 V 0x6D 3.325 V 0x0E 0.950 V 0x2E 1.750 V 0x4E 2.550 V 0x6E 3.350 V 0x0F 0.975 V 0x2F 1.775 V 0x4F 2.575 V 0x6F 3.375 V 0x10 1.000 V 0x30 1.800 V 0x50 2.600 V 0x70 3.400 V 0x11 1.025 V 0x31 1.825 V 0x51 2.625 V 0x71 3.400 V 0x12 1.050 V 0x32 1.850 V 0x52 2.650 V 0x72 3.400 V 0x13 1.075 V 0x33 1.875 V 0x53 2.675 V 0x73 3.400 V 0x14 1.100 V 0x34 1.900 V 0x54 2.700 V 0x74 3.400 V 0x15 1.125 V 0x35 1.925 V 0x55 2.725 V 0x75 3.400 V 0x16 1.150 V 0x36 1.950 V 0x56 2.750 V 0x76 3.400 V 0x17 1.175 V 0x37 1.975 V 0x57 2.775 V 0x77 3.400 V 0x18 1.200 V 0x38 2.000 V 0x58 2.800 V 0x78 3.400 V 0x19 1.225 V 0x39 2.025 V 0x59 2.825 V 0x79 3.400 V 0x1A 1.250 V 0x3A 2.050 V 0x5A 2.850 V 0x7A 3.400 V 0x1B 1.275 V 0x3B 2.075 V 0x5B 2.875 V 0x7B 3.400 V 0x1C 1.300 V 0x3C 2.100 V 0x5C 2.900 V 0x7C 3.400 V 0x1D 1.325 V 0x3D 2.125 V 0x5D 2.925 V 0x7D 3.400 V 0x1E 1.350 V 0x3E 2.150 V 0x5E 2.950 V 0x7E 3.400 V 0x1F 1.375 V 0x3F 2.175 V 0x5F 2.975 V 0x7F 3.400 V PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 48 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 8.2.31 0x20 LDO_AD_CTRL LDO active discharge resistor configuration register Table 53.0x20 LDO_AD_CTRL Reset Type 0x20 - LDO_AD_CTRL O Bit Name Type Reset Description 7 LDO1_AD R/W 1 LDO1 Active discharge enable 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 6 LDO2_AD R/W 1 LDO2 Active discharge enable 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 5 LDO3_AD R/W 1 LDO3 Active discharge enable 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 4 LDO4_AD R/W 1 LDO4 Active discharge enable 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 3 LDO5_AD R/W 1 LDO5 Active discharge enable 0b = Always disable Active discharge resistor 1b = Enable Active discharge resistor when regulator is OFF 2 RSVD R/W 0 Reserved 1 RSVD R/W 0 Reserved 0 RSVD R/W 0 Reserved 8.2.32 0x21 LDO1CTRL LDO1 control register for enable and voltage Table 54.0x21 LDO1CTRL Reset Type 0x21 - LDO1CTRL Bit Name Type Reset Description O 7:6 ENMODE R/W 11 LDO1 Enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON * When LDO1 is turned off, PCA9450/A transitions to READY mode 5:3 RSVD R/W 000 Reserved PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 49 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 54.0x21 LDO1CTRL...continued Reset Type 0x21 - LDO1CTRL Bit 2:0 Name Type L1_OUT R/W O Reset Description 010 LDO1 output voltage Programmable from 1.6 V - 1.9 V, 3.0 V - 3.3 V in 100 mV step 000b = 1.6 V 001b = 1.7 V 010b = 1.8 V 011b = 1.9 V 100b = 3.0 V 101b = 3.1 V 110b = 3.2 V 111b = 3.3 V 8.2.33 0x22 LDO2CTRL LDO2 control register for enable and voltage Table 55.0x22 LDO2CTRL Reset Type 0x22 - LDO2CTRL Bit Name Type Reset Description O 7:6 ENMODE R/W 11 LDO2 Enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON * When LDO2 is turned off, PCA9450/A transitions to READY mode 5:3 RSVD R/W 000 Reserved 001 LDO2 output voltage Programmable from 0.8 V to 1.15 V in 50 mV step 000b = 0.8 V 001b = 0.85 V 010b = 0.9 V 011b = 0.95 V 100b = 1.0 V 101b = 1.05 V 110b = 1.1 V 111b = 1.15 V 2:0 L2_OUT R/W 8.2.34 0x23 LDO3CTRL LDO3 control register for enable and voltage PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 50 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 56.0x23 LDO3CTRL Reset Type 0x23 - LDO3CTRL Bit Name Type Reset Description O 7:6 ENMODE R/W 01 LDO3 Enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON 5 RSVD R/W 0 Reserved 4:0 L3_OUT R/W 0 1010 LDO3 output voltage Programmable from 0.8 V to 3.3 V in 100 mV step, see Table 57 Table 57.LDO3 output voltage 0x00 : 0.80 V 0x8 : 1.60 V 0x10 : 2.40 V 0x18 : 3.20 V 0x01 : 0.90 V 0x9 : 1.70 V 0x11 : 2.50 V 0x19 : 3.30 V 0x02 : 1.00 V 0xA : 1.80 V 0x12 : 2.60 V 0x1A : 3.30 V 0x03 : 1.10 V 0xB : 1.90 V 0x13 : 2.70 V 0x1B : 3.30 V 0x04 : 1.20 V 0xC : 2.00 V 0x14 : 2.80 V 0x1C : 3.30 V 0x05 : 1.30 V 0xD : 2.10 V 0x15 : 2.90 V 0x1D : 3.30 V 0x06 : 1.40 V 0xE : 2.20 V 0x16 : 3.00 V 0x1E : 3.30 V 0x07 : 1.50 V 0xF : 2.30 V 0x17 : 3.10 V 0x1F : 3.30 V 8.2.35 0x24 LDO4CTRL LDO4 control register for enable and voltage Table 58.0x24 LDO4CTRL Reset Type 0x24 - LDO4CTRL Bit Name Type Reset Description O 7:6 ENMODE R/W 01 LDO4 Enable mode 00b = OFF (PCA9450B/PCA9450C) 01b = ON by PMIC_ON_REQ = H (PCA9450AA) 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON 5 RSVD R/W 0 Reserved 4:0 L4_OUT R/W 0 0001 LDO4 output voltage Programmable from 0.8 V to 3.3 V in 100 mV step, see Table 59 Table 59.LDO4 output voltage PCA9450 Product data sheet 0x00 : 0.80 V 0x8 : 1.60 V 0x10 : 2.40 V 0x18 : 3.20 V 0x01 : 0.90 V 0x9 : 1.70 V 0x11 : 2.50 V 0x19 : 3.30 V 0x02 : 1.00 V 0xA : 1.80 V 0x12 : 2.60 V 0x1A : 3.30 V All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 51 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 59.LDO4 output voltage...continued 0x03 : 1.10 V 0xB : 1.90 V 0x13 : 2.70 V 0x1B : 3.30 V 0x04 : 1.20 V 0xC : 2.00 V 0x14 : 2.80 V 0x1C : 3.30 V 0x05 : 1.30 V 0xD : 2.10 V 0x15 : 2.90 V 0x1D : 3.30 V 0x06 : 1.40 V 0xE : 2.20 V 0x16 : 3.00 V 0x1E : 3.30 V 0x07 : 1.50 V 0xF : 2.30 V 0x17 : 3.10 V 0x1F : 3.30 V 8.2.36 0x25 LDO5CTRL_L LDO5 control register for enable and voltage when SD_VSEL is low Table 60.0x25 LDO5CTRL_L Reset Type 0x25 - LDO5CTRL_L Bit Name Type Reset Description O 7:6 ENMODE R/W 01 LDO5 Enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON 5:4 RSVD R/W 00 Reserved 3:0 L5_OUT_L R/W 1111 LDO5 output voltage when SD_VSEL = Low Programmable from 1.8 V to 3.3 V in 100 mV step, see Table 61 Table 61.LDO5 output voltage when SD_VSEL = Low 0x00 : 1.80 V 0x4 : 2.20 V 0x8 : 2.60 V 0xC : 3.00 V 0x01 : 1.90 V 0x5 : 2.30 V 0x9 : 2.70 V 0xD : 3.10 V 0x02 : 2.00 V 0x6 : 2.40 V 0xA : 2.80 V 0xE : 3.20 V 0x03 : 2.10 V 0x7 : 2.50 V 0xB : 2.90 V 0xF : 3.30 V 8.2.37 0x26 LDO5CTRL_H LDO5 control register for enable and voltage when SD_VSEL is High Table 62.0x26 LDO5CTRL_H Reset Type 0x26 - LDO5CTRL_H O Bit Name Type Reset Description 7:6 RSVD R/W 00 Reserved 5:4 RSVD R/W 00 Reserved 3:0 L5_OUT_H R/W 0000 LDO5 output voltage when SD_VSEL = High Programmable from 1.8 V to 3.3 V in 100 mV step, see Table 63 Table 63.LDO5 output voltage when SD_VSEL = High 0x00 : 1.80 V PCA9450 Product data sheet 0x4 : 2.20 V 0x8 : 2.60 V All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 0xC : 3.00 V (c) NXP B.V. 2020. All rights reserved. 52 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 63.LDO5 output voltage when SD_VSEL = High...continued 0x01 : 1.90 V 0x5 : 2.30 V 0x9 : 2.70 V 0xD : 3.10 V 0x02 : 2.00 V 0x6 : 2.40 V 0xA : 2.80 V 0xE : 3.20 V 0x03 : 2.10 V 0x7 : 2.50 V 0xB : 2.90 V 0xF : 3.30 V 8.2.38 0x2A LOADSW_CTRL Load switch control register for active discharge, short/over current and enable Table 64.0x2A LOADSW_CTRL Reset Type 0x2A - LOADSW_CTRL O Bit Name Type Reset Description 7 SW_AD R/W 1 Load switch active discharge 0b = Always disable active discharge resistor 1b = Enable active discharge resistor when it is OFF 6:5 RSVD R/W 00 Reserved 4 SW_SC R/W 0 When switch detects short circuit current 0b = Turned OFF and set SWEN[1:0] are set to 00b automatically 1b = Turned off and restart in 100 ms 01 When load switch detects over current 00b = Turned OFF and set SWEN[1:0] are set to 00b automatically 01b = Turned off and restart in 100 ms 10b, 11b = stay ON 01 SW Enable control 00b = Forced OFF 01b = Enabled by SW_EN pin 10b = Forced ON 11b = Forced ON 3:2 1:0 SW_OC R/W SWEN R/W 8.2.39 0x2B VRFLT1_STS Voltage regulator fault status register. It is latched to 1 once corresponding regulator detects fault. If the bit is overwritten to 1, the corresponding bit is newly updated by current status. Table 65.0x2B VRFLT1_STS Reset Type 0x2B - VRFLT1_STS Bit Name Type Reset Description S 7 SW_OCP R/W/C 0 Load SW OCP status, deglitched with tDEB_POKB_SW 0 = Load SW doesn't exceed current limit or is OFF 1 = Load SW exceeded current limit 6 RSVD R/W/C 0 Reserved 5 BUCK6_FLT R/W/C 0 BUCK6 Fault status, deglitched with tDEB_POKB 0b = BUCK6 output is good or BUCK6 is OFF 1b = BUCK6 output falls below 80 % of target PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 53 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 65.0x2B VRFLT1_STS...continued Reset Type 0x2B - VRFLT1_STS S Bit Name Type Reset Description 4 BUCK5_FLT R/W/C 0 BUCK5 Fault status, deglitched with tDEB_POKB 0b = BUCK5 output is good or BUCK5 is OFF 1b = BUCK5 output falls below 80 % of target 3 BUCK4_FLT R/W/C 0 BUCK4 Fault status, deglitched with tDEB_POKB 0b = BUCK4 output is good or BUCK4 is OFF 1b = BUCK4 output is below 80 % 2 BUCK3_FLT R/W/C 0 BUCK3 Fault status, deglitched with tDEB_POKB 0b = BUCK3 output is good or BUCK3 is OFF 1b = BUCK3 output falls below 80 % of target 1 BUCK2_FLT R/W/C 0 BUCK2 Fault status, deglitched with tDEB_POKB 0b = BUCK2 output is good or BUCK2 is OFF 1b = BUCK2 output falls below 80 % of target 0 BUCK1_FLT R/W/C 0 BUCK1 Fault status, deglitched with tDEB_POKB 0b = BUCK1 output is good or BUCK1 is OFF 1b = BUCK1 output falls below 80 % of target 8.2.40 0x2C VRFLT2_STS Voltage regulator fault status register. It is latched to 1 once corresponding regulator detects fault. If the bit is overwritten to 1, the corresponding bit is newly updated by current status. Table 66.0x2C VRFLT2_STS Reset Type 0x2C - VRFLT2_STS S Bit Name Type Reset Description 7:5 RSVD R/W/C 000 Reserved 4 LDO5_FLT R/W/C 0 LDO5 Fault status, deglitched with tDEB_POKB 0b = LDO5 output is good or LDO5 is OFF 1b = LDO5 output falls below 80 % of target 3 LDO4_FLT R/W/C 0 LDO4 Fault status, deglitched with tDEB_POKB 0b = LDO4 output is good or LDO4 is OFF 1b = LDO4 output falls below 80 % of target 2 LDO3_FLT R/W/C 0 LDO3 Fault status, deglitched with tDEB_POKB 0b = LDO3 output is good or LDO3 is OFF 1b = LDO3 output falls below 80 % of target 1 LDO2_FLT R/W/C 0 LDO2 Fault status, deglitched with tDEB_POKB 0b = LDO2 output is good or LDO2 is OFF 1b = LDO2 output falls below 80 % of target 0 LDO1_FLT R/W/C 0 LDO1 Fault status, deglitched with tDEB_POKB 0b = LDO1 output is good or LDO1 is OFF 1b = LDO1 output falls below 80 % of target PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 54 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 8.2.41 0x2D VRFLT1_MASK VR fault mask bit. Once the bit is masked, PCA9450 doesn't enter Fault shutdown even if fault condition of corresponding regulator happens Table 67.0x2D VRFLT1_MASK Reset Type 0x2D - VRFLT1_MASK Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6 RSVD R/W 0 Reserved 5 BUCK6_FLT_M R/W 1 BUCK6 FLT mask 0b = Unmask 1b = Masked 4 BUCK5_FLT_M R/W 1 BUCK5 FLT mask 0b = Unmask 1b = Masked 3 BUCK4_FLT_M R/W 1 BUCK4 FLT mask 0b = Unmask 1b = Masked 2 BUCK3_FLT_M R/W 1 BUCK3 FLT mask 0b = Unmask 1b = Masked 1 BUCK2_FLT_M R/W 1 BUCK2 FLT mask 0b = Unmask 1b = Masked 0 BUCK1_FLT_M R/W 1 BUCK1 FLT mask 0b = Unmask 1b = Masked S 8.2.42 0x2E VRFLT2_MASK VR fault mask bit. Once the bit is masked, PCA9450 doesn't enter Fault shutdown even if fault condition of corresponding regulator happens Table 68.0x2E VRFLT2_MASK Reset Type 0x2E - VRFLT2_MASK Bit Name Type Reset Description 7 RSVD R/W/C 0 Reserved 6 RSVD R/W/C 0 Reserved 5 RSVD R/W/C 0 Reserved 4 LDO5_FLT_M R/W 1 LDO5 FLT mask 0b = Unmask 1b = Masked 1 LDO4 FLT mask 0b = Unmask 1b = Masked 3 LDO4_FLT_M PCA9450 Product data sheet R/W All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 S (c) NXP B.V. 2020. All rights reserved. 55 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 68.0x2E VRFLT2_MASK...continued Reset Type 0x2E - VRFLT2_MASK Bit Name Type Reset Description 2 LDO3_FLT_M R/W 1 LDO3 FLT mask 0b = Unmask 1b = Masked 1 LDO2_FLT_M R/W 1 LDO2 FLT mask 0b = Unmask 1b = Masked 0 LDO1_FLT_M R/W 1 LDO1 FLT mask 0b = Unmask 1b = Masked PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 S (c) NXP B.V. 2020. All rights reserved. 56 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 9 Application design-in information 9.1 Reference schematic 9.1.1 PCA9450AA reference schematic PCA9450AA reference schematic with i.MX 8M Mini is illustrated in Figure 21. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 57 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family VSYS SYS C1 1 F VINT C2 1 F PCA9450AA INT LDO LDO1 SBIAS, REF, UVLO, TSHDN INB26 DVS BUCK2 0.85 V 3A PMIC_RST_B PMIC_ON_REQ R1 100 k BUCK1 0.85 V 3A RTC_RESET_B POR_B DUAL PHASE CONFIG IN PCA9450 R4 100 k SCL l2C INTERFACE SDA R5 4.7 k i.MX 8M Mini R7 4.7 k INB13 DVS C15 10 F VDD_VPU VDD_GPU VDD_DRAM (1) PGND R_SNSP3_CFG INB45 LX4 ON/OFF CONTROL AND I2C REGISTER BUCK4 3.3 V 3A i.MX 8M Mini XTAL_OUT C4 INB45 MUX INL1 LDO1 VDD_SNVS LDO2 C7 1 F VDDA LDO3 C8 2.2 F NVCC_3V3 C18 22 F BUCK4FB 32.768 kHz X-TAL DRIVER CLK_32K_OUT C6 1 F VSYS PGND LDO1 C5 4.7 F C17 10 F L4 0.47 H XTAL_IN NVCC_SNVS VSYS L3 C16 0.47 H 22 F l2C LEVEL TRANSLATOR SDAH C3 SYS (1) PGND SWIN SCLH RTC_XTALI VDD_SOC L2 C14 0.47 H 22 F SCLL R8 4.7 k X1, X-tal VSYS R_SNSP1 BUCK3 0.85 V 3A VINT R6 4.7 k SDAL 3V3 V BUCK4 C13 10 F LX3 IRQ_B NVCC_1V8 BUCK5 INB13 DVS LX1 R3 4.7 k (1) PGND LDO1 R2 4.7 k VDD_ARM R_SNSP2 WDOG_B NVCC_1V8 BUCK5 VSYS L1 C12 0.47 H 22 F PMIC_STBY_REQ NVCC_SNVS LDO1 C11 10 F LX2 LX5 BUCK5 1.8 V 2A LDO1 1.8 V 10 mA C19 4.7 F VSYS NVCC_1V8 L5 0.47 H C20 22 F PGND BUCK5FB INB26 LDO2 0.8 V 10 mA LX6 C21 4.7 F BUCK6 1.1 V 2A LDO3 1.8 V 300 mA VSYS NVCC_DRAM L6 0.47 H C22 22 F PGND BUCK6FB VDD_MIPI_0P9 LDO4 C9 1 F NVCC_SD2 LDO5 C10 1 F LDO4 0.9 V 200 mA SWIN LOAD SW DRIVER LDO5 3.3 V/1.8 V 150 mA VDD_MIPI_1P2 LDO 1.2 V 150 mA SWOUT BUCK 4 SD_CARD C24 1 F SD_VSEL IN C23 1 F SD_CARD SW_EN BUCK4 EN BUCK_AGND AGND EP aaa-035724 (1) This capacitor is decoupling capacitor in MCU side. Figure 21.PCA9450AA application schematic PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 58 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 9.1.2 PCA9450B reference schematic PCA9450B reference schematic with i.MX 8M Nano is illustrated in Figure 22. SYS VSYS C1 1 F VINT C2 1 F PCA9450B INT LDO LDO1 SBIAS, REF, UVLO, TSHDN INB26 DVS BUCK2 0.85 V 3A PMIC_RST_B PMIC_ON_REQ POR_B DUAL PHASE CONFIG IN PCA9450 R4 100 k SCL l2C INTERFACE SDA R5 4.7 k SCLL SDAL i.MX 8M Nano R7 4.7 k R8 4.7 k XTAL_OUT SYS NVCC_SNVS R_SNSP3_CFG INB45 LX4 ON/OFF CONTROL AND I2C REGISTER BUCK4 3.3 V 3A VDD_SNVS LDO2 C7 1 F VDDA LDO3 C8 2.2 F NVCC_3V3 C18 22 F BUCK4FB INB45 MUX INL1 LDO1 VSYS PGND 32.768 kHz X-TAL DRIVER CLK_32K_OUT C6 1 F C17 10 F i.MX 8M Nano L4 0.47 H LDO1 C5 4.7 F VSYS PGND XTAL_IN C4 RTC_XTALI INB13 DVS l2C LEVEL TRANSLATOR SCLH X1, X-tal (1) PGND SWIN SDAH C3 L2 C14 0.47 H 22 F R_SNSP1 BUCK3 0.85 V 3A VINT R6 4.7 k VDD_SOC VDD_VPU VDD_GPU VDD_DRAM VSYS LX3 IRQ_B 3V3 V BUCK4 C13 10 F LX1 BUCK1 0.85 V 3A RTC_RESET_B NVCC_1V8 BUCK5 INB13 DVS R1 100 k R3 4.7 k (1) PGND LDO1 R2 4.7 k VDD_ARM R_SNSP2 WDOG_B NVCC_1V8 BUCK5 VSYS L1 C12 0.47 H 22 F PMIC_STBY_REQ NVCC_SNVS LDO1 C11 10 F LX2 LX5 BUCK5 1.8 V 2A LDO1 1.8 V 10 mA C19 4.7 F VSYS NVCC_1V8 L5 0.47 H C20 22 F PGND BUCK5FB INB26 LDO2 0.8 V 10 mA LX6 C21 4.7 F NVCC_DRAM L6 0.47 H BUCK6 1.1 V 2A LDO3 1.8 V 300 mA VSYS C22 22 F PGND BUCK6FB VDD_MIPI_1P2 LDO4 C9 1 F NVCC_SD2 LDO5 C10 1 F LDO4 0.9 V 200 mA SWIN LOAD SW DRIVER LDO5 3.3 V/1.8 V 150 mA C23 1 F SWOUT SD_CARD C24 1 F SD_VSEL BUCK 4 SD_CARD SW_EN VDD_MIPI_0P9 BUCK_AGND AGND EP aaa-035725 (1) This capacitor is decoupling capacitor in MCU side. Figure 22.PCA9450B application schematic PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 59 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 9.1.3 PCA9450C reference schematic PCA9450C reference schematic with i.MX 8M Plus is illustrated in Figure 23 SYS VSYS C1 1 F VINT C2 1 F PCA9450C INT LDO LDO1 SBIAS, REF, UVLO, TSHDN INB26 DVS BUCK2 0.85 V 3A PMIC_RST_B PMIC_ON_REQ POR_B DUAL PHASE CONFIG IN PCA9450 R4 100 k SCL l2C INTERFACE SDA R5 4.7 k i.MX 8M Plus R8 4.7 k INB45 LX4 ON/OFF CONTROL AND I2C REGISTER BUCK4 3.3 V 3A i.MX 8M Plus INB45 MUX INL1 LDO1 LDO2 C7 1 F VDDA LDO3 C8 2.2 F NVCC_3V3 C18 22 F BUCK4FB CLK_32K_OUT C6 1 F VSYS PGND LDO1 C5 4.7 F C17 10 F L4 0.47 H 32.768 kHz X-TAL DRIVER XTAL_OUT C4 NVCC_SNVS C16 22 F R_SNSP3_CFG l2C LEVEL TRANSLATOR SCLH SYS VSYS PGND XTAL_IN X1, X-tal C15 10 F L3 0.47 H SWIN SDAH C3 RTC_XTALI INB13 DVS SCLL SDAL R7 4.7 k (1) PGND R_SNSP1 BUCK3 0.85 V 3A VINT R6 4.7 k VDD_SOC VDD_VPU VDD_GPU VDD_DRAM VSYS L2 C14 0.47 H 22 F LX3 IRQ_B 3V3 V BUCK4 C13 10 F LX1 BUCK1 0.85 V 3A RTC_RESET_B NVCC_1V8 BUCK5 INB13 DVS R1 100 k R3 4.7 k (1) PGND LDO1 R2 4.7 k VDD_ARM R_SNSP2 WDOG_B NVCC_1V8 BUCK5 VSYS L1 C12 0.47 H 22 F PMIC_STBY_REQ NVCC_SNVS LDO1 C11 10 F LX2 LX5 BUCK5 1.8 V 2A LDO1 1.8 V 10 mA C19 4.7 F VSYS NVCC_1V8 L5 0.47 H C20 22 F PGND BUCK5FB INB26 LDO2 0.8 V 10 mA LX6 BUCK6 1.1 V 2A LDO3 1.8 V 300 mA C21 4.7 F VSYS NVCC_DRAM L6 0.47 H C22 22 F PGND BUCK6FB LDO4 C9 1 F NVCC_SD2 LDO5 C10 1 F LDO4 0.9 V 200 mA SWIN LOAD SW DRIVER LDO5 3.3 V/1.8 V 150 mA C23 1 F SWOUT SD_CARD C24 1 F SD_VSEL BUCK 4 SD_CARD SW_EN BUCK_AGND AGND EP aaa-035726 (1) This capacitor is decoupling capacitor in MCU side. Figure 23.PCA9450C application schematic PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 60 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 9.2 Typical application Please follow the recommendations below for your schematic/PCB layout design: * 1 F bypass capacitor on VINT and VSYS, located as close as possible to those pins to ground * Input capacitors must be present on the INB and INL supplies if used * Output inductors and capacitors must be used on the outputs of the BUCK converters if used * Output capacitors must be used on the outputs of the LDOs 9.2.1 Buck regulators 9.2.1.1 Inductor selection for buck converters Each of the converters on PCA9450 typically uses a 0.47 H output inductor which has to be rated for its DC resistance and saturation current. The DC resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest DC resistance must be selected for highest efficiency. Equation 1 calculates the maximum inductor current under static load conditions. The saturation current of the inductor must be rated higher than the maximum inductor current as calculated with Equation 2. This is needed because during heavy load transient the inductor current rises above the calculated value. (1) (2) Where * * * * f = switching frequency (2 MHz) L = Inductance IL = Peak to peak inductor ripple current IL.max = Maximum inductor current A conservative approach is to select the inductor current rating just for the maximum switch current of the PCA9450 Table 69 shows possible inductors list. Table 69.Tested inductor list Buck Vendor Part number Size DCR [m] Isat [A] Itemp [A] BUCK1, BUCK2, BUCK3, BUCK4 Sunlord WPN252012HR47MT 2520 29 5.6 4.0 Murata 1239AS-H-R47M 2520 39 3.8 3.7 BUCK5, BUCK6 Sunlord WPN201610UR47MT 2016 28 5.0 4.1 PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 61 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 69.Tested inductor list...continued Buck Vendor Part number Size DCR [m] Isat [A] Itemp [A] Murata 1286AS-H-R47M 2016 52 3.4 3.2 9.2.1.2 Output capacitor selection for buck converters The fast response adaptive constant ON time control scheme of the buck converters implemented on PCA9450 allows the use of a single typical 22 F ceramic capacitor for each converter output without compromising on output overshoot/undershoot voltage ripple during heavy load transients. Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. Just for completeness, the RMS ripple current is calculated in Equation 3. (3) At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: (4) Where * The highest output voltage ripple occurs at the highest input voltage Vin. At light load currents, the converters operate in PFM mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1 % of the nominal output voltage. 9.2.1.3 Input capacitor selection for buck converters Low ESR input capacitor is highly recommended for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes because of the nature of buck converter. Each DC-DC converter requires a 10 F ceramic input capacitor on its input pins. The input capacitor could be increased without any limit for better input voltage filtering. 9.2.2 Crystal oscillator 9.2.2.1 Crystal selection The most important parameters when choosing a crystal are: PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 62 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family * Crystal's required effective load capacitance (typically 6 pF to 15 pF) * Crystal's ESR (typically 30 k to 100 k) * Tolerance (typically 5 ppm to 30 ppm) All of these crystal parameters can usually be found in the crystal datasheet. 9.2.2.2 Effective load capacitance The crystal oscillator (see Figure 24) uses two load capacitors, CL1 and CL2, as load for the crystal. These capacitors generate, together with the crystal's inductance, the required 180 phase shift of the feedback loop. 180 XTAL_OUT XTAL_IN 32.768 kHz Xtal CL1_P CL1 CL2 180 C L2_P aaa-035750 Figure 24.Crystal oscillator From the view of the crystal, these capacitors are a serial connection through GND. Hence, if using two equal capacitors, the values of these capacitors must be twice the required load capacitance. It is also important to consider PCB parasitic capacitances for the calculation of the necessary capacitors according to Equation 5. (5) Where: * C'L1 = CL1 + CL1_P, CL1_P is PCB parasitic capacitance. * C'L2 = CL2 + CL2_P , CL2_P is PCB parasitic capacitance. When using equal capacitors for CL1 and CL2 and a symmetric layout with equal parasitic capacitance on both crystal pins, the effective load capacitance is shown in Equation 6. (6) Example: PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 63 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Crystal requires 12 pF load. Parasitic capacitance per pin is 2 pF. CL1 = (2 x CLoad) - CL1_P = (2 x 12 pF) - 2 pF = 22 pF CL2 = CL1 = 22 pF 9.2.2.3 Frequency tuning The crystal oscillator frequency is very much dependent on the load capacitance that is connected. Therefore, measuring the oscillator frequency gives a good indication if the load capacitors that are used match the crystal requirements. This measurement also automatically includes the parasitic PCB and pin capacitances of the application. It is strongly recommended not to measure the oscillator frequency directly at the crystal pins. The capacitance at the crystal pins is in the range of 10 pF, and the impedance on this signal line is several megaohms. A typical passive probe has a capacitance in the range of 10 pF and an input impedance of approximately 10 M. Both values are in the range of the oscillator characteristics and heavily influence the behavior of the crystal oscillators. Instead, it is recommended to measure frequency at CLK_32K_OUT pin. Assuming the crystal itself has no tolerance, too low a capacitive load results in a higher oscillator frequency than expected and, vice versa, the frequency is lower than the nominal value, if the load is too high. Therefore, if the oscillation frequency is too high, the value of load capacitors must be increased. When too low frequency is measured, it is necessary to decrease the value of the load capacitors. Comparing the finally optimized capacitors with the crystal data sheet value for load capacitance gives the parasitic capacitance added by the PCB layout and pins. 9.3 Layout guide Layout guide is shown in Figure 25. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 64 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 10 F (0603) 1 F (0402) LDO4 1 F (0402) 43 44 48 49 45 LX2 INB26 50 51 52 53 54 56 LX6 1 42 2 41 LDO1 3 40 VINT 4 39 5 38 LDO2 1 F (0402) 55 LDO3 VSYS INL1 0.47 H (2520) 46 1 F (0402) 2.2 F (0402) LDO5 4.7 F (0402) 4.7 F (0402) (2016) 10 F (0603) BUCK50.47 H 1 F (0402) BUCK2 22 F (0603) 47 BUCK6 1 F (0402) 6 I2C BUCK2 0.47 H (2520) 37 36 10 F (0603) LX3 28 27 26 25 24 23 29 22 14 1 21 2 30 20 31 13 19 12 18 32 17 33 11 15 10 INB4/5 10 F (0603) INB13 PGND 22 F (0603) 32.768 kHz Xtal Osc 22 pF (0402) 34 LX5 LX1 35 9 16 22 pF (0402) 8 22 F (0603) EP 7 0.47 H (2520) BUCK1 LX4 SWIN SWOUT 10 F (0603) 4.7 F (0402) 0.47 H (2016) 0.47 H (2520) PGND BUCK5 10 F (0603) 22 F (0603) BUCK4 aaa-035727 Figure 25.PCA9450 layout PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 65 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 10 Limiting values Table 70.Limiting values (Absolute maximum ratings) Explanation Voltage range (with respect to EP) Output Current Pin Conditions Min Max Unit VSYS, INB13, INB26, INB45, INL1, SWIN -0.5 +6.0 V SWOUT -0.5 SWIN + 0.5 V LX1, LX3 -0.5 INB13 + 0.5 V LX2, LX6 -0.5 INB26 + 0.5 V LX4, LX5 -0.5 INB45 + 0.5 V R_SNSP1, R_SNSP2, R_SNSP3_ CFG -0.5 VSYS + 0.5 V BUCK_AGND, AGND -0.5 +0.5 V BUCK4FB, BUCK5FB, BUCK6FB -0.5 VSYS + 0.5 V LDO1, LDO2, LDO3, LDO4, LDO5 -0.5 VINL1 + 0.5 V XTAL_IN, XTAL_OUT -0.5 VSYS + 0.5 V RTC_RESET_B, PMIC_RST_B, CLK_32K_OUT -0.5 LDO1 + 0.5 V PMIC_ON_REQ, POR_B PMIC_ STBY_REQ, WDOG_B, IRQ_B, SCL, SDA, SD_VSEL, SW_EN -0.5 VSYS + 0.5 V SCLH, SDAH -0.5 SWIN + 0.5 V SCLL, SDAL -0.5 VINT + 0.5 V VINT -0.5 +2.0 V LX1, LX2, LX3, LX4 RMS current 5.0 A LX5, LX6 RMS current 4.0 A SWIN, SWOUT RMS current 0.5 A -40 +150 C HBM (JESD22-001) -2 +2 kV CDM (JESD22-C101E) -500 +500 V Junction temperature VESD PCA9450 Product data sheet All pins All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 66 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 11 Recommended operating conditions Table 71.Recommended Operating Conditions Explanation Pin Conditions Min Max Unit 2.7 5.5 V 2.7 5.5 V 2.7 5.5 V Junction temperature -40 +125 C Ambient temperature -40 +105 C VSYS, INL1 Voltage range (with INB13, INB26, INB45 respect to EP) SWIN PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 67 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 12 Thermal characteristics Table 72.Thermal characteristics Symbol Rth(j-a) [1] [2] Parameter Conditions thermal resistance from junction to ambient [1] [2] Typ Unit 32.1 C/W Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific environment Thermal test board meets JEDEC specification for this package (JESD51-9) PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 68 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13 Electrical characteristics 13.1 Top level parameter Table 73.Top level parameter Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min Typ Max Unit LDO1 and LDO2 are ON and no load, other regulators are OFF, CLK_32K_OUT enabled, PMIC_ON_REQ = L, Tamb= 25 C 23 50 A LDO1 and LDO2 are ON and no load, other regulators are OFF, CLK_32K_OUT enabled, PMIC_ON_REQ = L, Tamb= -40 C ~105 C 23 120 A VSYS Standby current LDO1, LDO2, LDO3, LDO4, LDO5, BUCK1, BUCK3, BUCK4, BUCK5, BUCK6 are ON and no load. PMIC_ ON_REQ = H, PMIC_STBY_REQ = H 220 350 A VSYS UVLO VSYS Rising 3.0 3.15 V Quiescent Current IQ_SNVS IQ_STADNDBY VSYS SNVS Current VSYS VSYS_UVLO 2.85 VSYS_UVLO_H VSYS UVLO Hysteresis VSYS Falling 200 VSYS_POR VSYS POR VSYS Rising VSYS_POR_H VSYS POR Hysteresis VSYS Falling Internal Power supply LDO VSYS = 3.8 V 1.7 1.8 1.9 V VLOW_VSYS Low VSYS Low VSYS threshold above VSYS_UVLO, LOW_VSYS [7:6] = 01b 150 200 250 mV VLOW_VSYS_ Low VSYS Hysteresis 2.2 2.4 mV 2.6 200 V mV VINT VINT Low VSYS HYS 110 mV 150 C Thermal Shutdown TJSHDN Thermal Shutdown Tj Rising, 15 C hysteresis TJ105 Thermal interrupt1 Tj Rising, 15 C hysteresis 95 105 125 C TJ125 Thermal interrupt2 Tj Rising, 15 C hysteresis 115 125 145 C 0.4 V Logic and Control signals VIL Input Low level PCA9450 Product data sheet PMIC_ON_REQ, PMIC_STBY_ REQ, WDOG_B, SD_VSEL, SW_ EN, PMIC_RST_B All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 69 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 73.Top level parameter...continued Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VIH Input High level PMIC_ON_REQ, PMIC_STBY_ REQ, WDOG_B, SD_VSEL, SW_ EN, PMIC_RST_B 1.4 ILEAK Logic Input leakage current PMIC_ON_REQ, PMIC_STBY_ REQ, WDOG_B, SD_VSEL: VLogic = 5.5 V, VSYS = 5.5 V -0.5 RPD Internal Pull-down resistor SW_EN VOL Output Low level RTC_RESET_B, IRQB, POR_B, IOL = 6 mA RPU Internal Pull-up resistor RTC_RESET_B, PMIC_RST_B to LDO1 Typ Max Unit V +0.5 1.2 A M 0.4 100 V K Logic signal (PCA9450B/ PCA9450C) VIL Input Low level R_SNSP3_CFG 0.4 VIH Input High level R_SNSP3_CFG 1.4 ILEAK Logic Input leakage current R_SNSP3_CFG VLogic = 5.5 V, VSYS = 5.5 V -1 V V +1 A Timing spec tDEB_POKB Debounce time of regulator POKB 320 400 480 s tDEB_POKB_SW Debounce time of Load SW POKB 240 300 360 s tDEB_WDOGB Debounce time of WDOG_B 90 120 150 s 40 50 60 ms tDEB_PMIC_ RST_B Debounce time of PMIC_RST_B T_PMIC_RST_DEB[2:0] = 001b tSNVS_PU Time to 90 % of LDO1 from VSYS UVLO detected 16 20 24 ms tRTC_RST Time to RTC_RESET_B release from LDO2 POK 16 20 24 ms t32K_EN Time to 32K buffer enable from LDO2 POK 8 10 12 ms tRTC_TRAN Time to transition to Xtal osc after RTC_RESET_ B release 0.8 1 1.2 sec tON_DEB PMIC_ON_REQ high debounce time Programmable, Ton_Deb[1:0] = 01b 16 20 24 ms tSTEP Time step to turn on each regulator Programmable, Tstep[1:0] = 01b 2 2.4 ms tOFF_STEP Time step to turn off each regulator Programmable, Toff_step[1:0] = 10b 6 8 10 ms PCA9450 Product data sheet 1.6 All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 70 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Table 73.Top level parameter...continued Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min Typ Max Unit tOFF_DEB PMIC_ON_REQ low debounce time Programmable, Toff_Deb = 0b 90 120 150 s tPORB Time from LDO5 POK to POR_B release during Power on seq 16 20 24 ms tFLT_SD_PU Fault time to POK after regulator enable during power up sequence 8 10 12 ms POK mask time when tFLT_POK_MSK regulator is enabled at RUN/Standby mode 1.6 2 2.4 ms tFLT_THSD Time to enter FAULT_ SD when thermal Fault occurs 170 210 250 s tFLT_SD_STAY Time to stay at FAULT_ SD to move other mode 80 100 120 ms tFLT_SD_WAIT Wait time to enter FAULT_SD after fault interrupt At Standby and Run mode, programmable, tFLT_SD_WAIT = 0b1 80 100 120 ms tRESTART Wait time to start power up after power down at cold reset Programmable, Trestart = 0b 200 250 300 ms tWRESET POR_B low time at Warm reset 16 20 24 ms PCA9450 Product data sheet At power up sequence All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 71 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.2 I2C level translator Table 74.I2C level translator Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VDDH Operating voltage Internally tied to SWIN 2.7 IVDDH Shutdown current SWIN = 3.3 V, I2C_LT_EN bit = 0b IVDDH Active current IVDDH Max Unit 5.5 V 1 5 A SWIN = 3.3 V, I2C_LT_EN bit = 1b, SCLL, SDAL = 1.8 V 60 90 A Active current SWIN = 3.3 V, I2C_LT_EN bit = 1b, SCLL, SDAL = 0 V 715 850 A VIH High level input voltage SWIN = 3.3 V, I2C_LT_EN bit = 1b VIL Low level input voltage SWIN = 3.3 V, I2C_LT_EN bit = 1b VOH High level output voltage SWIN = 3.3 V, I2C_LT_EN bit = 1b, IOL = 20 A VOL Low level output voltage SWIN = 3.3 V, I2C_LT_EN bit = 1b, IOL = 1 mA [1] Input Output capacitance SWIN = 3.3 V [1] High to Low propagation SWIN = 3.3 V, SCL/SDA to SCLH/ delay SDAH 4.0 4.7 ns [1] Low to High propagation SWIN = 3.3 V, SCL/SDA to SCLH/ delay SDAH 5.0 6.8 ns [1] High to Low propagation SWIN = 3.3 V, SCLH/SDAH to SCL/ delay SDA 4.0 4.5 ns [1] Low to High propagation SWIN = 3.3 V, SCLH/SDAH to SCL/ delay SDA 4.0 4.5 ns ten Enable time 100 [1] fdata Data rate CI/O tPHL tPLH tPHL tPLH [1] [1] Typ VINT - 0.2 V 0.15 0.75 * SWIN SWIN = 3.3 V, from I2C enable V V 0.4 5 V pF s 20 Mbps Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 72 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.3 BUCK1 (PCA9450AA/PCA9450B) Table 75.BUCK1 (PCA9450AA/PCA9450B) Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK1 = 0.85 V, COUT = 22 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VINB13 Input voltage range INB13 pin 2.85 IShutdown Shutdown current Regulator disabled, VINB13 = 5.0 V 0.1 A IQ Quiescent current Regulator enabled, No load, No switching 20 A IOUT_MAX Max Output Current VBUCK1 Programmable Output voltage range DC Output Voltage Accuracy VBUCK1_OUT Typ Max Unit 5.5 V 3000 I2C programmable, 12.5 mV step mA 0.6 VINB13 = 3.8 V, VBUCK1_OUT = 0.85 V, -0.6 IOUT = 0 A, FPWM mode, 25 C VINB13 = 3.8 V, VBUCK1_OUT = 0.85 V, -2 IOUT = 0 A, FPWM mode 2.1875 V +0.6 % +2 % [1] DC Line regulation VINB13 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V [1] DC Load regulation 0 mA < IOUT < IOUT_MAX, VBUCK1_OUT = 0.85 V 3 mV/A [1] Transient Load Response IOUT changes 0 to IOUT_MAX (1 A/s slope), VBUCK1_OUT = 0.85 V 50 mV VOUT Output voltage Ripple FPWM mode 10 mV fSW Switching Frequency in CCM 2 MHz VOUT(VINB) VOUT(IOUT) VOUT(IOUT) [1] High Side P-FET RDSON VINB13 = 3.8 V, including bonding wire 87 Low Side N-FET RDSON VINB13 = 3.8 V, including bonding wire 45 High side current limit VINB13 = 3.8 V 4.0 4.5 5.0 A 2.5 3.0 3.7 A 250 500 s RDSON ILIM m m Low side current limit VINB13 = 3.8 V [1] tSTART Startup time EN rising to 90 % of output voltage [1] VRAMP Output voltage slew rate Programmable, RAMP[1:0] = 01b 12.5 mV/s [1] Vsoft_strup Soft-start slew rate 12.5 mV/s RDIS Output Active Discharge Resistance 100 150 POK Output Power good 85 95 % Inductor value 0.47 L [1] [1] COUT [1] Output capacitance Minimum nominal capacitance 22 H F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 73 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.4 Dual Phase BUCK1 (PCA9450C) Table 76.Dual Phase BUCK1 (PCA9450C) Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK1 = 0.85 V, COUT = 44 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VINB13 Input voltage range INB13 pin 2.85 IShutdown Shutdown current Regulator disabled, VINB13 = 5.0 V 0.2 A IQ Quiescent current Regulator enabled, No load, No switching 20 A IOUT_MAX Max Output Current VBUCK1 Programmable Output voltage range DC Output Voltage Accuracy VBUCK1_OUT Typ Max Unit 5.5 V 6000 mA I2C programmable, 12.5 mV step 0.6 2.1875 V VINB13 = 3.8 V, VBUCK1_OUT = 0.85 V, IOUT = 0 A, FPWM mode, 25 C -0.6 +0.6 % -2 +2 % VINB13 = 3.8 V, VBUCK1_OUT = 0.85 V, IOUT = 0 A, FPWM mode [1] DC Line regulation VINB13 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V [1] DC Load regulation 0 mA < IOUT < IOUT_MAX, VBUCK1_OUT = 0.85 V 3 mV/A [1] Transient Load Response IOUT changes 0 to IOUT_MAX (1 A/s slope), VBUCK3_OUT = 0.85 V 50 mV VOUT Output voltage Ripple FPWM mode 10 mV fSW Switching Frequency in CCM 2 MHz High Side P-FET RDSON VINB13 = 3.8 V, including bonding wire 87 m Low Side N-FET RDSON VINB13 = 3.8 V, including bonding wire 45 m High side current limit VINB13 = 3.8 V, each phase 4.0 4.5 5.0 A 2.5 3.0 3.7 A 250 500 s VOUT(VINB) VOUT(IOUT) VOUT(IOUT) [1] RDSON ILIM Low side current limit VINB13 = 3.8 V, each phase [1] tSTART Startup time EN rising to 90 % of output voltage [1] VRAMP Output voltage slew rate Programmable, RAMP[1:0] = 01b 12.5 mV/s [1] Vsoft_strup Soft-start slew rate 12.5 mV/s POK Output Power good RDIS L [1] [1] COUT [1] 75 85 95 % Output Active Discharge One phase buck Resistance 100 150 Inductor value Each phase 0.47 Output capacitance Minimum nominal capacitance 44 H F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 74 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.5 BUCK2 Table 77.BUCK2 Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK2 = 0.85 V, COUT = 22 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VINB26 Input voltage range INB26 pin 2.85 IShutdown Shutdown current Regulator disabled, VINB26 = 5.0 V 0.1 A IQ Quiescent current Regulator enabled, No load, No switching 20 A IOUT_MAX Max Output Current VBUCK2 Programmable Output voltage range Max Unit 5.5 V 3000 DC Output Voltage Accuracy VBUCK2_OUT Typ mA I2C programmable, 12.5 mV step 0.6 2.1875 V VINB26 = 3.8 V, VBUCK2_OUT = 0.85 V, IOUT = 0A, FPWM mode, 25 C -0.6 +0.6 % -2 +2 % VINB26 = 3.8 V, VBUCK2_OUT = 0.85 V, IOUT = 0A, FPWM mode [1] DC Line regulation VINB26 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V [1] DC Load regulation 0 mA < IOUT < IOUT_MAX, VBUCK2_OUT = 0.85 V 3 mV/A [1] Transient Load Response IOUT changes 0 to IOUT_MAX (1 A/s slope), VBUCK2_OUT = 0.85 V 50 mV VOUT Output voltage Ripple FPWM mode 10 mV fSW Switching Frequency in CCM 2 MHz VOUT(VINB) VOUT(IOUT) VOUT(IOUT) [1] High Side P-FET RDSON VINB26 = 3.8 V, including bonding wire 87 Low Side N-FET RDSON VINB26 = 3.8 V, including bonding wire 45 High side current limit VINB26 = 3.8 V 4.0 4.5 5.0 A 2.5 3.0 3.7 A 500 s RDSON ILIM m m Low side current limit VINB26 = 3.8 V [1] tSTART Startup time EN rising to 90 % of output voltage 250 [1] VRAMP Output voltage slew rate Programmable, RAMP[1:0] = 01b 12.5 mV/s [1] Vsoft_strup Soft-start slew rate 12.5 mV/s POK Output Power good RDIS L [1] [1] COUT [1] 85 95 % Output Active Discharge Resistance 100 150 Inductor value 0.47 Output capacitance 75 Minimum nominal capacitance 22 H F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 75 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.6 BUCK3 (PCA9450AA) Table 78.BUCK3 (PCA9450AA) Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK3 = 0.85 V, COUT = 22 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VINB13 Input voltage range INB13 pin 2.85 IShutdown Shutdown current Regulator disabled, VINB13 = 5.0 V 0.1 A IQ Quiescent current Regulator enabled, No load, No switching 20 A IOUT_MAX Max Output Current VBUCK3 Programmable Output voltage range DC Output Voltage Accuracy VBUCK3_OUT Typ Max Unit 5.5 V 3000 I2C programmable, 12.5 mV step mA 0.6 VINB13 = 3.8 V, VBUCK3_OUT = 0.85 V, -0.6 IOUT = 0 A, FPWM mode, 25 C VINB13 = 3.8 V, VBUCK3_OUT = 0.85 V, -2 IOUT = 0 A, FPWM mode 2.1875 V +0.6 % +2 % [1] DC Line regulation VINB13 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V [1] DC Load regulation 0 mA < IOUT < IOUT_MAX, VBUCK3_OUT = 0.85 V 3 mV/A [1] Transient Load Response IOUT changes 0 to IOUT_MAX (1 A/s slope), VBUCK3_OUT = 0.85 V 50 mV VOUT Output voltage Ripple FPWM mode 10 mV fSW Switching Frequency in CCM 2 MHz VOUT(VINB) VOUT(IOUT) VOUT(IOUT) [1] High Side P-FET RDSON VINB13 = 3.8 V, including bonding wire 87 Low Side N-FET RDSON VINB13 = 3.8 V, including bonding wire 45 High side current limit VINB13 = 3.8 V 4.0 4.5 5.0 A 2.5 3.0 3.7 A 250 500 s RDSON ILIM m m Low side current limit VINB13 = 3.8 V [1] tSTART Startup time EN rising to 90 % of output voltage [1] VRAMP Output voltage slew rate Programmable, RAMP[1:0] = 01b 12.5 mV/s [1] Vsoft_strup Soft-start slew rate 12.5 mV/s POK Output Power good RDIS L [1] [1] COUT [1] 85 95 % Output Active Discharge Resistance 100 150 Inductor value 0.47 Output capacitance 75 Minimum nominal capacitance 22 H F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 76 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.7 BUCK4 Table 79.BUCK4 Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK4 = 3.3 V, COUT = 22 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VINB45 Input voltage range INB45 pin 2.85 IShutdown Shutdown current Regulator disabled, VINB45 = 5.0 V 0.1 A IQ Quiescent current Regulator enabled, No load, No switching 20 A IOUT_MAX Max Output Current VBUCK4 Programmable Output voltage range DC Output Voltage Accuracy VBUCK4_OUT Typ Max Unit 5.5 V 3000 I2C programmable, 25 mV step mA 0.6 VINB45 = 3.8 V, VBUCK4_OUT = 3.3 V, -0.5 IOUT = 0 A, FPWM mode, 25 C VINB45 = 3.8 V, VBUCK4_OUT = 3.3 V, -2 IOUT = 0 A, FPWM mode 3.4 V +0.5 % +2 % [1] DC Line regulation VINB45 = 4 V to 5 V, IOUT= IOUT_MAX 2 mV/V [1] DC Load regulation 0 mA < IOUT < IOUT_MAX, VBUCK4_OUT = 3.3 V 6 mV/A [1] Transient Load Response IOUT changes 0 to IOUT_MAX (1 A/s slope), VBUCK4_OUT = 3.3 V 160 mV VOUT Output voltage Ripple FPWM mode 10 mV fSW Switching Frequency in CCM 2 MHz VOUT(VINB) VOUT(IOUT) VOUT(IOUT) [1] High Side P-FET RDSON VINB45 = 3.8 V, including bonding wire 87 Low Side N-FET RDSON VINB45 = 3.8 V, including bonding wire 45 High side current limit VINB45 = 3.8 V 4.0 4.5 5.0 A 2.5 3.0 3.7 A 250 500 s RDSON ILIM Low side current limit VINB45 = 3.8 V [1] tSTART Startup time EN rising to 90 % of output voltage [1] Vsoft_strup Soft-start slew rate POK Output Power good RDIS L [1] [1] COUT [1] m m 12.5 85 95 % Output Active Discharge Resistance 100 150 Inductor value 0.47 Output capacitance 75 mV/s Minimum nominal capacitance 22 H F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 77 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.8 BUCK5 Table 80.BUCK5 Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK5 = 1.8 V, COUT = 22 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VINB45 Input voltage range INB45 pin 2.85 IShutdown Shutdown current Regulator disabled, VINB45 = 5.0 V 0.1 A IQ Quiescent current Regulator enabled, No load, No switching 20 A IOUT_MAX Max Output Current VBUCK5 Programmable Output voltage range Max Unit 5.5 V 2000 DC Output Voltage Accuracy VBUCK5_OUT Typ mA I2C programmable, 25 mV step 0.6 3.4 V VINB45 = 3.8 V, VBUCK5_OUT = 1.8 V, IOUT = 0 A, FPWM mode, 25 C -0.5 +0.5 % -2 +2 % VINB45 = 3.8 V, VBUCK5_OUT = 1.8 V, IOUT = 0 A, FPWM mode [1] DC Line regulation VINB45 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V [1] DC Load regulation 0 mA < IOUT < IOUT_MAX, VBUCK5_OUT = 1.8 V 7 mV/A [1] Transient Load Response IOUT changes 0 to IOUT_MAX (1 A/s slope), VBUCK5_OUT = 1.8 V 50 mV VOUT Output voltage Ripple FPWM mode 22 mV fSW Switching Frequency in CCM 2 MHz VOUT(VINB) VOUT(IOUT) VOUT(IOUT) [1] RDSON ILIM High Side P-FET RDSON VINB45 = 3.8 V, including bonding wire 130 Low Side N-FET RDSON VINB45 = 3.8 V, including bonding wire 70 High side current limit VINB45 = 3.8 V 3.0 3.5 4.0 A 1.5 2 2.7 A 250 500 s Low side current limit VINB45 = 3.8 V [1] tSTART Startup time EN rising to 90 % of output voltage [1] Vsoft_strup Soft-start slew rate POK Output Power good RDIS L [1] [1] COUT [1] m m 12.5 85 95 % Output Active Discharge Resistance 100 150 Inductor value 0.47 Output capacitance 75 mV/s Minimum nominal capacitance 22 H F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 78 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.9 BUCK6 Table 81.BUCK6 Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VBUCK6 = 1.1 V, COUT = 22 F, Tamb= -40 C to +105 C Symbol Parameter Conditions Min VINB26 Input voltage range INB26 pin 2.85 IShutdown Shutdown current Regulator disabled, VINB26 = 5.0 V 0.1 A IQ Quiescent current Regulator enabled, No load, No switching 20 A IOUT_MAX Max Output Current VBUCK6 Programmable Output voltage range DC Output Voltage Accuracy VBUCK6_OUT Typ Max Unit 5.5 V 2000 mA I2C programmable, 25 mV step 0.6 3.4 V VINB26 = 3.8 V, VBUCK6_OUT = 1.1 V, IOUT = 0 A, FPWM mode, 25 C -0.8 +0.8 % -2 +2 % VINB26 = 3.8 V, VBUCK6_OUT = 1.1 V, IOUT = 0 A, FPWM mode [1] DC Line regulation VINB26 = 3 V to 5 V, IOUT= IOUT_MAX 2 mV/V [1] DC Load regulation 0 mA < IOUT < IOUT_MAX, VBUCK6_OUT = 1.1 V 6 mV/A [1] Transient Load Response IOUT changes 0 to IOUT_MAX (1 A/s slope), VBUCK6_OUT = 1.1 V 50 mV VOUT Output voltage Ripple FPWM mode 18 mV fSW Switching Frequency in CCM 2 MHz VOUT(VINB) VOUT(IOUT) VOUT(IOUT) [1] High Side P-FET RDSON VINB26 = 3.8 V, including bonding wire 130 Low Side N-FET RDSON VINB26 = 3.8 V, including bonding wire 70 High side current limit VINB26 = 3.8 V 3.0 3.5 4.0 A 1.5 2 2.7 A 250 500 s RDSON ILIM Low side current limit VINB26 = 3.8 V [1] tSTART Startup time EN rising to 90 % of output voltage [1] Vsoft_strup Soft-start slew rate POK Output Power good RDIS L [1] [1] COUT [1] m m 12.5 85 95 % Output Active Discharge Resistance 100 150 Inductor value 0.47 Output capacitance 75 mV/s Minimum nominal capacitance 22 H F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 79 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.10 LDO1 Table 82.LDO1 Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VLDO1 = 1.8 V, CINL1 = 4.7 F, COUT = 1 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VIN Input voltage range INL1 pin 2.85 IQ Quiescent current Regulator enabled, No load IOUT_MAX Maximum Output DC Current VIN > 2.85 V, VLDO1 = 1.8 V 10 ILIMIT Short Current Limit Output shorted to GND 30 VDO Dropout Voltage IOUT = IOUT_MAX, VIN = 3.2 V, L1_OUT[2:0]= 0x7, 3.3 V Nominal output voltage I C Programmable, 100 mV step VLDO1 2 Typ Max Unit 5.5 V 2 mA 35 1.6 Default voltage A 60 mA 60 mV 3.3 V 1.8 DC accuracy VLDO1 = 1.8 V, ILoad = 5 mA VNOISE Output noise f = 10 Hz to 10 kHz, IOUT = 10 % of IMAX, VLDO1 = 1.8 V 400 VOUT(VINL) DC Line regulation VLDO1 +0.3 V < VIN < 5.5 V, IOUT(LDO1) = 10 % of IOUT_MAX 0.2 0.5 %/V VOUT(IOUT) DC Load regulation VIN = VLDO1 +0.3 V to 5.5 V, 0 mA < IOUT < IOUT_MAX 0.5 1 % [1] Transient Line Response VLDO1 +0.3 V < VIN < 5.5 V, IOUT(LDO1) = 10 % of IOUT_MAX, tr = 10 s 0.5 [1] Transient Load Response VIN = VLDO1 +0.3 V to 5.5 V, 1 mA < IOUT < IOUT_MAX , tr = 10 s, VLDO1 = 1.8 V [1] VOUT(VINL) VOUT(IOUT) -3 V -3 Power Supply Rejection f = 10 Hz to 10 kHz, IOUT = 10 % ratio of IOUT_MAX [1] PSRR 3 % V %/V 3 % 45 dB 15 mV/s Soft-start slew rate IOUT = 0 mA, 10 % to 90 % of VLDO1 Overshoot at startup IOUT = 0 mA tEN Enable time EN rising to 90 % of output voltage 150 POK Output Power good Percentage of VLDO1 configuration 75 85 92 % RDIS Active Discharge Resistance 100 150 [1] Vsoft_strup [1] Vov_srtup [1] [1] COUT [1] Output capacitance Minimum nominal capacitance 10 1 mV s F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 80 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.11 LDO2 Table 83.LDO2 Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VLDO2 = 0.85 V, CINL1 = 4.7 F, COUT = 1 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VIN Input voltage range INL1 pin 2.85 IQ Quiescent current Regulator enabled, No load IOUT_MAX Maximum Output DC Current VIN > 2.8 V, VLDO2 = 0.8 V 10 ILIMIT Short Current Limit Output shorted to GND 30 VDO Dropout Voltage IOUT = IOUT_MAX, Nominal output voltage VLDO2 2 I C Programmable, 50 mV step Typ Max Unit 5.5 V 2 mA 35 0.8 Default voltage A 60 mA 60 mV 1.5 V 0.85 DC accuracy VLDO2 = 0.8 V, ILoad = 5 mA VNOISE Output noise f = 10 Hz to 10 kHz, IOUT = 10 % of IMAX, VLDO2 = 0.8 V 400 VOUT(VINL) DC Line regulation VLDO2 +0.3 V < VIN < 5.5 V, IOUT(LDO2) = 10 % of IOUT_MAX 0.2 0.5 %/V VOUT(IOUT) DC Load regulation VIN = VLDO2 +0.3 V to 5.5 V, 0 mA < IOUT < IOUT_MAX 0.5 1 % [1] [1] VOUT(VINL) -3 V VLDO2 +0.3 V < VIN < 5.5 V, Transient Line Response IOUT(LDO2) = 10 % of IOUT_MAX, tr = 10 s 3 % V 0.5 %/V Transient Load Response VIN = VOUT +0.3 V to 5.5 V, 1 mA < IOUT < IOUT_MAX , tr = 10 s, -3 VLDO2 = 0.8 V Power Supply Rejection ratio f = 10 Hz to 10 kHz, IOUT = 10 % of IOUT_MAX 60 dB Soft-start slew rate IOUT = 0 mA, 10 % to 90 % of VLDO2 15 mV/s Vov_srtup Overshoot at startup IOUT = 0 mA [1] tEN Enable time EN rising to 90 % of output voltage POK Output Power good Percentage of VLDO2 configuration RDIS Active Discharge Resistance [1] VOUT(IOUT) [1] PSRR [1] Vsoft_strup [1] [1] COUT [1] Output capacitance Minimum nominal capacitance 3 % 10 100 75 1 mV s 85 92 % 100 150 F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 81 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.12 LDO3 Table 84.LDO3 Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VLDO3 = 1.8 V, CINL1 = 4.7 F, COUT = 2.2 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VIN Input voltage range INL1 2.85 IShutdown Shutdown current Regulator disabled, VIN = 5.0 V 0.1 A IQ Quiescent current Regulator enabled, No load 15 A IOUT_MAX Maximum Output DC Current VIN > 2.8 V, VLDO3 = 1.8 V 300 ILIMIT Short Current Limit Output shorted to GND 310 VDO Dropout Voltage IOUT = IOUT_MAX, VIN = 3.2 V, L3_OUT[4:0] = 0x1F, 3.3 V Nominal output voltage I C Programmable, 100 mV step VLDO3 2 Typ Unit 5.5 V mA 70 0.8 Default voltage Max 480 mA 100 mV 3.3 V 1.8 DC accuracy VLDO3 = 1.8 V, ILoad = 5 mA VNOISE Output noise f = 10 Hz to 10 kHz, IOUT = 10 % of IMAX, VLDO3 = 1.8 V 150 VOUT(VINL) DC Line regulation VLDO3 +0.3 V < VIN < 5.5 V, IOUT(LDO3) = 10 % of IOUT_MAX 0.2 VOUT(IOUT) DC Load regulation VIN = VLDO3 +0.3 V to 5.5 V, 0 mA < IOUT < IOUT_MAX 0.6 % [1] Transient Line Response VLDO3 +0.3 V < VIN < 5.5 V, IOUT(LDO3) = 10 % of IOUT_MAX, tr = 10 s 0.5 %/V [1] Transient Load Response VIN = VLDO3 +0.3 V to 5.5 V, 1 mA < IOUT < IOUT_MAX , tr = 10 s, -3 VLDO3 = 1.8 V, Tamb= 25 C VOUT(VINL) VOUT(IOUT) Power Supply Rejection f = 10 Hz to 10 kHz, IOUT = 10 % of ratio IOUT_MAX [1] PSRR Soft-start slew rate IOUT = 0 mA, 10 % to 90 % of VLDO3 Vov_srtup Overshoot at startup IOUT = 0 mA [1] tEN Enable time EN rising to 90 % of output voltage POK Output Power good Percentage of VLDO3 configuration RDIS Active Discharge Resistance [1] Vsoft_strup [1] [1] COUT [1] -3 V Output capacitance Minimum nominal capacitance 3 % V 0.5 3 % 55 dB 15 mV/s 10 150 75 2.2 %/V mV s 85 92 % 100 150 F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 82 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.13 LDO4 Table 85.LDO4 Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VLDO4 = 0.9 V, CINL1 = 4.7 F, COUT = 1 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VIN Input voltage range INL1 2.85 IShutdown Shutdown current Regulator disabled, VIN = 5.0 V 0.1 A IQ Quiescent current Regulator enabled, No load 15 A IOUT_MAX Maximum Output DC Current VIN > 2.8, VLDO4 = 0.9 V 200 ILIMIT Short Current Limit Output shorted to GND 210 VDO Dropout Voltage IOUT = IOUT_MAX, VIN = 3.2 V, L4_OUT[4:0] = 0x1F, 3.3 V Nominal output voltage I C Programmable, 100 mV step VLDO4 2 Typ Unit 5.5 V mA 60 0.8 Default voltage Max 330 mA 100 mV 3.3 V 0.9 DC accuracy VLDO4 = 0.9 V, ILoad = 5 mA VNOISE Output noise f = 10 Hz to 10 kHz, IOUT = 10 % of IMAX, VLDO4 = 0.9 V 150 VOUT(VINL) DC Line regulation VLDO4 +0.3 V < VIN < 5.5 V, IOUT(LDO4) = 10 % of IOUT_MAX 0.2 VOUT(IOUT) DC Load regulation VIN = VLDO4 +0.3 V to 5.5 V, 0 mA < IOUT < IOUT_MAX 0.9 % 0.5 %/V [1] VOUT(VINL) -3 V VLDO4 +0.3 V < VIN < 5.5 V, Transient Line Response IOUT(LDO4) = 10 % of IOUT_MAX, tr = 10 s 3 % V 0.5 %/V Transient Load Response VIN = VLDO4 +0.3 V to 5.5 V, 1 mA < IOUT < IOUT_MAX , tr = 10 s, VLDO4 = 0.9 V, Tamb= 25 C Power Supply Rejection ratio f = 10 Hz to 10 kHz, IOUT = 10 % of IOUT_MAX 60 dB Vsoft_strup Soft-start slew rate IOUT = 0 mA, 10 % to 90 % of VLDO4 20 mV/s [1] Vov_srtup Overshoot at startup IOUT = 0 mA [1] tEN Enable time EN rising to 90 % of output voltage POK Output Power good Percentage of VLDO4 configuration RDIS Active Discharge Resistance [1] VOUT(IOUT) [1] PSRR [1] [1] COUT [1] Output capacitance Minimum nominal capacitance -4 4 % 10 100 75 1 mV s 85 92 % 100 150 F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 83 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.14 LDO5 Table 86.LDO5 Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VLDO5 = 3.3 V, CINL1 = 4.7 F, COUT = 1 F, Tamb= -40 C ~ +105 C Symbol Parameter VIN Input voltage range IShutdown Shutdown current Regulator disabled, VIN = 5.0 V 0.1 A IQ Quiescent current Regulator enabled, No load 15 A IOUT_MAX Maximum Output DC Current VIN > VLDO5 + VDO(MAX), VLDO5 = 3.3 V 150 ILIMIT Short Current Limit Output shorted to GND 160 VDO Dropout Voltage IOUT = IOUT_MAX, VIN = 3.2 V, L5_OUT_L[3:0] = 0xF, 3.3 V Nominal output voltage I C Programmable, 100 mV step VLDO5 Default voltage Conditions Min INL1 pin INL1 pin, when VLDO5 = 3.3 V 2 Typ Max Unit 2.85 5.5 V VLDO5 + VDO 5.5 V mA 50 1.8 280 mA 100 mV 3.3 V SD_VSEL = Low 3.3 V SD_VSEL = High 1.8 V DC accuracy VLDO5 = 1.8 V, ILoad = 5 mA VNOISE Output noise f = 10 Hz to 10 kHz, IOUT = 10 % of IMAX, VLDO5 = 3.3 V 300 VOUT(VINL) DC Line regulation VLDO5 +0.3 V < VIN < 5.5 V, IOUT(LDO5) = 10 % of IOUT_MAX 0.2 VOUT(IOUT) DC Load regulation VIN = VLDO5 +0.3 V to 5.5 V, 0 mA < IOUT < IOUT_MAX 0.3 % [1] Transient Line Response VLDO5 +0.3 V < VIN < 5.5 V, IOUT(LDO5) = 10 % of IOUT_MAX 0.5 %/V [1] Transient Load Response VIN = VLDO5 +0.3 V to 5.5 V, 1 mA < IOUT < IOUT_MAX , tr = 10 s, VLDO5 = 3.3 V, Tamb= 25 C VOUT(VINL) VOUT(IOUT) -3 3 -3 % V 0.5 3 %/V % Power Supply Rejection f = 10 Hz to 10 kHz, IOUT = 10 % of ratio IOUT_MAX 50 dB Vsoft_strup Soft-start slew rate IOUT = 0 mA, 10 % to 90 % of VLDO5 15 mV/s [1] Vov_srtup Overshoot at startup IOUT = 0 mA [1] tEN Enable time EN rising to 90 % of output voltage POK Output Power good Percentage of VLDO5 configuration RDIS Active Discharge Resistance [1] PSRR [1] [1] COUT [1] Output capacitance Minimum nominal capacitance 10 200 75 1 mV s 85 92 % 100 150 F Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 84 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.15 Load SW Table 87.Load SW Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8 V, VSWIN = 3.8 V, CSWIN = CSWOUT = 1 F, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min VSWIN Input voltage range SWIN 2.8 IQ Quiescent current Switch enabled, No load, VSWIN = 3.3 V ISHDN Shut down current SWEN = 0 V, VSWIN = 3.3 V [1] IOC OverCurrent Threshold 450 Typ Max Unit 5.5 V 5 8 A 1 2.5 A 800 mA 2 A ISC Short circuit current threshold RDSON Switch ON resistance VSWIN = 3.3 V, ILOAD = 200 mA, including bonding wire resistance 150 210 m [1] Enable time Time to SWOUT 10 % from EN pin high, VSWIN = 3.3 V 90 120 s tON [1] Output rise time CL = 10 F, VSWIN = 3.3 V, SWOUT 10 % to 90 % 200 500 s RDIS Active Discharge Resistance SWEN = 0 V 80 120 [1] tEN [1] Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 85 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.16 32 kHz Xtal driver Table 88.32 kHz Xtal driver Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min Typ Max Unit fOSC_32K Clock frequency Internal Oscillator 29 32.77 36 kHz Clock frequency External 32.768 kHz crystal oscillator [1] fCLK [1] tRTCSTB Oscillator stabilization time Output Duty cycle External 32.768 kHz crystal oscillator VOL Output Low level IOL = 1 mA VOH Output High level VLDO1 = 1.8 V, IOL = 1 mA Duty [1] [1] 30 1.6 32.768 kHz 1000 ms 50 70 % 0.4 V V Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 86 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 2 13.17 I C-bus interface and logic I/O 2 Table 89.I C-bus interface and logic I/O Unless otherwise specified, VSYS = 3.8 V, VINBx = 3.8 V, VINL1 = 3.8, Tamb= -40 C ~ +105 C Symbol Parameter Conditions Min Typ Max Unit - - 1 MHz SCL, SDA 2 fI2C I C Clock frequency VIH High-level Input voltage SCL, SDA; VSYS= 3.0 V to 5.5 V 1.2 - - V VIL Low-level Input voltage SCL, SDA; VSYS= 3.0 V to 5.5 V - - 0.4 V Vhys Hysteresis of Schmitt trigger inputs 0.01 - - V VOL Low-level output voltage SDA, Iload = 20 mA, VSYS = 3.0 V to 5.5 V 0 - 0.4 V Hold time (repeated) START condition Fast mode plus; After this period, the first clock pulse is generated 0.26 - - s tLOW LOW period of I2C clock Fast mode plus 0.5 - - s [1] tHIGH HIGH period of I2C clock Fast mode plus 0.26 - - s [1] Setup time (repeated) START condition Fast mode plus 0.26 - - s [1] Data Hold time Fast mode plus 0 - - s [1] Data Setup time Fast mode plus 50 - - ns Rise time of I2C_SCL and I2C_SDA signals Fast mode plus - - 120 ns Fall time of I2C_SCL and Fast mode plus I2C_SDA signals - - 120 ns Setup time for STOP condition Fast mode plus 0.26 - - s Bus free time between STOP and START condition Fast mode plus 0.5 - - s [1] Data valid time Fast mode plus - 0.45 s [1] Data valid acknowledge time Fast mode plus - 0.45 s - 50 ns [1] tHD,STA [1] tSU,STA tHD,DAT tSU,DAT tr [1] tf [1] [1] tSU,STO [1] tBUF tVD,DAT tVD,ACK [1] tSP [1] Pulse width of spikes that must be suppressed by input filter 0 Guaranteed by design PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 87 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 14 Package outline Figure 26.Package outline HVQFN56 (SOT949-6) PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 88 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Figure 27.Package outline HVQFN56 (SOT949-6) PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 89 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Figure 28.PCB Design Guidelines - Solder Mask Opening Pattern PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 90 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Figure 29.PCB Design Guidelines - I/O PADS AND SODERABLE AREA PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 91 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Figure 30.PCB Design Guidelines - Solder Paste Stencil PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 92 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 15 Revision history Table 90.Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9450 v2.1 20201207 Product data sheet - PCA9450 v2.0 Modifications: * Table 3: Updated description for pin 22 SWIN * Table 20: Device_ID Register "Reset Value" changed from "0x10" to "0x11" * Table 21: RSVD bit changed from "0000" to "0001" PCA9450 v2.0 20200924 Modifications: * * * * * * * * * PCA9450 v1.0 20191119 PCA9450 Product data sheet Product data sheet - PCA9450 v1.0 Replaced "PCA9450A" with "PCA9450AA" throughout Table 79: Added POK information Table 86: Updated conditions for VIN and IOUT_MAX Figure 1: Corrected LDO3 capacitor value; added footnote Figure 21, Figure 22: Added footnote Figure 23: Corrected LDO2, added footnote Figure 5: Corrected VINT Section 7.3.7: Corrected paragraph 1 Section 9.2.1.1: Corrected equations (1) and (2) Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 - (c) NXP B.V. 2020. All rights reserved. 93 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 16 Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 16.2 Definitions Draft -- A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without PCA9450 Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 94 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. PCA9450 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 95 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Tab. 18. Tab. 19. Tab. 20. Tab. 21. Tab. 22. Tab. 23. Tab. 24. Tab. 25. Tab. 26. Tab. 27. Tab. 28. Tab. 29. Tab. 30. Tab. 31. Tab. 32. Tab. 33. Tab. 34. Tab. 35. Tab. 36. Tab. 37. Tab. 38. Tab. 39. Tab. 40. Tab. 41. Tab. 42. Tab. 43. Tab. 44. Tab. 45. Tab. 46. Ordering information ..........................................4 Ordering options ................................................4 Pin description ...................................................6 PCA9450 selection guide ................................10 SNVS mode .................................................... 12 PWRUP mode .................................................14 Power modes summary .................................. 15 tFLT_THSD ......................................................17 tFLT_SD_WAIT ................................................19 0x08 - RESET_CTRL ..................................... 20 0x06 - SW_RST ............................................. 20 tRESTART ....................................................... 21 tRESET ............................................................22 PCA9450AA Regulator Control summary ........22 PCA9450B/PCA9450C Regulator Control summary ..........................................................23 PCA9450AA Buck Summary ...........................24 PCA9450C Buck Summary ............................. 24 LDO summary ................................................. 26 PCA9450 I2C Slave Address .......................... 30 Register map ...................................................31 0x00 Device_ID ...............................................34 0x01 INT1 ........................................................34 0x02 INT1_MSK .............................................. 35 0x03 STATUS1 ................................................35 0x04 STATUS2 ................................................36 0x05 PWRON_STAT ....................................... 37 0x06 SW_RST ................................................ 37 0x07 PWR_CTRL ............................................37 0x08 RESET_CTRL ........................................ 38 0x09 CONFIG1 ............................................... 39 0x0A CONFIG2 ............................................... 39 0x0C BUCK123_DVS ......................................40 0x0D BUCK1OUT_LIMIT ................................ 40 0x0E BUCK2OUT_LIMIT ................................ 40 0x0F BUCK3OUT_LIMIT .................................41 0x10 BUCK1CTRL .......................................... 41 0x11 BUCK1OUT_DVS0 ................................. 42 0x12 BUCK1OUT_DVS1 .................................42 0x13 BUCK2CTRL .......................................... 42 0x14 BUCK2OUT_DVS0 .................................43 0x15 BUCK2OUT_DVS1 .................................43 0x16 BUCK3CTRL .......................................... 43 0x17 BUCK3OUT_DVS0 .................................44 0x18 BUCK3OUT_DVS1 .................................44 BUCK1, BUCK2, BUCK3 Output voltage table .................................................................45 0x19 BUCK4CTRL .......................................... 46 PCA9450 Product data sheet Tab. 47. Tab. 48. Tab. 49. Tab. 50. Tab. 51. Tab. 52. Tab. 53. Tab. 54. Tab. 55. Tab. 56. Tab. 57. Tab. 58. Tab. 59. Tab. 60. Tab. 61. Tab. 62. Tab. 63. Tab. 64. Tab. 65. Tab. 66. Tab. 67. Tab. 68. Tab. 69. Tab. 70. Tab. 71. Tab. 72. Tab. 73. Tab. 74. Tab. 75. Tab. 76. Tab. 77. Tab. 78. Tab. 79. Tab. 80. Tab. 81. Tab. 82. Tab. 83. Tab. 84. Tab. 85. Tab. 86. Tab. 87. Tab. 88. Tab. 89. Tab. 90. 0x1A BUCK4OUT ............................................46 0x1B BUCK5CTRL ..........................................46 0x1C BUCK5OUT ........................................... 47 0x1D BUCK6CTRL ..........................................47 0x1E BUCK6OUT ............................................47 BUCK4, BUCK5, BUCK6 Output voltage table .................................................................48 0x20 LDO_AD_CTRL ......................................49 0x21 LDO1CTRL .............................................49 0x22 LDO2CTRL .............................................50 0x23 LDO3CTRL .............................................51 LDO3 output voltage ....................................... 51 0x24 LDO4CTRL .............................................51 LDO4 output voltage ....................................... 51 0x25 LDO5CTRL_L .........................................52 LDO5 output voltage when SD_VSEL = Low .................................................................. 52 0x26 LDO5CTRL_H ........................................ 52 LDO5 output voltage when SD_VSEL = High ................................................................. 52 0x2A LOADSW_CTRL .................................... 53 0x2B VRFLT1_STS ......................................... 53 0x2C VRFLT2_STS .........................................54 0x2D VRFLT1_MASK ......................................55 0x2E VRFLT2_MASK ......................................55 Tested inductor list .......................................... 61 Limiting values ................................................ 66 Recommended Operating Conditions ............. 67 Thermal characteristics ................................... 68 Top level parameter ........................................ 69 I2C level translator .......................................... 72 BUCK1 (PCA9450AA/PCA9450B) .................. 73 Dual Phase BUCK1 (PCA9450C) ................... 74 BUCK2 .............................................................75 BUCK3 (PCA9450AA) .....................................76 BUCK4 .............................................................77 BUCK5 .............................................................78 BUCK6 .............................................................79 LDO1 ............................................................... 80 LDO2 ............................................................... 81 LDO3 ............................................................... 82 LDO4 ............................................................... 83 LDO5 ............................................................... 84 Load SW ......................................................... 85 32 kHz Xtal driver ........................................... 86 I2C-bus interface and logic I/O ........................87 Revision history ...............................................93 All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 96 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. Fig. 13. Fig. 14. Fig. 15. Fig. 16. Block diagram ................................................... 5 PCA9450 pin map - Top View .......................... 6 PCA9450 functional block diagram ................. 10 Power States Diagram .................................... 11 SNVS mode ON/OFF sequence ..................... 12 PCA9450AA power ON/OFF sequence .......... 13 PCA9450B/C power ON/OFF sequence ......... 14 PCA9450AA mode transition ...........................15 PCA9450 FAULT_SD from Thermal shutdown ......................................................... 17 PCA9450 Fault event ...................................... 18 PCA9450 FAULT_SD from VR Fault except LDO1/LDO2 in RUN/STANDBY ...................... 19 PCA9450AA Cold reset ...................................21 Warm reset ......................................................22 DVS functional diagram .................................. 25 DVS timing ...................................................... 25 BUCK1/3 configuration ....................................26 PCA9450 Product data sheet Fig. 17. Fig. 18. Fig. 19. Fig. 20. Fig. 21. Fig. 22. Fig. 23. Fig. 24. Fig. 25. Fig. 26. Fig. 27. Fig. 28. Fig. 29. Fig. 30. 32 kHz Crystal oscillator driver block diagram ............................................................27 Load switch internal block diagram ................. 27 Architecture of I2C Level translator (One channel) ...........................................................28 Interrupt diagram ............................................. 29 PCA9450AA application schematic ................. 58 PCA9450B application schematic ................... 59 PCA9450C application schematic ................... 60 Crystal oscillator .............................................. 63 PCA9450 layout .............................................. 65 Package outline HVQFN56 (SOT949-6) ......... 88 Package outline HVQFN56 (SOT949-6) ......... 89 PCB Design Guidelines - Solder Mask Opening Pattern .............................................. 90 PCB Design Guidelines - I/O PADS AND SODERABLE AREA ........................................91 PCB Design Guidelines - Solder Paste Stencil ..............................................................92 All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 97 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.4 7.5 7.6 7.6.1 7.6.1.1 7.6.1.2 7.6.1.3 7.6.2 7.7 7.8 7.9 7.10 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 8.2.14 8.2.15 8.2.16 8.2.17 8.2.18 8.2.19 8.2.20 8.2.21 General description ............................................ 1 Features and benefits .........................................2 Applications .........................................................3 Ordering information .......................................... 4 Block diagram ..................................................... 5 Pinning information ............................................ 6 Pinning ............................................................... 6 Pin description ................................................... 6 Functional description ........................................9 Features .............................................................9 Functional diagram .......................................... 10 Power modes ...................................................11 Off mode ..........................................................11 READY mode .................................................. 11 SNVS mode .....................................................11 PWRUP mode ................................................. 12 PWRDN mode ................................................. 14 RUN mode .......................................................14 STANDBY mode .............................................. 15 FAULT_SD ....................................................... 16 PMIC reset .......................................................20 Regulator control in each power mode ............ 22 Regulator summary ......................................... 23 BUCK regulator ............................................... 23 Dynamic voltage scaling ..................................24 BUCK output voltage limiting ...........................25 Dual-phase configuration .................................25 LDO and load switch ....................................... 26 32 kHz Crystal Oscillator Driver .......................26 Load switch ......................................................27 I2C level translator .......................................... 27 Interrupt management ..................................... 28 Software interface ............................................. 30 Register map ................................................... 31 Register details ................................................ 34 0x00 Device_ID ............................................... 34 0x01 INT1 ........................................................ 34 0x02 INT1_MSK .............................................. 35 0x03 STATUS1 ................................................ 35 0x04 STATUS2 ................................................ 36 0x05 PWRON_STAT ........................................36 0x06 SW_RST .................................................37 0x07 PWR_CTRL ............................................ 37 0x08 RESET_CTRL .........................................38 0x09 CONFIG1 ................................................ 39 0x0A CONFIG2 ............................................... 39 0x0C BUCK123_DVS ...................................... 40 0x0D BUCK1OUT_LIMIT .................................40 0x0E BUCK2OUT_LIMIT ................................. 40 0x0F BUCK3OUT_LIMIT ................................. 41 0x10 BUCK1CTRL ...........................................41 0x11 BUCK1OUT_DVS0 ................................. 42 0x12 BUCK1OUT_DVS1 ................................. 42 0x13 BUCK2CTRL ...........................................42 0x14 BUCK2OUT_DVS0 ................................. 43 0x15 BUCK2OUT_DVS1 ................................. 43 PCA9450 Product data sheet 8.2.22 0x16 BUCK3CTRL ...........................................43 8.2.23 0x17 BUCK3OUT_DVS0 ................................. 44 8.2.24 0x18 BUCK3OUT_DVS1 ................................. 44 8.2.25 0x19 BUCK4CTRL ...........................................45 8.2.26 0x1A BUCK4OUT ............................................ 46 8.2.27 0x1B BUCK5CTRL .......................................... 46 8.2.28 0x1C BUCK5OUT ............................................47 8.2.29 0x1D BUCK6CTRL .......................................... 47 8.2.30 0x1E BUCK6OUT ............................................ 47 8.2.31 0x20 LDO_AD_CTRL ...................................... 49 8.2.32 0x21 LDO1CTRL ............................................. 49 8.2.33 0x22 LDO2CTRL ............................................. 50 8.2.34 0x23 LDO3CTRL ............................................. 50 8.2.35 0x24 LDO4CTRL ............................................. 51 8.2.36 0x25 LDO5CTRL_L ......................................... 52 8.2.37 0x26 LDO5CTRL_H .........................................52 8.2.38 0x2A LOADSW_CTRL .....................................53 8.2.39 0x2B VRFLT1_STS ......................................... 53 8.2.40 0x2C VRFLT2_STS ......................................... 54 8.2.41 0x2D VRFLT1_MASK ...................................... 55 8.2.42 0x2E VRFLT2_MASK ...................................... 55 9 Application design-in information ................... 57 9.1 Reference schematic ....................................... 57 9.1.1 PCA9450AA reference schematic ................... 57 9.1.2 PCA9450B reference schematic ......................59 9.1.3 PCA9450C reference schematic ..................... 60 9.2 Typical application ........................................... 61 9.2.1 Buck regulators ................................................61 9.2.1.1 Inductor selection for buck converters ............. 61 9.2.1.2 Output capacitor selection for buck converters ........................................................ 62 9.2.1.3 Input capacitor selection for buck converters ........................................................ 62 9.2.2 Crystal oscillator .............................................. 62 9.2.2.1 Crystal selection .............................................. 62 9.2.2.2 Effective load capacitance ............................... 63 9.2.2.3 Frequency tuning ............................................. 64 9.3 Layout guide .................................................... 64 10 Limiting values .................................................. 66 11 Recommended operating conditions .............. 67 12 Thermal characteristics ....................................68 13 Electrical characteristics .................................. 69 13.1 Top level parameter ......................................... 69 13.2 I2C level translator .......................................... 72 13.3 BUCK1 (PCA9450AA/PCA9450B) ...................73 13.4 Dual Phase BUCK1 (PCA9450C) ....................74 13.5 BUCK2 ............................................................. 75 13.6 BUCK3 (PCA9450AA) ..................................... 76 13.7 BUCK4 ............................................................. 77 13.8 BUCK5 ............................................................. 78 13.9 BUCK6 ............................................................. 79 13.10 LDO1 ................................................................80 13.11 LDO2 ................................................................81 13.12 LDO3 ................................................................82 13.13 LDO4 ................................................................83 13.14 LDO5 ................................................................84 All information provided in this document is subject to legal disclaimers. Rev. 2.1 -- 7 December 2020 (c) NXP B.V. 2020. All rights reserved. 98 / 99 PCA9450 NXP Semiconductors Power management IC for i.MX 8M application processor family 13.15 13.16 13.17 14 15 16 Load SW ..........................................................85 32 kHz Xtal driver ............................................ 86 I2C-bus interface and logic I/O ........................ 87 Package outline .................................................88 Revision history ................................................ 93 Legal information .............................................. 94 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. (c) NXP B.V. 2020. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 December 2020 Document identifier: PCA9450