NCP1236BD100R2G - ON Semiconductor

January, 2012 − Rev. 2

1Publication Order Number:

NCP1236/D

NCP1236

Fixed Frequency Current

Mode Controller for Flyback

Converters

The NCP1236 is a new fixed−frequency current−mode controller

featuring Dynamic Self−Supply (DSS). This device is pin−to−pin

compatible with the previous NCP12xx families.

The DSS function greatly simplifies the design of the auxiliary

supply and the VCC capacitor by activating the internal startup current

source to supply the controller during transients.

Due to frequency foldback, the controller exhibits excellent

efficiency in light load condition while still achieving very low

standby power consumption. Internal frequency jittering, ramp

compensation, and a versatile latch input make this controller an

excellent candidate for converters where components cost is the key

constraints.

In addition, the controller includes a new high voltage circuitry that

combines a start−up current source and a brown−out detector able to

sense the input voltage either from the rectified ac line or the dc

filtered bulk voltage. The high voltage sensing circuitry is used for the

overpower protection purposes as well. Overpower protection,

overload protection, and next protective features increases safety level

of the final application.

Finally, due to a careful design, the precision of critical parameters

is well controlled over the entire temperature range (−40°C to

+125°C).

Features

•Fixed−Frequency Current−Mode Operation with Built−In Ramp

Compensation

•65 kHz or 100 kHz Oscillator Frequency

•Frequency Foldback then Skip Mode for Maximized Performance in

Light Load and Standby Conditions

•Timer−Based Overload Protection with Latched (option A) or

Auto−Recovery (option B) Operation, Shortened Overload Timer for

Increased Safety (options C and D), (see all options on page 2)

•High−voltage Current Source with Brown−Out

detection and Dynamic Self−Supply, Simplifying the

Design of the VCC Capacitor

•Frequency Modulation for Softened EMI Signature,

including during Frequency Foldback mode

•Adjustable Overpower Compensation

•Latch−off Input for Severe Fault Conditions, Allowing

Direct Connection of an NTC for Overtemperature

Protection (OTP)

•VCC Operation up to 28 V, with Overvoltage Detection

•$500 mA Peak Source / Sink Current Drive Capability

•4.0 ms Soft−Start

•Internal Thermal Shutdown

•Pin−to−Pin Compatible with the Existing NCP12xx

Series

•These Devices are Pb−Free, Halogen Free/BFR Free

and are RoHS Compliant

Typical Applications

•AC−DC Adapters for Notebooks, LCD, and Printers

•Offline Battery Chargers

•Consumer Electronic Power Supplies

•Auxiliary/Housekeeping Power Supplies

SOIC−7

CASE 751U

MARKING

DIAGRAM

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36Xff

ALYWX

36Xff = Specific Device Code

X = A, B, C or D

ff = 65 or 100

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

See detailed ordering and shipping information in the package

dimensions section on page 33 of this data sheet.

ORDERING INFORMATION

(Top View)

Latch

PIN CONNECTIONS

GND DRV

VCC

NCP1236

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TYPICAL APPLICATION EXAMPLE

VOUT

VIN

(dc)

NCP1236

LATCH

GND

VCC

DRV

Figure 1. Flyback Converter Application Using the NCP1236

OPTIONS

Part Option Frequency OCP Fault Fault Timer

Autorecovery

Timer

NCP1236

A65 kHz Latched 128 ms 1 s

A100 kHz Latched 128 ms 1 s

B65 kHz Autorecovery 128 ms 1 s

B100 kHz Autorecovery 128 ms 1 s

C65 kHz Latched 32 ms 1.5 s

C100 kHz Latched 32 ms 1.5 s

D65 kHz Autorecovery 32 ms 1.5 s

D100 kHz Autorecovery 32 ms 1.5 s

PIN FUNCTION DESCRIPTION

Pin No Pin Name Function Pin Description

1 LATCH Latch−Off Input Pull the pin up or down to latch−off the controller. An internal current source

allows the direct connection of an NTC for over temperature detection

2 FB Feedback An optocoupler collector to ground controls the output regulation.

3 CS Current Sense This Input senses the Primary Current for current−mode operation, and Offers

an overpower compensation adjustment.

4 GND IC Ground

5 DRV Drive output Drives external MOSFET

6 VCC VCC input This supply pin accepts up to 28 Vdc, with overvoltage detection

8 HV High−voltage pin Connects to the bulk capacitor or the rectified AC line to perform the functions

of Start−up Current Source, Dynamic Self−Supply and brown−out detection

NCP1236

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SIMPLIFIED INTERNAL BLOCK SCHEMATIC

Figure 2. Simplified Internal Block Schematic

Reset

Brown−out

−

tLEB

blanking

/ 5

tfault timer

VFB(ref)

20 kW

−

VILIM

VCS(stop)

tSSTART

Soft−start ramp Start

Reset

IC Start

IC Stop

Oscillator

DCMAX

VCC

Latch

−

Vskip

Protection

Mode

release

tautorec

timer

For

Autorecovery

protection

mode only

DRV

HV sample

Clamp

UVLO

Fault

Sawtooth

Jitter

Brown−out

−

V to I

HV sample

IOPC = 0.5m x

(VHV − 125)

−

VFB(OPC)

Latch

Dual HV

start−up

current source

VCC

management

HV currentTSD

VDD

UVLO

Reset

TSD

Start

IC Start

PWM

Soft−start

ILIMIT

Reset

VDD

UVLO

IC stop

TSD

HV dc

ILIMIT

PWM

Fault Flag

Foldback

GND

Stop

DMAX

tBCS

blanking

−

VOVP

−

VOTP

tLatch(OVP)

blanking

VDD

Brown−out

Reset

Latch

Vclamp

INTC

tLatch(OTP)

blanking

1 kW

INTC

Soft−start

end

Soft−start end

End

slope

comp.

VCC OVP OVP

VCC OVP

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MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Pin (pin 6) (Note 2)

Voltage range

Current range

VCCMAX

ICCMAX

–0.3 to 28

$30

High Voltage Pin (pin 8) (Note 2)

Voltage range

Current range

VHVMAX

IHVMAX

–0.3 to 500

$20

Driver Pin (pin 5) (Note 2)

Voltage range

Current range

VDRVMAX

IDRVMAX

–0.3 to 20

$1000

All other pins (Note 2)

Voltage range

Current range

VMAX

IMAX

–0.3 to 10

$10

Thermal Resistance SOIC−7

Junction−to−Air, low conductivity PCB (Note 3)

Junction−to−Air, medium conductivity PCB (Note 4)

Junction−to−Air, high conductivity PCB (Note 5)

RθJ−A162

147

115

°C/W

Temperature Range

Operating Junction Temperature

Storage Temperature Range

TJMAX

TSTRGMAX

−40 to +150

−60 to +150

°C

ESD Capability (Note 1)

Human Body Model (All pins except HV)

Machine Model

2000

200

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC standard JESD22, Method A114E

Machine Model Method 200 V per JEDEC standard JESD22, Method A115A

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78

3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat spreading area. As specified

for a JEDEC 51−1 conductivity test PCB. Test conditions were under natural convection or zero air flow.

4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified

for a JEDEC 51−2 conductivity test PCB. Test conditions were under natural convection or zero air flow.

5. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified

for a JEDEC 51−3 conductivity test PCB. Test conditions were under natural convection or zero air flow.

NCP1236

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,

VCC = 11 V unless otherwise noted)

Characteristics Test Condition Symbol Min Typ Max Unit

HIGH VOLTAGE CURRENT SOURCE

Minimum voltage for current

source operation

VHV(min) −30 60 V

Current flowing out of VCC pin VCC = 0 V

VCC = VCC(on) − 0.5 V

Istart1

Istart2

0.2

0.5

0.8

Off−state leakage current VHV = 500 V Istart(off) −25 50 mA

SUPPLY

Turn−on threshold level, VCC

going up

HV current source stop threshold

VCC(on) 11.0 12.0 13.0 V

HV current source restart threshold VCC(min) 9.5 10.5 11.5 V

Turn−off threshold VCC(off) 8.5 9.5 10.5 V

Overvoltage threshold VCC(ovp) 25 26.5 28 V

Blanking duration on VCC(off) and

VCC(ovp) detection

tVCC(blank) 7 10 13 ms

VCC decreasing level at which

the internal logic resets

VCC(reset) 3.6 5.0 6.0 V

VCC level for ISTART1 to ISTART2

transition

VCC(inhibit) 0.4 1.0 1.6 V

Internal current consumption

(Note 6)

DRV open, VFB = 3 V, 65 kHz

DRV open, VFB = 3 V, 100 kHz

Cdrv = 1 nF, VFB = 3 V, 65 kHz

Cdrv = 1 nF, VFB = 3 V, 100 kHz

Off mode (skip or before start−up)

Fault mode (fault or latch)

ICC1

ICC2

ICC3

ICC4

1.2

1.9

2.2

0.67

0.4

1.8

1.9

2.5

2.9

0.9

0.7

2.2

2.3

3.2

3.6

1.13

1.0

BROWN−OUT

Brown−Out thresholds VHV going up

VHV going down

VHV(start)

VHV(stop)

107

122

105

Timer duration for line cycle

drop−out

tHV 47 68 90 ms

OSCILLATOR

Oscillator frequency fOSC 60

100

108

kHz

Maximum duty cycle DMAX 75 80 85 %

Frequency jittering amplitude, in

percentage of FOSC

Ajitter $4$6$8 %

Frequency jittering modulation

frequency

Fjitter 85 125 165 Hz

OUTPUT DRIVER

Rise time, 10% to 90 % of VCC VCC = VCC(min) + 0.2 V, CDRV = 1 nF trise −40 70 ns

Fall time, 90% to 10 % of VCC VCC = VCC(min) + 0.2 V, CDRV = 1 nF tfall −40 70 ns

Current capability VCC = VCC(min) + 0.2 V, CDRV = 1 nF

DRV high, VDRV = 0 V

DRV low, VDRV = VCC

IDRV(source)

IDRV(sink)

−

500

−

Clamping voltage (maximum

gate voltage)

VCC = VCCmax – 0.2 V, DRV high, RDRV

= 33 kW, Cload = 220 pF

VDRV(clamp) 11 13.5 16 V

High−state voltage drop VCC = VCC(min) + 0.2 V, RDRV = 33 kW,

DRV high

VDRV(drop) − − 1 V

6. internal supply current only, current in FB pin not included (current flowing in GND pin only).

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,

VCC = 11 V unless otherwise noted)

Characteristics Test Condition Symbol Min Typ Max Unit

CURRENT SENSE

Input Bias Current VCS = 0.7 V Ibias −0.02 −mA

Maximum internal current

setpoint

VFB > 3.5 V VILIM 0.66 0.7 0.74 V

Propagation delay from VIlimit

detection to DRV off

VCS = VILIM tdelay −80 110 ns

Leading Edge Blanking Duration

for VILIM

tLEB 190 250 310 ns

Threshold for immediate fault

protection activation

VCS(stop) 0.95 1.05 1.15 V

Leading Edge Blanking Duration

for VCS(stop)

tBCS 90 120 150 ns

Slope of the compensation ramp Scomp(65kHz)

Scomp(100kHz)

−

−32.5

−50

−

mV /

Soft−start duration From 1st pulse to VCS = VILIM tSSTART 2.8 4.0 5.2 ms

OVERPOWER COMPENSATION

VHV to IOPC conversion ratio KOPC −0.54 −mA / V

Current flowing out of CS pin VHV = 125 V

VHV = 162 V

VHV = 325 V

VHV = 365 V

IOPC(125)

IOPC(162)

IOPC(325)

IOPC(365)

−

105

110

130

−

150

FB voltage above which IOPC is

applied

VHV = 365 V VFB(OPCF) 2.12 2.35 2.58 V

FB voltage below which is no

IOPC applied

VHV = 365 V VFB(OPCE) −2.15 −V

Watchdog timer for dc operation tWD(OPC) −32 −ms

FEEDBACK

Internal pull−up resistor TJ = 25°C RFB(up) 15 20 25 kW

VFB to internal current setpoint

division ratio

KFB 4.7 5 5.3 −

Internal pull−up voltage on the

FB pin

VFB(ref) 4.3 5 5.7 V

OVERCURRENT PROTECTION

Fault timer duration From CS reaching VILIMIT to DRV stop tfault 98 128 168 ms

Fault timer duration (for the C

version only)

From CS reaching VILIMIT to DRV stop tfault 16 32 48 ms

Autorecovery mode latch−off

time duration

tautorec 0.85 1.00 1.35 s

Autorecovery mode latch−off

time duration (for the C version

only)

tautorec 1.0 1.5 2.0 s

FREQUENCY FOLDBACK

Feedback voltage threshold

below which frequency foldback

starts

VFB(foldS) 1.8 2.0 2.2 V

Feedback voltage threshold

below which frequency foldback

is complete

VFB(foldE) 1.22 1.35 1.48 V

Minimum switching frequency VFB = Vskip(in) + 0.2 fOSC(min) 22 27 32 kHz

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,

VCC = 11 V unless otherwise noted)

Characteristics UnitMaxTypMinSymbolTest Condition

SKIP−CYCLE MODE

Feedback voltage thresholds for

skip mode

VFB going down

VFB going up

Vskip(in)

Vskip(out)

0.63

0.72

0.7

0.80

0.77

0.88

LATCH−OFF INPUT

High threshold VLatch going up VOVP 2.35 2.5 2.65 V

Low threshold VLatch going down VOTP 0.76 0.8 0.84 V

Current source for direct NTC

connection

During normal operation

During soft−start

VLatch = 0 V

INTC

INTC(SSTART)

130

190

105

210

Blanking duration on high latch

detection

65 kHz version

100 kHz version

tLatch(OVP) 35

Blanking duration on low latch

detection

tLatch(OTP) −350 −ms

Clamping voltage ILatch = 0 mA

ILatch = 1 mA

Vclamp0(Latch)

Vclamp1(Latch)

1.0

2.0

1.2

2.4

1.4

3.0

TEMPERATURE SHUTDOWN

Temperature shutdown (Note 7) TJ going up TTSD 135 150 165 °C

Temperature shutdown

hysteresis (Note 7)

TJ going down TTSD(HYS) 20 30 40 °C

7. Guaranteed by design.

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TYPICAL PERFORMANCE CHARACTERISTICS

20.00

22.00

24.00

26.00

28.00

30.00

32.00

34.00

36.00

38.00

40.00

−50 −25 0 25 50 75 100 125

Figure 3. Minimum Current Source Operation

VHV(min)

TEMPERATURE (°C)

VHV(min) (V)

−50 −25 0 25 50 75 100 125

Figure 4. Off−State Leakage Current Istart(off)

TEMPERATURE (°C)

Istart(off) (V)

100

105

110

115

120

−50 −25 0 25 50 75 100 125

VHV(start) (V)

TEMPERATURE (°C)

Figure 5. Brown−out Device Start Threshold

VHV(start)

100

105

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

VHV(stop) (V)

Figure 6. Brown−Out Device Stop Threshold

VHV(stop)

0.65

0.66

0.67

0.68

0.69

0.70

0.71

0.72

0.73

0.74

0.75

−50 −25 0 25 50 75 100 125

VILIM (V)

TEMPERATURE (°C)

Figure 7. Maximum Internal Current Setpoint

VILIM

0.95

0.97

0.99

1.01

1.03

1.05

1.07

1.09

1.11

1.13

1.15

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

VCS(stop) (V)

Figure 8. Threshold for Immediate Fault

Protection Activation VCS(stop)

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TYPICAL PERFORMANCE CHARACTERISTICS

100

110

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

tdelay (ns)

Figure 9. Propagation Delay tdelay

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

tLEB (ns)

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

RFB(up) (kW)

Figure 10. Leading Edge Blanking Duration

tLEB

Figure 11. FB Pin Internal Pull−up Resistor

RFB(up)

4.60

4.70

4.80

4.90

5.00

5.10

5.20

5.30

−50 −25 0 25 50 75 100 125

VFB(ref) (V)

TEMPERATURE (°C)

Figure 12. FB Pin Open Voltage VFB(ref)

TEMPERATURE (°C)

fOSC (kHz)

Figure 13. Oscillator Frequency fOSC for the 65

kHz version

200

210

220

230

240

250

260

270

280

290

300

−50 −25 0 25 50 75 100 125

Figure 14. Oscillator Frequency fOSC for the

100 kHz version

100

101

102

103

104

105

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

fOSC (kHz)

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TYPICAL PERFORMANCE CHARACTERISTICS

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

DMAX (%)

Figure 15. Maximum Duty Cycle DMAX

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

−50 −25 0 25 50 75 100 12

VFB(foldS) (V)

TEMPERATURE (°C)

Figure 16. FB Pin Voltage Below Which

Frequency Foldback Starts VFB(foldS)

1.20

1.25

1.30

1.35

1.40

1.45

1.50

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

VFB(foldE) (V)

Figure 17. FB Pin Voltage Below Which

Frequency Foldback is Complete VFB(foldE)

0.63

0.65

0.67

0.69

0.71

0.73

0.75

0.77

−50 −25 0 25 50 75 100 12

Vskip(in) (V)

TEMPERATURE (°C)

Figure 18. FB Pin Skip−in Level Vskip(in)

0.72

0.74

0.76

0.78

0.80

0.82

0.84

0.86

0.88

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

Vskip(out) (V)

Figure 19. FB Pin Skip−Out Level Vskip(out)

−50 −25 0 25 50 75 100 12

fOSC(min) (kHz)

TEMPERATURE (°C)

Figure 20. Minimum Switching Frequency

fOSC

(

min

)

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TYPICAL PERFORMANCE CHARACTERISTICS

110

115

120

125

130

135

140

145

150

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

IOPC(365) (mA)

Figure 21. Maximum Overpower

Compensating Current IOPC(365) Flowing Out

of CS Pin

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

−50 −25 0 25 50 75 100 12

Figure 22. FB Pin Level VFB(OPCF) Above

Which is the Overpower Compensation

Applied

VFB(OPCF) (V)

TEMPERATURE (°C)

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

VFB(OPCE) (V)

Figure 23. FB Pin Level VFB(OPCE) Below

Which is No Overpower Compensation

Applied

2.35

2.40

2.45

2.50

2.55

2.60

2.65

−50 −25 0 25 50 75 100 12

VOVP (V)

TEMPERATURE (°C)

Figure 24. Latch Pin High Threshold VOVP

0.75

0.76

0.77

0.78

0.79

0.80

0.81

0.82

0.83

0.84

0.85

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

VOTP (V)

Figure 25. Latch Pin Low Threshold VOTP

1.18

1.20

1.22

1.24

1.26

1.28

1.30

1.32

1.34

−50 −25 0 25 50 75 100 12

Vclamp0 (V)

TEMPERATURE (°C)

Figure 26. Latch Pin Open Voltage Vclamp0

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TYPICAL PERFORMANCE CHARACTERISTICS

2.00

2.10

2.20

2.30

2.40

2.50

2.60

2.70

2.80

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

Vclamp1 (V)

Figure 27. Latch Pin Voltage Vclamp1 (Latch−off

Pin is Sinking 1 mA)

100

105

110

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

INTC (mA)

Figure 28. Current INTC Sourced from the

Latch Pin, Allowing Direct NTC Connection

140

150

160

170

180

190

200

210

220

−50 −25 0 25 50 75 100 125

INTC(SSTART) (mA)

TEMPERATURE (°C)

Figure 29. Current INTC(SSTART) Sourced from

the Latch Pin, During Soft−Start

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APPLICATION INFORMATION

Introduction

The NCP1236 includes all necessary features to build a safe

and efficient power supply based on a fixed−frequency

flyback converter. It is particularly well suited for

applications where low part count is a key parameter,

without sacrificing safety.

•Current−Mode Operation with slope compensation:

The primary peak current is permanently controlled by

the FB voltage, ensuring maximum safety: the DRV

turn−off event is dictated by the peak current setpoint.

It also ensures that the frequency response of the

system stays a first order if in DCM, which eases the

design of the FB loop. The controller can be also used

in CCM applications with a wide input voltage range

thanks to its fixed ramp compensation that prevents the

appearance of sub−harmonic oscillations.

•Fixed−Frequency Oscillator with Jittering: The

NCP1236 is available in different frequency options to

fit any application. The internal oscillator features a

low−frequency jittering that helps passing the EMI

limits by spreading out the energy content of frequency

peaks in quasi−peak and average mode of

measurement.

•Latched / Autorecovery Timer−Based Overload

Protection: The overload protection depends only on

the FB signal, making it able to work with any

transformer, even with very poor coupling or high

leakage inductance. When the fault timer elapses the

device can be permanently latched in version A or the

latch can be reset by an autorecovery restart of the

device in version B. The power supply has to be

stopped then restarted in order to resume operation,

even if the overload condition disapears, in case of

usage the A version of the NCP1236. The fault timer

duration is internally fixed. The controller also latches

off if the voltage on the CS pin reaches 1.5 times the

maximum internal setpoint (allowing to detect winding

short−circuits), with the same modes of releasing the

latch in A or B version.

•High Voltage Start−Up Current Source with

Brown−Out Detection: Due to ON Semiconductor’s

Very High Voltage technology, the NCP1236 can be

directly connected to the high input voltage. The

start−up current source ensures a clean start−up and the

Dynamic Self−Supply (DSS) restarting the start−up

current source to supply the controller if the VCC

voltage transiently drops. The high voltage pin also

features a high−voltage sensing circuitry, which is able

to turn the controller off if the input voltage is too low

(brown−out condition). This protection works either

with a DC input voltage or a rectified AC input voltage,

and is independent of the high voltage ripple.

•Adjustable Overpower Compensation: The high

input voltage sensed on the HV pin is converted into a

current to build on the current sense voltage an offset

proportional to the input voltage. By choosing the value

of the resistor in series with the CS pin, the amount of

compensation can be adjusted to the application.

•Frequency foldback then skip mode for light load

operation: In order to ensure a high efficiency under all

load conditions, the NCP1236 implements a frequency

foldback for light load condition and a skip mode for

extremely low load condition. The switching frequency

is decreased down to 27 kHz to reduce switching

losses.

•Extended VCC range: The NCP1236 accepts a supply

voltage as high as 28 V, with an overvoltage threshold

VCC(ovp) (typically 26.5 V) that latches the controller

off.

•Clamped Driver Stage: Despite the high maximum

supply voltage, the voltage on DRV pin is safely

clamped below 16 V, allowing the use of any standard

MOSFET, and reducing the current consumption of the

controller.

•Dual Latch−off Input: The NCP1236 can be latched

off by 2 ways: The voltage increase applied to its Latch

pin (typically an overvoltage) or by a decrease this

voltage. Thanks to the internal precise pull−up current

source a NTC can be directly connected to the latch pin.

This NTC will provide an overtemperature protection

by decreasing its resistance and consequently the

voltage at Latch pin,

•Soft−Start: At every start−up the peak current is

gradually increased during 4.0 ms to minimize the

stress on power components.

•Temperature Shutdown: The NCP1236 is internally

protected against self−overheating: if the die

temperature is too high, the controller shuts all

circuitries down (including the HV start−up current

source), allowing the silicon to cool down before

attempting to restart. This ensures a safe behavior in

case of failure.

NCP1236

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Typical Operation

•Start−up: The HV start−up current source ensures the

charging of the VCC capacitor up to the start−up

threshold VCC(on), until the input voltage is high

enough (above VHV(start)) to allow the switching to

start. The controller then delivers pulses, starting with a

soft−start period tSSTART during which the peak current

linearly increases before the current−mode control takes

over. During the soft−start period, the low level latch is

ignored, and the latch current is double, to ensure a fast

pre−charge of the Latch pin decoupling capacitor.

•Normal operation: As long as the feedback voltage is

within the regulation range and VCC is maintained

above VCC(min), the NCP1236 runs at a fixed frequency

(with jittering) in current−mode control. The peak

current (sensed on the CS pin) is set by the voltage on

the FB pin. Fixed ramp compensation is applied

internally to prevent sub−harmonic oscillations from

occurring.

•Light load operation: When the FB voltage decreases

below VFB(foldS), typically corresponding to a load of

33 % of the maximum load (for a DCM design), the

switching frequency starts to decrease down to

fOSC(min). By lowering the switching losses, this feature

helps to improve the efficiency in light load conditions.

The frequency jittering is enabled in light load

operation as well.

•No load operation: When the FB voltage decreases

below Vskip(in), typically corresponding to a load of 2

% of the maximum load, the controller enters skip

mode. By completely stopping the switching while the

feedback voltage is below Vskip(out), the losses are

further reduced. This allows minimizing the power

dissipation under extremely low load conditions. As the

skip mode is entered at very light loads, for which the

peak current is very small, there is no risk of audible

noise. VCC can be maintained between VCC(on) and

VCC(min) by the DSS, if the auxiliary winding does not

provide sufficient level of VCC voltage under this

condition.

•Overload: The NCP1236 features timer−based

overload detection, solely dependent on the feedback

information: as soon as the internal peak current

setpoint hits the VILIM clamp, an internal timer starts to

count. When the timer elapses, the controller stops and

enter the protection mode, autorecovery for the B

version (the controller initiates a new start−up after

tautorec elapses), or latched for the A version (the latch

is released if a brown−out event occurs or VCC is reset).

•Brown−out: The NCP1236 features a true AC line

monitoring circuitry. It includes a minimum start−up

threshold and an autorecovery brown−out protection;

both of them independent of the ripple on the input

voltage. It can even work with an unfiltered, rectified

AC input. The thresholds are fixed, but they are

designed to fit most of the standard AC−DC conversion

applications.

•Latch−off: When the Latch input is pulled up (typically

by an over−voltage condition), or pulled down

(typically by an over−temperature condition, using the

provided current source with an NTC), the controller

latches off. A voltage higher than VCC(ovp) on the VCC

pin has the same effect. The latch is released when a

brown−out condition occurs, or when the VCC is reset.

NCP1236

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DETAILED DESCRIPTION

High−Voltage Current Source with Built−in Brown−out

Detection

The NCP1236 HV pin can be connected either to the

rectified bulk voltage, or to the ac line through a rectifier.

Start−up

−

TSD

VCC

Istart

VCC(on)

VCC(off )

tUVLO(blank)

blanking

Control

UVLO

−

VCC(reset)

Reset

IC Start

−

VCC(min)

Figure 30. HV Start−up Current Source Functional Schematic

At start−up, the current source turns on when the voltage

on the HV pin is higher than VHV(min), and turns off when

VCC reaches VCC(on), then turns on again when VCC reaches

VCC(min), until the input voltage is high enough to ensure a

proper start−up, i.e. when VHV reaches VHV(start). The

controller actually starts the next time VCC reaches VCC(on).

Even though the DSS is able to maintain the VCC voltage

between VCC(on) and VCC(min) by turning the HV start−up

current source on and off, it can only be used in light load

condition, otherwise the power dissipation on the die would

be too much. As a result, an auxiliary voltage source is

needed to supply VCC during normal operation.

The DSS is useful to keep the controller alive when no

switching pulses are delivered, e.g. in brown−out condition,

or to prevent the controller from stopping during load

transients when the VCC might drop.

If the voltage increases above the overvoltage protection

threshold VCC(ovp), the controller is latched off.

NCP1236

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time

VHV

time

VCC

time

DRV

VHV(start)

VHV(min)

VCC(on)

VCC(min)

VCC(inhibit)

current

source =

Istart1

current

source =

Istart2

Waits

VCC(on)

before

starting

Figure 31. Start−up Timing Diagram

For safety reasons, the start−up current is lowered when

VCC is below VCC(inhibit), to reduce the power dissipation in

case the VCC pin is shorted to GND (in case of VCC capacitor

failure, or external pull−down on VCC to disable the

controller).

There are only two conditions for which the current source

doesn’t turn on when VCC reaches VCC(min): the voltage on

HV pin is too low (below VHV(min)), or a thermal shutdown

condition (TSD) has been detected. In all other conditions,

the HV current source will always turn on and off to maintain

VCC between VCC(min) and VCC(on).

Brown−out protection

When the input voltage goes below VHV(stop), a

brown−out condition is detected, and the controller stops.

The HV current source alternatively turns on and off to

maintain VCC between VCC(on) and VCC(min) until the input

voltage is back above VHV(start).

NCP1236

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time

HV stop

time

VCC

time

DRV

VCC(on)

VCC(min)

Waits next

VCC(on) before

starting

Brown-out

or AC OVP

detected

Figure 32. Brown−out Timing Diagram

When VHV crosses the VHV(start) threshold, the controller

can start immediately. When it crosses VHV(stop), it triggers

a timer of duration tHV: this ensures that the controller

doesn’t stop in case of line cycle drop−out.

NCP1236

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time

VHV

time

DRV

VHV(start)

Starts at next

VCC(ON)

VHV(stop)

Brown-out

Figure 33. AC Input Brown−out Timing Diagram

Oscillator with Maximum Duty Cycle and Frequency

Jittering

The NCP1236 includes an oscillator that sets the

switching frequency with an accuracy of $7%. Two

frequency options can be ordered: 65 kHz and 100 kHz. The

maximum duty cycle of the DRV pin is 80%, with an

accuracy of $7%.

In order to improve the EMI signature, the switching

frequency jitters $6% around its nominal value, with a

triangle−wave shape and at a frequency of 125 Hz. This

frequency jittering is active even when the frequency is

decreased to improve the EMI in light load condition.

Time

(125 Hz)

Figure 34. Frequency Jittering

fOSC

fOSC + 6

Nominal fOSC

fOSC − 6

Clamped Driver

The supply voltage for the NCP1236 can be as high as

28 V, but most of the MOSFETs that will be connected to the

DRV pin cannot accept more than 20 V on their gate. The

driver pin is therefore clamped safely below 16 V. This

driver has a typical current capability of $500 mA.

Figure 35. Clamped Driver

DRV

Clamp

DRV signal

VCC

NCP1236

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CURRENT−MODE CONTROL WITH OVERPOWER COMPENSATION AND SOFT−START

Current sensing

NCP1236 is a current−mode controller, which means that

the FB voltage sets the peak current flowing in the

inductance and the MOSFET. This is done through a PWM

comparator: the current is sensed across a resistor and the

resulting voltage is applied to the CS pin. It is applied to one

input of the PWM comparator through a 250 ns LEB block.

On the other input the FB voltage divided by 5 sets the

threshold: when the voltage ramp reaches this threshold, the

output driver is turned off.

The maximum value for the current sense is 0.7 V, and it

is set by a dedicated comparator.

−

tLEB

blanking

KFB

RFB(up)

−

VILIM

VCS(stop)

tSSTART

Soft−start ramp

Start

Reset

IC Start

IC Stop

Oscillator

DCMAX

Protection

Mode

UVLO

Jitter

HV stop

Latch

Soft−start

IC stop

TSD

Fault

DRV Stage

blanking

PWM

tBCS

Figure 36. Current Sense Block Schematic

VFB(ref)

Each time the controller is starting, i.e. the controller was

off and starts – or restarts – when VCC reaches VCC(on), a

soft−start is applied: the current sense setpoint is linearly

increased from 0 (the minimum level can be higher than 0

because of the LEB and propagation delay) until it reaches

VILIM (after a duration of tSSTART), or until the FB loop

imposes a setpoint lower than the one imposed by the

soft−start (the 2 comparators outputs are OR’ed). The

soft−start ramp signal is generated by the D/A converter in

the NCP1236, that’s why there are observable 15 discrete

steps instead the truly linearly increasing current setpoint

ramp.

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Time

VFB

VFB(fault)

Time

Soft-start ramp

VILIM

tSSTART

Time

CS Setpoint

VILIMI

VFB takes

over soft-start

Figure 37. Soft−Start

Under some conditions, like a winding short−circuit for

instance, not all the energy stored during the on time is

transferred to the output during the off time, even if the on

time duration is at its minimum (imposed by the propagation

delay of the detector added to the LEB duration). As a result,

the current sense voltage keeps on increasing above VILIM,

because the controller is blind during the LEB blanking

time. Dangerously high current can grow in the system if

nothing is done to stop the controller. That’s what the

additional comparator, that senses when the current sense

voltage on CS pin reaches VCS(stop) (= 1.5 x VILIM), does:

as soon as this comparator toggles, the controller

immediately enters the protection mode (latched or

autorecovery according to the chosen option).

Overpower compensation

The power delivered by a flyback power supply is

proportional to the square of the peak current in the

discontinuous conduction mode:

POUT +1

2@h@Lp@FSW @Ip2(eq. 1)

Unfortunately, due to the inherent propagation delay of

the logic, the actual peak current is higher at high input

voltage than at low input voltage, leading to a significant

difference in the maximum output power delivered by the

power supply.

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time

High

Line Low

Line

ILIMIT

tdelay tdelay

IP to be

compensated

Figure 38. Line Compensation for True Overpower Protection

To compensate this and have an accurate overpower

protection, an offset proportional to the input voltage is

added on the CS signal by turning on an internal current

source: by adding an external resistor in series between the

sense resistor and the CS pin, a voltage offset is created

across it by the current. The compensation can be adjusted

by changing the value of the resistor.

But this offset is unwanted to appear when the current

sense signal is small, i.e. in light load conditions, where it

would be in the same order of magnitude. Therefore the

compensation current is only added when the FB voltage is

higher than VFB(OPCE).

However, because the HV pin can be connected to an ac

voltage, there is needed an additional circuitry to read or at

least closely estimate the actual voltage on the bulk

capacitor.

A/D 3 bit

Converter

Peak Detector

Tblanking

LEB

Watch

Dog

VHVstop

HV Timer

(68 ms )

(32 ms)

3 bit

Brown Out

thv

VFB( OPC)

To CS

Block

I ctrl

Figure 39. Schematic Overpower Compensation Circuit

A 3 bit A/D converter with the peak detector senses the ac

input, and its output is periodically sampled and reset, in

order to follow closely the input voltage variations. The

sample and reset events are given by the VHV(stop)

comparator used for sampling detection for the AC line

input. If only the DC high voltage input is used, no reset

signal is generated by the VHV(stop) condition and the 32 ms

watch dog is used to generate the sampling events for

sampling the DC input high voltage line.

NCP1236

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VFB

IOPC

VFB(OPCE) VFB(OPCF)

VHV

Figure 40. Overpower Compensation Current Relation to Feedback Voltage and Input Voltage

time

Sample/reset

signal

time

Peak

detector

timer

starts

timer

restarts

timer

restarts

tHV

time

One shot HV

timer

restarts

Sample

Sample Sample Sample

Reset

Reset Reset

Reset

Figure 41. Overpower Compensation

IOPC

VHV(stop)

VHV

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time

Peak

detector

time

Sample

Sample Sample

Reset

VHV

VHV(stop)

IOPC

Figure 42. Overpower Compensation

twd twd twd

tHV

Feedback with Slope Compensation

The ratio from the FB voltage to the current sense setpoint

is 5, meaning that the FB voltage corresponding to VILIM is

3.5 V. There is a pull−up resistor of 20 kW from FB pin to an

internal reference.

−

blanking

Oscillator

20 kW

KFB

slope

comp.

PWM

VFB(ref)

Figure 43. FB Circuitry

tLEB

In order to allow the NCP1236 to operate in CCM with a

duty cycle above 50 %, a fixed slope compensation is

internally applied to the current−mode control. The slope

appearing on the internal voltage setpoint for the PWM

comparator is −32.5 mV/ms typical for the 65 kHz version,

and −50 mV/ms for the 100 kHz version.

NCP1236

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Overcurrent protection with Fault timer

When an overcurrent occurs on the output of the power

supply, the FB loop asks for more power than the controller

can deliver, and the CS setpoint reaches VILIMIT. When this

event occurs, an internal tfault timer is started: once the timer

elapsed, DRV pulses are stopped and the controller is either

latched off (latched protection, version A), or it enters an

autorecovery mode (version B). The timer is reset when the

CS setpoint goes back below VILIM before the timer elapses.

The fault timer is also started if the driver signal is reset by

the max duty cycle.

−

tLEB

blanking

/ 5

−

VILIM

Protection

Mode

Brown−out

tfault

timer

release

t autorec

timer

Reset

Autorecovery

protection

mode only

PWM

Reset DRV

Fault Flag

DC MAX

DRV

Figure 44. Timer−Based Overcurrent Protection

In autorecovery mode, the controller tries to restart after

tautorec. If the fault has gone, the supply resumes operation;

if not, the system starts a new burst cycle.

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time

Fault Flag

time

VCC

time

DRV

CC(on)

CC(min)

Overcurrent

applied

time

Output Load

Max Load

time

Fault timer

tfault

Fault

timer

starts

Controller

stops

Fault

disappears

tfault tautorec

Restart

At V

CC(on)

(new burst

cycle if Fault

still present)

Figure 45. Autorecovery Timer−Based Protection Mode

In the latched version, the controller can restart only if a

brown−out or a VCC reset occurs, which in a real application

can only happen if the power supply is unplugged from the

mains line.

NCP1236

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time

Fault Flag

time

VCC

time

DRV

CC(on)

CC(min)

Overcurrent

applied

time

Output Load

Max Load

time

Fault timer

tfault

Fault

timer

starts

Controller

latches off

No restart

when fault

disappears

tfault

Figure 46. Latched Timer−Based Overcurrent Protection

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LOW LOAD OPERATION

Frequency Foldback

In order to improve the efficiency in light load conditions,

the frequency of the internal oscillator is linearly reduced

from its nominal value down to fOSC(min). This frequency

foldback starts when the voltage on FB pin goes below

VFB(foldS), and is complete before VFB reaches Vskip(in),

whatever the nominal switching frequency option is. The

current−mode control is still active while the oscillator

frequency decreases. Note that the frequency foldback is

disabled if the controller runs at its maximum duty cycle.

fOSC

Nominal fOSC

Vskip(in) VFB(foldS)

fOSC(min)

Skip

Figure 47. Frequency Foldback when the FB Voltage Decreases

VFB(foldE)

Skip Cycle Mode

Figure 48. Skip Cycle Schematic

−

blanking

−

DRV stage

Vskip

KFB

tLEB

When the FB voltage reaches Vskip(in) while decreasing,

skip mode is activated: the driver stops, and the internal

consumption of the controller is decreased. While VFB is

below Vskip(out), the controller remains in this state; but as

soon as VFB crosses the skip out threshold, the DRV pin

starts to pulse again.

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Time

DRV

Enters

skip

Exits

skip

Enters

skip

Exits

skip

Figure 49. Skip Cycle Timing Diagram

VFB

VFB(fold)

Vskip(out)

Vskip(in)

Latch−off Input

−

Latch

VOVP

−

VOTP

tLatch(OVP)

blanking

VDD

Brown−out

Reset

Latch

Vclamp

INTC

tLatch(OTP)

blanking

1 kW

INTC

Soft−start

end

Figure 50. Latch Detection Schematic

The Latch pin is dedicated to the latch−off function: it

includes two levels of detection that define a working

window, between a high latch and a low latch: within these

two thresholds, the controller is allowed to run; but as soon

as either the low or the high threshold is crossed, the

controller is latched off. The lower threshold is intended to

be used with an NTC thermistor, thanks to an internal current

source INTC.

An active clamp prevents the voltage from reaching the

high threshold if it is only pulled up by the INTC current. To

reach the high threshold, the pull−up current has to be higher

than the pull−down capability of the clamp (typically

1.5 mA at VOVP).

To avoid any false triggering, spikes shorter than 50 ms

(for the high latch) or 350 ms (for the low latch) are blanked

and only longer signals can actually latch the controller.

Reset occurs when a brown−out condition is detected or

the VCC is cycled down to a reset voltage, which in a real

application can only happen if the power supply is

unplugged from the AC line.

Upon start−up, the internal references take some time

before being at their nominal values; so one of the

comparators could toggle even if it should not. Therefore the

internal logic does not take the latch signal into account

before the controller is ready to start: once VCC reaches

VCC(on), the latch pin High latch state is taken into account

NCP1236

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and the DRV switching starts only if it is allowed; whereas

the Low latch (typically sensing an overtemperature) is

taken into account only after the soft−start is finished. In

addition, the NTC current is doubled to INTC(SSTART) during

the soft−start period, to speed up the charging of the Latch

pin capacitor. The maximum value of Latch pin capacitor is

given by the following formula (The standard start−up

condition is considered and the NTC current is neglected) :

CLATCHmax +

tSSTARTmin @INTC(SSTART)min

Vclamp0min (eq. 2)

+2.8 @10−3@130 @10−6

1.0 F+364 nF

time

Internal Latch Signal

time

VCC

time

DRV

VCC(on)

VCC(min)

Latch signal

high during

pre-start phase

Noise spike

ignored

(tLatch blanking)

Start-up

initiated by

VCC(on)

Switching

allowed (no

latch event)

Latch-off

Figure 51. Latch−off Function Timing Diagram

Temperature Shutdown

The die includes a temperature shutdown protection with

a trip point guaranteed above 135°C and below 165°C, and

a typical hysteresis of 30°C. When the temperature rises

above the high threshold, the controller stops switching

instantaneously, and the HV current source is turned off.

Internal logic state is reset. When the temperature falls

below the low threshold, the HV start−up current source is

enabled, and a regular start−up sequence takes place.

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STATE DIAGRAMS

HV Start−up Current Source

Stop

Istart1

Istart2

Off

No TSD

TSD

VCC > VCC(inhibit)

VCC < VCC(inhibit)

VCC > VCC(on)

VCC < VCC(min)

TSD

Figure 52. HV Start−up Current Source State Diagram

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Controller Operation (Latched Version: A Option)

Stopped

Running

• Brown−out

• TSD

VCC >V

CC(on)

• Brown−out

• TSD

Skip out

With Fault=

•tfault expires

•VCS >V

CS(stop)

•VCC <V

CC(off)

Soft−start

Soft−start ends

Skip

Skip in

• Brown−out

• TSD

• Brown−out

• TSD

Latch

• Brown−out

• VCC reset

•High Latch

• VCC >V

CC(ovp)

• High Latch

• Low Latch

• VCC >V

CC(ovp)

• Fault

• High Latch

• Low Latch

• VCC >V

CC(ovp)

Figure 53. Controller Operation State Diagram (Latched Protection)

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Controller Operation (Autorecovery Version: B Option)

Stopped

Running

• Fault

• Brown−out

• TSD

VCC >V

CC(on)

• tautorec counting

• Brown−out

• TSD

Skip out

With Fault=

•tfault expires

•VCS >V

CS(stop)

•VCC <V

CC(off)

Soft−start

Soft−start ends

Skip

Skip in

• Brown−out

• TSD

• Brown−out

• TSD

Latch

• Brown−out

• VCC reset

•High Latch

• VCC >V

CC(ovp)

• High Latch

• Low Latch

• VCC >V

CC(ovp)

• High Latch

• Low Latch

• VCC >V

CC(ovp)

Figure 54. Controller Operation State Diagram (Autorecovery Protection)

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Table 1. ORDERING INFORMATION

Part No.

Switching

Frequency

Overload

Protection Fault Timer Package Shipping†

NCP1236AD65R2G 65 kHz Latched 128 ms

SOIC−7

(Pb−Free) 2500 / Tape & Reel

NCP1236AD100R2G 100 kHz Latched 128 ms

NCP1236BD65R2G 65 kHz Autorecovery 128 ms

NCP1236BD100R2G 100 kHz Autorecovery 128 ms

NCP1236CD65R2G (Note 8) 65 kHz Latched 32 ms

NCP1236CD100R2G (Note 8) 100 kHz Latched 32 ms

NCP1236DD65R2G 65 kHz Autorecovery 32 ms

NCP1236DD100R2G (Note 8) 100 kHz Autorecovery 32 ms

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

8. Contact your ON Semiconductor Sales Representative. These parts will be released upon customer request.

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PACKAGE DIMENSIONS

SOIC−7

CASE 751U

ISSUE E

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B ARE DATUMS AND T

IS A DATUM SURFACE.

4. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−A−

−B−

0.25 (0.010)

−T−

0.25 (0.010) TSAS

7 PL

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

NCP1236/D

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative