1
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
■ Selects between two clocks, and provides 8
precision, low skew LVPECL output copies
■ Guaranteed AC performance over temperature and
supply voltage:
■ Wide operating frequency: 1kHz to >1.5GHz
• <975psin-to-outtpd
• <180pstr/tf
• <40psoutput-to-outputskew
■ Unique input isolation design minimizes crosstalk
■ Ultra-lowjitterdesign:
• <1psrmsrandomjitter
• <1psrmscycle-to-cyclejitter
• <10pspptotaljitter(clock)
• <0.7psrmsMUXcrosstalkinducedjitter
■ UniqueinputterminationandVTpinacceptsDC-or
AC-coupledinputs(CML,PECL,LVDS)
■ 800mVLVPECLoutputswing
■ Powersupply+2.5V±5%or+3.3V±10%
■ –40°Cto+85°Cindustrialtemperaturerange
■ Availablein32-pin(5mmx5mm)MLF® package
FEATURES
PRECISION1:8LVPECLFANOUT
BUFFERWITH2:1RUNTPULSE
ELIMINATOR INPUT MUX
Precision Edge®
SY89837U
APPLICATIONS
■ Redundant clock distribution
■ Fail-safeclockprotection
Rev.: F Amendment: /0
Issue Date: June 2010
The SY89837U is a low jitter, low skew, high-speed 1:8
fanout buffer with a unique, 2:1 differential input multiplexer
(MUX) optimized for clock redundant switchover applications.
Unlike standard multiplexers, the SY89837U unique 2:1 runt
pulse eliminator (RPE) input MUX prevents any short cycles
or “runt” pulses during switchover. In addition, a unique
fail-safe input protection prevents metastable conditions
when the selected input clock fails to a static DC differential
voltage (differential input voltage drops below 200mV).
The SY89837U distributes clock frequencies from 1kHz to
1.5GHz, guaranteed, over temperature and voltage.
The differential input includes Micrel’s unique, 3-pin input
termination architecture that allows customers to interface
to any differential signal (AC- or DC-coupled) as small as
200mV without any level shifting or termination resistor
networks in the signal path. The outputs are 800mV, 100k
compatible LVPECL with fast rise/fall times guaranteed to
be less than 200ps.
The SY89837U operates from a +2.5V ±5% or +3.3V ±10%
supply and is guaranteed over the full industrial temperature
range of –40°C to +85°C. The SY89837U is part of Micrel’s
high-speed, Precision Edge® product line.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
Precision Edge®
2
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
TYPICAL APPLICATIONS CIRCUIT
Figure1. SimpliedExampleIllustratingRuntPulseEliminator(RPE)
CircuitWhenPrimaryClockFails
Inputs Outputs
IN0 /IN0 IN1 /IN1 SEL Q /Q
0 1 X X 0 0 1
1 0 X X 0 1 0
X X 0 1 1 0 1
X X 1 0 1 1 0
TRUTH TABLE
3
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERINGINFORMATION
PinNumber PinName PinFunction
1, 3, IN0, /IN0, Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs
6, 8 IN1, /IN1 accept AC- or DC-coupled signals as small as 200mV. Each pin of a pair internally terminates to
aVTpinthrough50Ω.Pleaserefertothe“InputInterfaceApplications”sectionformoredetails.
2, 7 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The
VT0andVT1pinsprovideacenter-taptoaterminationnetworkformaximuminterfaceexibility.
See the “Input Interface Applications” section for more details.
31 SEL This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. This input
isinternallyconnectedtoa25kΩpull-upresistorandwilldefaulttoalogicHIGHstateifleftopen.
9,19,22,32 VCC Positivepowersupply.Bypasswith0.1µF0.01µFlowESRcapacitorsasclosetothepinsas
possible.
30, 28, 26, 24, Q0 – Q7, Differential Outputs: These LVPECL output pairs are the outputs of the device. They are a logic
18, 16, 14, 12, /Q0 – /Q7 function of the IN0, IN1, and SEL inputs. Please refer to the truth table for details. Unused
29, 27, 25, 23, output pairs may be left open.
17, 15, 13, 11
20,21 GND, Ground. Ground and exposed pad to be tied together to most negative potential of chip.
Exposed Pad
10 CAP Power-On Reset (POR) Initialization Capacitor. When using the multiplexer with RPE capability,
this pin is tied to a capacitor to VCC. The purpose is to ensure the internal RPE logic starts up in
a known state. If this pin is tied to VCC, the RPE function will be disabled and the multiplexer will
function as a normal multiplexer. See “Application” section for more details. The CAP pin should
never be left open.
4,5 VREF-AC0 Reference Voltage: These outputs bias to V - 1.2V. They are used for AC-coupling inputs
VREF-AC1 (IN,/IN). Connect VREF_AC directly to the VT pin. Bypass with 0.01µF low ESR capacitor to
VCC. See "Input Interface Applications" section. Maximum sink/source current is ±1.5mA.
PIN DESCRIPTION
32-PinMLF®(MLF-32)
Ordering Information(1)
Package Operating Package Lead
PartNumber Type Range Marking Finish
SY89837UMI MLF-32 Industrial SY89837U Sn-Pb
SY89837UMITR(2) MLF-32 Industrial SY89837U Sn-Pb
SY89837UMG(3) MLF-32 Industrial SY89837U with Pb-Free
Pb-Free bar-line indicator NiduAu
SY89837UMGTR(2, 3) MLF-32 Industrial SY89837U with Pb-Free
Pb-Free bar-line indicator NiduAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
CC
4
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
DETAILEDFUNCTIONALDESCRIPTION
RPEMUXandFail-SafeInput
The SY89837U is optimized for clock switchover
applications where switching from one clock to another clock
without runt pulses (short cycles) is required. It features two
unique circuits:
1. Runt-Pulse Eliminator (RPE) Circuit
The RPE MUX provides a “glitchless” switchover between
two clocks and prevents any runt pulses from occurring
during the switchover transition. The design of both clock
inputs is identical (i.e., the switchover sequence and
protection is symmetrical for both input pair, IN0 or IN1. Thus,
eitherinputpairmaybedenedastheprimaryinput).Ifnot
required, the RPE function can be permanently disabled to
allow the switchover between inputs to occur immediately.
For more detail on how to disable the RPE function within the
MUX, see the “Power-On Reset (POR)” section.
2. Fail-Safe Input (FSI) Circuit
The FSI function provides protection against a selected
input pair that drops below the minimum amplitude
requirement.Iftheselectedinputpairdropssufcientlybelow
the 200mV minimum single-ended input amplitude limit (VIN),
or 400mV differentially (Vdiff_IN), the output will latch to the
last valid clock state.
RPEandFSIFunctionality
The basic operation of the RPE MUX and FSI functionality
is described with the following four case descriptions. All
descriptions are related to the true inputs and outputs. The
primary (or selected) clock is called CLK1, the secondary
(or alternate) clock is called CLK2. Due to the totally
asynchronous relation of the IN and SEL signals and an
additional internal protection against metastability, the
number of pulses required for the operations described in
cases 1 through 4 can vary within certain limits. Refer to
“Timing Diagrams” and “Applications” section for detailed
information.
Case #1 Two Normal Clocks and RPE Enabled.
In this case the frequency difference between the two
running clocks IN0 and IN1 must not be greater than 1.5:1.
For example, if the IN0 clock is 500MHz, the IN1 clock must
be within the range of 334MHz to 750MHz.
If the SEL input changes state to select the alternate
clock, the switchover from CLK1 to CLK2 will occur in three
stages:
• Stage 1: The output will continue to follow CLK1
for a limited number of pulses.
• Stage 2: The output will remain LOW for a lim-
ited number of pulses of CLK2.
• Stage 3: The output follows CLK2.
Figure2. TimingDiagram1
5
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
Case #2 Input Clock Failure: Switching from a selected clock
stuck HIGH to a valid clock (RPE enabled).
If CLK1 fails HIGH before the RPE MUX selects CLK2
(using the SEL pin), the switchover will occur in three
stages:
• Stage 1: The output will remain HIGH for a limited
number of pulses of CLK2.
• Stage 2: The output will switch to LOW and then
remain LOW for a limited number of falling edges
of CLK2.
• Stage 3: The output will follow CLK2.
Case #3 Input Clock Failure: Switching from a selected clock
stuck LOW to a valid clock (RPE enabled).
If CLK1 fails LOW before the RPE MUX selects CLK2
(using the SEL pin), the switchover will occur in two stages.
• Stage 1: The output will remain LOW for a lim-
ited number of falling edges of CLK2.
• Stage 2: The output will follow CLK2.
Figure3. TimingDiagram2(1)
Note:
1. Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2
period.
Figure4. TimingDiagram3
6
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
Case #4 Input Clock Failure: Switching from the selected
clock input stuck in an undetermined state to a valid clock
input (RPE enabled).
If CLK1 fails to an undetermined state (e.g., amplitude falls
below the 200mV (VIN) minimum single-ended input limit,
or 400mV differentially) before the RPE MUX selects CLK2
(using the SEL pin), the switchover to the valid clock CLK2
will occur either following Case #2 or Case #3, depending
upon the last valid state at the CLK1.
If the selected input clock fails to a oating, static, or
extremely low signal swing, including 0mV, the FSI function
will eliminate any metastable condition and guarantee a
stable output signal. No ringing and no undetermined state
will occur at the output under these conditions.
Please note that the FSI function will not prevent
duty cycle distortions or runt pulses in case of a slowly
deteriorating (but still toggling) input signal. Due to the FSI
function, the propagation delay will depend upon rise and
fall time of the input signal and on its amplitude. Refer to
“Operation Characteristics” for detailed information.
POWER-ONRESET(POR)DESCRIPTION
The SY89837U includes an internal power-on reset (POR)
function to ensure the RPE logic starts-up in a known logic
state once the power-supply voltage is stable. An external
capacitor connected between VCC and the CAP pin (pin 10)
controls the delay for the power-on reset function.
Calculation of the required capacitor value is based on
the time the system power supply needs to power up to a
minimum of 2.3V. The time constant for the internal power-
on-reset must be greater than the time required for the power
supply to ramp up to a minimum of 2.3V.
The following term describes this relationship:
C (µF ) >tdPS(ms)
12(ms/µF)
As an example, if the time required for the system power
supply to power up past 2.3V is 12ms, the required capacitor
value on pin 10 would:
C (µF ) >12ms
12(ms/µF)
C>1µF
Figure5. TimingDiagram4
7
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
AbsoluteMaximumRatings(1)
Supply Voltage (VCC) ....................................–0.5V to +4.0V
Input Volage (VIN) ............................................–0.5V to VCC
LVPECL Output Current (IOUT)
Continuous ............................................................................. 50mA
Surge ......................................................................................100mA
Termination Current(3)
Source or sink current on VT ...................................... ±100mA
Lead Temperature (soldering, 20 sec.) ...................... 260°C
Storage Temperature (TS) ........................ –65°C to +150°C
Operating Ratings(2)
Supply Voltage (VCC) ........................... +2.375V to +2.625V
............................................................. +3.0V to +3.6V
Ambient Temperature (TA) .......................... –40°C to +85°C
Package Thermal Resistance(4)
MLF® (θJA)
Stll-Air .............................................................................. 35°C/W
MLF®(ΨJB)
Junction-to-board ........................................................ 16°C/W
TA = –40°C to +85°C; unless noted.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply 2.5V nominal 2.375 2.625 V
3.3V nominal 3.0 3.6 V
ICC Power Supply Current No load, max. VCC 115 160 mA
RIN Input Resistance (IN-to-VT) 45 50 55 Ω
RDIFF_IN DifferentialInputResistance 90 100 110 Ω
(IN-to-/IN)
VIH Input High Voltage (IN-to-/IN) 1.2 VCC V
VIL Input Low Voltage (IN-to-/IN) 0 VIH–0.2 V
VIN Input Voltage Swing (IN-to-/IN) See Figure 1a.(6) 0.2 VCC V
VDIFF_IN Differential Input Voltage Swing See Figure 1b. 0.4 V
|IN–/IN|
VIN_LOS Input Voltage Swing when signal 100 200 mV
is lost
VT_IN IN-to-VT (IN-to-/IN) 1.8 V
VREF_AC Output Reference Voltage VCC–1.3 VCC–1.2 VCC–1.1 V
(VREF-AC)
Notes:
1. Permanent device damage may occur if ratings in the “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and functional
operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. yJB uses a 4-layer
qJA in still air unless otherwise stated.
5. ThecircuitisdesignedtomeettheDCspecicationsshownintheabovetableafterthermalequilibriumhasbeenestablished.
6. VIN(max.)isspeciedwhenVTisoating.
DC ELECTRICAL CHARACTERISTICS(5)
8
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
VCC = +2.5V ±5% or +3.3V ±10%; RL=50ΩtoVCC–2V; TA = –40°C to +85°C, unless noted.
Symbol Parameter Condition Min Typ Max Units
VOH Output HIGH Voltage VCC–1.145 VCC–0.895 V
Q, /Q
VOL Output LOW Voltage VCC–1.945 VCC–1.695 V
Q, /Q
VOUT Output Voltage Swing See Figure 1a. 500 800 mV
Q, /Q
VDIFF_OUT Differential Output Voltage Swing See Figure 1b. 1100 1600 mV
Q, /Q
LVPECL OUTPUTS DC ELECTRICAL CHARACTERISTICS(7)
VCC = +2.5V ±5% or +3.3V ±10%; RL=50ΩtoVCC–2V; TA = –40°C to +85°C, unless noted.
Symbol Parameter Condition Min Typ Max Units
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
IIH Input HIGH Current –125 30 µA
IIL Input LOW Current –300 µA
Notes:
7. ThecircuitisdesignedtomeettheDCspecicationsshownintheabovetableafterthermalequilibriumhasbeenestablished.
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(7)
9
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
VCC = +2.5V ±5% or +3.3V ±10%; TA = –40°C to +85°C; unless noted.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Operating Frequency RPE enabled 1.5 2.0 GHz
tpd Differential Propagation Delay
IN-to-Q tr, tf (IN) = 300ps (20% to 80%), Note 9 525 700 975 ps
SEL-to-Q RPE enabled, see Timing Diagram. 17 cycles
SEL-to-Q RPE disabled (VIN = VCC/2) 1000 ps
tpd tempco Differential Propagation Delay 115 fs/°C
TemperatureCoefcient
tSKEW Output-to-output Skew Note10 20 40 ps
Part-to-part Skew Note 11 200 ps
tJITTER Clock Random Jitter (RJ) Note 12 1 psRMS
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Propagation delay is a function of rise and fall time at IN. See “Operation Characteristics” for more details.
10. Output-to-output skew is measured between two different outputs under identical transitions.
11.Part-to-partskewisdenedfortwopartswithidenticalpowersupplyvoltagesatthesametemperatureandwithnoskewoftheedgesatthe
respective inputs.
12. Random jitter is measured with a K28.7 character pattern, measured at <fMAX.
13. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the
inputs.
AC ELECTRICAL CHARACTERISTICS(8)
SINGLE-ENDEDANDDIFFERENTIALSWINGS
Figure1a. SimpliedDifferentialInputSwing Figure1b. SimpliedLVPECLOutputSwing
Crosstalk-Induced Jitter Note 13 0.7 psRMS
t , t
rfOutput Rise/Fall Time (20% to 80%) At full output swing. 70 120 180 ps
10
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
0
100
200
300
400
500
600
700
800
900
1000
0 100 200 300 400 500 600
INPUT RISE/FALL TIME (ps)
Propagation Delay Variation
vs. Input Rise/Fall Time
tpd (min)
tpd (max)
VIN = 200mV PK
0
100
200
300
400
500
600
700
800
900
1000
0 100 200 300 400 500 600
INPUT RISE/FALL TIME (ps)
Propagation Delay Variation
vs. Input Rise/Fall Time
tpd (min)
tpd (max)
VIN = 400mV PK
0
100
200
300
400
500
600
700
800
900
1000
0 100 200 300 400 500 600
INPUT RISE/FALL TIME (ps)
Propagation Delay Variation
vs. Input Rise/Fall Time
tpd (min)
tpd (max)
VIN = 800mV PK
OPERATING CHARACTERISTICS
400
450
500
550
600
650
700
750
800
0 500 1000 1500 2000 2500 3000
FREQUENCY (MHz)
Output Swing
vs. Frequency
11
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
OPERATINGCHARACTERISTICS(CONTINUED)
12
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
INPUT AND OUTPUT STAGES
INPUTINTERFACEAPPLICATIONS
Figure2a. SimpliedDifferentialInputStage Figure2b. SimpliedLVPECLOutputStage
Figure3a. LVPECLInterface
(DC-Coupled)
Option: may connect VT to VCC.
Figure3c. CMLInterface
(DC-Coupled)
Figure3d. CMLInterface Figure3e. LVDSInterface
Figure3b.LVPECLInterface
(AC-Coupled)
(AC-Coupled)
13
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
LVPECLOUTPUTINTERFACEAPPLICATIONS
PartNumber Function DataSheetLink
MLF® Application Note www.amkor.com/product/notes_papers/MLFAppNote.pdf
HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Figure4b. ParallelTermination(3-Resistors)
Figure4a. ParallelThevenin-EquivalentTermination
14
Precision Edge®
SY89837U
Micrel, Inc.
M9999-060410
hbwhelp@micrel.com or (408) 955-1690
MICREL,INC. 2180FORTUNEDRIVE SANJOSE,CA 95131 USA
tel + 1 (408) 944-0800 fa x + 1 (408) 474-1000 w e b http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrelreservestherighttochangecircuitryandspecicationsatanytimewithoutnoticationtothecustomer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
thebodyor(b)supportorsustainlife,andwhosefailuretoperformcanbereasonablyexpectedtoresultinasignicantinjurytotheuser.APurchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
32-PINMicroLeadFrame®(MLF-32)
PCB Thermal Consideration for 32-Pin MLF® Package
Package Notes:
1. PackagemeetsLevel2MoistureSensitivityClassication.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.