TPS7A6333-Q1
or
TPS7A6350-Q1
VIN
COUT
EN nWD_EN WD
VOUT
nRST
VIN
RDELAY
ROSC
GND
CIN
CDLY
ROSC
RRST
VOUT
WD_FLT/
WD_FLG
RFLT/FLAG
RESET
FAULT/
FLAG
TPS7A6x01-Q1
VIN
COUT
EN WD
VOUT
nRST
VIN
RDELAY
ROSC
GND
CIN
CDLY
ROSC
RRST
R1
FB
R2
VOUT
WD_FLT/
WD_FLG
RESET
FAULT/
FLAG
nWD_EN
RFLT/FLAG
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
300-mA 40-V LOW-DROPOUT REGULATOR WITH ULTRALOW Iq
Check for Samples: TPS7A6301-Q1,TPS7A6333-Q1,TPS7A6350-Q1,TPS7A6401-Q1
1FEATURES • Low Input-Voltage Tracking
• Thermally Enhanced 14-pin TSSOP - PWP
• Qualified for Automotive Applications Package and 10-pin VSON - DRK Package
• AEC-Q100 Test Guidance With the Following
Results: APPLICATIONS
– Device Temperature Grade 1: –40°C to • Infotainment Systems With Sleep Mode
125°C Ambient Operating Temperature • Body Control Modules
– Device HBM ESD Classification Level H2 • Always-On Battery Applications
– Device CDM ESD Classification Level C2 – Gateway Applications
• Low Dropout Voltage – Remote Keyless Entry Systems
– 300 mV at IOUT = 150 mA – Immobilizers
• 4-V to 40-V Wide Input-Voltage Range
With up to 45-V Transients DESCRIPTION
• 300-mA Maximum Output Current The TPS7A63xx-Q1 and TPS7A6401-Q1 are a family
• Ultralow Quiescent Current of low-dropout linear voltage regulators designed for
– IQUIESCENT = 35 µA (Typ.) at Light Loads low power consumption and quiescent current less
than 35 µA in light-load applications. These devices,
– ISLEEP < 2 µA When EN = Low designed to achieve stable operation even with a low-
• Fixed (3.3-V and 5-V) and Adjustable (2.5-V to ESR ceramic output capacitor, feature an integrated
7-V) Output Voltages programmable window watchdog and overcurrent
• Integrated Watchdog With Fault/Flag protection. Designers can program the output voltage
using external resistors. A low-voltage tracking
• Stable With Low-ESR Ceramic Output feature allows for a smaller input capacitor and can
Capacitor possibly eliminate the need of using a boost
• Integrated Power-On Reset converter during cold-crank conditions. The power-
– Programmable Delay on-reset delay is fixed (250 µs typical), or an external
capacitor can program the delay. Because of such
– Open-Drain Reset Output features, these devices are well-suited in power
• Integrated Fault Protection supplies for various automotive applications.
– Short-Circuit/Overcurrent Protection
– Thermal Shutdown
TYPICAL APPLICATION SCHEMATIC
Figure 1. Fixed Output Voltage Option Figure 2. Adjustable Output Voltage Option
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
DESCRIPTION VALUE UNIT
VIN, VEN Unregulated inputs(2)(3) 45 V
VOUT Regulated output 7 V
FB Sense voltage for error amplifier(2) 7 V
ROSC Constant-voltage reference(2) 7 V
nWD_EN, WD,
WD_FLAG, Watchdog inputs and outputs(2) 7 V
WD_FLT
nRST Open-drain reset output(2) 7 V
RDELAY Reset delay timer output(2) 7 V
Thermal impedance junction to exposed pad TSSOP-PWP package 4.1 °C/W
θJP Thermal impedance junction to exposed pad VSON-DRK package 5.2 °C/W
Thermal impedance junction to ambient TSSOP-PWP package(4) 51 °C/W
θJA Thermal impedance junction to ambient VSON-DRK package(4) 51.7 °C/W
ESD Electrostatic discharge(5) 2 kV
TAOperating ambient temperature 125 °C
Tstg Storage temperature range –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to GND.
(2) Absolute negative voltage on these pins not to go below –0.3 V.
(3) Absolute maximum voltage for duration less than 480 ms.
(4) The thermal data is based on JEDEC standard high-K profile – JESD 51-5. The copper pad is soldered to the thermal land pattern. Also,
the correct attachment procedure must be incorporated.
(5) The human body model is a 100-pF capacitor discharged through a 1.5-kΩresistor into each pin.
2Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
DISSIPATION RATINGS TA< 25°C POWER DERATING FACTOR ABOVE TA= 85°C POWER
JEDEC STANDARD PACKAGE RATING (W) TA= 25°C (°C/W) RATING (W)
JEDEC standard PCB, 14 pin 2.45 51 1.27
high-K, JESD 51-5 TSSOP-PWP
JEDEC Standard PCB 10 pin VSON-DRK 2.41 51.7 1.25
high-K, JESD 51-5
RECOMMENDED OPERATING CONDITIONS
DESCRIPTION MIN MAX UNIT
VIN, VEN Unregulated input voltage 4 40 V
nRST, RDELAY, nWD_EN, WD_FLT(1) ,Low voltage input or output 0 5.25 V
WD_FLAG(2), WD, FB(3)
TJOperating junction temperature range -40 150 °C
(1) Applicable for TPS7A63xx-Q1 only
(2) Applicable for TPS746401-Q1 only
(3) Applicable for TPS7A6301-Q1 and TPS7A6401-Q1 only
ELECTRICAL CHARACTERISTICS
VIN = 14 V, TJ= –40ºC to 150ºC (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Voltage (VIN Pin)
VOUT +
VIN Input voltage VOUT = 2.5 V to 7 V, IOUT = 1 mA 40 V
0.3 V
VIN = 8.2 V to 18 V, VEN = 5 V,
IQUIESCENT Quiescent current 35 µA
IOUT = 0.01 mA to 0.75 mA
VIN = 8.2 V to 18 V, VEN < 0.8 V,
ISLEEP Sleep or shutdown current 3 µA
IOUT = 0 mA (no load), TA= 125°C
Undervoltage lockout
VIN-UVLO Ramp VIN down until output is turned OFF 3.16 V
voltage
VIN(POWERUP) Power-up voltage Ramp VIN up until output is turned ON 3.45 V
Device Enable Input (EN Pin)
VIL Logic-input low level 0 0.8 V
VIH Logic-input high level 2.5 40 V
Regulated Output Voltage (VOUT Pin)
Fixed VOUT value (3.3 V, 5 V or a programmed value),
VOUT Regulated output voltage –2% 2%
IOUT = 10 mA to 200 mA, VIN = VOUT + 1 V to 16V
VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 5 V 15 mV
ΔVLINE-REG Line regulation VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 3.3 V 20 mV
IOUT = 10 mA to 200 mA, VIN= 14 V, VOUT = 5 V 25 mV
ΔVLOAD-REG Load regulation IOUT = 10 mA to 200 mA, VIN = 14 V, VOUT = 3.3 V 35 mV
IOUT = 200 mA 500 mV
Dropout voltage
VDROPOUT (VIN – VOUT)IOUT = 150 mA 300 mV
RSW(1) Switch resistance VIN to VOUT resistance 2 Ω
VOUT in regulation 0 200 mA
IOUT Output current [VOUT in regulation, VOUT = 3.3 V, VIN = 6 V](2) 0 300 mA
ICL Output current limit VOUT = 0 V (VOUT pin is shorted to ground) 350 1000 mA
(1) This test is done with VOUT in regulation, measuring the VIN – VOUT parameter when VOUT drops by 100 mV from the programmed value
(of VOUT) at specified loads.
(2) Design Information - not tested; specified by characterization.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VIN = 14 V, TJ= –40ºC to 150ºC (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN-RIPPLE = 0.5 Vpp, IOUT = 200 mA, frequency = 100 60
Hz, VOUT = 5 V and VOUT = 3.3 V
Power-supply ripple
PSRR(3) dB
rejection VIN-RIPPLE = 0.5 Vpp, IOUT = 200 mA, frequency = 150 30
kHz, VOUT = 5 V and VOUT = 3.3 V
Reset (nRST Pin)
VOL Reset pulled low IOL = 5 mA 0.4 V
IOH Leakage current Reset pulled to VOUT through a 5-kΩresistor 1 µA
VOUT powered up above internally set tolerance, 4.5 4.65 4.77
VOUT = 5 V
VTH(POR) Power-on-reset threshold V
VOUT powered up above internally set tolerance, 3.07
VOUT = 3.3 V
VOUT falling below internally set tolerance, 4.5 4.65 4.77
VOUT = 5 V
UVTHRES Reset threshold V
VOUT falling below internally set tolerance, 3.07
VOUT = 3.3 V
CDLY = 100 pF 300 µs
tPOR(2) Power-on-reset delay CDLY = 100 nF 300 ms
Internally preset
tPOR-PRESET CDLY not connected, VOUT = 5 V and VOUT = 3.3 V 250 µs
Power-on-reset delay
tDEGLITCH Reset deglitch time 5.5 µs
Reset Delay (RDELAY Pin)
Threshold to release nRST
VTH(RDELAY) Voltage at RDELAY pin is ramped up 3 3.3 V
high
Delay capacitor
IDLY 0.75 1 1.25 µA
charging current
Delay capacitor
IOL Voltage at RDELAY pin = 1 V 5 mA
discharging current
Current Voltage Reference (ROSC Pin)
VROSC Voltage reference 0.95 1 1.05 V
Watchdog Fault/ Flag Output ( WD_FLT/ WD_FLAG Pin)
VOL Logic output low level IOL= 5 mA 0.4 V
WD_FLT/WD_FLG pulled to VOUT through 5-kΩ
IOH Leakage current 1 µA
resistor
Watchdog Enable Input (nWD_EN Pin)
VIL Logic input low level 0.8 V
VIH Logic input high level 5.25 V < VDD < 3 V 2.5
Watchdog Input Pulse (WD Pin)
VIL Logic input low level 0.8 V
VIH Logic input high level 5.25 V < VDD < 3 V 2.5
ROSC = 10 kΩ± 1% 10
tWD Watchdog window duration ms
ROSC = 20kΩ± 1% 20
Tolerance of watchdog Excludes tolerance of ROSC
tWD-tol period using external –10% 10%
(external resistor connected to ROSC pin)
resistor External resistor not connected, ROSC pin is floating
tWD-DEFAULT Default watchdog period 108 164 254 ms
or open
Minimum pulse width for
tWD-HOLD 1.65 µs
resetting watch dog timer
(3) Specified by design - not tested.
4Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
ELECTRICAL CHARACTERISTICS (continued)
VIN = 14 V, TJ= –40ºC to 150ºC (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Operating Temperature Range
Operating junction
TJ–40 150 ºC
temperature
Thermal shutdown trip
TSHUTDOWN 165 ºC
point
Thermal shutdown
THYST 10 ºC
hysteresis
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
1
2
3
4 11
12
13
14
5
6
7
10
9
8
VOUT
RDELAY
VIN
NC
WD_FLT/FLAG
WD
NC
nWD_EN
NC
ROSC
nRST
FB
GND
EN
VOUT
GND
EN
nRST
VIN
WD_FLT
WD
RDELAY
nWD_EN
ROSC
1
2
3
4
5
10
9
8
7
6
1
2
3
4 11
12
13
14
5
6
7
10
9
8
VOUT
RDELAY
VIN
NC
WD_FLT/FLAG
WD
NC
nWD_EN
NC
ROSC
nRST
NC
GND
EN
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
DEVICE INFORMATION
TSSOP PWP PACKAGE (TOP VIEW) VSON DRK PACKAGE (TOP VIEW)
Fixed Output Voltage Option Fixed Output Voltage Option
TSSOP PWP PACKAGE (TOP VIEW)
Adjustable Output Voltage Option
PIN FUNCTIONS
PIN NO. PIN NAME TYPE DESCRIPTION
PWP DRK
Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor connected between
1 1 VIN I the VIN pin and GND pin dampens line transients on the input.
2 2 nRST O Reset pin: This is an open-drain reset output pin with an external pullup resistor connected to the VOUT pin.
FB I Feedback pin (only applicable for TPS7A6x01-Q1): Sense voltage for error amplifier
3 – NC – Not connected (only applicable for TPS7A6333-Q1/6350-Q1)
4 3 GND I/O Ground pin: This is signal ground pin of the IC.
Chip enable pin: This is a high-voltage-tolerant input pin with an internal pulldown. A high input to this pin
5 4 EN I activates the device and turns the regulator ON. Connect this input to the VIN terminal for self-bias applications.
If this pin remains unconnected, the device stays disabled.
6 8 RDELAY O Reset delay timer pin: This pin programs the reset delay timer using an external capacitor (CDLY) to ground.
Regulated output voltage pin: This is a regulated voltage output (VOUT = 3.3 V or 5 V or a programmed value) pin
with a limitation on maximum output current. For devices with adjustable output voltage (TPS7A6x01-Q1),
7 5 VOUT O connecting an external resistor network programs the output voltage. In order to achieve stable operation and
prevent oscillation, connect an external output capacitor (COUT) with low ESR between this pin and GND pin.
8 – NC – Not connected
Watchdog fault pin (for TPS7A63xx-Q1 only): This is an active-low fault output pin with an external pullup
WD_FLT O resistor connected to the VOUT pin.
9 6 Watchdog flag pin (for TPS746401-Q1 only): This is an active-high latched fault (that is, flag) output pin with an
WD_FLAG O external pullup resistor connected to VOUT pin.
10 7 WD I Watchdog service pin: This is an input pin to provide a service signal to the watchdog.
11 – NC – Not connected
Watchdog enable pin: A high input to this pin disables the watchdog, and vice versa. This is an active-low input
12 9 nWD_EN I pin with an internal pulldown. Leaving this pin is unconnected and floating keeps the watchdog enabled. An
external microcontroller can pull this pin high momentarily to disable and reinitialize the watchdog.
13 – NC – Not connected
ROscillator pin: This pin programs the internal oscillator frequency (and hence the duration of the watchdog
14 10 ROSC O window) by connecting an external resistor to ground.
6Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
Q1
Oscillator
UVLO Comp.
with internal
reference
Voltage
Supervisor with
Reset Delay
Charge Pump
Logic
Control
Band Gap Temp. Sensor/
Thermal Shutdown
Over Current
Detection
VRef1
Error
Amp.
Regulator
Control
Q2
VIN
VOUT
CIN
COUT
CDLY
RRST
RDELAY
VIN
VOUT
GND
nRST
RESET
VRef1
Q3
WD_FLT
FAULT
Watchdog
Oscillator
Current
Regulator
EN
Timer
Watchdog
Fault Control
RFLT
ROSC
ROSC
R1
R2
FB
WDnWD_EN
Q1
Oscillator
UVLO Comp.
with internal
reference
Voltage
Supervisor with
Reset Delay
Charge Pump
Logic
Control
Band Gap Temp. Sensor/
Thermal Shutdown
Over
Current
Detection
VRef1
Error
Amp.
Regulator
Control
Q2
VIN
VOUT
CIN
COUT
CDLY
RRST
RDELAY
VIN
VOUT
nRST
RESET
VRef1
Q3
WD_FLT
FAULT
Watchdog
Oscillator
Current
Regulator
EN
Timer
Watchdog
Fault Control
RFLT
ROSC
ROSC
GND
WDnWD_EN
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
FUNCTIONAL BLOCK DIAGRAMS
Figure 3. TPS7A6333-Q1 and TPS7A6350-Q1 (Fixed Output Voltage With FAULT Output)
Figure 4. TPS7A6301 (Adjustable Output Voltage With FAULT Output)
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
Q1
Oscillator
UVLO Comp.
with internal
reference
Voltage
Supervisor with
Reset Delay
Charge Pump
Logic
Control
Band Gap Temp. Sensor/
Thermal Shutdown
Over Current
Detection
VRef1
Error
Amp.
Regulator
Control
Q2
VIN
VOUT
CIN
COUT
CDLY
RRST
RDELAY
VIN
VOUT
GND
nRST
RESET
VRef1
Q3
WD_FLAG
FLAG
Watchdog
Oscillator
Current
Regulator
EN
Timer
Watchdog
Fault Control
RFLAG
ROSC
ROSC
R1
R2
FB
WDnWD_EN
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
Figure 5. TPS7A6401-Q1 (Adjustable Output Voltage With FLAG Output)
8Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 50 100 150 200
IOUT (mA)
VDROP OUT (V)
TA= 25°C
VOUT = 5V
TA= 125°C
TA= -40°C
0
100
200
300
400
500
600
700
4 14 24 34
VIN (V)
VOUT = 5V, 3.3V
T
A= 25°C
IOUT = 100mA
No Load
I (µA)
QUIESCENT
40
15
20
25
30
35
40
45
50
55
-50 0 50 100 150
TA(°C)
I (µA)
QUIESCENT
VIN =14V
VOUT= 5V, 3.3V
I = 1mA
OUT
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
TYPICAL CHARACTERISTICS
Graphs shown in the Typical Characteristics section for unreleased devices are for preview only.
Figure 6. Quiescent Current versus Load Current Figure 7. Quiescent Current versus Ambient Air
Temperature
Figure 8. Quiescent Current versus Input Voltage Figure 9. Dropout Voltage versus Load Current (1)
(1) Measure dropout voltage when the output voltage drops by 100 mV from the regulated output-voltage level. (For example, for an output
voltage programmed to be 5 V, measure the dropout voltage when the output voltage drops down to 4.9 V from 5 V.)
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
0
0.5
1
1.5
2
2.5
3
-50 0 50 100 150
TA(°C)
IOUT = 10mA
VOUT = 5V, 3.3V
VIN step from
8V to 28V
Line Regulation (mV)
450
500
550
600
650
700
750
-50 0 50 100 150
TA(°C)
ICL (mA)
V = 14V
V = 5V, 3.3V
IN
OUT
0
0.02
0.04
0.06
0.08
0.1
0.12
0 10 20 30 40 50
V (V)
IN
IOUT (A)
ILOAD = 100mA
VOUT = 5V, 3.3V
T
A= 25°C
T
A= -40°C
T
A= 125°C
4.9
4.92
4.94
4.96
4.98
5
5.02
5.04
5.06
5.08
5.1
-50 0 50 100 150
TA(°C)
VOUT (V)
VIN = 14V
IOUT = 1mA
0
5
6
2 3 4 5 6 7
VIN (V)
1
2
3
4
VOUT (V)
IOUT = 100mA
T
A= 25°C
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 10. Output Voltage versus Ambient Air Temperature Figure 11. Output Voltage versus Input Voltage
(VOUT Set to 5 V) (VOUT Set to 5 V)
Figure 12. Output Voltage versus Input Voltage Figure 13. Output Current Limit versus Ambient Air
Temperature
Figure 14. Load Regulation versus Ambient Air Figure 15. Line Regulation versus Ambient Air Temperature
Temperature
10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
0
20
40
60
80
100
120
Frequency (Hz)
PSRR (dB)
VIN = 14V
IOUT = 1mA
T
A= 25°C
C
OUT = 10µF
VOUT = 5V, 3.3V
10 100 1k 10k 100k 1M
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M
Frequency (Hz)
PSRR (dB)
VIN = 14V
IOUT = 200mA
T
A= 25°C
C
OUT = 10µF
VOUT = 5V, 3.3V
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
TYPICAL CHARACTERISTICS (continued)
Figure 16. PSRR at Heavy Load Current Figure 17. PSRR at Light Load Current
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
VIN(POWERUP)
VIN
VOUT
0
0
V = 93% of VTH(POR) OUT
VTH(RDELAY)
VRDELAY
VnRST
tPOR
0
0
VIN
VOUT
0
0
VTH(POR)
VnRST
0
0
t < tDEGLITCH
UVTHRES
tDEGLITCH
t>tDEGLITCH
tPOR
VTH(RDELAY)
VRDELAY
POR 6
CDLY 3
t
1 10-
´
=
´
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
DETAILED DESCRIPTION
TPS7A63xx-Q1/6401-Q1 is a family of monolithic low- When starting up, and also when the output recovers
dropout linear voltage regulators with integrated from a negative voltage spike due to a load step or a
watchdog and reset functionality. These voltage dip in the input voltage for a specified duration, the
regulators are designed for low power consumption device implements reset delay to indicate that output
and quiescent current less than 25 µA in light-load voltage is stable and in regulation.
applications. Because of an programmable reset When the output voltage reaches the power-on-reset
delay (also called power-on-reset delay), these threshold (VTH(POR)) level, that is, 93% of regulated
devices are well-suited in power supplies for output voltage (3.3 V or 5 V, or a programmed value),
microprocessors and microcontrollers. a constant output current charges an external
These devices are available in two fixed and capacitor (CDLY) to an internal threshold (VTH(RDELAY))
adjustable output-voltage versions as follows: voltage level. Then, nRST asserts high and CDLY
discharges through an internal load. This allows CDLY
• Fault (WD_FLT) output version: TPS7A63xx-Q1 to charge from approximately 0 V during the next
• Flag (WD_FLAG) output version: TPS7A6401-Q1 power cycle.
The following section describes the features of Program the reset delay time by connecting an
TPS7A63xx-Q1/6401-Q1 voltage regulators in detail. external capacitor (CDLY ,100 pF to 100 nF) to the
RDELAY pin. Equation 1 gives the delay time:
Power Up, Reset Delay, and Reset Output
(1)
During power up, the regulator incorporates a
protection scheme to limit the current through the where,
pass element and output capacitor. When the input tPOR = reset delay time in seconds
voltage exceeds a certain threshold (VIN(POWERUP))CDLY = reset delay capacitor value in farads
level, the output voltage begins to ramp up as shown
in Figure 18.
Figure 18. Power Up and Conditions for Activation Figure 19. Reset Delay and Deglitch Filter
of Reset
12 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
ON
OFF
Charge Pump State
9.2 9.6
Hysteresis
V (V)
IN
OUT REF
V V R1 R2
R1
tol = tol + tol + tol
R1 + R2
é ù é ù
ë û
ê ú
ë û
ON
OFF
Charge Pump State
7.8 7.9
Hysteresis
V (V)
IN
OUT REF
R1
V = V 1 +
R2
é ù
ê ú
ë û
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
As Figure 19 shows, if the regulated output voltage Charge-Pump Operation
falls below 93% of the set level, nRST asserts low These devices have an internal charge pump which
after a short de-glitch time of approximately 5.5 µs turns on or off depending on the input voltage and the
(typical). In case of negative transients in the input output current. The charge pump switching circuitry
voltage (VIN), the reset signal asserts low only if the must not cause conducted emissions to exceed
output (VOUT) drops and stays below the reset required thresholds on the input voltage line. For a
threshold level (VTH(POR)) for more than the deglitch given output current, the charge pump stays on at
time (tDEGLITCH), as Figure 19 and Figure 22 illustrate. lower input voltages and turns off at higher input
While nRST is low, if the input voltage returns to the voltages. The charge-pump switching thresholds are
nominal operating voltage, the normal power-up hysteretic. Figure 20 and Figure 21 show typical
sequence ensues. nRST asserts high only if the switching thresholds for the charge pump at light (IOUT
output voltage exceeds the reset threshold voltage < ~2 mA) and heavy (IOUT > ~2 mA) loads,
(VTH(POR)) and the reset delay time (tPOR) has respectively.
elapsed.
Adjustable Output Voltage
Program the regulated output voltage (VOUT) by
connecting external resistors to FB pin. Calculate the
feedback resistor values using Equation 2.
(2)
where,
VOUT= desired output voltage
VREF = reference voltage (VREF= 1.23 V, typically) Figure 20. Charge-Pump Operation at Light
R1, R2 = feedback resistors (see Figure 5)Loads
Equation 3 gives the overall tolerance of the
regulated output.
(3)
where,
tolVOUT = tolerance of the output voltage
tolVREF = tolerance of the internal reference
voltage (tolVREF = ± 1.5% typically)
tolR1,tolR2 = tolerance of feedback resistors R1,
R2
For a tighter tolerance on VOUT, select lower-value Figure 21. Charge-Pump Operation at Heavy
feedback resistors. TI recommends to select Loads
feedback resistors such that the sum of R1 and R2 is
between 20 kΩand 200 kΩ.
Low-Power Mode
Chip Enable At light loads and high input voltages (VIN >
These devices have a high-voltage-tolerant EN pin approximately 8 V, such that the charge pump is off),
that an external microcontroller or a digital control the device operates in low-power mode and the
circuit can use to enable and disable them. A high quiescent current consumption is reduced to 25 µA
input to this pin activates the device and turns the (typical) as shown in Table 1.
regulator on. For self bias applications, connect this
input to the VIN terminal . An internal pulldown Table 1. Typical Quiescent Current Consumption
resistor is connected to this pin, and therefore if this IOUT Charge Pump ON Charge Pump OFF
pin remains unconnected, the device stays disabled. IOUT <
approximately 2 35 µA
250 µA
mA (Low-power mode)
(Light load)
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
VIN-UVLO
VIN
VOUT
0
0
VRDELAY
VnRST
0
0
Tracking
UVTHRES
tDEGLITCH
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
Table 1. Typical Quiescent Current Integrated Fault Protection
Consumption (continued) These devices feature integrated fault protection to
IOUT Charge Pump ON Charge Pump OFF make them ideal for use in automotive applications.
In order to remain in a safe area of operation during
IOUT >
approximately 2 certain fault conditions, the devices use internal
280 µA 70 µA
mA current-limit protection and current-limit foldback to
(Heavy load) limit the maximum output current. This protects them
from excessive power dissipation. For example,
Undervoltage Shutdown during a short-circuit condition on the output, fault
protection limits the current through the pass element
These devices have an integrated undervoltage to ICL to protect the device from excessive power
lockout (UVLO) circuit to shut down the output if the dissipation.
input voltage (VIN) falls below an internally fixed
UVLO threshold level (VIN-UVLO). This ensures that the Thermal Shutdown
regulator does not latch into an unknown state during
low-input-voltage conditions. The regulator powers up These devices incorporate a thermal shutdown (TSD)
when the input voltage exceeds the VIN(POWERUP) circuit as a protection from overheating. For
level, as Figure 22 shows. continuous normal operation, the junction
temperature should not exceed the TSD trip point.
Low-Voltage Tracking The junction temperature exceeding the TSD trip
point causes the output to turn off. When the junction
At low input voltages, the regulator drops out of temperature falls below TSD trip point, the output
regulation, and the output voltage tracks the input turns on again, as Figure 23 shows.
minus a voltage based on the load current (IOUT) and
switch resistance (RSW), as Figure 22 shows. This
feature allows for a smaller input capacitor and can
possibly eliminate the need of using a boost
convertor during cold crank conditions, as Figure 22
shows.
Figure 22. Low-Voltage Tracking and Undervoltage Figure 23. Thermal Cycling Waveform for
Lockout TPS7A6350-Q1 (VIN= 24 V, IOUT= 200 mA, VOUT= 5 V)
14 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
8 x tWD
OPEN
WINDOW
(must be serviced to
prevent fault)
t =½ tOW WD
t =½ tCW WD
t 5000 tWD = x WD_OUT
CLOSED
WINDOW
(must not be serviced
to prevent fault)
OPEN WINDOW
After watchdog initialization
(must be serviced to prevent fault)
Event causing
watchdog initialization
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
INTEGRATED WINDOW WATCHDOG Watchdog Enable
These devices have an integrated watchdog with fault An external microcontroller or a digital circuit can
(WD_FLT) and flag (WD_FLAG) output options. Both apply an appropriate signal to the nWD_EN pin to
device options are available in fixed- and adjustable- enable or disable the watchdog. A low input to this
output versions. The watchdog operation, service pin turns the watchdog on. Because of an internal
fault conditions, and difference between fault pulldown resistor connected to this pin, leaving the
(TPS7A63xx-Q1) and flag (TPS746401-Q1) output pin unconnected keeps the watchdog enabled.
versions are described as follows. Watchdog Service Signal
Programmable-Window Watchdog In order for the watchdog service signal (WD) to
Program the duration of the watchdog window by service an open window correctly, the service signal
connecting an external resistor (ROSC) to ground at must stay high for a duration of at least tWD_HOLD. The
the ROSC pin. The current through the resistor sets recommended value of tWD_HOLD is given by
the clock frequency of the internal oscillator. The user Equation 7:
can adjust the duration of the watchdog window (that tWD_HOLD = 3 × tWD_OUT (7)
is, the watchdog timer period) by changing the
resistor value. The duration of the watchdog window Watchdog Fault Outputs
and the duration of the fault output are multiples of The WD_FLT pin and WD_FLAG pin are fault output
the internal oscillator frequency and are given by the terminals for the TPS7A63xx-Q1 and TPS7A6401-Q1
following equations: devices, respectively. Typically, one pulls these fault
tWD = 10–6 × ROSC = 5000 × 1 / fOSC (4) outputs high to a regulated output supply. In the case
tWD_OUT = 1 / fOSC (5) of a watchdog fault condition, the TPS7A63xx-Q1
tCW = tOW = 1 / 2 tWD (6) momentarily pulls WD_FLT low for a duration of
tWD_OUT, whereas the TPS746401-Q1 latches the
where, WD_FLAG high and momentarily pulls nRST low for
tWD = width of watchdog window a duration of tWD_OUT.
ROSC = resistor connected at ROSC pin
tWD_OUT = duration of fault output Watchdog Initialization
fOSC = frequency of internal oscillator On power up and during normal operation, the
tCW = duration of closed window watchdog initializes under the conditions shown in
tOW = duration of open window Table 2. The normal operation of the watchdog for
the WD_FLT and WD_FLAG output device options is
As shown in Figure 24, each watchdog window shown in Figure 25 and Figure 26, respectively.
consists of an open window and a closed window,
each having a width approximately 50% of the Table 2. Conditions for Watchdog Initialization
watchdog window. However, there is an exception to TPS7A63xx TPS746401
this; the first open window after watchdog initialization What causes watchdog -Q1 -Q1
is eight times the duration of the watchdog window. Edge to initialize? (FAULT (FLAG
All open windows except the one after watchdog Option) Option)
initialization are one-half the width of the watchdog Rising edge of nRST
window. On initialization, the watchdog must receive (when VOUT exceeds
service (by software, external microcontroller, and so VTH(POR)) while the ✓ ✓
forth) only during an open window. A watchdog watchdog is in the enabled
state, for example, during
serviced during a closed window, or not serviced soft power up
during a open window, creates a watchdog fault Falling edge of nWD_EN
condition. while the nRST is already
high, for example, when ✓ ✓
the microprocessor
enables the watchdog after
the device is powered up
Rising edge of WD_FLT
while the nRST is already
high and the watchdog is in ✓X
the enabled state, for
example, right after a
Figure 24. Watchdog Window Duration closed window is serviced
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
0
0
VOUT
0
0
nRST
nWD EN_
tPOR
93% of VOUT
0
NA OW
WD Initialization CW OW
<½ tWD½ tWD
<8 tWD
WD
WD FL_ T
CW
tWD HOLD_
WD
Window
Status
0
0
0
VOUT
0
0
nRST
nWD EN_
tPOR
93% of VOUT
0
NA OW
WD Initialization CW OW
<½ tWD½ tWD
<8 tWD
WD
WD FLAG_
CW
tWD HOLD_
WD
Window
Status
0
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
Watchdog Operation
Figure 25. Power Up, Initialization, and Normal Figure 26. Power Up, Initialization, and Normal
Operation for TPS7A63xx-Q1 Operation for TPS7A6401-Q1
Figure 25 shows watchdog initialization and operation Figure 26 shows watchdog initialization and operation
for the TPS7A63xx-Q1. After output voltage is in for FLAG output version (TPS7A6401-Q1). The fault
regulation and reset asserts high (clearly the chip- output (WD_FLAG), externally pulled up to VOUT
enable pin is high), the watchdog becomes enabled (typically), stays low as long as the watchdog
when an external signal pulls nWD_EN (the watchdog receives proper service and there is no fault
enable pin) low. This causes the watchdog to initialize condition.
and wait for a service signal during the first open
window for 8× the duration of tWD. A service signal Likewise, enabling the watchdog before powering the
applied to the WD pin during the first open window device on (that is, pulling the nWD_EN pin low before
resets the watchdog counter and a closed window power up), the watchdog initializes as soon as the
starts. To prevent a fault condition from occurring, output voltage is in regulation and reset asserts high
watchdog service must not occur during the closed (see Table 2 for Conditions for Watchdog
window. Watchdog service must occur during the Initialization).
following open window to prevent fault condition from
occurring. The fault output (WD_FLT), externally
pulled up to VOUT (typically), stays high as long as
the watchdog receives proper serviced and there is
no fault condition.
16 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
0
0
VOUT
0
0
nRST
nWD EN_
0
CW
<½ tWD
OW
WD Initialization
<8 tWD
OWCW
FLT
tWD OUT_
FLT
½ tWD ½ tWD
tWD OUT_
0
OW
WD FL_ T
WD
FLT OW
WD
Init.
0
0
VOUT
0
0
nRST
nWD EN_
0
CW
<½ tWD
OW
WD Init.
<8 tWD
OWCW
FLT
tWD OUT_
FLT
½ tWD ½ tWD
tWD OUT_
0
OW
WD FLAG_
WD
FLT
OW
WD
Init.
NA
tWD OUT_
tWD OUT_
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
Watchdog Fault Conditions
Figure 27. Watchdog Service Fault Conditions for Figure 28. Watchdog Service Fault Conditions for
TPS7A63xx-Q1 TPS7A6401-Q1
For both device options, a watchdog fault condition As shown in Figure 28, for TPS746401-Q1 the first
occurs in following (non-exhaustive) cases: watchdog fault registers when watchdog receives
i) When the watchdog receives service during a service during a closes window. This causes the
closed window watchdog flag pin (WD_FLAG) to become high and
stay latched. At the same time, nRST pin goes low
ii) When watchdog does not rexceive serviced during temporarily for the duration of tWD_OUT. WD_FLAG
an open window (this open window could be the one remains high until toggling the nWD_EN pin disables
after watchdog initialization, or the one following a and re-enables the watchdog or the watchdog
closed window). receives service properly (while nWD_EN is low and
nRST is high). The second fault registers when the
As shown in Figure 27, for TPS7A63xx-Q1 the first watchdog does not receive service during an open
watchdog fault registers when the watchdog receives window (following a closed window). While
service during a closed window. This causes the WD_FLAG is high (i.e. during a fault condition), if the
watchdog fault pin (WD_FLT) to go low temporarily watchdog stays enabled, and reset is high; a
for a duration of tWD_OUT. Following the fault, the watchdog service signal can also bring WD_FLAG
watchdog reinitializes. Likewise, the second fault low (about 5 µs after the watchdog receives service).
registers when the watchdog does not receive service
during an open window (following a closed window).
Again, the fault pin (WD_FLT) is asserts low for a
duration of tWD_OUT.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
0
VOUT
0
0
nRST
nWD_EN
0
OW
WD Init.
FLT
< ½tWD
93% of VOUT
tDEGLITCH
tPOR
8 tWD
tWD_OUT
<8 tWD
0
OW
WD Initialization CW OW
WD Init.
8 tWD
0
WD
WD_FLT
CW OW
WD Initialization
tWD_OUT
F
L
T
N
A
0
VOUT
0
0
nRST
nWD_EN
FLT
93% of VOUT
tDEGLITCH
tPOR
8 tWD
tWD_OUT
<8 tWD
0
OW
WD Initialization CW OW
WD Init.
8 tWD
0
WD
WD_FLAG
OW
WD Initialization
tWD_OUT tWD_OUT
OW
WD Init. NA
F
L
T
N
A
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
Figure 29. Watchdog Fault During Initialization, Figure 30. Watchdog Fault During Initialization,
and Reinitialization During Reset for TPS7A63xx- and Reinitialization During Reset for TPS7A6401-
Q1 Q1
As shown in Figure 29 for the TPS7A6401-Q1, the As shown in Figure 30 for the TPS7A6401-Q1, the
watchdog fault condition also occurs if the watchdog watchdog fault condition also occurs if the watchdog
does not receive service during the open window does not receive service during the open window
after watchdog initialization. That is, if the watchdog after watchdog initialization. That is, if the watchdog
does not receive service during the first 8× tWD_OUT does not receive service in first 8× tWD_OUT period
period after initialization, a fault condition occurs. This after initialization, a fault condition occurs. This
causes the watchdog fault pin (WD_FLT) to go low causes the watchdog flag pin (WD_FLAG) to become
temporarily for a duration of tWD_OUT. In case of a load high and stay latched. At the same time, the nRST
transient, if the regulated output voltage drops down pin goes low temporarily for a duration of tWD_OUT. In
causing reset (nRST) to go low, the rising edge on the case of a load transient, if the regulated output
nRST causes the watchdog to reinitialize (that is, voltage drops down causing the reset output to go
when reset becomes high with the watchdog still low, the WD_FLAG asserts low, and the rising edge
enabled). During a fault condition (that is, WD_FLT is on nRST causes the watchdog to reinitialize (while
low) with the watchdog disabled, the fault output the watchdog remains enabled). During a fault
continues to stay low until tWD_OUT is elapsed. A condition (that is, WD_FLAG is high), and with a
falling edge on nWD_EN pin causes the watchdog to disabled watchdog, the flag output continues to stay
reinitialize while nRST is still high.
18 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
high as long as the watchdog remains enabled or
receives proper service. However, nRST stays low
until tWD_OUT elapses. Re-enabling the watchdog
causes watchdog to reinitialize (while nRST is still
high).
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6401-Q1
VIN
EN nWD_EN WD
VOUT
nRST
VIN
RDELAY
ROSC
GND
0.1 Fμ
10k
to
200k
Ω
Ω
R1
FB
R2
VOUT
WD_FLT/
WD_FLG
RESET
FAULT/
FLAG
1k
to
5k
Ω
Ω
1k
to
5k
Ω
Ω
10 F
to
22 F
μ
μ
100pF
to 100nF
0.1 Fμ
1 F
to
10 F
μ
μ
TPS7A6333-Q1/
50-Q1TPS7A63
VIN
EN nWD_EN WD
VOUT
nRST
VIN
RDELAY
ROSC
GND
0.1 Fμ
10k
to
200k
Ω
Ω
VOUT
WD_FLT/
WD_FLG
RESET
FAULT/
FLAG
1k
to
5k
Ω
Ω
1k
to
5k
Ω
Ω
10 F
to
22 F
μ
μ
100pF
to 100nF
0.1 Fμ
1 F
to
10 F
μ
μ
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
APPLICATION INFORMATION
Typical application circuits for TPS7A6401-Q1 and
TPS76333-Q1/6350-Q1 are shown in Figure 31 and Power Dissipation and Thermal
Figure 32. Depending on the end application, one Considerations
may use different values of external components. Calculated the power dissipated in the device using
Carefully select feedback resistors (R1 and R2), used Equation 8.
to program the output voltage. Using smaller resistors
results in higher current consumption, whereas using PD= IOUT × (VIN – VOUT)) + IQUIESCENT × VIN (8)
very large resistors impacts the sensitivity of the where,
regulator. Therefore, TI recommends selecting PD= continuous power dissipation
feedback resistors such that the sum of R1 and R2 is
between 20 kΩand 200 kΩ.IOUT = output current
VIN = input voltage
Example VOUT = output voltage
If the desired regulated output voltage is 5 V, after IQUIESCENT = quiescent current
selecting R2 then one can calculate R1 using (or vice
versa) Equation 2. Knowing VREF = 1.23 V (typical), As IQUIESCENT << IOUT, therefore, ignore the term
VOUT = 5 V, selecting R2 = 20 kΩ, the calculated IQUIESCENT × VIN in Equation 8.
value of R1 is 61.3 kΩ.For a device in operation at a given ambient air
During fast load steps, an application may require a temperature (TA), calculate the junction temperature
larger output capacitor to prevent the output from (TJ) using Equation 9.
temporarily dropping down. TI recommends a low- TJ= TA+ (θJA × PD) (9)
ESR ceramic capacitor with dielectric of type X5R or where,
X7R. One can also connect a bypass capacitor at the
output to decouple high-frequency noise as per the θJA = junction-to-ambient-air thermal impedance
end application. Calculate the rise in junction temperature due to
power dissipation using Equation 10.
ΔT = TJ– TA= (θJA × PD) (10)
For a given maximum junction temperature (TJ-Max),
calculate the maximum ambient air temperature (TA-
Max) at which the device can operate using
Equation 11.
TA-Max = TJ-Max – (θJA × PD) (11)
Example
If IOUT = 100 mA, VOUT =5V,VIN = 14 V, IQUIESCENT =
250 µA, and θJA= 50°C/W, the continuous power
dissipated in the device is 0.9 W. The rise in junction
Figure 31. Typical Application Schematic, temperature due to power dissipation is 45°C. For a
TPS7A6333-Q1/6350-Q1 maximum junction temperature of 150°C, the
maximum ambient air temperature at which the
device can operate is 105°C.
Figure 32. Typical Application Schematic
TPS7A6401-Q1
20 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
PCB
Thermal Land Pad
Thermal Via
Ground Plane
Bat Wings
PCB
Thermal Land Pad
Thermal Via
Dedicated
Ground Plane
(a) Multilayer PCB with a dedicated ground plane
(b) Dual layer PCB with Bat wings for enhanced heat spreading
0
0.5
1
1.5
2
2.5
0 25 50 75 100 125 150
Junction Temperature (°C)
Power Dissipated (W)
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
For adequate heat dissipation, TI recommends For optimum thermal performance, TI recommends
soldering the thermal pad (exposed heat sink) to the using a high-K PCB with thermal vias between the
thermal land pad on the PCB. Doing this provides a ground plane and solder pad or thermal land pad; see
heat conduction path from the die to the PCB and Figure 34 (a) and (b). Further, use a thicker ground
reduces overall package thermal resistance. Power plane and a thermal land pad with a larger surface
derating curves for the TPS7A63xx-Q1/6401-Q1 area to inprove considerably the heat-spreading
PWP package and TPS7A6333-Q1 DRK are capabilities of a PCB. For a two-layer PCB, a bat
comparable; see Figure 33. wing layout can enhance the heat-spreading
capabilities.
Figure 33. Power Derating Curve
Figure 34. Using Multilayer PCB and Thermal
Vias for Adequate Heat Dissipation
Keeping other factors constant, surface area of the
thermal land pad contributes to heat dissipation only
to a certain extent.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
REVISION HISTORY
Changes from Original (June 2011) to Revision A Page
• Deleted the Ordering Information Table ............................................................................................................................... 2
• Changed values for VIL and VIH in the Watchdog Enable Input (nWD_EN pin) section ....................................................... 4
• Changed values for VIL and VIH in the Watchdog Input Pulse (WD pin) section .................................................................. 4
Changes from Revision A (August 2011) to Revision B Page
• Deleted devices TPS7A64333-Q1 and TPSA6450-Q1 ........................................................................................................ 1
Changes from Revision B (December 2011) to Revision C Page
• Changed regulated output voltage (6.1), added text to the test conditions (10mA to 200mA, VIN = VOUT + 1V to 16V) ...... 3
Changes from Revision C (April 2012) to Revision D Page
• Added new bullets at top of Features list ............................................................................................................................. 1
• Corrected part number in numerous locations throughout the data sheet ........................................................................... 1
• Deleted the NO. column from the electrical tables ............................................................................................................... 2
• ............................................................................................................................................................................................... 9
• Deleted two Typical Characteristics graphs .......................................................................................................................... 9
22 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jun-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS7A6301QPWPRQ1 ACTIVE HTSSOP PWP 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TPS7A6333QDRKRQ1 ACTIVE VSON DRK 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TPS7A6333QPWPRQ1 ACTIVE HTSSOP PWP 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TPS7A6350QPWPRQ1 ACTIVE HTSSOP PWP 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TPS7A6401QPWPRQ1 ACTIVE HTSSOP PWP 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jun-2012
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS7A6301QPWPRQ1 HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS7A6333QDRKRQ1 VSON DRK 10 3000 330.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
TPS7A6333QPWPRQ1 HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS7A6350QPWPRQ1 HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS7A6401QPWPRQ1 HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7A6301QPWPRQ1 HTSSOP PWP 14 2000 367.0 367.0 35.0
TPS7A6333QDRKRQ1 VSON DRK 10 3000 367.0 367.0 35.0
TPS7A6333QPWPRQ1 HTSSOP PWP 14 2000 367.0 367.0 35.0
TPS7A6350QPWPRQ1 HTSSOP PWP 14 2000 367.0 367.0 35.0
TPS7A6401QPWPRQ1 HTSSOP PWP 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated