9372H-INDCO-11/15
Features
●Fully integrated, single-chip RF transmitter (SIGFOX™ compliant)
●System-on-chip solution including SIGFOX related protocol handling for modem
operation
●AVR® microcontroller core with embedded firmware, SIGFOX, protocol stack and
ID/PAC
●Supports uplink operation, i.e. transmit data telegram to SIGFOX base stations
●Operating frequency range: 868.0MHz to 868.6MHz
●Low current consumption: 32.7mA during telegram transmit with +14.5dBm TX
output power
●Typical OFF mode current: 5nA (maximum 600nA at VS = +3.6V and T = +85°C)
●Data rate: 100bit/s with DBPSK modulation
●SPI interface for TX data access and transmitter configuration
●Event signal indicates the status of the IC to an external microcontroller
●Power-up (typical 10ms OFF mode -> IDLE mode)
●Supply voltage ranges 1.9V to 3.6V and 2.4V to 5.5V (SIGFOX compliant supply
range 3V±5% and 3.3V to 5.5V)
●Temperature range –40°C to +85°C
●ESD protection at all pins (±4kV HBM, ±200V MM, ±750V FCDM)
●Small 55mm QFN32 package/pitch 0.5mm
Applications
SIGFOX compatible modem for long-range, low-power and low-cost applications using the
SIGFOX network
●Home and building automation
●Alarm and security systems
●Smart environment and industrial
●Smart parking
●Tracking
●Metering
ATA8520
Single-Chip SIGFOX RF Transmitter
DATASHEET
ATA8520 [DATASHEET]
9372H–INDCO–11/15
2
1. General Description
1.1 Introduction
The Atmel® ATA8520 is a highly integrated, low-power RF transmitter with an integrated AVR® microcontroller for
applications using the wide area SIGFOX™ network
The Atmel ATA8520 is partitioned into three sections: an RF front end, a digital baseband and the low-power 8-bit AVR
microcontroller. The product is designed for the ISM frequency band in the range of 868.0MHz to 868.6MHz. The external
part count is kept to a minimum due to the very high level of integration in this device. By combining outstanding RF
performance with highly sophisticated baseband signal processing, robust wireless communication can be easily achieved.
The transmit path uses a closed loop fractional-N modulator.
The SPI interface enables external control and device configuration.
1.2 System Overview
Figure 1-1. Circuit Overview
Figure 1-1 shows an overview of the main functional blocks of the Atmel ATA8520. External control of the Atmel ATA8520 is
performed through the SPI pins SCK, MOSI, MISO, and NSS. The functionality of the device is defined by the internal
firmware and processed by the AVR. SPI commands are used to control the device and to start the data telegram
transmission. The end of the telegram transmission is signaled to an external microcontroller on pin 28 (PB6/EVENT).
It is important to note that all PWRON and NPWRON pins (PC1..5, PB4, PB7) are active in OFF mode. This means that
even if the Atmel ATA8520 is in OFF mode and the DVCC voltage is switched off, the power management circuitry within the
Atmel ATA8520 biases these pins with VS.
The AVR microcontroller ports can be used as button inputs, LED drivers, EVENT pin, general purpose digital inputs, or
wake-up inputs, etc. Functionality of these ports is already implemented in the firmware.
RF Frontend
TX
DSP
RF_OUT
DATA BUS
Port BXTO
PLL
XTAL
PB[7..0]
(SPI)
PC[5..0]
Port C
Peripherals
CPU
Supply and Reset
VS
Firmware
SIGFOX
Protocol Stack
ID and PAC
AVCC DVCC
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1.3 Pinning
Figure 1-2. Pin Diagram
Note: The exposed die pad is connected to the internal die.
Table 1-1. Pin Description
Pin No. Pin Name Type Description
1NC Connected to GND
2NC Connected to GND
3NC Connected to GND
4NC Connected to GND
5NC Leave open
6NC Connected to GND
7RF_OUT Analog Power amplifier output
8VS_PA Analog
Power amplifier supply. 3V supply: connect to VS.
5V supply: leave open. Use SPI command “Write System
Configuration” (0x11) to enable 5V supply mode
9NC –Connected to GND
10 XTAL1 Analog Crystal oscillator pin 1 (input)
11 XTAL2 Analog Crystal oscillator pin 2 (output)
12 AVCC Analog RF front-end supply regulator output
13 VS Analog Main supply voltage input
14 PC0 Digital Main : NRESET
15 PC1 Digital Main
Alternate
: AVR Port C1
: NPWRON1
16 PC2 Digital Main
Alternate
: AVR Port C2
: NPWRON2
17 PC3 Digital Main
Alternate
: AVR Port C3
: NPWRON3
NC
NC
AGND
PB7
PB6
PB5
PB4
PB3
PC2
PC1
PC0
VS
AVCC
XTAL2
XTAL1
NC
NC
NC
NC
NC
RF_OUT
VS_PA
PB2
32
1
2exposed die pad
3
4
5
6
7
8
24
23
22
21
20
19
18
17
31 30 29 28 27 26 25
9 10111213141516
PB1
PB0
DGND
DVCC
PC5
PC4
PC3
Atmel
ATA8520
NC
NC
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4
18 PC4 Digital Main
Alternate
: AVR Port C4
: NPWRON4
19 PC5 Digital Main
Alternate
: AVR Port C5
: NPWRON5
20 DVCC –Digital supply voltage regulator output
21 DGND –Digital ground
22 PB0 Digital Main :--
23 PB1 Digital Main : SCK
24 PB2 Digital Main : MOSI (SPI master out Slave in)
25 PB3 Digital Main : MISO (SPI master in Slave out)
26 PB4 Digital Main : PWRON
27 PB5 Digital Main : NSS
28 PB6 Digital Main : EVENT
29 PB7 Digital Main
Alternate
: TX active
: NPWRON6
30 AGND –Analog ground
31 NC –Connected to GND
32 NC –Connected to GND
GND –Ground/backplane on exposed die pad
Table 1-1. Pin Description (Continued)
Pin No. Pin Name Type Description
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1.4 Applications
This section provides application examples for the two supply modes for the Atmel® ATA8520 device. In addition the
recommended PCB design and layout is described to achieve the SIGFOX™ certification.
1.4.1 3V Application Exam pl e
Figure 1-3. 3V Applicatio n with External Microcontroller
Figure 1-3 shows a typical application circuit with an external host microcontroller operating from a 3V lithium cell. The Atmel
ATA8520 stays in OFFMode until NPWRON1 (PC1) is used to wake it up. In OFFMode the Atmel ATA8520 draws typically
less than 5nA at 25°C.
In OFFMode all Atmel ATA8520 AVR® ports PB0..PB7 and PC0..PC5 are switched to input. PC0..PC5 and PB7 have
internal pull-up resistors ensuring that the voltage at these ports is VS. PB0..PB6 are tri-state inputs and require additional
consideration. PB1, PB2, and PB5 have defined voltages since they are connected to the output of the external
microcontroller. PB4 is connected to ground to avoid unwanted power-ups. PB0, PB3 and PB6 do not require external
circuitry since the internal circuit avoids transverse currents in OFFMode. The external microcontroller has to tolerate the
floating inputs. Otherwise additional pull-down resistors are required on these floating lines.
Typically, the Atmel ATA8520 wake-up is done by pulling NPWRON1 (pin 15) to ground.
RF_OUT is matched with C1/L1 for 50 antenna connection. The RF filter is required to suppress unwanted side and
spurious emissions. The design of this filter depends on the final PCB and system layout and is subject to SIGFOX and ETSI
certification procedures.
Together with the fractional-N PLL within the Atmel ATA8520, an external crystal is used to fix the Tx frequency. Accurate
load capacitors for this crystal are integrated to reduce the system part count and cost. Only four supply blocking capacitors
are needed to decouple the different supply voltages AVCC, DVCC, VS, and VS_PA of the Atmel ATA8520. The exposed
die pad is the RF and analog ground of the Atmel ATA8520. It is connected directly to AGND via a fused lead. The Atmel
ATA8520 is controlled using specific SPI commands via the SPI interface.
NC
IRQ
NSS
MISO
MOSI
SCK
RF Filter
VDD
NC
AGND
PB7
PB6
PB5
PB4
PB3
PC2
PC1
PC0
VS
AVCC
XTAL2
XTAL1
NC
NC
NC
NC
RF_OUT
VS_PA
PB2
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
31 30 29 28 27 26 25
910111213141516
PB1
PB0
DGND
DVCC
PC5
PC4
PC3
VS = 3V
Supply
L1
C1
C2
Q1 C3 C4
C5
Microcontroller
Atmel
ATA8520
Wake/Monitor
NC
NC
NC
C6
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1.4.2 5V Application Exam pl e
In addition to the 3V supply mode the device can be used with a 3.3V to 5.5V supply voltage as shown in Figure 1-4. This
requires to remove the connection between VS and VS_PA (pin 8) and to enable the internal LDO regulator. The 5V mode
can be enabled using the SPI command “Write System Configuration” (0x11) followed by a system reset to enable these
settings (the 5V mode can only be used with firmware revision ≥V1.0. Firmware revisions <V1.0 allow only the 3V supply
mode).
Figure 1-4. 5V Applicatio n with External Microcontroller
Figure 1-4 shows a typical application circuit with an external host microcontroller operating from a 5V supply. This
application differs from the 3V supply mode that VS is not connected to VS_PA. Instead an internal LDO must be activated
using the SPI command “Write System Configuration” (0x11) after powering the device and before transmitting a data
telegram.
NC
IRQ
NSS
MISO
MOSI
SCK
VDD
NC
AGND
PB7
PB6
PB5
PB4
PB3
PC2
PC1
PC0
VS
AVCC
XTAL2
XTAL1
NC
NC
NC
NC
RF_OUT
VS_PA
PB2
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
31 30 29 28 27 26 25
910111213 1415 16
PB1
PB0
DGND
DVCC
PC5
PC4
PC3
VS = 5V
Supply
Q1 C3 C4
C5
Microcontroller
Atmel
ATA8520
Wake/Monitor
NC
NC
NC
RF Filter
L1
C1
C2
C6
7
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2. System Functional Description
2.1 SPI Command Interface
The SPI command interface requires a timing setup as described in the following section and provides a set of commands to
control the operation of the Atmel® ATA8520 device. The SPI transmission occurs with MSB first.
2.1.1 SPI Timing
The SPI communication requires a special timing to prevent data corruption. The SPI peripheral uses a SCK frequency of
125kHz for the bit transmission and requires timing delays between the CS signals and the start and stop of the SPI
communication as shown in Figure 2-1.
Figure 2-1. SPI Timing Parameters
T0 ≥ 65µs, T1 ≥ 40µs, T2 ≥ 100µs, T3 ≥ 50µs, SPI CLK ≤ 125kHz (SPI Mode 0: CPOL = CPHA = 0)
2.1.2 SPI Command Set
The following SPI commands are available to control the ATA8520 operation from a host microcontroller.
2.1.2.1 System Reset
This command uses the system internal WDT to do a complete hardware reset of the ATA8520D. Resetting the device takes
~10ms. Afterwards the system restarts and generates an event on the EVENT signal after ~10ms. This event will be cleared
with the “Get Status” SPI command (0x0A).
2.1.2.2 I/O Init
The I/O lines of port C can be used as additional I/O lines for an application. The port C I/O Init command defines the internal
data direction register of output port PORTC (DDRC). Pin PC0 is used as NRESET signal and will always be an input pin,
i.e. bit 0 will be written as 0 to be an input pin.
2.1.2.3 I/O Write
The I/O write command writes directly to the output port register PORTC to set the I/O pins. Pin PC0 is used as NRESET
signal and will always be an input pin with enabled pull-up, i.e. bit 0 will be written as 1 to enable the internal pull-up resistor.
T0
NSS
CLK
MISO/MOSI
T1 T2 T3
Master System Reset (0x01)
ATA8520 Dummy
Master I/O Init (0x02) DDRC content
ATA8520 Dummy Dummy
Master I/O Init (0x03) PORTC content
ATA8520 Dummy Dummy
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2.1.2.4 I/O Read
The I/O read command reads the status of the I/O pins directly from the input port register PINC. Pin PC0 is used as
NRESET signal and will always be read as 1.
2.1.2.5 OFF Mode
The OFF mode command puts the ATA8520 into off mode. To wake up the ATA8520 device, one of the power on lines has
to be activated, i.e. set PWRON line to high or NPWRONx line to low. To switch the device into OFF mode the power on
lines have to be de-activated before otherwise the device will remain in the on state.
2.1.2.6 Atmel Version
The Atmel version command reads the version information including a major and a minor version number.
2.1.2.7 Write TX Buffer
The write TX buffer command fills the TX buffer to be sent with the next SIGFOX™ data frame with payload data of up to 12
bytes. The buffer can hold any number of bytes ranging from 0 to 12 bytes and are not buffered, i.e. a new SPI command will
override the previous data.
2.1.2.8 Test Mode (for Atmel Version <V1.0)
The test mode command triggers the SIGFOX defined test procedure to generate a test signal with frame (high, low byte):
Number of frames to be send. Each frame is send 3 times [0...32768, –1 for infinite]. Chain (high, low Byte): Channel number
used for transmission [0...480, –1 for hopping].
Note: This command will change in next generation devices.
2.1.2.9 SIGFOX Vers io n
The SIGFOX version reads the SIGFOX library version information as a text string with N = 11 characters.
Master I/O Read (0x04) Dummy Dummy
ATA8520 Dummy Dummy PINC content
Master OFF Mode (0x05)
ATA8520 Dummy
Master Atmel Version (0x06) Dummy Dummy Dummy
ATA8520 Dummy Dummy MajorVers MinorVers
Master Write TX Buffer (0x07) RF TX Num bytes RF TX Bytes 0 ..............
RF TX Num
bytes-1
ATA8520 Dummy Dummy Dummy Dummy
Master Test Mode (0x08) FrameLowByte FramHighByte ChanLowByte ChanHighByte
ATA8520 Dummy Dummy Dummy Dummy Dummy
Master SIGFOX Version (0x09) Dummy Dummy .............. Dummy
ATA8520 Dummy Dummy SFX Verinfo[0] SFX Verinfo[N]
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2.1.2.10 Get Status
The get status command reads the internal status of the device. Issuing this command clears the systems event line (PB6)
and the status bytes. The event line is set to low when:
a. System is ready after power-up or reset
b. finishes the transmit operation
c. finishes a temperature and supply measurement
d. finishes the EEPROM write operation.
The following status information is read after the event line is activated, i.e. polling using the Get Status command is not
necessary:
Hardware SSM status
Atmel® status:
●Bit6: System ready to operate (system ready event)
●Bit5: Frame sent (frame ready event)
●Bit4 to Bit1: Error code
●0000: no error
●0001: command error / not supported
●0010: generic error
●0011: frequency error
●0100: usage error
●0101: opening error
●0110: closing error
●0111: send error
●Bit0: PA on/off indication
SIGFOX™ status:
●0x00: No error
●0x01: Manufacturer error
●0x02: ID or key error
●0x03: State machine error
●0x04: Frame size error
●0x05: Manufacturer send error
●0x06: Get voltage/temperature error
●0x07: Close issues encountered
●0x08: API error indication
●0x09: Error getting PN9
●0x0A: Error getting frequency
●0x0B: Error building frame
●0x0C: Error in delay routine
●0x0D: callback causes error
●0x0E: timing error
●0x0F: frequency error
Master Get Status (0x0A) Dummy Dummy Dummy Dummy
ATA8520 Dummy Dummy SSM status Atmel status SIGFOX status
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2.1.2.11 Send Data Bit
This command sends a data bit (0/1) within a SIGFOX™ RF frame as specified by SIGFOX. An event on the EVENT signal is
generated when finished.
2.1.2.12 Send Frame
The send frame command triggers the start of a frame transmit process. The payload data has to be written into the TX
buffer before using the write TX buffer command. The transmit operation will take ~7 seconds and will generate an event on
the EVENT signal when finished. For Atmel® version ≥1.0 pin PB7 is switched to logic “1” during transmit operation which
can be used to control an external power amplifier.
2.1.2.13 Get PAC
The get PAC command will read the 16 byte PAC information which is used for the device registration process at the
SIGFOX backend. Only the 8 lower bytes (0) .. (7) are used, the remaining 8 upper bytes (8) .. (15) are read as 0.
2.1.2.14 Write System Configuration
The Write System Configuration command writes the configuration data for the port C and the system configuration into the
internal EEPROM. This changes will be applied by performing a system reset. An event on the EVENT signal is generated
when finished.DDRC register defines the data direction for the port C pins (0: input, 1: output). PORTC register defines the
output level for an output pin and enables a pull-up resistor for input pins when set. SysConf has to be set to 0xFF for 3V
supply mode and 0xF7 for 5V supply mode.
5V supply mode can only be used when this command was send before, otherwise the device may be damaged.
2.1.2.15 Get ID
The get ID command will read the 4 byte ID information which is used for the device registration process at the SIGFOX
backend.
Master Send Bit (0x0B) Bit
ATA8520 Dummy Dummy
Master Send Frame (0x0D)
ATA8520 Dummy
Master Get PAC (0x0F) Dummy Dummy ...... Dummy
ATA8520 Dummy Dummy PAC ID[0] PAC ID[15]
Master Write Sys Conf (0x11) DDRC PORTC 0x02 SysConf
ATA8520D Dummy Dummy Dummy Dummy Dummy
Master Get ID (0x12) Dummy Dummy ...... Dummy
ATA8520 Dummy Dummy UID[3] UID[0]
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2.1.2.16 Read Supply Voltage and Temperature
This command triggers the read out of the measured supply voltage in idle and active mode and the device temperature. To
trigger a measurement the SPI command (0x14) has to be used. The return voltage level is in mV and the temperature value
has to be calculated as T = (TM – 500)/10 in °C. All values are of type 16 bit unsigned integer (with high and low byte).
2.1.2.17 Start Supply and Temperature Measurement
This command will start the measurement of the temperature and the supply voltage. An event on the EVENT signal is
generated when finished.
2.1.2.18 S tart TX Test Mode
The test mode command triggers the SIGFOX™ defined test procedure to generate a test signal with frame (high, low byte):
Number of frames to be send. Each frame is send 3 times [0...32768, –1 for infinite]. Chain (high, low Byte): Channel number
used for transmission [0...480, –1 to deactivate hopping]. An event on the EVENT signal is generated when finished.
2.1.2.19 Send CW
The test mode command enables or disables the transmission of a continuous carrier (CW) as defined by SIGFOX.
2.1.2.20 Set TX Frequency
Set TX center frequency temporarily for testing purposes. This settings are lost after reset or when switching the device off.
The frequency value is an unsigned 32-bit integer within the range [868.000.000Hz to 868.600.000Hz]. Default is
868.130.000Hz.
Master Read Sup/Temp
(0x13) Dummy Dummy Dummy Dummy Dummy Dummy Dummy
ATA8520 Dummy Dummy VHidle VLidle VHactive VLactive TemperatureH TemperatureL
Master Start Measurement (0x14)
ATA8520 Dummy
Master TX Test Mode (0x15) FrameLowByte FramHighByte ChanLowByte ChanHighByte
ATA8520 Dummy Dummy Dummy Dummy Dummy
Master Send CW (0x17) On(0x11)/Off(0x00)
ATA8520 Dummy Dummy
Master Set TX Frequency (0x1B) TX[31:24] TX[23:16] TX[15:8] TX[7:0]
ATA8520 Dummy Dummy Dummy Dummy Dummy
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2.1.3 Command Table Overview
Table 2-1. Command Table Overview
CMD Index Write D ata Read Data
System reset 0x01 None None
I/O Init 0x02 DDRC register setting None
I/O Write 0x03 PORTC register setting None
I/O Read 0x04 None PINC register setting
OFF mode 0x05 None None
Atmel version 0x06 None Major / minor
Write TX buffer 0x07 Data written to TX buffer None
Test mode (<V1.0) 0x08 Frame/channel None
Reserved (≥V1.0) - -
SIGFOX™ version 0x09 None Version L-H
Get status 0x0A None SSM / Atmel® FW / SIGFOX library
Send bit 0x0B(1) Bit (0/1) None
Reserved 0x0C - -
Send frame 0x0D None None
Reserved 0x0E - -
Get PAC 0x0F None PAC[0], PAC[1] …. PAC[15]
Reserved 0x10 - -
Write Sys Conf 0x11(1) DDRC, PORTC, SysConf None
Get ID 0x12 None ID[3] … ID[0]
Read sup/temp 0x13(1) None Supply idle / supply active / temperature
Start measurement 0x14(1) None None
TX test mode 0x15(1) Frame/channel None
Reserved 0x16 - -
Send CW 0x17(1) On/Off None
Reserved 0x18 - -
Reserved 0x19 - -
Reserved 0x1A - -
Set TX frequency 0x1B(1) TX frequency None
Reserved 0x1C - -
Note: 1. These commands are available in device with Atmel Version V ≥ 1.0
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2.2 Operating Modes Overview
This section gives an overview of the operating modes supported by the Atmel ATA8520.
After connecting the supply voltage to the VS pin, the Atmel ATA8520 always starts in OFF mode. All internal circuits are
disconnected from the power supply. Therefore, no SPI communication is supported. The Atmel ATA8520 can be woken up
by activating the PWRON pin or one of the NPWRONx pins. This triggers the power-on sequence which will set the event
line PB6 to low. After the system initialization the Atmel ATA8520 reaches the IDLE Mode.
The IDLE Mode is the basic system mode supporting SPI communication and transitions to the other operating modes. The
transmit mode (TX Mode) starts the data transmission using the payload data which has to be previously written into the TX
buffer with the SPI command “Write TX Buffer”. The data transmission is started with the SPI command “Send Frame”. After
transmitting the data frame, the end of the transmission is indicated when the event pin PB6 switches to low and the device
enters the IDLE Mode again. Reading the device status with the “Get Status” SPI command clears the PB6 event line,
setting it to high level again.
2.2.1 System Config u rat io n
This section specifies the system configuration settings used in the SPI command (0x11). This system configuration has to
be set after the system issues a system ready event and before using any other SPI RF transmit command. The settings are
stored in the internal EEPROM and will be applied after a system reset. This settings are typically applied at the EOL testing
in the factory. Table 2-2 summarizes the configuration settings.
Caution: The device is delivered with default configuration, i.e. with 3V supply mode enabled. When using the device
with 5V supply it has to be ensured that before using the RF transmit operation the 5V supply mode is
configured!
2.2.2 Power-up Sequence
This section describes the power-up sequence for the device as described in Figure 2-2. The device is usually in OFF mode
were the signals NPWRONx, PWRON and NRESET are inactive but VS is supplied with power. Switching the NRESET
signal active or sending the SPI command System Reset (0x01) will have no effect in OFF mode. Switching one of the
power-on pins active will wake-up the device and an internal power-on reset is performed. In addition the external NRESET
line can be used to keep the device in reset state when waking-up the device. The minimum activation time for the
NPWRONx, PWRON and NRESET signals is 10µs.
Figure 2-2. Power-up Sequence
Table 2-2. System Configuration
Function Bit No. Settings
None 7 to 4 :1111 (default)
Supply voltage 3:0, 5V supply
:1, 3V supply (default)
None 2 to 0 :111 (default)
1
NPWRONx
PWRON
NRESET
EVENT
2 3 4 5 6
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After applying the reset signal NRESET one of the power-up signals NPWRON1...6 or PWRON is applied at timing point T1.
At timing point T2 (~10µs after T1) the external reset signal is removed and the device starts its internal power-up sequence.
This internal sequence is finished at timing point T3 (~10ms after T2) and is signaled with the event line. Reading the device
status with the SPI command (0x0A) „Get status” will clear the event line at timing point T4. The device is now in idle mode
and operational even if the NPWRONx and PWRON signals are deactivated.
To shutdown the device into OFF mode the power-up signals NPWRON1...6 or PWRON have to be deactivated at first
(shown in timing point T5). The shutdown into OFF mode is then performed by sending the SPI command (0x05) „OFF
mode” to the device.
2.2.3 Application Example
The software to control the device and to transmit a data frame has to perform the following steps:
1. Initialize device as shown in Figure 2-2 for the power-up sequence
2. Check for the startup event and read the device status with SPI command (0x0A) „Get status” to clear this event
3. Load the transmit buffer with up to 12 bytes using the SPI command (0x07) „Write TX Buffer“
4. Start the data transmit with SPI command (0x0D) „Send Frame“
5. Wait until the event signal appears (this takes about 7-8 seconds)
6. Read the device status with SPI command (0x0A) „Get status” to clear this event
7. Switch off the power-on signals as shown in Figure 2-2
8. Send the SPI command (0x05) „OFF mode” to the shutdown the device
For the SPI communication it is important to keep the timing as shown in Figure 2-1 on page 7. With the SPI commands
(0x0F) „Get PAC” and (0x12) „Get ID” the SIGFOX™ registration information can be read to register the device in the
SIGFOX cloud.
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3. Electrical Characteristics
3.1 ESD Protection Circuits
GND is the exposed die pad of the Atmel® which is internally connected to AGND (pin 30). All Zener diodes shown in
Figure 3-1 (marked as power clamps) are realized with dynamic clamping circuits and not physical Zener diodes. Therefore,
DC currents are not clamped to the shown voltages.
Figure 3-1. Atmel ESD Protection Circuit
VS
(Pin 13)
AVCC
(Pin 12)
Power
Clamp
1.8V
Power
Clamp
3.3V
Power
Clamp
5.5V
Power
Clamp
1.8V
GND
GND
GND
RF_OUT
(Pin 7)
PC0 to PC5
(Pin 14 to Pin 19)
DGND
(Pin 21)
PB0 to PB7
(Pin 22 to Pin 29)
VS_PA (Pin 8) VS (Pin 13)
VS (Pin 13) DVCC (Pin 20)
AGND
(Pin 30)
XTAL2
(Pin 11)
GND
XTAL1
(Pin 10)
ATA8520 [DATASHEET]
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16
3.2 Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters Symbol Min. Max. Unit
Junction temperature Tj +150 °C
Storage temperature Tstg –55 +125 °C
Ambient temperature Tamb –40 +85 °C
Supply voltage VVS –0.3 +6.0 V
Supply voltage PA (1.9 to 3.6V application) VVS_PA –0.3 +4.0 V
ESD (human body model) all pins HBM –4 +4 kV
ESD (machine model) all pins MM –200 +200 V
ESD (field induced charged device model) all pins FCDM –750 +750 V
3.3 Thermal Resistance
Parameters Symbol Value Unit
Thermal resistance, junction ambient, soldered in
compliance with JEDEC Rth_JA 35 K/W
3.4 Supply Voltages and Current Consumption
All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V across all process tolerances
unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified.
Crystal oscillator frequency fXTO = 24.305MHz.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.00 Supply voltage
range VS
3V application 13 VVS 1.9 3.0 3.6 V A
5V application 13 VVS 2.4 5.0 5.5 V A
1.01 Supply voltage for
SIGFOX™ compliance
3V application 13 VVS 2.9 3.0 3.1 V
5V application 13 VVS 3.3 5.0 5.5 V
1.05 Supply voltage rise
time 13 VVS_rise 1V/µs D
1.10 Supply voltage range
VS_PA
3V application 8VVS_PA 1.9 33.6 V A
5V application 8VVS_PA 3 V A
SIGFOX compliant 8VVS_PA 3 V
1.20 OFF mode
Current consumption
Tamb = 25°C
Tamb = 85°C 8, 13 IOFFMode_3V 5150
600
nA
nA
B
B
1.30 Idle Mode current
consumption
Temperature range
–40°C to +65°C 13 IIdleMode 50 90 µA B
*) Type means: A = 100% tested, B = 100% correlation tested, C = characterized on samples, D = design parameter
Pin numbers in brackets mean they are measured matched to 50 on the application board.
17
ATA8520 [DATASHEET]
9372H–INDCO–11/15
2.00 TX mode current
consumption
Pout = +14dBm
fRF = 868.3MHz
(7), 8,
13 ITXMode 32.7 45 mA B
2.05 SIGFOX™ TX mode
current consumption
Tamb = 25°C,
3V application
(7), 8,
13 ISIGFOXMode 31.8 40.1 mA B
2.06 SIGFOX TX mode
current consumption
Tamb = 85°C,
3V application
(7), 8,
13 ISIGFOXMode 32.7 41.1 mA B
3.4 Supply Voltages and Current Consumption (Continued)
All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V across all process tolerances
unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified.
Crystal oscillator frequency fXTO = 24.305MHz.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = characterized on samples, D = design parameter
Pin numbers in brackets mean they are measured matched to 50 on the application board.
3.5 RF Transmit Characteristics
All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V across all process tolerances
unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified.
Crystal oscillator frequency fXTO = 24.305MHz.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
10.00 Output power range Tamb = 25°C (7) PRange +14.5 dBm B
10.01 Output power for
SIGFOX compliance
Tamb = 25°C, VVS =2.9V
to 3.1V, 3V application
(for 5V applications see
no. 11.50)
(7) PSIGFOX 13.5 13.8 14.0 dBm B
10.02 Output power for
SIGFOX compliance
Tamb = –45°C to +85°C,
VVS = 3.0V, 3V application
(for 5V applications see
no. 11.50)
(7) PSIGFOX 13.1 13.8 14.7 dBm B
10.05 Frequency range Defined by SIGFOX
protocol (7) fVCO 868.0 868.6 MHz
11.00 Output power at
14dBm
Tamb = 25°C
using 14dBm matching
(7) Pout_14dBm –1.5dB 14 +1.5dB dBm B
11.10 Output 2nd harmonic
at 14dBm
Tamb = 25°C
using 14dBm matching
(7) HM214dBm –24 dBc C
11.20 Output 3rd harmonic
at 14dBm
Tamb = 25°C
using 14dBm matching
(7) HM314dBm –50 dBc C
11.50
Output power change
full temperature and
supply voltage range
For 13.8dBm
VVS_PA = 3.0V ±0.3V
P = Pout + P
(7) PTambVs2 –3.5 +2 dB C
C
11.60 Spurious emission
at ±fXTO
at ±fAVR (fXTO / 4)
at ±fCLK_OUT (fXTO / 6)
(7) SPTX
–72
–85
–78
–60
–60
–60
dBc
B
C
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = characterized on samples, D = design parameter
Pin numbers in brackets mean they are measured matched to 50 on the application board.
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18
3.6 RF Transmit Characteristics
All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances,
quartz parameters Cm = 4fF and C0 = 1pF unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a
typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
13.30 XTO frequency range 10, 11 fxto 24.305 MHz C
13.35 XTO frequency for
SIGFOX™ compliance
KDS: 1C324305AB0B
NDK: NX3225SA
EXS00A-CS08559
NX2016SA
EXS00A-CS08560
10, 11 fSIGFOX_XTO 24.305 MHz
13.40
XTO pulling due to
internal capacitance
and XTO tolerance
Cm = 4fF, Tamb = 25°C 10, 11 FXTO1 –10 +10 ppm B
13.50
XTO pulling due to
temperature and
supply voltage
Cm = 4fF
Tamb = –40°C to +85°C 10, 11 FXTO2 –4 +4 ppm B
13.60 Maximum C0 of XTAL XTAL parameter 10, 11 C0_max 1 2 pF D
13.70 XTAL, Cm motional
capacitance XTAL parameter 10, 11 Cm410 fF D
13.80 XTAL, real part of XTO
impedance at start-up Cm = 4fF, C0 = 1pF 10, 11 Rm_start1 950 B
13.90 XTAL, real part of XTO
impedance at start-up
Cm = 4fF, C0= 1pF,
Tamb < 85°C 10, 11 Re_start2 1100 B
14.00 XTAL, maximum Rm
after start-up XTAL parameter 10, 11 Rm_max 110 D
14.10 Internal load capacitors
Including ESD and
package capacitance.
XTAL has to be specified
for 7.5pF load capacitance
(incl. 1pF PCB
capacitance per pin)
10, 11 CL1, CL2 13.3 14 14.7 pF B
*) Type means: A = 100% tested, B = 100% correlation tested, C = characterized on samples, D = design parameter
Pin numbers in brackets mean they are measured matched to 50 on the application board.
19
ATA8520 [DATASHEET]
9372H–INDCO–11/15
3.7 I/O Characteristics for Ports PB0 to PB7 and PC0 to PC5
All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances
unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified.
Crystal oscillator frequency fXTO = 24.305MHz.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
15.00 Input low voltage PC0 to PC5
PB0 to PB7
14-19
22-29 VIL –0.3 0.2 VVS V A
15.05 Input low leakage
current I/O pin
PC0 to PC5
PB0 to PB7
14-19
22-29 IIL –1 µA A
15.10 Input high voltage PC0 to PC5
PB0 to PB7
14-19
22-29 VIH 0.8 VVS VVS + 0.3 V A
15.15 Input high leakage
current I/O pin
PC0 to PC5
PB0 to PB7
14-19
22-29 IIH 1µA A
15.20 Output low voltage IOL = 0.2mA 14-19
22-29 VOL_3V 0.1 VVS V A
15.30 Output high voltage IOH = –0.2mA 14-19
22-29 VOH_3V 0.9 VVS V A
15.40 I/O pin pull-up resistor OFF mode:
see port B and port C
14-19
22-29 RPU 30 50 70 kA
16.10 I/O pin output delay
time (rising edge) CLoad = 10pF 14-19
22-29 Tdel_rise_3V 13.6 17.5 22.4 ns D
16.20
I/O pin rise time
(0.1 VVS to
0.9 VVS)
CLoad = 10pF 14-19
22-29 Trise_3V 20.7 23.9 28.4 ns D
16.30 I/O pin slew rate
(rising edge) CLoad = 10pF 14-19
22-29 Tsr_rise_3V 0.115 0.100 0.084 V/ns D
16.40 I/O pin output delay
time (falling edge) CLoad = 10pF 14-19
22-29 Tdel_fall_3V 13.7 17.4 22.7 ns D
16.50
I/O pin fall time
(0.9 VVS to
0.1 VVS)
CLoad = 10pF 14-19
22-29 Tfall_3V 16.2 19.2 22.5 ns D
16.60 I/O pin slew rate
(falling edge) CLoad = 10pF 14-19
22-29 Tsr_fall_3V 0.148 0.125 0.106 V/ns D
*) Type means: A = 100% tested at voltage and temperature limits, B = 100% correlation tested, C = characterized on samples,
D = design parameter
3.8 Hardware Timings
All parameters refer to GND (backplane) and are valid for Tamb = –40°C to + 85°C, VVS =1.9V to 3.6V over all process tolerances.
Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency
fXTO = 24.305MHz.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
17.50 Startup time
PWRON = ‘1’ or
NPWRON = ‘0’ to
EVENT generation
13, 20 TSTARTUP 10 ms C
*) Type means: A = 100% tested at voltage and temperature limits, B = 100% correlation tested, C = characterized on samples,
D = design parameter
ATA8520 [DATASHEET]
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20
Figure 3-2. SPI Interface Timing Requirements
3.9 Hardware SPI Timing Characteristics
Timing shown for CPHA=0 and CPOL=0 in Figure 3-2, timing is valid for all CPHA and CPOL configurations. See also Section 2.1
“SPI Command Interface” on page 7 for functional SPI description and for firmware limitations on SPI data transfer.
All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V (3V Application) and 4.5V to
5.5V (5V Application) over all process tolerances. Typical values are given at VVS =5V, T
amb = 25°C, and for a typical process unless
otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
49.10 SCK cycle time 23 TSCK_periode 8µs D
49.20 SCK high or low time 23 TSCK_high_low 330 ns D
49.30 SCK rise or fall time 23 TSCK_rise_fall 100 ns D
49.40 MOSI setup time to
active edge of SCK 23, 24 TSetup 80 ns D
49.50 MOSI hold time to
active edge of SCK 23, 24 THold 245 ns D
49.60
Time periode active
edge of SCK to data
out at MISO
CLOAD_MISO = 10pF 23, 25 TSCK_out 250 ns D
49.70 Time periode SCK
inactive to NSS high 23, 27 TSCK_NSS_high 100 µs D
49.80 Time periode NSS
high to MISO tristate CLOAD_MISO = 10pF 25, 27 TNSS_high_tristate 250 ns D
49.90 Time periode NSS low
to active edge SCK 23, 27 TNSS_low_SCK 65 µs D
*) Type means: A = 100% tested at voltage and temperature limits, B = 100% correlation tested, C = characterized on samples,
D = design parameter
TNSS_low_SCK TSCK_out
THold
TSetup
TSCK_periode
MSB
NSS
SCK
(CPOL = 0)
MOSI
(Data Input)
MISO
(Data Output) MSB LSB
LSB
TNSS_high_tristate
TSCK_NSS_high
TSCK_rise_fall
TSCK_high_low
21
ATA8520 [DATASHEET]
9372H–INDCO–11/15
5. Package Information
4. Ordering Information
Extended Type Number Package Remarks
ATA8520-GHQW QFN32 5mm 5mm, Pb-free, 6k, taped and reeled
COMMON DIMENSIONS
(Unit of Measure = mm)
Package Drawing Contact:
packagedrawings@atmel.com
GPC
SYMBOL MIN NOM MAX NOTE
0.8A 0.85 0.9
0A1 0.035 0.05
0.16A3 0.21 0.26
4.9D 55.1
3.5D2 3.6 3.7
4.9E 55.1
3.5E2 3.6 3.7
0.35L0.4 0.45
0.2b 0.25 0.3
e0.5
DRAWING NO.
REV. TITLE
6.543-5124.03-4 1
10/18/13
Package: VQFN_5x5_32L
Exposed pad 3.6x3.6
Dimensions in mm
specifications
according to DIN
technical drawings
Top View
Partially Plated Surface
D
1
8
32
PIN 1 ID
E
Side View
A3
A
A1
b
L
Z 10:1
Bottom View
e
D2
9
1
8
16
17
24
25
32
E2
Z
Two Step Singulation process
ATA8520 [DATASHEET]
9372H–INDCO–11/15
22
6. Disclaimer
Atmel® components and materials in the Product comply with Atmel data sheet and the Product has achieved SIGFOX-
compliant certification. Apart from these warranties, the customer acknowledges that no express or implied warranties are
given in relation to the Product and, in particular, no warranties are given in relation to the quality or suitability of any third
party software or materials incorporated into the Product.
Atmel does not warrant that the Product will be error-free and the Customer acknowledges that it has not been developed to
meet the Customer's individual requirements. Accordingly, Atmel accepts no liability or responsibility with regard to any third
party software or materials incorporated into the Product and in no event shall Atmel be liable for any direct, indirect or
consequential loss (of whatever nature) caused by the use or possession of any third party software or material.
Without prejudice to the remainder of this Agreement, in no circumstances will Atmel's liability to the Customer for any direct
loss or damage arising out of use or possession of the Product (if any) exceed the price payable for the relevant Order
relating to the defective Product. In no circumstances will Atmel be liable for any indirect or consequential loss or for any loss
of profits or revenue caused by the Product being defective.
7. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No. History
9372H-INDCO-11/15 Section 2.2.1 “System Configuration” on page 13 updated
9372G-INDCO-10/15
Table 1-1 “Pin Description” on page 3 updated
Section 1.4 “Applications” on pages 5 to 6 updated
9372F-INDCO-09/15
Section 1.4.3 “Recommended PCB Design and Layout” removed
Section 3.5 “RF Transmit Characteristics” on page 17 updated
9372E-INDCO-08/15
Section 1.4.3 “Recommended PCB Design and Layout” on page 7 updated
Section 2.1 “SPI Command Interface” on pages 8 to 12 updated
Section 2.2 “Operating Modes Overview” on page 14 updated
Section 3.9 “Hardware SPI Timing Characteristics” on page 21 added
9372D-INDCO-06/15
Section 2.1 “SPI Command Interface” on pages 9 to 13 updated
Figure 3-1 “Atmel ESD Protection Circuit” on page 15 updated
Section 3.2 “Absolute Maximum Ratings” on page 16 updated
Section 3.4 “Supply Voltages and Current Consumption” on pages 16 to 17 updated
Section 6 “Disclaimer” on page 21 added
9372C-INDCO-06/15
Features on page 1 updated
Section 1.3 “Pinning” on page 3 updated
Section 1.4 “Applications and Recommendations” on pages 5 to 7 updated
Section 2 “System Functional Description” on pages 8 to 12 updated
Section 3.2 “Absolute Maximum Ratings” on page 15 updated
Section 3.4 “Supply Voltages and Current Consumption” on pages 15 to 16 updated
Section 3.5 “RF Transmit Characteristics” on page 16 updated
Section 3.8 “Hardware Timings” on page 18 updated
9372B-INDCO-01/15
Power-up timing in section “Features” on page 1 updated
Section 2.1.2.6 “Atmel Version” on page 7 updated
Table 2-1 “Command Table Overview” on page 9 updated
Section 2.2.1 “Power-up Sequence” on page 10 updated
Figure 2-2 “Power-up Sequence” on page 10 updated
Section 2.2.2 “Application Example” on page 10 updated
X
XXX
XX
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© 2015 Atmel Corporation. / Rev.: 9372H–INDCO–11/15
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