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FEATURES DESCRIPTION
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SYNC1
SYNC2
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
TCLK_R/F
TCLK
DVCC
DVCC
AVCC
AGND
PWRDN
AGND
DO+
DO–
AGND
DEN
AGND
AVCC
DGND
DGND
SN65LV1021
Serializer
1
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15
AGND
RCLK_R/F
REFCLK
AVCC
RI+
RI–
PWRDN
REN
RCLK
LOCK
AVCC
AGND
AGND
DGND
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
DVCC
DGND
DVCC
DGND
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
SN65LV1212
Deserializer
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
•100-Mbps to 400-Mbps Serial LVDS Data
The SN65LV1021 serializer and SN65LV1212Payload Bandwidth at 10-MHz to 40-MHz
deserializer comprise a 10-bit serdes chipsetSystem Clock
designed to transmit and receive serial data overLVDS differential backplanes at equivalent parallel•Pin-Compatible Superset of NSM
word rates from 10 MHz to 40 MHz. IncludingDS92LV1021/DS92LV1212
overhead, this translates into a serial data rate•Chipset (Serializer/Deserializer) Power
between 120-Mbps and 480-Mbps payload-encodedConsumption <350 mW (Typ) at 40 MHz
throughput.•Synchronization Mode for Faster Lock
Upon power up, the chipset link can be initialized via•Lock Indicator
a synchronization mode with internally generatedSYNC patterns, or the deserializer can be allowed to•No External Components Required for PLL
synchronize to random data. By using the•Low-Cost 28-Pin SSOP Package
synchronization mode, the deserializer establishes•Industrial Temperature Qualified,
lock within specified, shorter time parameters.T
A
= -40°C to 85°C
The device can be entered into a power-down state•Programmable Edge Trigger on Clock
when no data transfer is required. Alternatively, a(Rising or Falling Edge)
mode is available to place the output pins in the•Flow-Through Pinout for Easy PCB Layout high-impedance state without losing PLL lock.
The SN65LV1021 and SN65LV1212 arecharacterized for operation over ambient airtemperature of -40°C to 85°C.
ORDERING INFORMATION
DEVICE PART NUMBER
Serializer SN65LV1021DBDeserializer SN65LV1212DB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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SYNC1
SYNC2
DEN
A+
A–
PLL
10
SN65LVDS1021
LVDS
Timing /
Control
Input Latch
Parallel-to-Serial
TCLK_R/F
DIN
Y+
Y–
PLL
SN65LVDS1212
Timing /
Control
Output Latch
Serial-to-Parallel
Clock
Recovery
10
DOUT
REN
REFCLK
LOCK
RCLK_R/F
RCLK
(10 MHz to
40 MHz)
TCLK
(10 MHz
to
40 MHz)
FUNCTIONAL DESCRIPTION
INITIALIZATION MODE
SYNCHRONIZATION MODE
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAMS
The SN65LV1021 and SN65LV1212 are a 10-bit serializer/deserializer chipset designed to transmit data overdifferential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 40 MHz. The chipsethas five states of operation: initialization mode, synchronization mode, data transmission mode, power-downmode, and high-impedance mode. The following sections describe each state of operation.
Initialization of both devices must occur before data transmission can commence. Initialization refers tosynchronization of the serializer and deserializer PLLs to local clocks.
When V
CC
is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state,while on-chip power-on circuitry disables internal circuitry. When V
CC
reaches 2.45 V, the PLL in each devicebegins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by anexternal source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputsremain in the high-impedance state, while the PLL locks to the TCLK.
The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can beaccomplished in one of two ways:•RAPID SYNCHRONIZATION: The serializer has the capability to send specific SYNC patterns consisting ofsix ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables thedeserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNCpatterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid a SYNC1 orSYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent.
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SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
FUNCTIONAL DESCRIPTION (continued)When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clockinformation. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNCpatterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes low.When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie thedeserializer LOCK output directly to SYNC1 or SYNC2.•RANDOM-LOCK SYNCHRONIZATION: The deserializer can attain lock to a data stream without requiringthe serializer to send special SYNC patterns. This allows the SN65LV1212 to operate in open-loopapplications. Equally important is the deserializer's ability to support hot insertion into a running backplane. Inthe open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore, becauselock time varies due to data stream characteristics, the exact lock time cannot be predicted. The primaryconstraint on the random lock time is the initial phase relation between the incoming data and the REFCLKwhen the deserializer powers up.
The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializercould enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitivemultitransition (RMT);see Figure 1 for RMT examples. RMT occurs when more than one low-high transition takesplace per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the datapattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock exists.Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false lock patternchanges. Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock,the RMT pattern does not affect the deserializer state as long as the same data boundary happens each cycle.The deserializer does not go into lock unitil it finds a unique four consecutive cycles of data boundary (stop/startbits) at the same position.
The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutivecycles. Then the desiralizer goes out of lock and hunts for the new data boundary (stop/start bits). In the event ofloss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter ahigh-impedance state. The user's system should monitor the LOCK pin in order to detect a loss ofsynchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable ifreestablishing lock within a specific time is critical. However, the deserializer can lock to random data aspreviously noted.
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Start
Bit
Stop
Bit
DIN0 Held Low and DIN1 Held High
DIN0 DIN1
Start
Bit
Stop
Bit
Start
Bit
Stop
Bit
DIN4 Held Low and DIN5 Held High
DIN4 DIN5
Start
Bit
Stop
Bit
Start
Bit
Stop
Bit
DIN8 Held Low and DIN9 Held High
DIN8 DIN9
Start
Bit
Stop
Bit
DATA TRANSMISSION MODE
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
FUNCTIONAL DESCRIPTION (continued)
Figure 1. RMT Pattern Examples
After initialization and synchronization, the serializer accepts parallel data from inputs D
IN0
-D
IN9
. The serializeruses the TCLK input to latch the incoming data. The TCLK_R/ F pin selects which edge the serializer uses tostrobe incoming data. If either of the SYNC inputs is high for 6 TCLK cycles, the data at D
IN0
-D
IN9
is ignoredregardless of the clock edge selected and 1026 cycles of SYNC pattern are sent.
After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in theregister. The start bit is always high and the stop bit is always low. The start and stop bits function as theembedded clock bits in the serial stream.
The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO±) at12 times the TCLK frequency. For example, if TCLK is 10 MHz, the serial rate is 10 × 12 = 120 Mbps. Becauseonly 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 12 MHz,the useful data rate is 10 × 12 = 120 Mbps. The data source, which provides TCLK, must be in the range of10 MHz to 40 MHz.
The serializer outputs (DO±) can drive point-to-point connections or limited multipoint or multidrop backplanes.The outputs transmit data when the enable pin (DEN) is high, PWRDN is high, and SYNC1 and SYNC2 are low.When DEN is driven low, the serializer output pins enter the high-impedance state.
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POWER DOWN
HIGH-IMPEDANCE MODE
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
FUNCTIONAL DESCRIPTION (continued)Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks tothe embedded clock and uses it to recover the serialized data. R
OUTx
data is valid when LOCK is low, otherwiseR
OUT0
-R
OUT9
is invalid. The R
OUT0
-R
OUT9
data is strobed out by RCLK. The specific RCLK edge polarity to beused is selected by the RCLK_R/ F input. The R
OUT0
-R
OUT9
, LOCK and RCLK outputs can drive a maximum ofthree CMOS input gates (15-pF load, total for all three) with a 40-MHz clock.
When no data transfer is required, the power-down mode can be used. The serializer and deserializer use thepower-down mode, a low-power sleep mode, to reduce power consumption. The deserializer enters power downwhen you drive PWRDN and REN low. The serializer enters power down when the PWRDN is driven low. Inpower down, the PLL stops and the outputs enter a high-impedance state, which disables load current andreduces supply current to the milliampere range. To exit power down, you must drive the PWRDN pin high.
Before valid data exchanges between the serializer and deserializer can resume, you must reinitialize andresynchronize the devices to each other. Initialization of the serializer takes 1026 TCLK cycles. The deserializerinitializes and drives LOCK high until lock to the LVDS clock occurs.
The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output pins(DO+ and DO-) into a high-impedance state. When you drive DEN high, the serializer returns to its previousstate, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/ F). When the REN pinis driven low, the deserializer enters high-impedance mode. Consequently, the receiver output pins(R
OUT0
-R
OUT9
) and RCLK are placed into the high-impedance state. The LOCK output remains active, reflectingthe state of the PLL.
Deserializer Truth Table
INPUTS OUTPUTS
PWRDN REN ROUT[0:9] LOCK
(1)
,
(2)
RCLK
(3)
H H Z H ZH H Active L ActiveL X Z Z ZH L Z Active Z
(1) LOCK output reflects the state of the deserializer with regard to the selected data stream.(2) ROUT and RCLK are 3-stated when LOCK is asserted high.(3) RCLK active indicates the RCLK is running if the deserializer is locked. The timing of RCLK withrespect to ROUT is determined by RCLK_R/ F.
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SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
TERMINAL FUNCTIONS
PIN NAME DESCRIPTION
SERIALIZER
1, 2 SYNC1, SYNC2 LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of the two pins is assertedhigh for 6 cycles of TCLK, the serializer initiates transmission of a minimum 1026 SYNC patterns. If aftercompletion of transmission of 1026 patterns SYNC continues to be asserted, then the transmissioncontinues until SYNC is driven low and if the time SYNC holds > 6 cycles, another 1026 SYNC patterntransmission initiates.3-12 D
IN0
-D
IN9
Parallel LVTTL data inputs13 TCLK_R/ F LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a TCLK rising-edge datastrobe.14 TCLK LVTTL-level reference clock input. The SN65LV1021 accepts a 10-MHz to 40-MHz clock. TCLK strobesparallel data into the input latch and provides a reference frequency to the PLL.15, 16 DGND Digital circuit ground18, 20, 23, AGND Analog circuit ground (PLL and analog circuits)25
17, 26 AV
CC
Analog circuit power supply (PLL and analog circuits)19 DEN LVTTL logic input. Low puts the LVDS serial output into the high-impedance state. High enables serialdata output.21 D
O
- Inverting LVDS differential output22 D
O
+ Noninverting LVDS differential output27, 28 DV
CC
Digital circuit power supply24 PWRDN LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs into the high-impedancestate, putting the device into a low-power mode.
DESERIALIZER
3 REFCLK LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL frequency.15-19, R
OUT0-
R
OUT9
Parallel LVTTL data outputs24-28
2 RCLK_R/ F LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an RCLK rising-edge datastrobe.9 RCLK LVTTL-level output recovered clock. Use RCLK to strobe R
OUTx
.14, 20, 22 DGND Digital circuit ground1, 12, 13 AGND Analog circuit ground (PLL and analog circuits)4, 11 AV
CC
Analog circuit power supply (PLL and analog circuits)8 REN LVTTL logic input. Low places R
OUT0
-R
OUT9
, LOCK, and RCLK in the high-impedance state.5 R
I
+ Serial data input. Noninverting LVDS differential input6 R
I
- Serial data input. Inverting LVDS differential input10 LOCK LVTTL-level output. LOCK goes low when the deserializer PLL locks onto the embedded clock edge.21, 23 DV
CC
Digital circuit power supply7 PWRDN LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a high-impedancestate, putting the device into a low-power mode.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
2.4
VID
2
VID
2
ELECTRICAL CHARACTERISTICS
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
CC
to GND -0.3 V to 4 VLVTTL input voltage -0.3 V to (V
CC
+ 0.3 V)LVTTL output voltage -0.3 V to (V
CC
+ 0.3 V)LVDS receiver input voltage -0.3 V to 3.9 VLVDS driver output voltage -0.3 V to 3.9 VLVDS output short circuit duration ContinuousElectrostatic discharge: HBM up to 6 kVMM up to 200 VJunction temperature 150°CStorage temperature -65°C to 150°CLead temperature (soldering, 4 seconds) 260°CT
A
= 25°C Maximum package power dissipation 1.27 WPackage derating 10.3 mW/°C above 25°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN NOM MAX UNIT
V
CC
(1)
Supply voltage 3 3.3 3.6 VReceiver input voltage range 0 2.4 V
V
CM
Receiver input common mode range V
Supply noise voltage 100 mV
P-P
T
A
Operating free-air temperature -40 25 85 °C
(1) By design, DVCC and AVCC are separated internally and does not matter what the difference is for XDVCC-AVCCX, as long as bothare within 3 V to 3.6 V.
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (see Note
(1)
)
V
IH
High-level input voltage 2 V
CC
VV
IL
Low-level input voltage GND 0.8 VV
CL
Input clamp voltage I
CL
= -18 mA -1.5 VI
IN
Input current (see Note
(2)
) V
IN
= 0 V or 3.6 V -200 ±100 200 µA
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (see Note
(3)
)
V
IH
High-level input voltage 2 V
CC
VV
IL
Low-level input voltage GND 0.8 VV
CL
Input clamp voltage I
CL
= -18 mA -0.62 -1.5 VI
IN
Input current V
IN
= 0 V or 3.6 V -200 200 µAV
OH
High-level output voltage I
OH
= -5 mA 2.2 3 V
CC
VV
OL
Low-level output voltage I
OL
= 5 mA GND 0.25 0.5 VI
OS
Output short-circuit current V
OUT
= 0 V -15 -47 -85 mA
(1) Apply to D
IN0
-D
IN9
, TCLK, PWRDN, TCLK_R/ F, SYNC1, SYNC2, DEN(2) High I
IN
values are due to pull-up and pull-down resistors on the inputs.(3) Apply to input pins PWRDN, RCLK_R/ F, REN, REFCLK; apply to output pins R
OUTx
, RCLK, LOCK
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SERIALIZER TIMING REQUIREMENTS FOR TCLK
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
OZ
High-impedance output current PWRDN or REN = 0.8 V, V
OUT
= 0 V or V
CC
-10 ±1 10 µA
SERIALIZER LVDS DC SPECIFICATIONS (apply to pins DO+ and DO-)
V
OD
Output differential voltage (DO+)-(DO-) 350 400 mV∆V
OD
Output differential voltage unbalance 35 mVR
L
= 27 Ω, See Figure 18V
OS
Offset voltage 1.1 1.2 1.3 V∆V
OS
Offset voltage unbalance 35 mVI
OS
Output short circuit current D0 = 0 V, D
INx
= high, PWRDN and DEN = 2.4 V -10 -90 mAI
OZ
High-impedance output current PWRDN or DEN = 0.8 V, DO = 0 V or V
CC
-10 ±1 10 µAI
OX
Power-off output current V
CC
= 0 V, DO = 0 V or V
CC
-20 ±1 20 µA
DESERIALIZER LVDS DC SPECIFICATIONS (apply to pins RI+ and RI-)
V
TH
Differential threshold high voltage V
CM
= 1.1 V 50 mVV
TL
Differential threshold low voltage -50 mVV
IN
= 2.4 V, V
CC
= 3.6 V or 0 V -10 ±1 15I
IN
Input current µAV
IN
= 0 V, V
CC
= 3.6 V or 0 V -10 ±0.05 10
SERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)
f = 40 MHz 40 50I
CCD
Serializer supply current, worst case R
L
= 27 Ω, See Figure 2 mAf = 10 MHz 20 25I
CCXD
Serializer supply current, power down PWRDN = 0.8 V 200 500 µA
DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)
f = 40 MHz 63 75I
CCR
Deserializer supply current, worst case C
L
= 15 pF, See Figure 3 mAf = 10 MHz 15 35I
CCXR
Deserializer supply current, power down PWRDN = 0.8 V, REN = 0.8 V 0.36 1 mA
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
TCP
Transmit clock period 25 T 100 nst
TCIH
Transmit clock high time 0.4T 0.5T 0.6T nst
TCIL
Transmit clock low time 0.4T 0.5T 0.6T nst
t(CLK)
TCLK input transition time See Figure 6 3 6 nst
JIT
TCLK input jitter 150 ps (RMS)
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SERIALIZER SWITCHING CHARACTERISTICS
tTCP
23
DESERIALIZER TIMING REQUIREMENTS FOR REFCLK
DESERIALIZER SWITCHING CHARACTERISTICS
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
TLH(L)
LVDS low-to-high transition time 0.2 1R
L
= 27 Ω, C
L
= 10 pF to GND, SeeFigure 4t
THL(L)
LVDS high-to-low transition time 0.25 1t
su(DI)
D
IN0
-D
IN9
setup to TCLK 1 0R
L
= 27 Ω, C
L
= 10 pF to GND, SeeFigure 7t
h(D)
D
IN0
-D
IN9
hold from TCLK 6.5 4.5DO± high-to-high impedancet
d(HZ)
2.5 5state delayDO± low-to-high impedance statet
d(LZ)
2.5 5delay
R
L
= 27 Ω, C
L
= 10 pF to GND, SeeFigure 8
nsDO± high-impedancet
d(ZH)
2.5 10state-to-high delayDO± high-impedance state-to-lowt
d(ZL)
2.7 10delayt
w(SP)
SYNC pulse duration 6×t
TCPR
L
= 27 Ω, See Figure 9andFigure 10t
PLD
Serializer PLL lock time 1026×t
TCP
t
d(S)
Serializer delay R
L
= 27 Ω, See Figure 11
t
(BIT)
Bus LVDS bit width R
L
= 27 Ω, C
L
= 10 pF to GND t
CLK
/12
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
RFCP
REFCLK period 25 T 100 nst
RFDC
REFCLK duty cycle 40% 50% 60%t
t(RF)
REFCLK transition time 3 6 nsFrequency tolerance -100 +100 ppm
over recommended operating supply and temperature ranges (unless otherwise specified)
TESTPARAMETER PIN/FREQ MIN TYP MAX UNITCONDITIONS
t
(RCP)
= t
(TCP)t
RCP
Receiver out clock period RCLK 25 100See Figure 11CMOS/TTL low-to-high transitiont
TLH(C)
0.7 2.5R
OUT0
-time
C
L
=15 pF,
R
OUT9
, LOC
nsSee Figure 5CMOS/TTL high-to-low transition
K, RCLKt
THL(C)
1.1 2.5time
10 MHz 2×t
RCP
+ 9 2.833×t
RCP
+ 14Room temperature,t
d(D)
Deserializer delay, See Figure 12
3.3 V
40 MHz 2×t
RCP
+ 6 2.833×t
RCP
+ 10t
su(ROS)
R
OUT0
-R
OUT9
setup data to RCLK 0.4×t
RCP
0.5×t
RCP
nst
(ROH)
R
OUT0
-R
OUT9
hold data to RCLK See Figure 13 RCLK -0.4×t
RCP
-0.5×t
RCP
t
(RDC)
RCLK duty cycle 40% 50% 60%High-to-high impedance statet
d(HZ)
6.7 8delay
Low-to-high impedance statet
d(LZ)
4.6 8R
OUT0
-delay
See Figure 14 R
OUT9
, nsHigh-impedance state-to-high
LOCKt
d(ZH)
5.5 8delay
High-impedance state-to-lowt
d(ZL)
4.8 8delay
9
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TCLK
ODD DIN
EVEN DIN
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
DESERIALIZER SWITCHING CHARACTERISTICS (continued)over recommended operating supply and temperature ranges (unless otherwise specified)
TESTPARAMETER PIN/FREQ MIN TYP MAX UNITCONDITIONS
10 MHz (1024+26)t
RFCPDeserializer PLL lock time fromt
(DSR1)
PWRDN(with SYNCPAT)
40 MHz (1024+26)t
RFCP
µsSee
10 MHz 0.7Deserializer PLL lock time from
Figure 15 ,Figure 1t
(DSR2)
SYNCPAT
40 MHz 0.26, and Note
(1)
High-impedance state-to-hight
d(ZHL)
LOCK 3 nsdelay (power up)
10 MHz 3680See Figure 17 andt
(RNM)
Deserializer noise margin psNote
(2)
40 MHz 1100
(1) t
(DSR1)
represents the time required for the deserializer to register that a lock has occurred upon power up or when leaving thepower-down mode. t
(DSR2)
represents the time required to register that a lock has occurred for the powered up and enabled deserializerwhen the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specifydeserializer PLL performance t
DSR1
and t
DSR2
are specified with REFCLK active and stable and specific conditions of SYNCPATs.(2) t
RNM
represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur.
TIMING DIAGRAMS AND TEST CIRCUITS
Figure 2. Worst-Case Serializer I
CC
Test Pattern
Figure 3. Worst-Case Deserializer I
CC
Test Pattern
10
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80%
20%
80%
20%
tTLH(L)
Vdiff
RL
10 pF
DO+
DO–
10 pF
Vdiff = (DO+) – (DO–)
tTHL(L)
80%
20%
80%
20%
CMOS/TTL Output
15 pF
Deserializer tTLH(C) tTHL(L)
90%
10%
90%
10%
tt(CLK)
TCLK 3 V
0 V
tt(CLK)
DIN [9:0]
tsu(DI)
TCLK
th(DI)
For TCLK_R/F = Low
Setup Hold 1.5 V1.5 V
tTCP
1.5 V 1.5 V 1.5 V
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 4. Serializer LVDS Output Load and Transition Times
Figure 5. Deserializer CMOS/TTL Output Load and Transition Times
Figure 6. Serializer Input Clock Transition Time
Figure 7. Serializer Setup/Hold Times
11
www.ti.com
13.5 Ω
DO+
DO–
Parasitic Package and
Trace Capacitance
DEN
td(HZ)
1.5 V1.5 V
3 V
0 V
50%50% 1.1 V
VOH
DO±
VOL
1.1 V
50%
50%
13.5 Ω
1.1 V
DEN
td(ZH)
td(ZL)
td(LZ)
DO±
TCLK
2 V
1026 Cycles
PWRDN 0.8 V
Output Active
t(PLD)
td(ZH) or td(ZL)
3-State 3-State
1026 Cycles
SYNC Pattern
DEN = High
tw(SP)
SYNC 1.5 V 1.5 V
td(HZ) or td(LZ)
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 8. Serializer High-Impedance-State Test Circuit and Timing
Figure 9. Serializer PLL Lock Time and PWRDN High-Impedance-State Delays
12
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tw(SP)
PWRDN
TCLK
REN
SYNC1
or
SYNC2
DO±DATA SYNC Pattern
tw(SP) Min. T iming Met
TCLK
SYNC1
or
SYNC2
DO±
DATA
SYNC Pattern
DO
Start
Bit D00 – D09 SYMBOL N Stop
Bit
Start
Bit D00 – D09 SYMBOL N–1 Stop
Bit
TCLK
DIN
td(S)
DIN0 – DIN9 SYMBOL N DIN0 – DIN9 SYMBOL N+1
Timing for TCLK_R/F = High
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 10. SYNC Timing Delays
Figure 11. Serializer Delay
13
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RI
Start
Bit D00 – D09 SYMBOL N+2 Stop
Bit 1.2 V
1 V
Start
Bit D00 – D09 SYMBOL N+1 Stop
Bit
Start
Bit D00 – D09 SYMBOL N Stop
Bit
RCLK
ROUT
tDD
ROUT0 – ROUT9 SYMBOL N–1 ROUT0 – ROUT9 SYMBOL N ROUT0 – ROUT9 SYMBOL N+1
Timing for TCLK_R/F = High
ROUT [9:0]
RCLK
RCLK_R/F = High
tROS
Data Valid
Before RCLK 1.5 V1.5 V
tROH
tLow
tHigh
RCLK
RCLK_R/F = Low
tHigh
tLow
Data Valid
After RCLK
7 V(LZ/ZL), Open (HZ/ZH)
REN
td(ZL)
td(LZ)
1.5 V1.5 V
VOH
VOL
VOL + 0.5 V
VOL
ROUT[9:0]
VOH
td(ZH)
td(HZ)
500 Ω
450 Ω
50 Ω
Scope
VOL + 0.5 V
VOH – 0.5 V VOH – 0.5 V
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 12. Deserializer Delay
Figure 13. Deserializer Setup and Hold Times
Figure 14. Deserializer High-Impedance-State Test Circuit and Timing
14
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ROUT[9:0]
REFCLK
2 V
PWRDN 0.8 V
td(ZHL)
DATA
Not Important
3-State
SYNC Patterns
1.5 V
RI±
LOCK 3-State
3-State3-State
RCLK 3-State3-State
SYNC Symbol or DIN[9:0]
RCLK_R/F = Low
REN
td(HZ) or td(LZ)
td(ZH) or td(ZL)
tDSR1
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 15. Receiver LVDS Input Skew Margin
15
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ROUT[9:0]
REFCLK
PWRDN 0.8 V
DATA
Not Important
SYNC Patterns
RI±
LOCK 3-State
3-State3-State
RCLK 3-State3-State
SYNC Symbol or DIN[9:0]
REN
td(HZ) or td(LZ)
td(ZH) or td(ZL)
tDSR2
VCC
3.6 V
3 V
0 V
1.2 V
1 V
tDJIT
tSW: Setup and Hold Time (Internal Data Sampling Window)
tDJIT: Serializer Output Bit Position Jitter That Results From Jitter on TCLK
tRNM: Receiver Noise Margin Time
VTH
RI±VTL
1.2 V
1 V
tDJIT
tRNM tRNM
tSW
Ideal Sampling Position
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 16. Deserilaizer PLL Lock Time From SyncPAT
Figure 17. Receiver LVDS Input Skew Margin
16
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RL
DO+
DO–
10
DIN Parallel-to-Serial
> TCLK
VOD = (DO+) – (DO–)
Differential Output Signal Is Shown as (DO+) – (DO–)
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 18. V
OD
Diagram
17
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LV1021DB ACTIVE SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LV1021DBG4 ACTIVE SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LV1021DBR ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LV1021DBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LV1212DB NRND SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LV1212DBG4 NRND SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LV1212DBR NRND SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LV1212DBRG4 NRND SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LV1021DBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
SN65LV1212DBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LV1021DBR SSOP DB 28 2000 346.0 346.0 33.0
SN65LV1212DBR SSOP DB 28 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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