LTC2309
1
2309fd
BLOCK DIAGRAM
FeAtuRes
AppLICAtIOns
DesCRIptIOn
8-Channel, 12-Bit SAR ADC
with I2C Interface
n Industrial Process Control
n Motor Control
n Accelerometer Measurements
n Battery-Operated Instruments
n Isolated and/or Remote Data Acquisition
n Power Supply Monitoring
Integral Nonlinearity
vs Output Code
n
12-Bit Resolution
n Low Power: 1.5mW at 1ksps, 35µW Sleep Mode
n
14ksps Throughput Rate
n
Low Noise: SNR = 73.4dB
n
Guaranteed No Missing Codes
n Single 5V Supply
n 2-Wire I2C Compatible Serial Interface with Nine
Addresses Plus One Global for Synchronization
n
Fast Conversion Time: 1.3µs
n Internal Reference
n Internal 8-Channel Multiplexer
n Internal Conversion Clock
n Unipolar or Bipolar Input Ranges (Software Selectable)
n Guaranteed Operation from –40°C to 125°C
(TSSOP Package)
n 24-Pin 4mm × 4mm QFN and 20-Pin TSSOP Packages
The LTC
®
2309 is a low noise, low power, 8-channel, 12-bit
successive approximation ADC with an I2C compatible
serial interface. This ADC includes an internal reference
and a fully differential sample-and-hold circuit to reduce
common mode noise. The LTC2309 operates from an
internal clock to achieve a fast 1.3µs conversion time.
The LTC2309 operates from a single 5V supply and
draws just 300µA at a throughput rate of 1ksps. The
ADC enters nap mode when not converting, reducing
the power dissipation.
The LTC2309 is available in both a small 24-pin 4mm ×
4mm QFN and a 20-pin TSSOP package. The internal 2.5V
reference and 8-channel multiplexer further reduce PCB
board space requirements.
The low power consumption and small size make the
LTC2309 ideal for battery-operated and portable applica-
tions, while the 2-wire I2C compatible serial interface makes
this ADC a good match for space-constrained systems.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Easy Drive is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
2309 TA01
I2C
PORT
ANALOG
INPUT
MUX
ANALOG INPUTS
0V TO 4.096V UNIPOLAR
±2.048V BIPOLAR
REFCOMP
INTERNAL
2.5V REF
VDD
5V
GND
LTC2309
0.1µF
12-BIT
SAR ADC
+
–
2.2µF
10µF0.1µF
10µF
VREF
SDA
SCL
AD1
AD0
OUTPUT CODE
0
INL (LSB)
0
0.25
0.50
4096
2309 G01
–0.25
–0.50
–1.00 1024 2048 3072
–0.75
1.00
0.75
LTC2309
2
2309fd
ABsOLute MAxIMuM RAtInGs
(Notes 1, 2)
ORDeR InFORMAtIOn
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2309CUF#PBF LTC2309CUF#TRPBF 2309 24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C
LTC2309IUF#PBF LTC2309IUF#TRPBF 2309 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C
LTC2309CF#PBF LTC2309CF#TRPBF LTC2309F 20-Lead Plastic TSSOP 0°C to 70°C
LTC2309IF#PBF LTC2309IF#TRPBF LTC2309F 20-Lead Plastic TSSOP –40°C to 85°C
LTC2309HF#PBF LTC2309HF#TRPBF LTC2309F 20-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Supply Voltage
VD
D
.......................................................... –0.3V to 6V
Analog Input Voltage (Note 3)
CH0-CH7, COM, VREF
,
REFCOMP .................... (GND – 0.3V) to (VDD + 0.3V)
Digital Input Voltage
(Note 3) ............................ (GND – 0.3V) to (VDD + 0.3V)
Digital Output Voltage ...... (GND – 0.3V) to (VDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2309C ................................................ 0°C to 70°C
LTC2309I .............................................–40°C to 85°C
LTC2309H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
TSSOP .............................................................. 300°C
24
25
23 22 21 20 19
789
TOP VIEW
UF PACKAGE
24-LEAD (4mm s 4mm) PLASTIC QFN
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18
CH3
CH4
CH5
CH6
CH7
COM
GND
SDA
SCL
AD1
AD0
VDD
CH2
CH1
CH0
VDD
GND
GND
VREF
REFCOMP
GND
GND
GND
VDD
TJMAX = 150°C, θJA = 37°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
F PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
REFCOMP
GND
VDD
AD0
AD1
SCL
SDA
GND
GND
VDD
VREF
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
TJMAX = 150°C, θJA = 90°C/W, θJC = 20°C/W
pIn COnFIGuRAtIOn
LTC2309
3
2309fd
COnVeRteR AnD MuLtIpLexeR CHARACteRIstICs
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) l12 Bits
Integral Linearity Error (Note 6) l±0.45 ±1 LSB
Differential Linearity Error l±0.35 ±1 LSB
Bipolar Zero Error (Note 7) l±1 ±8 LSB
Bipolar Zero Error Drift 0.002 LSB/°C
Bipolar Zero Error Match ±0.1 ±3 LSB
Unipolar Zero Error (Note 7) l±0.4 ±6 LSB
Unipolar Zero Error Drift 0.002 LSB/°C
Unipolar Zero Error Match ±0.2 ±1 LSB
Bipolar Full-Scale Error External Reference (Note 8)
REFCOMP = 4.096V
l
l
±0.5
±0.4
±10
±9
LSB
LSB
Bipolar Full-Scale Error Drift External Reference 0.05 LSB/°C
Bipolar Full-Scale Error Match ±0.4 ±3 LSB
Unipolar Full-Scale Error QFN External Reference (Note 8)
TSSOP External Reference (Note 8)
l
l
±0.4
±0.5
±10
±12
LSB
LSB
REFCOMP = 4.096V l±0.3 ±6 LSB
Unipolar Full-Scale Error Drift External Reference 0.05 LSB/°C
Unipolar Full-Scale Error Match ±0.3 ±2 LSB
The l denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4, 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+Absolute Input Range (CH0 to CH7) (Note 9) l–0.05 REFCOMP V
VIN–Absolute Input Range (CH0 to CH7, COM) Unipolar (Note 9)
Bipolar (Note 9)
l
l
–0.05
–0.05
0.25 • REFCOMP
0.75 • REFCOMP
V
V
VIN+ – VIN–Input Differential Voltage Range VIN = VIN+ – VIN– (Unipolar)
VIN = VIN+ – VIN– (Bipolar)
l
l
0 to REFCOMP
±REFCOMP/2
V
V
IIN Analog Input Leakage Current l±1 µA
CIN Analog Input Capacitance Sample Mode
Hold Mode
55
5
pF
pF
CMRR Input Common Mode Rejection Ratio 70 dB
AnALOG Input
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 1kHz l71 73.3 dB
SNR Signal-to-Noise Ratio fIN = 1kHz l71 73.4 dB
THD Total Harmonic Distortion fIN = 1kHz, First 5 Harmonics l–88 –77 dB
SFDR Spurious Free Dynamic Range fIN = 1kHz l79 90 dB
Channel-to-Channel Isolation fIN = 1kHz –109 dB
Full Linear Bandwidth (Note 11) 700 kHz
–3dB Input Linear Bandwidth 25 MHz
Aperture Delay 13 ns
Transient Response Full-Scale Step 240 ns
DYnAMIC ACCuRACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 4, 10)
LTC2309
4
2309fd
pOWeR ReQuIReMents
PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 (QFN)
IOUT = 0 (TSSOP)
l
l
2.47
2.46
2.50
2.50
2.53
2.54
V
V
VREF Output Tempco IOUT = 0 ±25 ppm/°C
VREF Output Impedance –0.1mA ≤ IOUT ≤ 0.1mA 8 kΩ
VREFCOMP Output Voltage IOUT = 0 4.096 V
VREF Line Regulation VDD = 4.75V to 5.25V 0.8 mV/V
InteRnAL ReFeRenCe CHARACteRIstICs
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
I2C Inputs AnD DIGItAL Outputs
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l2.85 V
VIL Low Level Input Voltage l1.5 V
VIHA High Level Input Voltage for Address Pins A1, A0 l4.75 V
VILA Low Level Input Voltage for Address Pins A1, A0 l0.25 V
RINH Resistance from A1, A0, to VDD to Set Chip
Address Bit to 1
l10 kΩ
RINL Resistance from A1, A0 to GND to Set Chip
Address Bit to 0
l10 kΩ
RINF Resistance from A1, A0 to GND or VDD to Set
Chip Address Bit to Float
l2 MΩ
IIDigital Input Current VIN = VDD l–10 10 µA
VHYS Hysteresis of Schmitt Trigger Inputs (Note 9) l0.25 V
VOL Low Level Output Voltage (SDA) I = 3mA l0.4 V
tOF Output Fall Time VH to VIL(MAX) (Note 12) l20 + 0.1CB250 ns
tSP Input Spike Suppression l50 ns
CCAX External Capacitance Load On-Chip Address Pins
(A1, A0) for Valid Float
l10 pF
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l4.75 5 5.25 V
IDD Supply Current 14ksps Sample Rate l2.3 3 mA
Nap Mode SLP Bit = 0, Conversion Done l210 350 µA
Sleep Mode SLP Bit = 1, Conversion Done l7 15 µA
PDPower Dissipation 14ksps Sample Rate l11.5 15 mW
Nap Mode SLP Bit = 0, Conversion Done l1.05 1.75 mW
Sleep Mode SLP Bit = 1, Conversion Done l35 75 µW
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2309
5
2309fd
I2C tIMInG CHARACteRIstICs
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCL SCL Clock Frequency l400 kHz
tHD(SDA) Hold Time (Repeated) START Condition l0.6 µs
tLOW LOW Period of the SCL Pin l1.3 µs
tHIGH HIGH Period of the SCL Pin l0.6 µs
tSU(STA) Set-Up Time for a Repeated START Condition l0.6 µs
tHD(DAT) Data Hold Time l0 0.9 µs
tSU(DAT) Data Set-Up Time l100 ns
trRise Time for SDA/SCL Signals (Note 12) l20 + 0.1CB300 ns
tfFall Time for SDA/SCL Signals (Note 12) l20 + 0.1CB300 ns
tSU(STO) Set-Up Time for STOP Condition l0.6 µs
tBUF Bus Free Time Between a STOP and START Condition l1.3 µs
ADC tIMInG CHARACteRIstICs
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Throughput Rate (Successive Reads) l14 ksps
tCONV Conversion Time (Note 9) l1.3 1.8 µs
tACQ Acquisition Time (Note 9) l240 ns
tREFWAKE REFCOMP Wake-Up Time (Note 13) CREFCOMP = 10µF, CREF = 2.2µF 200 ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above V
DD
,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above V
DD
without latchup.
Note 4: V
DD
= 5V, f
SMPL
= 14ksps internal reference unless otherwise
noted.
Note 5: Linearity, offset and full-scale specifications apply for a
single-ended analog input with respect to COM.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from +0.5LSB
when the output code flickers between 0000 0000 0000 and 0000 0000
0001.
Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 9: Guaranteed by design, not subject to test.
Note 10: All specifications in dB are referred to a full-scale ±2.048V input
with a 2.5V reference voltage.
Note 11: Full linear bandwidth is defined as the full-scale input frequency
at which the SINAD degrades to 60dB or 10 bits of accuracy.
Note 12: C
B
= capacitance of one bus line in pF (10pF ≤ C
B
≤ 400pF).
Note 13: REFCOMP wake-up time is the time required for the REFCOMP
pin to settle within 0.5LSB at 12-bit resolution of its final value after
waking up from SLEEP mode.
LTC2309
6
2309fd
tYpICAL peRFORMAnCe CHARACteRIstICs
Integral Nonlinearity
vs Output Code
1kHz Sine Wave
8192 Point FFT Plot
Supply Current
vs Sampling Frequency Offset Error vs Temperature Full-Scale Error vs Temperature
Supply Current vs Temperature Sleep Current vs Temperature
Analog Input Leakage Current
vs Temperature
TA = 25°C, VDD = 5V, fSMPL = 14ksps, unless otherwise noted.
Differential Nonlinearity
vs Output Code
OUTPUT CODE
0
INL (LSB)
0
0.25
0.50
4096
2309 G01
–0.25
–0.50
–1.00 1024 2048 3072
–0.75
1.00
0.75
OUTPUT CODE
0
DNL (LSB)
0
0.25
0.50
4096
2309 G02
–0.25
–0.50
–1.00 1024 2048 3072
–0.75
1.00
0.75
FREQUENCY (kHz)
0
–140
MAGNITUDE (dB)
–120
–100
–80
0
–40
134 7
2309 G03
–20
–60
256
SNR = 73.4dB
SINAD = 73.3dB
THD = –88dB
SAMPLING FREQUENCY (ksps)
0.1
0
SUPPLY CURRENT (mA)
1.5
2.0
2.5
1 10 100
3209 G04
1.0
0.5
TEMPERATURE (°C)
–50
OFFSET ERROR (LSB)
1.5
25
2309 G05
0
–1.0
–25 0 50
–0.5
–2.0
2.0
1.0
0.5
–0.5
75 100 125
UNIPOLAR
BIPOLAR
TEMPERATURE (°C)
–50 –25
–6
FULL-SCALE ERROR (LSB)
–2
4
050 75
2309 G06
–4
2
0
25 100 125
UNIPOLAR
BIPOLAR
TEMPERATURE (°C)
–50
1.0
SUPPLY CURRENT (mA)
1.2
1.6
1.8
2.0
3.0
2.4
050 75
2309 G07
1.4
2.6
2.8
2.2
–25 25 100 125
TEMPERATURE (°C)
–50
0
LEAKAGE CURRENT (nA)
100
300
400
500
1000
700
050 75
2309 G09
200
800
900
600
–25 25 100 125
CH (ON)
CH (OFF)
TEMPERATURE (°C)
–50 –25
0
SLEEP CURRENT (µA)
4
10
050 75
2309 G08
2
8
6
25 100 125
LTC2309
7
2309fd
pIn FunCtIOns
CH3-CH7 (Pins 1-5): Channel 3 to Channel 7 Analog
Inputs. CH3-CH7 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexer section.
COM (Pin 6): Common Input. This is the reference
point for all single-ended inputs. It must be free of
noise and should be connected to ground for unipolar
conversions and midway between GND and REFCOMP
for bipolar conversions.
VREF (Pin 7): 2.5V Reference Output. Bypass to GND
with a minimum 2.2µF ceramic capacitor. The internal
reference may be overdriven by an external 2.5V refer-
ence at this pin.
REFCOMP (Pin 8): Reference Buffer Output. Bypass
to GND with 10µF and 0.1µF ceramic capacitors in
parallel. Nominal output voltage is 4.096V. The internal
reference buffer driving this pin is disabled by ground-
ing VREF
, allowing REFCOMP to be overdriven by an
external source.
GND (Pins 9-11, 18-20): Ground. All GND pins must
be connected to a solid ground plane.
VDD (Pins 12, 13, 21): 5V Supply. The range of VDD is
4.75V to 5.25V. Bypass VDD to GND with a 10µF ceramic
capacitor in parallel with three 0.1µF ceramic capacitors,
one located as close as possible to each pin.
AD0 (Pin 14): Chip Address Control Pin. This pin is
configured as a three-state (LOW, HIGH, floating) ad-
dress control bit for the device I2C address. See Table 2
for address selection.
AD1 (Pin 15): Chip Address Control Pin. This pin is
configured as a three-state (LOW, HIGH, floating)
address control bit for the device I2C address. See
Table 2 for address selection.
SCL (Pin 16): Serial Clock Pin of the I2C Interface. The
LTC2309 can only act as a slave and the SCL pin only
accepts an external serial clock. Data is shifted into
the SDA pin on the rising edges of the SCL clock and
output through the SDA pin on the falling edges of the
SCL clock.
SDA (Pin 17): Bidirectional Serial Data Line of the I2C
Interface. In transmitter mode (read), the conversion
result is output at the SDA pin, while in receiver mode
(write), the DIN word is input at the SDA pin to con-
figure the ADC. The pin is high impedance during the
data input mode and is an open-drain output (requires
an appropriate pull-up device to VDD) during the data
output mode.
CH0-CH2 (Pins 22-24): Channel 0 to Channel 2 Analog
Inputs. CH0-CH2 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexer section.
Exposed Pad (Pin 25): Ground. Must be soldered
directly to ground plane.
(QFN)
LTC2309
8
2309fd
pIn FunCtIOns
REFCOMP (Pin 1): Reference Buffer Output. Bypass
to GND with 10µF and 0.1µF ceramic capacitors in
parallel. Nominal output voltage is 4.096V. The internal
reference buffer driving this pin is disabled by ground-
ing VREF
, allowing REFCOMP to be overdriven by an
external source.
GND (Pins 2, 8 , 9): Ground. All GND pins must be
connected to a solid ground plane.
VDD (Pins 3, 10): 5V Supply. The range of VDD is 4.75V
to 5.25V. Bypass VDD to GND with a 10µF ceramic ca-
pacitor in parallel with two 0.1µF ceramic capacitors,
one located as close as possible to each pin.
AD0 (Pin 4): Chip Address Control Pin. This pin is con-
figured as a three-state (LOW, HIGH, floating) address
control bit for the device I2C address. See Table 2 for
address selection.
AD1 (Pin 5): Chip Address Control Pin. This pin is
configured as a three-state (LOW, HIGH, floating)
address control bit for the device I2C address. See
Table 2 for address selection.
SCL (Pin 6): Serial Clock Pin of the I2C Interface. The
LTC2309 can only act as a slave and the SCL pin only
accepts an external serial clock. Data is shifted into
the SDA pin on the rising edges of the SCL clock and
output through the SDA pin on the falling edges of the
SCL clock.
SDA (Pin 7): Bidirectional Serial Data Line of the I2C
Interface. In transmitter mode (read), the conversion
result is output at the SDA pin, while in receiver mode
(write), the DIN word is input at the SDA pin to con-
figure the ADC. The pin is high impedance during the
data input mode and is an open-drain output (requires
an appropriate pull-up device to VDD) during the data
output mode.
CH0-CH7 (Pins 11-18): Channel 0 to Channel 7 Analog
Inputs. CH0-CH7 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexer section.
COM (Pin 19): Common Input. This is the reference
point for all single-ended inputs. It must be free of
noise and should be connected to ground for unipolar
conversions and midway between GND and REFCOMP
for bipolar conversions.
VREF (Pin 20): 2.5V Reference Output. Bypass to GND
with a minimum 2.2µF ceramic capacitor. The internal
reference may be overdriven by an external 2.5V refer-
ence at this pin.
(TSSOP)
LTC2309
9
2309fd
FunCtIOnAL BLOCK DIAGRAM
tIMInG DIAGRAM
Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
SDA
SCL
S Sr P S
tHD(SDA)
S = START, Sr = REPEATED START, P = STOP
tHD(DAT)
tSU(STA) tSU(STO)
tSU(DAT)
tLOW tHD(SDA) tSP
tBUF
trtftr
tf
tHIGH 2309 TD
LTC2309
10
2309fd
AppLICAtIOns InFORMAtIOn
Overview
The LTC2309 is a low noise, 8-channel, 12-bit succes-
sive approximation register (SAR) A/D converter with an
I2C compatible serial interface. The LTC2309 includes a
precision internal reference and a configurable 8-chan-
nel analog input multiplexer (MUX). The ADC may be
configured to accept single-ended or differential signals
and can operate in either unipolar or bipolar mode. A
sleep mode option is also provided to further reduce
power during inactive periods.
The LTC2309 communicates through a 2-wire I2C
compatible serial interface. Conversions are initiated
by signaling a STOP condition after the part has been
successfully addressed for a read/write operation. The
device will not acknowledge (NACK) an external request
until the conversion is finished. After a conversion is
finished, the device is ready to accept a read/write
request. Once the LTC2309 is addressed for a read
operation, the device begins outputting the conver-
sion result under the control of the serial clock (SCL).
There is no latency in the conversion result. There are
12 bits of output data followed by 4 trailing zeros. Data
is updated on the falling edges of SCL, allowing the
user to reliably latch data on the rising edge of SCL. A
write operation may follow the read operation by using
a repeat START or a STOP condition may be given to
start a new conversion. By selecting a write operation,
the ADC can be programmed with a 6-bit DIN word. The
DIN word configures the MUX and programs various
modes of operation of the ADC.
During a conversion, the internal 12-bit capacitive
charge redistribution DAC output is sequenced through
a successive approximation algorithm by the SAR start-
ing from the most significant bit (MSB) to the least
significant bit (LSB). The sampled input is successively
compared with binary weighted charges supplied by
the capacitive DAC using a differential comparator. At
the end of a conversion, the DAC output balances the
analog input. The SAR contents (a 12-bit data word)
that represent the sampled analog input are loaded into
12 output latches that allow the data to be shifted out
via the I2C interface.
Programming the LTC2309
The various modes of operation of the LTC2309 are
programmed by a 6-bit DIN word. The SDI input data
bits are loaded on the rising edge of SCL during a write
operation, with the S/D bit loaded on the first rising edge
and the SLP bit on the sixth rising edge (see Figure 8b
in the I2C Interface section). The input data word is
defined as follows:
S/D O/S S1 S0 UNI SLP
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
S1 = CHANNEL SELECT BIT 1
S0 = CHANNEL SELECT BIT 0
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
Analog Input Multiplexer
The analog input MUX is programmed by the S/D,
O/S, S1 and S0 bits of the DIN word. Table 1 lists the
MUX configurations for all combinations of the con-
figuration bits. Figure 1a shows several possible MUX
configurations and Figure 1b shows how the MUX can
be reconfigured from one conversion to the next.
Driving the Analog Inputs
The analog inputs of the LTC2309 are easy to drive.
Each of the analog inputs can be used as a single-ended
input relative to the COM pin (CH0-COM, CH1-COM,
etc.) or in differential input pairs (CH0 and CH1, CH2
and CH3, CH4 and CH5, CH6 and CH7). Figure 2 shows
how to drive COM for single-ended inputs in unipolar
and bipolar modes. Regardless of the MUX configura-
tion, the “+” and “–” inputs are sampled at the same
instant. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection
of the sample-and-hold circuit. The inputs draw only
one small current spike while charging the sample-and-
hold capacitors during the acquire mode. In conversion
LTC2309
11
2309fd
AppLICAtIOns InFORMAtIOn
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM (–)
8 Single-Ended
+
+
+
+
+
+
+
4 Differential
+(–)+
+(–)
+(–)
+(–)
–(+)
–(+)
–(+)
–(+)
COM (–)
Combinations of Differential
and Single-Ended
+
+
+
+
+
+
–
–
{
{
{
{
{
{
2309 F01a
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Table 1. Channel Configuration
S/D O/S S1 S0 0 1 2 3 4 5 6 7 COM
0 0 0 0 + –
0 0 0 1 + –
0 0 1 0 + –
0 0 1 1 + –
0 1 0 0 – +
0 1 0 1 – +
0 1 1 0 – +
0 1 1 1 – +
1 0 0 0 + –
1 0 0 1 + –
1 0 1 0 + –
1 0 1 1 + –
1 1 0 0 + –
1 1 0 1 + –
1 1 1 0 + –
1 1 1 1 + –
COM
(UNUSED) COM (–)
1st Conversion 2nd Conversion
+
–
+
–
+
–
+
+
{
{
{
{
CH2
CH3
CH4
CH5
CH2
CH3
CH4
CH5
2328 F01b
COM COM
REFCOMP/2
Unipolar Mode Bipolar Mode
2328 F02
+
–
Figure 1a. Example of MUX Configurations
Figure 1b. Changing the MUX Assignments “On the Fly”
Figure 2. Driving COM in Unipolar and Bipolar Modes
mode, the analog inputs draw only a small leakage cur-
rent. If the source impedance of the driving circuit is
low, the ADC inputs can be driven directly. Otherwise,
more acquisition time should be allowed for a source
with higher impedance.
Input Filtering
The noise and distortion of the input amplifier and
other circuitry must be considered since they will add
to the ADC noise and distortion. Therefore, noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient
for many applications.
The analog inputs of the LTC2309 can be modeled as
a 55pF capacitor (CIN) in series with a 100Ω resistor
(RON), as shown in Figure 3a. CIN gets switched to the
selected input once during each conversion. Large filter
RC time constants will slow the settling of the inputs.
It is important that the overall RC time constants be
short enough to allow the analog inputs to completely
settle to 12-bit resolution within the acquisition time
(tACQ) if DC accuracy is important.
LTC2309
12
2309fd
AppLICAtIOns InFORMAtIOn
When using a filter with a large CFILTER value (e.g. 1µF),
the inputs do not completely settle and the capacitive
input switching currents are averaged into a net DC
current (IDC). In this case, the analog input can be mod-
eled by an equivalent resistance (REQ = 1/(fSMPL • CIN))
in series with an ideal voltage source (VREFCOMP/2), as
shown in Figure 3b. The magnitude of the DC current
is then approximately IDC = (VIN – VREFCOMP/2)/REQ,
which is roughly proportional to VIN. To prevent large
DC drops across the resistor RFILTER, a filter with a small
resistor and large capacitor should be chosen. When
running at the maximum throughput rate of 14ksps,
the input current equals 1.5µA at VIN = 4.096V, which
amounts to a full-scale error of 0.5LSB when using a
filter resistor (RFILTER) of 333Ω. Applications requiring
lower sample rates can tolerate a larger filter resistor
for the same amount of full-scale error.
self heating and from damage that may occur during
soldering. Metal film surface mount resistors are much
less susceptible to both problems.
Dynamic Performance
Fast Fourier Transform (FFT) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the A/D output. The output is
band-limited to frequencies from above DC and below
half the sampling frequency. Figure 5 shows a typical
SINAD of 73.3dB with a 14kHz sampling rate and a
1kHz input. An SNR of 73.4dB can be achieved with
the LTC2309.
VIN
INPUT
CH0-CH7 RON
100Ω
CIN
55pF
CFILTER
RSOURCE
2309 F03a
LTC2309
Figure 3a. Analog Input Equivalent Circuit
VIN
INPUT
CH0-CH7
REQ
1/(fSMPL • CIN)
VREFCOMP/2
CFILTER
RFILTER IDC
2309 F03b
LTC2309
+
–
Figure 3b. Analog Input Equivalent
Circuit for Large Filter Capacitances
Figures 4a and 4b show examples of input filtering for
single-ended and differential inputs. For the single-
ended case in Figure 4a, a 50Ω source resistor and a
2000pF capacitor to ground on the input will limit the
input bandwidth to 1.6MHz. High quality capacitors and
resistors should be used in the RC filter since these
components can add distortion. NPO and silver mica
type dielectric capacitors have excellent linearity. Carbon
surface mount resistors can generate distortion from
2309 F04a
CH0
COM
LTC2309
REFCOMP
2000pF
0.1µF 10µF
50Ω
ANALOG
INPUT
Figure 4a. Optional RC Input Filtering for Single-Ended Input
1000pF
2309 F04b
CH0
CH1
LTC2309
REFCOMP
1000pF
1000pF
0.1µF 10µF
50Ω
50Ω
DIFFERENTIAL
ANALOG
INPUTS
Figure 4b. Optional RC Input Filtering for Differential Inputs
LTC2309
13
2309fd
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the
RMS sum of all harmonics of the input signal to the
fundamental itself. The out-of-band harmonics alias into
the frequency band between DC and half the sampling
frequency (fSMPL/2). THD is expressed as:
THD V V V V
V
N
=
+ + +
20 223242 2
1
log ...
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Internal Reference
The LTC2309 has an on-chip, temperature compen-
sated bandgap reference that is factory trimmed to
2.5V (Refer to Figure 6a). It is internally connected to a
reference amplifier and is available at VREF . VREF should
be bypassed to GND with a 2.2μF ceramic capacitor to
minimize noise. An 8k resistor is in series with the output
so that it can be easily overdriven by an external refer-
ence if more accuracy and/or lower drift are required,
as shown in Figure 6b. The reference amplifier gains
the VREF voltage by 1.638 to 4.096V at REFCOMP. To
compensate the reference amplifier, bypass REFCOMP
with a 10μF ceramic capacitor in parallel with a 0.1μF
ceramic capacitor for best noise performance. The
internal reference buffer can also be overdriven from
1V to VDD, as shown in Figure 6c. To do so, VREF must
be grounded to disable the reference buffer.
AppLICAtIOns InFORMAtIOn
Figure 5. 1kHz Sine Wave 8192 Point FFT Plot
R2
R3
REFERENCE
AMP
0.1µF
10µF
2.2µF
REFCOMP
GND
VREF
R1
8k
2.5V
4.096V
LTC2309
2309 F06a
BANDGAP
REFERENCE
Figure 6a. LTC2309 Reference Circuit
0.1µF
10µF
2309 F06b
LT1790A-2.5
VOUT
VIN
5V
VREF
LTC2309
GND
REFCOMP
2.2µF
0.1µF
Figure 6b. Using the LT
®
1790A-2.5 as an External Reference
FREQUENCY (kHz)
0
–140
MAGNITUDE (dB)
–120
–100
–80
0
–40
134 7
2309 G03
–20
–60
256
SNR = 73.4dB
SINAD = 73.3dB
THD = –88dB
Figure 6c. Overdriving REFCOMP Using the LT1790A-4.096
0.1µF
0.1µF
10µF
2309 F06c
LT1790A-4.096
VOUT
VIN
5V
VREF
LTC2309
GND
REFCOMP
LTC2309
14
2309fd
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieve a typical conversion time (tCONV) of 1.3μs and
a maximum conversion time of 1.8μs over the full
operating temperature range.
I2C Interface
The LTC2309 communicates through an I2C interface.
The I2C interface is a 2-wire open-drain interface sup-
porting multiple devices and multiple masters on a
single bus. The connected devices can only pull the
serial data line (SDA) LOW and can never drive it HIGH.
SDA is required to be externally connected to the sup-
ply through a pull-up resistor. When the data line is not
being driven LOW, it is HIGH. Data on the I2C bus can
be transferred at rates up to 100kbits/s in the standard
mode and up to 400kbits/s in the fast mode. The VDD
power should not be removed from the LTC2309 when
the I2C bus is active to avoid loading the I2C bus lines
through the internal ESD protection diodes.
Each device on the I2C bus is recognized by a unique
address stored in the device and can only operate either
as a transmitter or receiver, depending on the function
of the device. A device can also be considered as a
master or a slave when performing data transfers. A
master is the device which initiates a data transfer on
the bus and generates the clock signals to permit the
transfer. Devices addressed by the master are consid-
ered slaves.
The LTC2309 can only be addressed as a slave (see
Table 2). Once addressed, it can receive configuration
bits (DIN word) or transmit the last conversion result. The
serial clock line (SCL) is always an input to the LTC2309
and the serial data line (SDA) is bidirectional. The device
supports the standard mode and the fast mode for data
transfer speeds up to 400kbits/s (see the Timing Diagram
section for definition of the I2C timing).
The START and STOP Conditions
Referring to Figure 7, a START (S) condition is gener-
ated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The bus is considered to be busy after the
START condition. When the data transfer is finished, a
STOP (P) condition is generated by transitioning SDA
from LOW to HIGH while SCL is HIGH. The bus is free
after a STOP condition is generated. START and STOP
conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated
START (Sr) is generated instead of a STOP condition.
The repeated START timing is functionally identical to
the START and is used for writing and reading from the
device before the initiation of a new conversion.
AppLICAtIOns InFORMAtIOn
S
START Condition STOP Condition
P
2309 F07
SDA
SCL
SDA
SCL
Figure 7. Timing Diagrams of START and STOP Conditions
Data Transferring
After the START condition, the I2C bus is busy and
data transfer can begin between the master and the
addressed slave. Data is transferred over the bus in
groups of nine bits, one byte followed by one ac-
knowledge (ACK) bit. The master releases the SDA
line during the ninth SCL clock cycle. The slave device
can issue an ACK by pulling SDA LOW or issue a Not
Acknowledge (NACK) by leaving the SDA line high
impedance (the external pull-up resistor will hold the
line high). Change of data only occurs while the SCL
line is LOW.
Data Format
After a START condition, the master sends a 7-bit
address followed by a read/write (R/W) bit. The R/W
bit is 1 for a read request and 0 for a write request.
If the 7-bit address matches one of the LTC2309’s
9 pin-selectable addresses, the ADC is selected. When
LTC2309
15
2309fd
AppLICAtIOns InFORMAtIOn
the ADC is addressed during a conversion, it will not
acknowledge R/W requests and will issue a NACK by
leaving the SDA line HIGH. If the conversion is com-
plete, the LTC2309 issues an ACK by pulling the SDA
line LOW. The LTC2309 has two registers. The 12-bit
wide output register contains the last conversion result.
The 6-bit wide input register configures the input MUX
and the operating mode of the ADC.
Output Data Format
The output register contains the last conversion result.
After each conversion is completed, the device auto-
matically enters either nap or sleep mode depending
on the setting of the SLP bit (see Nap Mode and Sleep
Mode sections). When the LTC2309 is addressed for
a read operation, it acknowledges by pulling SDA
LOW and acts as a transmitter. The master/receiver
can read up to two bytes from the LTC2309. After a
complete read operation of 2 bytes, a STOP condition
is needed to initiate a new conversion. The device will
NACK subsequent read operations while a conversion
is being performed.
The data output stream is 16 bits long and is shifted
out on the falling edges of SCL (see Figure 8a). The
first bit is the MSB and the 12th bit is the LSB of the
conversion result. The remaining four bits are zero.
Figures 14 and 15 are the transfer characteristics for
the bipolar and unipolar modes. Data is output on the
SDA line in 2’s complement format for bipolar readings
or in straight binary for unipolar readings.
1 2
A6SDA
START BY
MASTER
ACK BY
ADC
ACK BY
MASTER
NACK BY
MASTER
STOP
BY MASTER
CONVERSION
INITIATED
SCL
SCL
(CONTINUED)
A5 A4 A3 A2 A1 A0 R/W
3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
2309 F08a
B11 B10
READ 1 BYTE
B9 B8 B7
MOST SIGNIFICANT DATA BYTE
B6 B5 B4
• • •
• • •
SDA
(CONTINUED) • • •
• • •
B3 B2 B1 B0
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
ADDRESS FRAME
Figure 8a. Timing Diagram for Reading from the LTC2309
LTC2309
16
2309fd
Input Data Format
When the LTC2309 is addressed for a write operation,
it acknowledges by pulling SDA LOW during the LOW
period before the 9th cycle and acts as a receiver. The
master/transmitter can then send 1 byte to program the
device. The input byte consists of the 6-bit DIN word
followed by two bits that are ignored by the ADC and
are considered don’t cares (X) (see Figure 8b). The
input bits are latched on the rising edge of SCL during
the write operation.
After power-up, the ADC initiates an internal reset
cycle which sets the DIN word to all 0s (S/D = O/S =
S0 = S1 = UNI = SLP = 0). A write operation may be
performed if the default state of the ADC’s configuration
is not desired. Otherwise, the ADC must be properly
addressed and followed by a STOP condition to initiate
a conversion.
Initiating a New Conversion
The LTC2309 awakens from either nap or sleep when
properly addressed for a read/write operation. A STOP
command may then be issued after performing the
read/write operation to trigger a new conversion.
Issuing a STOP command after the 8th SCL clock pulse
of the address frame and before the completion of a
Table 2. Address Assignment
AD1 AD0 ADDRESS
LOW LOW 0001000
LOW Float 0001001
LOW HIGH 0001010
Float HIGH 0001011
Float Float 0011000
Float LOW 0011001
HIGH LOW 0011010
HIGH Float 0011011
HIGH HIGH 0101000
1 2
A6SDA
START BY
MASTER
ACK BY
ADC
ACK BY
ADC
CONVERSION
INITIATED
STOP BY
MASTER
SCL
A5 A4 A3 A2 A1 A0 R/W
3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
2309 F08b
S/D O/S
WRITE 1 BYTE
S1 S0 UNI
DIN WORD
SLP X X
ADDRESS FRAME
Figure 8b. Timing Diagram for Writing to the LTC2309
AppLICAtIOns InFORMAtIOn
read/write operation will also initiate new conversion,
but the output result may not be valid due to lack of
adequate acquisition time (see Acquisition section).
LTC2309 Address
The LTC2309 has two address pins (AD0 and AD1) that
may be tied HIGH, LOW, or left floating to enable one
of 9 possible addresses (see Table 2).
In addition to the configurable addresses listed in
Table 2, the LTC2309 also contains a global address
(1101011) which may be used for synchronizing mul-
tiple LTC2309s or other I2C LTC230X SAR ADCs (see
Synchronizing Multiple LTC2309s with Global Address
Call section).
LTC2309
17
2309fd
AppLICAtIOns InFORMAtIOn
ates a NACK signal indicating the conversion cycle is
in progress.
Continuous Read/Write
Once the conversion cycle is complete, the LTC2309
can be written to and then read from using the repeated
START (Sr) command. Figure 10 shows a cycle which
begins with a data write, a repeated START, followed
by a read and concluded with a STOP command. After
all 16 bits are read out, a conversion may be initiated
by issuing a STOP command. The following conver-
sion will be performed using the newly programmed
data.
S
CONVERSION NAP DATA OUTPUT CONVERSION CONVERSIONNAP DATA
OUTPUT
R ACK READ7-BIT ADDRESS P S R ACK
2309 F09
READ7-BIT ADDRESS P
Figure 9. Consecutive Reading with the Same Configuration
Continuous Read
In applications where the same input channel is sampled
each cycle, conversions can be continuously performed
and read without a write cycle (see Figure 9). The DIN
word remains unchanged from the last value written
into the device. If the device has not been written to
since power-up, the DIN word defaults to all 0s (S/D =
O/S = S0 = S1 = UNI = SLP = 0). At the end of a read
operation, a STOP condition may be given to start a new
conversion. At the conclusion of the conversion cycle,
the next result may be read using the method described
above. If the conversion cycle is not concluded and a
valid address selects the device, the LTC2309 gener-
S
CONVERSION NAP DATA INPUT ADDRESS CONVERSIONDATA
OUTPUT
WACK WRITE7-BIT ADDRESS Sr R ACK
2309 F10
READ7-BIT ADDRESS P
Figure 10. Write, Read, START Conversion
LTC2309
18
2309fd
AppLICAtIOns InFORMAtIOn
Synchronizing Multiple LTC2309s with a Global
Address Call
In applications where several LTC2309s or other I2C SAR
ADCs from Linear Technology Corporation are used on
the same I2C bus, all converters can be synchronized
through the use of a global address call. Prior to issu-
ing the global address call, all converters must have
completed a conversion cycle. The master then issues
a START, followed by the global address 1101011, and
a write request. All converters will be selected and ac-
knowledge the request. The master then sends a write
byte (optional) followed by the STOP command. This will
update the channel selection (optional) and simultane-
ously initiate a conversion for all ADCs on the bus (see
Figure 11). In order to synchronize multiple converters
without changing the channel, a STOP command may
be issued after acknowledgement of the global write
command. Global read commands are not allowed and
the converters will NACK a global read request.
Nap Mode
The ADC enters nap mode after a conversion is com-
plete (tCONV) if the SLP bit is set to a logic 0. The sup-
ply current decreases to 210μA in nap mode between
conversions, thereby reducing the average power
dissipation as the sample rate decreases. For example,
the LTC2309 draws an average of 300µA at a 1ksps
sampling rate. The LTC2309 keeps only the reference
(VREF) and reference buffer (REFCOMP) circuitry active
when in nap mode.
Sleep Mode
The ADC enters sleep mode after a conversion is com-
plete (tCONV) if the SLP bit is set to a logic 1. The ADC
draws only 7µA in sleep mode, provided that none of
the digital inputs are switching. When the LTC2309 is
properly addressed, the ADC is released from sleep mode
and requires 200ms (tREFWAKE) to wake up and charge
the respective 2.2μF and 10μF bypass capacitors on the
VREF and REFCOMP pins. A new conversion should not
be initiated before this time, as shown in Figure 12.
S
SDA
SCL
CONVERSION NAP
LTC2309
DATA OUTPUT CONVERSION OF ALL LTC2309s
WACK WRITE (OPTIONAL)GLOBAL ADDRESS P
LTC2309 LTC2309
2309 F11
Figure 11. Synchronous Multiple LTC2309s with a Global Address Call
S
CONVERSION SLEEP tREFWAKE CONVERSION
R/WACK7-BIT ADDRESS P
2309 F12
Figure 12. Exiting Sleep Mode and Starting a New Conversion
LTC2309
19
2309fd
AppLICAtIOns InFORMAtIOn
Acquisition
The LTC2309 begins acquiring the input signal at dif-
ferent instances depending on whether a read or write
operation is being performed. If a read operation is
being performed, acquisition of the input signal begins
on the rising edge of the 9th clock pulse following the
address frame, as shown in Figure 13a.
If a write operation is being performed, acquisition of
the input signal begins on the falling edge of the sixth
clock cycle after the DIN word has been shifted in, as
shown in Figure 13b. The LTC2309 will acquire the
signal from the input channel that was most recently
programmed by the DIN word. A minimum of 240ns is
required to acquire the input signal before initiating a
new conversion.
1 2
A6SDA
SCL
A5 A4 A3 A2 A1 A0 R/W
3 4 5 6 7 8 9 1 2
B11
ACQUISITION BEGINS
tACQ
2309 F13a
B10
1 2
A2 A1 A0 R/WSDA
SCL
S/D O/S S1 S0 UNI X X
3 4 55 6 7 8 9 6 7 8 9
ACQUISITION BEGINS
tACQ 2309 F13b
SLP
Figure 13a. Timing Diagram Showing Acquisition During a Read Operation
Figure 13b. Timing Diagram Showing Acquisition During a Write Operation
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
2309 F14
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 – 1LSB–FS/2
FS = 4.096V
1LSB = FS/212
1LSB = 1mV
INPUT VOLTAGE (V)
OUTPUT CODE
2309 F15
111...111
111...110
100...001
100...000
000...000
000...001
011...110
011...111
FS – 1LSB0V
UNIPOLAR
ZERO
FS = 4.096V
1LSB = FS/212
1LSB = 1mV
Figure 14. Bipolar Transfer Characteristics (2’s Complement) Figure 15. Unipolar Transfer Characteristics (Straight Binary)
LTC2309
20
2309fd
AppLICAtIOns InFORMAtIOn
Figure 16a. Top Silkscreen
2309 F16a
Board Layout and Bypassing
To obtain the best performance, a printed circuit board with
a solid ground plane is required. Layout for the printed
board should ensure digital and analog signal lines are
separated as much as possible. Care should be taken not
to run any digital signals alongside an analog signal. All
analog inputs should be shielded by GND. VREF
, REFCOMP
and VDD should be bypassed to the ground plane as close
to the pin as possible. Maintaining a low impedance path
for the common return of these bypass capacitors is
essential to the low noise operation of the ADC. These
traces should be as wide as possible. See Figures 16a-e
for a suggested layout.
LTC2309
21
2309fd
2309 F16b
Figure 16b. Layer 1 Component Side
AppLICAtIOns InFORMAtIOn
Figure 16c. Layer 2 Ground Plane
2309 F16c
LTC2309
22
2309fd
AppLICAtIOns InFORMAtIOn
Figure 16d. Layer 3 Power Plane
2309 F16d
Figure 16e. Layer Back Solder Side
2309 F16e
LTC2309
23
2309fd
pACKAGe DesCRIptIOn
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
2423
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.45 ± 0.05
(4 SIDES)
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 s 45° CHAMFER
LTC2309
24
2309fd
F Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1650)
F20 TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50**
(.169 – .177)
1 3 4 5678 9 10
111214 13
6.40 – 6.60*
(.252 – .260)
20 19 18 17 16 15
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
6.40
(.252)
BSC
0.19 – 0.30
(.0075 – .0118)
TYP
2
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
RECOMMENDED SOLDER PAD LAYOUT
0.45 ±0.05 0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
pACKAGe DesCRIptIOn
LTC2309
25
2309fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ReVIsIOn HIstORY
REV DATE DESCRIPTION PAGE NUMBER
D 7/10 Revised Block Diagram 1
Changed AVDD and DVDD pins to VDD only 2, 4-9, 20
Revised Note 2 5
Consolidated AVDD and DVDD into VDD and revised VREF and REFCOMP pin descriptions in Pin Functions section 7, 8
Revised Figures 6b and 6c and Internal Reference paragraph, and added text to I2C Interface in Applications
Information section
13, 14
Changed NAK to NACK in Figure 8a 15
Revised Typical Application 26
(Revision history begins at Rev D)
LTC2309
26
2309fd
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2008
LT 0710 REV D • PRINTED IN USA
ReLAteD pARts
tYpICAL AppLICAtIOn
PART NUMBER DESCRIPTION COMMENTS
LTC1417 14-Bit, 400ksps Serial ADC 20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
LTC1468/LTC1469 Single/Dual 90MHz, 22V/µs, 16-Bit Accurate
Op Amps
Low Input Offset: 75µV/125µV
LTC1609 16-Bit, 200ksps Serial ADC 65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
LTC1790 Micropower Low Dropout Reference 60µA Supply Current, 10ppm/°C, SOT-23 Package
LTC1850/LTC1851 10-Bit/12-Bit, 8-Channel, 1.25Msps ADCs Parallel Output, Programmable MUX and Sequencer, 5V Supply
LTC1852/LTC1853 10-Bit/12-Bit, 8-Channel, 400ksps ADCs Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
LTC1860/LTC1861 12-Bit, 1-/2-Channel 250ksps ADCs in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
LTC1860L/LTC1861L 3V, 12-bit, 1-/2-Channel 150ksps ADCs 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
LTC1863/LTC1867 12-/16-Bit, 8-Channel 200ksps ADCs 6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
LTC1863L/LTC1867L 3V, 12-/16-bit, 8-Channel 175ksps ADCs 2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
LTC1864/LTC1865 16-Bit, 1-/2-Channel 250ksps ADCs in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADCs in MSOP 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
LTC2302/LTC2306 12-Bit, 1-/2-Channel 500ksps SPI ADCs in
3mm × 3mm DFN
14mW at 500ksps, Single 5V Supply, Software Compatible with LTC2308
LTC2308 12-Bit, 8-Channel 500ksps SPI ADC 5V, Internal Reference, 4mm × 4mm QFN Package, Software Compatible with
LTC2302/LTC2306
LTC2453 Easy-to-Use, Ultratiny 16-Bit I2C Delta Sigma ADC 2LSB INL, 50nA Sleep Current, 60Hz Output Rate, 3mm × 2mm DFN Package
LTC2487/LTC2489/
LTC2493
2-/4-Channel Easy Drive™ I2C Delta Sigma ADCs 16-/24 Bits, PGA and Temperature Sensor, 15Hz Output Rate, 4mm × 3mm
DFN Packages
LTC2495/LTC2497/
LTC2499
8-/16-Channel Easy Drive I2C Delta Sigma ADCs 16-/24-Bits, PGA and Temperature Sensor, 15Hz Output Rate, 5mm × 7mm
QFN Packages
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
2309 TA02
I2C
PORT
ANALOG
INPUT
MUX
REFCOMP
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC)
INTERNAL
2.5V REF
VDD
5V
10V
–10V
±10V
INPUT
SIGNAL
GND
LTC2309
0.1µF
12-BIT
SAR ADC
+
–
2.2µF
10µF0.1µF
10µF
1µF
0.1µF
47pF
7
4 5
6
8
1
9
10
100Ω
450k
LT1790-2.5
5V
IN OUT
GND
50k
150k
450k
150k
450k 4pF
VREF
SDA
SCL
1.7k 1.7k
AD1 AD0
CH0
450k
4pF
3
2
50k
–
+
LT1991
Driving the LTC2309 with ±10V Input Signals Using a Precision Attenuator