ZL38090 Preliminary Data Sheet Revision 2.0
ZL38090 Preliminary Data Sheet
Designed for USB Headsets and Microphones
Description
The ZL38090 is part of Microsemi's Timberwolf audio
processor family of products that features Microsemi’s
innovative AcuEdge™ firmware, which uses a set of
highly-complex and integrated algorithms designed for
audio enhancement. These algorithms are incorporated
into a powerful DSP platform that allows the user to
extract intelligible information from adverse audio
environments.
The Microsemi AcuEdge Firmware for the ZL38090
device is specifically designed for USB headset and USB
microphones. The ZLS38090 AcuEdge firmware is
royalty-free and provides an advanced audio feature set
including beam forming (BF), noise reduction (NR),
equalizers (EQ), and a compressor, limiter and expander
(CLE) to improve both the intelligibility and subjective
quality of voice in harsh acoustic environments.
Microsemi offers additional tools to speed up the product
development cycle. The MiTuner™ ZLS38508 or
ZLS38508LITE GUI software packages allow a user to
interactively configure the ZL38090 device. The optional
ZLE38470BADA Automatic Tuning Kit provides
automatic tuning and easy control for manual fine tuning
adjustments.
Ordering Information
• ZL38090LDF1: 64-pin QFN (9×9) Package (Tape &
Reel)
• ZL38090LDG1: 64-pin QFN (9×9) Package (Tray)
• ZL38090UGB2: 56-ball WLCSP (3.1×3.1) Package
(Tape & Reel)
Note:These packages meet RoHS 2 Directive
2011/65/EU of the European Council to minimize
the environmental impact of electrical equipment.
Applications
• USB Beamforming Microphones
• USB to analog bridge/ USB to I2S bridge
• USB Headsets/headset dongles
• USB Speakerphones
• USB Speakers
Figure 1 • ZL38090 Block Diagram
Timberwolf™ ZL38090
Digital
Mic
Input
DAC
(2)
PLL
Microsemi Audio Processor
Hardware
x282MHz DSP Core
xIntegrated Memory
xHardware Accelerators
Digital
M
icrophone
Interface
(PDM)
Analog
Output
AcuEdge™ Technology Firmware Modes
xBeamforming
xNoise Reduction
xEQ
xCLE
Cross
Point
switch
Cross
Point
switch
I
2
S
TDM
Digital Audio
Interface
USB
USB Audio
V-Com
SPI/I
2
C
Slave
Optional Host
Processor
Port
GPIO
Control
Buttons or
Status LEDs
SPI
Master
Optional
External FLASH
Port
UART
Debug Port
ZL38090 Preliminary Data Sheet Revision 2.0
Microsemi AcuEdge™ Technology
ZL38090 Firmware
• Supports 1 stereo headset with play and record or
playback-only functions
• Microphone Beamforming (2 microphones)
• Advanced Microphone noise reduction
• Standard Dynamic Range Compressor
• Limiter
• Expander
• Send and receive path 8-band parametric
equalizers
• 8 kHz/16 kHz/24 kHz/48 kHz audio streaming
• 4 Defined Function GPIOs for Volume Up/Down,
Mute Mic, and Hook-Switch On/Off
• 4 Defined Function PWM outputs for LED control
• 4 additional GPIOs capable of key input and PWM
LED control
• USB Audio Class Device v1.0 compliant
• Adaptive mode for playback, Asynchronous mode
for record
• USB Audio Class clock modes
• Common HID controls for volume, hookswitch
control and mute
• USB port that enumerates with:
• EP0 (Control)
• 2 endpoints for Microphones and Speakers
(both stereo)
• 1 interrupt endpoint (for HID Status Reporting)
• 2 optional endpoints for Virtual Com support
• Skype/Lync Compatible
• Standalone USB device (additional host processor
not required for headphone applications)
Hardware Features
• DSP with Voice Hardware Accelerators
• Dual ΔΣ 16-bit digital-to-analog converters (DAC)
• Sampling up to 48 kHz and internal output
drivers
• Headphone amplifiers capable of 32mW output
drive power into 16 ohms
• 2 Digital Microphone input supporting up to 4
Microphones
• 1 TDM / Inter-IC Sound (I2S) port
• SPI or I2C Slave port for host processor interface
• Master SPI port for optional serial Flash interface
• Device boots from either Flash or SPI
• General Purpose Input/Output pins (GPIOs)
• General purpose UART port for debug
The MiTuner™ Automatic Tuning
Kit and ZLS38508 MiTuner GUI
Microsemi's Automatic Tuning Kit option includes:
• Audio Interface Box hardware
• Microphone and Speaker
• ZLS38508 MiTuner GUI software
• Allows tuning of Microsemi's AcuEdge
Technology Audio Processor
The ZLS38508 software features:
• Auto Tuning and Subjective Tuning support
• Provides visual representations of the audio paths
with drop-down menus to program parameters,
allowing:
• Control of the audio routing configuration
• Programming of key blocks in the transmit (Tx)
and receive (Rx) audio paths
• Setting analog and digital gains
• Configuration parameters allow users to “fine tune”
the overall performance
Tools
• ZLK38000 Evaluation Kit
•MiTuner™ ZLS38508 and ZLS38508LITE GUI
•MiTuner™ ZLE38470BADA Automatic Tuning Kit
ZL38090 Preliminary Data Sheet Revision 2.0 iii
ZL38090 Preliminary Data Sheet Revision 2.0 iv
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.3 Hardware Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.4 Audio Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3AcuEdge Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Main Application Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.1 Headset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.2 USB Bridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Digital Microphone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1.1 Analog Microphone Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 DAC Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2.1 Output Driver Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.2 DAC Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.1 I2S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.2 PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.3 GCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 Control Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 SPI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.2 I2C Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.3 Host Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Master SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3.1 Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.5 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5.1 USB Audio Function Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 Power Supply Sequencing/Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.1 Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Device Booting and Firmware Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.2 Bootstrap Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.3 Loadable Device Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.3.1 Boot Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ZL38090 Preliminary Data Sheet Revision 2.0 v
8.4 Bootup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1 64-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2 56-Ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.1 Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.2 DAC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.3 Microphone Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.4 TDM and I2S Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.5 Headset Control/Indicator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.6 USB Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.7 HBI – SPI Slave Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.8 Master SPI Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.9 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.10 UART Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.11 GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.12 Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.13 No Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.14 IN0 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.3 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.4 Device Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11.4.1 Working State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11.4.2 USB Suspend State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11.4.3 Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11.4.4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.5 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.6 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.6.1 Microphone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.6.2 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.7 External Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.7.1 Crystal Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.7.2 Clock Oscillator Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11.7.3 AC Specifications - External Clocking Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.1 TDM Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.1.1 GCI and PCM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.1.2 I2S Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.2 Host Bus Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.2.1 SPI Slave Port Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.2.2 I2C Slave Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.3 UART Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.4 Master SPI Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.1 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ZL38090 Preliminary Data Sheet Revision 2.0 vi
Figures
Figure 1 ZL38090 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i
Figure 2 USB Headset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3 ZL38090 AcuEdge Firmware Typical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4 Single Mono Digital Microphone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5 Dual Microphone or Stereo Digital Microphone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6 Four Digital Microphone Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7 ECM Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8 Audio Output Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9 ZL38090 Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10 I2S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11 Left Justified Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 12 Dual Codec Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13 TDM – PCM Slave Functional Timing Diagram (8-bit, xeDX = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14 TDM – PCM Slave Functional Timing Diagram (8-bit, xeDX = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15 TDM – PCM Master Functional Timing Diagram (8-bit, xeDX = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16 TDM – PCM Master Functional Timing Diagram (8-bit, xeDX = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17 TDM – GCI Slave Functional Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18 TDM – GCI Master Functional Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19 USB Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20 SPI Slave Byte Framing Mode – Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 21 SPI Slave Byte Framing Mode – Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 22 SPI Slave Word Framing Mode – Write, Multiple Data Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 23 SPI Slave Word Framing Mode – Read, Multiple Data Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24 SPI Slave Command Framing Mode – Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 25 SPI Slave Command Framing Mode – Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26 Flash Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27 Typical Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 28 Internal +1.2 V Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 29 ZL38090 64-Pin QFN – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 30 ZL38090 56-Ball WLCSP – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 31 THD+N Ratio versus Output Power – Driving Low Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 32 THD+N Ratio versus VRMS – Driving High Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 33 Crystal Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 34 Clock Oscillator Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 35 Timing Parameter Measurement Digital Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 36 GCI Timing, 8-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 37 PCM Timing, 8-bit with xeDX = 0 (Transmit on Negative PCLK Edge) . . . . . . . . . . . . . . . . . . . . . . 46
Figure 38 PCM Timing, 8-bit with xeDX = 1 (Transmit on Positive PCLK Edge) . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 39 Slave I2S Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 40 Master I2S Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 41 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 42 I2C Timing Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 43 UART_RX Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 44 UART_TX Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 45 Master SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 46 64-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 47 Recommended 64-Pin QFN Land Pattern – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 48 56-Ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 49 56-Ball WLCSP Staggered Balls Expanded Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
ZL38090 Preliminary Data Sheet Revision 2.0 vii
Tables
Table 1 HBI Slave Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2 Flash Devices Tested with the ZL38090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3 Supported Flash Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4 Q1 Component Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5 Bootstrap Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6 Reset Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7 DAC Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8 Microphone Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9 TDM and I2S Ports Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10 Headset Control/Indicator Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11 USB Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12 HBI – SPI Slave Port Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13 Master SPI Port Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14 Oscillator Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15 UART Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16 GPIO Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17 Supply and Ground Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18 No Connect Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19 IN0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21 Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 22 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 23 Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 24 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 25 Microphone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 26 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 27 AC Specifications – External Clocking Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 28 GCI and PCM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 29 I2S Slave Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 30 I2S Master Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 31 SPI Slave Port Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 32 I2S Slave Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 33 UART Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 34 Master SPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Revision History
ZL38090 Preliminary Data Sheet Revision 2.0 1
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1 Revision 2.0
The following is a summary of the changes in revision 2 of this document.
• Migration to new document format; no other changes to technical details or content besides those
listed here
• Added USB interface schematic and recommendation for protection device
• Added second digital microphone input pin
• Removed reference to second TDM port
• Updated verbiage on front page to better delineate and describe features
• Minor text corrections
• Headers applied to aid in documentation navigation
• Updated typical power consumption numbers and updated descriptions of operating power states
• Added more detailed block diagram on front page
• Section 2 Overview, page 2 and Section 3 AcuEdge Firmware, page 4 rewritten to provide
clarification on applications and firmware operational modes: no changes to technical details or
specification
• Type 3 and Type 4 flash devices are supported, but not recommended; specific devices previously
recommended have been removed from Table 3, page 20
• Removed remote wake up bullet from firmware feature highlights
Overview
ZL38090 Preliminary Data Sheet Revision 2.0 2
2 Overview
2.1 Introduction
The Microsemi ZL38090 Audio Processor powered by ZLS38090 AcuEdge™ Firmware is ideal for
providing high definition audio for USB headsets, USB Microphones and for USB audio bridging devices
(USB to I2S/TDM).
The ZL38090 provides Two-way Audio Communication using sophisticated audio processing. This
includes beam forming (BF), noise reduction (NR), equalizers (EQ), and a compressor, limiter and
expander (CLE) to improve both the intelligibility and subjective quality of voice in harsh acoustic
environments.
2.2 Applications
Applications for the ZL38090 device include any design that requires USB to analog or USB to I2S/TDM
bridging. In addition to this basic function, the ZL38090 also offers audio enhancement for audio
recording and two-way audio. Typical applications include:
• USB Beamforming Microphones
• USB to analog bridge/ USB to I2S bridge
• USB Headsets/ headset dongles
• USB Speakerphone
• USB Speakers
The following application block diagram shows the ZL38090 used in an USB headset utilizing the 2-
microphone beam forming to remove interfering noise.The USB headset does not need a host processor
to control the device. The ZL38090 is a self-contained processor that provide basic functions for 2-way
audio communications, including GPIO functions for Volume Up/Down, Mute Mic, and Hook-Switch
On/Off. The ZL38090 is Skype/Lync compatible allowing the user to control Skype/Lync through the
GPIO. The ZL38090 incorporates a virtual com port to allow the developer/user to modify various audio
processing settings. An external FLASH is used to hold the PID and VID of the end device.
Figure 1 • USB Headset
2.3 Hardware Peripherals
The main peripherals of the ZL38090 device are shown in Figure 1, page i, and a description of each
follows.
The ZL38090 device provides the following peripheral interfaces:
• USB Audio Class Device v1.0 compliant
• Adaptive mode for playback, Asynchronous mode for record
• USB Audio Class clock modes
• Remote wake-up via fixed function GPIO
• Common HID controls for volume, hookswitch control and mute
ZL38090
DAC
DAC
Digital Mic
Input
AcuEdge™
Noise ReducƟon
EQ
CLE
Flash
Beam Forming
/2S/TDM
SPI
USB
Overview
ZL38090 Preliminary Data Sheet Revision 2.0 3
• USB port that enumerates with EP0 (Control), 2 endpoints for Microphones and Speakers, (both
stereo), and 1 interrupt endpoint (for Status Reporting)
• Skype/Lync Compatible
• Standalone USB device (additional host processor not required for headphone applications)
• 1 digital Microphone interface allowing sampling of 1 or 2 digital microphones
• 2 independent headphone drivers
• Dual 16-bit digital-to-analog converters (DACs)
• 16 ohms single-ended or differential drive capability
• 32 mW output drive power into 16 ohms
• 2 Time-Division Multiplexing (TDM) buses
• The ports can be configured for Inter-IC Sound (I2S) or Pulse-Code Modulation (PCM)
operation
• PCM operation supports PCM and GCI timing, I2S operation supports normal and left justified
transmission
• Each port can be a clock master or a slave
• Each port supports up to four bi-directional streams when configured in PCM mode or two bi-
directional streams when configured for I2S mode at data rates from 128 kb/s to 8 Mb/s
• Sample rate conversions are automatically done when data is sent/received at different rates
than is processed internally. Only integer conversions are allowed.
• SPI – The device provides two Serial Peripheral Interface (SPI) ports
• The SPI Slave port is recommended as the main communication port with a host processor. The
port provides the fastest means to Host Boot and configures the device’s firmware and
configuration record1.
• The Master SPI port is used to load the device’s firmware and configuration record from
external Flash memory (Auto Boot).
•I
2C - The device provides one Inter-Integrated Circuit (I2C) port. (Pins are shared with the SPI Slave
port)
•The I
2C port can be used as the main communication port with a host processor, and can be
used to Host Boot and configure the device’s firmware and configuration record.
• UART – The device provides one Universal Asynchronous Receiver/Transmitter (UART) port
• The UART port can be used as a debug tool and is used for tuning purposes.
• GPIO – The device provides 14 General Purpose Input/Output (GPIO) ports.
• GPIO ports can be used for interrupt and event reporting, fixed function control, bootstrap
options, as well as being used for general purpose I/O for communication and controlling
external devices.
• The 56 pin WLCSP package is limited to 11 GPIOs.
2.4 Audio Design Considerations
The acoustic design consists of the microphone, speaker, speaker driver and the industrial design of the
enclosure. For optimal performance, care must be taken with the device speaker, speaker driver,
microphone selection, and the industrial design to insure maximum acoustic isolation and minimize
distortion.
Microsemi offers various tools and guides to assist in developing the end system. Consult the Microsemi
AcuEdge™ Firmware Manual and the Microphone Speaker and Amplifier Design Note for more
information.
1. The configuration record is a set of register values that are customizable by the application developer to configure and
tune the ZL38090 for a particular design. Refer to the Microsemi AcuEdge™ Firmware Manual for firmware and config-
uration record information
AcuEdge Firmware
ZL38090 Preliminary Data Sheet Revision 2.0 4
3AcuEdge Firmware
Firmware-implemented algorithms, configuration options, and performance can vary based on the
loaded firmware image. The description here of firmware modes and features represents a summary of
the options available at the time of publication, and should not be considered part of the hardware
datasheet specification. The Microsemi AcuEdge™ Firmware Manual for the appropriate firmware image
should be referenced for more detailed information and specification about each of the firmware modes.
Figure 1 depicts many of the typical interfaces available in an AcuEdge firmware image. The desired
firmware image may be loaded at startup or swapped during runtime via the host processor or via an
optional external flash device (see Device Booting and Firmware Swapping, page 26, for more
information). Once running, the AcuEdge firmware and Cross Point Switch share configuration registers,
which may be accessed via the Host Bus Interface. The MiTuner GUI Application can be used during
development to tune the various registers via the UART debug interface. MiTuner can save the complete
set of configuration registers to a file, called the Configuration Record. The set and definition of
configuration registers is defined by the firmware, and can vary based on the loaded image. The
specification of these registers is documented in the Microsemi AcuEdge™ Firmware Manual.
Figure 2 • ZL38090 AcuEdge Firmware Typical Interfaces
The Microsemi AcuEdge Firmware implements various signal processing algorithms, such as
Equalization, Noise Reduction, beam forming and CLE. These algorithms execute in the Audio
Processing Block. The send path is processed at 16 kHz sampling rate while the receive path is
processed at full band. All audio is presented at the USB at full band sampling rates. The Audio
Processing Block has between one and four audio IO (input/output) ports which can be routed to/from
the various audio interfaces via the Cross Point Switch. The firmware automatically decimates audio
inputs down to the Audio Processing sampling rate (16 kHz), and interpolates audio outputs up to the rate
appropriate for the given output peripheral. Refer to the corresponding Audio Interface-specific
documentation in Audio Interfaces, page 6, for details and audio rates for each audio peripheral.
The following section highlights some key features of the firmware. Consult the Microsemi AcuEdge™
Firmware Manual for more details.
7LPEHUZROI=/
'LJLWDO
0LF
,QSXW
'$&
0LFURVHPL'63&RUH
'LJLWDO
0LFURSKRQH
,QWHUIDFH
3'0
$QDORJ
2XWSXW
$FX(GJH)LUPZDUH
&URVV
3RLQW
6ZLWFK
&URVV
3RLQW
6ZLWFK
$XGLR3URFHVVLQJ
%ORFN
6RXW6LQ
5RXW 5LQ
&RQILJXUDWLRQ5HFRUG5$0%RRW5$0
+RVW%XV
,QWHUIDFH
63,RU,
&
8$57
+RVW
&RQWUROOHU 0L7XQHU
0DVWHU
63,
2SWLRQDO
%RRW)/$6+
86%$XGLR
9&RP
86%
'LJLWDO$XGLR
,QWHUIDFH
,
6
7'0
AcuEdge Firmware
ZL38090 Preliminary Data Sheet Revision 2.0 5
3.1 Main Application Configurations
The configuration of the ZL38090 is determined depending on which firmware block is enabled. The
firmware image and configuration is initially loaded at power-on-reset, either from external serial Flash or
from a host controller (see Device Booting and Firmware Swapping, page 26).
There are two main configurations, headset configuration and USB/I2S bridge configuration. The
sections that follow highlight the primary features and operation of the various configurations.
3.1.1 Headset Configuration
In this configuration, the ZL38090 can use either a single mic or dual microphones. In both
configurations, the following features are available:
• Noise Reduction – Analyses the spectral density of the background noise. This information is used
to remove noise while minimizing signal distortion.
• CLE – A sophisticated audio compressor/limiter/expander with adjustable attack and decay time.
This feature along with Beamforming and advanced Noise Reduction allows for Far Field
Microphone pick-up.
• 8 band parametric equalizer – Equalizers are available on the Rin/Rout path, and the Sin/Sout path.
Each path contains eight programmable equalization filters. These equalization filters allow the
application developer to adjust and tune the audio signal to meet certain design requirements
When using dual microphones, Beam Forming (BF) can be implemented to form a steerable beam in
from of the 2-microphone array. The beamformer accepts those sources that it determines are in the
direction of interest and attenuates those that are deemed to be coming from other directions. The beam
former setting can be programmed to allow the beam angle and aggressiveness of the off-beam
attenuation to be modified. This can allow multiple setting corresponding to a "low/med/high" setting for
noise reduction and beamforming. If a single mic is used, beamforming is not available but all other
functions are available.
3.1.2 USB Bridge Configuration
In this configuration, the ZL38090 is used as a simple I2S/TDM/Audio to USB bridge. All audio processes
are bypassed.
Audio Interfaces
ZL38090 Data Sheet Revision 2.0 6
4 Audio Interfaces
4.1 Digital Microphone Interface
The ZL38090 supports up to four digital microphones using the DMIC_CLK, DMIC_IN1, and DMIC_IN2
interface pins.The ZL38090 digital microphone clock output (DMIC_CLK) is either 1.024 MHz or
3.072 MHz depending on the selected TDM-A sample rate. Selecting an 8 kHz or 16 kHz TDM-A sample
rate corresponds to a 1.024 MHz digital microphone clock and selecting a 48 kHz sample rate
corresponds to a 3.072 MHz digital microphone clock. Microphone data is decimated and filtered to
operate at the 16 kHz sampling rate of the Audio Processing block. When there is no TDM-A bus to set
the sample rate, the ZL38090 will operate from the crystal and will pass digital audio from the
microphones operating at a 48 kHz sampling rate.
A stereo digital microphone, or two separate mono digital microphones, send two microphone channels
on one pin by sending the data for one channel on the rising edge and one channel on the falling edge.
The selection as to which clock edge is used to clock in the microphone data (rising/falling) is done via a
firmware configuration record register. Various digital microphone interfaces are presented in Figures 3–
5.
Figure 3 • Single Mono Digital Microphone Interface
Figure 4 • Dual Microphone or Stereo Digital Microphone Interface
ZL38090
Digital Microphone
DMIC_CLK
DMIC_IN1
CLK
DATA
L/R SEL
ZL38090
Stereo Digital
Microphone
Left
Right
DMIC_CLK
DMIC_IN1
CLK
DATA
CLK
DATA
L/R SEL
L/R SEL
Audio Interfaces
ZL38090 Data Sheet Revision 2.0 7
Figure 5 • Four Digital Microphone Interfaces
4.1.1 Analog Microphone Use
Electret condenser microphones (ECM) can be used with the digital microphone interface by using a
Digital Electret Microphone Pre-Amplifier device as shown in Figure 6. External Codecs can also be used
to connect to analog microphones. The external Codecs would interface to the ZL38090 via the TDM
buses.
The analog microphone is wired to an optional differential amplifier which can provide filtering and gain
and converts the microphone signal to single-ended. The microphone signals are then further amplified
and digitized through the Digital Electret Microphone Pre-Amplifiers and applied to the ZL38090 digital
microphone input. The ZL38090 provides the clock to activate the Digital Electret Microphone Pre-
Amplifier.
Figure 6 • ECM Circuit
When using an analog microphone, operation in the Low Power state is not recommended. For more
information, see Device Power States, page 38.
4.2 DAC Output
The ZL38090 supports two 16-bit fully differential delta-sigma digital-to-analog converters. The two
output DACs independently drive an analog output subsystem. Each subsystem is able to drive two
output pins, representing four independent single-ended headphone outputs that can be driven by two
independent data streams. The pins can be independently configured. Four analog gains on each
headphone output are provided and can be set to: 1x, 0.5x, 0.333x, or 0.25x.
Note: Only the positive DAC outputs are available with the 56-ball WLCSP package. The 56-ball WLCSP
package provides two independent single-ended headphone outputs that can be driven by two
independent data streams.
ZL38090
Digital Microphones
Left
Right
DMIC_CLK
DMIC_IN1
CLK
DATA
CLK
DATA
CLK
DATA DMIC_IN2
L/R SEL
L/R SEL
L/R SEL
CLK
DATA
L/R SEL
Right
Left
ZL38090
E
CM DMIC_CLK
DMIC_IN
Vbias VDD
CLK
DATA
DGND
IN
VDD
-
+L/R
Select
Optional circuitry
Commonly used for handset
microphone with long cord
DGND
AGNDAGND
ECM
preamp
with
Digital
Output
Audio Interfaces
ZL38090 Data Sheet Revision 2.0 8
The headphone amplifiers are self-protecting so that a direct short from the output to ground or a direct
short across the terminals does not damage the device.
The ZL38090 provides audible pop suppression which reduces pop noise in the headphone earpiece
when the device is powered on/off or when the device channel configurations are changed. This is
especially important when driving a headphone single-ended through an external capacitor (see Output
Driver Configurations, page 8, configuration C).
The DACs and headphone amplifiers can be powered down if they are not required for a given
application. To fully power down the DACs, disable both the positive and negative outputs.
4.2.1 Output Driver Configurations
Figure 7, page 9 shows the different possible output driver configurations for the 64-pin QFN package.
When using the 56-ball WLCSP package, only the positive single ended outputs DAC1_P and DAC2_P
are provided.
The two output DACs independently drive positive and negative headphone driver amplifiers. The output
pins can be independently configured in the following ways:
A. Direct differential drive of a speaker as low as 32 ohms. For this configuration an analog gain of 1x is
commonly used. (Differentially driving a 16 ohm speaker is possible, but only with the same amount
of power as in the single-ended case. The signal level must be reduced to not exceed ½ scale in this
case.) This configuration is not available in the 56-ball WLCSP package.
B. Direct differential drive of a high impedance power amplifier. A Class D amplifier is recommended for
this speaker driver. A 1 μF coupling capacitor is generally used with the Class D amplifier. The
analog gain setting depends on the gain of the Class D amplifier, analog gain settings of 0.25x or
0.5x are commonly used. This configuration is not available in the 56-ball WLCSP package.
C. Driving either a high impedance or a capacitively coupled speaker as low as 16 ohms single-ended.
For this configuration an analog gain of 1x is commonly used. The coupling capacitor value can vary
from 10 μF to 100 μF depending on the type of earpiece used and the frequency response desired.
Audio Interfaces
ZL38090 Data Sheet Revision 2.0 9
Figure 7 • Audio Output Configurations
4.2.2 DAC Bias Circuit
The common mode bias voltage output signal (CREF) must be decoupled through a 0.1 μF (CREF1) and
a 1.0 μF (CREF2) ceramic capacitor to VSS.
The positive DAC reference voltage output (CDAC) must be decoupled through a 0.1 μF (CDAC) ceramic
capacitor to VSS as shown in Figure 8.
All capacitors can have a 20% tolerance and should have a minimum voltage rating of 6.3 V.
ZL38090
64-pin QFN
+
-
+
-
En 1P
En 1M
DAC 1
+
-
DAC1_M
DAC1_P
AB
C
+
-
+
-
+
-
+
-
En 2P
En 2M
DAC 1
+
-
DAC2_M
DAC2_P
AB
C
+
-
+
-
Audio Interfaces
ZL38090 Data Sheet Revision 2.0 10
Figure 8 • ZL38090 Bias Circuit
4.3 TDM Interface
The ZL38090 supports a generic TDM interface that consists of four signals:
• Data clock (PCLK/I2S_SCK)
• Data rate sync (FS/I2S_WS)
• Serial data input (DR/I2S_SDI)
• Serial data output (DX/I2S_SDO)
The TDM port can be configured for Inter-IC Sound (I2S) or Pulse-Code Modulation (PCM) operation.
The TDM block is capable of being a master or a slave.
While a TDM bus configuration may carry many encoded audio streams, the ZL38090 device Cross
Point Switch can only address a maximum of 4 bi-directional audio streams per TDM bus. These four
audio streams are referred to as channels #1 through #4, and each of these channels can be
independently configured to decode any of the TDM bus’s audio streams.
Once the TDM bus is configured for a data sample rate and encoding, all data rates and encoding on that
bus will be the same. 16-bit linear data will be sent on consecutive 8-bit timeslots (e.g., if timeslot N is
programmed in the timeslot registers, the consecutive timeslot is N+1).
The TDM interface supports bit reversal (LSB first <- -> MSB first) and loopbacks within the TDM
interface and from one interface to another.
The generic TDM interface supports the following mode and timing options.
4.3.1 I2S Mode
In I2S mode, the 4-wire TDM port conforms to the I2S protocol and the port pins become I2S_SCK,
I2S_WS, I2S_SDI, and I2S_SDO (refer to Table 9, page 31 for pin definitions).
An I2S bus supports two bi-directional data streams with left and right channels, by using the send and
receive data pins utilizing the common clock and word signals. The send data is transmitted on the
I2S_SDO line and the receive data is received on the I2S_SDI line.
The I2S port can be used to connect external analog-to-digital converters or Codecs. The port can
operate in master mode where the ZL38090 is the source of the port clocks, or slave mode where the
word select and serial clocks are inputs to the ZL38090.
The word select (I2S_WS) defines the I2S data rate and sets the frame period when data is transmitted
for the left and right channels. A frame consists of one left and one right audio channel. The I2S ports
operate at 8, 16, and 48 kHz data rates as slave or master. Per the I2S standard, the word select is
output using a 50% duty cycle.
The serial clock (I2S_SCK) rate sets the number of bits per word select frame period and defines the
frequency of I2S_CLK. I2S data is input and output at the serial clock rate. Input data bits are received on
I2S_SDI and output data bits are transmitted on I2S_SDO. Data bits are always MSB first. The number
ZL38090
CREF
CDAC
C
REF1
C
REF2
C
DAC
0.1 ȝ)
0.1 ȝ)
1.0 ȝ)
Audio Interfaces
ZL38090 Data Sheet Revision 2.0 11
of clock and data bits per frame can be programmed as 8, 16, 32, 64, 96, 128, 192, 256, 384, 512, or
1024. Any input data bits that are received after the LSB are ignored.
The I2S port operates in two frame alignment modes (I2S and Left justified) which determine the data
start in relation to the word select.
Figure 9 illustrates the I2S mode, which is left channel first with I2S_WS (Left/Right Clock signal) low,
followed by the right channel with I2S_WS high. The MSB of the data is clocked out starting on the
second falling edge of I2S_SCK following the I2S_WS transition and clocked in starting on the second
rising edge of I2S_SCK following the I2S_WS transition. Figure 9 shows I2S operation with 32 bits per
frame.
Figure 9 • I2S Mode
Figure 10 illustrates the left justified mode, which is left channel first associated with I2S_WS (Left/Right
Clock signal) high, followed by the right channel associated with I2S_WS low. The MSB of the data is
clocked out starting on the falling edge of I2S_SCK associated with the I2S_WS transition, and clocked
in starting on the first rising edge of I2S_SCK following the I2S_WS transition.
Figure 10 • Left Justified Mode
Each I2S interface can support one dual channel Codec (Figure 11) through the Codec’s I2S interface.
The four 16- bit channel processing capacity of the DSP is spread across the two input channels from the
ADCs of Codec(0) and Codec(1), and the two output channels to the DACs of Codec(0) and Codec(1).
Left Channel
I2S_WS
I2S_SCK
I2S_SDI
I
2S_SDO 03141510123031415141234
BSLBSMBSLBSM
lennahC thgiRlennahC tfeL
1 Bit Clock Cycle Offset 1 Bit Clock Cycle Offset
Data
Right Channel
Data
5121014131211
10 512101413121110
5121014131211 051211413121110
031415112340123463141516
BSMBSM BSLBSL
I2S_WS
I2S_SCK
I2S_SDI
I
2S_SDO
lennahC thgiRlennahC tfeL
Left Channel
Data
Right Channel
Data
10
Audio Interfaces
ZL38090 Data Sheet Revision 2.0 12
Figure 11 • Dual Codec Configuration
Both I2S bus modes can support full bi-directional stereo communication. The device supports I2S
loopback.
See the Microsemi AcuEdge™ Firmware Manual for I2S port registers.
4.3.2 PCM Mode
Each of the PCM channels can be assigned an independent timeslot. The timeslots can be any 8-bit
timeslot up to the maximum supported by the PCLK being used.
The PCM ports can be configured for Narrowband G.711 A-law/µ-Law or Linear PCM or Wideband
G.722 encoding. For a given TDM bus, once it is configured for a data sample rate and encoding, all data
rates and encoding on that bus will be the same. 16-bit linear PCM will be sent on consecutive 8-bit
timeslots (e.g., if timeslot N is programmed in the timeslot registers, the consecutive timeslot is N+1). The
PCM interface can transmit/receive 8-bit compressed or 16-bit linear data with 8 kHz sampling
(Narrowband), or 16-bit linear data with 16 kHz sampling (Wideband). Although the firmware allows it,
44.1 and 48 kHz sampling are not commonly used with PCM.
Wideband audio usually means that the TDM bus is operating at a 16 kHz FS, but there are two other
operating modes that support wideband audio using an 8 kHz FS:
• G.722 supports wideband audio with an 8 kHz FS. This uses a single 8-bit timeslot on the TDM bus.
• “Half-FS Mode” supports wideband audio with an 8 kHz FS signal. In this mode, 16-bit linear audio is
received on two timeslot pairs; the first at the specified timeslot (N, N+1) and the second a half-
frame later. In total, four 8-bit timeslots are used per frame, timeslots (N, N+1) and ((N +
((bits_per_frame)/16)), (N + 1 + ((bits_per_frame)/16))). The user programs the first timeslot and the
second grouping is generated automatically 125/2 µs from the first timeslot.
The PCM voice/data bytes can occupy any of the available timeslots, except for PCM clock rates that
have extra clocks in the last timeslot. If there is more than one extra clock in the last timeslot, the timeslot
data will be corrupted, do not use the last timeslot for these clock frequencies (e.g., 3.088 MHz etc.).
The PCM block can be configured as a master or a slave and is compatible with the Texas Instruments
Inc. McBSP mode timing format.
Figure 12 and Figure 13 illustrate the PCM format with slave timing, FS and PCLK are provided by the
host. Slave mode accommodates frame sync pulses with various widths (see GCI and PCM Timing
Parameters, page 45).
ZL38090
ADC
ADC
I2S_SDI
I2S_SDO
CODEC(1)
CODEC(0)
DAC
DAC
CODEC(0)
CODEC(1)
Left Codec0 Right Codec1
Right Codec0 Left Codec1
Audio Interfaces
ZL38090 Data Sheet Revision 2.0 13
Figure 12 • TDM – PCM Slave Functional Timing Diagram (8-bit, xeDX = 0)
Figure 13 • TDM – PCM Slave Functional Timing Diagram (8-bit, xeDX = 1)
Figure 14 and Figure 15 illustrate the PCM format with master timing, FS and PCLK are provided by the
ZL38090. Master mode outputs a frame sync pulse equal to one PCLK cycle.
Diagrams for PCM transmit on negative edge (xeDX = 0) and PCM transmit on positive edge (xeDX = 1)
are shown for both slave and master timing.
Figure 14 • TDM – PCM Master Functional Timing Diagram (8-bit, xeDX = 0)
5674 123010 1230564 7
5674 123010 1230564 7
FS
PCLK
DR
DX
Time Slot 0 Time Slot N = 2
n
– 1,
where: n = 1 … 8; 0 N 255
5674 123010 1230564 7
5674 123010 1230564 7
FS
P
CLK
DR
DX
Time Slot 0 Time Slot N = 2
n
– 1,
where: n = 1 … 8; 0 N 255
5674 123010 1230564 7
5674 123010 1230564 7
FS
PCLK
DR
DX
Time Slot 0 Time Slot N = 2
n
– 1,
where: n = 1 … 8; 0 N 255
Audio Interfaces
ZL38090 Data Sheet Revision 2.0 14
Figure 15 • TDM – PCM Master Functional Timing Diagram (8-bit, xeDX = 1)
4.3.3 GCI Mode
The GCI voice/data bytes can occupy any of the available timeslots. The GCI block can be configured as
a master or a slave and supports a clock that has the same frequency as the data rate.
Note: Traditional GCI Monitor, Signaling, and Control channel bytes and double data rate are not supported.
Figure 16 illustrates the GCI format with slave timing, FS and PCLK are provided by the host. Slave
mode accommodates frame sync pulses with various widths (see GCI and PCM Timing Parameters,
page 45).
Figure 17 illustrates the GCI format with master timing, FS and PCLK are provided by the ZL38090.
Master mode outputs a frame sync pulse equal to one PCLK cycle.
For both, first data bits are aligned with the rising edge of the frame sync pulse.
Figure 16 • TDM – GCI Slave Functional Timing Diagram
Figure 17 • TDM – GCI Master Functional Timing Diagram
5674 123010 1230564 7
5674 123010 1230564 7
FS
PCLK
DR
DX
Time Slot 0 Time Slot N = 2
n
– 1,
where: n = 1 … 8; 0 N 255
4563 012707 0127453 6
4563 012707 0127453 6
Time Slot 0 Time Slot N = 2
n
– 1,
where: n = 1 … 8; 0 N 255
FS
P
CLK
DR
DX
FS
P
CLK
DR
DX
4563 012707 0127453 6
4563 012707 0127453 6
Time Slot 0 Time Slot N = 2
n
– 1,
where: n = 1 … 8; 0 N 255
Audio Interfaces
ZL38090 Data Sheet Revision 2.0 15
4.4 USB Interface
The ZL38090 will enumerate as an USB Audio Class v1.0 Device. Windows, Macintosh, and Linux PCs
will all identify the ZLS38090 as an audio class device without requiring additional driver installation. The
ZL38090 is USB 2.0 compliant. It will send and receive at the full speed rate of 12 Mbps. The device will
enumerate with one control endpoint, and two endpoints for Microphone input and Speaker output (both
are Stereo) with one interrupt endpoint for Status Reporting. Configuration settings allows for either
stereo play/record or just stereo playback.
Figure 18 illustrates the connection of the USB interface to the ZL38090. A USB protection device
(transient voltage suppressor) is recommended. The ZL38090 uses GPIO_6 for USB Resume.
Figure 18 • USB Interface Circuit
ZL38090
86%B'3
86%B'0
86%
'
'
796
GND
*3,2B
RKP
RKP
86%B5781(
RKP
Control Interfaces
ZL38090 Preliminary Data Sheet Revision 2.0 16
5 Control Interfaces
5.1 Host Bus Interface
The host bus interface (HBI) is the main communication port from a host processor to the ZL38090. It
can be configured to be either a SPI Slave or an I2C Slave port, either of which can be used to program
or query the device.
The ZL38090 allows for automatic configuration between SPI and I2C operation. For the HBI port, if the
HCLK toggles for two cycles, the HBI will default to the SPI Slave, otherwise it will remain configured as
I2C (see Table 1, page 16). The HBI comes up listening in both SPI and I2C modes, but with I2C inputs
selected. If HCLK is present, it switches the data selection before the first byte is complete so that no bits
are lost. Once the port is determined to be SPI, a hardware reset is needed to change back to I2C.
This port can read and write all of the memory and registers on the ZL38090. The port can also be used
to boot the device, refer to Device Booting and Firmware Swapping, page 26.
5.1.1 SPI Slave
The physical layer is a 4-wire SPI interface. Chip select and clock are both inputs.
The SPI Slave port can support byte, word, or command framing. Write and read diagrams for these
framing modes are shown in Figures 19 ‒ 24. The SPI Slave chip select polarity, clock polarity, and
sampling phase are fixed.
The ZL38090 command protocol is half duplex, allowing the serial in and serial out to be shorted together
for a 3- wire connection. The chip select is active low. The data is output on the falling edge of the clock
and sampled on the rising edge of the clock.
The SPI Slave supports access rates up to 25 MHz. The outbound interrupt is always active low.
Figure 19 • SPI Slave Byte Framing Mode – Write
Table 1 • HBI Slave Interface Selection
Description Condition Operating Mode Notes
HBI Slave interface
selection.
HCLK toggling Host SPI bus
HDIN tied to VSS Host I2C bus. Slave address 45h (7-bit). 1
1. By default, the HBI comes up as an I2C interface. Toggling the HCLK pin will cause the host interface to switch
to a SPI interface. If an I2C interface is desired, HCLK needs to be tied to ground.
HDIN tied to
DVDD33
Host I2C bus. Slave address 52h (7-bit).
HCS
HCLK
HDIN
H
DOUT
Cmd_wd[15:8] Cmd_wd[7:0] Data_wd[15:8] Data_wd[7:0]
t
ACC
t
ACC
t
ACC
t
ACC
Cmd_wd
Control Interfaces
ZL38090 Preliminary Data Sheet Revision 2.0 17
Figure 20 • SPI Slave Byte Framing Mode – Read
Figure 21 • SPI Slave Word Framing Mode – Write, Multiple Data Words
Figure 22 • SPI Slave Word Framing Mode – Read, Multiple Data Words
Figure 23 • SPI Slave Command Framing Mode – Write
HCS
HCLK
HDIN
H
DOUT
Cmd_wd[15:8] Cmd_wd[7:0]
Data_wd[15:8] Data_wd[7:0]
t
ACC
t
WR_RDV
t
ACC
t
ACC
Cmd_wd
HCS
HCLK
HDIN
H
DOUT
Command word Data word
t
ACC
t
ACC
Data wor
d
HCS
HCLK
HDIN
H
DOUT
Command word
Data word
t
WR_RDV
t
ACC
Data word
HCS
HCLK
HDIN
HDOUT
Command word Data word
t
ACC
Command word
Control Interfaces
ZL38090 Preliminary Data Sheet Revision 2.0 18
Figure 24 • SPI Slave Command Framing Mode – Read
5.1.2 I2C Slave
The I2C bus is similar to the Philips Semiconductor (NXP) 1998 Version 2.0, I2C standard. The ZL38090
I2C bus supports 7-bit addressing and transfer rates up to 400 kHz. External pull-up resistors are
required on the I2C serial clock input (HCS) and the I2C serial data input/output (HDOUT) when operating
in this mode (note, the I2C slave pins are 3.3 V pins and are not 5 V tolerant).
The selection of the I2C slave address is performed at bootup by the strapping of the HDIN and HCLK
pins, see Table 1, page 16.
5.1.3 Host Interrupt Pin
An internal host interrupt controller controls the active low interrupt pin which is part of the host bus
interface. Associated with the interrupt controller is an event queue which reports status information
about which event caused the interrupts.
Upon sensing the interrupt, the host can read the event queue to determine which event caused the
interrupt. Specific events are enabled by the host processor, and are typically not used with a standalone
(controllerless) design.
Refer to Events in the Microsemi AcuEdge™ Firmware Manual for Event ID Enumerations.
5.2 UART
The ZL38090 device incorporates a two-wire UART (Universal Asynchronous Receiver Transmitter)
interface with a fixed 115.2 K baud transfer rate, 8 data bits, 1 stop and no parity. TX and RX pins allow
bi-directional communication with a host PC. The UART pins must be made accessible on the PCB for
debug and tuning purposes.
5.3 Master SPI
Like the HBI SPI Slave, the physical layer of the Master SPI is a 4-wire SPI interface supporting half
duplex communication.It supports only one chip select which is multiplexed with GPIO_9.
The Master SPI is only used by the built-in boot ROM to bootload from an external serial Flash. The
ZL38090 can automatically read the Flash data (program code and configuration record) through this
interface upon the release of reset (Auto Boot), depending on the value of the bootstrap options.
Note: An alternative to Auto Boot is to perform a Host Boot through the HBI port. Refer to Device Booting and
Firmware Swapping, page 26.
5.3.1 Flash Interface
After power-up the ZL38090 will run its resident boot code, which establishes the initial setup of the
Master SPI port and then downloads the firmware from external Flash memory when configured for auto
boot mode. This Flash firmware establishes the resident application and sets the configuration of all the
ZL38090 ports.
Figure 25 illustrates the connection of Flash memory to the ZL38090 Master SPI port. Figure 25 and the
ZLE38000 demonstration hardware uses the Macronix™ MX25L4006E 4 Mbit CMOS Serial Flash
device.
HCS
HCLK
HDIN
H
DOUT
Command word
Data word
tACC
Command word
tWR_RDV
Control Interfaces
ZL38090 Preliminary Data Sheet Revision 2.0 19
Figure 25 • Flash Interface Circuit
5.3.1.1 Flash Selection
The ZL38090 Boot ROM is designed to work with a wide variety of Flash devices. There are numerous
Flash devices that the ZL38090 Boot ROM can recognize and program without host intervention other
than a command to initialize the Flash. Other unrecognized devices may be utilized if they conform to
certain characteristics of known devices and the host informs the ZL38090 Boot ROM of their type and
size.
The ZL38090 identifies Flash devices (with a single binary image) with the ZL38090 boot ROM auto-
sensing the Flash type. The ZL38090 complies with JEDEC Manufacturer and Device ID Read
Methodology for SPI Compatible Serial Interface Memory Devices. The ZL38090 is compatible with the
Serial Flash Discoverable Parameters JEDEC standard JESD216B and the Common Flash Interface
JESD68.01 JEDEC standard. The ZL38090 can identify devices by their JEDEC standard JEP106-K
Standard Manufacturer’s Identification Code.
Select a Flash size that is adequate to store all the firmware images required of the application. The
image sizes can be obtained from the specific firmware releases.
A list of Flash devices that are identifiable by the ZL38090 Boot ROM are shown in Ta b l e 2 . The size of
these devices are all 2 Mbit or 4 Mbit, the Boot ROM will also recognize the size of 8 Mbit parts that are
Type 1 or Type 2 devices (as defined in Table 3).
Table 2 • Flash Devices Tested with the ZL38090
Manufacturer Part Number Description
Macronix™ MX25V4006EM1I-13G 4 Mbit Flash.
Winbond™ W25X40CLSNIG-ND 4 Mbit Flash.
W25X20CLSNIG-ND 2 Mbit Flash.
Micron® M25P20-VMN6PB Large 512 Kbit sectors limit the usefulness of this device. Holds
only 1 application image.
M25P40-VMN6PB 4 Mbit Flash. Large 512 Kbit sectors limit the usefulness of this
device. Holds only 2 or 3 application images.
Spansion™ S25FL204K0TMF1010 4 Mbit Flash.
ZL38090
SM_CS
+3.3 V
SM_CLK
100 nF
SM_MISO
SM_MOSI
SCLK
CS
SO/SIO1
SI/SIO0
HOLD
WP
VCC
GND
10K
10K
100K 100K
Master SPI
MX25L4006E
Control Interfaces
ZL38090 Preliminary Data Sheet Revision 2.0 20
Flash devices whose JEDEC ID or size (usually a size of 16 Mbit or larger) that are not recognized by the
ZL38090 Boot ROM can be made to work if they fit the characteristics of one of the four Flash types
listed in Tab l e 3 . By writing the type (1, 2, 3, or 4) to ZL38090 address 0x118 and the number of sectors
to ZL38090 address 0x116 prior to initializing the Flash device, the Boot ROM will treat it as a known
device of known size even though the manufacturer ID or size field are not recognized.
5.4 GPIO
The ZL38090 64-pin QFN package has 14 GPIO (General Purpose Input/Output) pins; the ZL38090 56-
ball WLCSP package has 11 GPIO pins.
The GPIO pins can be individually configured as either inputs or outputs, and have associated maskable
interrupts reported to the host processor through the interrupt controller and event queue. The GPIO pins
are intended for low frequency signaling.
When a GPIO pin is defined as an input, the state of that pin is sampled and latched into the GPIO Read
Register. A transition on a GPIO input can cause an interrupt and event to be passed to the host
processor.
GPIO pins 7, 8, and 10‒13 have special predefined functions, such as volume up/down, associated with
these pins. This functionality is designed to support the features of a headset designed for Skype, Lync,
AMIC Technology A25L020O-F 2 Mbit Flash.
Table 3 • Supported Flash Types
Characteristic Type 1 Type 2 Type 31
1. While Type 3 and Type 4 flash devices are supported, they are not recommended due to the time and complexity required to
program these devices.
Type 41
Sector Size 512 Kbit (64 KB) 32 Kbit (4 KB) 32 Kbit (4 KB) 16 Kbit (2 KB)
Read Status Reg Cmd 0x05 0x05 0x05 0xD7
Status Reg Busy bit = 0x01 Busy bit = 0x01 Busy bit = 0x01 Done bit = 0x80
Data Read Cmd 0x03 0x03 0x03 0x03
Write Enable Cmd 0x06 0x06 0x06 N/A
Page Write Cmd 0x02 0x02 N/A
Uses AAI to program
word or byte. Uses
Write Disable
command to terminate
AAI.
N/A
Uses write from
buffer command.
4-Byte Bulk Erase Cmd N/A N/A N/A 0xC794809A
Examples Micron®
M25P20-VMN6PB
M25P40-VMN6PB
Winbond™
W25X40CLSNIG-ND
W25X20CLSNIG-ND
Macronix™
MX25V4006EM1I-13G
AMIC Technology
A25L020O-F
Spansion™
S25FL204K0TMF1010
Atmel®
AT25DF041A
Table 2 • Flash Devices Tested with the ZL38090
Manufacturer Part Number Description
Control Interfaces
ZL38090 Preliminary Data Sheet Revision 2.0 21
or other VoIP communication system. See Fixed Function I/O in the Microsemi AcuEdge™ Firmware
Manual.
Immediately after any power-on or hardware reset the GPIO pins are defined as inputs and their state is
captured in the GPIO Configuration Register. The state of this register is used to determine which options
are selected for the device. The GPIO pin status is then redefined as specified in the configuration record
that is loaded from the Flash or host.
In addition to the predefined fixed functions and the general functionality of the GPIO pins, the GPIO pins
also support the bootstrap functions listed in Table 5, page 26.
5.5 USB Interface
In addition to the USB Audio outlined in USB Interface, page 15, the ZL38090 has the option of
enumerating 2 endpoints for bi-directional Virtual Com support over USB. This optional USB Virtual Com
interface can be used for code load and debug control from any connected PC. This Virtual Com
interface is available over the same USB connection that carries audio and can be enabled or disabled
via the configuration record. See USB Endpoints in the Microsemi AcuEdge™ Firmware Manual.
5.5.1 USB Audio Function Topology
The USB Audio Class Descriptors allow the host to discover and control the USB devices’ audio controls,
commonly called the Audio Function. See USB Audio Function in the Microsemi AcuEdge™ Firmware
Manual.
Reset
ZL38090 Preliminary Data Sheet Revision 2.0 22
6 Reset
The device has a hardware reset pin (RESET) that places the entire device into a known low power state.
When the reset pin is brought low for a duration of at least 10µs, both a digital and analog reset will occur.
The digital reset will reset all device states and registers. The analog reset will deactivate the internal
PLL and drive the VDD12_CTRL pin low, disabling the +1.2V supply.
When the reset pin is driven high, the device will go though its boot process and the firmware will be
reloaded. GPIO pins will be re-sensed when the reset pin is brought high.
A 10 KΩ pull-up resistor is required on the RESET pin to DVDD33 if this pin is not continuously driven.
Power Supply
ZL38090 Preliminary Data Sheet Revision 2.0 23
7 Power Supply
7.1 Power Supply Sequencing/Power up
No special power supply sequencing is required. The +3.3 V or +1.2 V power rails can be applied in either
order.
Upon power-up, the ZL38090 begins to boot and senses the external resistors on the GPIO to determine
the bootstrap settings. After 3 ms, the boot process begins and the ZL38090 takes less than 1 second to
become fully operational (for Auto Boot from Flash, including the time it takes to load the firmware).
In order to properly boot, the clocks (and power supplies) to the device must be stable. This requires
either the 12.000 MHz crystal or clock oscillator to be active and stable before the ZL38090’s reset is
released.
7.1.1 Power Supply Considerations
The 5V USB supply is typically used to power the ZL38090.
The ZL38090 requires +1.2 V to power its core DSP power supply (DVDD12). To achieve optimum noise
and power performance, supply DVDD12 from an external source. Use a DC-DC switching power
converter like the Microsemi LX7186A to achieve high efficiency and load regulation. The ZL38090 is
designed to minimize power in its active states when DVDD12 is supplied externally.
Figure 26, page 24 shows DVDD33 and DVDD12 powered from the +5V USB supply. The Microsemi
LX8213-33ISE 300mA Low Drop Out Voltage Regulator is shown supplying DVDD33. The Microsemi
LX7186A 1.4MHz fixed frequency, current mode, synchronous PWM buck (step-down) DC-DC converter
is shown supplying DVDD12.
External +1.2 V supply use is selected when the EXT_SEL pin is tied to +3.3 V. The EXT_SEL pin can be
pulled high or simply hard-wired to DVDD33. This is the typical use case.
VDD12_CTRL is a CMOS output which can be used to control the shutdown of the external +1.2 V
supply. VDD12_CTRL will provide a steady +3.3 V output (with up to 4 mA of source current) for the
external supply to be enabled and 0 V for the supply to be disabled.
For power savings when the ZL38090 does not need to be operational, the external voltage regulator can
be turned off by pulling the RESET pin low for longer than 10 µS (Reset mode). This action will force the
VDD12_CTRL pin low, shutting off the external LDO and allowing the +1.2 V supply to collapse to 0 V.
If shutdown of the external +1.2 V supply is not desired, simply leave the VDD12_CTRL output pin
floating.
Power Supply
ZL38090 Preliminary Data Sheet Revision 2.0 24
Figure 26 • Typical Power Supply Configuration
7.1.1.1 Internal +1.2 V Power
Note: The internal +1.2 V power option is only available with the 64-pin QFN package. The VDD12_CTRL pin is
not available on the 56-ball WLCSP package.
An alternative supply configuration takes advantage of the ZL38090 built-in voltage regulator as the
DVDD12 source. The internal voltage regulator requires an external N-channel FET device and a parallel
470 ohm resistor. Figure 27, page 25 shows DVDD12 powered from the internal supply. Power
dissipation is higher with internal regulator use due to the internal control circuitry and functional blocks
being active.
Note: When using the internal regulator, the ZL38090 will not meet the 12.5 mW USB suspend power
specification.
Internal supply use is selected when the EXT_SEL pin is tied to VSS. With the built-in voltage regulator
enabled, VDD12_CTRL will drive Q1 and generate +1.2 V at DVDD12. The parallel 470 ohm resistor is
required to ensure supply start-up. Q1 can be any of the high power FETs shown in Ta b l e 4 , page 24, or
an equivalent.
For power savings when the ZL38090 does not need to be operational, the internal voltage regulator can
be turned off by pulling the RESET pin low for longer than 10 µS (Reset mode). This action will force the
VDD12_CTRL pin low, shutting off the FET and allowing the +1.2 V supply to collapse to 0 V.
Table 4 • Q1 Component Options
Manufacturer Part Number
Vishay® Si1422DH
International Rectifier IRLMS2002
Diodes Inc.® ZXMN2B03E6
VSS
VDD12_CTRL
DVDD12
DVDD33
+3.3 V
ZL38090
'&'&
6ZLWFKLQJ
&RQYHUWHU
SHDN
+1.2 V
GND
EXT_SEL
+V
9%86
VOUT
Supply decoupling is not shown
RESET
LX$
/'2
5HJXODWRU
LX
Power Supply
ZL38090 Preliminary Data Sheet Revision 2.0 25
Figure 27 • Internal +1.2 V Power Supply Configuration
VSS
VDD12_CTRL
DVDD12
DVDD33 +3.3 V
ZL38090
EXT_SEL
47
0
Q1
G
D
S
G
Supply decoupling is not shown
RESET
Device Booting and Firmware Swapping
ZL38090 Preliminary Data Sheet Revision 2.0 26
8 Device Booting and Firmware Swapping
8.1 Bootloader
The ZL38090 device contains a built-in bootloader that gets executed after a hardware reset, when
power is initially applied to the part, and during the firmware Swap process. The bootloader performs the
following actions:
• Reads the GPIO bootstrap information and stores it in the Boot Sense registers
• Determinant on the bootstrap setting, it loads external serial Flash device contents (firmware and
configuration record) into Program RAM (Auto Boot), or waits for the host to load Program RAM
(Host Boot and Firmware Swap)
• If Auto Boot is selected, the bootloader then programs the ZL38090 configuration registers to their
proper default values, and jumps to Program RAM to execute the firmware
8.2 Bootstrap Modes
Table 5 lists the different boot options that can be selected by using an external resistor. GPIOs have
internal pull-down resistors, thereby defaulting to a 0 setting. A resistor to DVDD33 is required to select a
1 option. An external pull-up resistor must have a value of 3.3 KΩ. A GPIO with a bootstrap pull-up can
be used for other functionality following the power-up boot sense process.
8.3 Loadable Device Code
In order for the ZL38090 to operate, it must be loaded with code that resides externally. This code can be
Auto Booted from an external Flash memory through the Master SPI, loaded into the ZL38090 by the
host processor through the HBI port, or loaded from the USB host over the USB Virtual Com port. An
external resistor pull-up or an internal resistor pull-down determines which boot mode will be used (see
Table 5).
The external code consists of two logical segments, the firmware code itself and the configuration record.
The firmware is a binary image which contains all of the executable code allowing the ZL38090 to
perform voice processing and establishes the user command set. The configuration record contains
settings for all of the user registers and defines the power-up operation of the device.
The configuration record is set up so that the registers are initialized to their desired values for normal
operation.
A GUI development tool (MiTuner™ ZLS38508) is provided to create and modify a configuration record
and create a bootable Flash image which can then be duplicated for production of the end product. This
tool requires access to the UART for tuning.
8.3.1 Boot Speed
When performing an Auto Boot from a Flash device, the boot sequence lasts <1 second (for a typical
firmware image and configuration record of size 400 kB).
Table 5 • Bootstrap Modes
GPIO_2 GPIO_1 GPIO_0 Operating Mode Description Notes
X 0 0 12.000 MHz Crystal (default) Clock source selection
X 1 1 Reserved
0 X X Host Boot over HBI or USB Virtual
Com Port (default)
Boot source selection
1 X X Auto Boot from external Flash 1
1. Apply a 3.3 KΩ resistor from GPIO_2 to DVDD33. Note, when external Flash is selected, GPIO_9 = SM_CS.
Device Booting and Firmware Swapping
ZL38090 Preliminary Data Sheet Revision 2.0 27
8.4 Bootup Procedure
Valid clocks (crystal or clock oscillator) must be present before the ZL38090 device can exit its reset
state. After the reset line is released, the ZL38090’s internal voltage regulator will be enabled (if the
EXT_SEL pin is strapped low). Once the +1.2 V supply is established, the PLL will be also be enabled.
Based on the GPIO bootstrap options, the ZL38090 will select the system parameters and the PLL will
lock to the desired operating frequency.
Next, if the GPIO strapping pins indicate that the ZL38090 will Auto Boot, it will begin reading data from
the external Flash. Refer to the Microsemi AcuEdge™ Firmware Manual for a listing of the complete Boot
Sequence.
If the GPIO strapping pins indicate that the ZL38090 will Host Boot, the SPI or I2C port that initiates the
loading process becomes the boot master. The ZL38090 allows for automatic configuration between SPI
and I2C operation.
Device Pinouts
ZL38090 Preliminary Data Sheet Revision 2.0 28
9 Device Pinouts
9.1 64-Pin QFN
Figure 28 • ZL38090 64-Pin QFN – Top View
64 585960616263 57 56 55 54
11
10
9
8
7
6
5
4
3
2
1
IN0
GPIO_9/SM_CS
IN0
IN0
NC
53 52 51 50 49
16
15
14
13
12
38
39
40
41
42
43
44
45
46
47
48
33
34
35
36
37
3231
3029
28
272625
24
23
22
2120191817
DVDD33
GPIO_1
0
GPIO_8
DVDD12
GPIO_7
GPIO_6
GPIO_1
2
GPIO_2
GPIO_5
GPIO_4
GPIO_0
GPIO_3
DVDD33
GPIO_1
3
GPIO_1
FS/I2S_WS
DR/I2S_SDI
DMIC_IN1
USB_RTUNE
DVDD33
USB_DM
XO
DVDD12
DMIC_CLK
USB_DP
EXT_SEL
DMIC_IN2
DX/I2S_SDO
SM_CLK
SM_MISO
SM_MOSI
DVDD33
DAC1_M
DAC1_P
DAC2_P
CDAC
CREF
RESET
DVDD12
GPIO_1
1
AVDD33
DAC2_M
DVDD12
AVDD33
DVDD33
DVDD12
+,17
+'287
+',1
VSS
+&6
+&/.
DVDD33
UART_RX
UART_TX
Exposed Ground Pad
V
DD12_CTRL
XI
DVDD33_XTAL
PCLK/I2S_SCK
Device Pinouts
ZL38090 Preliminary Data Sheet Revision 2.0 29
9.2 56-Ball WLCSP
Figure 29 • ZL38090 56-Ball WLCSP – Top View
XI
DMIC_CLK
DMIC_IN1
DMIC_IN2
H1 H2 H3 H4 H5 H6 H7
CREF
DVDD12DVDD12
DVDD33
VSS
G1 G2 G3 G4 G5 G6 G7
XO CDAC
GPIO_2 GPIO_0
GPIO_3 GPIO_5
F1 F2 F3 F4 F5 F6 F7
GPIO_10
GPIO_7 AVDD33
VSS
GPIO_1
PCLK/I2S_SCK
FS/I2S_WS
DX/I2S_SDO
DR/I2S_SDI
GPIO_6
E1 E2 E3 E4 E5 E6 E7
GPIO_8 RESET DAC2_PVSSVSS
DVDD12
D1 D2 D3 D4 D5 D6 D7
GPIO_11 DAC1_P
IN0
IN0
USB_RTUNE
USB_DP USB_DM
IN0 NC
+,17
UART_TX
C1 C2 C3 C4 C5 C6 C7
DVDD33
VSSDVDD12VSS
DVDD33
+&6
UART_RX
B1 B2 B3 B4 B5 B6 B7
SM_MOSISM_MISOSM_CLK
GPIO_9/SM_CS
+&/. +',1 +'287
A1 A2 A3 A4 A5 A6 A7
Pin Descriptions
ZL38090 Preliminary Data Sheet Revision 2.0 30
10 Pin Descriptions
10.1 Reset Pin
10.2 DAC Pins
Table 6 • Reset Pin Description
QFN
Pin #
WLCSP
Ball Name Type Description
15 D6 RESET Input Reset. When low the device is in its reset state and all tristate
outputs will be in a high impedance state. This input must be high
for normal device operation.
A 10 KΩ pull-up resistor is required on this pin to DVDD33 if this pin
is not continuously driven.
Refer to Reset, page 22 for an explanation of the various reset
states and their timing.
Table 7 • DAC Pin Description
QFN
Pin #
WLCSP
Ball Name Type Description
6 – DAC1_M Output DAC 1 Minus Output. This is the negative output signal of the
differential amplifier of DAC 1. Pin functionality is firmware
dependent.
Not available on the WLCSP package.
7 C7 DAC1_P Output DAC 1 Plus Output. This is the positive output signal of the
differential amplifier of DAC 1. Pin functionality is firmware
dependent.
9 – DAC2_M Output DAC 2 Minus Output. This is the negative output signal of the
differential amplifier of DAC 2. Pin functionality is firmware
dependent.
Not available on the WLCSP package.
8 D7 DAC2_P Output DAC 2 Plus Output. This is the positive output signal of the
differential amplifier of DAC 2. Pin functionality is firmware
dependent.
12 F7 CDAC Output DAC Reference. This pin may require capacitive decoupling. Refer
to DAC Output, page 7.
13 G7 CREF Output Common Mode Reference. This pin requires capacitive
decoupling. Refer to DAC Output, page 7.
Pin Descriptions
ZL38090 Preliminary Data Sheet Revision 2.0 31
10.3 Microphone Pins
10.4 TDM and I2S Port Pins
The firmware supports a single TDM interface. The TDM block is capable of being a master or a slave.
The ports can be configured for Pulse-Code Modulation (PCM) or Inter-IC Sound (I2S) operation. The
ports conform to PCM, GCI, and I2S timing protocols.
Table 8 • Microphone Pin Description
QFN
Pin #
WLCSP
Ball Name Type Description
18 H6 DMIC_CLK Output Digital Microphone Clock Output. Clock output for digital
microphones and digital electret microphone pre-amplifier devices.
19 H3 DMIC_IN1 Input Digital Microphone Input 1. Stereo or mono digital microphone
input.
Tie to VSS if unused.
20 H2 DMIC_IN2 Input Digital Microphone Input 2. Stereo or mono digital microphone
input.
Tie to VSS if unused.
Table 9 • TDM and I2S Ports Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
29 E1 PCLK/
I2S_SCK
Input/
Output
PCM Clock (Input/Tristate Output). PCLK is equal to the bit rate of
signals DR/DX. In TDM master mode this clock is an output and in
TDM slave mode this clock is an input.
I2S Serial Clock (Input/Tristate Output). This is the I2S bit clock.
In I2S master mode this clock is an output and drives the bit clock
input of the external slave device’s peripheral converters. In I2S
slave mode this clock is an input and is driven from a converter
operating in master mode.
After power-up, this signal defaults to be an input in I2S slave mode.
A 100 KΩ pull-down resistor is required on this pin to VSS. If this pin
is unused, tie the pin to VSS.
When driving PCLK/I2S_SCK from a host, one of the following
conditions must be satisfied:
1. Host drives PCLK low during reset, or
2. Host tri-states PCLK during reset (the 100 KΩ resistor will
keep PCLK low), or
3. Host drives PCLK at its normal frequency
Pin Descriptions
ZL38090 Preliminary Data Sheet Revision 2.0 32
10.5 Headset Control/Indicator Pins
These pins are used for headset control functions and LED indicators.
30 F1 FS/I2S_WS Input/
Output
PCM Frame Sync (Input/Tristate Output). This is the TDM frame
alignment reference. This signal is an input for applications where
the PCM bus is frame aligned to an external frame signal (slave
mode). In master mode this signal is a frame pulse output.
I2S Word Select (Left/Right) (Input/Tristate Output). This is the
I2S left or right word select. In I2S master mode word select is an
output which drives the left/right input of the external slave device’s
peripheral converters. In I2S slave mode this pin is an input which is
driven from a converter operating in master mode.
After power-up, this signal defaults to be an input in I2S slave mode.
Tie this pin to VSS if unused.
31 G1 DR/I2S_SDI Input PCM Serial Data Stream Input. This serial data stream operates at
PCLK data rates.
I2S Serial Data Input. This is the I2S port serial data input.
Tie this pin to VSS if unused.
32 H1 DX/I2S_SDO Output PCM Serial Data Stream Output. This serial data stream operates
at PCLK data rates.
I2S Serial Data Output. This is the I2S port serial data output.
Table 10 • Headset Control/Indicator Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
41 E2 GPIO_7 Input/
Output
Hook Switch/Volume Down. Fixed function used to control the
hook state and volume down with GPIO[10:13].
43 D3 GPIO_8 Input/
Output
Microphone/Volume Up. Fixed function used to control the hook
state and volume down with GPIO[10:13].
44 E3 GPIO_10 Input/
Output
Volume Control/Call State. Fixed function used to control the
volume and indicate the call state with GPIO[7:8].
45 C3 GPIO_11 Input/
Output
Call Control/Volume State 1. Fixed function used to control the
hook switch (on/off) and control multicolor LEDs for volume
indication with GPIO[7:8].
47 – GPIO_12 Input/
Output
Volume State 2. Fixed function used to control multicolor LEDs for
volume indication with GPIO[7:8].
GPIO_12 is not available on the WLCSP package.
48 – GPIO_13 Input/
Output
Volume State 3. Fixed function used to control multicolor LEDs for
volume indication with GPIO[7:8].
GPIO_13 is not available on the WLCSP package.
Table 9 • TDM and I2S Ports Pin Descriptions (continued)
QFN
Pin #
WLCSP
Ball Name Type Description
Pin Descriptions
ZL38090 Preliminary Data Sheet Revision 2.0 33
10.6 USB Pins
These pins are used for USB functions.
10.7 HBI – SPI Slave Port Pins
This port functions as a peripheral interface for an external controller, and supports access to the internal
registers and memory of the device.
Table 11 • USB Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
25 H5 USB_DM Input/
Output
USB Data D- Signal. Carries USB data to/from USB 2.0.
26 G4 USB_RTUNE Input/
Output
Tx Resistor Tune. Connect to external 43.2 Ω resistor to VSS.
27 H4 USB_DP Input/
Output
USB Data D+ Signal. Carries USB data to/from USB 2.0.
40 E5 GPIO_6 Input/
Output
USB Resume. This pin is used to sense activity on USB Data D+ to
resume from sleep or perform a USB reset. It can be configured as
an input or output and is intended for low-frequency signaling.
Table 12 • HBI – SPI Slave Port Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
52 A1 HCLK Input HBI SPI Slave Port Clock Input. Clock input for the SPI Slave port.
Maximum frequency = 25 MHz.
This input should be tied to VSS in I2C mode, refer to Table 1,
page 16
Tie this pin to VSS if unused.
53 B1 HCS Input HBI SPI Slave Chip Select Input. This active low chip select signal
activates the SPI Slave port.
HBI I2C Serial Clock Input. This pin functions as the I2C_SCLK
input in I2C mode. A pull-up resistor is required on this node for I2C
operation.
Tie this pin to VSS if unused.
55 A2 HDIN Input HBI SPI Slave Port Data Input. Data input signal for the SPI Slave
port.
This input selects the slave address in I2C mode, refer to Tab l e 1 ,
page 16
Tie this pin to VSS if unused.
56 A3 HDOUT Input/
Output
HBI SPI Slave Port Data Output (Tristate Output). Data output
signal for the SPI Slave port.
HBI I2C Serial Data (Input/Output). This pin functions as the
I2C_SDA I/O in I2C mode. A pull-up resistor is required on this node
for I2C operation.
57 C1 HINT Output HBI Interrupt Output. This output can be configured as either
CMOS or open drain by the host.
Pin Descriptions
ZL38090 Preliminary Data Sheet Revision 2.0 34
10.8 Master SPI Port Pins
This port functions as the interface to an external Flash device used to optionally Auto Boot and load the
device’s firmware and configuration record from external Flash memory.
10.9 Oscillator Pins
These pins are connected to a 12.000 MHz crystal or clock oscillator which drives the device's internal
PLL.
10.10 UART Pins
The ZL38090 device incorporates a two-wire UART (Universal Asynchronous Receiver Transmitter)
interface with a fixed 115.2 K baud transfer rate, 8 data bits, 1 stop and no parity. The UART port can be
used as a debug tool and is used for tuning purposes.
Table 13 • Master SPI Port Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
1 A5 SM_CLK Output Master SPI Port Clock (Tristate Output). Clock output for the
Master SPI port. Maximum frequency = 8 MHz.
2 A6 SM_MISO Input Master SPI Port Data Input. Data input signal for the Master SPI
port.
3 A7 SM_MOSI Output Master SPI Port Data Output (Tristate Output). Data output signal
for the Master SPI port.
64 A4 GPIO_9/
SM_CS
Input/
Output
Master SPI Port Chip Select (Input Internal Pull-Up/Tristate
Output). Chip select output for the Master SPI port.
Shared with GPIO_9, see Table 16, page 35.
Table 14 • Oscillator Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
22 H7 XI Input Crystal Oscillator Input. Refer to External Clock Requirements,
page 42.
23 F5 XO Output Crystal Oscillator Output. Refer to External Clock Requirements,
page 42.
Table 15 • UART Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
50 B2 UART_RX Input UART (Input). Receive serial data in. This port functions as a
peripheral interface for an external controller and supports access
to the internal registers and memory of the device.
49 C2 UART_TX Output UART (Tristate Output). Transmit serial data out. This port
functions as a peripheral interface for an external controller and
supports access to the internal registers and memory of the device.
Pin Descriptions
ZL38090 Preliminary Data Sheet Revision 2.0 35
10.11 GPIO Pins
GPIO ports can be used for interrupt and event reporting, fixed function control, bootstrap options, as
well as being used for general purpose I/O for communication and controlling external devices. Pin
functionality is firmware dependent.
10.12 Supply and Ground Pins
Table 16 • GPIO Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
33, 34,
36
F4, E4, F3 GPIO_[0:2] Input/
Output
General Purpose I/O (Input Internal Pull-Down/Tristate Output).
These pins can be configured as an input or output and are
intended for low-frequency signaling. Refer to Ta b le 5 , page 26 for
bootstrap functionality.
37, 38,
39
F2, –,
F6
GPIO_[3:5] Input/
Output
General Purpose I/O (Input Internal Pull-Down/Tristate Output).
These pins can be configured as an input or output and are
intended for low-frequency signaling.
GPIO_4 is not available on the WLCSP package.
64 A4 GPIO_9/
SM_CS
Input/
Output
General Purpose I/O (Input Internal Pull-Down/Tristate Output).
This pin can be configured as an input or output and is intended for
low-frequency signaling.
Alternate functionality with SM_CS, see Table 13, page 34.
Table 17 • Supply and Ground Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
17 – EXT_SEL Input VDD +1.2 V Select. Select external +1.2 V supply. Tie to DVDD33 if
the +1.2 V supply is to be provided externally. Tie to VSS (0 V) if the
+1.2 V supply is to be generated internally.
Refer to Power Supply Considerations, page 23 for more
information.
Not available on the WLCSP package.
16 – VDD12_CTRL Output VDD +1.2 V Control. Analog control line for the voltage regulator
external FET when EXT_SEL is tied to VSS. When EXT_SEL is tied
to DVDD33, the VDD12_CTRL pin becomes a CMOS output which
can drive the shutdown input of an external LDO.
Refer to Power Supply Considerations, page 23 for more
information.
Not available on the WLCSP package.
4, 14,
24, 42,
58
B5, D1,
G5, G6
DVDD12 Power Core Supply. Connect to a +1.2 V ±5% supply.
Place a 100 nF, 20%, 10 V, ceramic capacitor on each pin
decoupled to the VSS plane.
Refer to Power Supply Considerations, page 23 for more
information.
5, 21,
35, 46,
51, 59
B3, B7,
G3
DVDD33 Power Digital Supply. Connect to a +3.3 V ±5% supply.
Place a 100 nF, 20%, 10 V, ceramic capacitor on each pin
decoupled to the VSS plane.
28 – DVDD33_
XTAL
Power Crystal Digital Supply. This pin must be connected to a +3.3 V
supply source capable of delivering 10 mA.
Not available on the WLCSP package.
Pin Descriptions
ZL38090 Preliminary Data Sheet Revision 2.0 36
10.13 No Connect Pins
10.14 IN0 Pins
These pins are to be tied to Ground only.
10, 11 E7 AVDD33 Power Analog Supply. Connect to a +3.3 V ±5% supply.
Place a 100 nF, 20%, 10 V, ceramic capacitor on each pin
decoupled to the VSS plane.
54 B4, B6,
D2, D4,
E6, G2
VSS Ground Ground. Connect to digital ground plane.
– Exposed
Ground Pad
Ground Exposed Pad Substrate Connection. Connect to VSS. This pad is
at ground potential and must be soldered to the printed circuit board
and connected via multiple vias to a heatsink area on the bottom of
the board and to the internal ground plane.
Not available on the WLCSP package.
Table 18 • No Connect Pin Description
QFN
Pin #
WLCSP
Ball Name Type Description
63 C6 No Connection. This pins is to be left unconnected, do not use as a
tie point.
Table 19 • IN0 Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
60, 61,
62
C4, C5,
D5
IN0 Input IN0. Tie these pins to Ground.
Table 17 • Supply and Ground Pin Descriptions (continued)
QFN
Pin #
WLCSP
Ball Name Type Description
Electrical Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 37
11 Electrical Characteristics
11.1 Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
11.2 Thermal Resistance
11.3 Operating Ranges
Microsemi guarantees the performance of this device over the industrial (−40 °C to 85 °C) temperature
range by conducting electrical characterization over each range and by conducting a production test with
single insertion coupled to periodic sampling. These characterization and test procedures comply with
the Telcordia GR-357-CORE Generic Requirements for Assuring the Reliability of Components Used in
Telecommunications Equipment.
Table 20 • Absolute Maximum Ratings
Supply voltage (DVDD33, AVDD33) −0.5 to +4.0 V
Core supply voltage (DVDD12) −0.5 to +1.32 V
Input voltage −0.5 to +4.0 V
Continuous current at digital outputs 15 mA
Reflow temperature, 10 sec., MSL3, per JEDEC J-STD-020 260 °C
Storage temperature −55 to +125 °C
ESD immunity (Human Body Model) JS-001-2014 Class 1C compliant
Table 21 • Thermal Resistance
Junction to ambient thermal resistance1, θJA
1. The thermal specifications assume that the device is mounted on an effective thermal conductivity test board (4 layers, 2s2p) per
JEDEC JESD51-7 and JESD51-5
64-pin QFN 22.1 °C/W
56-ball WLCSP 33.8 °C/W
Junction to board thermal resistance1,<Footnote> θJB 64-pin QFN 6.1 °C/W
56-ball WLCSP 3.9 °C/W
Junction to exposed pad thermal resistance1, θJC 64-pin QFN 2.0 °C/W
Junction to case thermal resistance1, θJC 56-ball WLCSP 5.2 °C/W
Junction to top characterization parameter, ΨJT 64-pin QFN 0.1 °C/W
56-ball WLCSP 0.3 °C/W
Table 22 • Operating Ranges
Parameter Symbol Min. Typ. Max. Units
Ambient temperature TA−40 +85 °C
Electrical Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 38
11.4 Device Power States
The ZL38090 operates in one of four hardware power states. These power states are defined as
Working, Sleep, Reset, and USB Suspend. The current consumed by the ZL38090 is dependent upon
the power state and the active firmware mode. Typical current consumption for all firmware modes and
hardware states are shown in Table 23, page 39. Refer to the Microsemi AcuEdge™ Firmware Manual
for programming and additional information on the firmware modes.
11.4.1 Working State
In the Working state, the ZL38090 is awake and running. In simple terms, the device is “on”. Device
features are enabled and supported depending on the firmware and configuration settings.
There are two modes of operation in the ZLS38090firmwareNormal Mode and Power Saving Mode. Both
modes support the full complement of firmware audio processing features.
Normal Mode is recommended for applications that use the internal voltage regulator with analog
microphones. Normal Mode keeps the Audio Processor always on, thereby minimizing +1.2 V power
supply noise that could be injected into sensitive analog microphone circuitry via the board layout.
Power Saving Mode can be enabled by setting register 0x206 (System Control Flags) bit 0, or it can be
selected from the ZLS38508 MiTuner™ GUI in the AEC Control window (Enable Power Saving Mode).
This mode disables the audio processor block when idle, reducing the average current drawn from the
+1.2 V power supply. The resulting trade-off is switching noise on this supply. Because of this, Power
Saving Mode is not recommended for applications that use the internal voltage regulator with analog
microphones.
11.4.2 USB Suspend State
USB Suspend is used to conserve power when a quick response is required. The Audio Processor is
made inactive and the internal clocks are shut down. The ZL38090 will respond to no other inputs until it
awakens from USB Suspend mode. In accordance with the USB specification, the ZL38090 will respond
to activity on the USB bus to wake from USB Suspend state. The firmware and configuration records
loaded into the device RAM are retained and no re-boot is required.
11.4.3 Reset State
Reset is a hardware state used to further conserve power. The +1.2V supply can be removed. The
firmware and configuration records loaded into the device RAM are not retained in Reset and must be
reloaded when the device is brought out of Reset. See Reset, page 22 for more information and refer to
Power Supply, page 23 for information on +1.2 V removal.
Analog supply voltage VAVDD33 3.135 3.3 3.465 V
Digital supply voltage VAVDD33
Crystal Digital supply voltage VDVDD33_XTAL
Crystal I/O voltage VXI 2.5 2.625 V
Core supply voltage VDVDD12 1.14 1.2 1.26 V
Table 22 • Operating Ranges (continued)
Parameter Symbol Min. Typ. Max. Units
Electrical Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 39
11.4.4 Current Consumption
Device current consumption can vary with the firmware load. Common values are listed here using an
external +1.2 V supply for the core power supply with a 12.000 MHz crystal and a 3.3 KΩ resistor from
GPIO_2 to DVDD33 (external Flash selected), unless otherwise noted.
11.5 DC Specifications
Typical values are for TA = 25 ºC and nominal supply voltage. Minimum and maximum values are over
the industrial −40 ºC to 85 ºC temperature range and supply voltage range as shown in Operating
Ranges, page 37, except as noted. A 12.000 MHz clock oscillator is active.
Table 23 • Current Consumption
+3.3 V1
1. Table values include all current entering DVDD33, AVDD33, and DVDD33_XTAL pins. Add 1.0 mA to Normal, Power Saving,
and USB Suspend modes if the internal voltage regulator is used (EXT_SEL = VSS).
+1.2 V2
2. Core supply voltage. Table values include all current entering DVDD12 pins.
Device Power State Typ. Max. Typ. Max. Units Notes / Conditions
Working state, Normal Mode 21 115 mA Firmware active, Power Saving off, 1
DAC active3, 2 MICs active4.
3. DAC in differential mode, for 2 DACs active in differential mode, add 3.6 mA to +3.3 V current.
4. DMIC_IN active.
Working state, Power Saving
Mode
21 85 Firmware active, Power Saving on, 1
DAC active3, 2 MICs active4.
USB Suspend state 0.68 3.4 Firmware inactive (firmware and
configuration record are retained),
DACs and MICs are powered down.
Reset state 100 0 µA Device in reset (reset > 10 µS), DVDD12
removed5.
5. DVDD12 is removed if the internal regulator is used for +1.2 V generation or if the VDD12_CTRL pin is used to shutdown an
external +1.2 V LDO that provides DVDD12 to the ZL38090.
Table 24 • DC Specifications
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
Input high voltage VIH 0.7 ×
VDVDD33
VDVDD33 +
0.3
V All digital inputs
Input low voltage VIL VVSS − 0.3 0.3 ×
VDVDD33
V All digital inputs
Input hysteresis voltage VHYS 0.4 V
Input leakage (input pins) IIL 5 µA 0 to +3.3 V
Input leakage (bi-directional pins) IBL 5 µA 0 to +3.3 V
Weak pull-up current IPU 38 63 101 µA Input at 0 V
Weak pull-down current IPD 19 41 158 µA Input at +3.3 V
Input pin capacitance CI5pF
Output high voltage VOH 2.4 V At 12 mA
Output low voltage VOL 0.4 V At 12 mA
Output high impedance leakage IOZ 5 µA 0 to +3.3 V
Pin capacitance (output &
input/tristate pins)
CO5pF
Electrical Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 40
11.6 AC Specifications
For all AC specifications, typical values are for TA = 25 °C and nominal supply voltage. Minimum and
maximum values are over the industrial −40 °C to 85 °C temperature range and supply voltage ranges as
shown in Operating Ranges, page 37, except as noted. A 12.000 MHz clock oscillator is active with Two-
Way Voice Communication firmware in Normal, Wideband operational mode.
11.6.1 Microphone Interface
AC specifications for microphone interface.
11.6.2 DAC
Measurements taken using PCM mode. THD+N versus output power for speaker drive applications
presented in Figure 30, page 41; THD+N versus output voltage for amplifier drive applications presented
in Figure 31, page 42.
Output rise time tRT 1.25 ns 10% to 90%,
CLOAD = 20 pF
Output fall time tFT 1.25 ns 90% to 10%,
CLOAD = 20 pF
Table 25 • Microphone Interface
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
Microphone clock output
(DMIC_CLK),
8 kHz, 16 kHz sample rate 1.024 MHz
48 kHz sample rate 3.072 MHz
DMIC_CLK, Output high current IOH 20 mA VOH = DVDD33 − 0.4 V
DMIC_CLK, Output low current IOL 30 mA VOL = 0.4 V
DMIC_CLK, Output rise and fall
time
tR, tF5nSC
LOAD = 100 pF
Table 26 • DAC
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
DAC output level: DAC gain = 1, 1 KΩ load.
Full scale: Differential VDACFS 4.8 VPP
Single-ended 2.4
0 dBm0: Differential 2.8
Single-ended 1.4
PCM full scale level (Vppd value) 9 dBm0 DAC gain = 1, 600 Ω load
DAC output power: 1,
Single-ended loads driven
capacitively to ground
Single-ended, 32 ohm load 20.6 24 mW
Single-ended, 16 ohm load 37.5 47
Differential, 32 ohm load 86.0 94
Table 24 • DC Specifications (continued)
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
Electrical Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 41
1. Guaranteed by design, not tested in production.
2. Single-ended or differential output.
Figure 30 • THD+N Ratio versus Output Power – Driving Low Impedance
Frequency response:
Sample rate = 48 kS/s
fR20 20000 Hz 1,3 dB cutoff includes
external AC coupling,
without AC coupling the
response is low pass.
Dynamic range:
Sample rate = 48 kS/s
92 dBFS 20 Hz ‒ 20 kHz
Total harmonic distortion plus
noise
THD + N −82 dBFS 2, Input = −3 dBFS.
Signal to Noise Ratio SNR 85 dB 2,1004 Hz, C-message
weighted
Allowable capacitive load to
ground
CL100 pF 1, At each DAC output.
Power supply rejection ratio PSRR 70 dB 1, 20 Hz - 100 kHz,
100 mVpp supply noise.
Crosstalk −85 −70 dB 1, Between DAC outputs.
Table 26 • DAC (continued)
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
Electrical Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 42
Figure 31 • THD+N Ratio versus VRMS – Driving High Impedance
11.7 External Clock Requirements
In all modes of operation the ZL38090 requires an external clock source. The external clock drives the
device’s internal PLL which is the source for the internal timing signals.
The external clock source can either be:
• 12.000 MHz crystal, or
• 12.000 MHz clock oscillator with a 2.5 V output
The following sections discuss these options.
11.7.1 Crystal Application
The oscillator circuit that is created across pins XI and XO requires an external fundamental mode crystal
that has a specified parallel resonance (fP) at 12.000 MHz.
0.001
0.01
0.1
1
10
00.511.52
THD+N(%)
Vrms
100KDifferential
100KSingleEnded
Electrical Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 43
Figure 32 • Crystal Application Circuit
11.7.2 Clock Oscillator Application
Figure 33, page 43 illustrates the circuit that is used when the ZL38090 external clock source is a clock
oscillator. The oscillator pins are 2.5 V compliant and should not be driven from 3.3 V CMOS without a
level shifter or voltage attenuator.
Figure 33 • Clock Oscillator Application Circuit
ZL38090
DVDD33_XTAL
+3.3 V
XI
XO
Crystal
DVDD33
PLL
12.000 MHz
20 pF 20 pF
Supply decoupling is not shown
PCLK/I2S_SCK
100K
PCLK/I2S_SCK (if used)
GND (VSS)
ZL38090
DVDD33_XTAL
+3.3 V
XI
XO
VDD
DVDD33
PLL
100 nF
12.000
MHz
Oscillator
2.5 V
Output
Supply decoupling is not shown
GND (VSS
)
PCLK/I2S_SCK
100K
PCLK/I2S_SCK (if used)
Electrical Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 44
11.7.3 AC Specifications - External Clocking Requirements
These specifications apply to crystal and clock oscillator external clocking.
Table 27 • AC Specifications – External Clocking Requirement
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
External clocking frequency
accuracy
AOSC −50 50 ppm Not tested in production.
External clocking duty cycle DCOSC 40 60 %
PCLK input jitter 1 nspp
PCLK output jitter (master mode) 0.75 nspp
PCLK input jitter 200 μs
Holdover accuracy 50 ppm
Timing Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 45
12 Timing Characteristics
Figure 34 depicts the timing reference points that apply to the timing diagrams shown in this section. For
all timing characteristics, typical values are for TA = 25 °C and nominal supply voltage. Minimum and
maximum values are over the industrial −40 °C to 85 °C temperature range and supply voltage ranges as
shown in Operating Ranges, page 37, except as noted.
Figure 34 • Timing Parameter Measurement Digital Voltage Levels
12.1 TDM Interface Timing Parameters
12.1.1 GCI and PCM Timing Parameters
Specifications for GCI and PCM timing modes are presented in the following table. The specifications
apply to both port A and port B in slave operation.
A timing diagram that applies to GCI timing of the TDM interface is illustrated in Figure 35, page 46.
Timing diagrams that apply to PCM timing of the TDM interface are illustrated in Figure 36, page 46 and
Figure 37, page 47.
Table 28 • GCI and PCM Timing Parameters
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
PCLK period tPCY 122 7812.5 ns 1, 2
1. PCLK frequency must be within 100 ppm.
2. CLOAD = 40 pF
PCLK High pulse width tPCH 48 2
PCLK Low pulse width tPCL 48 2
Fall time of clock tPCF 8
Rise time of clock tPCR 8
FS delay (output rising or falling) tFSD 215 2
225 3
FS setup time (input) tFSS 54
FS hold time (input) tFSH 0.5 125000 − 2tPCY 4
Data output delay tDOD 215 2
225 5
Data output delay to High-Z tDOZ 010 5
Data input setup time tDIS 54
Data input hold time tDIH 04
Allowed PCLK jitter time tPCT 20 Peak-to-peak
Allowed Frame Sync jitter time tFST 20 Peak-to-peak
All Digital
Signals
Timing Reference Points
TiRF/ToRF
VH
M
VLM
VT
T
iRF
/T
oRF
Timing Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 46
Figure 35 • GCI Timing, 8-bit
Figure 36 • PCM Timing, 8-bit with xeDX = 0 (Transmit on Negative PCLK Edge)
3. CLOAD = 150 pF
4. Setup times based on 2 ns PCLK rise and fall times; hold times based on 0 ns PCLK rise and fall times.
5. Guaranteed by design, not tested in production.
V
IH
V
IL
V
IH
First
Bit
V
OL
V
OH
P
CLK
FS
DX
DR
t
FSS
t
PCR
t
PCY
t
PCF
t
PCH
t
PCL
t
FSH
t
DOD
t
DIH
t
DIS
t
DOZ
Time Slot Zero, Clock Slot Zero
First
Bit
Second
Bit
V
IL
Time Slot Zero, Clock Slot Zero
First
Bit
P
CLK
FS
DX
First
Bit
Second
Bit
V
OL
V
OH
V
IH
V
IL
V
IH
V
IL
DR
tFSS
tPCR
tPCY
tPCF
tPCH
tPCL
tFSH
tDOD
tDIH
tDIS
tDOZ
Timing Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 47
Figure 37 • PCM Timing, 8-bit with xeDX = 1 (Transmit on Positive PCLK Edge)
12.1.2 I2S Timing Parameters
12.1.2.1 I2S Slave
Specifications for I2S Slave timing are presented in the following table. The specifications apply to both
port A and port B. A timing diagram for the I2S Slave timing parameters is illustrated in Figure 38,
page 48.
Table 29 • I2S Slave Timing Specifications
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
I2S_SCK Clock Period
fs = 48 kHz tISSCP 651.04 ns
fs = 8 kHz 3.91 µs
I2S_SCK Pulse Width High
fs = 48 kHz tISSCH 292.97 358.07 ns
fs = 8 kHz 1.76 2.15 µs
I2S_SCK Pulse Width Low
fs = 48 kHz tISSCL 292.97 358.07 ns
fs = 8 kHz 1.76 2.15 µs
I2S_SDI Setup Time tISDS 5ns
I2S_WS Setup Time tISDS 5ns
I2S_SDI Hold Time tISDH 0ns
I2S_WS Hold Time tISDH 0.5 ns
I2S_SCK Falling Edge to
I2S_SDO Valid
tISOD 215nsC
LOAD = 40 pF
VIH
VIL
VIH
First
Bit
VOL
VOH
P
CLK
FS
DX
DR
t
FSS
t
PCR
t
PCY
t
PCF
t
PCH
t
PCL
t
FSH
t
DOD
t
DIH
t
DIS
t
DOZ
Time Slot Zero, Clock Slot Zero
First
Bit
Second
Bit
VIL
Timing Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 48
Figure 38 • Slave I2S Timing
12.1.2.2 I2S Master
Specifications for I2S Master timing are presented in the following table. The specifications apply to both
port A and port B. A timing diagram for the I2S Master timing parameters is illustrated in Figure 39.
Figure 39 • Master I2S Timing
Table 30 • I2S Master Timing Specifications
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
I2S_SCK Clock Period
fs = 48 kHz tIMSCP 651.04 ns
fs = 8 kHz 3.91 µs
I2S_SCK Pulse Width High
fs = 48 kHz tIMSCH 318.0 333.0 ns
fs = 8 kHz 1.95 1.96 µs
I2S_SCK Pulse Width Low
fs = 48 kHz tIMSCL 318.0 333.0 ns
fs = 8 kHz 1.95 1.96 µs
I2S_SDI Setup Time tIMDS 5ns
I2S_SDI Hold Time tIMDH 0ns
I2S_SCK Falling Edge to I2S_WS tIMOD 215nsC
LOAD = 40 pF
I2S_SCK Falling Edge to
I2S_SDO Valid
tIMOD 215nsC
LOAD = 40 pF
t
ISOD
tISDS
tISDH
tISSCL
tISSCH
tISSCP
I2S_SDI
I2S_SDO
(input)
(output)
I
2S_SCK
(input)
I2S_WS
(input)
tIMDS
tIMDH
tIMOD tIMSCP
tIMSCH tIMSCL
I2S_SDI
I2S_SDO
(input)
(output)
I2S_
SCK
(output)
I2S_WS
(output)
Timing Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 49
12.2 Host Bus Interface Timing Parameters
The HBI is the main communication port from the host processor to the , this port can read and write all
of the memory and registers on the . The port can be configured as SPI Slave or I2C Slave.
For fastest command and control operation, use the SPI Slave configuration. The SPI Slave can be
operated with HCLK speeds up to 25 MHz; the I2C Slave will operate with HCLK speeds up to 400 kHz.
12.2.1 SPI Slave Port Timing Parameters
The following table describes timing specific to the device. A timing diagram for the SPI Slave timing
parameters is illustrated in Figure 40, page 50.
For seamless control operation, both the SPI Slave timing and the system timing need to be considered
when operating the SPI Slave at high speeds. System timing includes host set-up and delay times and
board delay times.
1. HCLK may be stopped in the high or low state indefinitely without loss of information. When HCS is at low state, every 16 HCLK
cycles, the 16-bit received data will be interpreted by the SPI interface logic.
2. The first data bit is enabled on the falling edge of HCS or on the falling edge of HCLK, whichever occurs last.
3. The SPI Slave requires 61 ns HCS off time just to make the transition of HCS synchronized with HCLK clock. In the command
framing mode, there is no HCS off time between each 16-bit command/data, and HCS is held low until the end of command.
4. If HCS is not held low for 8 or 16 HCLK cycles exactly, the SPI Slave will reset. During byte or word framing mode, HCS is held
low for the whole duration of the command. Multiple commands can be transferred with HCS low for the whole duration of the
multiple commands. The rising edge of the HCS indicates the end of the command sequence and resets the SPI Slave.
5. Guaranteed by design, not tested in production.
Table 31 • SPI Slave Port Timing Parameters
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
HCLK Clock Period tSSCP 40 ns
HCLK Pulse Width High tSSCH 16 tSSCP/2 1
HCLK Pulse Width Low tSSCL 16 tSSCP/2 1
HDIN Setup Time tSSDS 5
HDIN Hold Time tSSDH 0
HCS Asserted to HCLK Rising Edge:
Write tSHCSC 5t
SSCP/2
Read if host samples on falling edge 5 tSSCP/2
Read if host samples on rising edge tSSFD +
host
HDOUT
setup time
to HCLK
tSSFD +
tSSCP/2
HCLK Driving Edge to HDOUT Valid tSSOD 215C
LOAD = 40 pF
HCS Falling Edge to HDOUT Valid tSSFD 015
2, CLOAD = 40 pF
HCS De-asserted to HDOUT Tristate tSSOZ 010
5, CLOAD = 40 pF
HCS Pulse High tSHCSH 20 tSSCP/2 1, 3
HCS Pulse low tSHCSL 4
Timing Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 50
Figure 40 • SPI Slave Timing
12.2.2 I2C Slave Interface Timing Parameters
The I2C interface uses the SPI Slave interface pins.
Specifications for I2C interface timing are presented in the following table. A timing diagram for the I2C
timing parameters is illustrated in Figure 41, page 51.
Table 32 • I2S Slave Timing Specifications
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
SCLK Clock Frequency fSCL 0 400 kHz
START Condition Hold Time tSTARTH 0.6 µs
SDA data setup time tSDAS 100 ns
SDA Hold Time Input tSDAH 100 ns
SDA Hold Time Output tSDAH 300 ns
High period of SCLK tSCLH 0.6 µs
Low period of SCLK tSCLL 1.3 µs
STOP Condition Setup Time tSTOPS 0.6 µs
Repeated Start Condition Setup
Time
tSTARTS 0.6 µs
Pulse Width Spike Suppression,
glitches ignored by input filter
tSP 50 ns
HCS
HCLK
HDOU
T
HDI
N
tSSDS
tSSCH tSSCL
tSSDH
tSHCSC
tSSCP
tSSOZ
tSHCSH
tSSOD
tSSFD
t
SHCSL
Timing Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 51
Figure 41 • I2C Timing Parameter Definitions
12.3 UART Timing Parameters
Specifications for UART timing are presented in the following table. Timing diagrams for the UART timing
parameters are illustrated in Figure 42 and Figure 43.
Figure 42 • UART_RX Timing
Figure 43 • UART_TX Timing
Table 33 • UART Timing Specifications
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
UART_RX and UART_TX bit
width Baud rate = 115.2 kbps
tUP 8.68 µs
Allowed baud rate deviation 8 bits
with no parity
4.86 % Guaranteed by design, not
tested in production.
I2C_SCLK
I2C_SDA
(With Start/Stop)
I2C_SDA
(
With Start/Repeated Start)
f
SCL
t
SCLL
t
SCLH
t
STARTH
t
SDAS
t
SDAH
t
STOPS
t
STARTS
UA
RT_RX
t
UP
t
UIA
1 Stop bit example
UA
RT_TX
t
UP
Timing Characteristics
ZL38090 Preliminary Data Sheet Revision 2.0 52
12.4 Master SPI Timing Parameters
Specifications for Master SPI timing are presented in the following table. A timing diagram for the Master
SPI timing parameters is illustrated in Figure 44.
Figure 44 • Master SPI Timing
Table 34 • Master SPI Timing Specifications
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
SM_CLK Clock Period tMSCP 40 320 ns Max. 25.0 MHz
SM_CLK Pulse Width High tMSCH (tMSCP/2) − 2 160
SM_CLK Pulse Width Low tMSCL (tMSCP/2) − 2 160
SM_MISO Setup Time tMSDS 3
SM_MISO Hold Time tMSDHD 0
SM_CS Asserted to SM_CLK
Sampling Edge
tMSCC (tMSCP/2) − 4
SM_CLK Driving Edge to
SM_MOSI Valid
tMSOD −1 2 CLOAD = 40 pF
SM_MOSI Setup to SM_CLK
Sampling Edge
tMSOS (tMSCP/2) − 4 CLOAD = 40 pF
SM_MOSI Hold Time to SM_CLK
Sampling Edge
tMSOHD (tMSCP/2) − 4 CLOAD = 40 pF
SM_CS Hold Time after last
SM_CLK Sampling Edge
tMSCSHD (tMSCP/2) − 4
SM_CS Pulse High tMSCSH (tMSCP/2) − 2
SM_CS
S
M_CLK
SM_MIS
O
SM_MOS
I
S
M_CLK
tMSDS
tMSCH tMSCL
tMSDHD
tMSCC
tMSCP tMSCSHD
tMSOD tMSOHD
tMSCSH
tMSOS
Package Outline Drawings
ZL38090 Preliminary Data Sheet Revision 2.0 53
13 Package Outline Drawings
13.1 Package Drawings
Figure 45 • 64-Pin QFN
Package Outline Drawings
ZL38090 Preliminary Data Sheet Revision 2.0 54
Figure 46 • Recommended 64-Pin QFN Land Pattern – Top View
64-QFN
9 mm x 9 mm, 0.5 mm pitch
Recommended EPAD configuration uses 0.292"/7.42 mm square pad tied to a ground plane with
a 9 x 9 array of 0.013"/0.33 mm vias. This is necessary for good thermal performance.
* Minimum spacing between pins and epad must be 0.3 mm
EPAD 0.292"/7.42 mm
square pad
0.013"/0.33 mm drill
tied to ground plane,
9 x 9 array
0.0197"/0.5 mm
0.1772"/4.5 mm
Pad and Pastemask
30 mil x 10 mil
Soldermask 35 mil x 15 mil
SOLDER MASK and EPAD
0
.3543"/9 mm
1
0.0125"/0.318 mm
0.3 mm min*
EPAD solder mask
0.287" sq/7.29 mm
0.3543"/9 mm
EPAD 0.292"/7.42 mm
square pad
EPAD solder mask
0.287"/7.29 mm sq
Package Outline Drawings
ZL38090 Preliminary Data Sheet Revision 2.0 55
Figure 47 • 56-Ball WLCSP
Package Outline Drawings
ZL38090 Preliminary Data Sheet Revision 2.0 56
Figure 48 • 56-Ball WLCSP Staggered Balls Expanded Bottom View
Package Outline Drawings
ZL38090 Preliminary Data Sheet Revision 2.0 57
