Preliminary Rev. 0.91 11/02 Copyright © 2002 by Sili con Laboratories Si3220/Si3225-DS091
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si3220/Si3225
DUAL PROSLIC™ PROGRAMMABLE CMOS SLIC/CODEC
Features
Applications
Description
The Dual ProSLIC is a series of low-voltage CMOS devices that integrate both
SLIC and codec functionality into a single IC to provide a compl ete dual-channel
analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI
specifications. The Si3220 includes internal ringing generation to eliminate
centralized ringers and ringing relays, and the Si3225 supports centralized ringing
for long loop and legacy applications. On-chip subscriber loop and audio testing
allows remote diagnostics and fault detection with no external test equipment or
relays. The Si3220 and Si3225 operate from a single 3.3 V or 5 V supply and
interface to standard PCM/SPI or GCI bus digital interfaces. The Si320 0 linefeed
interface IC performs all high voltage functions and operates fro m a 3.3 V or 5 V
supply as well as single or dual battery supplies up to 100 V. The Si3220 and
Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200 is
available in a thermally enhanced 16-pin small outline (SOIC) package.
Functional Block Diagram
!Performs all BORSCHT functions
!Ideal for applications up to 18 kft
!Internal balanced ringing to 65 Vrms
(Si3220)
!External bulk ringer support (Si32 25)
!Low standby power consumption:
<65 mW per channel
!Software programmable parameters:
" Ringing frequency, amplitude, cadence,
and waveshape (Si3220)
" Two-wire ac impedance
" Transhybrid ba l a nce
" DC current loop feed (18–45 mA)
" Loop closure and ring trip thresholds
" Ground key detect threshold
!Automatic switching of up to three battery
supplies
!On-hook transmission
!Loop or ground start operation with
smooth/abrupt polarity reversal
!Modem/fax tone detection
!DTMF generation/decoding
!Dual tone generators
!A-Law/µ-Law, linear PCM
companding
!PCM and SPI bus digital interfaces
with programmable interru pts
!GCI/IOM-2 mode support
!3.3 or 5 V operation
!GR-909 loop diagnostics
!Audio diagnostics with loopback
!12 kHz/16 kHz pulse metering
(Si3220)
!FSK caller ID generation
!Digital loop carriers
!Central Office telephony
!Pair gain remote terminals
!Wireless local loop
!Public Branch Exchange (PBX) systems
!Cable telephony
!Voice over IP/voice over DSL
!ISDN terminal adapters
text
DAC
ADC
Linefeed
Control
Linefeed
Monitor
DAC
ADC
Linefeed
Control
Linefeed
Monitor
SLIC A
SLIC B
Codec A
Codec B
DSP
SPI
Control
Interface
PCM /
GCI
Interface
PLL
Si3220/25
Si3200
Linefeed
Interface
Si3200
Linefeed
Interface
2-Wire AC
Impedance
Hybrid Balanc e
Pulse Met ering
Subscri ber Li ne
Diagnostics
DTMF Decode
Programmable
Audio Filters
Gain Adjust
Dual Tone
Generators
Modem Tone
Detection
Ringing
Generator
& Ring Trip
Sense
Loop Closure,
& Ground Key
Detection
FSK
Caller ID
Relay Drivers
CS
SCLK
SDO
SDI
DTX
DRX
FSYNC
INT RESET
PCLK
TIP
Channel A
RING
TIP
RING
Channel B
Patents pending
Ordering Information
See page 105.
Part
Number Ringing
Method
Si3220 Internal
Si3225 External
Ringer
PRELIMINARY DATA SHEET
Si3220/Si3225
2 Preliminary Rev. 0.91
Dual ProSLIC Selection Guide
Part
Number Description On-Chip
Ringing External
Ringing
Support
Pulse
Metering Temp
Range Package
Si3200-KS Linefeed interface 0 to 70 °CSOIC-16
Si3200-BS Linefeed interface –40 to 85 °CSOIC-16
Si3220-KQ Dual ProSLIC ""
0 to 70 °CTQFP-64
Si3220-BQ Dual ProSLIC ""
–40 to 85 °CTQFP-64
Si3225-KQ Dual ProSLIC "0 to 70 °CTQFP-64
Si3225-BQ Dual ProSLIC "–40 to 85 °CTQFP-64
Si3220/Si3225
Preliminary Rev. 0.91 3
TABLE OF CONTENTS
Section Page
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Dual ProSLIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Automatic Dual Battery Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Ringing Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Ring Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Relay Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Modem Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Audio Path Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PCM Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8-Bit Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
16-Bit RAM Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Pin Descriptions: Si3220/25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Dual ProSLIC Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Si3220/Si3225
4 Preliminary Rev. 0.91
Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter Symbol Test Condition Value Unit
Supply Voltage, Si3200 and Si3220/
Si3225 VDD, VDD1–VDD4 –0.5 to 6.0 V
High Battery Supply Voltage, Si32002VBATH Continuous 0.4 to –104 V
10 ms 0.4 to –109
Low Battery Supply Voltage, Si3200 VBAT,VBATL Continuous VBATH V
TIP or RING Voltage, Si3205 VTIP,VRING Continuous
Pulse < 10 µs
Pulse < 4 µs
–104
VBATH –15
VBATH –35
TIP, RING Current, Si3200 ITIP, IRING ±100 mA
STIPAC, STIPDC, SRINGAC,
SRINGDC Current, Si3220/Si3225 ±20 mA
Input Current, Digital Input Pins IIN Continuous ±10 mA
Digital Input Voltage VIND –0.3 to (VDDD + 0.3) V
Operating Temperature Range TA–40 to 100 °C
Storage Temperature Range TSTG –40 to 150 °C
Si3220/Si3225 Thermal Resistance,
Typical3 (TQFP-64 ePad) θJA 25 °C/W
Si3200 Thermal Resistance, Typical3
(SOIC-16 ePad) θJA 65 °C/W
Continuous Power Dissipation,
Si32004PDTA = 85 °C, SOIC-16 0.85 W
Continuous Power Dissipation,
Si3220/25 PDTA = 85 °C, TQFP-64 1.6 W
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. The dv/dt of the voltage applied to the VBAT, VBATH, and VBATL pins must be limited to 10 V/µs.
3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
4. On-chip thermal limiting circuitry will shut down the circuit at a junctio n temperature of approximately 150 °C. For
optimal reliability, opera tion above 140 °C junction temperature should be avoided.
Si3220/Si3225
Preliminary Rev. 0.91 5
Table 2. Recommended Operating Conditions
Parameter Symbol Test
Condition Min*Typ Max*Unit
Ambient Temperature TAK-grade 0 25 70 oC
Ambient Temperature TAB-grade –40 25 85 oC
Supply Voltage, Si3220/Si3225 VDD1–VDD4 3.13 3.3/5.0 5.25 V
Supply Voltage, Si3200 VDD 3.13 3.3/5.0 5.25 V
High Battery Supply Voltage, Si3200 VBATH –15 — –99 V
Low Battery Supply Voltage, Si3200 VBATL –15 — VBATH V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typ ical values apply at nominal supply voltages and an operating temperature of 25 oC unless otherwise stated.
Table 3. 3.3 V Power Supply Characteristics*
(VDD, VDD1–VDD4 = 3.3 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
VDD1–VDD4 Supply
Current (Si3220/Si3225) IVDD1–IVDD4 Sleep mode, RESET = 0 — 1 — mA
Open (high-impedance) — 15 — mA
Active on-hook standby — 15 — mA
Forward/reverse active off-hook no
ILOOP, ABIAS = 4 mA —40—mA
Forward/reverse active OHT
OBIAS = 4 mA —44—mA
Ringing, VRING = 45 Vrms, VBAT = –
70 V, Sine Wave, 1 REN load —28—mA
VDD Supply Current
(Si3200) IVDD Sleep mode, RESET = 0 — 110 — µA
Open (high-impedance) — 110 — µA
Active on-hook standby — 110 — µA
Forward/reverse active off-hook, no
ILOOP, ABIAS = 4 mA, VBAT = –24 V —110—µA
Forward/reverse OHT, OBIAS = 4 mA,
VBAT = –70 V —110—µA
Ringing, VRING = 45 Vrms,
VBAT = –70 V,
Sine Wave, 1 REN load
—110—µA
*Note: All specifications are for a single channel based on measurements with both channels in the same operating state.
Si3220/Si3225
6 Preliminary Rev. 0.91
VBAT Supply Current
(Si3200) IVBAT Sleep mode, RESET=0, VBAT = –70 V — 100 — µA
Open (high-impedance), VBAT = –70 V — 225 — µA
Active on-hook standby, VBAT = –70 V — 400 — µA
Forward/reverse active off-hook no
ILOOP, ABIAS = 4 mA, VBAT = –2 4 V —4.4—mA
Forward/reverse OHT, OBIAS = 4 mA,
VBAT = –70 V —8.4—mA
Ringing, VRING = 45 Vrms,
VBAT = –70 V,
Sine Wave, 1 REN load
—6—mA
Power Consumption PSLEEP Sleep mode, RESET = 0,
VBAT =–70V —8—mW
POPEN Open (high-impedance), VBAT = –70 V — 65 — mW
PSTBY Active on-hook standby, VBAT = –48 V — 70 — mW
PSTBY Active on-hook standby, VBAT = –70 V — 80 — mW
PACTIVE Forward/reverse active off-hook no
ILOOP, ABIAS = 4 mA, VBAT = –2 4 V —240—mW
PACTIVE Forward/reverse active off-hook, no
ILOOP, ABIAS = 4 mA, VBAT = –4 8 V —345—mW
POHT Forward/reverse OHT, OBIAS = 4 mA,
VBAT = –48 V —550—mW
POHT Forward/reverse OHT, OBIAS = 4 mA,
VBAT = –70 V —735—mW
PRING Ringing, VRING = 45 vrms,
VBAT = –70V, 1REN load —516—mW
Table 3. 3.3 V Power Supply Characteristics* (Continued)
(VDD, VDD1–VDD4 = 3.3 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
*Note: All specifications are for a single channel based on measurements with both channels in the same operating state.
Si3220/Si3225
Preliminary Rev. 0.91 7
Table 4. 5 V Power Supply Characteristics*
(VDD, VDD1–VDD4 = 5 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
VDD1–VDD4 Supply
Current (Si3220/Si3225) IVDD1–IVDD4 Sleep mode, RESET = 0 — 1 — mA
Open (high-impedance) — 20 — mA
Active on-hook standby — 20 — mA
Forward/reverse active off-hook no
ILOOP, ABIAS = 4 mA —56—mA
Forward/reverse active OHT
OBIAS = 4 mA —60—mA
Ringing, VRING = 45 Vrms,
VBAT = –70V, 1REN load —32—mA
VDD Supply Current
(Si3200) IVDD Sleep mode, RESET = 0 — 110 — µA
Open (high-impedance) — 110 — µA
Active on-hook standby — 110 — µA
Forward/reverse active off-hook, no
ILOOP, ABIAS = 4 mA, VBAT = –24 V —110—mA
Forward/reverse OHT, OBIAS = 4 mA,
VBAT = –70 V —110—mA
Ringing, VRING = 45 Vrms,
VBAT = –70 V,
1 REN load
—110—mA
VBAT Supply Current
(Si3200) IVBAT Sleep mode, RESET=0, VBAT = –70 V — 100 — µA
Open (high-impedance), VBAT = –70 V — 225 — µA
Active on-hook standby, VBAT = –70 V — 400 — µA
Forward/reverse active off-hook no
ILOOP, ABIAS = 4 mA, VBAT = –2 4 V —4.4—mA
Forward/reverse OHT, OBIAS = 4 mA,
VBAT = –70 V —8.4—mA
Ringing, VRING = 45 Vrms,
VBAT = –70 V,
1 REN load
—6—mA
*Note: All specifications are for a single channel based on measurements with both channels in the same operating state.
Si3220/Si3225
8 Preliminary Rev. 0.91
Power Consumption PSLEEP Sleep mode, RESET = 0,
VBAT =–70V —12—mW
POPEN Open (high-impedance), VBAT = –70 V — 115 — mW
PSTBY Active on-hook standby, VBAT = –48 V — 120 — mW
PSTBY Active on-hook standby, VBAT = –70 V — 130 — mW
PACTIVE Forward/reverse active off-hook no
ILOOP, ABIAS = 4 mA, VBAT = –2 4 V —385—mW
PACTIVE Forward/reverse active off-hook, no
ILOOP, ABIAS = 4 mA, VBAT = –4 8 V —490—mW
POHT Forward/reverse OHT, OBIAS = 4 mA,
VBAT = –48 V —700—mW
POHT Forward/reverse OHT, OBIAS = 4 mA,
VBAT = –70 V —890—mW
PRING Ringing, VRING = 45 Vrms,
VBAT = –70V, 1REN load —585—mW
Table 4. 5 V Power Supply Characteristics* (Continued)
(VDD, VDD1–VDD4 = 5 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
*Note: All specifications are for a single channel based on measurements with both channels in the same operating state.
Si3220/Si3225
Preliminary Rev. 0.91 9
Table 5. AC Characteristics
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Test Condition Min Typ Max Unit
TX/RX Performance
Overload Level 2.5 — — VPK
Overload Compression 2-Wire – PCM Figure 6 — —
Single Frequency Distortion12-Wire – PCM or PCM – 2-Wire:
200Hz to 3.4kHz ——–65dB
PCM – 2-Wire – PCM:
200 Hz – 3. 4 kHz,
16-bit Linear mode
——–65dB
Signal-to-(Noise + Distortion)
Ratio2200Hz to 3.4kHz
D/A or A/D 8-bit
Active off-hook, and OHT, any ZT
Figure 5 — —
Audio Tone Generator Signal-to-
Distortion Ratio20 dBm0, Active off-hook, and
OHT, any ZT
46 — — dB
Intermodulation Distortion — — –41 dB
Gain Accuracy22-Wire to PCM or PCM to 2-Wire
1014 Hz, Any gain setting
VDD1 –V
DD4 =3.3V±5%
VDD1 –V
DD4 =5V±5% –0.25
–0.1 —
—+0.25
+0.4 dB
dB
Attenuation Distortion vs. Freq. 0 dBm 0 Figure 7,8 — — —
Group Delay vs. Frequency Figure 9 — — —
Gain Tracking31014 Hz sine wave,
reference level –10 dBm
Signal level:
————
3 dB to –37 dB — — ± 0.25 dB
–37 dB to –50 dB — — ± 0.5 dB
–50 dB to –60 dB — — ± 1.0 dB
Round-Trip Group Delay 1014 Hz, Within same time-slot — 450 500 µs
Crosstalk between channels
TX or RX to TX
TX or RX to RX
0 dBm0,
300Hz to 3.4kHz
300Hz to 3.4kHz —
——
—–75
–75 dB
dB
Gain Step Increment4Step size around 0 dB — ±0.0005 — dB
2-Wire Return Loss5200Hz to 3.4kHz 26 30 — dB
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. The digital gain block is a linear multiplier that is programmable from –∞ to +6 dB. The step size in dB varies over the
complete range. See “Audio Path Processing”.
5. VDD1–VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 Ω, ZS = 600 Ω synthesized using RS register coef ficients.
6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmi ssion and off-
hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the
sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
Si3220/Si3225
10 Preliminary Rev. 0.91
Transhybrid Balance5300Hz to 3.4kHz 34 40 — dB
Noise Performance
Idle Channel Noise6C-Message weighted — 12 15 dBrnC
Psophometric weighted — –78 –75 dBmP
3 kHz flat — — 18 dBrn
PSRR from VDD1–VDD4 RX and TX, dc to 3.4 kHz 40 — — dB
Longitudinal Performance
Longitudinal to Metallic/PCM
Balance (forward or reverse) 200Hz to 1kHz 58 63 — dB
1kHz to 3.4kHz 53 58 — dB
Metallic/PCM to Longitudinal
Balance 200 Hz to 3.4 kHz 40 — — dB
Longitudinal Impedance7200 Hz to 3.4 kHz at TIP or RING
Register-dependent
OBIAS/ABIAS
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = 16 mA
—
—
—
—
50
25
25
20
—
—
—
—
Ω
Ω
Ω
Ω
Longitudinal Current per Pin7Active off-hook
200Hz to 3.4kHz
Register-dependent
OBIAS/ABIAS
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = 16 mA
—
—
—
—
4
8
8
10
—
—
—
—
mA
mA
mA
mA
Table 5. AC Characteristics (Continued)
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Test Condition Min Typ Max Unit
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. The digital gain block is a linear multiplier that is programmable from –∞ to +6 dB. The step size in dB varies over the
complete range. See “Audio Path Processing”.
5. VDD1–VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 Ω, ZS = 600 Ω synthesized using RS register coef ficients.
6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmi ssion and off-
hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the
sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
Si3220/Si3225
Preliminary Rev. 0.91 11
Table 6. Linefeed Characteristics
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
Maximum Loop Resistance RLOOP RDC,MAX = 430 Ω,
ILOOP = 18 mA, VBAT = –52 V,
ABIAS = 8 mA
1600 — — Ω
DC Loop Current Accuracy ILIM = 18 mA — — ±10 %
DC Open Circuit Voltage
Accuracy Active Mode; VOC = 48 V,
VTIP – VRING
——±4V
DC Differential Output
Resistance RDO ILOOP < ILIM —320— Ω
DC On-Hook Voltage
Accuracy—Ground Start VOHTO IRING<ILIM; VRING wrt ground,
VRING = –51 V ——±4V
DC Output
Resistance—Ground Start RROTO IRING<ILIM; RING to ground — 320 — Ω
DC Output Resistance—
Ground Start RTOTO TIP to ground 300 — — kΩ
Loop Closure Detect Thresh-
old Accuracy ITHR = 13 mA — ±10 ±15 %
Ground Key Detect
Threshold Accuracy ITHR = 13 mA — ±10 ±15 %
Ring Trip Threshold
Accuracy Si3220, ac detection,
VRING = 70 Vpk, no offset,
ITH =80mA
—±4±5mA
Si3220, dc detection,
20 V dc offset, ITH = 13 mA —±1.5±2mA
Si3225, dc Detection,
48 V dc offset, Rloop = 1500 Ω——±4.5mA
Ringing Amplitude, Si3220*VRING Open circuit, VBATH = 100 V 93 — — VPK
5 REN load, RLOOP = 0 Ω,
VBATH = 100 V 82 — — VPK
Sinusoidal Ringing Total
Harmonic Distortion RTHD —2—%
Ringing Frequency Accuracy f = 16 Hz to 100 Hz — — ±1 %
Ringing Cadence Accuracy Accuracy of ON/OFF times — — ±50 ms
Calibration Time ↑CAL to ↓CAL bit — — 600 ms
Loop Voltage Sense
Accuracy Accuracy of boundaries for
each output code;
VTIP – VRING = 48 V
—±2±4%
Si3220/Si3225
12 Preliminary Rev. 0.91
Loop Current Sense
Accuracy Accuracy of boundaries for
each output code;
ILOOP = 18 mA
—±7±10%
Power Alarm Threshold
Accuracy Power Threshold = 300 mW — — ±25 %
*Note: Ringing amplitude is set for 93 V peak using the RINGAMP RAM address and measured at TIP-RING using no series
protection resistance.
Table 7. Monitor ADC Characteristics
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
Differential Nonlinearity
(8-bit resolution) DNLE — — ±1 LSB
Integral Nonlinearity
(8-bit resolution) INLE — — ±1 LSB
Gain Error — — 10 %
Table 8. Si3200 Characteristics
(VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
TIP/RING Pulldown Transistor
Saturation Voltage VOV VRING – VBAT (Forward)
VTIP – VBAT (Reverse)
ILIM = 22 mA, IABIAS = 4 mA*
ILIM = 45 mA, IABIAS = 16 mA*
3
4
—V
V
TIP/RING Pullup Tran sistor Satu-
ration Voltage VCM GND – VTIP (Forward)
GND – VRING (Reverse)
ILIM = 22 mA*
ILIM = 45 mA*
3
4
—V
V
Battery Switch Saturation Imped-
ance RSAT VBAT – VBATH, IOUT = 60 mA 15 Ω
OPEN State TIP/RING Leakage
Current ILKG RL = 0Ω100 µA
Internal Blocking Diode Forward
Voltage VFVBAT – VBATL, IOUT = 60 mA 0.8 V
*Note: VBATL = –24 V, VTIP = –4 V, VRING = –15 V, VAC = 2.5 VPK, RLOAD = 600 Ω.
Table 6. Linefeed Characteristics (Continued)
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
Si3220/Si3225
Preliminary Rev. 0.91 13
Table 9. DC Characteristics (VDD, VDD1–VDD4 = 5 V)
(VDD, VDD1–VDD4 = 4.75 V to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input
Voltage VIH 0.7 x VDD —5.25V
Low Level Input
Voltage VIL — — 0.3 x VDD V
High Level Output
Voltage VOH IO = 8 mA VDD – 0.6 — — V
Low Level Output
Voltage VOL DTX, SDO, INT, SDITHRU:
IO = –8 mA ——0.4V
BATSELa/b, RRDa/b,
GPOa/b, TRD1a/b,TRD2a/b:
IO = –40 mA
— — 0.72 V
SDITHRU Internal
Pullup Resistance 20 30 — kΩ
Relay Driver Source
Impedance ROUT VDD1–VDD4 = 4.75 V
IO < 28 mA —63—Ω
Relay Driver Sink
Impedance RIN VDD1–VDD4 = 4.75 V
IO < 85 mA —11—Ω
Input Leakag e Curr en t IL——±10µA
Table 10. DC Characteristics (VDD, VDD1–VDD4 = 3.3 V)
(VDD, VDD1–VDD4 = 3.13 V to 3.47 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 0.7 x VDD —5.25V
Low Level Input Voltage VIL — — 0.3 x VDD V
High Level Output
Voltage VOH IO = 4 m A VDD –0.6 — — V
Low Level Output
Voltage VOL DTX, SDO, INT,
SDITHRU:
IO = –4 mA
——0.4V
BATSELa/b, RRDa/b,
GPOa/b, TRD1a/b, TRD2a/b:
IO = –40 mA
——0.72
SDITHRU internal pullup
resistance 35 50 — kΩ
Relay Driver Source
Impedance ROUT VDD1–VDD4 = 3.13 V
IO < 28 mA —63—Ω
Relay Driver Sink
Impedance RIN VDD1–VDD4 = 3.13 V
IO < 85 mA —11—Ω
Input Leakage Current IL——±10µA
Si3220/Si3225
14 Preliminary Rev. 0.91
Table 11. Switching Characteristics—General Inputs1
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL = 20 pF)
Parameter Symbol Min Typ Max Unit
Rise Time, RESET tr—— 5 ns
RESET Pulse Width, GCI Mode2trl 500 — — ns
RESET Pulse Width, SPI Daisy Chain Mode trl 6——µs
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VDD –
0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than
10 kΩ per device.
Table 12. Switching Characteristics—SPI
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL = 20 pF)
Parameter Symbol Test
Conditions Min Typ Max Unit
Cycle Time SCLK tc0.062 — — µs
Rise Time, SCLK tr— — 25 ns
Fall Time, SCLK tf— — 25 ns
Delay Time, SCLK Fall to SDO
Transition td2 — — 20 ns
Delay Time, CS Rise to SDO Tristate td3 — — 20 ns
Setup Time, CS to SCLK Rise tsu1 15 — — ns
Hold Time, SCLK Rise to CS Rise th1 20 — — ns
Setup Time, SDI to SCLK Rise tsu2 25 — — ns
Hold Time, SCLK Rise to SDI Rise th2 20 — — ns
SDI to SDITHRU Propagation Delay — 6 — ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VDD –0.4 V, VIL = 0.4 V
Si3220/Si3225
Preliminary Rev. 0.91 15
Figure 1. SPI Timing Diagram
Table 13. Switching Characteristics—PCM Highway Interface
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL = 20 pF)
Parameter Symbol Test
Conditions Min1Typ1Max1Units
PCLK Period tp122 — 3906 ns
Valid PCLK Inputs —
—
—
—
—
—
—
—
—
256
512
768
1.024
1.536
1.544
2.048
4.096
8.192
—
—
—
—
—
—
—
—
—
kHz
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
FSYNC Period2tfs —125 —µs
PCLK Duty Cycle Tolerance tdty 40 50 60 %
FSYNC Jitter Tolerance tjitter — — ±120 ns
Rise Time, PCLK tr— — 25 ns
Fall Time, PCLK tf— — 25 ns
Delay Time, PCLK Rise to DTX Active td1 — — 20 ns
Delay Time, PCLK Rise to DTX
Transition td2 — — 20 ns
SCLK
SDI
CS
SDO
td2
tsu2 th2
td3
tsu1
trtctf
th1
Si3220/Si3225
16 Preliminary Rev. 0.91
Figure 2. PCM Highway Interface Timing Diagram
Delay Time, PCLK Rise to DTX
Tristate3td3 —— 20ns
Setup Time, FSYNC to PCLK Fall tsu1 25 — — ns
Hold Time, FSYNC to PCLK Fall th1 20 — — ns
Setup Time, DRX to PCLK Fall tsu2 25 — — ns
Hold Time, DR X to PCLK Fall th2 20 — — ns
FSYNC Pulse Width twfs tp—125µs–tp
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test leve ls are VIH – VI/O –0.4 V, VIL = 0.4 V.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Spec applies to PCLK fall to DTX tristate when that mode is selected.
Table 13. Switching Characteristics—PCM Highway Interface (Continued)
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL = 20 pF)
Parameter Symbol Test
Conditions Min1Typ1Max1Units
PCLK
DRX
FSYNC
DTX
td1 td2
tsu2 th2
td3
tr
tp
tsu1
th1
tf
tfs
twfs
Si3220/Si3225
Preliminary Rev. 0.91 17
Table 14. Switching Characteristics—GCI Highway Serial Interface
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Figure 3. GCI Highway Interface Timing Diagram (2.048 MHz PCLK Mode)
Parameter1Symbol Test
Conditions Min Typ Max Units
PCLK Period (2.048 MHz PCLK Mode) tp—488—ns
PCLK Period (4.096 MHz PCLK Mode) tp—244—ns
FSYNC Period2 t
fs —125—µs
PCLK Duty Cycle Tolerance tdty 40 50 60 %
FSYNC Jitter Tolerance tjitter ——±120ns
Rise Time, PCLK tr——25ns
Fall Time, PCLK tf——25ns
Delay Time, PCLK Rise to DTX Active td1 ——20ns
Delay Time, PCLK Rise to DTX Transition td2 ——20ns
Delay Time, PCLK Rise to DTX Tristate3td3 ——20ns
Setup Time, FSYNC Rise to PCLK Fall tsu1 25 — — ns
Hold Time, PCLK Fall to FSYNC Fall th1 20 — — ns
Setup Time, DRX Transition to PCLK Fall tsu2 25 — — ns
Hold T ime, PCLK Fa lling to DRX Transition th2 20 — — ns
FSYNC Pulse Width twfs tp——ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V, VIL = 0.4 V, rise and fall
times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
tsu1
th1
tp
trtf
th2
td3
td2
td1
PCLK
FSYNC
DRX
DTX
tfs
tsu2
Frame 0,
Bit 0
Frame 0,
Bit 0
Si3220/Si3225
18 Preliminary Rev. 0.91
Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode)
Figure 5. Transmit and Receive Path SNDR
tsu1
th1
tc
trtf
tsu2 th2
td3
td2
td1
PCLK
FSYNC
DRX
DTX
tfs
Frame 0,
Bit 0
Frame 0,
Bit 0
Acceptable Region
Si3220/Si3225
Preliminary Rev. 0.91 19
Figure 6. Overload Compression Performance
Figure 7. Transmit Path Frequency Response
123456789
1
2
3
4
5
6
7
8
9
0
2.6
Acceptable
Region
Fundamental Input Power (dBm0)
Fundamental
Output Power
(dBm0)
0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 500
0
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5TX Attenuation Distortion
Loss(dB)
Frequency (Hz)
0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 500
0
−1.2
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4 TX Pass−Band Detail
Loss (dB)
Frequency (Hz)
Si3220/Si3225
20 Preliminary Rev. 0.91
Figure 8. Receive Path Frequency Response
0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 500
0
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5RX Attenuation Distortion
Loss (dB)
Frequency (Hz)
0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 500
0
−1.2
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4 RX Pass−Band Detail
Loss (dB)
Frequency (Hz)
Si3220/Si3225
Preliminary Rev. 0.91 21
Figure 9. Transmit Group Delay Distortion
Figure 10. Receive Group Delay Distortion
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 340
0
0
100
200
300
400
500
600
700
800
900
1000
1100 TX Group Delay Distortion
Distortion (us)
Frequency (Hz)
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 340
0
0
100
200
300
400
500
600
700
800
900
1000
1100 RX Group Delay Distortion
Distortion (us)
Frequency (Hz)
Typical Response
Si3220/Si3225
22 Preliminary Rev. 0.91
D/ A Interpolation
Filter +
+
Decimation
Filter +
+
From Billin g
To ne DAC
H
+
Interpolation
Filter RPGA µ/A-law
Expander Serial
Input
Decimation
Filter
RHPF
To Ringer
Circuit
THPF
Mode m Tone
Detection
DTMF
Decode
Digital
RX
Digital
TX
DLM2 Dual Tone
Generator
Ibuf Gm
DLM3
ZD
Diagnostics
Filter
Equalizer TPGA
Mod em Tone
Detection
Codec
Loopback
DLM1
PCM
Loopback
Hybrid
Loopback
Transmit Path
Rece ive Path
ZA
A/D µ/A-law
Compressor Serial
Output
Figure 11. AC Signal Path Block Diagram for a Single Channel
Si3220/Si3225
Preliminary Rev. 0.91 23
TIPb
RINGb
RINGa
TIPa
GPOb
GPOa
VDD
VDD
VDD
VBATH VBLO
VBATH VBLO
VBAT
VBAT
RINGa_ext
FSYNC
/INT
RINGa
RINGb_ext
SDITHRU
DTX
TIPa_ext
SDI
TIPb
PCLK
TIPb_ext
/RESET
TIPa
/CS
SCLK
DRX
SDO
RINGb
BATSELb
BATSELa
GPOa
GPOb
BATSWa
BATSWb
TRD2a
TRD1a
GPOa
GPOb
TRD1b
TRD2b
Protection
Protection
R5 806k
R3 4.7k
R15 806k
U3 Si3200
TIP
1
NC
2
RING
3
VBAT
4
VBATH
5
VBATL
6
GND
7
VDD
8
NC 11
NC 10
BATSEL 9
IRINGP 13
IRINGN 12
THERM 14
ITIPP 16
ITIPN 15
GND epad
R2 402k
R12 402k
C14
10n
100V
J1
RJ-11 SMD
1
2
3
4
5
6
C1 0.1u
100V
X7R
U1
Si3220
QGND
8
CAPPb
11
STIPDCb
17
NC
28
BATSELb
32 TRD2a 50
TRD1a 51
GPOb
31
NC 53
RPOa
2
ITIPNb
21
ITIPPb
23
GND2
25 VDD2
24
STIPACa 63
THERMa 54
SRINGACa 62
IRINGNa 59
IRINGPa 55
ITIPPa 58
CAPPa
6
SRINGDCa 61
VDD1 57
ITIPNa 60
RPIa
3
RNIa
4
STIPACb
18
SRINGACb
19
NC 52
IRINGPb
26
RPOb
15
RNOa
5
CAPMa
7
IRINGNb
22
RPIb
14
STIPDCa 64
GND1 56
SRINGDCb
20
CAPMb
10 IREF
9
RNOb
12
RNIb
13
FSYNC 34
TRD1b
29
TRD2b
30
SVBATa
1
DRX 35
SVBATb
16
/CS 47
PCLK 39
SDO 44
DTX 36
VDD3 37
SDITHRU 46
THERMb
27
SDI 45
GND3 38
/RST 33
SCLK 43
BATSELa 49
VDD4 42
/INT 40
GPOa 48
GND4 41
TP1
1
C4
10n
100V
TP5
1
C15
1u
6V
R6 40.2k
J6
1
2
TP8
1
TP6
1
C2 0.1u
100V
X7R
C3
10n
100V
C30
0.1u
100V
R18 182
C16
1u
6V
R13 4.7k
R10 40.2k
C5
1u
6V
U2 Si3200
TIP
1
NC
2
RING
3
VBAT
4
VBATH
5
VBATL
6
GND
7
VDD
8
NC 11
NC 10
BATSEL 9
IRINGP 13
IRINGN 12
THERM 14
ITIPP 16
ITIPN 15
GND epad
C33
0.1u
100V
R8 182
C11 0.1u
100V
X7R
R7 182
R11 402k
J7
1
2
TP7
1
C12 0.1u
100V
X7R
TP2
1
C13
10n
100V
C6
1u
6V
R14 4.7k
R17 182
C31
0.1u
100V
C32
0.1u
100V
J11
RJ-11 SMD
1
2
3
4
5
6
TP3
1
J5
1
2
R4 4.7k
J2
1
2
R1 402k
J3
1
2
TP4
1
J4
1
2
R16 40.2k
Figure 12. Si3220 Application Circuit Using Dual Battery Supply
Si3220/Si3225
24 Preliminary Rev. 0.91
RRDa
RRDa
RRDb
RRDb
RNGNGb
RNGNGa
TRD1a
TRD2b
TRD1b
TRD2a
VDD
VRNGSOURCE
VBLO
VRNGSOURCE
VBLO
VDD
VBHI
VDD
VDD
VDD
VBHI
SDITHRU
SDO
SCLK
SDI
FSYNC
/RESET
PCLK
DTX
/INT
/CS
DRX
RINGa_ext
TIPaTIPa_ext
RINGa
TIPbTIPb_ext
RINGbRINGb_ext
Protection
Protection
TRD1b
RRDb
RRDa
TRD2b
TRD1a
TRD2a
R10 40.2k
C6
1u
6V
U1
Si3225
QGND
8
CAPPb
11
STIPDCb
17
RTRPb
28
BATSELb
32 TRD2a 50
TRD1a 51
RRDb
31
BLKRNG 53
RPOa
2
ITIPNb
21
ITIPPb
23
GND2
25 VDD2
24
STIPACa 63
THERMa 54
SRINGACa 62
IRINGNa 59
IRINGPa 55
ITIPPa 58
CAPPa
6
SRINGDCa 61
VDD1 57
ITIPNa 60
RPIa
3
RNIa
4
STIPACb
18
SRINGACb
19
RTRPa 52
IRINGPb
26
RPOb
15
RNOa
5
CAPMa
7
IRINGNb
22
RPIb
14
STIPDCa 64
GND1 56
SRINGDCb
20
CAPMb
10 IREF
9
RNOb
12
RNIb
13
FSYNC 34
TRD1b
29
TRD2b
30
SVBATa
1
DRX 35
SVBATb
16
/CS 47
PCLK 39
SDO 44
DTX 36
VDD3 37
SDITHRU 46
THERMb
27
SDI 45
GND3 38
/RST 33
SCLK 43
BATSELa 49
VDD4 42
/INT 40
RRDa 48
GND4 41
C32
0.1u
100V
C15
1u
6V
U2
Si3200
TIP
1
NC
2
RING
3
VBAT
4
VBATH
5
VBATL
6
GND
7
VDD
8
NC 11
NC 10
BATSEL 9
IRINGP 13
IRINGN 12
THERM 14
ITIPP 16
ITIPN 15
GND epad
TP1
Tip A
1
C16
1u
6V
TP2
Ring A
1
K2
DPDT
3
2
4
8
9
7
1
10
TP3
Tip B
1
TP4
Ring B
1
U3
Si3200
TIP
1
NC
2
RING
3
VBAT
4
VBATH
5
VBATL
6
GND
7
VDD
8
NC 11
NC 10
BATSEL 9
IRINGP 13
IRINGN 12
THERM 14
ITIPP 16
ITIPN 15
GND epad
TP5
GND
1
TP6
GND
1
C5
1u
6V
J4
1
2
J1
RJ-11 SMD
1
2
3
4
5
6
R22
510
R21
510
R6 40.2k
C30
0.1u
100V
J7
1
2
K1
DPDT
3
2
4
8
9
7
1
10
C31
0.1u
100V
J11
RJ-11 SMD
1
2
3
4
5
6
TP8
GND
1
R19
806k
R16 40.2k
C3
10n
100V
C2 0.1u
100V
X7R
J3
1
2
C4
10n
100V
C13
10n
100V
C14
10n
100V
J6
1
2
R11 402k
C11 0.1u
100V
X7R
R12 402k
R13 4.7k
C12 0.1u
100V
X7R
R7 182
R14 4.7k
J2
1
2
R15 806k
C1 0.1u
100V
X7R
R18 182
TP7
GND
1
R17 182
C33
0.1u
100V
R1 402k
R2 402k
R3 4.7k
R4 4.7k
R8 182
J5
1
2
R5 806k
R20
806k
R9
806k
Figure 13. Si3225 Application Circuit Using Centralized Ringer and Secondary Battery Supply
Si3220/Si3225
Preliminary Rev. 0.91 25
Bill of Materials
Table 15. Si3220 + Si3200 External Component Values
Component Value Function
C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac sensing inp uts.
C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% TIP/RING compensation capacitors.
C5, C6, C15, C16 1 µF, 6.3 V, X7R, ±20% Low pass filter capacitors to stabilize differential and com-
mon mode SLIC feedback loops.
C30–C33 0.1 µF, 100 V, Y5V Decoupling for battery voltage supply pins.
C20–C25 0.1 µF, 10 V, Y5V Decoupling fo r analog and digital chip supply pins.
R1, R2, R11, R12 402 kΩ, 1/10 W, ±1% Sense resistors for TIP, RING voltage sensing nodes.
R3, R4, R13, R14 4.7 kΩ, 1/10 W, ±1% Current limiting resistors for TIP, RING ac sensing inputs.
R5, R15 806 kΩ, 1/10 W, ±1% Sense resistor for battery dc sensing nodes.
R6, R16 40.2 kΩ, 1/10 W, ±5% Sets bias current for battery switching circuit.
R7, R8, R17, R18 182 Ω, 1/10 W, ±1% Reference resistors for internal transconductance amplifier.
R10 40.2 kΩ, 1/10 W, ±1% Generates a high accuracy reference current.
Table 16. Si3225 + Si3200 External Component Values
Component Value Function
C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac sensing inp uts.
C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% TIP/RING compensation capacitors.
C5, C6, C15, C16 1 µF, 6.3 V, X7R, ±20% Low pass filter capacitors to stabilize differential and com-
mon mode SLIC feedback loops.
C301, C311,
C32, C33 0.1 µF, 100 V, Y5V Decoupling for battery voltage supply pins.
C20–C25 0.1 µF, 10 V, Y5V Decoupling fo r analog and digital chip supply pins.
R1, R2, R11, R12 402 kΩ, 1/10 W, ±1% Sense resistors for TIP, RING dc sensing nodes.
R5, R15 806 kΩ, 1/10 W, ±1% Sense resistors for battery voltage sensing nodes.
R3, R4, R13, R14 4.7 kΩ, 1/10 W, ±1% Current limiting resistors for TIP, RING ac sensing inputs.
R61, R16140.2 kΩ, 1/10 W, ±5% Sets bias current for battery switching circuit.
R7, R8, R17, R18 182 Ω, 1/10 W, ±1% Reference resistors for internal transconductance amplifier.
R9, R19, R20 806 kΩ, 1/10 W, ±1% Sense registers for ringing generator feed.
R10 40.2 kΩ, 1/10 W, ±1% Generates a high accuracy reference current.
RRING 510 Ω, 2W, ±2%2Feed resistor for ringing generator source.
Notes:
1. Optional. Only required when using dual battery architecture.
2. Example power rating.
Si3220/Si3225
26 Preliminary Rev. 0.91
Functional Description
The Dual ProSLIC chipset is a three-chip integrated
solution that provides all SLIC, codec, and DTMF
detection/decoding functions needed for a complete
dual-channel analog telephone interface. Intended for
multiple channel long loop (up to 18 kft) applications
requiring high-density line card designs, the Dual
ProSLIC chipset provides high integration and low-
power operation for applications such as Central Office
(CO) and digital loop carrier (DLC) enclosures. The
Dual ProSLIC chipset is also ideal for short-loop
applications requiring a space-effective solution such as
terminal adapters, integrated access devices (IADs),
PBX/key systems, and voice over IP systems. The
chipset meets all relevant Bellcore LSSGR, ITU and
ETSI standards.
The Si3220/Si3225 ICs perform all battery, overvoltage,
ringing, supervision, codec, hybrid, and test
(BORSCHT) functions on-chip in a low-power, small
footprint solution. DTMF decoding and generation,
phase continuous FSK (caller ID) signaling, and pulse
metering are also integrated. All high-voltage functions
are implemente d u sing the Si32 00 Line fe ed In te rface IC
allowing a highly programmable integrated solution that
offers the lowest total system cost.
The internal linefeed circuitry provides programmable
on-hook voltage and off-current loop current, reverse
battery operation, loop or ground start operation, and
on-hook transmission. Loop current and voltage are
continuously monitored using an integrated 8-bit
monitor A/D converter. The Si3220 provides on-chip
balanced 5 REN ringing with or without a pr ogram mable
dc offset, eliminating the need for an external bulk ring
generator and per- channe l ringing relay. Both sinusoidal
and trapezoidal ringing waveshapes are available.
Ringing parameters such as frequency, waveshape,
cadence, and offset are available in registers to reduce
external controller requirements. The Si3225 supports
external ringing generation with ring relay driver and
external ring trip sensing to address legacy systems
that implement a centralized ringing architecture. All
ringing options are software programmable over a wide
range of parameters to address a wide variety of
application requirements.
The Si3220/Si3225 ICs also provide a variety of line
monitoring and subscriber loop testing functions. All
versions have the ability to generate specific dc and
audio signals and co ntinuously mo nitor and sto re all line
voltage and current parameters. This combination of
signal generation and mea surement tool s allows remote
line card and loop diagnostics without requiring
additional test equipment. These diagnostic functions
are intended to comply with relevant LSSGR and ITU
requirements for line-fault detection and reporting, and
measured values are stored in registers for later use or
further calculations. The Si3220 and Si3225 also
include two per-channel relay drivers to support legacy
systems implementing centralized test equipment.
A complete audio transmit and receive path is
integrated, including DTMF generation and decoding,
tone generation, modem/fax tone detection,
programmable ac impedance synthesis, and
programmable transhybrid balance and programmable
gain attenuation. These features are software
programmable, providing a single hardware design to
meet international requirements. Digital voice data
transfer occurs over a standard PCM bus and control
data is transferred using a standard 4-wire serial
peripheral interface (SPI). The Si3220 and Si3225 can
also be configured to support a 4-wire general circuit
interface (GCI). The Si3220 and Si3225 are available in
a 64-lead TQFP and the Si3200 is available in a 16-lead
SOIC.
Dual ProSLIC Architecture
The Dual ProSLIC chipset is comprised of a low-voltage
CMOS device that uses a low-cost integrated linefeed
interface IC to control the high voltages needed for
operating the terminal equipment connected to the
telephone line. Figure 15 on page 28 presents a
simplified diagram of the linefeed control loop circuit for
controlling the TIP and RING leads. The diagram shows
a single-ended model for simplicity, showing either the
TIP or the RING lead.
The Dual ProSLIC chipset produces line voltages and
currents on the TIP/RING pair using register
programmable settings in the Si3220 and Si3225 as
well as direct ac and dc voltage/current sensing from
the line. The Si3200 LFIC provides a low-cost interface
for bridging the low-voltage CMOS devices to the high
voltage TIP/RING pair. Sense resistors allow the volt age
and current to be measured on each lead or across T-R
using the low voltage circuitry inside the Si3220 and
Si3225, eliminating expensive analog sensing circuitry
inside the high-voltage Si3200. In addition, the total
power inside the Si3200 is constantly monitored and
controlled to provide optimal reliability under all
operating conditions. The sensing circuitry is calibrated
for environmental and process variations to guarantee
accuracy with standard external resistor tolerances.
Si3220/Si3225
Preliminary Rev. 0.91 27
DC Feed Characteristics
The Si3220 and Si3225 offer programmable constant
voltage and constant current operating regions as
illustrated in Figure 14 and Figure 16. The constant
voltage reg ion (defined by the ope n-circuit volt age, VOC)
is programmable from 0 to 63.3 V in 1 V steps. The
constant current region (defined by the loop current
limit, ILIM) is programmable from 18 to 45 mA in
0.87 mA steps. The Si3220 and Si3225 exhibit a
characteristic dc impedance of 320 Ω during Active
mode.
The TIP-RING voltage (VOC) is offset from ground by a
programmable voltage (VCM) to provide sufficient
voltage headroom to the most positive terminal
(typically the TIP lead in normal polarity or the RING
lead in reverse polarity) for carrying audio signals. A
similar programmable voltage (VOV) is an offset
between the most negative terminal and the battery
supply rail for carrying audio signals. (See Figure 14.)
The user-supplied battery voltage must have sufficient
amplitude under all operating states to ensure sufficient
headroom. The Si3200 may be powered by a lower
secondary battery supply (VBATL) to reduce total power
dissipation when driving short-loop lengths.
Figure 14. DC Linefeed Overhead Voltages
(Forward State)
Calculating Overhead Voltages
The two programmable overhead voltages (VOV and
VCM) represent one portion of the total voltage between
VBAT and ground as illustrated in Figure 14. In normal
operating conditions, these overhead voltages are
sufficiently low enough to maintain the desired TIP-
RING voltage (VOC). However, there are certain
conditions under which the user must exercise care in
providing a battery supply with enough amplitude to
supply the required TIP-RING voltage and enough
margin to accommodate these overhead voltages. The
VCM voltage is programmed for a given operating
condition. Therefore, the open-circuit voltage (VOC)
varies according to the required overhead voltage (VOV)
and the supplied battery voltage (VBAT). The user
should pay attention to th e maximum VOV and VCM that
might be required for each operating state.
In the off-hook active state, sufficient VOC must be
maintained to correctly power the phone from the
battery supply that is provided. Because the battery
supply depends on the state of the input supply (i.e.,
Charging, Discharging, or Battery Backup mode), the
user must decide ho w much loop current is re quired and
then determine the maximum loop impedance that can
be driven based on the battery supply provided. The
minimum battery supply required can be calculated with
the following equation:
where VCM and VOV are provided in Table 8. The default
VCM value of 3 V provides sufficient overhead for a
3.1 dBm signal into a 600 Ω loop impedance with an
ILIM setting of 22 mA and an ABIAS setting of 4 mA. A
VOV value of 4 V provides sufficie nt headroom to so urce
a maximum ILOOP of 45 mA with a 3.1 dBm audio signal
and an ABIAS setting of 16 mA. For a typical operating
condition of VBAT = –56 V and ILIM = 22 mA:
These conditions apply when the dc sensing inputs
(STIPDCa/b and SRINGDCa/b) are placed on the SLIC
side of any protection resistance placed in series with
the TIP and RING leads. If line-side sensing is desired,
both VOV and VCM must be increased by a voltage
equal to RPROT xI
LIM where RPROT is the value of each
protection resistor. Other safety precautions may also
apply.
See the "Linefeed Overhead Voltage Considerations
During Ringing" on p age 43 for det ails on calcu lating the
overhead voltage during the ringing state.
The Dual ProSLIC chipset uses both voltage and
current information to control TIP and RING. Sense
resistor RDC measures dc line voltages on TIP and
RING; Capacitor CAC couples the ac line voltages on
the TIP and RING leads to be measured. The Si3220
and Si3225 both use the Si3200 to drive TIP and RING
and isolate the high-voltage line from the low-voltage
CMOS devices.
The Si3220 and Si3225 measure voltage at various
nodes to monitor the linefeed current. RDC and RBAT
provide these measuring points. The sense circuitry is
calibrated on-chip to guarantee measurement accuracy.
See "Linefeed Calibration" on page 31 for details.
Constant I Region Constant V Region
VCM
VOC
VOV
VOV
RLOOP
VBATH
VTIP
VRING
VBATL
Secondary VBAT
Selected
V
VBAT VOC VCM VOV
++≥
VOC MAX,56 V 3 V 4 V+()–49 V==
Si3220/Si3225
28 Preliminary Rev. 0.91
Figure 15. Simplified Dual ProSLIC Linefeed Architecture for TIP and RING Leads (diagram
illustrates either TIP or RING lead of a single channel)
DSP A/D
D/A
D/A
A/D
SLIC
Control
Audio
Control
SLIC
Control
Loop
Audio
Control
Loop
VBAT Sense
RDC
RBAT
TIP or
RING
CAC
Si3220/
Si3225
Monitor A/D
SLIC DA C
Σ
Current
Mirror Battery
Select
Control
VBAT
VBATH
Si3200
Low
Frequency
Diagnostic
Filters
Audio
Diagnostic
Filters
Audio
Codec
VBATL
Si3220/Si3225
Preliminary Rev. 0.91 29
Linefeed Operation States
The linefeed interface includes eight different operating
states. (See Table 17.) The linefeed register settings
(LF[2:0], Linefeed register) are also listed. The Open
state is the default condition in the absence of any pre-
loaded register settings. The device may also
automatically enter the Open state if excess power
consumption is detected in the Si3200. See "Power
Monitoring and Power Fault Detection" on page 33 for
more details. The register and RAM locations used for
programming the linefeed parameters are provided in
Table 18. See “Loop Voltage and Current Monitoring,”
“Power Monitoring and Power Fault Detection,” and
“Power Dissipation Considerations” for detailed
descriptions and register/RAM locations for these
functions.
Table 17. Linefeed States
Open (LF[2:0] = 000).
The Si3200 output is hig h-impedance. This mode can be used in the presence of line fault condition s and to
generate open switch intervals (OSIs). The de vice also can autom atically enter the Open st ate if excess power
consumption is detected in the Si3200.
Forward Active (LF[2:0] = 001).
Linefeed is active, but audio paths are powered down until an off-hook condition is detected. The Si3220 and
Si3225 automatically enter a low power state to reduce power consumption during on-hook standby periods.
Forward On-Hook Transmission (L F[2:0] = 010).
Provides data transmission during an on -hook loop condition (e.g., transmitting FSK caller ID information
between ringing bursts).
Tip Open (LF[2:0] = 011).
Sets the portion of the linefeed interface connected to the TIP side of the subscriber loop to high-impedance
and provides an active linefeed on the RING side of the loop for ground start operation.
Ringing (LF[2:0] = 100).
Drives programmable ringing waveforms onto the subscriber loop (Si3220) or switches in a centralized ringing
generator by driving an external rela y (Si3225).
Reverse Active (LF[2:0] = 101).
Linefeed circuitry is active, but audio paths are powered down until an off-hook condition is detected. The
Si3220 and Si3225 automatically enter a low power state to reduce power consumption during on-hook
standby periods.
Reverse On-Hook Transmission (LF[2:0] = 110).
Provide data transmission during an on-hook loop condition.
Ring Open (LF[2:0] = 111).
Sets the por tion of th e linef eed interfa ce connecte d to the RING side of the su bscriber lo op to h igh- impeda nce
and provides an active linefeed on the TIP si de of the loop for ground start operation.
Si3220/Si3225
30 Preliminary Rev. 0.91
The dc linefeed circuitry generates the necessary TIP/
RING I/V characteristics along with loop closure and
ring trip detection. For loop start applications, VTIP-
VRING is programmable. The loop current limit (ILIM) is
software programmable with a range from 18–45 mA.
Figure 16 illustrates the linefeed characteristics for a
typical application using an ILOOP setting of 24 mA and
a TIP-RING open circuit voltage (VOC) of 48 V. The
VOC and VOCTRACK RAM locations are used to
program the TIP-RING voltage, and these two values
are equal when VBAT > VOC + VOV + VCM. When the
battery voltage drops below that point, VOCTRACK
decreases at the same rate as VBAT decreases to
provide sufficient headroom to accommodate both VOV
and VCM levels below VBAT.
The equation for calculating the RAM address value for
VOC, VCM, VOCDELTA, VOV, VOVRING, RINGOF,
VOCLTH, and VOCHTH is shown below. The CEILING
function rounds up the result to the next integer.
For example, to program a VOC value of 51 V:
During the on-hook state, the Si3220/Si3225 is in the
constant voltage operating area and typically presents a
640 Ω output impedance (Figure 16). The Si3220 and
Si3225 include a special modified linefeed scheme
called Modfeed™, which adjusts the ProSLIC’s output
impedance based on the linefeed voltage level in order
to ensure the ability to source extended loop lengths.
When the terminal equipment transitions to the off-hook
state, the linefeed voltage typically collapses and
transitions through the preset Modfeed threshold
voltage causing the Si3220/Si3225 to reduce its output
impedance to 320 Ω. The TIP-RING voltage will then
continue decreasing until the preset loop current limit
(ILIM) setting is reached. Loop closure and ring trip
detection thresholds are programmable and include
internal debouncing. A high-gain common mode loop
generates a low-impedance from TIP or RING to
ground, effectively reducing the effects of longitudinal
interference.
Table 18. Register and RAM Locations for Linefeed Control
Parameter Register/RAM
Mnemonic Register/RAM
Bits Programmable
Range LSB Size Effective
Resolution
Linefeed LINEFEED LF[2:0] See Table 17 N/A N/A
Linefeed Shadow LINEFEED LFS[2:0] Monitor Only N/A N/A
Battery Feed Control RELAYCON BATSEL VBATH/VBATL N/A N/A
Loop Current Limit ILIM ILIM[4:0] 18–45 mA 0.875 mA 0.875 mA
On-Hook Line Voltage VOC VOC[14:0] 0 to 63.3 V 4.907 mV 1.005 V
Common Mode Voltage VCM VCM[14:0] 0 to 63.3 V 4.907 mV 1.005 V
VOC Delta for Off-Hook VOCDELTA VOCDELTA[14:0] 0 to 63.3 V 4.907 mV 1.005 V
VOC Delta Threshold,
Low VOCLTH VOCLTH[15:0] 0 to 63.3 V 4.907 mV 1.005 V
VOC Delta Threshold,
High VOCHTH VOCHTH[15:0] 0 to 63.3 V 4.907 mV 1.005 V
Overhead Voltage VOV VOV[14:0] 0 to 63.3 V 4.907 mV 1.005 V
Ringing Overhead Volt-
age VOVRING VOVRING[14:0] 0 to 63.3 V 4.907 mV 1.005 V
VOC During Battery
Tracking VOCTRACK VOCTRACK[15:0] 0 to 63.3 V 4.907 mV 1.005 V
RAM VALUE
2CEILING×ROUND desired voltage
1.005V
----------------------------------------
512
5
----------
×
=
VOC 2 CEILING×ROUND 51V
1.005V
-------------------
512
5
----------
×
28CEh==
Si3220/Si3225
Preliminary Rev. 0.91 31
Figure 16. VTIP–RING vs. ILOOP Characteristic for
Loop Start Operation
Figure 17. VRING vs. IRING Characteristic for
Ground Start Operation
For ground start operation, the active lead presents a
640 Ω output impedance dur ing the on-h ook st ate an d a
320 Ω output impedance in the off-hook state. The
“open” lead presents a high-impedance feed (>150 kΩ).
Figure 17 illustrates a typical ground start application
using VOC = 48 V and ILIM = 24 mA in the TIP OPEN
state. The ring ground detection threshold and
debouncing interval are both programmable.
Figure 18. VTIP–RING vs. ILOOP Characteristics
using Modfeed™
The Modfeed scheme also allows the user to modify the
apparent VOC voltage as a means of boosting the
linefeed voltage when the battery voltage drops below a
certain level. Figure 18 illustrates a typical Si3225
application using Modfeed while sourcing a 1930 Ω
subscriber loop (1500 Ω loop impedance with a 430 Ω
phone connected) from a 48 V battery. For VOV and
VCM values of 3 V, the VOCTRACK RAM location is set
to 42 V given a programmed value of 42 V for the VOC
RAM location. When a loop closure event occurs, the
TIP-RING voltage decreases linearly until it reaches a
preset voltage threshold that is lower than VOCTRACK
by an amount programmed into the VOCLTH RAM
location. Exceeding this threshold causes the Si3220/
Si3225 to increase its “target” VOC level by an amount
programmed into the VOCDELTA RAM location to
provide additional overhead for driving the higher
impedance loop. In the on-hook condition, the TIP-
RING voltage increases linearly until it rises above a
second preprogrammed voltage threshold, which is
higher than VOCTRACK by an amount programmed
into the VOCHTH RAM location. This of fers the ability to
drive very long loop lengths while using the lowest
possible battery voltage. Consult the factory for optimal
register and RAM location settings for specific
applications.
Linefeed Calibration
An internal calibratio n algor ithm correct s for internal and
external component erro rs. The calibration is initiated by
setting the CAL register bit. This bit automatically resets
on completion of the calibr ation cycle.
A calibration should be executed following system
powerup. Upon release of the chip reset, the chip se t will
be in the Open state and calibration may be initiated.
010 20 30 40 50
10
20
30
40
50
60
Constant
Loop Current
Region
ILIM
RO
VTIP–RING (V)
ILOOP (mA)
Constant
TIP-RING
Voltage
Region
VOC RO
Loop Cl osure
Threshold = 640 Ω
= 320Ω
ILIM = 24 mA
0
–20
–40
–60
10 20 30 40 50
Constant
Loop Current
Region
ILIM = 24 mA
RO = 640 Ω
IRING (mA)
VRING (V)
Constant
TIP-RING
Voltage
Region
RO = 320 Ω
Loop Clos ure
Threshold
010 20
10
20
30
40
50
VTIP–RING (V)
ILIM (mA)
1930 Ω
load line
RO = 320 Ω
RO = 640 Ω
VOCTRACK
VOCDELTA
Si3220/Si3225
32 Preliminary Rev. 0.91
Only one calibration should be necessary if the system
remains powered up.
To optimize performance, it is recommended that the
user perform the following steps when running the CAL
routines:
1. Set CALR1 = 0x3F and CALR2 = 0x3E. This enables all
calibration routines except the AC longitudinal balance
(CALCMBAL) routine.
2. Set the CAL bit in the CALR1 register. This runs the first
set of calibration routines.
3. Set the ProSLIC to the ACTIVE state (set
LINEFEED = 0x01)
4. Set CALR2 = 0x01. This enables only the AC longitudinal
balance calibration routine.
5. Set the CAL bit in the CALR1 register .
There is an initial settling period of approximately
300 ms that is required prior to running the first set of
calibration routines. Each calibration routine requires
approximately 1 ms to complete, except for the ac
longitudinal balance routine, which requires up to
100 ms. An additional 300 ms settling period is also
required after going to the ACTIVE state and prior to
running the ac longitudinal balance routine.
During calibration, VTIP and VRING are controlled by the
calibration engine to provide th e correct external vo lt age
conditions for the algorithm. Calibration should always
be performed in the on-hook active state. The TIP and
RING leads must not be connected to ground during
calibration.
Loop Voltage and Current Monitoring
The Dual ProSLIC chipset continuously monitors the
TIP and RING voltages and currents. These values are
available in registers. An internal 8-bit A/D converter
samples the measured voltages and currents from the
analog sense circuitry and translates them into the
digital domain. The A/D updates the samples at an
800 Hz rate for all inputs except VRNGNG and
IRNGNG, which are sampled at 8 kHz to provide higher
resolution for zero crossing detection in external ringing
applications. Two derived values, the loop voltage
(VTIP –V
RING) and the loop current also are reported.
For ground start operation, the values reported are
VRING and the current flowing in the RING lead.
Table 19 lists the register set associated with the loop
monitoring functions.
The Dual ProSLIC chipsets also include the ability to
perform loop diagnostics functions as outlined in "Line
Test and Diagnostics" on page 85.
Table 19. Register and RAM Locations Used for Loop Monitoring
Parameter Register/RAM
Mnemonic Register/
RAM Bits Measurement
Range LSB Size Effective
Resolution
Loop Voltage Sense
(VTIP –V
RING)VLOOP VLOOP[15:0] 0 to 64.07 V
64.07 to 160.173 V 4.907 mV 251 mV
628 mV
TIP Voltage Sense VTIP VTIP[15:0] 0 to 64.07 V
64.07 to 160.173 V 4.907 mV 251 mV
628 mV
RING Voltage Sense VRING VRING[15:0] 0 to 64.07 V
64.07 to 160.173 V 4.907 mV 251 mV
628 mV
Loop Current Sense ILOOP ILOOP[15:0] 0 to 101.09 mA 3.097 µA500µA*
Battery Voltage Sense VBAT VBAT[15:0] 0 to 63.3 V
0 to 160.173 V 4.907 mV 251 mV
628 mV
Longitudinal Current
Sense ILONG ILONG[15:0] 0 to 101.09 mA 3.097 µA500µA*
External Ringing Genera-
tor Voltage Sense VRNGNG VRNGNG[15:
0] 332.04 V 10.172 mV 1.302 V
External Ringing Genera-
tor Current Sense IRNGNG IRNGNG[15:0
]662.83 mA 20.3 µA2.6mA
*Note: ILOOP and ILONG are calculated values based on measured I Q1–IQ4 currents. The resulting effective resolution is
approximately 500 µA.
Si3220/Si3225
Preliminary Rev. 0.91 33
Power Monitoring and Power Fault
Detection
The Dual ProSLIC line monitoring functions can be
used to protect the high-voltage circuitry against
excessive power dissipation and thermal overload
conditions. This protection scheme can be implemented
in a number of different ways depending on the
application circuit used. When the Si3200 linefeed
interface chip is used, an on-chip thermal monitor diode
provides realtime Si3200 die temperature data to the
Si3220/3225. The Dual ProSLIC devices also have the
ability to prevent thermal overloads by regulating the
total power inside the Si3200 or in each of the external
bipolar transistors (if using a discrete linefeed circuit).
The DSP engine performs all power calculations and
provides the ability to automatically transition the device
into the OPEN state and generate a power alarm
interrupt when excessive po wer is detected. Table 20 on
page 35 describes the register and RAM locations used
for power monitoring.
Thermometer-Based Si3200 Power Monitor
The Si3200 includes an on-chip analog thermal sensing
diode that provides realtime die temperature data to the
Si3220/3225 provided the THERMSEL bit is set to 1.
The analog thermometer has a built in temperature
threshold which, when exceeded, turns off the Si3200
and asserts the STAT bit of the THERM register. The
internal temperature threshold is set to approximately
140 °C to maintain optimal device reliability.
Figure 19. Discrete Linefeed Circuit for Power Monitoring
Tran si st or Power Equatio ns
(Using Discrete Transistors)
When using the Si3220 or Si3225 along with discrete
bipolar transistors, it is possible to control the total
power of the solution by regulating the power in each
discrete transistor individually. Figure 19 illustrates the
basic transistor-based linefeed circuit for one channel.
The power dissipation of each external transistor is
estimated based on the A/D sample values. The
approximate power equations for each external BJT are
as follows:
PQ1 ≅ VCE1 x IQ1 ≅ (VTIP + 0.75 V) x (IQ1)
PQ2 ≅ VCE2 x IQ2 ≅ (VRING + 0.75 V) x (IQ2)
PQ3 ≅ VCE3 x IQ3 ≅ (VBAT – R106 x IQ5) x (IQ3)
PQ4 ≅ VCE4 x IQ4 ≅ (VBAT – R103 x IQ6) x (IQ4)
PQ5 ≅ VCE5 x IQ5 ≅ (VBAT – VRING – R106 x IQ5) x (IQ5)
PQ6 ≅ VCE6 x IQ6 ≅ (VBAT – VTIP – R103 x IQ6) x (IQ6)
The maximum power threshold for each device is
software progr amm able and should be se t ba sed on the
characteristics of the transistor package, PCB design,
and available airflow. If the peak power exceeds the
programmed threshold for any device, the power alarm
bit is set for that device. Each external bipolar has its
own register bit (PQ1S–PQ6S bits of the IRQVEC3
register) which goes high on a rising edge of the
Q2
Q5
R7
IRINGP
Q9
R7*gain
IRINGN
Q3
RING
Q1
Q6
R6
ITIPP
Q10
R6*gain
ITIPN
Q4
TIP
VBAT
RBQ6 RBQ5
Q8 Q7
82.51.74k 82.5 1.74k
Si3220/Si3225
34 Preliminary Rev. 0.91
comparator output and remains high until the user
clears it. Each transistor power alarm bit is also
maskable by setting the PQ1E–PQ6E bits in the
IRQEN3 register.
Si3200 Power Calculation
When using the Si3200, it is also possible to control
thermal temperature rise by calculating the total power
dissipated within the IC. This case is similar to the
Transistor Power Equations case, with the exception
that the total power from all transistor devices is
dissipated within the same package enclosure and the
total power result is placed in the PSUM RAM location.
The power calculation is derived using the following set
of equations:
PQ1 ≅ (VTIP + 0.75 V) x IQ1
PQ2 ≅ (VRING + 0.75 V) x IQ2
PQ3 ≅ (VBAT + 0.75 V) x IQ3
PQ4 ≅ (VBAT + 0.75 V) x IQ4
PQ5 ≅ (VBAT – VRING) x IQ5
PQ6 ≅ (VBAT – VTIP) x IQ6
PSUM = total dissipated power = PQ1 + PQ2 + PQ3 +
PQ4 + PQ5 + PQ6
Power Filter and Alarms
The power calculated during each A/D sample period
must be filtered before being compared to a user
programmable maximum power threshold. A simple
digital low pass filter is used to approximate the
transient thermal behavior of the package, with the
output of the filter representing the effective peak power
within the package or, equivalently, the peak junction
temperature.
For Q1, Q2, Q3, Q4 in SOT23 and Q5, Q6 in SOT223
packages, the settings for thermal low pass filter poles
and power threshold settings are (for an ambient
temperature of 70 °C) calculated as follows. If the
thermal time constant of the package is τthermal, the
decimal values of RAM locations PLPF12, PLPF34, and
PLPF56 are given by rounding to the next integer the
value given by the equation:
Where 4096 is the maximum value of the 12-bit plus
sign RAM locations PLPF12, PLPF34, and PLPF56,
and 800 is the power calculation clock rate in Hz. The
equation is an excellent approximation of the exact
equation for τthermal = 1.25 ms … 5.12 s. With the above
equations in mind, the values of the RAM locations
PLPF12, PLPF34, and PLPF5 6 are presented below:
PTH12 = power threshold for Q1, Q2 = 0.21 W (0x0480)
PTH34 = power threshold for Q3, Q4 = 0.21 W (0x2600)
PTH56 = power threshold for Q5, Q6 = 1.28 W
(0x1B80)
PLPF12 = thermal LPF pole for Q1, Q2 (0x0100 for
M = 128)
PLPF34 = thermal LPF pole for Q3, Q4 (0x0100 for
M = 128)
PLPF56 = thermal LPF pole for Q5, Q6 (0x0010 for
M = 2048)
In the case where the Si3200 is used, the thermal
filtering needs only to be performed only on the total
power reflected in the PSUM RAM location. When the
filter output exceeds the total power threshold, an
interrupt is issued. The PTH12 RAM location is used to
preset the total power threshold for the Si3200, and the
PLPF12 RAM location is used to preset the thermal low
pass filter pole.
Automatic State Change Based on Power Alarm
If any of the following situations occurs, the device will
automatically transition to the OPEN state:
!The thermometer based power alarm in the Si3200
is asserted.
!Any of the transistor power alarm thresholds is
exceeded, in the case of the discrete tr ansistor
circuit.
!The total power threshold is exceeded, when using
the power calculator method al ong with the Si3200.
To provide optimal reliability, the device automatically
transitions into the open st ate until the user changes the
state manua lly, independent of whe ther or not the power
alarm interrupt has been masked. The PQ1E–PQ6E
bits of the IRQEN3 register enable the interrupts for
each transistor power alarm and the PQ1S to PQ6S bit s
of the IRQVEC3 register are set when a power alarm is
triggered in the respective transistor. When using the
Si3200, the PQ1E bit enable s the power alar m inte rrupt,
and the PQ1S bit is set when a Si3200 power alarm is
triggered.
PLPFxx (decimal value) 4096
800 τthermal
×
------------------------------------
=
Si3220/Si3225
Preliminary Rev. 0.91 35
Power Dissipation Considerations
The Dual ProSLIC chipset is designed with the ability to
source long loop lengths in excess of 18 kft, but can
also accommodate short loop configurations. For
example, the Si3220 can operate from one of two
battery supplies depending on the operating state.
When in the on-hook state, the on-hook loop feed is
generated from the ringing battery supply, generally –
70 V or more. Once the SLIC transitions to the off-hook
state, a lower off-hook battery supply (typically –24 V)
supplies the required current to power the loop if the
loop length is sufficiently short to accommodate the
lower battery supply. This battery switching method
allows the SLIC chipset to dissipate less power than is
possible if operating from a –70 V battery supply. See
"Automatic Dual Battery Switching" on page 38 for more
details.
In long loop applications, there is generally a single
battery supply (e.g., –48 V) available for powering the
loop in the off-hook state. When sourcing loop lengths
similar to the maximum specified service distance (e.g.,
18 kft.), most of the power is dissipated in the
impedance of the line. SLICs used in long-loop
applications must also be able to provide phone service
to customers who are located much closer to the line
card than the maximum loop length specified for the
system. This situation may cause substantial power to
be dissipated inside the SLIC chipset, often resulting in
thermal shutdown or destruction of the device due to
thermal runaway.
The Dual ProSLIC devices rely on the Si3200 to power
the line from the battery supply. The PCB layout and
enclosure conditions should be designed to allow
sufficient thermal dissipation out of the Si3200, and a
programmable power alarm threshold ensures product
safety under all operating conditions. See "Power
Monitoring and Power Fault Detection" on page 33 for
more details on power alarm considerations.
The Si3200’s thermally enhanced SOIC-16 package
offer s an exposed p ad that improves th ermal dissip ation
out of the package when soldered to a top side PCB pad
connected to inner power planes. Using appropriate
layout practices, the Si3200 can provide a thermal
performance of 65 °C/W. The exposed path should be
connected to a low-impedance ground plane via a
topside PCB pad directly under the part. See package
outlines for PCB pad dimensions. In addition, an
opposite-side PCB pad with multiple vias connecting it
to the topside pad directly under the exposed pad will
further improve the overall thermal performance of the
system. Contact the factory for layout guidelines for
optimal thermal dissipation.
Loop Closure Detection
Loop closure detection is required to accurately signal a
terminal device going off-hook during the Active or On-
Hook Transmission linefeed states (forward or reverse
polarity). The functional blocks required to implement a
loop closure detector are shown in Figure 20, and the
register set for detecting a loop closure event is
Table 20. Register and RAM Locations Used for Power Monitoring and Power Fault Detection
Parameter Register/RAM
Mnemonic Register/RAM
Bits Measurement
Range Resolution
Si3200 Total Power Output Monitor PSUM PSUM[15:0] 0 to 16.319 W 498 µW
Si3200 Power Alarm Interrupt Pending IRQVEC3 PQ1S N/A N/A
Si3200 Power Alarm Interrupt Enable IRQEN3 PQ1E N/A N/A
Q1/Q2 Power Alarm Threshold PTH12 PTH12[15:0] 0 to 16.319 W 498 µW
Q3/Q4 Power Alarm Threshold PTH34 PTH34[15:0] 0 to 1.03 W 31.4 µW
Q5/Q6 Power Alarm Threshold PTH56 PTH56[15:0] 0 to 16.319 W 498 µW
Q1/Q2 Thermal LPF Pole PLPF12 PLPF12[15:0] See “Power Filter and Alarms”
Q3/Q4 Thermal LPF Pole PLPF34 PLPF34[15:0] See “Power Filter and Alarms”
Q5/Q6 Thermal LPF Pole PLPF56 PLPF56[15:0] See “Power Filter and Alarms”
Q1–Q6 Power Alarm Interrupt Pending IRQVEC3 PQ1S–PQ6S N/A N/A
Q1–Q6 Power Alarm Interrupt Enable IRQEN3 PQ1E–PQ6E N/A N/A
Si3220/Si3225
36 Preliminary Rev. 0.91
provided in Table 21. The pr imary in put to the sys tem is
the loop current sense value from the voltage/current/
power monitoring circuitry and reported in the ILOOP
RAM address. The LCS value is processed in the input
signal processor (ISP) provided the LFS bits in the
Linefeed register indicate the device is in an Active or
On-Hook Transmission state. The output of the ISP is
the input to a programma ble digital low pass filter, which
removes unwanted ac signal components before
threshold detection.
The low-pass filter coefficient is calculated using the
equation below and is entered into the LCRLPF RAM
location.
LCRLPF = [(2πf x 4096)/800]
Where f = the desired cutoff freque ncy of the filter.
The programmable range of the filter is from 0 (blocks
all signals) to 4000 (unfiltered). A typical value of 10 Hz
(0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
The output of the low pass filter is compared to a
programmable threshold, LCROFFHK. Hysteresis is
enabled by programming a second threshold,
LCRONHK, to detect the loop going to an open or on-
hook state. The threshold comparator output feeds a
programmable debounce filter. The output of the
debounce filter remains in its present state unless the
input remains in the opposite state for the entire period
of time programmed by the Loop closure debounce
interval, LCRDBI. There is also a loop closure mask
interval (LCRMASK) that is used to mask transients
caused when an internal ringing burst (with no offset)
ends in the presence of a high REN load. If the
debounce interval has been satisfied, the LCR bit is set
to indicate that a va lid loop clos ure has occurred .
Figure 20. Discrete Linefeed Circuit for Power Monitoring
ILOOP
LFS
LCRLPF
LCROFFHK
Input
Signal
Processor
Digital
LPF
Loop Closure
Threshold
Debounce
Filter
+
–
LCR
LCRONHK
LOOPS
LOOPE
Interrupt
Logic
LCRDBI
Loop
Closure
Mask
LCRMASK
Table 21. Register and RAM Locations Used for Loop Closure Detection
Parameter Register/RAM
Mnemonic Register/RAM
Bits Programmable
Range LSB
Size Effective
Resolution
Loop Closure Interrupt Pend-
ing IRQVEC2 LOOPS Yes/No N/A N/A
Loop Closure Interrupt Enable IRQEN2 LOOPE Yes/No N/A N/A
Linefeed Shadow LINEFEED LFS[2:0] Mo nitor only N/A N/A
Loop Closure Detect Status LCRRTP LCR Monitor only N/A N/A
Loop Closure Detect
Debounce Interval LCRDBI LCRDBI[15:0] 0 to 40.96 s 1.25 ms 1.25 ms
Loop Current Sense ILOOP ILOOP[15:0] 50.54 to
101.09 mA 3.097 µA500µA1
Si3220/Si3225
Preliminary Rev. 0.91 37
Ground Key Detection
Ground Key detection detects an alerting signal from
the terminal equipment during the Active linefeed state
(forward or reverse polarity). The functional blocks
required to implement a Ground Key detector are
shown in Figure 21, and the register set for detecting a
ground key event is provided in Table 22. The primary
input to the system is the Longitudinal Current Sense
value provided by the voltage/current/power monitoring
circuitry and reported in the ILONG RAM address. The
ILONG value is processed in the ISP provided the LFS
bits in the Linefeed register indicate the device is in an
Active state. The output of the ISP is the input to a
programmable digital low-pass filter, which removes
unwanted ac signal components before threshold
detection.
The low-pass filter coefficient is calculated using the
equation below and is entered into the LONGLPF RAM
location.
LONGLPF = [(2πf x 4096)/800]
Where f = the desired cutoff frequency of the filter.
The programmable range of the filter is from 0 (blocks
all signals) to 4000h (unfiltered). A typical value of
10 Hz (0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
The output of the low-pass filter is compared to the
programmable threshold, LONGHITH. Hysteresis is
enabled by programming a second threshold,
LONGLOTH, to de tect when th e ground key is r eleased.
The threshold comp ar ator output feed s a programm able
debounce filter. The output of the debounce filter
remains in its present state unless the input remains in
the opposite state for the entire period of time
programmed by the loop closure debounce interval,
LONGDBI. If the debounce interval is satisfied, the
LONGHI bit is set to indicate that a valid loop closure
has occurred .
Figure 21. Ground Key Detection Circuitry
Loop Closure Threshold (on-
hook to off-hook) LCROFFHK LCROFFHK[15:0] 0 to 101.09 mA23.097 µA396.4µA
Loop Closure Threshold (off-
hook to on-hook) LCRONHK LCRONHK[15:0] 0 to 101.09 mA23.097 µA396.4µA
Loop Closure Filter Coefficient LCRLPF LCRLPF[15:3] 0 to 4000h N/A N/A
Loop Closure Mask Interval LCRMASK LCRMASK[15:0] 0 to 40.96s 1.25 ms 1.25 ms
Notes:
1. ILOOP is a calculated value based on measured IQ1–IQ4 increments. The resulting effective resolution is approximately
500 µA.
2. The usable range for LCRONHK and LCROFFHK is limited to 61 mA. Entering a value > 61 mA will disable threshold
detection.
Table 21. Register and RAM Locations Used for Loop Closure Detection (Continued)
ILONG
LFS
LONGLPF
LONGHITH
Input
Signal
Processor
Digital
LPF
Ground Key
Threshold
Debounce
Filter
+
–
LONGHI
LONGLOTH
LONGS
LONGE
Interrupt
Logic
LONGDBI
Si3220/Si3225
38 Preliminary Rev. 0.91
Automatic Dual Battery Switching
The Dual ProSLIC chipsets provide the ability to switch
between several user-provided battery supplies to aid
thermal management. Two specific scenarios where
this method may be required are as follows:
!Ringing to off-hook state transition (Si3220):
During the on-hoo k op e ra tin g state, the Dual
ProSLIC chipset must operate from the ringin g
battery supply to provide the desired ringing signal
when required. Once an off-hook condition is
detected, the Dual ProS LIC chipset must transition
to the lower battery supply, typically –24 V, to reduce
power dissipation during the active state. The low
current consumed by the Dual ProSLIC chipset
during the on-hook state results in very little power
dissipation while being powered from the ringing
battery supply, which can have a n amplitu de as h igh
as –100 V depending on the desired rin ging
amplitude.
!On-hook to off-hook state, short loop feed
(Si3225): When sourcing both long and short loop
lengths, the Dual ProSLIC chipset can automatica lly
switch from the typical –48 V off- hook battery supp ly
to a lower of f-hook battery supply (e.g., –24 V) to
reduce the tot al off-hook po wer dissipation. The Dual
ProSLIC chipset continuously monitors the TIP-
RING voltage and selects the lowest battery voltage
required to power the loop when transitioning from
the on-hook to the off-hook state, thus assuri ng the
lowest power dissipation.
The BATSELa and BATSELb pins switch between the
two battery voltages based on the operating state and
the TIP-RING voltage. Figure 22 illustrates the chip
connections required to implement an automatic dual
battery switching scheme. When BATSEL is pulled
LOW, the desired channel is powered from the VBATL
supply. When BATSEL is pulled HIGH, the VBATH
source supplies power to the desired channel.
The BATSEL pins for both chan nels are controlled using
the BATSEL bit of the RLYCON register and can be
programmed to auto matically switch to th e lower ba tte ry
supply (VBATL) when the off-hook TIP-RING voltage is
low enough to allow proper operation from the lower
supply. When using the Si3220, this mode should
always be enabled to allow seamless switching
between the ringing and off-hook states. The same
switching scheme is used with the Si3225 to reduce
power by switching to a lower off-hook battery when
sourcing a short loo p.
Table 22. Register and RAM Locations Used for Ground Key Detection
Parameter Register/
RAM
Mnemonics
Register/RAM
Bits Programmable
Range LSB
Size Resolution
Ground Key Interrupt
Pending IRQVEC2 LONGS Yes/No N/A N/A
Ground Key Interrupt
Enable IRQEN2 LONGE Yes/No N/A N/A
Ground Key Linefeed
Shadow LINEFEED LFS[2:0] Monitor only N/A N/A
Ground Key Detect Status LCRRTP LONGHI Monitor only N/A N/A
Ground Key Detect
Debounce Interval LONGDBI LONGDBI[15:0] 0 to 40.96 s 1.25 ms 1.25 ms
Longitudinal Current Sense ILONG ILONG[15:0] Monitor only See Table 19
Ground Key Threshold
(enabled) LONGHITH LONG-
HITH[15:0] 0 to
101.09 mA* 3.097 µA 396.4 µA
Ground Key Threshold
(released) LONGLOTH LON-
GLOTH[15:0] 0 to
101.09 mA* 3.097 µA 396.4 µA
Ground Key Filter Coeffi-
cient LONGLPF LONGLPF[15:3] 0 to 4000h N/A N/A
*Note: The usable range for LONGHITH and LONGLOTH is limited to 16 mA. Setting a va lue > 16 mA will disable
threshold detection.
Si3220/Si3225
Preliminary Rev. 0.91 39
Two thresholds are provided to enable battery switching
with hysteresis. The BATHTH RAM location specifies
the threshold at which the Dual ProSLIC device
switches from the low battery (VBATL) to the high battery
(VBATH) due to an off-hook to on-hook transition. The
BATLTH RAM location specifies the threshold at which
the Si3220/Si3225 switches from VBATH to VBATL due to
a transition from the on-hook or ringing state to the off-
hook state or because the overhead during active Off-
Hook mode is sufficient to feed the subscriber loop
using a lower battery voltage.
The low pass filter coefficient is calculated using the
equation below and is entered into the BATLPF RAM
location.
BATLPF = [(2πf x 4096)/800]
Where f = the desired cuto ff frequency of the filter
The programmable range of the filter is from 0 (blocks
all signals) to 4000h (unfiltered). A typical value of
10 Hz (0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
Table 23 provides the register and RAM locations used
for programming the battery switching functions.
Figure 22. External Battery Switching Using the Si3220/Si3225
Table 23. Register and RAM Locations Used for Battery Switching
Parameter Register/RAM
Mnemonic Register/RAM
Bits Programmable
Range Resolution
(LSB Size)
Battery Select Switch RLYCON BATSEL Toggle N/A
High Battery Detect Threshold BATHTH BATHTH[14:7] 0 to 160.173 V* 628 mV
(4.907 mV)
Low Battery Detect Threshold BATLTH BATLTH[14:7] 0 to 160.173 V* 628 mV
(4.907 mV)
Ringing Battery Switch (Si3220 only) RLYCON GPO Toggle N/A
Battery Select Indicator RLYCON BSEL Toggle N/A
Battery Switching LPF BATLPF BATLPF[15:3] 0 to 4000h N/A
*Note: Usable range for BATHTH and BATLTH is limited to VBATH.
Si3220
Si3225
Battery
Sense
Circuit
Battery
Control
Logic
Si3200
Linefeed
Circuitry Battery
Select
Control
VBATL
VBATH
SVBAT BATSEL
BATSEL
40.2 kΩ
806 kΩ
VBATH
VBAT
VBATL
Si3220/Si3225
40 Preliminary Rev. 0.91
When generating a h igh- voltage ring ing a mplitude u sing
the Si3220, the power dissipated during the OHT state
typically increases due to operating from the ringing
battery supply in this mode. To reduce power, the
Si3220/Si3200 chipset provides the ability to
accommodate up to three separate battery supplies by
implementing a secondary battery switch using a few
low-cost external components as illustrated in Figure
22. The Si3220’ s BATSEL pin is used to switch between
the VBATH (typically –48 V) and VBATL (typically
–24 V) ra ils using th e switch inte rnal to the Si3200. The
Si3220’s GPO pin is used along with the external
transistor circuit to switch the VRING rail (the ringing
voltage battery rail) onto the Si3200’s VBAT pin when
ringing is enabled. The GPO signal is driven
automatically by the ringing cadence provided that the
RRAIL bit of the RLYCON register is set to 1 (signifying
that a third battery rail is present).
Figure 23. 3-Battery Switching with Si3220/
Si3200
Ringing Generation
The Si3220-based Dual ProSLIC chipset provides a
balanced ringing waveform, with or without dc offset.
The ringing frequency, cadence, waveshape, and dc
offset are register programmable.
Using a balanced ringing scheme, the ringing signal is
applied to both the TIP and the RING line s using rin ging
waveforms that are 180° out of phase with each other.
The resulting ringing signal seen across TIP-RING is
twice the amplitude of the ringing waveform on either
the TIP or the RING line, which allows the ringing
circuitry to withstand half the total ringing amplitude
seen across TIP-RING.
Figure 24. Balanced Ringing
An internal ringing scheme provides >40 Vrms into a
5REN load at the terminal equipment using a user-
provided ringing battery supply. The specific ringing
supply voltage required depends on the ringing voltage
desired. The ringing amplitude at the terminal
equipment depends on the loop impedance as well and
Table 24. 3-Battery Switching Components
Component Value Comments
D1 200 V, 200 mA 1N4003 or similar
Q1 100 V PNP CXT5401 or
similar
Q2 100 V NPN CXT5551 o r
similar
R101 1/10 W, ± 5% 2.4 kΩ for
VDD=3.3 V
3.9 kΩ for
VDD=5 V
Si3220
SVBAT
GPO
BATSEL
Si3200
VBAT
VBATH
VBATL BATSEL
VBAT
VBATH
VBATL
R6
40.2 kΩ
R9
40.2 kΩ
0.1 µF
0.1 µF
806 kΩ
D1
IN4003
R103
CXT5551
Q2
R102
Q1 CXT5401
R101
10 kΩ402 kΩ
R102 10 kΩ,1/10 W, ± 5%
R103 402 kΩ,1/10 W,± 1%
Table 24. 3-Battery Switching Components
Component Value Comments
RING
TIP
VRING
VTIP
SLIC VOFF
GND VTIP
VRING
VBATH
V PK
VOV
VCM
VOFF
Si3220/Si3225
Preliminary Rev. 0.91 41
the load impedance in REN. The following equation can
be used to determine the TIP-RING ringing amplitude
required for a specific load and loop condition.
Figure 25. Simplified Loop Circuit During
Ringing
where
When ringing longer loop lengths, adding a dc offset
voltage is necessary to reliably detect a ring trip
condition (off-hook phone). Adding dc offset to the
ringing signal decreases the maximum possible ringing
amplitude. Adding significant dc offset also increases
the power dissipation in the Si3200 and may require
additional airflow or modified PCB layout to maintain
acceptable operating temperatures in the line feed
circuitry. The Dual ProSLIC chipset automatically
applies and removes the ringing signal during VOC-
crossing periods to reduce noise and crosstalk to
adjacent lines. Table 25 provides a list of registers
required for inter nal ringing generation
RLOOP
VRING RLOAD VTERM
+
–
ROUT
VTERM VRING RLOAD
RLOAD RLOOP ROUT
++()
---------------------------------------------------------------------
×=
RLOOP 0.09Ω per foot for 26AWG wire()=
ROUT 320Ω=
RLOAD 7000Ω
#REN
------------------
=
Table 25. Register and RAM Locations Used for Ringing Generation
Parameter Register/
RAM
Mnemonic
Register/RAM
Bits Programmable
Range Resolution
(LSB Size)
Ringing Waveform RINGCON TRAP Sinusoid/Trapezoid N/A
Ringing Active Timer Enable RINGCON TAEN Enabled/Disabled N/A
Ringing Inactive Timer Enable RINGCON TIEN Enabled/Disabled N/A
Ringing Oscillator Enable
Monitor RINGCON RINGEN Enabled/Disabled N/A
Ringing Oscillator Active Timer RINGTALO/
RINGTAHI RINGTA[15:0] 0 to 8.19 s 125 µs
Ringing Oscillator Inactive
Timer RINGTILO/
RINGTIHI RINGTI[15:0] 0 to 8.19 s 125 µs
Linefeed Control
(Initiates Ringing State) LINEFEED LF[2:0] 000 to 111 N/A
On-Hook Line Voltage VOC VOC[15:0] 0 to 63.3 V 1.005 V
(4.907 mV)
Ringing Voltage Offset RINGOF RINGOF[15:0] 0 to 63.3 V 1.005 V
(4.907 mV)
Ringing Frequency RINGFRHI/
RINGFRLO RINGFRHI[14:3]/
RINGFRLO[14:3] 4 to 100 Hz
Ringing Amplitude RINGAMP RINGAMP[15:0] 0 to 160.173 V 628 mV
(4.907 mV)
Si3220/Si3225
42 Preliminary Rev. 0.91
Internal Sinusoidal Ringing
A sinusoidal ringing waveform is generated by the on-
chip digital tone generator. The tone generator used to
generate ringing tones is a two-pole resonator with a
programmable frequency and amplitude. Since ringing
frequencies are low compared to the audio band
signaling frequencies, the sinusoid is generated at a
1 kHz rate. The rin ging generato r is progra mmed via the
RINGFREQ, RINGAMP, and RINGPHAS registers. The
equations are as follows:
For example, to generate a 60 Vrms (87 VPK), 20 Hz
ringing signal, the equations are as follows:
In addition to the variable frequency and amplitude, a
selectable dc offset (VOFF), which can be added to the
waveform is included. The dc offset is defined in the
RINGOF RAM location.
As with the tone generators, the ringing generator has
two timers which function as described above. They
allow on/off cadence settings up to 8 s on/8 s off. In
addition to controlling ringing cadence, these timers
control the transition into and out of the ringing state.
To initiate ringing, the user must program the
RINGFREQ, RINGAMP, and RINGPHAS RAM
addresses as well as the RINGTA and RINGTI registers,
and select the ringing waveshape and dc offset. After
this is done, TAEN and TIEN bits are set as desired.
Ringing state is invoked by a write to the linefeed
register. At the expiration of RINGTA, the Dual ProSLIC
turns off the ringing waveform and goes to the on-hook
transmission state. At the expiration of RINGTI, ringing
is initiated again. This process continues as long as the
two timers are enabled and the linefeed register
remains in the ringing state.
Internal Trapezoidal Ringing
In addition to the traditional sinusoidal ringing
waveform, the Dual ProSLIC can generate a tr apezoidal
ringing waveform similar to the one illustrated in
Figure 26. The RINGFREQ, RINGAMP, and
RINGPHAS RAM addresses are used for programming
the ringing wave shape as follows:
RINGPHAS = 4 x Period x 8000
RINGAMP = (Desired V/160.8 V) x (215)
RINGFREQ = (2 x RINGAMP)/(tRISE x 8000)
RINGFREQ is a value that is added or subtracted from
the waveform to ramp the signal up or down in a linear
fashion. This value is a function of rise time, period, and
amplitude, where rise time and period are related
through the following equation for the crest factor of a
trapezoidal waveform.
where
Ringing Initial Phase
Sinusoidal
Trapezoid
External Ringing
RINGPHAS RINGPHAS[15:0] N/A
0 to 1.024 s
0 to 662.83 mA
N/A
31.25 µs
2.6 mA (20.3 µA)
Ringing Relay Driver Enable
(Si3225 only) RELAYCON RDOE Enabled/Disabled N/A
Ringing Overhead Voltage VOVRING VOVRING[15:0] 0 to 63.3 V 1.005 V
(4.907 mV)
Table 25. Register and RAM Locations Used for Ringing Generation (Continued)
Parameter Register/
RAM
Mnemonic
Register/RAM
Bits Programmable
Range Resolution
(LSB Size)
coeff 2πf
1000Hz
---------------------
cos=
RINGAMP 1
4
---1 coeff–
1coeff+
------------------------215
()×DesiredVPK
160.173V
---------------------------------
×=
RINGPHAS 0=
RINGFREQ coeff 223
()=
coeff 2π20
1000Hz
---------------------
99211=cos=
RINGFREQ 99211 223
()×8322461
0x7EFD9D ===
RINGAMP 1
4
---00789
1.99211
--------------------- 215
()×85
160.173
---------------------
×273 0x111===
tRISE 3
4
---T1 1
CF2
-----------
–
=
Si3220/Si3225
Preliminary Rev. 0.91 43
So for a 90 VPK, 20 Hz trapezoidal waveform with a
crest factor of 1.3, the period is 0.05 s and the rise time
requirement is 0.015 s.
RINGPHAS = 4 x 0.05 x 8000 = 1600 (0x0640)
RINGAMP = 90/160.8 x (215) = 18340 (0x47A5)
RINGFREQ = (2 x RINGAMP)/(0.0153 x 8000) = 300
(0x012C)
The time registers and interrupts described in the
sinusoidal ring description also apply to the trapezoidal
ring waveform.
Ringing Coefficients
The ringing coefficients are calculated in decimal for
sinusoidal and trapezoidal waveforms. The RINGPHAS
and RINGAMP hex values are decimal to hex
conversions in 16-bit, 2’s complement representations
for their respective RAM locations.
To obtain sinusoidal RINGFREQ RAM values, the
RINGFREQ decima l numbe r is converted to a 24-bit 2’s
complement value. The lower 12 bits are placed in
RINGFRLO bits 14:3. RINGFRLO bits 15 and 2:0 are
cleared to 0. The upper 12 bits are set in a similar
manner in RINGFRHI, bits 13:3. RINGFRHI bit 14 is the
sign bit and RINGFRHI bits 2:0 are cleared to 0.
For example, the register values for
RINGFREQ=0x7EFD9D are as follows:
RINGFRHI = 0x3F78
RINGFRLO = 0x6CE8
To obtain trapezoidal RINGFREQ RAM values, the
RINGFREQ decimal number is conve rted to an 8-bit, 2’ s
complement value. This value is loaded into RINGFRHI.
RINGFRLO is not used.
Figure 26. Trapezoidal Ringing Waveform
Ringing DC Offset Voltage
A dc offset voltage can be added to the Si3220’s ac
ringing waveform by programming the RINGOF RAM
location to the appropriate setting. The value of
RINGOF is calculated as follows:
External Unbalanced Ringing
The Si3225 supports centralized, battery-backed
unbalanced ringing schemes by providing a ringing
relay driver as well as inputs from an external ring trip
circuit. Using this scheme, line-card designers can use
the Dual ProSLIC chipset in existing system
architectures with minimal system changes.
Linefeed Overhead Voltage Considerations
During Ringing
The ringing mode output impedance allows ringing
operation without overhead voltage modification
(VOVR = 0). If an offset of the ringing signal from the
ring lead is desired, VOVR can be used for this
purpose.
Ringing Power Considerations
The total power consumption of the Si3220/Si3200
chipset using internal ringing generation is dependent
on the VDD supply voltage, the desired ringing
amplitude, the total loop impedance, and the AC load
impedance (number of REN). The following equations
can be used to approximate the total current required
for each channel during ringing mode.
VDD = 3.3 V:
VDD = 5 V:
And
Where:
REN = number of REN
RLOAD = 7000/REN for North America
RLOOP = loop impedance
ROUT = ProSLIC output impedance = 320 Ω
TPeriod 1
fRING
-------------- CF desired crest factor===
VTIP-RING
VOFF
tRISE
T = 1/freq
time
RINGOF VOFF
64.32
---------------215
×=
IDD,AVE 22mA 6mA REN×()+=
IDD,AVE 26mA 6mA REN×()+=
IBAT,RMS vRING,RMS
RLOAD RLOOP ROUT
++
---------------------------------------------------------------- 2.04
π
-----------
×=
Si3220/Si3225
44 Preliminary Rev. 0.91
Ring Trip Detection
A ring trip event signals that the terminal equ ipment has
transitioned to an off-hook state after ringing has
commenced, ensuri ng th at the r inging signal is r emove d
before normal speech begins. The Dual ProSLIC is
designed to implement either an ac- or dc-based
internal ring trip detection scheme or a combination of
both schemes. The system design is flexible to address
varying loop lengths of different applications. An ac ring
trip detection scheme cannot reliably detect an off-hook
condition when sourcing longer loop lengths, as the
20 Hz ac impedance of an off-hook long loop is
indistinguishable from a heavily loaded (5 REN) short
loop in the on-hook state. Therefore, a dc ring trip
detection scheme is require d when sou rcing long er loo p
lengths.
The Si3220 can implement either an ac- or dc-based
ring trip detection scheme, de pending on the application .
The Si3225 allows external dc ring trip detection when
using a battery-backed external ringing generator by
monitoring the ringing feed path through two sensing
inputs on each channel. By monitoring this path, the
Dual ProSLIC detects a dc current flowing in the loop
once the end equipment has gone off-hook. Table 26
provides recommended register and RAM settings for
various applications, and Table 27
lists the register and
RAM addresses that must be written or monitored to
correctly detect a ring trip condition.
Figure 27 illustrates the internal functional blocks that
correctly detect and process a ring trip event. The
primary input to the system is the loop current sense
(ILOOP) valu e provided by th e loop monitoring circu itry
and reported in the ILOOP RAM location register. The
ILOOP RAM location value is processed by the ISP
block when the L FS bits in the L inefe ed register ind icate
the device is in the ringing state. The output of the ISP
then feeds into a pair of programmable digital low-pass
filters; one fo r th e ac r ing tr ip de tectio n path and one for
the dc path. The ac path also includes a full wave
rectifier block prior to the LPF block. The outputs of
each low pass filter block are then passed on to a
programmable ring trip threshold (RTACTH for ac
detection and RTDCTH for dc detection). Each
threshold block output is then fed to a programmable
debounce filter to ensure a valid ring trip event. The
output of each debounce filter remains constant unless
the input remains in the opposite state for the entire
period of time set using the ac and dc ring trip deboun ce
interval registers, RTACDB and RTDCDB, respectively.
The outputs of both debounce filter blocks are then
ORed together. If either the ac or the dc ring trip circuits
indicate a valid ring trip event has occurred, the RTP bit
is set. Either the ac or dc ring trip detection circuits are
disabled by setting the respective ring trip threshold
sufficiently high so that it does not trip under any
condition. A ring trip interrupt also generates if the
RTRIPE bit is enabled.
Ringtrip Timeout Counter
The Dual ProSLIC incorporates a ringtrip timeout
counter (RTCOUNT) that will monitor the status of the
ringing control. When exiting ringing, the Dual ProSLIC
will allow the ringtrip timeout counter amount of time
(RTCOUNT x 1.25 ms/LSB) for the mode to switch to
On-hook Transmission or Active. The mode that is
being exited to is governed by whether the command to
exit ringing is a ringing active timer expiration (on-hook
transmission) or ringtrip/manual mode change (Active
mode). The ringtrip timeout counter will assure ringing is
exited within its time setting (RTCOUNT x 1.25 ms/LSB,
typically 200 ms).
Ringtrip Debounce Interval
The ac and dc ring trip debounce intervals can be
calculated based on the following equations:
RTACDB = tdebounce (1600/RTPER)
RTDCDB = tdebounce (1600/RTPER)
Si3220/Si3225
Preliminary Rev. 0.91 45
Figure 27. Ring Trip Detect Processing Circuitry
Input
Signal
Processor
Digital
LPF +
_
AC Ring Trip
Threshold
RTPER
LFS
ILOOP
RTACTH
Debounce
Filter_AC
Interrupt
Logic RTRIPS
RTP
RTRIPE
+
_
DC Ring Trip
Threshold
RTDCTH
Debounce
Filter_DC
RTACDB
RTDCDB
Digital
LPF
Full Wave
Rectifier
Si3220/Si3225
46 Preliminary Rev. 0.91
Loop Closure Mask
The Dual ProSLIC implements a loop closure mask to
ensure mode change between Ringing and Active or
On-hook Transmission without causing an erroneous
loop closure detection. The loop closure mask register,
LCRMASK, should be set such that loop closure
detection is ignored for LCRMASK 1.25 ms/LSB
amount of time. The programmed time is set to mask
detection of tran sitio n al cu rr en ts that occur wh en exit ing
the ringing mode while driving a reactive load (i.e., 5
REN). A typical setting is 80 ms (LCRMASK = 0x40).
Si3220 Ring Trip Detection
The Si3220 provides the ability to process a ring trip
event using an ac-based detection scheme. Using this
scheme eliminates the need to add dc offset to the
ringing signal, which reduces the total power dissipation
during the ringing state and maximizes the available
ringing amplitude. This scheme is valid for shorter loop
lengths only since it cannot reliably detect a ring trip
event if the off-hook line impedance overlaps the on-
hook impedance at 20 Hz.
The Si3220 also can add a dc offset component to the
ringing signal and detect a ring trip event by monitoring
the dc loop current flowing once the terminal equipment
transitions to the off-hook state. Although adding dc
offset reduces the maximum available ringing amplitude
(using the same ringing supply), this method is required
to reliably detect a valid ring trip event when sourcing
longer loop lengths. The dc offset can be programmed
from 0 to 64.32 V in the RINGOF RAM address as
Table 26. Recommended Values for Ring Trip Registers and RAM Addresses1
Ringing
Method Ringing
Frequency DC
Offset
Added?
RTPER RTACTH RTDCTH RTACDB/
RTDCDB
Internal
(Si3220)
16–32 Hz Yes 800/fRING 221 x RTPER 0.577(RTPER x VOFF)
See Note 2
No 800/fRING 1.59 x VRING,PK x RTPER 32767
33–60 Hz Yes 2(800/fRING) 221 x RTPER 0.577(RTPER x VOFF)
No 2(800/fRING)1.59xV
RING,PK x RTPER 32767
External
(Si3225) 16–32 Hz Yes 800/fRING 32767 0.067 x RTPER x VOFF
33–60 Hz Yes 2(800/fRING) 32767 0.067 x RTPER x VOFF
Notes:
1. All calculated values should be rounded to the nearest integer.
2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations.
Table 27. Register and RAM Locations Used for Ring Trip Detection
Parameter Register/RAM
Mnemonic Register/RAM
Bits Programmable
Range Resolution
Ring Trip Interrupt Pending IRQVEC2 RTRIPS Yes/No N/A
Ring Trip Interrupt Enable IRQEN2 RTRIPE Enabled/Disabled N/A
AC Ring Trip Threshold RTACTH RTACTH[15:0] See Table 26
DC Ring Trip Threshold RTDCTA RTDCTH[15:0] See Table 26
Ring Trip Sample Period RTPER RTPER[15:0] See Table 26
Linefeed Shado w (m on ito r on ly) LINEFEED LF S[ 2:0 ] N/A N/A
Ring Trip Detect Status
(monitor only) LCRRTP RTP N/A N/A
AC Ring Trip Detect Debounce
Interval RTACDB RTACDB[15:0] 0 to 40.96 s 1.25 ms
DC Ring Trip Detect Debounce
Interval RTDCDB RTDCDB[15:0] 0 to 40.96 s 1.25 ms
Loop Current Sense
(monitor only) ILOOP ILOOP[15:0] 0 to 101.09 mA See
Table 19
Si3220/Si3225
Preliminary Rev. 0.91 47
required to produce adequate dc loop current in the off-
hook state. Depending on the loop length and the ring
trip method, the ac or dc ring trip detection circuits are
disabled by setting their respective ring trip thresholds
(RTACTH or RTDCTH) sufficiently high so it does not
trip under any condition.
Si3225 Ring Trip Detection
The Si3225 implements an external ring trip detection
scheme when using a st andard battery- backed, external
ringing generator. In this application, the centralized
ringing generator produces an unbalanced ringing
signal that is distributed to individual TIP/RING pairs. A
per-channel ringing relay is required to disconnect the
Si3225 from the TIP/RING pair and apply the ringing
signal. By monitoring the ringing feed path across a ring
feed sense resistor (RRING in Figure 31) in series with
the ringing source, the Si3225 can detect the dc current
path created when the hook switch inside the terminal
equipment closes. The internal ring trip detection
circuitry is identical to that illustrated in Figure 27.
Figure 31 illustrates the typical external ring trip circuitry
required for the Si32 25. Because of the long lo op nature
of these applications, a dc ring trip detection scheme is
used typically. The user can disable the ac ring trip
detection circuitry by setting the RTACTH threshold
sufficiently high so it does not trip under any condition.
Relay Driver Considerations
The Dual ProSLIC devices include up to three
dedicated relay drivers to drive external ringing and/or
test relays. Test relay drivers TRD1a, TRD1b, TRD2a,
and TRD2b are provided in all product versions, and
ringing relay drivers RRDa and RRDb are included for
the Si3225 only. In most applications, the relay can be
driven directly from the Dual ProSLIC with no external
relay drive circuitry required. Figure 28 illustrates the
internal relay driver circuitry using a 3 V or 5 V relay.
Figure 28. Dual ProSLIC Internal Relay Drive
Circuitry
The internal driver logic and drive circuitry is powered
by the same VDD supply as the chip’s main VDD supply
(VDD1–VDD4 pins). When operating external relays
from a VCC supply equal to the chip’s VDD supply, an
internal diode network provides protection against
overvoltage conditions from flyback spikes when the
relay is opened. Both 3 V or 5 V relays can be used in
the configuration shown in Figure 28 and either
polarized or non-polarized relays are acceptable if the
VCC and VDD supplies are identical. The input
impedance (RIN) of the relay driver pins is a constant
11 Ω while sinking less than the maximum rated 85 mA
into the pin.
If the ope rating voltage of the relay ( VCC) is higher than
the Dual ProSLIC’s VDD supply voltage, an external
drive circuit is required to eliminate leakage from VCC to
VDD through the internal protection diode. In this
configuration, a polarized relay will provide optimal
overvoltage protection and minimal external
components. Figure 29 illustrates the required external
drive circuit and Table 28 provides recommended
values for RDRV for typical relay characteristics and VCC
supplies. The output impedance (ROUT) of the relay
driver pins is a constant 63 Ω while sourcing less than
the maximum rated 28 mA out of the pin.
Si3220/
Si3225
Relay
Driver
Logic
VDD
GDD
RRDa/b
TRD1a/b
TRD2a/b
VCC
3 V/5 V Relay
(polarized or
non-polarized)
Si3220/Si3225
48 Preliminary Rev. 0.91
Figure 29. Driving Relays with VCC > VDD
The maximum allowable RDRV value can be calculated with the following equation:
Where βQ1,MIN ~ 30 for a 2N2222.
Table 28. Recommended RDRV Values
ProSLIC VDD Relay VCC Relay RCOIL Maximum RDRV Recommended 5% Value
3.3 V ±5% 3.3 V ±5% 64 ΩNot Required —
5 V ±5% 5 V ±5% 178 ΩNot Required —
3.3 V ±5% 5 V ±5% 178 Ω2718 Ω2.7 kΩ
3.3 V ±5% 12 V ±10% 1028 Ω6037 Ω5.6 kΩ
3.3 V ±5% 24 V ±10% 2880 Ω8364 Ω8.2 kΩ
3.3 V ±5% 48 V ±10% 7680 Ω11092 Ω11 kΩ
5V ±5% 12V ±10% 1028Ω9910 Ω9.1 kΩ
5V ±5% 24V ±10% 2880Ω13727 Ω13 kΩ
5V ±5% 48V ±10% 7680Ω18202 Ω18 kΩ
Si3220/
Si3225
VDD
RRDa/b
TRD1a/b
TRD2a/b
VCC
Polarized
relay
RDRV
IDRV
Q1
MaxRDRV VDD,MIN 0.6 V–()RRELAY
()β
Q1,MIN
()
VCC,MAX 0.3 V–
-------------------------------------------------------------------------------------------------RSOURCE
–=
Si3220/Si3225
Preliminary Rev. 0.91 49
611109870 54321 6 11109870 54321 6 11109870 54321 60 54321
0 54321 0 543216 1110987 0 543216 1110987 06 1110987
IRINGXSCAL
COUNTER0
COUNTER1
RINGEN
RRD On Off On Off
LF Ringing Active
Ringing OHT Ringing Active
LFSDELAY LFSDELAY
LFS
ZERDELAY D
Figure 30. Timing Characteristics for Ringing Relay Control
Si3220/Si3225
50 Preliminary Rev. 0.91
Figure 31. Si3225 External Ring Trip Circuitry
Ringing Relay Activation During Zero Crossings
The Si3225 is for applications that use a centralized
ringing generator and a per-channel ringing relay to
connect the ringing signal to the TIP/RING pair. The
Si3225 has one relay driver output per channel (RRDa
and RRDb) that can drive a mechanical or solid-state
DPDT relay. To reduce impulse noise that can couple
into adjacent lines, the relay should be closed when
there is zero voltage across the relay contacts and
opened during periods when there is zero current
through the contacts.
Closing the Relay at Zero Voltage
Internal voltage monitoring circuitry closes the relay at
zero voltage with respect to the line voltage. By
observing the phase of the ringing signal and constantly
monitoring the open-circuit T-R voltage, VOC, the
Si3225 can detect the next time when there is zero
voltage across the relay contacts.
Opening the Relay at Zero Current
Opening the ringing relay at zero current also is
accomplished using the internal monitoring circuitry and
prevents arcing from excess cur rent flow when the relay
contacts are opened. The current flowing through the
ringing relay is continuously monitored in the IRNGNG
RAM address, and two internal counters (COUNTER0
and COUNTER1) detect time elapsed since the last two
zero current crossings based on the ringing period and
predict when the next zero cr ossing oc curs. The r inging
relay current and internal counters are both updated at
an 8 kHz rate. To account for the mechanical delay of
the relay, a programmable advance firing timer allows
the user to initiate relay opening up to 10 ms prior to the
zero current crossing event. Figure 30 illustrates the
timing sequence for a typical ringing relay control
application.
During a typical ringing sequence, the Si3225 monitors
both the ringing relay current (IRNGNG) and the
RINGEN bit of the RINGCON register. The RINGEN bit
toggles because of pre-programmed ringing cadence or
a change in operating state. COUNTER0 and
COUNTER1 are re-started at each alternating zero
current crossing event, and the delay period
ZERDELAY equal to the ringing frequency period less
the desired advance firing time (D) is entered by the
user. If either counter reaches the same value as
ZERDELAY, the relay control signal is enabled when the
RINGEN bit transition has already occurred. During
typical ringing bursts, the LFS bits of the Linefeed
register toggle between the RINGING and OHT states
based on the pre-programmed ringing cadence. The
transition from OHT to RINGING is synchronized with
the RRD state transitions so the ringing burst starts
immediately. The transition from RINGING to OHT is
gated by a user-programmed delay period LFSDELAY
that ensures the ringing burst has ceased before going
to the OHT state or to the ACTIVE state in response to a
Linefeed state change.
VRING
VOFF
806 kΩ806 kΩ
510 Ω
+_
Si3200
RING
TIP Protection
Si3225
BLkRING
RTRP
Relay
Hook
Switch
Phone
VDD
RRD
Si3220/Si3225
Preliminary Rev. 0.91 51
Polarity Reversal
The Dual ProSLIC devices support polarity reversal for
message waiting functionality and various signaling
modes. The ramp r ate can be programmed for a smooth
transition or an abrupt transition to accommodate
different application requirements. A wink function is
provided for special equipment that responds to a
smooth ramp to VOC = 0 V. Table 29 illustrates the
register bits required to program the polarity reversal
modes.
Setting the Linefeed register to the opposite polarity
immediately reverses (hard reversal) the line polarity.
For example, to transition from Forward Active mode to
Reverse Active mode changes LF[2:0] from 001 to 101.
Polarity reversal is accommodated in the OHT and
ground start modes. The POLREV bit is a read-only bit
that reflects if the device is in Polarity Reversal mode.
For smooth polarity reversal, set the PREN bit to 1 and
the RAMP bit to 0 or 1 depending on the desired ramp
rate (see Table 29). Polarity reversal is then
accomplished by toggling the linefeed register from
forward to reverse modes as desired.
A wink function slowly ramps down the TIP-RING
voltage (VOC) to 1 followed by a return to the original
VOC value (set in the VOC RAM location). This scheme
lights a message-waiting lamp in certain handsets. No
change to the linefeed register is necessary to enable
this function. Instead, the user sets the VOCZERO bit to
1 so that the TIP-RING voltage collapses to 0 V at the
rate programmed by the RAMP bit. Setting the
VOCZERO bit back to 0 returns the TIP-RING voltage
to its normal setting. With a software timer, the user can
automate the cadence of the wink function. Figure 32
illustrates the wink function.
Table 29. Register and RAM Locations used for Polarity Reversal
Parameter Programmable Range Register/RAM
Bits Register/RAM
Mnemonic
Linefeed See table 15 LF[2:0] LINEFEED
Polarity Reversal Status Read only POLREV POLREV
Wink Function
(Smooth transition to Voc=0V) 1 = Ramp to 0 V
0 = Return to previous VOC
VOCZERO POLREV
Smooth Polarity Reversal Enable 0 = Disabled
1 = Enabled PREN POLREV
Smooth Polarity Reversal Ramp
Rate 0 = 1 V/1.25 ms
1 = 2 V/1.25 ms RAMP POLREV
Si3220/Si3225
52 Preliminary Rev. 0.91
Figure 32. Wink Function with Programmable Ramp Rate
Two-Wire Impedance Synthesis
Two-wire impedance synthesis is performed on-chip to
optimally match the output impedance of the Dual
ProSLIC to the impedance of the subscriber loop to
minimize the receive path signal reflected back onto the
transmit path. The Dual ProSLIC chipset provides on-
chip digitally programmable, two-wire impedance
synthesis to meet return loss requirements against
virtually any global two-wire impedance requirement.
Real and complex two- wire impedances ar e realized by
a programmable digital filter block. (See Z block in
Figure 11 on page 22.)
Figure 33. Two-Wire Impedance Synthesis
Configuration
The two-wire impedance is programmed by loading the
desired real or complex impedance value into the
Si322X Coefficient Generator software in the format RS
+ RP||CP, as shown in Figure 33. The software
calculates the appropriate hex coefficients and loads
them into the appropriate control registers
(registers 33–52). The two-wire impedance can be set
to any real or complex value within the boundaries set in
Table 30. The actual impedance presented to the
subscriber loop varies with series impedance from
protection devices placed between the Dual ProSLIC
chipset outputs and the TIP/RING pair according to the
following equation:
Where: ZT is the termination impedance presented
to the TIP/RING pair
VTIP/RING (V)
50
40
30
20
10
0Time (ms)
5040302010 60 70 800
2 V/1.25 ms sl ope
set by RAMP bit
Set VOCZERO bit to 1 Set VOCZERO bit to 0
VOC = 48 V
RP
CP
RS
Table 30. Two-Wire Impedance
Synthesis Limitations
Desired
Configuration Programmable Limits
RS only 100–1000 Ω
RS + CPRS x CP > 0.5 ms
RS + RP||CPRS/(RS + RP) > 0.1
ZT2RPROT RSRPCP
||
+()+=
Si3220/Si3225
Preliminary Rev. 0.91 53
RPROT is the series resistance caused by
protection de vice s
RS is the series portion of the synthesized
impedance
RP||CP is the parallel portion of the
synthesized impedance
The user must enter the value of RPROT into the
software so the equalizer block can compensate for
additional series impedance. (See Figure 11 on page
22.) Figure 34 illustrates the simplified two-wire
impedance circuit including external protection
resistors, where ZL is the actual line impedance for the
specific geographical re gion. The Dua l Pro SLIC de vices
can accomodate up to 50 Ω of series protection
impedance per leg. The Dual ProSLIC devices load a
600 Ω default setting into the RS register if the user
does not define the impedance setting, which assumes
there is no additional series protection resistance.
The ac impedance generation scheme is comprised of
analog and DSP-based coefficients. To turn off the
analog coefficients (RS, ZP, and ZZ bits in the ZRS and
ZZ registers), the user can simply set the ZSDIS bit of
the ZZ register to 0. To turn off the DSP coefficients
(ZA1H1 through ZB3LO registers), each register must
be loaded with 0x00.
Figure 34. Two-Wire Impedance Simplified
Circuit
Transhybrid Balance Filter
The Dual ProSLIC devices provide a transhybrid
balance function via a digitally programmable balance
filter block. (See “H” block in Figure 11 on page 22.) The
Dual ProSLIC devices implement a 8 -ta p FIR filte r and a
second order IIR filter, both running at a 16 kHz sample
rate. These two filters combine to form a digital replica
of the reflected signal (echo) from the transmit path
inputs. The user can filter settings on a per-line basis by
loading the desired impedance cancellation coefficients
into the appropriate registers. The Si322X Coefficient
Generator software interface is provided for calculating
the appropriate coefficients for the FIR and IIR filter
blocks.
The transhybrid balance filters can be disabled to
implement loopback diagnostic modes. To disable the
transhybrid balance filter (zero cancellation), set the
HYBDIS bit in the DIGCON register to 1. With the hybrid
balance cancellation scheme disabled, the user can
accurately measure the full transmit path signal to
measure the two-wire return loss.
Note: The user must enter va lues into each register location
to ensure correct operation when the hybrid balance
block is enabled.
Tone Generators
Dual ProSLIC devices have two digital tone generators
that allow a wide variety of single or dual tone frequ ency
and amplitude combinations that spare the user the
effort of generating the required POTS signaling tones
on the PCM highway. DTMF, FSK (caller ID), call
progress, and other tones can all be generated on-chip.
The tones are sent to the receive or transmit paths.
(See Figure 11 on page 22.)
Tone Generat or Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 35. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected for flexibility in creating audio signals.
Control and status register bits are placed in the figure
to indicate their association with the tone generator
architecture. The register set for tone generation is
summarized in Table 31 on page 55.
Dual
ProSLIC
ZT
ZL
RPROT
RPROT
Si3200
TIP
RING
Si3220/Si3225
54 Preliminary Rev. 0.91
Figure 35. Tone Generator Diagram
Oscillator Frequency and Amplitude
Each of the two tone generators contains a two-pole
resonant oscillator circuit with a programmable
frequency and amplitude, which are programmed via
RAM addresses OSC1FREQ, OSC1AMP, OSC1PHAS,
OSC2FREQ, OSC2AMP, and OSC2PHAS. The sample
rate for the two oscillators is 8000 Hz. The equations
are as follows:coeffn = cos(2π fn/8000 Hz),
where fn is the frequency to be generated;
OSCnFREQ = coeffn x (214);
where desired Vrms is the amplitude to be generated;
OSCnPHAS = 0,
n = 1 or 2 for oscillator 1 or oscillator 2, respectively.
For example, to generate a DTMF digit of 8, the two
required tones are 852 Hz and 1336 Hz. Assuming we
want to generate half-scale values (ignoring twist), the
following values are calculated:
OSC1PHAS = 0
coeff2 = cos (2π 1336 / 8000) = 0.4981 9
OSC2FREQ = 0.49819 (214) = 8162 = 0x1FE2
OSC2PHAS = 0
The computed values above are written to the
corresponding registers to initialize the oscillators. Once
the oscillators are initialized, the oscillator control
registers can be accessed to enable the os cillators and
direct their outputs.
Tone Generator Cadence Programming
Each of the two tone generators contains two timers,
one for setting the active period and one for setting the
inactive period. The oscillator signal is generated during
the active period and suspended during the inactive
period. Both the active and inactive periods can be
programmed from 0 to 8 seconds in 125 µs steps. The
active period time interval is set using OSC1TA for tone
generator 1 and OSC2TA for tone generator 2.
ZEROENn
ENSYNCn
*Tone Generator 1 Only
n = "1" or "2" for Tone Generator 1 and 2, respectively
Two-Pole
Resonant
Oscillator
16-Bit
Modulo
Counter
OSCnTA
OSCnTI
OSCnTIEN
OSCnTAEN
OSCnFREQ
OSCnPHAS
OSCnAMP
Load
Logic
Zero
Cross
Logic Signal
Routing
ROUTn
to TX Path
to RX Path
INT
Logic OSnTIS
OSnTIE
INT
Logic OSnTAS
OSnTAE
REL*
Register
Load
Enable
8 kHz
Clock
Zero Cross
OSCnEN
OSCnTA
Expire
OSCnTI
Expire
8 kHz
Clock
OSCnAMP 1
4
---1 coeff–
1 coeff+
------------------------215 1–()×DesiredVrms
1.11Vrms
--------------------------------------
×=
coeff12π852
8000
-----------------
cos 0.78434==
OSC1FREQ 0.78434 214
()12851 0x3233===
OSC1AMP 1
4
---0.21556
1.78434
--------------------- 215 1–()×0.5 1424
0x590=
=×=
OSC2AMP 1
4
---0.50181
1.49819
--------------------- 215 1–()×0.5 2370
0x942=
=×=
Si3220/Si3225
Preliminary Rev. 0.91 55
To enable automatic cadence for tone generator 1,
define the OSC1TA and OSC1TI registers and then set
the OSC1TAEN and OSC1TIEN bits. This enables each
of the timers to control the state of the Oscillator Enable
bit, OSC1EN. The 16-bit counter counts until the active
timer expires, when the 16-bit counter resets to zero
and begins counting until the inactive timer expires. The
cadence continues until the user clears the OSC1TA
and OSC1TIEN control bits. Setting the ZEROEN1 bit
implements the zero crossing detect feature. This
ensures that each oscillator pulse ends without a dc
component. The timing diagram in Figure 36 is an
example of an output cadence that uses the zero
crossing feature.
One-shot oscillation is possible with OSC1EN and
OSC1TAEN. Direct control over the cadence is
achieved by setting the OSC1EN bit directly if
OSC1TAEN and OSC1TIEN are disab led .
The operation of tone generator 2 is identical to that of
tone generator 1 using its respective control registers.
Note: Tone Generator 2 should not be enabled simulta-
neously with the ringing oscillator because of resource
sharing within the hardware.
Table 31. Register and RAM Locations Used for Tone Generation
Tone Generator 1
Parameter Register/RAM
Mnemonics Register/RAM Bits Description/Range
(LSB Size)
Oscillator 1 Frequency
Coefficient OSC1FREQ OSC1FREQ[15:3] Sets oscillator frequency
Oscillator 1 Amplitude Coefficient OSC1AMP OSC1AMP[15:0] Sets oscillator amplitude
Oscillator 1 Initial Phase
Coefficient OSC1PHAS OSC1PHAS[15:0] Sets initial phase
(default = 0)
Oscillator 1 Active Timer O1TALO/O1TAHI OSC1TA[15 :0] 0 to 8.19 s (125 µs)
Oscillator 1 Inactive Timer O1TILO/O1TIHI OSC1TI[15:0] 0 to 8.19 s (125 µs)
Oscillator 1 Control OMODE, OCON FSKSSEN, OSC1FSK,
ZEROEN1, ROUT1,
ENSYNC1, OSC1TAEN,
OSC1TIEN, OSC1EN
Enables all Oscillator 1 param-
eters
Oscillator 1 Interrupts IRQVEC1, IRQEN1 OS1TAS, OS1TIS, OS1TAE,
OS1TIE Interrupt enable/status
Tone Generator 2
Parameter Location Register/RAM Address Description/Range
Oscillator 2 Frequency
Coefficient OSC2FREQ OSC2FREQ[15:3] Sets oscillator frequency
Oscillator 2 Amplitude Coefficient OSC2AMP OSC2AMP[15:0] Sets oscillator amplitude
Oscillator 2 Initial Phase
Coefficient OSC2PHAS OSC2PHAS[15:0] Sets initial phase
(default = 0)
Oscillator 2 Active Timer O2TALO/O2TAHI OSC2TA[15:0] 0 to 8.19 s (125 µs)
Oscillator 2 Inactive Timer O2TILO/O2TIHI OSC2T I[15:0] 0 to 8.19 s (125 µs)
Oscillator 2 Control OMODE, OCON ZEROEN2, ROUT2,
ENSYNC2, OSC2TAEN,
OSC2TIEN, OSC2EN
Enables all Oscillator 2 param-
eters
Oscillator 2 Interrupts IRQVEC1, IRQEN1 OS2TAS, OS2TIS, OS2TAE,
OS2TIE Interrupt enable/status
Si3220/Si3225
56 Preliminary Rev. 0.91
Figure 36. Tone Generator Timing Diagram
Figure 37. On-Hook Caller ID Transmission Sequence
...
...
0,1 ... 0,1 ......, OSC1TA ..., OSC1TA..., OSC1TI0,1 ... 0,1 ...
OSC1EN
ENSYNC1
Tone
Gen. 1
Signal
Output
First
Ring Burst Channel
Seizure Mark Data
Packet Second
Ring Burst
Message
Type Message
Length Parameter 1 Checksum
Parameter
Type Data
Length Data
Content
Parameter n
Parameter 2
Message Header Message Body
Si3220/Si3225
Preliminary Rev. 0.91 57
Tone Generator Interrupts
Both the active and inactive timers can generate an
interrupt to signal “on/off” transitions to the software.
The timer interrupts for tone generator 1 can be
individually enabled by setting the O S1TAE and OS1TIE
bits. Timer interrupts for tone generator 2 are OS2TAE
and OS2TIE. A pending interrupt for each of the timers
is determined by reading the OS1TAS, OS1TIS,
OS2TAS, and OS2TIS bits in the IRQVEC1 register.
Caller ID Generation
The Dual ProSLIC devices generate caller ID signals in
compliance with various Bellcore and ITU specifications
as described in Table 32 by providing continuous phase
binary frequency shift key (FSK) modulation.
Oscillator 1 is required because it preserves phase
continuity during frequency shifts whereas Oscillator 2
does not. Figure 37 illustrates a typical caller ID
transmission sequence in accordance with Bellcore
requirements.
The register and RAM locations for caller ID generation
are listed in Table 33. Caller ID data is entered into the
8-bit FSKDAT registe r. The data byte is d ouble buffered
so that the Dual ProSLIC can generate an interrupt
indicating the next data byte can be written when
processing begins on the current data byte. The caller
ID data can be transmitted in one of two modes
controlled by the O1FSK8 register bit. When
O1FSK8 = 0 (default case), the 8-bit caller ID data is
transmitted with a start bit and stop bit to create a 10-bit
data sequence. If O1FSK8 = 1, the caller ID data is
transmitted as a raw 8-bit sequen ce with no st ar t or sto p
bits. The value programmed into the OSC1TA register
determines th e bit rate, and the interrupt rate is equal to
the bit rate divided by the data sequence len gth (8 or 10
bits).
Pulse Metering Generation
The Si3220 offers an additional tone generator to
generate tones above the audio frequency band. This
oscillator generates billing tones which are typically
12 kHz or 16 kHz. The generator follows the same
algorithm as described in "Tone Generator Architecture"
on page 53 with the exception that the sample rate for
computation is 64 kHz instead of 8 kHz. The equation is
as follows: Coeff = cos (2 πf / 64000 Hz)
PMFREQ = coeff x (214 – 1)
Table 32. FSK Modulation Requirements
Parameter ITU-T V.23 Bellcore GR-
30-CORE
Mark Frequency (logic 1) 1300 Hz 1200 Hz
Space Frequency (logic 0) 2100 Hz 2200 Hz
Transmission Rate 1200 baud
Table 33. Register and RAM Locations used for Caller ID Generation
Parameter Register/RAM
Mnemonic Register/RAM Bits Description/Range
FSK Start & Stop Bit Enable OMODE O1FSK8 Enable/disable
Oscillator 1 Active Timer O1TALO/O1TAHI OSC1TA[15:0] 0 to 8.19 s/125 µs
FSK Data Byte FSKDAT FSKDAT[7:0] Caller ID data
FSK Frequency for Space FSKFREQ0 FSKFREQ0[15:3] Audio range
FSK Frequency for Mark FSKFREQ1 FSKFREQ1[15:3] Audio ra nge
FSK Amplitude for Space FSKAMP0 FSKAMP0[15:3]
FSK Amplitude for Mark FSKAMP1 FSKAMP1[15:3]
FSK 0-1 Transition Freq, High FSK01HI FSK01HI[15:3]
FSK 0-1 Transition Freq, Low FSK01LO FSK01LO[15:3]
FSK 1-0 Transition Freq, High FSK10HI FSK10HI[15:3]
FSK 1-0 Transition Freq, Low FSK10LO FSK10LO[15:3]
Si3220/Si3225
58 Preliminary Rev. 0.91
where Full Scale VPK = 0.5 V.
The pulse metering oscillator has a volume envelope
(linear ramp) on the on/off transitions of the oscillator.
The ramp is controlled by the value in the PMRAMP
RAM address, and the sinusoidal generator output is
multiplied by this volume before it is sent to the Pulse
Metering DAC. The volume value is incremented by the
value in PMRAMP at an 8 kHz rate. The volume will
ramp from 0 to 7FFF in increments of PMRAMP to allow
the value of PMRAMP to set the slope of the ramp. The
clip detector stops the ramp once the signal seen at the
transmit path exceeds the amplitude threshold set by
PMAMPTH, which provides an automatic gain control
(AGC) function to pre vent the audio signal from clippin g.
When the pulse metering signal is turned off, the
volume ramps down to 0 by decrementing according to
the value of PMRAMP. Figure 38 illustrates the
functional blocks involved in pulse metering generation,
and Table 34 presents the register and RAM locations
required that must be set to generate pulse metering
signals.
PMAMPL 1
4
---1 coeff–
1coeff+
------------------------215 1–()×DesiredVPK
FullScaleVPK
--------------------------------------
×=
Table 34. Register and RAM Locations Used for Pulse Metering Generation
Parameter Register/RAM
Mnemonic Register/RAM
Bits Description/Range
(LSB Size)
Pulse Metering Frequency
Coefficient PMFREQ PMFREQ[15:3] Sets oscillator frequency
Pulse Metering Amplitude
Coefficient PMAMPL PMAMPL[15:0] Sets oscillator amplitude
Pulse Metering Att ack/Decay
Ramp Rate PMRAMP PMRAMP[15:0] 0 to PMAMPL
(full amplitude)
Pulse Metering Active Timer PMTALO/PMTAHI PULSETA[15:0] 0 to 8.19 s (125 µs)
Pulse Metering Inactive T imer PMTILO/PMTIHI PULSETI[15:0] 0 to 8.19 s (125 µs)
Pulse Metering, Control
Interrupt IRQVEC1, IRQEN1 PULSTAE,
PULSTIE,
PULSTAS,
PULSTIS
Interrupt Status and control
registers
Pulse Metering AGC
Amplitude Threshold PMAMPTH PMAMPTH[15:0] 0 to 500 mV
PM Waveform Present PMCON ENSYNC Indicates signal present
PM Active Timer Enable PMCON TAEN Enable/disable
PM Inactive Timer Enab le PMCON TIEN Enable/disable
Pulse Metering Enable PMCON PULSE1 Enable/disable
Si3220/Si3225
Preliminary Rev. 0.91 59
Figure 38. Pulse Metering Generation Block Diagram
DTMF Detection
On-chip DTMF detection, also known as Touch Tone, is
available in the Si3220 and Si3225.
It is an in-band signaling system that repla ces the pulse-
dial signaling standard. In DTMF, two tones generate a
DTMF digit. One tone is chosen from the four possible
row tones and one tone is chosen from the four possible
column tones. The sum of these tones constitute one of
16 possible DTMF digits. The row and column tones
and corresponding digits are shown in Table 35.
DTMF detection is performed using a modified Goertzel
algorithm to compute the DFT for each of the eight
DTMF frequencies and their second harmonics. At the
end of the DFT comput ation, the squar ed magnitu des of
the DFT results for the 8 DTMF fundamental tones are
computed. The row results are sorted to determine the
strongest row frequency, and the column frequencies
are sorted as well. At the completion of this process,
checks are made to determine if the strongest row and
column tones constitute a DTMF digit.
The detection process occurs twice within the 45 ms
minimum tone time. A digit must be detected on two
consecutive tests after a pause to be recognized as a
new digit. If all tests pass, an interrupt is generated and
the DTMF digit value is loaded into the DTMF register
according to the following table. If tones occur at the
maximum rate of 100 ms per digit, the interrupt must be
serviced within 85 ms so that the current digit is not
overwritten by a new one. There is no buffering of the
digit information.
Table 36 outlines the hex code corresponding to the
detected DTMF digits.
Decimation
Filter
ADC
DAC
Pulse
Metering
DAC
Pulse
Metering
Oscillator Volume
PMRAMP
Peak Detector PMAMPTH
ZA
IBUF
8 kHz 7FFF
or 0
Clip
Logic
– +
12/16 kHz
Bandpass
+
+
+
x+
±
Table 35. DTMF Row/Column Tones
697 Hz 123A
770 Hz 456B
852 Hz 789C
941 Hz *0#D
1209 Hz 1336 Hz 1477 Hz 1633 Hz
Si3220/Si3225
60 Preliminary Rev. 0.91
Modem Tone Detection
The Dual ProSLIC devices are capable of detecting a
2100 Hz modem tone as described in ITU-T
Recommendation V.8. The detection scheme can be
implemented in both transmit and receive paths, and is
enabled by programming the appropriate register bit.
The detection scheme should be disabled for power
conservation after the modem tone wind ow has passed.
Once a valid modem tone is detected, a register bit will
be set accordingly and the user can check the results by
reading the register value. A programmable debounce
interval is provided to eliminate false detection and can
be programmed in increments of 67 ms by writing to the
appropri at e re gister.
Audio Path Processing
Unlike traditional SLICs, the Dual ProSLIC devices
integrate the codec function into the same IC. The on-
chip 16-bit codec offers programmable gain/attenuation
blocks and multiple loopback modes for self testing. The
signal path b lock diagram is shown in Figure 11 on page
22.
Transmit Path
In the transmit path, the analog signal fed by the
external ac coupling capacitors is passed through an
anti-aliasing filter before being processed by the A/D
converter. An analog mute function is provided directly
prior to the A/D converter input. The output of the A/D
converter is an 8 kHz, 16-bit wide, linear PCM data
stream. The standard requirements for transmit path
attenuation for signals above 3.4 kHz are part of the
combined decimation filter characteristic of the A/D
converter. One more digital filter is available in the
transmit path, THPF. THPF implements the high-pass
attenuation requirements for signals below 65 Hz. An
equalizer block then equalizes the transmit signal path
to compensate for series protection resistance (RPROT)
outside of the ac-sensing inputs. The linear PCM data
stream output from the equalizer block is amplified by
the transmit-path programmable gain amplifier, TPGA,
which can be programmed from –∞ to 6 dB. The DTMF
decoder receives the linear PCM data stream and
performs the digit extraction if enabled by the user. The
final step in the transmit path signal processing is the
A-law or µ-law compression which can reduce the data
stream word width to 8 bits. Depending on the PCM
Mode Select register selection, every 8-bit compressed
serial data word occupies one time slot on the PCM
highway, or every 16-bit uncompressed serial data
word occupies two time slots on the PCM highway.
Receive Path
In the receive path, the option ally compressed 8-bit dat a
is first expanded to 16-bit words. The PCMF register bit
can bypass the expansion process, so that two 8-bit
words are assembled into one 16-bit word. RPGA is the
receive path programmable gain amplifier which can be
programmed from –∞dB to 6 dB. An 8 kHz, 16-bit
signal is then provided to a D/A converter. An analog
mute function is provided directly after the D/A
converter. When not muted, the resulting analog signal
is applied at the input of the transconductance amplifier,
Gm, which drives the off-chip current buffer, IBUF.
TPGA/RPGA Gain/Attenuation Blocks
The TPGA and RPGA blocks are essentially linear
multipliers with the structure illustrated in Figure 39.
Both blocks can be independently programmed from –∞
to +6 dB (0 to 2 linear scale). The TXGAIN and RXGAIN
RAM locations are used to program each block. A
setting of 0000h will mute all audio signals; a setting of
4000h will pass the audio signal with no gain or
attenuation (0 dB), and a setting of 7FFFh will provide
the maximum 6 dB of gain to the incoming audio signal.
The DTXMUTE and DRXMUTE bits in the DIGCON
register are also available in order to allow muting of the
transmit and receive paths without requiring
modifications to the TXGAIN or RXGAIN settings.
Table 36. DTMF Hex Codes
Digit Hex code
10x1
20x2
30x3
40x4
50x5
60x6
70x7
80x8
90x9
00xA
*0xB
#0xC
A0xD
B0xE
C0xF
D0x0
Si3220/Si3225
Preliminary Rev. 0.91 61
Figure 39. TPGA and RPGA structure
Audio Characteristics
The dominant source of distortion and noise in both the
transmit and receive paths is the quantization noise
introduced by the µ-law or the A-law compression
process. Figure 5 on page 18 specifies the minimum
Signal-to-Noise-and- Distortion Ratio for either path for a
sine wave input of 200 Hz to 3400 Hz.
Both the µ-law and the A- law speech encoding allow th e
audio codec to transfer and process audio signals lar ger
than 0 dBm0 without clipping. The maximum PCM code
is generated for a µ-law encoded sine wave of
3.17 dBm0 or an A-law encoded sine wave of
3.14 dBm0. The device overload clipping limits are
driven by the PCM encodin g process. F igure 6 on page
19 shows the acceptable limits for the analog-to-analog
fundamental power transfer-function, which bounds the
behavior of the device.
The transmit path gain distortion versus frequency is
shown in Figure 7 on page 19. The same figure also
presents the minimum required attenuation for out-of-
band analog signals applied on the line. The presence
of a high-pass filter transfer-function ensures at least
30 dB of attenuation for signals below 65 Hz. The low-
pass filter transfer function attenuates signals above
3.4 kHz. It is implemented as part of the A-to-D
converter.
The receive path transfer function requirement, shown
in Figure 8 on page 20, is very similar to the transmit
path transfer function. The PCM data rate is 8 kHz so no
frequencies greater than 4 kHz are digitally encoded in
the data stream. At frequencies greater than 4 kHz, the
plot in Figure 8 is interpreted as the maximum allowable
magnitude of spurious signals that are generated when
a PCM data stream representing a sine wave signal in
the range of 300 Hz to 3.4 kHz at a level of 0 dBm0 is
applied at the digital input.
The group delay distortion in either path is limited to no
more than the levels indicated in Figure 9. The
reference in Figure 9 is the smallest group delay for a
sine wave in the range of 500 Hz to 2500 Hz at 0 dBm0.
The block diagram for the voice-band signal processing
paths are shown in Figure 11 on page 22. Both the
receive and the transmit paths employ the optimal
combination of analog and digital signal processing for
maximum performance while maintaining sufficient
flexibility for users to optimize their particular application
of the device. The two-wire (TIP/RING) voice-band
interface to the device is implemented with a small
number of external components. The receive path
interface consists of a unity-gain current buffer, IBUF,
while the transmit path interface is an ac coupling
capacitor. Signal paths, although implemented
differentially, are shown as single-e nded for simplicity.
System Clock Generation
The Dual ProSLIC devices generate the internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 786 kHz,
1.024 MHz, 1.536 MHz, 1.544 MHz, 2.048 MHz,
4.096 MHz or 8.192 MHz. The ratio of the PCLK rate to
the FSYNC rate is determined by a counter clocked by
PCLK. The three-bit ratio information is transferred into
an internal register, PLL_MULT, after a device reset.
The PLL_MULT controls the internal PLL which
multiplies PCLK to generate the rate required to run the
internal filters and other circuitry.
The PLL clock synthesizer settles quickly after powerup
or update of the PLL_MULT register. However, the
settling time depends on the PCLK frequency and it is
approximately predicted by the following equation:
Tsettle = 64/FPCLK
Figure 40. PLL Frequency Synthesizer
TPGA or RPGA
PCM
In PCM
Out
X
M
where M = {0, 1/16384, 2/16384,...32767/16384}
PFD
DIV M
PLL_MULT
VCO ÷2 ÷2
RESET
28.672 MHz
PCLK
Si3220/Si3225
62 Preliminary Rev. 0.91
Interrupt Logic
The Dual ProSLIC devices are capable of generating
interrupts for the following events:
!Loop current/ring gr ound detected.
!Ring trip detected.
!Ground Key detected.
!Power alarm.
!DTMF digit detected.
!Active timer 1 expired.
!Inactive timer 1 expired.
!Active timer 2 expired.
!Inactive timer 2 expired.
!Ringing active timer expired.
!Ringing inactive timer expired.
!Pulse metering active timer expired.
!Pulse metering inactive timer expired.
!RAM address access complete.
!Receive path modem tone detected.
!Transmit path modem tone detected.
The interface to the interrupt logic consists of six
registers. Three interrupt status registers (IRQ0–IRQ3)
contain 1 bit for each of the above interrupt functions.
These bits are set when an interrupt is pending for the
associated resource. Three interrupt mask registers
(IRQEN1–IRQEN3) also contain 1 bit for each interrupt
function. For interrupt mask registers, the bits are active
high. Refer to the appropriate functional description text
for operational details of the interrupt functions.
When a resource reaches an interrupt condition, it
signals an interrupt to the interrupt control block. The
interrupt control block sets the associated bit in the
interrupt status register if the mask bit for that interrupt
is set. The INT pin is a NOR of the bits of the interrupt
status registers. Therefore, if a bit in the interrupt status
registers is asserted, IRQ asserts low. Upon receiving
the interrupt, the interrupt handler should read interrupt
status registers to determine which resource requests
service. All interrupt bits in the interrupt status registers
IRQ0–IRQ3 are cleared following a register read
operation. If the interrupt status registers are non-0, the
INT pin remains asserted.
SPI Control Interface
The control interface to the Dual ProSLIC devices is a
4-wire interface modeled after micro-controller and
serial peripheral devices. The interface consists of a
clock (SCLK), chip select (CS), serial data input (SDI),
and serial data output (SDO). In addition, the Dual
ProSLIC devices include a serial data through output
(SDI_THRU) to support a daisy-chain operation of up to
eight devices (up to sixteen channels). The device
operates with both 8-bi t and 1 6-bit SPI con trolle rs. Ea ch
SPI operation consists of a control byte, an address
byte (of which only the seven LSBs are used internally),
and either one or two dat a bytes de pending on the wid th
of the controller and whether the access is to an 8-bit
register or 16-bit RAM address. Bytes are always
transmitted MSB first.
There are variations of usage on this four-wire interface
as follows:
!Continuous clocking. During continuous clocking,
the data transfe rs are controlled by the assertion of
the CS pin. CS must be asserted before the falling
edge of SCLK on which the first bit of data is
expected during a read cycle, and must remain low
for the duration of the 8-bit transfer (command/
address or data), going high after the last rising of
SCLK after the transfer.
!Clock during transfer only. In this mode, only the
clock is cycling during the actual byte transfers. Each
byte transfer will consist of eight clock cycles in a
return to “1” for m at.
!SDI/SDO wired operation. Independent of the
clocking options described, SDI and SDO can be
treated as two separate lines or wired together if the
master is cap able of tri-stating its output during the
data byte transfer of a read operation.
!Soft reset. The SPI state machin e resets whe never
CS asserts during an oper at ion on an SCLK cycle
that is not a multiple of eight. This is a mechanism
for the controller to force the state machine to a
known state when the controller and the device are
out of synchronization.
Si3220/Si3225
Preliminary Rev. 0.91 63
The control byte has the following structu re and is presented on the SDI pin MSB first.
The bits are defined as follows:
76543210
BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3]
Table 37. SPI Control Interface
7 BRDCST Indicates a broadcast operation that is intended for all devices in the daisy chain. This is
only valid for write operations, since it would cause contention on the SDO pin during a
read.
6R/W
Read/Write Bit.
0 = W rite operation.
1 = Read operation.
5 REG/RAM Register/RAM Access Bit.
0 = RAM access.
1 = Register access.
4 Reserved
3:0 CID[3:0] Indicates the channel that is tar geted by the opera tion. The 4-bit channel value is provided
LSB first. The devices reside on the daisy chain such that device 0 is nearest to the con-
troller and device 15 is furthest down the SDI/SDU_THRU chain. (See Figure 41.)
As the CID information propagates down the daisy chain, each channel decrements the
CID by 1. The SDI node s between devices reflects a decrement of 2 per device since each
device contains two channels. Th e de vice re ceiv ing a value of 0 in the CID field responds
to the SPI transaction. (See Figure 42.) If a broadcast to all devices con nected to the chain
is requested, the CID does not decrem ent. In this case, the same 8-bit or 16-bit d ata is pre-
sented to all channels regardless of the CID values.
Si3220/Si3225
64 Preliminary Rev. 0.91
Figure 41. SPI Daisy-Chain Mode
CPU Channel 0
Channel 1
SDO
SDI
SDI
SDITHRU
Dual P roS LIC #8
Dual P roS LIC #2
Dual P roS LIC #1
CS CS
SDO
Channel 2
Channel 3
SDI
SDITHRU
CS
SDO
Channel 14
Channel 15
SDI
SDITHRU
SDO
CS
SDI0
SDI1
SDI2
SDI3
SDI4
SDI15
SDI14
Si3220/Si3225
Preliminary Rev. 0.91 65
In Figure 42 the CID field is 0. As this field is decremented (in LSB to MSB order) the value decrements for each
SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control word passes through
the entire chain. The odd SDIs are internal to the device and represent the SDI to SDI_THRU connection between
channels of the same device . A unique CID is prese nted to each ch annel, and the channe l receiving a CID valu e of
zero is the target of the operation (channel 0 in this case). The last line of Figure 42 illustrates that in Broadcast
mode, all bits pass through the chain without permutation.
Figure 42. Sample SPI Control Word to Address Channel 0
SPI Control Word
BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3]
0 A B C 0 0 0 0
0 A B C 1 1 1 1
0 A B C 0 1 1 1
0 A B C 1 0 1 1
0 A B C 0 1 0 0
0 A B C 1 0 0 0
1 A B C D E F G
SDI0
SDI1 (Internal)
SDI2
SDI3 (Internal)
SDI 14
SDI15 (Internal)
SDI0-15
Si3220/Si3225
66 Preliminary Rev. 0.91
Figures 43 and 44 illustrate WRITE and READ operations to register addresses via an 8-bit SPI controller. These
operations are performed as a 3-byte transfer. CS is asserted between each byte which is required for CS to be
asserted before the first fa lling edge of SCLK af ter th e DATA byte to indicate to the sta te machine tha t one byte only
should be transferred. The state of SDI is a “don’t care” during the DATA byte of a read operation.
Figure 43. Register Write Operation via an 8-Bit SPI Port
Figure 44. Register Read Operation via an 8-Bit SPI Port
Figure 45. Register Write Operation via a 16-Bit SPI Port
Figure 46. Register Read Operation via a 16-Bit SPI Port
CONTROL ADDRESS DATA [7:0]
SCLK
SDI
SDO Hi-Z
CS
CONTROL ADDRESS
X X X X X X X X
CS
SCLK
SDI
SDO Data [7:0]
X X X X X X X X
CS
SCLK
SDI
SDO
CONTROL ADDRESS Data [7:0]
Hi - Z
X X X X X X X X
CS
SCLK
SDI
SDO Data [7:0]
CONTROL ADDRESS X X X X X X X X
Data [7:0]
Same byte repeated twice.
Si3220/Si3225
Preliminary Rev. 0.91 67
Figures 45 and 46 illustrate WRITE and READ
operations to register addresses via a 16-bit SPI
controller. These operations require a 4-byte transfer
arranged as two 16-bit wor ds. T he absence o f CS goin g
high afte r the eighth bit of dat a indicates to the SPI st ate
machine that eight more SCLK pulses follow to
complete the operation. F or a WRITE ope ration, the last
eight bits are ignored. For a read operation, the 8-bit
data value repeats so that the data is captured during
the last half of a data transfer if required by the
controller.
During register accesses, the CONTROL, ADDRESS,
and DATA are captured in the SPI module. At the
completion of the ADDRESS byte of a READ access,
the contents of the addressed register move into the
data register of th e SPI data register. At the completion
of the DATA byte of a WRITE access, the data is
transferred from the SPI to the addressed register.
Figures 47–50 illustrate the various cycles for accessing
RAM addresses. RAM addresses are 16-bit entities;
therefore, the accesses always require four bytes.
During RAM address accesses, the CONTROL,
ADDRESS, and DATA are captured in the SPI module.
At the completion of the ADDRESS byte of a READ
access, the contents of the channel-based data buffer
move into the data register in the SPI for shifting out
during the DATA portion of the SPI transfer. This is the
data loaded into the data buffer in response to the
previous RAM add ress r ead re qu est. Th erefor e, th ere is
a one-deep pipeline nature to RAM address READ
operations. At the completion of the DATA portion of the
READ cycle, the ADDRESS is transferred to the
channel-based address buffer register and a RAM
address is logged for that channel. The RAMSTAT bit in
each channel is polled to monitor the status of RAM
address accesses that are serviced twice per sample
period at dedicated windows in the DSP algorithm.
A RAM access interrupt in each channel indicates that
the pending RAM access request is serviced. For a
RAM access, the ADDRESS and DATA is transferred
from the SPI registers to the addre ss and d at a buffers in
the appropriate channel. The RAM WRITE request will
be then logged. As for READ operations, the status of
the pending request is monitored by either polling the
RAMSTAT bit for the channel or enabling the RAM
access interrupt for the channel. By keeping the
address, data buffers, and RAMSTAT register on a per
channel basis, RAM address accesses can be
scheduled for both channels without interface.
Figure 47. RAM Write Operation via an 8-Bit SPI Port
Figure 48. RAM Read Operation via an 8-Bit SPI Port
SCLK
SDI
SDO
CONTROL ADDRESS DATA [15:8] DATA [7:0]
Hi-Z
CS
CS
SCLK
SDI
SDO
CONTROL ADDRESS
x x x x x x x x x x x x x x x x
DATA [15:8] DATA [7:0]
Si3220/Si3225
68 Preliminary Rev. 0.91
Figure 49. RAM Write Operation via a 16-Bit SPI Port
Figure 50. RAM Read Operation via a 16-Bit SPI Port
CS
SCLK
SDI
SDO
CONTROL ADDRESS Data [15:8]
Hi - Z
Data [7:0]
CS
SCLK
SDI
SDO
CONTROL ADDRESS
Data [15:8] Da ta [7:0 ]
Si3220/Si3225
Preliminary Rev. 0.91 69
PCM Interface
The Dual ProSLIC devices contain a flexible
programmable interface for the transmission and
reception of digital PCM samples. PCM data transfer is
controlled by the PCLK and FSYNC inputs, PCM Mode
Select, PCM Transmit Start Count (PCMTXHI/
PCMTXLO), and PCM Receive Start Count (PCMRXHI/
PCMRXLO) registers. The interface can be configured
to support from 4 to 128 8-bit timeslots in each frame.
This corresponds to PCLK frequencies of 256 kHz to
8.192 MHz in power of 2 increments. (768 kHz,
1.536 MHz and 1.544 MHz also are available.)
Timeslots for data transmission and reception are
independently configured with the PCMTXHI,
PCMTXLO, PCMRXHI, and PCMRXLO. Setting the
correct starting point of the data configures the part to
support long FSYNC and short FSYNC variants, IDL2 8-
bit, 10-bit, B1 and B2 channel time slots. DTX data is
high-impedance e xcept for the d uration of the 8- bit PCM
transmit. DTX returns to high-impedance on the
negative edge of PCLK during the LSB or on the
positive edge of PCLK following the LSB. This is based
on the setting of the PCMTRI bit of the PCM Mode
Select register. Tristating on the negative edge allows
the transmission of data by multiple sources in adjacent
timeslots without the risk of driver contention. In a ddition
to 8-bit data modes, there is a 16-bit mode provided for
testing. This mode can be activated via the PCMF bits
of the PCM Mode Select reg ister. Setting the PCMTXHI/
PCMTXLO or PCMRXHI/PCMRXLO register greater
than the number of PCLK cycles in a sample period
stops data transmission because PCMTXHI/PCMTXLO
or PCMRXHI/PCMRXLO do not equal the PCLK count.
Figures 51–53 illustrate the usage of the PCM highway
interface to adapt to common PCM standards.
Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
01 765432 16151413121110981817
MSB LSB
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
01 765432 16151413121110981817
MSB LSB
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
Si3220/Si3225
70 Preliminary Rev. 0.91
PCM Companding
The Dual ProSLIC devices support both µ-255 Law (µ-
Law) and A-Law companding formats in addition to
Linear Data mode. The data format is selected via the
PCMF bits of the PCM Mode Select register. µ-Law
mode is more commonly used in North America and
Japan, and A-Law is primarily used in Europe and other
countries. These 8-bit companding schemes follow a
segmented curve for matted as a sign b it (MSB) followe d
by three chord bits and four step bits. A-Law typically
uses a scheme of inverting all even bits while µ-Law
does not. Dual ProSLIC devices also support A-Law
with inversion of even bits, inversion of all bits, or no bit
inversion by programming the ALAW bits of the PCM
Mode Select register to the appropriate setting. Tables
38 and 39 define the µ-Law and A-Law encoding
formats.
The Dual ProSLIC devices also support a 16-bit linear
data format with no companding. This Linear mode is
typically used in systems that convert to another
companding format such as adaptive delta PCM
(ADPCM) or systems that perform all companding in an
external DSP. The data format is 2’s complement with
MSB first (sign bit). Transmitting and receiving data via
Linear mode requir es two continuous time slot s. An 8- bit
Linear mode enables 8-bit transmission without
companding.
Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10)
Figure 54. 16-Bit Linear Mode Example, Timeslots 1 and 2, Long FSYNC
01 765432 16151413121110981817
MSB LSB
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
01 765432 16151413121110981817
MSB LSB
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
Si3220/Si3225
Preliminary Rev. 0.91 71
Table 38. µ-Law Encode-Decode Characteristics*
Segment
Number #Intervals X Interval Size Value at Segment Endpoints Digital Code Decode Level
8 16 X 256 8159
.
.
.
4319
4063
10000000b
10001111b
8031
4191
7 16 X 128 .
.
.
2143
2015 10011111b 2079
6 16 X 64 .
.
.
1055
991 10101111b 1023
5 16 X 32 .
.
.
511
479 10111111b 495
4 16 X 16 .
.
.
239
223 11001111b 231
3 16 X 8 .
.
.
103
95 11011111b 99
2 16 X 4 .
.
.
35
31 11101111b 33
1 15 X 2
__________________
1 X 1
.
.
.
3
1
011111110b
11111111b 2
0
*Note: Characteristics are symmetrica l about analog zero with sign bit = 0 for negative analog values.
Si3220/Si3225
72 Preliminary Rev. 0.91
Table 39. A-Law Encode-Decode Characteristics1,2
Segment
Number #intervals X interval size Value at segment endpoints Digital Code Decode Level
7 16 X 128 4096
3968
.
.
2176
2048
10101010b
10100101b
4032
2112
6 16 X 64 .
.
.
1088
1024 10110101b 1056
5 16 X 32 .
.
.
544
512 10000101b 528
4 16 X 16 .
.
.
272
256 10010101b 264
3 16 X 8 .
.
.
136
128 11100101b 132
2 16 X 4 .
.
.
68
64 11110101b 66
1 32 X 2 .
.
.
2
0 11010101b 1
Notes:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values.
2. Digital code includes inversion of even numbered bits. Other available formats include inversion of odd bits, inversion of
all bits, or no bit inversion. See "PCM Companding" on page 70 for more details.
Si3220/Si3225
Preliminary Rev. 0.91 73
General Circuit Interface
The Dual ProSLIC devices also contain an alternate
communication interface to the SPI and PCM control
and data interface. The general circuit interface (GCI) is
used for the transmission and reception of both control
and dat a information o nto a GCI bus. The PCM and G CI
interfaces are both four-wire interfaces and share the
same pins. The SPI control interface is not used as a
communication interface in the GCI mode, but rather as
hard-wired channel selector pins. The selection
between PCM and GCI modes is performed out of reset
using the SDITHRU pin. Tables 40 and 41 illustrate how
to select the communication mod e and ho w the pins ar e
used in each mode.
If GCI mode is selected, the following pins must be tied
to the correct state to select one of eight sub-frame
timeslots in the GCI frame (described below). These
pins must remain in this state while the Dual ProSLIC is
operating. Selecting a particular subframe causes that
individual Dual ProSLIC device to transmit and receive
on the appropriate sub-frame in the GCI frame, which is
initiated by an FSYNC p ulse. No further register settings
are needed to select which sub-frame a device uses,
and the sub-frame for a particular device cannot be
changed while in operation.
In GCI mode, the PCLK input requires either a
2.048 MHz or a 4.096 MHz clock signal, and the
FSYNC input requires an 8 kHz frame sync signal. The
overall unit of data used to communicate on the GCI
highway is a frame 125 µs in length. Each frame is
initiated by a pulse on the FSYNC pin, whose rising
edge signifies the beginning of the next frame. In 2x
PCLK mode, the user sees twice as many PCLK cycles
during each 125 µs frame versus 1x PCLK mode. Each
frame consists of eight fixed timeslot sub-frames, which
are assigned by the Sub-Frame Select pins as
described above (SDI, SDO, and CS). Within each sub-
frame are four channels (bytes) of data, including two
voice data channels B1 and B2, one Monitor channel M
used for initialization and setup of the device, and one
Signaling and Control channel (SC) used for
communicating status of the device and for initiating
commands. Within the SC channel are six Command/
Table 40. PCM or GCI Mode Selection
SDITHRU SCLK Mode Selected
0 0 GCI Mode—1x PCLK (2.048 MHz)
0 1 GCI Mode—2x PCLK (4.096 MHz)
1 x PCM Mode
Note: Values shown are the states of the pins at the rising
edge of RESET.
Table 41. Pin Functionality in PCM or GCI Mode
Pin Name PCM Mode GCI Mode
CS SPI Chip Select Channel Selector,
bit 0
SCLK SPI Clock Input PCLK Rate
Selector
SDI SPI Serial Data Inpu t Channel Selector,
bit 2
SDO SPI Serial Data
Output Channel Selector,
bit 1
SDITHRU SPI Data Through-
put pin for Daisy
Chaining Operation
(Connects to the SDI
pin of the subse-
quent device in the
daisy chain)
PCM/GCI Mode
Selector
FSYNC PCM Frame Sync
Input GCI Frame Sync
Input
PCLK PCM Input Clock GCI Input Clock
DTX PCM Data Transmit GCI Data Transmit
DRX PCM Data Receive GCI Data Receive
Note: This table denotes pin functionality after the rising
edge of RESET and mode selection.
Table 42. GCI Mode Sub-Frame Selection
SDI SDO CS
GCI Subframe 0 Selected
(Voice channels 1–2) 11 1
GCI Subframe 1 Selected
(Voice channels 3–4) 11 0
GCI Subframe 2 Selected
(Voice channels 5–6) 10 1
GCI Subframe 3 Selected
(Voice channels 7–8) 10 0
GCI Subframe 4 Selected
(Voice channels 9–10) 01 1
GCI Subframe 5 Selected
(Voice channels 11–12) 01 0
GCI Subframe 6 Selected
(Voice channels 13–14) 00 1
GCI Subframe 7 Selected
(Voice channels 15–16) 00 0
Si3220/Si3225
74 Preliminary Rev. 0.91
Indicate (C/I) bits and two handshaking bits, MR and
MX. The C/I bits indicate status and command
communication, while the handshaking bits Monitor
Receive (MR) and Monitor Transmit (MX), exchange
data in the Monitor channel. Figure 55 illustrates the
contents of a GCI highway frame.
16-Bit GCI Mode
In addition to the standard 8-bit GCI mode, the Dual
ProSLIC devices also offer a 16-bit GCI mode for
passing 16-bit voice data to the upstream host
processor. This mode can be used for testing purposes
or for passing non-companded voice data to an
upstream DSP for further processing.
In 16-bit GCI mode, both of the 8-bit voice data
channels (B1 and B2, Figure 56) of each sub-frame are
required to pass the 16-bit voice data to the host. Each
125 µs frame can therefore accommodate up to eight
voice channels (the Dual ProSLIC can accommo date up
to sixteen voice channels in 8-bit GCI mode). Table 43
describes the GCI mode sub-frame selection for 16-bit
GCI mode.
Figure 55. Time-Multiplexed GCI Highway Frame Structure
Table 43. Sub-Frame Selection 16-Bit GCI Mode
SDI SDO
GCI Subframe 0 Selected
(Voice channels 0–1) 11
GCI Subframe 1 Selected
(Voice channels 2–3) 10
GCI Subframe 2 Selected
(Voice channels 4–5) 01
GCI Subframe 3 Selected
(Voice channels 6–7) 00
SF0 SF1 SF7SF6SF5SF4SF3SF2
SC
B1 B2 M
0123
11
Channel
Sub-Frame
888
FS
C/I MR MX
125 µs = 1 Frame
Si3220/Si3225
Preliminary Rev. 0.91 75
Figure 56. GCI Highway Frame Structure for 16-Bit GCI Mode
Monitor Channel
The Monitor channel is used for initialization and setup
of the Dual ProSLIC devices. It is also for general
communication with the Dual ProSLIC by allowing read
and write access to the Dual ProSLIC devices registers.
Use of the monitor channel requires manipulation of the
MR and MX handshaking bits, located in bits 1 and 0 of
the SC channel described. For purposes of this
specification, “downstream” is identified as th e data sent
by a host to the Dual ProSLIC. “Upstream” is identified
as the data sent by the Dual ProSLIC devices to a host.
The following diagram illustrates the Monitor channel
communication protocol. For successful communication
with the Dual ProSLIC, the transmitter should anticipate
the falling edge of the receiver’s acknowledgement.
This also maximizes communication speed. Because of
the handshaking protocol required for successful
communication, the data transfer rate using the Monitor
channel is less than 8 kbps.
Figure 57. Monitor Handshake Timing
Sub-Frame
16 8
FS
125 µs = 1 Frame
CH0 CH1 CH3CH2
61 1 16
MB1 C/I MR MX B2 Unused
16
Transmitter
Receiver
1s t B yte 2nd B yte 3rd Byte
MX
MX
MR
ACK
1s t B y te ACK
2nd Byte ACK
3rd Byte
125 µs
MR
Si3220/Si3225
76 Preliminary Rev. 0.91
The Idle state is achieved by the MX and MR bits being
held inactive for two or more frames. When a
transmission is initiated by a host device, an active state
is seen on the downstream MX bit. This sig nals the Dual
ProSLIC that a transmission has begun on the Monitor
channel and it should begin accepting data from it. The
Dual ProSLIC, after reading the data on the Monitor
channel, acknowledges the initial transmission by
placing the upstream MR bit in an active state. The da ta
is received and the upstream MR becomes active in the
frame immediately following the downstream MX
becoming active. The upstream MR then remains active
until either the next byte is received or an end of
message is detected (signaled by the downstream MX
being held inactive for two or mor e consecutive frames).
Upon receiving acknowledgement from the Dual
ProSLIC that the initial data was received (signaled by
the upstream MR bit transitioning from an inactive to an
active state), the host device places the downstream
MX bit in the inactive st ate for one fra me and th en either
transmit another byte by placing the downstream MX bit
in an active state again, or signal an end of message by
leaving the downstream MX bit inactive for a second
frame.
When the host is performing a write command, the host
only manipulates the downstream MX bit, and the Dual
ProSLIC only manipulates the upstream MR bit. If a
read command is performed, the host initially
manipulates the downstream MX bit to communicate
the command, but then manipulates the downstream
MR bit in response to the Dual ProSLIC respond ing with
the requested data. Similarly, the Dual ProSLIC initially
manipulates its upstream MR bit to receive the read
command, and will then manipulate its upstream MX bit
to respond with the requested data. If the host is
transmitting data, the Dual ProSLIC always transmits a
$FF value on its Monitor data byte. While the Dual
ProSLIC is transmitting data, the host should always
transmit a $FF value on its Monitor byte. If the Dual
ProSLIC is transmitting data and detects a value other
than a $FF on the downstream Monitor byte, the Dual
ProSLIC signals an Abort.
For read and write commands, an initial address must
be specified. The Dual ProSLIC responds to a read or a
write command at this address, and then subsequently
increment this address after every register access. In
this manner, multiple consecutive registers can be read
or written in one transmission sequence. By correctly
manipulating the MX and MR bits, a transmission
sequence can continue from the beginning specified
address until an invalid memory location is re ached. To
end a transmission sequence, the host processor must
signal an End-of-Message (EOM) by placing the
downstream MX and MR bits inactive for two
consecutive frames. The transmission can also be
stopped by the Dual ProSLIC by signaling an Abort.
This is signaled by placing the upstream MR bit inactive
for at least two consecutive cycles in response to the
downstream MX bit going active. An abort is sign aled by
the Dual ProSLIC for the following reasons:
!A read or write to an invalid memory address is
attempted.
!An invalid command sequence is received.
!A data byte was not received for at least two
consecutive frames.
!A collision occurs on the Monitor data bytes while
the Dual ProSLIC is transmitting data.
!Downstream monitor byte not $FF while upstrea m
monitor byte is transmitting.
!MR/MX protocol violation
Whenever the Dual ProSLIC aborts due to an invalid
command sequence, the state of the Dual ProSLIC
does not change. If a read or write to an invalid memory
address is attempted, all previous re ads or wr ites in th at
transmission sequence are valid up to the read or write
to the invalid memory address. If an end-of-message is
detected before a valid command sequence is
communicated, the Dual ProSLIC returns to the idle
state and re mains unchanged.
The data presented to the Dual ProSLIC in the
downstream Monitor bits must be present for two
consecutive frames to be considered valid data. The
Dual ProSLIC is designed to ensure it has received the
same data in two consecutive frames. If it does not, it
does not acknowledge receipt of the d ata byte a nd waits
until it does r ecei ve two cons e cutive identical dat a bytes
before acknowledging to the transmitter it has received
the data. If the transmitter attempts to signal
transmission of a subsequent data byte by placing the
downstream MX bit in an inactive state while the Dual
ProSLIC is still waiting to receive a valid data byte
transmission of two consecutive identical data bytes,
the Dual ProSLIC signals an abort and ends the
transmission. Figure 58 shows a state diagram for the
Receiver Monitor channel for the Dual ProSLIC.
Figure 59 shows a state diagram for the Transmitter
Monitor channel for the Dual ProSLIC.
Si3220/Si3225
Preliminary Rev. 0.91 77
Figure 58. Dual ProSLIC Monitor Receiver State Diagram
Idle
MR = 1
1st Byte
Received
MR = 0
Byte
Valid
MR = 0
New Byte
MR = 1
nth byte
received
MR = 1
Wait
for LL
MR = 0
Wait
for LL
MR = 0
Abort
MR = 1
MX
MX
MX
MX
MX
MX
MX
MX
MX * LL
MX * LL
MX * LL
MX * LL
MX * LL
Initial
State
Any
State
MX * LL
ABT
M R: M R bit calculat ed and t ransmit t ed on dat a upst ream (DT X ) line.
MX: MX bit received data downstream (DRX) line.
LL: Last look of monitor byte received on DRX line.
ABT: Abort indication to internal source.
MX
MX
Si3220/Si3225
78 Preliminary Rev. 0.91
Figure 59. Dual ProSLIC Monitor Transmitter State Diagram
Figures 60 and 61 are example timing diagrams of a
register read and a register write to the Dual ProSLIC
using the GCI. As noted in Figure 59, the transmitter
should always anticipate the acknowledgement of the
receiver for correct communication with the Dual
ProSLIC. Devices that do not accept this “best
case” timing scenario will not be able to
communicate with the Dual ProSLIC.
Initial
State
MR: MR bit received on DRX l ine.
MX: MX bit calculated and expected on DTX line.
MXR: MX bit sampled on DTX line.
CLS: Collision within the monitor data byte on DTX
line.
RQT: Request for transmission from internal source.
ABT: Abort request/indication.
Idle
MR = 1
1s t Byte
MX = 0
nth By te
ack
MX = 1
Wait f or
ack
MX = 0
EOM
MX = 1 MR
MR
CLS/ABT
Abort
MX = 1
Wait
MX = 1
MXR
MR * MXR
MR * MXR
MR * MXR
MR
MR * RQT
MR * RQT
MR * RQT
MR * RQT
MR * RQT
MR
Any State
Si3220/Si3225
Preliminary Rev. 0.91 79
M on itor Data Down stre a m
$FF $FF $91 $91 $81 $81 $10 $10 $FF $FF $FF $FF $FF $FF $FF $FF $FF
125 µs
1 F rame
M X Downstre a m Bi t
M R Downstre a m Bit
M on itor Data Upstre a m
$FF $FF $FF $FF $FF $FF $FF $FF $FF $91 $91 Contents of
Register $10 Contents of
Register $10 Contents of
Register $11 Contents of
Register $11 Contents of
Register $12
(ignored by
host)
$FF
MX Upstream Bit
MR Upstrea m Bit
<product> sends
address befor e
data
EOM
Acknowledge
EOM Signalled
= Acknowledgement of data reception
Figure 60. Example Read of Registers $10 and $11 in Channel 0 of the Dual ProSLIC
Si3220/Si3225
80 Preliminary Rev. 0.91
M on itor Data Down stre a m
$FF $FF $91 $91 $01 $01 $10 $10 Data to be
wr itten to $10 Data to be
written to $10 Da ta to b e
written to $11 Data to be
wr itten to $11 $FF $FF
125 µs
1 F rame
M X Downstre a m Bi t
M R Downstre a m Bit
M on itor Data Upstre a m
$FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF
MX Upstream Bit
MR Upstrea m Bit
EOM
Acknowledge
EOM Signalled
= Acknowledgement of data reception
Figure 61. Example Write to Registers $10 and $11 in Channel 0 of the Dual ProSLIC
Si3220/Si3225
Preliminary Rev. 0.91 81
Programming the Dual ProSLIC Using the
Monitor Channel
The Dual ProSLIC devices use the monitor channel to
Transfer Status or Operating mode information to and
from the host processor. Communication with the Dual
ProSLIC should be in the following format:
Byte 1: Device Address Byte
Byte 2: Command Byte
Byte 3: Register Address Byte
Bytes 4-n: Data Bytes
Bytes n+1, N+2: EOM
Device Address Byte
The Device Address Byte identifies which device
receives the particular message. This address must be
the first byte sent to the Dual ProSLIC at the beginning
of each transmission sequence. The Device Address
Byte has the following structure:
A = 1: Channel A receives the command
A = 0: Channel A does not receive the command
B = 1: Channel B receives the command
B = 0: Channel B does not receive the command
C = 1: Normal command follows
C = 0: Channel identification command
When C = 1, bits A and B are channel enable bits.
When these bits are set to 1, the corresponding
channels receives the command in the next command
byte. The channels with corresponding bits set to 0
ignore the subsequent command byte.
Channel Identification (CID) Command
The lowest programmable bit of the Device Address
Byte, C, enables a special Channel Identification
Command to identify themselves by software. The
structure of this command is as follows:
A = 1: Channel A is the destination
A = 0: Channel B is the destination
Immediately after the last bit of the CID command is
received, the Dual ProSLIC responds with a fixed two-
byte identification code as follows:
A = 1: Channel A is the source
A = 0: Channel B is the source
Upon sending the two-byte CID command, the Dual
ProSLIC sends an EOM signal (MR = MX = 1) for two
consecutive frames. When C = 0, B must be 0 or the
Dual ProSLIC signals an abort due to an invalid
command. In this mode, only bit C is pr ogrammable.
Command Byte
The Command Byte has the following structure:
RW = 1: A Read operation is performed from the Dual
ProSLIC
RW = 0: A Write operation is performed to the Dual
ProSLIC
CMD[6:0] = 0000001: Read or Write from the Dual
ProSLIC
CMD[6:0] = 0000010-1111111: Reserved
Register Address Byte
The Register Address Byte has the following structure:
This byte contains the actual 8-bit address of the
register to be read or written.
MSB LSB
7 6543210
100AB00C
MSB LSB
Bit 7 654321 0
Address Byte 1 0 0 A 0 0 0 0
Command Byte 0 0 0 0 0 0 0 0
MSB LSB
Bit 7 654321 0
Address Byte 1 0 0 A 0 0 0 0
Command Byte 1 0 1 1 1 1 1 0
MSB LSB
RW CMD[6:0]
MSB LSB
ADDRESS[7:0]
Si3220/Si3225
82 Preliminary Rev. 0.91
SC Channel
The downstream and upstream SC channels are
continuously carrying I/O information to and from the
Dual ProSLIC during every frame. The upstream
processor has immediate access to the receive
(downstream) and transmit (upstream) data present on
the Dual ProSLIC’s digital I/O port when used in GCI
mode. The SC channel consists of six C/I bits and two
handshaking bits as described in the tables below. The
functionality of the handshaking bits is defined in the
Monitor Channel section. This section defines the
functionality of the six C/I bits whether they are being
transmitted to the GCI bus via the DTX pin (upstream)
or received from the GCI bus via the DRX pin
(downstream). The structure of the SC channel is
shown in Fig u r e 62.
Figure 62. SC Channel Structure
Downstream (Receive) SC Channel Byte
The first six bits in the downstream SC channel control
both channels of the Dual ProSLIC where the C/I bits
are defined as follows:
Figure 63 illustrates the transmission protocol for the C/I
bits within the downstream SC channel. New data
received by either channel must be present and match
for two consecutive frames to be considered valid.
When a new command is communicated via the
downstream C/I bits, this data must be sent for at least
two consecutive frames to be recognized by the Dual
ProSLIC.
The current state of the C/I bits is stored in a primary
register P. If the received C/I bits are identical to the
current state, no action is taken. If the received C/I bits
differ from those in register P, the new set of C/I bits is
loaded into secondary register S and a latch is set.
When the next set of C/I bits is received during the
frame that immediately follows, the following rules
apply:
!If the receive d C/I bits a re identical to the content s of
register S, the stored C/I bit s are loaded in to register
P and a valid C/I bit transition is recognized. The
latch is reset and the Dual ProSLIC responds
accordingly to the command repr esented by the new
C/I bits.
!If the received C/I bit s differ from both the contents of
register S and the contents of register P, the newly
received C/I bits are loaded into register S and the
latch remains set. This cycle continues as long as
any new set of C/I bits differs from the contents of
registers S and P.
!If the newly received C/I bits are identical to the
contents of register P, the contents of register P
remain unchanged and the latch is reset.
MSB LSB
76543210
CI2A CI1A CI0A CI2B CI1B CI0B MR MX
CI2A, CI1A, CI0A Used to select operating mode for
channel A
CI2B, CI1B, CI0B Used to select operating mode for
channel B
MR, MX Monitor channel handshake bits
Table 44. Programming Operating Modes Using
Downstream SC Channel C/I Bits
Channel Specific C/I bits Dual ProSLIC Operating
Mode
CI2x CI1x CI0x
0 0 0 Open (high impedence,
no line monitoring)
0 0 1 Forward Active
0 1 0 Forward On-Hook Trans-
mission
0 1 1 Ground Start (Tip Open)
100Ringing
101Reverse Active
1 1 0 Reverse On-Hook Trans-
mission
1 1 1 Ground Start (Ring Open)
Note: x = A or B, corresponding to channel A or channel B.
Table 44. Programming Operating Modes Using
Downstream SC Channel C/I Bits (Continued)
Si3220/Si3225
Preliminary Rev. 0.91 83
Figure 63. Protocol for Receiving C/I Bits in the Dual ProSLIC
When the Dual ProSLIC is set to GCI mode at
initialization, the default set ting ignor es the downstr eam
SC channel byte and allows linefeed st ate co mmands to
be directed through the monitor channel. This default
configuration is enabled by initializing the GCILINE bit
of the PCMMODE register to 0, which pre vent s th e Dual
ProSLIC from transitioning between linefeed operating
states due to invalid data that may exist within the
downstream SC channel byte. To transfer direct linefeed
control to the downstream SC channel, the user must
set the GCILINE bit to 1. Once the GCILINE bit has
been set, the Dual ProSLIC follows the commands that
are contained in the downstream SC channel byte as
described in Figure 62.
The Dual ProSLIC architecture also enables automatic
transitions between linefeed operating states to reduce
the amount of interaction required between the host
processor and the Dual ProSLIC. When a GCI bus is
implemented, the user must ensure that these
automatic linefeed state transitions are consistent with
the linefeed commands contained within the
downstream SC channel byte.
In normal operation these automatic linefeed state
transitions are accompanied by the setting of a
threshold detection flag and an interrupt bit, if enabled.
To allow the Dual ProSLIC to automatically detect the
appropriate thresholds and control the linefeed
transitions, the downstream SC channel byte should be
updated accordingly once the interrupt bit is read from
the upstream SC ch annel byte. To disable the automatic
transitions, the user must set the GCILINE bit. Enabling
this Manual mode requires the host processor to read
the upstream SC channel information and provide the
appropriate downstream SC channel byte command to
program the correct linefeed state.
Table 45 presents the automatic linefeed state
transitions and their associated registers that cause the
transition.
The transition to the OPEN state stemming from power
alarm detection is intended to protect the Dual ProSLIC
circuit in the event that too much power is dissipated in
the Si3200 LFIC. This alarm is typically due to a fault in
the application circuit or on the subscriber loop, but can
be caused by intermittent power spikes depending on
the threshold to which th e alarm is set. The user can re-
initialize the linefeed operating state that was in effect
just prior to the power alarm by toggling th e downstream
SC channel byte to the OPEN state for two consecutive
cycles and then resetting the downstream SC channel
byte to the intended linefeed state for two consecutive
Receive New
C/I Code
Store in S
Receive New
C/I Code
= P?
= P?
= S? Load C/I Register
With New C/I Bits
Yes
No
Yes
Yes
No
No
P: C/I P rimary Register Contents
S: C/I Secondary Register Content s
Si3220/Si3225
84 Preliminary Rev. 0.91
cycles. If the Dual ProSLIC continues to automatically
transition to the OPEN state, the power alarm threshold
might be set incorrectly. If this problem persists after the
power alarm settings are verified, a system fault is
probable and the user should take measures to
diagnose the problem.
Upstream (Transmit) SC Channel Byte
The upstream SC channel byte looks similar to the
downstream SC channel byte, except that the
information quickly transfers the most time-critical
information from the Dual ProSLIC to the GCI bus. Each
upstream SC channel byte transfer from the Dual
ProSLIC lasts for at least two consecutive frames to
represent a valid transfer. The upstream C/I bits are
defined as follows:
The interrupt information for channels A and B is a
single bit that indicates that o ne or mor e interrupt s might
exist on the respective channel. Each of the individual
interrupt flags (see registers 18–20) can be individually
masked by writing the appropriate bit in registers 21–23
to ignore specific interrupts. When using the GCI mode,
the user should verify that each of the desired interrupt
bits are set so the upstream SC channel byte includes
the required interrupt functions.
Table 45. Automatic Linefeed State Transitions
Initiating Action Automatic Linefeed State
Transition Detection/Control Bits Interrupt Enable/Status
Bits
Loop closure detected On-hook active → off-hook active,
Off-hook active → on-hook active LCR (Register 9) LOOPE, LOOPS
(Register 16/19)
Ring trip detected Ringing → off-hook active RTP (Register 9) RTRIPE, RTRIPS
(Register 16/19)
Ringing burst
cadence Ringing → on-hook transmission
On-hook transmission → ringing T1EN, T2EN
(Register 23) RINGT1E, RINGT2E,
RINGT1S, RINGT2S
(Register 15/18)
Power alarm detected Any state → open PQ1DL (RAM 50) PQ1E, PQ1S
(Registers 17/20)
CI2A, CI1A, CI0A Monitors status data for channel A
CI2B, CI1B, CI0B Monitors status data for channel B
MR, MX Monitor channel handshake bits
(see Monitor Channel section)
Table 46. Monitored Data via Upstream SC Channel C/I Bits
C/I Bit Information Provided Context
CI2A Interrupt information on channel A CI2A = 0: No interrupt on channel A
CI2A = 1: Interrupt present on channel A
CI1A Hook status information on channel A CI1A = 0: Channel A is on-hook
CI1A = 1: Channel A is off-hook
CI0A Ground key information on channe l A CI0A = 0: No longitudinal current detected
CI0A = 1: Longitudinal current detected in ch A
CI2B Interrupt information on channel B CI2A = 0: No interrupt on channel B
CI2A = 1: Interrupt present on channel B
CI1B Hook status information on channel B CI1A = 0: Channel B is on-hook
CI1A = 1: Channel B is off-hook
CI0B Ground key information on channe l B CI0A = 0: No longitudinal current detected
CI0A = 1: Longitudinal current detected in ch B
Si3220/Si3225
Preliminary Rev. 0.91 85
System Testing
The Dual ProSLIC devices include a complete suite of
test tools to test the functionality of the line card and
detect fault conditions present on the TIP/RING pair.
Using one of the loopback test modes with the signal
generation and measurement tools eliminates the need
for per-line test relays and centralized test equipment.
Loopback Modes
Three loopback test options are available for the Dual
ProSLIC devices:
!The codec loopback path encompasses almost
entirely the electronics of both the transmit and
receive paths. The analog signal at the output of the
receive path is fed back to the input of the transmit
path through a feedback path on the analog side of
the audio codec. Both the impedance synthesis and
transhybrid bala nc e fu nctions are disabl ed in this
mode. (See DLM3 path in Figure 11 on page 22.)
The signal path starts with 8-bit PCM data input to
the receive pa th and ends with 8-bit PCM dat a at the
output of the transmit path. The user can bypass the
companding pr ocess and interface directly to the 16-
bit data.
!A second digital loopback takes the receive path
digital stream and routes it back to the transmit path
via the transhybrid feedback path. (See DLM2 path
through block H in Figure 11.) This mode
characterize s th e tra ns hy br id filte r re sp on se . The
transhybrid block also can be disabled (set to unity
gain) in this mode for diagnosing the digital gain
blocks and filter stages in both transmit and receive
paths. The signal path starts with 8-bit PCM data
input to the receive path and ends with 8-bit PCM
data at th e output of the transmit path. The user can
bypass the companding process and interface
directly to the 16-b it da ta.
!A third digit al loopback takes the digit al stream at the
output of the µ-Law/A-Law expander and feeds it
back to the input of the µ-Law/A-Law compressor.
(See DLM1 p ath in Figure 11.) This path verifies that
the host is connected correctly with the Dual
ProSLIC through the PCM interface and that the
PCLK and FSYNC signals are correctly set. This
mode also can test the µ-Law/A-Law companding
process. The signal path starts with 8-bit PCM data
input to the receive path and ends with 8-bit PCM
data at th e output of the transmit path. The user can
also connect directly to the 16-bit data to eliminate
the µ-Law/A-Law companding process when testing
the PCM interface.
Line Test and Diagnostics
The Dual ProSLIC devices provide a variety of signal
generation and measurement tools that facilitate fault
detection and parametric diagnostics on the TIP/RING
pair and line card functionality verification. The Dual
ProSLIC generates test signals, measures the
appropriate volt age/curre nt/signal levels, and processes
the results to provide a meaningful result to the user.
Interaction is required from the host microprocessor to
load the test parameters into the appropriate registers,
initiate the test(s), and read the results from the
registers. In some cases, the host processor might also
be required to perform some simple mathematics to
achieve the results. Software modules are available to
simplify integration of the diagnostics functions into the
system. The need for test relays and a separate test
head is eliminated in most applications. To address
legacy applications, all versions of the Dual proSLIC
include test-in and test-out relay drivers to switch in a
centralized test head.
The Dual ProSLIC’s line test and diagnostics
capabilities are categorized into three sections: signal
generation tools, measurement tools, and diagnostics
capabilities. Using these signal generation and
measurement tools, a variety of other diagnostics
functions can also be performed to meet the unique
requirements of specific applications. Table 47
summarizes the ranges and capabilities of the signal
generation and measurement tools.
Si3220/Si3225
86 Preliminary Rev. 0.91
Signal Generation Tools
!TIP/RING DC si gnal generation. The Dual Pro SLIC
line feed D/A converter can program a constant
current linefeed from 18–45 mA in 0.87 mA steps
with a ±10% total accuracy. In addition, the open-
circuit TIP/RING volt age ca n be prog rammed from 0
to 63 V in 1 V steps. The linefeed circuitry also can
generate a controlled polarity reversal.
!Tone generation. The Dual ProSLIC de vices can
generate single or dual tones over the entire audio
band, and can direct them into either the transmit or
the receive path depending on the diagnostic
requirements. Ringing signals from 4–100 Hz also
can be generated.
!Diagnostics mode ringing generation. The Dual
ProSLIC devices can generate an internal low-level
ringing signal to test for the presence of REN without
causing the terminal equipment to ring audibly. This
ringing signal can be either balance or unbalanced
depending on the state of the RINGUNB bit of the
RINGCON register. This feature is also available
with the Si3225 provided that a suff icient battery
voltage is present.
Table 47. Summary of Signal Generation and Measurement Tools
Function Range Accuracy/Resolution Comments
Signal Generation Tools
DC Current Generation 18 to 45 mA 0.875 mA
DC Voltage Generation 0 to 63.3 V 1.005 V
Audio Tone Generation 200 to 3400 Hz
Ringing Signal Generation 4 to 15 Hz
16 to 100 Hz ±5%
±1%
Measurement Tools
8-Bit DC/Low Frequency
Monitor A/D Converter High Range:
0 to 160.173 V
0 to 101.09 mA 628 mV
396.4 µA
800 Hz update rate
acrms, acPK, and dc
post-processing blocks
Low Range: 0 to 64.07 V
0 to 50.54 mA 251 mV
198.2 µA
Programmable Timer 0 to 8.19 s 125 µs
AC Low Pass Filter 3 to 400 Hz
16-Bit Audio A/D Converter 0 to 2.5 V 38 µV
Transmit Path Notch Filter 300 to 3400 Hz Single or dual notch,
≥90 dB attenuation
Transmit Path Bandpass Filter 300 to 3400 Hz
Si3220/Si3225
Preliminary Rev. 0.91 87
Figure 64. SLIC Diagnostic Filter Structure
Measurement Tools
!8-Bit monitor A/D converter. This 8-bit A/D
converter monitors all dc and low frequency voltage
and current data from TIP to ground and RING to
ground. Two additional values, TIP – RING and
TIP + RING, are calculated and stored in on-chip
registers to analyze met allic and longitudinal ef fect s.
The A/D operates at an 800 Hz update rate to allow
measurement bandwidth from dc to 400 Hz. A dual-
range capability allows high-voltage/high-current
measurement in the high range but also can
measure lower voltages and currents with a tighter
resolution.
!Programmable bandpass filter. A bandpass filter
discriminates cer tain frequency ranges such as
ringing frequencies and 50 Hz/60 Hz induction from
nearby or crossed powe r leads.
!SLIC diagnostics filter. Several post-processing
filter blocks monitor peak dc and ac characteristics of
the Monitor A/D converter outputs and values
derived from these outputs. Setting the SDIAG bit in
the DIAG register enables the filters. There are
separate filters for each channel, and their control is
independent. These filters require DSP processing
which is available only when voice band processing
is not being performed. If an off-hook or a ring trip
condition is detected while the SDIAG bit is set, the
bit is cleared and the diagnostic information is not
processed.
The following pa rameters can be selected as inputs
to the diagnostic block by setting the SDIAG bits in
the DIAG register to va lues 0–7 corresponding to the
order below:
" VTIP = voltage on the TIP lead
" VRI NG = voltage on the RING lead
" VLOOP = VTIP-VRING = metallic (loop) voltage
" VLONG = (VTIP+VRING)/2 = longitudinal voltage
" ILOOP = ITIP-IRING = metallic (loop) current
" ILOOP = ITIP-IRING = metallic (loop) current
" ILONG = (ITIP+IRING)/2 = longitudinal current
" VRING, EXT = ringing voltage when using an external
ringing source (Si3225 only)
" IRING,EXT = ringing current when using an external
ringing source (Si3225 only)
The SLIC diagnostic capability consists of a peak detect
block and two filter blocks, one for dc and one for ac.
The topology is illustrated in Figure 64.
The peak detect fi lte r block repor ts the magnitude of the
largest positive or negative value without sign. The dc
filter block consists of a single pole IIR low pass filter
with a coefficient held in the DIAGDCCO RAM location.
The filter output is read from the DIAGDC RAM lo cation.
The ac filter block consists of a full wave rectifier,
followed by a single pole IIR low pass filter with a
coefficient held in the DIAGACCO RAM location. The
peak value is read from the DIAGPK RAM location. The
peak value is cleared and the filters are flushed on the
0-1 transition of the SDIAG bit and when the input
source changes. The user can write 0 to the DIAGPK
RAM location to get peak information for a specific time
interval.
!16-bit audio A/D converter. The A/D converter
portion of the audio cod e c is mad e av aila ble for
processing test data received back through the
transmit audio path. The audio path offers a 2.5 V
peak voltage measure ment capability and a coarse
attenuation stage for scenarios where the incoming
signal amplitude must be attenua te d by as much as
3 dB to bring it into the allowab le input range without
clipping.
VTIP
VRING
VLOOP
VLONG
ILOOP
ILONG
VRING,EXT
IRING,EXT
LPF
PEAK
DETECT
FULL WAVE
RECTIFY LPF DIAGAC
DIAGDC
DIAGPK
DIAGACCO
DIAGDCCO
Si3220/Si3225
88 Preliminary Rev. 0.91
!Programmable timer. The Dual ProSLIC devices
incorporate several digital oscillator circuits to
program the on - and off-times of the ringing and
pulse metering signals. The tone generation
oscillator can be used to program a time period for
averaging specific measu red test parameters.
!Transmit audio path diagnostics filter. Transmit
path audio di agnostics are facilitated by
implementing a sixth-or der IIR filter followed by peak
detection and power estimation blocks. This filter
can be programmed to eliminate or amplify specific
signals for the purpose of measuring the peak
amplitude and power co ntent of individual
components in the audio spectrum. Figure 11 on
page 22 illustrates the location of the diagnostics
filter block.
The sixth order IIR filter ope rates at an 8 kHz sample
rate and is implemented as three second-order filter
stages in cascade. Each second-order filter offers
five fully programmable coefficients (a1, a2, b0, b1,
and b2) with 25-bit precision by providing several
user-accessible registers. Each filter stage is
implemented with the following format:
If any of the second-order filter stages are not
required, they can be pr ogrammed to H(z)=1 by
setting a1=0, a2=0, b0=1, b1=0, and b2=0. This
flexible filter block can be programmed any of the
following characteristics:
" Single notch. Used for measuring noise/distortion in
the presence of a single tone. 90 dB attenuation is
provided at the notched fre quency. Implemented by
placing two 0s on the unit circle at the notch frequency
and two poles inside the unit circle at the notch
frequency.
" Dual notch. Used for measuring noise/distortion in the
presence of dual tones.
" Single notch/single peak. Used for measuring
particular harmonic in the presence of a single tone.
" Dual notch/single peak. Used to measu r e particular
intermodulation product in the presence of dual tones.
Because each second-order filter stage is fully
programmable, there are many other possible filter
implementations.
The IIR filter output is measured for power and peak
post-processing. The peak measurement window
duration is programmable by entering a value into the
TESTWLN RAM address. The peak value (TESTPKO)
is updated at the end of each window period. Power
measurement is performed by using a single pole IIR
filter to average the output of the sixth-order IIR filter.
The power averaging filter time constant is absolute
value programmable, and the average power result is
read from the TESTAVO RAM location.
Diagnostics Capabilities
!Foreign voltages test. The Dual ProSLIC devices
can detect the presence of foreign voltages
according to GR-909 requirements of ac voltages >
10 V and dc voltages > 6 V from T-G or R-G. This
test is performed when it has been dete rmined that a
hazardous voltage is not present on the line.
!Resistive faults (leakage current) test. Resistive
fault conditions are measured from T-G, R-G, or T-R
for dc resist ance per GR-909 specifications. If the dc
resistance is < 150 kΩ, it is considered a resistive
fault. To perform this test, program the Dua l ProSLIC
chipset to generate a constant open-circuit voltage
and measure the re sulting cur rent. The resist ance is
then calculated.
!Receiver off-hook test. Use s a similar procedure
as described in the Resistive Faults test above, but
is measured across T-R only. In addition, two
measurements must be performed at different open-
circuit voltages to verify the resistive linearity. If the
calculated resistance has more than 15%
nonlinearity betwe en the two calculated points and
the voltage/current origin, it is determined to be a
resistive fault.
!Ringers (REN) test. Verifies the presence of REN at
the end of the TIP/RING pa ir per TA-909
specifications. It can be implemented by generating
a 20 Hz ringing signal between 7 Vrms and 17 V rms
and measuring the 20 Hz ac current using the 8-bit
monitor ADC. The resistance (REN) can then be
calculated using the software module. The
acceptable REN range is > 0.175 REN (< 40 kΩ) or
< 5 REN (> 1400 Ω). A returned value of < 1400 Ω is
determined to be a resistive fault from T-R, and a
returned value > 40 kΩ is determined to be a loop
with no handset attached.
!ac line impedance measurement. Determines the
ac loop impedence across T-R. It can be
implemented by sending o ut multiple discre te to nes,
one at a time, and measur ing the returned amplitud e
with the hybrid balance filte r disabled. By calcul ating
the voltage d ifference between the initial amplitude
and the received amplitude and dividin g the result by
the audio current, the line impedance can then be
calculated.
Hz() b0 b1z
1
–b2z
2
–
++()
1a1z
1–
–a2z 2–
–()
--------------------------------------------------------
=
Si3220/Si3225
Preliminary Rev. 0.91 89
!Line capacitance measurement. Implemented like
the ac line impedance measurement test above, but
the frequency band of interest is be tween 1 kHz and
3.4 kHz. Knowing the synthesized 2-wire impedance
of the Dual ProSLIC, the roll-of f effect can be used to
calculate the ac line capacitance .
!Ringing voltage verification. Verifies that the
desired ringing signal is correctly applied to the TIP/
RING pair and can be measured in the 8-bit monitor
ADC, which senses low frequency signals directly
across T-R.
!Idle channel noise measurement. Given any
transmission mode with no tone generated a nd the
hybrid balance filte r tur ned off, the voice band
energy can be measur ed through the normal audio
path and read through the approp riate register.
!Echo path gain measurement.
!Harmonic distortion measurement. Detects the
power conten t of a particular ha rm o nic . It can be
implemented by progra mming two of the IIR
diagnostics filter stages to provide a notch at the
fundamental frequency and a peak at the harmonic
of interest. Performing this procedure on all relevant
harmonics individually and summing the results
provide the total harmonic distortion.
!Intermodulation distortion measurement (two-
tone method). Measures the intermodulation
distortion product in the presence of two tones. It can
be implemented by programming the three IIR
diagnostics filter st ages to provide two notches at the
two tone frequencies and a peak at the freque ncy of
interest.
Si3220/Si3225
90 Preliminary Rev. 0.91
8-Bit Control Register Summary
Any register not listed here is reserved and must not be written. Shaded registers are read only. All registers are
assigned a default value during initialization and following a system reset. Only registers 0, 2, 3, and 14 are
available until a PL L lock is est abli shed o r during a clock failure. Refer to AN58 “Du al ProSLIC Prog rammer Guide”
for detailed register descriptions and recommended settings.
(Ordered alphabeti cally by mnemonic except in cases of high, medium and low bytes which are ordered high to low.)
Reg
Addr3Mnemonic Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W Def.
Hex
Audio
21 AUDGAIN Audio Gain Control ATXMUTE ARXMUTE In i t R/W 0x00
Calibration
11 CALR1 Calibration Register 1 CAL CALO FFR CALOFFT CALOFFRN CALOFFTN CALDIFG CALCMG Init R/W 0x3F
12 CALR2 Calibration Register 2 CALLKGR CALLKGT CALMADC CALDACO CALADCO CALCMBA L Init R/W 0x3F
Diagnostic Tools
13 DIAG Diagnostics Tool Enable IQ2HR IQ1HR TSTRING TXFILT SDIAG SDIAGIN[2:0] Diag R/W
Digital Control and Loopback
22 DIGCON Digital Control and
Loopback Enable CODECLB PCMLB HYBLB HYBDIS THPFDIS RHPFDIS DTXMUTE DRXMUTE Diag R/W 0x00
FSK Data Byte
68 FSKDAT FSK Data Byte FSKBYTE[7:0] Oper R/W 0x00
Chip ID
0ID Chip ID PARTNUM[2:0]4REV[3:0]4Init R 0x—
Loop Current Limit
10 ILI M Loop Current Limit ILIM[4:0] Init R/W 0x05
Interrupts
14 IRQ0 Interrupt St atus 0 CLKIRQ4,6 IRQ3B4,6 IRQ2B4,6 IRQ1B4,6 IRQ3A4,6 IRQ2A4,6 IRQ1A4,6 Oper R 0x00
15 IRQ1 Interrupt St a tus 1 PULSTAS PULSTIS RINGT AS RINGTIS OS2TAS OS2TIS OS1 TAS OS1TIS Oper R/W 0x00
16 IRQ2 Interrupt Sta tus 2 RXMDMS TXMDMS RAMIRS DTMFS VOCTRKS LONGS LOOP S RTRIPS Oper R/W 0x00
17 IRQ3 Interrupt S tatus 3 CMBALS PQ6S PQ5S PQ4S PQ3S PQ2S PQ1S Oper R/W 0x00
18 IRQEN1 Interrupt Enable 1 PULSTAE PULSTIE RINGTAE RINGTIE OS2 TAE OS2TIE OS1TAE OS1TIE Init R/W 0x00
19 IRQEN2 Interrupt Enable 2 RXMDME TXMDME RAMIRE DTMFE VOCTRKE LONGE LOOPE RTRIPE Init R/W 0x00
20 IRQEN3 Interrupt Enable 3 CMBALE PQ6E PQ5E PQ4E PQ3E PQ2E PQ1E Init R/W 0x00
Linefeed Control
9 LCRRTP Loop Closure/Ring Trip/
Ground Key
Detection
CMH4SPEED4VOCTST4LONGHI4RTP4LCR4Oper R 0x40
6LINEFEED Linefeed LFS[2:0]4LF[2:0] Oper R/W 0x00
Notes:
1. Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the
PLL is not locked (MSTRSTAT[PLOCK]).
2. Reserved bit values are indetermina te.
3. Register address is in decimal.
4. Read only.
5. Protected bits.
6. Per channel bit(s).
7. Si3220 only.
Si3220/Si3225
Preliminary Rev. 0.91 91
SPI
2 MSTREN Master Initialization
Enable PLLFLT FSFLT PCFLT Init R/W 0x00
3 MSTRSTAT Master Initialization
Status PLLFAULT FSFAULT PCFAULT SRCLR4PLOCK4FSDET4FSVAL4PCVAL4Init R/W 0x00
Oscillators
61 O1TAHI Oscillator 1 Active Timer—
High Byte OSC1TA[15:8] Init R/W 0x00
60 O1TALO Oscillator 1 Active Timer—
Low Byte OSC1TA[7:0] Init R/W 0x00
63 O1TIHI Oscillator 1 Inactive Timer—
High Byte OSC1TI[15:8] Init R/W 0x00
62 O1TILO Oscillator 1 Inactive Timer—
Low Byte OSC1TI[7:0] Init R/W 0x00
65 O2TAHI Oscillator 2 Active Timer—
High Byte OSC2TA[15:8] Init R/W 0x00
64 O2TALO Oscillator 2 Active Timer—
Low Byte OSC2TA[7:0] Init R/W 0x00
67 O2TIHI Oscillator 2 Inactive Timer—
High Byte OSC2TI[15:8] Init R/W 0x00
66 O2TILO Oscillator 2 Inactive Timer—
Low Byte OSC2TI[7:0] Init R/W 0x00
59 OCON Oscillator Control ENSYNC24OSC2TAEN OSC2TIEN OSC2EN ENSYNC14OSC1TAEN OSC1TIEN OSC1EN Oper R/W 0x00
58 OMODE Oscillator Mode Select FSKSSEN ZEROEN2 ROUT2[1:0] OSC1FSK ZEROEN1 ROUT1[1:0] Init R/W 0x00
PCM Control
53 PCMMODE PCM Mode Select GCILINE6PCLK2X6PCMTRI6PCMEN ALAW[1:0]6PCMF[1:0]6Init R/W 0x05
57 PCMRXHI PCM RX Clock Slot—
High Byte PCMRX[9:8] Init R/W 0x00
56 PCMRXL0 PCM RX Clock Slot—
Low Byte PCMRX[7:0] Init R/W 0x00
55 PCMTXHI PCM TX Clock Slot—
High Byte PCMTX[9:8] Init R/W 0x00
54 PCMTXLO PCM TX Clock Slot—
Low Byte PCMTX[7:0] Init R/W 0x00
Pulse Metering
28 PMCON Pulse Metering Contro l ENSYNC4,7 TAEN17TIEN17PULSE17Oper R/W 0x00
30 PMTAHI Pulse Meteri ng Oscillator
Active Timer—
High Byte
PULSETA[15:8]7Init R/W 0x00
29 PM TALO Pulse Metering Osc illator
Active Timer—
Low Byte
PULSETA[7:0]7Init R/W 0x00
32 PMTIHI Pul se Metering Os cillator
Inactive Timer—
High Byte
PULSETI[15:8]7Init R/W 0x00
Reg
Addr3Mnemonic Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W Def.
Hex
Notes:
1. Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the
PLL is not locked (MSTRSTAT[PLOCK]).
2. Reserved bit values are indetermina te.
3. Register address is in decimal.
4. Read only.
5. Protected bits.
6. Per channel bit(s).
7. Si3220 only.
Si3220/Si3225
92 Preliminary Rev. 0.91
31 PMTILO Pulse Me tering Oscillator
Inactive Timer—
Low Byte
PULSETI[7:0]7Init R/W 0x00
Polarity Reversal
7 POLREV Polarity Reversal Sett in gs POLREV4VOCZERO PREN RAMP Init R/W
RAM Access
103 RAMADDR RAM Address RAMADDR[7:0] Oper R/W 0x00
102 RAM DATHI RAM Data—
High Byte RAMDAT[15:8] Oper R/W 0x00
101 RAMDATLO RAM Data—
Low Byte RAMDAT[7:0] Oper R/W 0x00
4 RAMSTAT RAM Address Status RAMSTAT4Init R 0x00
Soft Reset
1 RESET Soft Reset RESETB RESETA Init R/W 0x00
Ringing
23 RINGCON Ringing Configuration ENSYNC4RDACEN4RINGUNB TAEN TIEN RINGEN4UNBPOLR TRAP Init R/W 0x00
25 RINGTAHI Ringing Oscillator
Active Timer—High Byte RINGTA[15:8] Init R/W 0x00
24 RINGTALO Ringing Oscillator
Active Timer—Low Byte RINGTA[7:0] Init R/W 0x00
27 RINGTIHI Ringing Oscilla tor
Inactive Timer—High Byte RINGTI[15:8] Init R/W 0x00
26 RINGTILO Ringing Oscillator
Inactive Ti mer— Lo w Byte RINGTI[7:0] Init R/W 0x00
Relay Configuration
5 RLYCON Relay Driver and
Battery Switching
Configuration
BSEL5RRAIL RDOE RRD/GPO TRD2 TRD1 Diag R/W 0x00
SLIC Bias Control
8 SBIAS SLIC Bias Control OBIAS[1:0]5ABIAS[1:0]5Init R/W 0xE0
Si3200 Thermometer
72 THERM Si3200 Ther mometer STAT4Oper R/W 0x45
Tone Detection
70 TONDET Modem Tone Detection FAILCNT[3:0] PASSCNT[3:0] Oper R/W 0x00
69 TONDTMF DTMF Detection VALID4VALTONE4DTMFDIGIT[3:0]4Oper R 0x00
71 TONDEN Tone Detection Enab l e DTMF RXMDM TXMDM Init R/W 0x00
Impedance Synthesis Coefficients
49 ZA1HI Impedance Synthesis
Coeff A1— High Byte COEFFA1[20:16]6Init R/W 0x00
48 ZA1MID Impedance Synthesis
Coeff A1—Middle Byte COEFFA1[15:8]6Init R/W 0x00
Reg
Addr3Mnemonic Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W Def.
Hex
Notes:
1. Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the
PLL is not locked (MSTRSTAT[PLOCK]).
2. Reserved bit values are indetermina te.
3. Register address is in decimal.
4. Read only.
5. Protected bits.
6. Per channel bit(s).
7. Si3220 only.
Si3220/Si3225
Preliminary Rev. 0.91 93
47 ZA1LO Impedance Synthesis
Coeff A1—Low Byte COEFFA1[7:0] Init R/W 0x00
52 ZA2HI Impedance Synthesis
Coeff A2— High Byte COEFFA2[20:16]6Init R/W 0x00
51 ZA2MID Impedance Synthesis
Coeff A2—Middle Byte COEFFA2[15:8]6Init R/W 0x00
50 ZA2LO Impedance Synthesis
Coeff A2—Low Byte COEFFA2[7:0]6Init R/W 0x00
37 ZB0HI Impedance Synthesis
Coeff B0— High Byte COEFFB0[23:16]6Init R/W 0x00
36 ZB0MID Impedance Synthesis
Coeff B0—Middle Byte COEFFB0[15:8]6Init R/W 0x00
35 ZB0LO Impedance Synthesis
Coeff B0—Low Byte COEFFB0[7:0]6Init R/W 0x00
40 ZB1HI Impedance Synthesis
Coeff B1— High Byte COEFFB1[23:16]6Init R/W 0x00
39 ZB1MID Impedance Synthesis
Coeff B1—Middle Byte COEFFB1[15:8]6Init R/W 0x00
38 ZB1LO Impedance Synthesis
Coeff B1— Low Byte COEFFB1[7:0]6Init R/W 0x00
43 ZB2HI Impedance Synthesis
Coeff B2— High Byte COEFFB2[23:16]6Init R/W 0x00
42 ZB2MID Impedance Synthesis
Coeff B2—Middle Byte COEFFB2[15:8]6Init R/W 0x00
41 ZB2LO Impedance Synthesis
Coeff B2— Low Byte COEFFB2[7:0]6Init R/W 0x00
46 ZB3HI Impedance Synthesis
Coeff B3— High Byte COEFFB3[23:16]6Init R/W 0x00
45 ZB3MID Impedance Synthesis
Coeff B3—Middle Byte COEFFB3[15:8]6Init R/W 0x00
44 ZB3LO Impedance Synthesis
Coeff B3—Low Byte COEFFB3[7:0]6Init R/W 0x00
33 ZRS Impedance Synthesis
Analog Real Coeff RS[3:0]6Init R/W 0x00
34 ZZ Impedance Synthesis
Analog Complex Coeff ZSDIS6ZSOHT6ZP[1:0]6ZZ[1:0]6Init R/W 0x00
Reg
Addr3Mnemonic Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W Def.
Hex
Notes:
1. Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the
PLL is not locked (MSTRSTAT[PLOCK]).
2. Reserved bit values are indetermina te.
3. Register address is in decimal.
4. Read only.
5. Protected bits.
6. Per channel bit(s).
7. Si3220 only.
Si3220/Si3225
94 Preliminary Rev. 0.91
16-Bit RAM Address Summary
All internal 16-bit RAM addresses can be assigned unique values for each SLIC channel and are accessed in a
similar manner as the 8-bit control registers except the data is twice as long. In addition, one more READ cycle is
required during READ operations to accommodate the one-deep pipeline architecture. See "SPI Control Interface"
on page 62 for more details. All internal RAM addresses are assigned a default value of 0 during initialization and
following a system reset. Unless otherwise noted, all RAM addresse s use a 2’ s comp lement, MSB first d ate format.
Refer to AN58 “Dual ProSLIC Programmer Guide” for detailed RAM location descriptions and recommended
settings.
Note: Any RAM address not listed is reserved and must not be written. (ordered alphabeti cally by mnemonic)
RAM
Addr Mnemonic Description Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9Bit
8Bit
7Bit
6Bit
5Bit
4Bit
3Bit
2Bit
1Bit
0Type Example
Hex Example
Dec Unit
Battery Selection and VOC Tracking
31 BATHTH High Battery
Switch Threshold BATHTH[14:7]2Init 0E54 18 V
34 BATLPF Battery Tracking
Filter Coeff BATLPF[15:3] Init 0A08 10 Hz
32 BATLTH Low Battery Switch
Threshold BATLTH[14:7]2Init 0D88 17 V
33 B SWLPF RING Voltage Filter Coeff BSWLPF[15:3] Init 0A08 10 Hz
Speedup
36 CMHITH Speedup Threshold—
High Byte CMHITH[15:0] Init 0001 1 V
35 CMLOTH Speedup Threshold—
Low Byte CMLOTH[15:0] Init 07F5 10 V
SLIC Diagnostics Filter
53 DIAGAC SLIC Diags AC
Detector Threshold DIAGAC[15:0] Diag V
54 DIAGACCO SLIC Diags AC Filter Coeff DIAGACCO[15:3] Diag 7FF8 127.3 Hz
51 DIAGDC SLIC Diags DC Output DIAGDC[15:0] Diag V
52 DIAGDCCO SL IC Diags DC Filter Coeff DIAGDCCO[15:3] Diag 0A08 10 Hz
55 DIAGPK SLIC Diags Peak
Detector DIAGPK[15:0] Diag V
DTMF Detection
11 8 DTCOL2HTH DTMF Column Second
Harmonic Threshold DTCOL2HTH[15:3] Init 1013
11 6 DTCOLRTH DTMF Column
Ratio Threshold DTCOLRTH[15:3] Init 0CC5
112 DTCOLTH DTMF Column
Peak Threshold DTCOLTH[15:3] Init 1999
113 DTFTWTH DTMF Forward
Twist Threshold DTFTWTH[15:3] Init 1013
120 DTHOTTH DTMF Hot Limit
Threshold DTHOTTH[15:0] Init 0A1C
119 DTMINPTH DTMF Minimum
Power Threshold DTMINPTH[15:0] Init 00E5
Notes:
1. Any register not listed is reserved and must not be written.
2. Only positive input values are valid for these RAM addresses.
3. Si3225 only.
4. Si3220 only.
5. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay
between when the relay opens and when the LFS register transitions out of the ringing state.
6. For the Si3220, the RINGA MP RAM ad dr ess l o cati on is use d to sto re the am p litu de of the intern al r in gin g si gn al . Fo r t he Si3225, this address location stores the desired time relay between the last
zero current crossing and the next opportunity to open the ringing relay.
7. RAM address in decimal.
Si3220/Si3225
Preliminary Rev. 0.91 95
108 DTROW0TH DTMF Row 0
Peak Threshold DTROW0TH[15:3] Init 2AE1
109 DTROW1TH DTMF Row 1
Peak Threshold DTROW1TH[15:3] Init 28FB
117 DTROW2HTH DTMF Row Second
Harmonic Threshold DTROW2HTH[15:3] Init 308C
110 DTROW2TH DTMF Row 2
Peak Threshold DTROW2TH[15:3] Init 25C2
111 DTROW3TH DTMF Row 3
Peak Threshold DTROW3TH[15:3] Init 249B
115 DTROWRTH DTMF Row Ratio
Threshold DTROWRTH[15:3] Init 0CC5
114 DTRTWTH DTMF Reverse
Twist Threshold DTRTWTH[15:3] Init 1013
Echo Cancellation
89 ECCO0 Echo Cancellation Coeff 0 ECCO0[15:3] Init 01B0 1728
82 ECCO1 Echo Cancellation Coeff 1 ECCO1[15:3] Init FF20 –896
83 ECCO2 Echo Cancellation Coeff 2 ECCO2[15:3] Init 1548 21792
84 ECCO3 Echo Cancellation Coeff 3 ECCO3[15:3] Init 1E38 30944
85 ECCO4 Echo Cancellation Coeff 4 ECCO4[15:3] Init 1238 18656
86 ECCO5 Echo Cancellation Coeff 5 ECCO5[15:3] Init 01B8 1760
87 ECCO6 Echo Cancellation Coeff 6 ECCO6[15:3] Init FD08 –3040
88 ECCO7 Echo Cancellation Coeff 7 ECCO7[15:3] Init FFA0 –384
92 ECIIRA1 Echo Cancel IIR
Filter Coeff A1 ECIIRA1[15:3] Init 0370 3520
93 ECIIRA2 Echo Cancel IIR
Filt Coeff A2 ECIIRA2[15:3] Init CB58 –53920
90 ECIIRB0 Echo Cancel IIR
Filt Coeff B0 ECIIRB0[15:3] Init 0068 416
91 ECIIRB1 Echo Cancel IIR
Filt Coeff B1 ECIIRB1[15:3] Init FEA0 –1408
FSK Generation
102 FSKAMP0 FSK Amplitude for Space FSKAMP0 [15:3] Init 0100 .22 Vrms
103 FSKAMP1 FSK Amplitude for Mark FSKAMP1[15:3] Init 01E0 .22 Vrms
100 FSKFREQ0 FSK Frequency for Space FSKFREQ0[15:3] Init 3CE0 1200 Hz
101 FSKFREQ1 FSK Frequency for Mark FSKFREQ1[15:3] Init 35B0 2200 Hz
104 FSK01HI FSK 0-1 Transition Freq—
High FSK01HI[15:3] Init 3BE0
105 FSK01LO FSK 0-1 Transition
Frequency—Low FSK01LO[15:3] Init 1330
106 FSK10HI FSK 1-0 Transition
Frequency—High FSK10HI[15:3] Init 1118
107 FSK10LO FSK 1-0 Transition
Frequency—Low FSK10LO[15:3] Init 1D88
RAM
Addr Mnemonic Description Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9Bit
8Bit
7Bit
6Bit
5Bit
4Bit
3Bit
2Bit
1Bit
0Type Example
Hex Example
Dec Unit
Notes:
1. Any register not listed is reserved and must not be written.
2. Only positive input values are valid for these RAM addresses.
3. Si3225 only.
4. Si3220 only.
5. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay
between when the relay opens and when the LFS register transitions out of the ringing state.
6. For the Si3220, the RINGA MP RAM ad dr ess l o cati on is use d to sto re the am p litu de of the intern al r in gin g si gn al . Fo r t he Si3225, this address location stores the desired time relay between the last
zero current crossing and the next opportunity to open the ringing relay.
7. RAM address in decimal.
Si3220/Si3225
96 Preliminary Rev. 0.91
Loop Currents
9 ILON G Longitudinal Cur rent Sense
Value ILONG[15:0]2DIag mA
8 ILOOP Loop Current Sense Value ILOOP[15:0]2Diag mA
18 IRING Q5 Current Measurement IRING[15:0] Diag mA
16 IRINGN Q3 Current Measurement IRINGN[15:0] Diag mA
15 IRINGP Q2 Current Measurement IRINGP[15:0] Diag mA
21 IRNGNG External Ringing Genera-
tor Current Measurement IRNGNG[15:0]3Diag mA
19 ITIP Q6 Current Measurement ITIP[15:0] Diag mA
17 ITIPN Q4 Current Measurement ITIPN[15:0] Diag mA
14 ITIPP Q1 Current Measurement ITIPP[15:0] Diag mA
Loop Closure Detection
24 LCRDBI Loop Closure Detection
Debounce Interval LCRDBI[15:0]2Init 000C 15 ms
25 LCRLPF Loop Closure Filter
Coefficient LCRLPF[15:3] Init 0A10 10 Hz
26 LCRMASK Loop Closure Mask Inte rval
Coeff LCRMASK[15:0]2Init 0040 80 ms
166 LCRMSKPR LCR Mask During Polarity
Reversal LCRMSKPR[15:0] Init 0040 80 ms
22 LCROFFHK Off-Hook Detect
Threshold LCROFFHK[15:0]2Init 0C0C 10 mA
23 LCRONHK On-Hook Detect
Threshold LCRONHK[15:0]2Init 0DEO 11 mA
Longitudinal Current Detection
29 LONGDBI Ground Key Detection
Debounce Interval LONGDBI[15:0]2Init ms
27 LONGHITH Ground Key Detection
Threshold LONGHITH[15:0]2Init 08D4 7 mA
28 LONGLOTH Ground Key Removal
Detection Threshold LONGLOTH[15:0]2Init 0A17 8 mA
30 LONGLPF Ground Key Filter
Coefficient LONGLPF[15:3] Init 0A08 10 Hz
Oscillator Coeffic ie nts
95 OSC1AMP Oscillator 1 Amplitude OSC1AMP[15:0] Init 004F 0.0775 Vrms
94 OSC1FREQ Oscillator 1 Frequency OSC1FREQ[15:3] Init 3D98 350 Hz
96 OSC1PHAS Oscillator 1 In itial Phase OSC1PHAS[15:0] Init 000 0
98 OSC2AMP Oscillator 2 Amplitude OSC2AMP[15:0] Init 0063 0.0775 Vrms
97 OSC2FREQ Oscillator 2 Frequency OSC2FREQ[15:3] Init 3C38 440 Hz
99 OSC2PHAS Oscillator 2 In itial Phase OSC2PHAS[15:0] Init 000 0
Power Calculations
RAM
Addr Mnemonic Description Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9Bit
8Bit
7Bit
6Bit
5Bit
4Bit
3Bit
2Bit
1Bit
0Type Example
Hex Example
Dec Unit
Notes:
1. Any register not listed is reserved and must not be written.
2. Only positive input values are valid for these RAM addresses.
3. Si3225 only.
4. Si3220 only.
5. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay
between when the relay opens and when the LFS register transitions out of the ringing state.
6. For the Si3220, the RINGA MP RAM ad dr ess l o cati on is use d to sto re the am p litu de of the intern al r in gin g si gn al . Fo r t he Si3225, this address location stores the desired time relay between the last
zero current crossing and the next opportunity to open the ringing relay.
7. RAM address in decimal.
Si3220/Si3225
Preliminary Rev. 0.91 97
40 PLPFQ12 Q1/Q2 Thermal Low Pass
Filter Coeff PLFPQ12[15:3] Init 0008 .3 s
41 PLFPQ34 Q3/Q4 Thermal Low Pass
Filter Coeff PLFPQ34[15:3] Init 0008 .3 s
42 PLFPQ56 Q5/Q6 Thermal Low Pass
Filter Coeff PLFPQ56[15:3] Init 0008 .3 s
Pulse Metering
68 PMAMPL Pulse Meteri ng Amplitude PMAMPL[15:0]4Init 4000 65536 V
70 PMAM PTH Pulse Metering AGC
Amplitude Threshold PMAMPTH[15:0]4Init 00C8 798 V
67 PMFREQ Pulse Metering
Frequency PMFREQ[15:3]4Init 0000 0 Hz
69 PMRAMP Pulse Metering Ramp Rate PMRAMP[15:0]4Init 008A 550 s
Power Calculations
44 PQ1DH Q1 Calculated Power PQ1DH[15:0] Diag W
45 PQ2DH Q2 Calculated Power PQ2DH[15:0] Diag W
46 PQ3DH Q3 Calculated Power PQ3DH[15:0] Diag W
47 PQ4DH Q4 Calculated Power PQ4DH[15:0] Diag W
48 PQ5DH Q5 Calculated Power PQ5DH[15:0] Diag W
49 PQ6DH Q6 Calculated Power PQ6DH[15:0] Diag W
50 PSUM Total Calculated Power PSUM[15:0] Diag W
37 PTH12 Q1/Q2 Power Threshold PTH12[15:0]2Init 0007 .22 W
38 PTH34 Q3/Q4 Power Threshold PTH34[15:0]2Init 003C 17 W
39 PTH56 Q5/Q6 Power Threshold PTH56[15:0]2Init 002A 1.28 W
43 RB56 Q5/Q6 Base Resistor RB56[15:0] Init Ω
Ringing
59 RINGAMP Ringing Amplitude/Zero
Crossing Delay RINGAMP[15:0]6/ZERDELAY[15:0] Init 00D5 47 Vrms
57 RINGFRHI Ringing Frequency—High
Byte/Linefeed Status Delay RINGFRHI[14:3]5/LFSDELAY[14:3] Init 3F78 20 Hz
58 RIN GF RLO Ringing Frequency—
Low Byte RINGFRLO[14:3]4Init 6CE8 20 Hz
56 RINGOF Ringing Waveform DC
Offset RINGOF[15:0]4Init 0000 0 V
60 RINGPHAS Ringing Oscillator
Initial Phase RINGPHAS[15:3]4Init 0000
Ring Trip Detection
66 RTACDB AC Ring Trip
Debounce Interval RTACDB[15:0] Init 0008 10 ms
64 RTACTH AC Ring Trip
Detect Threshold RTACTH[15:0] Init 1086 mA
61 RTCOUNT Ring Trip
Tim eo ut Counter RTCOUNT[15:0] Init 0400 128 ms
RAM
Addr Mnemonic Description Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9Bit
8Bit
7Bit
6Bit
5Bit
4Bit
3Bit
2Bit
1Bit
0Type Example
Hex Example
Dec Unit
Notes:
1. Any register not listed is reserved and must not be written.
2. Only positive input values are valid for these RAM addresses.
3. Si3225 only.
4. Si3220 only.
5. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay
between when the relay opens and when the LFS register transitions out of the ringing state.
6. For the Si3220, the RINGA MP RAM ad dr ess l o cati on is use d to sto re the am p litu de of the intern al r in gin g si gn al . Fo r t he Si3225, this address location stores the desired time relay between the last
zero current crossing and the next opportunity to open the ringing relay.
7. RAM address in decimal.
Si3220/Si3225
98 Preliminary Rev. 0.91
65 RTDCDB DC Ring Trip
Debounce Interval RTDCDB[15:0] Init 0008 10 ms
62 RTDCTH DC Ring Trip
Detect Threshold RTDCTH[15:0] Init 7FFF mA
63 RTPER Ring Trip Low Pass Filter
Coeff Period RTPER[15:0] Init 0028 20 Hz
Receive Path Gain and Filters
81 RXIIRPOL RX IIR Filter Pole Coeff RXIIRPOL[15:3] Init 3CCC 62256
80 RXEQCO0 RX Equalizer
Coeff 0 RXEQCO0[15:3] Init 4000 65536
79 RXEQCO1 RX Equalizer
Coeff 1 RXEQCO1[15:3] Init 0000 0
78 RXEQCO2 RX Equalizer
Coeff 2 RXEQCO2[15:3] Init 0000 0
77 RXEQCO3 RX Equalizer
Coeff 3 RXEQCO3[15:3] Init 0000 0
71 RXGAIN RX Gain Setting RXGAIN[15:3] Init 4000 1
123 RXMODPWR RX Path Modem
Tone Power RXMODPWR[15:3] Init
121 RXPWR RX Path Input
Signal Power RXPWR[15:0] Init
DC Speedup
168 SPEEDUP DC Spe e d up Tim er SPEEDUP[15:0] Init 0000 60 ms
Test Diagnostic Filters
132 TESTA1H1 TX Diag Filter Coeff A1H1 TESTA1H1[15:3] Diag
142 TESTA1H2 TX Diag Filter Coeff A1H2 TESTA1H2[15:3] Diag
152 TESTA1H3 TX Diag Filter Coeff A1H3 TESTA1H3[15:3] Diag
131 TESTA1L1 TX Diag Filter Coeff A1L1 TESTA1L1[15:3] Diag
141 TESTA1L2 TX Diag Filter Coeff A1L2 TESTA1L2[15:3] Diag
151 TESTA1L3 TX Diag Filter Coeff A1L3 TESTA1L3[15:3] Diag
134 TESTA2H1 TX Diag Filter Coeff A2H1 TESTA2H1[15:3] Diag
144 TESTA2H2 TX Diag Filter Coeff A2H2 TESTA2H2[15:3] Diag
154 TESTA2H3 TX Diag Filter Coeff A2H3 TESTA2H3[15:3] Diag
133 TESTA2L1 TX Diag Filter Coeff A2L1 TESTA2L1[15:3] Diag
143 TESTA2L2 TX Diag Filter Coeff A2L2 TESTA2L2[15:3] Diag
153 TESTA2L3 TX Diag Filter Coeff A2L3 TESTA2L3[15:3] Diag
156 TESTAVO TX Diag Filter
Avg Output TESTAVO[15:0] Diag V
158 TESTAVBW TX Diag Filter
Avg Bandwidth TESTAVBW[15:3] Diag
160 TESTAVFL TX Diag Filter
Average Flag TESTAVFL[15:3] Diag
RAM
Addr Mnemonic Description Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9Bit
8Bit
7Bit
6Bit
5Bit
4Bit
3Bit
2Bit
1Bit
0Type Example
Hex Example
Dec Unit
Notes:
1. Any register not listed is reserved and must not be written.
2. Only positive input values are valid for these RAM addresses.
3. Si3225 only.
4. Si3220 only.
5. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay
between when the relay opens and when the LFS register transitions out of the ringing state.
6. For the Si3220, the RINGA MP RAM ad dr ess l o cati on is use d to sto re the am p litu de of the intern al r in gin g si gn al . Fo r t he Si3225, this address location stores the desired time relay between the last
zero current crossing and the next opportunity to open the ringing relay.
7. RAM address in decimal.
Si3220/Si3225
Preliminary Rev. 0.91 99
162 TESTAVTH TX Diag Filter
Avg Threshold TESTAVTH[15:3] Diag
126 TESTB0H1 TX Diag Filter Coeff B0H1 TESTB0H1[15:3] Diag
136 TESTB0H2 TX Diag Filter Coeff B0H2 TESTB1H2[15:3] Diag
146 TESTB0H3 TX Diag Filter Coeff B0H3 TESTB0H3[15:3] Diag
125 TESTB0L1 TX Diag Filter Coeff B0L1 TESTB0L1[15:3] Diag
135 TESTB0L2 TX Diag Filter Coeff B0L2 TESTB0L2[15:3] Diag
145 TESTB0L3 TX Diag Filter Coeff B0L3 TESTB0L3[15:3] Diag
128 TESTB1H1 TX Diag Filter Coeff B1H1 TESTB1H1[15:3] Diag
138 TESTB1H2 TX Diag Filter Coeff B1H2 TESTB1H2[15:3] Diag
148 TESTB1H3 TX Diag Filter Coeff B1H3 TESTB1H3[15:3] Diag
127 TESTB1L1 TX Diag Filter Coeff B1L1 TESTB1L1[15:3] Diag
137 TESTB1L2 TX Diag Filter Coeff B1L2 TESTB1L2[15:3] Diag
147 TESTB1L3 TX Diag Filter Coeff B1L3 TESTB1L3[15:3] Diag
130 TESTB2H1 TX Diag Filter Coeff B2H1 TESTB2H1[15:3] Diag
140 TESTB2H2 TX Diag Filter Coeff B2H2 TESTB2H2[15:3] Diag
150 TESTB2H3 TX Diag Filter Coeff B2H3 TESTB2H3[15:3] Diag
129 TESTB2L1 TX Diag Filter Coeff B2L1 TESTB2L1[15:3] Diag
139 TESTB2L2 TX Diag Filter Coeff B2L2 TESTB2L2[15:3] Diag
149 TESTB2L3 TX Diag Filter Coeff B2L3 TESTB2L3[15:3] Diag
159 TESTPKFL TX Diag Filter
Peak Flag TESTPKFL[15:3] Diag
155 T ESTPKO TX Diag Filter
Peak Output TESTPKO[15:3] Diag V
161 TESTPKTH TX Diag Filter
Peak Threshold TESTPKTH[15:3] Diag
157 TESTWLN TX Diag Filter TESTWLN[15:3] Diag
Transmit Path Gain and Filters
76 TXEQCO0 TX Equalizer
Coefficient 0 TXEQCO0[15:3] Init 4A6A 76201
75 TXEQCO1 TX Equalizer
Coefficient 1 TXEQCO1[15:3] Init F84C –7888
74 TXEQCO2 TX Equalizer
Coefficient 2 TXEQCO2[15:3] Init 012C 1199
73 TXEQCO3 TX Equalizer
Coefficient 3 TXEQCO3[15:3] Init 004C 302
72 TXGAIN TX Gain Setting TXGAIN[15:3] Init 4000 1
163 TXHPF1 TX HPF Coefficient 1 TXHPF1[15:3] Diag
164 TXHPF2 TX HPF Coefficient 2 TXHPF2[15:3] Diag
165 TXHPF3 TX HPF Coefficient 3 TXHPF3[15:3] Diag
RAM
Addr Mnemonic Description Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9Bit
8Bit
7Bit
6Bit
5Bit
4Bit
3Bit
2Bit
1Bit
0Type Example
Hex Example
Dec Unit
Notes:
1. Any register not listed is reserved and must not be written.
2. Only positive input values are valid for these RAM addresses.
3. Si3225 only.
4. Si3220 only.
5. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay
between when the relay opens and when the LFS register transitions out of the ringing state.
6. For the Si3220, the RINGA MP RAM ad dr ess l o cati on is use d to sto re the am p litu de of the intern al r in gin g si gn al . Fo r t he Si3225, this address location stores the desired time relay between the last
zero current crossing and the next opportunity to open the ringing relay.
7. RAM address in decimal.
Si3220/Si3225
100 Preliminary Rev. 0.91
124 TXMODPWR TX Path Modem
Tone Power TXMODPWR[15:3] Init
122 TXPWR TX Path Input
Signal Power TXPWR[15:0] Init
Loop Voltages
13 VBAT Scaled Battery Voltage
Measurement VBAT[15:0] Diag V
4 VCM Common Mode Voltage VCM[14:0]2Init 0268 3 V
7 VLOOP Loop Voltage VLOOP[15:0]2Diag V
0 VOC Open Circuit Voltage VOC[14:0]2Init 2668 48 V
1 VOCDELTA VOC Delta for Off-Hook VOCDELTA[14:0]2Init 059A 7 V
3 VOCHTH VOC Delta Upper
Threshold VOCHTH[15:0]2Init 0198 2 V
2 VOCLTH VOC Delta Lower
Threshold VOCLTH[15:0] Init F9A2 –8 V
10 VOCTRACK Battery Tracking Open
Circuit Voltage VOCTRACK[15:0]2Diag V
5 VOV Overhead Voltage VOV[14:0]2Init 0334 4 V
6 VOVRING Ringing Overhead
Voltage VOVRING[14:0]2Init 0000 0 V
12 VRING Scaled RING Voltage
Measurement VRING[15:0] Diag V
20 VRNGNG External Ringing Genera-
tor Volt age Measurem en t VRNGNG[14:7]3Diag V
11 VTIP Scaled TIP Voltage
Measurement VTIP[15:0] Diag V
RAM
Addr Mnemonic Description Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9Bit
8Bit
7Bit
6Bit
5Bit
4Bit
3Bit
2Bit
1Bit
0Type Example
Hex Example
Dec Unit
Notes:
1. Any register not listed is reserved and must not be written.
2. Only positive input values are valid for these RAM addresses.
3. Si3225 only.
4. Si3220 only.
5. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay
between when the relay opens and when the LFS register transitions out of the ringing state.
6. For the Si3220, the RINGA MP RAM ad dr ess l o cati on is use d to sto re the am p litu de of the intern al r in gin g si gn al . Fo r t he Si3225, this address location stores the desired time relay between the last
zero current crossing and the next opportunity to open the ringing relay.
7. RAM address in decimal.
Si3220/Si3225
Preliminary Rev. 0.91 101
Pin Descriptions: Si3220/25
Pin Number(s) Symbol Input/
Output Description
Si3220 Si3225
1, 16 1, 16 SVBATa,
SVBATb IBattery Sensin g Input.
Analog current input used to sense battery voltage.
2,15 2,15 RPOa, RPOb O Transconductance Amplifier External Resistor Connection.
3, 14 3, 14 RPIa,
RPIb ITransconductance Amplifier External Resistor Conne ction.
4, 13 4, 13 RNIa,
RNIb ITransconductance Amplifier Resistor Connection.
5, 12 5, 12 RNOa, RNOb O Transconductance Amplifier Resistor Connection.
6, 11 6, 11 CAPPa,
CAPPb Differential Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback
loops.
7, 10 7, 10 CAPMa,
CAPMb Common Mode Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback
loops.
88 QGND Component Reference Ground.
Return path for diffe rential and common mode capacitors. Do n ot
connect to system ground.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 201918 24232221 31302928272625 32
64 616263 57585960 50515253545556 49
RPOa
SVBATa
RPIa
RNIa
RNOa
CAPPa
CAPMa
QGND
IREF
CAPMb
CAPPb
RNOb
RNIb
RPIb
RPOb
SVBATb
STIPACb
STIPDCb
SRINGACb
SRINGDCb
ITIPNb
IRINGNb
ITIPPb
VDD2
GND2
IRINGPb
THERMb
RTRPb
TRD1b
TRD2b
RRDb
BATSELb
CS
RRDa
SDITHRU
SDI
SDO
SCLK
VDD4
GND4
INT
PCLK
GND3
VDD3
DTX
DRX
RESET
FSYNC
STIPACa
STIPDCa
SRINGACa
SRINGDCa
ITIPNa
IRINGNa
ITIPPa
VDD1
GND1
IRINGPa
THERMa
BLKRNG
RTRPa
TRD1a
BATSELa
TRD2a
Si3225
64-Lead TQFP
(epad)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 201918 24232221 31302928272625 32
64 616263 57585960 50515253545556 49
RPOa
SVBATa
RPIa
RNIa
RNOa
CAPPa
CAPMa
QGND
IREF
CAPMb
CAPPb
RNOb
RNIb
RPIb
RPOb
SVBATb
STIPACb
STIPDCb
SRINGACb
SRINGDCb
ITIPNb
IRINGNb
ITIPPb
VDD2
GND2
IRINGPb
THERMb
NC
TRD1b
TRD2b
GPOb
BATSELb
CS
GPOa
SDITHRU
SDI
SDO
SCLK
VDD4
GND4
INT
PCLK
GND3
VDD3
DTX
DRX
RESET
FSYNC
STIPACa
STIPDCa
SRINGACa
SRINGDCa
ITIPNa
IRINGNa
ITIPPa
VDD1
GND1
IRINGPa
THERMa
NC
NC
TRD1a
BATSELa
TRD2a
Si3220
64-Lead TQFP
(epad)
Si3220/Si3225
102 Preliminary Rev. 0.91
99 IREF IIREF Current Reference.
Connects to an external resisto r to provide a high accuracy refe r-
ence current. Return path for IREF resistor should be routed to
QGND pin.
17, 64 17, 64 STIPDCb,
STIPDCa ITIP Sense.
Analog current input senses dc volt age on TIP side of subscriber
loop.
18, 63 18, 63 STIPACb,
STIPACa ITIP Transmit Input.
Analog input senses ac voltage on TIP side of subscriber loop.
19, 62 19, 62 SRINGACb,
SRINGACa IRING Transmit Input.
Analog input senses ac voltage on RING side of subscriber loop.
20, 61 20, 61 SRINGDCb,
SRINGDCa IRING Sense.
Analog current input senses dc voltage on RING side of sub-
scriber loop.
21, 60 21, 60 ITIPNb,
ITIPNa ONegative TIP Current Control.
Analog current output provides dc current return path to VBAT
from TIP side of the loop.
22, 59 22, 59 IRINGNb,
IRINGNa ONegative RING Current Contro l.
Analog current output provides dc current return path to VBAT
from RING side of loop.
23, 58 23, 58 ITIPPb,
ITIPPa OPositive TIP Current Control.
Analog current output drives dc current onto TIP side of sub-
scriber loop in normal polarity. Also modulates ac current onto
TIP side of loop.
24, 37,
42, 57 24, 37,
42, 57 VDD2,VDD3,
VDD4,VDD1 Supply Voltage.
Power supply for internal ana log a nd digital circuitry. Connect all
VDD pins to the same supply and de couple to adjacent GND pi n
as close to the pins as possible.
25, 38,
41, 56 25, 38,
41, 56 GND2,GND3,
GND4,GND1 Ground.
Ground connection for internal analog and digital circuitry. Con-
nect all pins to low-impedance ground plane.
26, 55 26, 55 IRINGPb,
IRINGPa OPositive RING Current Control.
Analog current ou tp ut drive s dc current onto RING sid e of sub-
scriber loop in reverse polarity. Also modulates ac current onto
RING side of loop.
27,54 27,54 THERMb,
THERMa ITemperature Sensor.
Senses Internal temperature of Si3200.
29, 51 29, 51 TRD1b,
TRD1a OTest Relay Driver Output.
Drives test relays for connecting loop test equipment.
28, 52,
53 NC No Internal Connection.
Leave unconnected or connect to ground plane.
Pin Number(s) Symbol Input/
Output Description
Si3220 Si3225
Si3220/Si3225
Preliminary Rev. 0.91 103
28, 52 RTRPb,
RTRPa IExternal Ring Trip Sensing Input.
Used to sense ring-trip condition when using centralized ring
generator. Connect to low side of ring sense resistor.
30, 50 30, 50 TRD2b,
TRD2a OTest Relay Driver Output.
Drives test relays for connecting loop test equipment.
31, 48 RRDb, RRDa O Ring Relay Driver Output.
Connects an external centralized ring generator to the subscriber
loop.
31, 48 GPOb, GPOa O General Purpose Output Driver.
Used as a relay driver or as a second battery select pin when
using a third battery supply.
32, 49 32, 49 BATSELb,
BATSELa OBattery Voltage Select Pin.
Switches between high and low exte rnal battery supplies.
35 35 DRX I Receive PCM Data.
Input data from PCM/GCI bus.
36 36 DTX O Transmit PCM Dat a.
Output data to PCM/GCI bus.
39 39 PCLK I PCM Bus Clock.
Clock input for PCM/GCI bus timing.
33 33 RESET IReset.
Active low. Hardware reset used to place all control registers in
known state. An internal pulldown resistor asserts this pin low
when not driven externally.
34 34 FSYNC I Frame Sync.
8 kHz frame synchronization signal for PCM/GCI bus. May be
short or long pulse format.
40 40 INT OInterrupt.
Maskable interrupt output. Open drain output for wire-ORed
operation.
43 43 SCLK I Serial Port Bit Clock Input.
Controls serial data on SDO and latches data on SDI.
44 44 SDO O Serial Port Data Out.
Serial port control data output.
45 45 SDI I Serial Port Dat a In.
Serial port control data input.
46 46 SDITHRU O Serial Data Daisy Chain.
Enables multiple devices to use a single CS for serial port con-
trol. Connect SDITHRU pin from master device to SDI pin of
slave device. An internal pu llup resistor holds this pin hig h during
idle periods.
Pin Number(s) Symbol Input/
Output Description
Si3220 Si3225
Si3220/Si3225
104 Preliminary Rev. 0.91
47 47 CS IChip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO
is high impedance. When active, serial port is operational.
53 BLKRNG I Ring Generator Sensing Input.
Senses ring-trip condition when using centralized r ing generator.
Connect to high side of ring sen se re sistor. Shared by chann el a
and b.
epad epad GND Exposed Die Paddle Ground.
Connect to a low-impedance gr ound p lane via top side PCB pad
directly under the part. See Package Outlines: 64-Pin TQFP for
PCB pad dimensions.
Pin Number(s) Symbol Input/
Output Description
Si3220 Si3225
Si3220/Si3225
Preliminary Rev. 0.91 105
Pin Descriptions: Si3200
Pin #(s) Symbol Input/
Output Description
1 TIP I/O TIP Output.
Connect to the TIP lead of the subscriber loop.
2, 10, 11 NC — No Internal Connection.
Do not connect to any electrical signal.
3 RING I/O RING Output.
Connect to the RIN G lea d of the subscriber loop.
4VBAT—
Operating Battery Voltage.
Si3200 internal system battery supply. Connect SVBATa/b pin from Si3220/
25 and decouple with a 0.1 µF/100 V filter capacitor.
5VBATH—
High Battery Voltage.
Connect to the system ringing battery supply. Decouple with a 0.1 µF/100 V
filter capacitor.
6 VBATL — Low Battery Voltage.
Connect to lowest system battery supply for off-hook operation driving short
loops. An internal diode prevents leakage current when operating from
VBATH.
7GND—
Ground.
Connect to a low-impedance ground plane.
8VDD—
Supply Voltage.
Main power supply for all internal circuitr y. Conn ect to a 3.3 V or 5 V supply.
Decouple locally with a 0.1 µF/10 V capacitor.
9 BATSEL I Battery Volt age Select.
Connect to the BATSEL pin of the Si3220 or Si3225 through an exter nal
resistor to enable automatic battery switching. No connection is required
when used with the Si3225 in a single battery system configuration.
Si3200
16-Lead SOIC
(epad)
116
215
314
413
512
611
710
89
ITIPP
THERM
IRINGP
IRINGN
NC
NC
BATSEL
ITIPN
TIP
NC
RING
VBATH
GND
VBATL
VDD
VBAT
Si3220/Si3225
106 Preliminary Rev. 0.91
12 IRINGN I Negative RING Current Control.
Connect to the IRINGN lead of the Si3220 or Si3225.
13 IRINGP I Positive RING Current Drive.
Connect to the IRINGP lead of the Si3220 or Si3225.
14 THERM O Thermal Sensor.
Connection to internal temperature sensing circ uit.
Connect to THERM pin of Si3220 or Si3225.
15 ITIPN I Negative TIP Current Control.
Connect to the ITIPN lead of the Si3220 or Si3225.
16 ITIPP I Positive TIP Current Control.
Connect to the ITIPP lead of the Si3220 or Si3225.
epad GND Exposed Die Paddle Ground.
For adequate thermal management, the exposed die paddle should be sol-
dered to a PCB pad that is connected to low-impedance inner and/or back-
side ground planes using multiple vias. See “Package Outline: 16-Pin
SOIC” for PCB pad dimensions.
Pin #(s) Symbol Input/
Output Description
Si3220/Si3225
Preliminary Rev. 0.91 107
Dual ProSLIC Selection Guide
Part
Number Description On-Chip
Ringing External
Ringing
Support
Pulse
Metering Temp
Range Package
Si3200-KS Linefeed in terface 0 to 70 °CSOIC-16
Si3200-BS Linefeed interface –40 to 85 °CSOIC-16
Si3220-KQ Dual ProSLIC ""
0 to 70 °CTQFP-64
Si3220-BQ Dual ProSLIC ""
–40 to 85 °CTQFP-64
Si3225-KQ Dual ProSLIC "0 to 70 °CTQFP-64
Si3225-BQ Dual ProSLIC "–40 to 85 °CTQFP-64
Si3220/Si3225
108 Preliminary Rev. 0.91
Package Outline: 64-Pin TQFP
Figure 65 illustrates the package details for the Dual ProSLIC. Table 48 lists the values for the dimensions shown
in the illustration.
Figure 65. 64-Pin Thin Quad Flat Package (TQFP)
Table 48. 64-Pin Package Diagram Dimensions
Symbol Millimeters
Min Nom Max
A——1.20
A1 0.05 — 0.15
A2 0.95 1.00 1.05
D 12.00 BSC
D1 10.00 BSC
E 12.00 BSC
E1 10.00 BSC
L 0.45 0.60 0.75
e 0.50 BSC
b 0.17 0.22 0.27
b1 0.17 0.20 0.23
D
D1
E
E1
1
16
A
17 32
33
48
4964
Exposed Pad
6 x 6 mm
e
See Detail A
See Detail B
0° Min.
0.08/0.20 R
L
Detail A
GAUGE PLANE
A2
A1
0-7°
1.00 REF
0.08
R. Min.
0.20 Min.
Detail B
0.09/0.20 0.09/0.16
b
b1
with lead finish
base metal
Si3220/Si3225
Preliminary Rev. 0.91 109
Package Outline: 16-Pin SOIC
Figure 66 illustrates the package details for the Si3200. Table 49 lists the values for the dimensions shown in the
illustration.
Figure 66. 16-Pin Small Outline Integrated Circuit (SOIC) Package
Table 49. Package Diagram Dimensions
Symbol Millimeters
Min Max
A1.351.75
A1 .10 .25
A2 1.30 1.50
B.33.51
C.19.25
D9.8010.01
E3.804.00
e 1.27 BSC
H5.806.20
h.25.50
L .40 1.27
L1 1.07 BSC
γ—0.10
θ0º 8º
E H
A1
B
C
h
L
θ
e
See Detail F
Detail F
A
16 9
8
1GAUGE PLANE
0.010
D
A2
Seating Pl ane
L1
γ
Exposed Pad
2.3 x 3.6 mm
Si3220/Si3225
110 Preliminary Rev. 0.91
Document Change List
Revision 0.9 to Revision 0.91
!Table 8 on page 12
" TIP/RING Pulldown Transistor Saturation Voltage
updated.
" TIP/RING Pullup Transistor Saturation Voltage updated.
" Note added.
!"Calculating Overhead Voltages" on page 27
" Second paragraph updated.
!"Internal Trapezoidal Ringing" on page 42
" RINGAMP equation updated.
Si3220/Si3225
Preliminary Rev. 0.91 111
Notes:
Si3220/Si3225
112 Preliminary Rev. 0.91
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: productinfo@silab s .com
Internet: www.silabs.com
Silicon Laboratories, Silicon Labs, ProSLIC, and Modfeed are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
