ADSP-BF537BBCZ-5BV - Analog Devices, Inc.

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Blackfin

Embedded Processor

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

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Tel: 781.329.4700 www.analog.com

FEATURES

Up to 600 MHz high performance Blackfin processor

Three 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Wide range of operating voltages (see Operating Conditions

on Page 24)

Qualified for Automotive Applications (see Automotive Prod-

ucts on Page 67)

Programmable on-chip voltage regulator

182-ball and 208-ball CSP_BGA packages

MEMORY

Up to 132K bytes of on-chip memory

Instruction SRAM/cache and instruction SRAM

Data SRAM/cache plus additional dedicated data SRAM

Scratchpad SRAM (see Table 1 on Page 3 for available

memory configurations)

External memory controller with glueless support for SDRAM

and asynchronous 8-bit and 16-bit memories

Flexible booting options from external flash, SPI and TWI

memory or from SPI, TWI, and UART host devices

Memory management unit providing memory protection

PERIPHERALS

IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and

ADSP-BF537 only)

Controller area network (CAN) 2.0B interface

Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats

2 dual-channel, full-duplex synchronous serial ports

(SPORTs), supporting 8 stereo I

S channels

12 peripheral DMAs, 2 mastered by the Ethernet MAC

2 memory-to-memory DMAs with external request lines

Event handler with 32 interrupt inputs

Serial peripheral interface (SPI) compatible

2 UARTs with IrDA support

2-wire interface (TWI) controller

Eight 32-bit timer/counters with PWM support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), 8 with high current drivers

On-chip PLL capable of frequency multiplication

Debug/JTAG interface

Figure 1. Functional Block Diagram

SPORT0

CAN

VOLTAGE REGULATOR

PORT J

GPIO

PORT H

GPIO

PORT G

GPIO

PORT F

JTAG TEST AND EMULATION

PERIPHERAL ACCESS BUS

WATCHDOG TIMER

RTC

TWI

SPORT1

PPI

SPI

TIMER7-0

ETHERNET MAC

(See Table 1)

BOOT ROM

DMA

EXTERNAL

BUS

INTERRUPT

CONTROLLER

DMA

CONTROLLER

DATA

MEMORY

INSTRUCTION

MEMORY

DMA CORE BUS

EXTERNAL ACCESS BUS

EXTERNAL PORT

FLASH, SDRAM CONTROL

UART0-1

Rev. I | Page 2 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

Blackfin Processor Peripherals ................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 9

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) .......................................... 10

Serial Peripheral Interface (SPI) Port ....................... 10

UART Ports ...................................................... 10

Controller Area Network (CAN) ............................ 11

TWI Controller Interface ...................................... 11

10/100 Ethernet MAC .......................................... 11

Ports ................................................................ 12

Parallel Peripheral Interface (PPI) ........................... 12

Dynamic Power Management ................................ 13

Voltage Regulation .............................................. 14

Clock Signals ..................................................... 15

Booting Modes ................................................... 16

Instruction Set Description ................................... 17

Development Tools .............................................. 17

Designing an Emulator-Compatible Processor Board ... 18

Related Documents .............................................. 19

Related Signal Chains ........................................... 19

Pin Descriptions .................................................... 20

Specifications ........................................................ 24

Operating Conditions ........................................... 24

Electrical Characteristics ....................................... 26

Absolute Maximum Ratings ................................... 30

ESD Sensitivity ................................................... 30

Package Information ............................................ 30

Timing Specifications ........................................... 31

Output Drive Currents ......................................... 51

Test Conditions .................................................. 53

Thermal Characteristics ........................................ 57

182-Ball CSP_BGA Ball Assignment ........................... 58

208-Ball CSP_BGA Ball Assignment ........................... 61

Outline Dimensions ................................................ 64

Surface-Mount Design .......................................... 66

Automotive Products .............................................. 67

Ordering Guide ..................................................... 68

REVISION HISTORY

7/10—Rev. H to Rev. I

Corrected all document errata.

Replaced incorrect Figure 5, Voltage Regulator Circuit ... 14

Replaced incorrect Figure 13, External Port Bus Request and

Grant Cycle Timing ................................................ 34

To view product/process change notifications (PCNs) related to

this data sheet revision, please visit the processor’s product page

on the www.analog.com website and use the View PCN link.

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 3 of 68 | July 2010

GENERAL DESCRIPTION

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are

members of the Blackfin

family of products, incorporating the

Analog Devices, Inc./Intel Micro Signal Architecture (MSA).

Blackfin processors combine a dual-MAC, state-of-the-art sig-

nal processing engine, the advantages of a clean, orthogonal

RISC-like microprocessor instruction set, and single-instruc-

tion, multiple-data (SIMD) multimedia capabilities into a single

instruction-set architecture.

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are

completely code and pin compatible. They differ only with

respect to their performance, on-chip memory, and presence of

the Ethernet MAC module. Specific performance, memory, and

feature configurations are shown in Table 1.

By integrating a rich set of industry-leading system peripherals

and memory, the Blackfin processors are the platform of choice

for next-generation applications that require RISC-like pro-

grammability, multimedia support, and leading-edge signal

processing in one integrated package.

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. They are produced with a low power and low

voltage design methodology and feature on-chip dynamic

power management, which is the ability to vary both the voltage

and frequency of operation to significantly lower overall power

consumption. This capability can result in a substantial reduc-

tion in power consumption, compared with just varying the

frequency of operation. This allows longer battery life for

portable appliances.

SYSTEM INTEGRATION

The Blackfin processor is a highly integrated system-on-a-chip

solution for the next generation of embedded network-con-

nected applications. By combining industry-standard interfaces

with a high performance signal processing core, cost-effective

applications can be developed quickly, without the need for

costly external components. The system peripherals include an

IEEE-compliant 802.3 10/100 Ethernet MAC (ADSP-BF536 and

ADSP-BF537 only), a CAN 2.0B controller, a TWI controller,

two UART ports, an SPI port, two serial ports (SPORTs), nine

general-purpose 32-bit timers (eight with PWM capability), a

real-time clock, a watchdog timer, and a parallel peripheral

interface (PPI).

BLACKFIN PROCESSOR PERIPHERALS

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors con-

tain a rich set of peripherals connected to the core via several

high bandwidth buses, providing flexibility in system configura-

tion as well as excellent overall system performance (see

Figure 1). The processors contain dedicated network communi-

cation modules and high speed serial and parallel ports, an

interrupt controller for flexible management of interrupts from

the on-chip peripherals or external sources, and power manage-

ment control functions to tailor the performance and power

characteristics of the processor and system to many application

scenarios.

All of the peripherals, except for the general-purpose I/O, CAN,

TWI, real-time clock, and timers, are supported by a flexible

DMA structure. There are also separate memory DMA channels

dedicated to data transfers between the processor’s various

memory spaces, including external SDRAM and asynchronous

memory. Multiple on-chip buses running at up to 133 MHz

provide enough bandwidth to keep the processor core running

along with activity on all of the on-chip and external

peripherals.

The Blackfin processors include an on-chip voltage regulator in

support of the processors’ dynamic power management capabil-

ity. The voltage regulator provides a range of core voltage levels

when supplied from V

DDEXT

. The voltage regulator can be

bypassed at the user’s discretion.

Table 1. Processor Comparison

Features

ADSP-BF534

ADSP-BF536

ADSP-BF537

Ethernet MAC — 1 1

CAN 1 1 1

TWI 1 1 1

SPORTs 2 2 2

UARTs 2 2 2

SPI 1 1 1

GP Timers 8 8 8

Watchdog Timers 1 1 1

RTC 1 1 1

Parallel Peripheral Interface 1 1 1

GPIOs 48 48 48

Memory

Configuration

L1 Instruction

SRAM/Cache

16K bytes 16K bytes 16K bytes

L1 Instruction

SRAM

48K bytes 48K bytes 48K bytes

L1 Data

SRAM/Cache

32K bytes 32K bytes 32K bytes

L1 Data SRAM 32K bytes — 32K bytes

L1 Scratchpad 4K bytes 4K bytes 4K bytes

L3 Boot ROM 2K bytes 2K bytes 2K bytes

Maximum Speed Grade 500 MHz 400 MHz 600 MHz

Package Options:

CSP_BGA

208-Ball

182-Ball

208-Ball

182-Ball

208-Ball

182-Ball

Rev. I | Page 4 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

BLACKFIN PROCESSOR CORE

As shown in Figure 2, the Blackfin processor core contains two

16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,

four video ALUs, and a 40-bit shifter. The computation units

process 8-, 16-, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

operands for compute operations come from the multiported

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation

are supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2

multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations,

16-bit and 8-bit adds with clipping, 8-bit average operations,

and 8-bit subtract/absolute value/accumulate (SAA) operations.

Also provided are the compare/select and vector search

instructions.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If the second ALU is used,

quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates, and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

Figure 2. Blackfin Processor Core

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

16 16

8888

40 40

A0 A1

BARREL

SHIFTER

DATA ARITHMETIC UNIT

CONTROL

UNIT

R7.H

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

ASTAT

40 40

32 32

32LD0

LD1

DAG0

DAG1

ADDRESS ARITHMETIC UNIT

DA1

DA0

PREG

RAB

TO MEMORY

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 5 of 68 | July 2010

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors view

memory as a single unified 4G byte address space, using 32-bit

addresses. All resources, including internal memory, external

memory, and I/O control registers, occupy separate sections of

this common address space. The memory portions of this

address space are arranged in a hierarchical structure to provide

a good cost/performance balance of some very fast, low latency

on-chip memory as cache or SRAM, and larger, lower cost, and

performance off-chip memory systems. (See Figure 3).

The on-chip L1 memory system is the highest performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the external bus interface unit

(EBIU), provides expansion with SDRAM, flash memory, and

SRAM, optionally accessing up to 516M bytes of

physical memory.

The memory DMA controller provides high bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal memory and the external

memory spaces.

Internal (On-Chip) Memory

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have

three blocks of on-chip memory providing high-bandwidth

access to the core.

The first block is the L1 instruction memory, consisting of

64K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

The second on-chip memory block is the L1 data memory, con-

sisting of up to two banks of up to 32K bytes each. Each memory

bank is configurable, offering both cache and SRAM functional-

ity. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM, which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM, and cannot be configured as cache memory.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory

devices including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

The PC133-compliant SDRAM controller can be programmed

to interface to up to 128M bytes of SDRAM. A separate row can

be open for each SDRAM internal bank, and the SDRAM con-

troller supports up to 4 internal SDRAM banks, improving

overall performance.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks are only contiguous if each is fully populated

with 1M byte of memory.

I/O Memory Space

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors do

not define a separate I/O space. All resources are mapped

through the flat 32-bit address space. On-chip I/O devices have

their control registers mapped into memory-mapped registers

(MMRs) at addresses near the top of the 4G byte address space.

These are separated into two smaller blocks, one which contains

the control MMRs for all core functions, and the other which

contains the registers needed for setup and control of the on-

chip peripherals outside of the core. The MMRs are accessible

only in supervisor mode and appear as reserved space to on-

chip peripherals.

Rev. I | Page 6 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Booting

The Blackfin processor contains a small on-chip boot kernel,

which configures the appropriate peripheral for booting. If the

Blackfin processor is configured to boot from boot ROM mem-

ory space, the processor starts executing from the on-chip boot

ROM. For more information, see Booting Modes on Page 16.

Event Handling

The event controller on the Blackfin processor handles all asyn-

chronous and synchronous events to the processor. The

Blackfin processor provides event handling that supports both

nesting and prioritization. Nesting allows multiple event service

routines to be active simultaneously. Prioritization ensures that

servicing of a higher priority event takes precedence over servic-

ing of a lower priority event. The controller provides support for

five different types of events:

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

• Nonmaskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

• Exceptions – Events that occur synchronously to program

flow (in other words, the exception is taken before the

instruction is allowed to complete). Conditions such as

data alignment violations and undefined instructions cause

exceptions.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

The Blackfin processor event controller consists of two stages:

the core event controller (CEC) and the system interrupt con-

troller (SIC). The core event controller works with the system

interrupt controller to prioritize and control all system events.

Figure 3. ADSP-BF534/ADSP-BF536/ADSP-BF537 Memory Maps

RESERVED

CORE MMR REGISTERS (2M BYTES)

RESERVED

SCRATCHPAD SRAM (4K BYTES)

INSTRUCTION BANK B SRAM (16K BYTES)

SYSTEM MMR REGISTERS (2M BYTES)

RESERVED

DATA BANK B SRAM/CACHE (16K BYTES)

DATA BANK B SRAM (16K BYTES)

DATA BANK A SRAM/CACHE (16K BYTES)

ASYNC MEMORY BANK 3 (1M BYTES)

ASYNC MEMORY BANK 2 (1M BYTES)

ASYNC MEMORY BANK 1 (1M BYTES)

ASYNC MEMORY BANK 0 (1M BYTES)

SDRAM MEMORY (16M BYTES TO 512M BYTES)

INSTRUCTION SRAM/CACHE (16K BYTES)

INTERNAL MEMORY MAP

EXTERNALMEMORYM

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0xEF00 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

DATA BANK A SRAM (16K BYTES)

0xFF90 0000

0xFF80 0000

RESERVED

0xFFA0 C000

0xFFA0 8000

INSTRUCTION BANK A SRAM (32K BYTES)

RESERVED

BOOT ROM (2K BYTES)

0xEF00 0800

ADSP-BF534/ADSP-BF537 MEMORY MAP

RESERVED

CORE MMR REGISTERS (2M BYTES)

RESERVED

SCRATCHPAD SRAM (4K BYTES)

INSTRUCTION BANK B SRAM (16K BYTES)

SYSTEM MMR REGISTERS (2M BYTES)

RESERVED

DATA BANK B SRAM/CACHE (16K BYTES)

DATA BANK A SRAM/CACHE (16K BYTES)

ASYNC MEMORY BANK 3 (1M BYTES)

ASYNC MEMORY BANK 2 (1M BYTES)

ASYNC MEMORY BANK 1 (1M BYTES)

ASYNCMEMORYBANK0(1MBYTES)

SDRAM MEMORY (16M BYTES TO 512M BYTES)

INSTRUCTION SRAM/CACHE (16K BYTES)

INTERNALMEMORYMAP

EXTERNAL MEMORYMAP

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0xEF00 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

0xFF90 0000

0xFF80 0000

RESERVED

0xFFA0 C000

0xFFA0 8000

INSTRUCTION BANK A SRAM (32K BYTES)

RESERVED

BOOT ROM (2K BYTES)

0xEF00 0800

ADSP-BF536 MEMORY MAP

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 7 of 68 | July 2010

Conceptually, interrupts from the peripherals enter into the

SIC, and are then routed directly into the general-purpose inter-

rupts of the CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest priority

interrupts (IVG15–14) are recommended to be reserved for

software interrupt handlers, leaving seven prioritized interrupt

inputs to support the peripherals of the Blackfin processor.

Table 2 describes the inputs to the CEC, identifies their names

in the event vector table (EVT), and lists their priorities.

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Although the processor provides a default mapping, the user

can alter the mappings and priorities of interrupt events by writ-

ing the appropriate values into the interrupt assignment

registers (IAR). Table 3 describes the inputs into the SIC and the

default mappings into the CEC.

Table 2. Core Event Controller (CEC)

Priority

(0 Is Highest) Event Class EVT Entry

0Emulation/Test ControlEMU

1Reset RST

2 Nonmaskable Interrupt NMI

3Exception EVX

4Reserved —

5 Hardware Error IVHW

6 Core Timer IVTMR

7 General-Purpose Interrupt 7 IVG7

8 General-Purpose Interrupt 8 IVG8

9 General-Purpose Interrupt 9 IVG9

10 General-Purpose Interrupt 10 IVG10

11 General-Purpose Interrupt 11 IVG11

12 General-Purpose Interrupt 12 IVG12

13 General-Purpose Interrupt 13 IVG13

14 General-Purpose Interrupt 14 IVG14

15 General-Purpose Interrupt 15 IVG15

Table 3. System Interrupt Controller (SIC)

Peripheral Interrupt Event

Default

Mapping

Peripheral

Interrupt ID

PLL Wakeup IVG7 0

DMA Error (Generic) IVG7 1

DMAR0 Block Interrupt IVG7 1

DMAR1 Block Interrupt IVG7 1

DMAR0 Overflow Error IVG7 1

DMAR1 Overflow Error IVG7 1

CAN Error IVG7 2

Ethernet Error (ADSP-BF536 and

ADSP-BF537 only)

IVG7 2

SPORT 0 Error IVG7 2

SPORT 1 Error IVG7 2

PPI Error IVG7 2

SPI Error IVG7 2

UART0 Error IVG7 2

UART1 Error IVG7 2

Real-Time Clock IVG8 3

DMA Channel 0 (PPI) IVG8 4

DMA Channel 3 (SPORT 0 Rx) IVG9 5

DMA Channel 4 (SPORT 0 Tx) IVG9 6

DMA Channel 5 (SPORT 1 Rx) IVG9 7

DMA Channel 6 (SPORT 1 Tx) IVG9 8

TWI IVG10 9

DMA Channel 7 (SPI) IVG10 10

DMA Channel 8 (UART0 Rx) IVG10 11

DMA Channel 9 (UART0 Tx) IVG10 12

DMA Channel 10 (UART1 Rx) IVG10 13

DMA Channel 11 (UART1 Tx) IVG10 14

CAN Rx IVG11 15

CAN Tx IVG11 16

DMA Channel 1 (Ethernet Rx,

ADSP-BF536 and ADSP-BF537 only)

IVG11 17

Port H Interrupt A IVG11 17

DMA Channel 2 (Ethernet Tx,

ADSP-BF536 and ADSP-BF537 only)

IVG11 18

Port H Interrupt B IVG11 18

Timer 0 IVG12 19

Timer 1 IVG12 20

Timer 2 IVG12 21

Timer 3 IVG12 22

Timer 4 IVG12 23

Timer 5 IVG12 24

Timer 6 IVG12 25

Timer 7 IVG12 26

Port F, G Interrupt A IVG12 27

Port G Interrupt B IVG12 28

Rev. I | Page 8 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Event Control

The Blackfin processor provides a very flexible mechanism to

control the processing of events. In the CEC, three registers are

used to coordinate and control events. Each register is

32 bits wide:

• CEC interrupt latch register (ILAT) – Indicates when

events have been latched. The appropriate bit is set when

the processor has latched the event and cleared when the

event has been accepted into the system. This register is

updated automatically by the controller, but it can be writ-

ten only when its corresponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK) – Controls the

masking and unmasking of individual events. When a bit is

set in the IMASK register, that event is unmasked and is

processed by the CEC when asserted. A cleared bit in the

IMASK register masks the event, preventing the processor

from servicing the event even though the event may be

latched in the ILAT register. This register can be read or

written while in supervisor mode. (Note that general-pur-

pose interrupts can be globally enabled and disabled with

the STI and CLI instructions, respectively.)

• CEC interrupt pending register (IPEND) – The IPEND

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but can be read while in supervisor mode.

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 3 on Page 7.

• SIC interrupt mask register (SIC_IMASK) – Controls the

masking and unmasking of each peripheral interrupt event.

When a bit is set in the register, that peripheral event is

unmasked and is processed by the system when asserted. A

cleared bit in the register masks the peripheral event, pre-

venting the processor from servicing the event.

• SIC interrupt status register (SIC_ISR) – As multiple

peripherals can be mapped to a single event, this register

allows the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

• SIC interrupt wake-up enable register (SIC_IWR) – By

enabling the corresponding bit in this register, a peripheral

can be configured to wake up the processor, should the

core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 13.)

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC recognizes and queues the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

DMA CONTROLLERS

The Blackfin processors have multiple, independent DMA

channels that support automated data transfers with minimal

overhead for the processor core. DMA transfers can occur

between the processor’s internal memories and any of its DMA-

capable peripherals. Additionally, DMA transfers can be accom-

plished between any of the DMA-capable peripherals and

external devices connected to the external memory interfaces,

including the SDRAM controller and the asynchronous mem-

ory controller. DMA-capable peripherals include the Ethernet

MAC (ADSP-BF536 and ADSP-BF537 only), SPORTs, SPI port,

UARTs, and PPI. Each individual DMA-capable peripheral has

at least one dedicated DMA channel.

The DMA controller supports both one-dimensional (1-D) and

two-dimensional (2-D) DMA transfers. DMA transfer initial-

ization can be implemented from registers or from sets of

parameters called descriptor blocks.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to ±32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

Examples of DMA types supported by the DMA controller

include

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page.

DMA Channels 12 and 13

(Memory DMA Stream 0)

IVG13 29

DMA Channels 14 and 15

(Memory DMA Stream 1)

IVG13 30

Software Watchdog Timer IVG13 31

Port F Interrupt B IVG13 31

Table 3. System Interrupt Controller (SIC) (Continued)

Peripheral Interrupt Event

Default

Mapping

Peripheral

Interrupt ID

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 9 of 68 | July 2010

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels provided for transfers between the

various memories of the processor system. This enables trans-

fers of blocks of data between any of the memories—including

external SDRAM, ROM, SRAM, and flash memory—with mini-

mal processor intervention. Memory DMA transfers can be

controlled by a very flexible descriptor-based methodology or

by a standard register-based autobuffer mechanism.

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors also

have an external DMA controller capability via dual external

DMA request pins when used in conjunction with the external

bus interface unit (EBIU). This functionality can be used when a

high speed interface is required for external FIFOs and high

bandwidth communications peripherals such as USB 2.0. It

allows control of the number of data transfers for memDMA.

The number of transfers per edge is programmable. This feature

can be programmed to allow memDMA to have an increased

priority on the external bus relative to the core.

REAL-TIME CLOCK

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the

processor. The RTC peripheral has dedicated power supply pins

so that it can remain powered up and clocked even when the

rest of the processor is in a low power state. The RTC provides

several programmable interrupt options, including interrupt

per second, minute, hour, or day clock ticks, interrupt on pro-

grammable stopwatch countdown, or interrupt at a

programmed alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day, while the second alarm is for a day and time of

that day.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch is

enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the processor

from sleep mode upon generation of any RTC wake-up event.

Additionally, an RTC wake-up event can wake up the processor

from deep sleep mode, and wake up the on-chip internal voltage

regulator from the hibernate operating mode.

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 4.

WATCHDOG TIMER

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors

include a 32-bit timer that can be used to implement a software

watchdog function. A software watchdog can improve system

availability by forcing the processor to a known state through

generation of a system reset, nonmaskable interrupt (NMI), or

general-purpose interrupt, if the timer expires before being reset

by software. The programmer initializes the count value of the

timer, enables the appropriate interrupt, then enables the timer.

Thereafter, the software must reload the counter before it

counts to zero from the programmed value. This protects the

system from remaining in an unknown state where software,

which would normally reset the timer, has stopped running due

to an external noise condition or software error.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the processor peripherals. After a reset,

software can determine if the watchdog was the source of the

hardware reset by interrogating a status bit in the watchdog

timer control register.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f

SCLK

TIMERS

There are nine general-purpose programmable timer units in

the processor. Eight timers have an external pin that can be con-

figured either as a pulse-width modulator (PWM) or timer

output, as an input to clock the timer, or as a mechanism for

measuring pulse widths and periods of external events. These

timers can be synchronized to an external clock input to the sev-

eral other associated PF pins, to an external clock input to the

PPI_CLK input pin, or to the internal SCLK.

The timer units can be used in conjunction with the two UARTs

and the CAN controller to measure the width of the pulses in

the data stream to provide a software auto-baud detect function

for the respective serial channels.

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

In addition to the eight general-purpose programmable timers,

a ninth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generating periodic interrupts in an operating system.

Figure 4. External Components for RTC

RTXO

C1 C2

SUGGESTED COMPONENTS:

X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR

EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)

C1 = 22 pF

C2 = 22 pF

R1 = 10 M

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

RTXI

Rev. I | Page 10 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

SERIAL PORTS (SPORTs)

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors

incorporate two dual-channel synchronous serial ports

(SPORT0 and SPORT1) for serial and multiprocessor commu-

nications. The SPORTs support the following features:

•I

S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I

S stereo audio.

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f

SCLK

/131,070) Hz to (f

SCLK

/2) Hz.

• Word length – Each SPORT supports serial data words

from 3 bits to 32 bits in length, transferred most significant

bit first or least significant bit first.

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

• Companding in hardware – Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without additional

latencies.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer, or buffers,

through DMA.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have

an SPI-compatible port that enables the processor to communi-

cate with multiple SPI-compatible devices.

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSI, and Master Input-

Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI

chip select input pin (SPISS) lets other SPI devices select the

processor, and seven SPI chip select output pins (SPISEL7–1) let

the processor select other SPI devices. The SPI select pins are

reconfigured programmable flag pins. Using these pins, the SPI

port provides a full-duplex, synchronous serial interface, which

supports both master/slave modes and multimaster

environments.

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA controller,

configurable to support transmit or receive data streams. The

SPI’s DMA controller can only service unidirectional accesses at

any given time.

The SPI port’s clock rate is calculated as:

where the 16-bit SPI_BAUD register contains a value of 2

to 65,535.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

UART PORTS

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-

vide two full-duplex universal asynchronous receiver and

transmitter (UART) ports, which are fully compatible with PC-

standard UARTs. Each UART port provides a simplified UART

interface to other peripherals or hosts, supporting full-duplex,

DMA-supported, asynchronous transfers of serial data. A

UART port includes support for five to eight data bits, one or

two stop bits, and none, even, or odd parity. Each UART port

supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

Each UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f

SCLK

/1,048,576) to

SCLK

/16) bits per second.

• Supporting data formats from 7 bits to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

where the 16-bit UARTx_Divisor comes from the UARTx_DLH

significant 8 bits).

SPI Clock Rate fSCLK

2SPI_BAUD×

------------------------------------

UART Clock Rate fSCLK

16 UARTx_Divisor×

--------------------------------------------------

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 11 of 68 | July 2010

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

The capabilities of the UARTs are further extended with sup-

port for the infrared data association (IrDA

) serial infrared

physical layer link specification (SIR) protocol.

CONTROLLER AREA NETWORK (CAN)

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors offer

a CAN controller that is a communication controller imple-

menting the CAN 2.0B (active) protocol. This protocol is an

asynchronous communications protocol used in both industrial

and automotive control systems. The CAN protocol is well-

suited for control applications due to its capability to communi-

cate reliably over a network, since the protocol incorporates

CRC checking message error tracking, and fault node

confinement.

The CAN controller offers the following features:

• 32 mailboxes (eight receive only, eight transmit only, 16

configurable for receive or transmit).

• Dedicated acceptance masks for each mailbox.

• Additional data filtering on first two bytes.

• Support for both the standard (11-bit) and extended

(29-bit) identifier (ID) message formats.

• Support for remote frames.

• Active or passive network support.

• CAN wake-up from hibernation mode (lowest static power

consumption mode).

• Interrupts, including: Tx complete, Rx complete, error,

global.

The electrical characteristics of each network connection are

very demanding so the CAN interface is typically divided into

two parts: a controller and a transceiver. This allows a single

controller to support different drivers and CAN networks. The

CAN module represents only the controller part of the interface.

The controller interface supports connection to 3.3 V high-

speed, fault-tolerant, single-wire transceivers.

TWI CONTROLLER INTERFACE

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors

include a 2-wire interface (TWI) module for providing a simple

exchange method of control data between multiple devices. The

TWI is compatible with the widely used I

bus standard. The

TWI module offers the capabilities of simultaneous master and

slave operation, support for both 7-bit addressing and multime-

dia data arbitration. The TWI interface utilizes two pins for

transferring clock (SCL) and data (SDA) and supports the

protocol at speeds up to 400 kbps. The TWI interface pins are

compatible with 5 V logic levels.

Additionally, the processor’s TWI module is fully compatible

with serial camera control bus (SCCB) functionality for easier

control of various CMOS camera sensor devices.

10/100 ETHERNET MAC

The ADSP-BF536 and ADSP-BF537 processors offer the capa-

bility to directly connect to a network by way of an embedded

fast Ethernet Media Access Controller (MAC) that supports

both 10-BaseT (10 Mbps) and 100-BaseT (100 Mbps) operation.

The 10/100 Ethernet MAC peripheral is fully compliant to the

IEEE 802.3-2002 standard, and it provides programmable fea-

tures designed to minimize supervision, bus use, or message

processing by the rest of the processor system.

Some standard features are

• Support of MII and RMII protocols for external PHYs.

• Full duplex and half duplex modes.

• Data framing and encapsulation: generation and detection

of preamble, length padding, and FCS.

• Media access management (in half-duplex operation): col-

lision and contention handling, including control of

retransmission of collision frames and of back-off timing.

• Flow control (in full-duplex operation): generation and

detection of PAUSE frames.

• Station management: generation of MDC/MDIO frames

for read-write access to PHY registers.

• SCLK operating range down to 25 MHz (active and sleep

operating modes).

• Internal loopback from Tx to Rx.

Some advanced features are

• Buffered crystal output to external PHY for support of a

single crystal system.

• Automatic checksum computation of IP header and IP

payload fields of Rx frames.

• Independent 32-bit descriptor-driven Rx and Tx DMA

channels.

• Frame status delivery to memory via DMA, including

frame completion semaphores, for efficient buffer queue

management in software.

• Tx DMA support for separate descriptors for MAC header

and payload to eliminate buffer copy operations.

• Convenient frame alignment modes support even 32-bit

alignment of encapsulated Rx or Tx IP packet data in mem-

ory after the 14-byte MAC header.

• Programmable Ethernet event interrupt supports any com-

bination of

• Any selected Rx or Tx frame status conditions.

• PHY interrupt condition.

• Wake-up frame detected.

• Any selected MAC management counter(s) at

half-full.

• DMA descriptor error.

• 47 MAC management statistics counters with selectable

clear-on-read behavior and programmable interrupts on

half maximum value.

Rev. I | Page 12 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

• Programmable Rx address filters, including a 64-bit

address hash table for multicast and/or unicast frames, and

programmable filter modes for broadcast, multicast, uni-

cast, control, and damaged frames.

• Advanced power management supporting unattended

transfer of Rx and Tx frames and status to/from external

memory via DMA during low power sleep mode.

• System wake-up from sleep operating mode upon magic

packet or any of four user-definable wake-up frame filters.

• Support for 802.3Q tagged VLAN frames.

•Programmable MDC clock rate and preamble suppression.

• In RMII operation, 7 unused pins can be configured as

GPIO pins for other purposes.

PORTS

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors

group the many peripheral signals to four ports—Port F, Port G,

Port H, and Port J. Most of the associated pins are shared by

multiple signals. The ports function as multiplexer controls.

Eight of the pins (Port F7–0) offer high source/high sink current

capabilities.

General-Purpose I/O (GPIO)

The processors have 48 bidirectional, general-purpose I/O

(GPIO) pins allocated across three separate GPIO modules—

PORTFIO, PORTGIO, and PORTHIO, associated with Port F,

Port G, and Port H, respectively. Port J does not provide GPIO

functionality. Each GPIO-capable pin shares functionality with

other processor peripherals via a multiplexing scheme; however,

the GPIO functionality is the default state of the device upon

power-up. Neither GPIO output or input drivers are active by

default. Each general-purpose port pin can be individually con-

trolled by manipulation of the port control, status, and interrupt

registers:

• GPIO direction control register – Specifies the direction of

each individual GPIO pin as input or output.

• GPIO control and status registers – The processors employ

a “write one to modify” mechanism that allows any combi-

nation of individual GPIO pins to be modified in a single

instruction, without affecting the level of any other GPIO

pins. Four control registers are provided. One register is

written in order to set pin values, one register is written in

order to clear pin values, one register is written in order to

toggle pin values, and one register is written in order to

specify a pin value. Reading the GPIO status register allows

software to interrogate the sense of the pins.

• GPIO interrupt mask registers – The two GPIO interrupt

mask registers allow each individual GPIO pin to function

as an interrupt to the processor. Similar to the two GPIO

control registers that are used to set and clear individual

pin values, one GPIO interrupt mask register sets bits to

enable interrupt function, and the other GPIO interrupt

mask register clears bits to disable interrupt function.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO inter-

rupt sensitivity registers specify whether individual pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

PARALLEL PERIPHERAL INTERFACE (PPI)

The processor provides a parallel peripheral interface (PPI) that

can connect directly to parallel ADC and DAC converters, video

encoders and decoders, and other general-purpose peripherals.

The PPI consists of a dedicated input clock pin, up to three

frame synchronization pins, and up to 16 data pins. The input

clock supports parallel data rates up to half the system clock rate

and the synchronization signals can be configured as either

inputs or outputs.

The PPI supports a variety of general-purpose and ITU-R 656

modes of operation. In general-purpose mode, the PPI provides

half-duplex, bidirectional data transfer with up to 16 bits of

data. Up to three frame synchronization signals are also pro-

vided. In ITU-R 656 mode, the PPI provides half-duplex

bidirectional transfer of 8- or 10-bit video data. Additionally,

on-chip decode of embedded start-of-line (SOL) and start-of-

field (SOF) preamble packets is supported.

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

1. Input mode – Frame syncs and data are inputs into the PPI.

2. Frame capture mode – Frame syncs are outputs from the

PPI, but data are inputs.

3. Output mode – Frame syncs and data are outputs from the

PPI.

Input Mode

Input mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_COUNT register. The PPI supports 8-bit and 10-bit

through 16-bit data, programmable in the PPI_CONTROL

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 13 of 68 | July 2010

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave

(for frame capture for example). The ADSP-BF534/

ADSP-BF536/ADSP-BF537 processors control when to read

from the video source(s). PPI_FS1 is an HSYNC output and

PPI_FS2 is a VSYNC output.

Output Mode

Output mode is used for transmitting video or other data with

up to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

1. Active video only mode

2. Vertical blanking only mode

3. Entire field mode

Active Video Mode

Active video only mode is used when only the active video por-

tion of a field is of interest and not any of the blanking intervals.

The PPI does not read in any data between the end of active

video (EAV) and start of active video (SAV) preamble symbols,

or any data present during the vertical blanking intervals. In this

mode, the control byte sequences are not stored to memory;

they are filtered by the PPI. After synchronizing to the start of

Field 1, the PPI ignores incoming samples until it sees an SAV

code. The user specifies the number of active video lines per

frame (in PPI_COUNT register).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1. Data is transferred to or from the

synchronous channels through eight DMA engines that work

autonomously from the processor core.

DYNAMIC POWER MANAGEMENT

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-

vide five operating modes, each with a different performance

and power profile. In addition, dynamic power management

provides the control functions to dynamically alter the proces-

sor core supply voltage, further reducing power dissipation.

Control of clocking to each of the peripherals also reduces

power consumption. See Table 4 for a summary of the power

settings for each mode. Also, see Table 16, Table 15 and

Table 17.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

Active Operating Mode—Moderate Dynamic Power

Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. In this

mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the full-on mode is

entered. DMA access is available to appropriately configured

L1 memories.

In the active mode, it is possible to disable the PLL through the

PLL control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the full-on or sleep modes.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally an external event or RTC activity wakes up the processor.

When in the sleep mode, asserting wake-up causes the processor

to sense the value of the BYPASS bit in the PLL control register

(PLL_CTL). If BYPASS is disabled, the processor transitions to

the full on mode. If BYPASS is enabled, the processor transi-

tions to the active mode.

System DMA access to L1 memory is not supported in

sleep mode.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals,

such as the RTC, may still be running but cannot access internal

resources or external memory. This powered-down mode can

only be exited by assertion of the reset interrupt (RESET) or by

an asynchronous interrupt generated by the RTC. When in deep

sleep mode, an RTC asynchronous interrupt causes the

Table 4. Power Settings

Mode PLL

PLL

Bypassed

Core

Clock

(CCLK)

System

Clock

(SCLK)

Internal

Power

DDINT

)

Full On Enabled No Enabled Enabled On

Active Enabled/

Disabled

Yes Enabled Enabled On

Sleep Enabled — Disabled Enabled On

Deep

Sleep

Disabled — Disabled Disabled On

Hibernate Disabled — Disabled Disabled Off

Rev. I | Page 14 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

processor to transition to the active mode. Assertion of RESET

while in deep sleep mode causes the processor to transition to

the full-on mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all of

the synchronous peripherals (SCLK). The internal voltage regu-

lator for the processor can be shut off by writing b#00 to the

FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V

DDINT

) to 0 V to provide the greatest power savings. To

preserve the processor state, prior to removing power, any criti-

cal information stored internally (memory contents, register

contents, etc.) must be written to a nonvolatile storage device.

Since V

DDEXT

is still supplied in this state, all of the external pins

three-state, unless otherwise specified. This allows other devices

that are connected to the processor to still have power applied

without drawing unwanted current.

The Ethernet or CAN modules can wake up the internal supply

regulator. If the PH6 pin does not connect as the PHYINT sig-

nal to an external PHY device, it can be pulled low by any other

device to wake the processor up. The regulator can also be

woken up by a real-time clock wake-up event or by asserting the

RESET pin. All hibernate wake-up events initiate the hardware

reset sequence. Individual sources are enabled by the VR_CTL

With the exception of the VR_CTL and the RTC registers, all

internal registers and memories lose their content in the hiber-

nate state. State variables can be held in external SRAM or

SDRAM. The SCKELOW bit in the VR_CTL register provides a

means of waking from hibernate state without disrupting a self-

refreshing SDRAM, provided that there is also an external pull-

down on the SCKE pin.

Power Savings

As shown in Table 5, the processors support three different

power domains which maximizes flexibility, while maintaining

compliance with industry standards and conventions. By isolat-

ing the internal logic of the processor into its own power

domain, separate from the RTC and other I/O, the processor

can take advantage of dynamic power management, without

affecting the RTC or other I/O devices. There are no sequencing

requirements for the various power domains.

The dynamic power management feature allows both the pro-

cessor’s input voltage (V

DDINT

) and clock frequency (f

CCLK

) to be

dynamically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in power dissipation, while reducing the voltage by

25% reduces power dissipation by more than 40%. Further,

these power savings are additive, in that if the clock frequency

and supply voltage are both reduced, the power savings can be

dramatic, as shown in the following equations.

The power savings factor (PSF) is calculated as:

where:

CCLKNOM

is the nominal core clock frequency

CCLKRED

is the reduced core clock frequency

DDINTNOM

is the nominal internal supply voltage

DDINTRED

is the reduced internal supply voltage

NOM

is the duration running at f

CCLKNOM

RED

is the duration running at f

CCLKRED

The percent power savings is calculated as

VOLTAGE REGULATION

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-

vide an on-chip voltage regulator that can generate appropriate

DDINT

voltage levels from the V

DDEXT

supply. See Operating

Conditions on Page 24 for regulator tolerances and acceptable

DDEXT

ranges for specific models.

Table 5. Power Domains

Power Domain V

Range

All internal logic, except RTC V

DDINT

RTC internal logic and crystal I/O V

DDRTC

All other I/O V

DDEXT

Figure 5. Voltage Regulator Circuit

PSF fCCLKRED

fCCLKNOM

--------------------- VDDINTRED

VDDINTNOM

--------------------------





×tRED

tNOM

-----------





×



% power savings 1PSF–()100%×=

DDEXT

(LOW-INDUCTANCE)

DDINT

OUT

100μF

OUT

GND

SHORT AND LOW-

INDUCTANCE WIRE

DDEXT

100μF

10μF

LOW ESR

100nF

SET OF DECOUPLING

CAPACITORS

FDS9431A

ZHCS1000

NOTE: DESIGNER SHOULD MINIMIZE

TRACE LENGTH TO FDS9431A.

10μH

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 15 of 68 | July 2010

Figure 5 shows the typical external components required to

complete the power management system. The regulator con-

trols the internal logic voltage levels and is programmable with

the voltage regulator control register (VR_CTL) in increments

of 50 mV. To reduce standby power consumption, the internal

voltage regulator can be programmed to remove power to the

processor core while keeping I/O power supplied. While in

hibernate state, V

DDEXT

can still be applied, eliminating the need

for external buffers. The voltage regulator can be activated from

this power-down state by asserting the RESET pin, which then

initiates a boot sequence. The regulator can also be disabled and

bypassed at the user’s discretion. For additional information on

voltage regulation, see Switching Regulator Design Consider-

ations for the ADSP-BF533 Blackfin Processors (EE-228).

CLOCK SIGNALS

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors can

be clocked by an external crystal, a sine wave input, or a buff-

ered, shaped clock derived from an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Alternatively, because the processors include an on-chip oscilla-

tor circuit, an external crystal can be used. For fundamental

frequency operation, use the circuit shown in Figure 6. A

parallel-resonant, fundamental frequency, microprocessor-

grade crystal is connected across the CLKIN and XTAL pins.

The on-chip resistance between CLKIN and the XTAL pin is in

the 500 kΩ range. Further parallel resistors are typically not rec-

ommended. The two capacitors and the series resistor shown in

Figure 6 fine-tune phase and amplitude of the sine frequency.

The capacitor and resistor values shown in Figure 6 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations of multiple

devices over temperature range.

A third-overtone crystal can be used for frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 6. A design procedure for third-overtone oper-

ation is discussed in detail in the application note Using Third

Overtone Crystals with the ADSP-218x DSP (EE-168).

The CLKBUF pin is an output pin, and is a buffer version of the

input clock. This pin is particularly useful in Ethernet applica-

tions to limit the number of required clock sources in the

system. In this type of application, a single 25 MHz or 50 MHz

crystal can be applied directly to the processors. The 25 MHz or

50 MHz output of CLKBUF can then be connected to an exter-

nal Ethernet MII or RMII PHY device.

Because of the default 10× PLL multiplier, providing a 50 MHz

CLKIN exceeds the recommended operating conditions of the

lower speed grades. Because of this restriction, an RMII PHY

requiring a 50 MHz clock input cannot be clocked directly from

the CLKBUF pin for the lower speed grades. In this case, either

provide a separate 50 MHz clock source, or use an RMII PHY

with 25 MHz clock input options. The CLKBUF output is active

by default and can be disabled using the VR_CTL register for

power savings.

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 7, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable 0.5× to 64× multiplication

factor (bounded by specified minimum and maximum VCO

frequencies). The default multiplier is 10×, but it can be modi-

fied by a software instruction sequence in the PLL_CTL register.

On-the-fly CCLK and SCLK frequency changes can be effected

by simply writing to the PLL_DIV register. Whereas the maxi-

mum allowed CCLK and SCLK rates depend on the applied

voltages V

DDINT

and V

DDEXT

, the VCO is always permitted to run

up to the frequency specified by the part’s speed grade. The

CLKOUT pin reflects the SCLK frequency to the off-chip world.

It belongs to the SDRAM interface, but it functions as a refer-

Figure 6. External Crystal Connections

Figure 7. Frequency Modification Methods

CLKIN

CLKOUT

XTAL

CLKBUF

TO PLL CIRCUITRY

FOR OVERTONE

OPERATION ONLY:

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY.

18 pF *

330 *

BLACKFIN

350

1M

VDDEXT

PLL

0.5to 64

÷1to15

÷1,2,4,8

VCO

CLKIN

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

CCLK

SCLK

SCLK CCLK

SCLK 133 MHz

Rev. I | Page 16 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

ence signal in other timing specifications as well. While active

by default, it can be disabled using the EBIU_SDGCTL and

EBIU_AMGCTL registers.

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f

SCLK

. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

The maximum CCLK frequency not only depends on the part’s

speed grade (see Ordering Guide on Page 68), it also depends on

the applied V

DDINT

voltage (see Table 10, Table 11, and Table 12

on Page 25 for details). The maximal system clock rate (SCLK)

depends on the chip package and the applied V

DDEXT

voltage (see

Table 14 on Page 25).

BOOTING MODES

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor has six

mechanisms (listed in Table 8) for automatically loading inter-

nal and external memory after a reset. A seventh mode is

provided to execute from external memory, bypassing the boot

sequence.

The BMODE pins of the reset configuration register, sampled

during power-on resets and software-initiated resets, imple-

ment the following modes:

• Execute from 16-bit external memory – Execution starts

from address 0x2000 0000 with 16-bit packing. The boot

ROM is bypassed in this mode. All configuration settings

are set for the slowest device possible (3-cycle hold time;

15-cycle R/W access times; 4-cycle setup).

• Boot from 8-bit and 16-bit external flash memory – The

8-bit or 16-bit flash boot routine located in Boot ROM

memory space is set up using asynchronous memory

bank 0. All configuration settings are set for the slowest

device possible (3-cycle hold time; 15-cycle R/W access

times; 4-cycle setup). The Boot ROM evaluates the first

byte of the boot stream at address 0x2000 0000. If it is 0x40,

8-bit boot is performed. A 0x60 byte assumes a 16-bit

memory device and performs 8-bit DMA. A 0x20 byte also

assumes 16-bit memory but performs 16-bit DMA.

• Boot from serial SPI memory (EEPROM or flash) – 8-, 16-,

or 24-bit addressable devices are supported as well as

AT45DB041, AT45DB081, AT45DB161, AT45DB321,

AT45DB642, and AT45DB1282 DataFlash

devices from

Atmel. The SPI uses the PF10/SPI SSEL1 output pin to

select a single SPI EEPROM/flash device, submits a read

command and successive address bytes (0x00) until a valid

8-, 16-, or 24-bit, or Atmel addressable device is detected,

and begins clocking data into the processor.

• Boot from SPI host device – The Blackfin processor oper-

ates in SPI slave mode and is configured to receive the bytes

of the .LDR file from an SPI host (master) agent. To hold

off the host device from transmitting while the boot ROM

is busy, the Blackfin processor asserts a GPIO pin, called

host wait (HWAIT), to signal the host device not to send

any more bytes until the flag is deasserted. The flag is cho-

sen by the user and this information is transferred to the

Blackfin processor via bits 10:5 of the FLAG header.

• Boot from UART – Using an autobaud handshake

sequence, a boot-stream-formatted program is downloaded

by the host. The host agent selects a baud rate within the

UART’s clocking capabilities. When performing the auto-

baud, the UART expects an “@” (boot stream) character

Table 6. Example System Clock Ratios

Signal Name

SSEL3–0

Divider Ratio

VCO:SCLK

Example Frequency Ratios

(MHz)

VCO SCLK

0001 1:1 100 100

0110 6:1 300 50

1010 10:1 500 50

Table 7. Core Clock Ratios

Signal Name

CSEL1–0

Divider Ratio

VCO:CCLK

Example Frequency Ratios

(MHz)

VCO CCLK

00 1:1 300 300

01 2:1 300 150

10 4:1 500 125

11 8:1 200 25

Table 8. Booting Modes

BMODE2–0 Description

000 Execute from 16-bit external memory (bypass

boot ROM)

001 Boot from 8-bit or 16-bit memory

(EPROM/flash)

010 Reserved

011 Boot from serial SPI memory (EEPROM/flash)

100 Boot from SPI host (slave mode)

101 Boot from serial TWI memory (EEPROM/flash)

110 Boot from TWI host (slave mode)

111 Boot from UART host (slave mode)

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 17 of 68 | July 2010

(8 bits data, 1 start bit, 1 stop bit, no parity bit) on the RXD

pin to determine the bit rate. It then replies with an

acknowledgement that is composed of 4 bytes: 0xBF, the

value of UART_DLL, the value of UART_DLH, and 0x00.

The host can then download the boot stream. When the

processor needs to hold off the host, it deasserts CTS.

Therefore, the host must monitor this signal.

• Boot from serial TWI memory (EEPROM/flash) – The

Blackfin processor operates in master mode and selects the

TWI slave with the unique ID 0xA0. It submits successive

read commands to the memory device starting at 2-byte

internal address 0x0000 and begins clocking data into the

processor. The TWI memory device should comply with

Philips I

C Bus Specification version 2.1 and have the capa-

bility to auto-increment its internal address counter such

that the contents of the memory device can be read

sequentially.

• Boot from TWI host – The TWI host agent selects the slave

with the unique ID 0x5F. The processor replies with an

acknowledgement and the host can then download the

boot stream. The TWI host agent should comply with

Philips I

C Bus Specification version 2.1. An I

C multi-

plexer can be used to select one processor at a time when

booting multiple processors from a single TWI.

For each of the boot modes, a 10-byte header is first brought in

from an external device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks can be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the start of L1 instruction SRAM.

In addition, Bit 4 of the reset configuration register can be set by

application code to bypass the normal boot sequence during a

software reset. For this case, the processor jumps directly to the

beginning of L1 instruction memory.

To augment the boot modes, a secondary software loader can be

added to provide additional booting mechanisms. This second-

ary loader could provide the capability to boot from flash,

variable baud rate, and other sources. In all boot modes except

bypass, program execution starts from on-chip L1 memory

address 0xFFA0 0000.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the

programmer to use many of the processor core resources in a

single instruction. Coupled with many features more often seen

on microcontrollers, this instruction set is very efficient when

compiling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded

in 16 bits.

DEVELOPMENT TOOLS

Blackfin processors are supported with a complete set of

CROSSCORE

†

software and hardware development tools,

including Analog Devices emulators and the VisualDSP++

‡

development environment. The same emulator hardware that

supports other Analog Devices processors also fully emulates

the Blackfin processor family.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler that is based on an algebraic

syntax, an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ runtime library that includes DSP and mathemati-

cal functions. A key point for these tools is C/C++ code

efficiency. The compiler has been developed for efficient

translation of C/C++ code to Blackfin assembly. The Blackfin

processor has architectural features that improve the efficiency

of compiled C/C++ code.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and

†

CROSSCORE is a registered trademark of Analog Devices, Inc.

‡

VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. I | Page 18 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

efficiently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can

• View mixed C/C++ and assembly code (interleaved source

and object information).

• Insert breakpoints.

• Set conditional breakpoints on registers, memory, and

stacks.

• Trace instruction execution.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

• Create custom debugger windows.

The VisualDSP++ IDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all development tools,

including color syntax highlighting in the VisualDSP++ editor.

These capabilities permit programmers to

• Control how the development tools process inputs and

generate outputs.

• Maintain a one-to-one correspondence with the tool’s

command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of embedded, real-time

programming. These capabilities enable engineers to develop

code more effectively, eliminating the need to start from the

very beginning when developing new application code. The

VDK features include threads, critical and unscheduled regions,

semaphores, events, and device flags. The VDK also supports

priority-based, pre-emptive, cooperative, and time-sliced sched-

uling approaches. In addition, the VDK was designed to be

scalable. If the application does not use a specific feature, the

support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used with standard

command line tools. When the VDK is used, the development

environment assists the developer with many error prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state when debugging an application that uses the VDK.

The expert linker can be used to visually manipulate the place-

ment of code and data in the embedded system. Memory

utilization can be viewed in a color-coded graphical form. Code

and data can be easily moved to different areas of the processor

or external memory with the drag of the mouse. Runtime stack

and heap usage can be examined. The expert linker is fully com-

patible with existing linker definition file (LDF), allowing the

developer to move between the graphical and textual

environments.

Analog Devices emulators use the IEEE 1149.1 JTAG test access

port of the Blackfin to monitor and control the target board

processor during emulation. The emulator provides full-speed

emulation, allowing inspection and modification of memory,

registers, and processor stacks. Nonintrusive in-circuit emula-

tion is assured by the use of the processor’s JTAG interface—the

emulator does not affect target system loading or timing.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the Blackfin processor family. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

EZ-KIT Lite® Evaluation Board

For evaluation of ADSP-BF534/ADSP-BF536/ADSP-BF537

processors, use the ADSP-BF537 EZ-KIT Lite board available

from Analog Devices. Order part number

ADDS-BF537-EZLITE. The board comes with on-chip

emulation capabilities and is equipped to enable software

development. Multiple daughter cards are available.

DESIGNING AN EMULATOR-COMPATIBLE

PROCESSOR BOARD

The Analog Devices family of emulators are tools that every sys-

tem developer needs in order to test and debug hardware and

software systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG processor. The

emulator uses the TAP to access the internal features of the pro-

cessor, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers. The

processor must be halted to send data and commands, but once

an operation has been completed by the emulator, the processor

system is set running at full speed with no impact on

system timing.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see Analog Devices JTAG Emulation Technical Reference

(EE-68) on the Analog Devices website under

www.analog.com/ee-notes. This document is updated regularly

to keep pace with improvements to emulator support.

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 19 of 68 | July 2010

RELATED DOCUMENTS

The following publications that describe the ADSP-BF534/

ADSP-BF536/ADSP-BF537 processors (and related processors)

can be ordered from any Analog Devices sales office or accessed

electronically on our website:

•Getting Started with Blackfin Processors

•ADSP-BF537 Blackfin Processor Hardware Reference

•ADSP-BF53x/ADSP-BF56x Blackfin Processor Program-

ming Reference

•ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Proces-

sor Anomaly List

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the "signal chain" entry in

Wikipedia or the Glossary of EE Terms on the Analog Devices

website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The Application Signal Chains page in the Circuits from the

Lab

site (http://www.analog.com/signalchains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

Rev. I | Page 20 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

PIN DESCRIPTIONS

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pin

definitions are listed in Table 9. In order to maintain maximum

functionality and reduce package size and pin count, some pins

have dual, multiplexed functions. In cases where pin function is

reconfigurable, the default state is shown in plain text, while the

alternate function is shown in italics. Pins shown with an aster-

isk after their name (*) offer high source/high sink current

capabilities.

All pins are three-stated during and immediately after reset,

with the exception of the external memory interface, asynchro-

nous and synchronous memory control, and the buffered XTAL

output pin (CLKBUF). On the external memory interface, the

control and address lines are driven high, with the exception of

CLKOUT, which toggles at the system clock rate. If BR is active

(whether or not RESET is asserted), the memory pins are also

three-stated. During hibernate, all outputs are three-stated

unless otherwise noted in Table 9.

All I/O pins have their input buffers disabled with the exception

of the pins noted in the data sheet that need pull-ups or pull-

downs if unused.

The SDA (serial data) and SCL (serial clock) pins are open drain

and therefore require a pull-up resistor. Consult version 2.1 of

the I

C specification for the proper resistor value.

Table 9. Pin Descriptions

Pin Name Type Function

Driver

Type

Memory Interface

ADDR19–1 O Address Bus for Async Access A

DATA15–0 I/O Data Bus for Async/Sync Access A

ABE1–0/SDQM1–0 O Byte Enables/Data Masks for Async/Sync Access A

BR I Bus Request (This pin should be pulled high when not used.)

BG OBus Grant A

BGH O Bus Grant Hang A

Asynchronous Memory Control

AMS3–0 O Bank Select (Require pull-ups if hibernate is used.) A

ARDY I Hardware Ready Control

AOE O Output Enable A

ARE ORead Enable A

AWE OWrite Enable A

Synchronous Memory Control

SRAS O Row Address Strobe A

SCAS O Column Address Strobe A

SWE OWrite Enable A

SCKE O Clock Enable(Requires a pull-down if hibernate with SDRAM self-refresh is

used.)

CLKOUT O Clock Output B

SA10 O A10 Pin A

SMS OBank Select A

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 21 of 68 | July 2010

Port F: GPIO/UART1–0/Timer7–0/SPI/

External DMA Request/PPI

(* = High Source/High Sink Pin)

PF0* – GPIO/UART0 TX/DMAR0 I/O GPIO/UART0 Transmit/DMA Request 0 C

PF1* – GPIO/UART0 RX/DMAR1/TACI1 I/O GPIO/UART0 Receive/DMA Request 1/Timer1 Alternate Input Capture C

PF2* – GPIO/UART1 TX/TMR7 I/O GPIO/UART1 Transmit/Timer7 C

PF3* – GPIO/UART1 RX/TMR6/TACI6 I/O GPIO/UART1 Receive/Timer6/Timer6 Alternate Input Capture C

PF4* – GPIO/TMR5/SPI SSEL6 I/O GPIO/Timer5/SPI Slave Select Enable 6 C

PF5* – GPIO/TMR4/SPI SSEL5 I/O GPIO/Timer4/SPI Slave Select Enable 5 C

PF6* – GPIO/TMR3/SPI SSEL4 I/O GPIO/Timer3/SPI Slave Select Enable 4 C

PF7* – GPIO/TMR2/PPI FS3 I/O GPIO/Timer2/PPI Frame Sync 3 C

PF8 – GPIO/TMR1/PPI FS2 I/O GPIO/Timer1/PPI Frame Sync 2 C

PF9 – GPIO/TMR0/PPI FS1 I/O GPIO/Timer0/PPI Frame Sync 1 C

PF10 – GPIO/SPI SSEL1 I/O GPIO/SPI Slave Select Enable 1 C

PF11 – GPIO/SPI MOSI I/O GPIO/SPI Master Out Slave In C

PF12 – GPIO/SPI MISO I/O GPIO/SPI Master In Slave Out (This pin should be pulled high through a 4.7 kΩ

resistor if booting via the SPI port.)

PF13 – GPIO/SPI SCK I/O GPIO/SPI Clock D

PF14 – GPIO/SPI SS/TACLK0 I/O GPIO/SPI Slave Select/Alternate Timer0 Clock Input C

PF15 – GPIO/PPI CLK/TMRCLK I/O GPIO/PPI Clock/External Timer Reference C

Port G: GPIO/PPI/SPORT1

PG0 – GPIO/PPI D0 I/O GPIO/PPI Data 0 C

PG1 – GPIO/PPI D1 I/O GPIO/PPI Data 1 C

PG2 – GPIO/PPI D2 I/O GPIO/PPI Data 2 C

PG3 – GPIO/PPI D3 I/O GPIO/PPI Data 3 C

PG4 – GPIO/PPI D4 I/O GPIO/PPI Data 4 C

PG5 – GPIO/PPI D5 I/O GPIO/PPI Data 5 C

PG6 – GPIO/PPI D6 I/O GPIO/PPI Data 6 C

PG7 – GPIO/PPI D7 I/O GPIO/PPI Data 7 C

PG8 – GPIO/PPI D8/DR1SEC I/O GPIO/PPI Data 8/SPORT1 Receive Data Secondary C

PG9 – GPIO/PPI D9/DT1SEC I/O GPIO/PPI Data 9/SPORT1 Transmit Data Secondary C

PG10 – GPIO/PPI D10/RSCLK1 I/O GPIO/PPI Data 10/SPORT1 Receive Serial Clock D

PG11 – GPIO/PPI D11/RFS1 I/O GPIO/PPI Data 11/SPORT1 Receive Frame Sync C

PG12 – GPIO/PPI D12/DR1PRI I/O GPIO/PPI Data 12/SPORT1 Receive Data Primary C

PG13 – GPIO/PPI D13/TSCLK1 I/O GPIO/PPI Data 13/SPORT1 Transmit Serial Clock D

PG14 – GPIO/PPI D14/TFS1 I/O GPIO/PPI Data 14/SPORT1 Transmit Frame Sync C

PG15 – GPIO/PPI D15/DT1PRI I/O GPIO/PPI Data 15/SPORT1 Transmit Data Primary C

Table 9. Pin Descriptions (Continued)

Pin Name Type Function

Driver

Type

Rev. I | Page 22 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Port H: GPIO/10/100 Ethernet MAC (On

ADSP-BF534, these pins are GPIO only)

PH0 – GPIO/ETxD0 I/O GPIO/Ethernet MII or RMII Transmit D0 E

PH1 – GPIO/ETxD1 I/O GPIO/Ethernet MII or RMII Transmit D1 E

PH2 – GPIO/ETxD2 I/O GPIO/Ethernet MII Transmit D2 E

PH3 – GPIO/ETxD3 I/O GPIO/Ethernet MII Transmit D3 E

PH4 – GPIO/ETxEN I/O GPIO/Ethernet MII or RMII Transmit Enable E

PH5 – GPIO/MII TxCLK/RMII REF_CLK I/O GPIO/Ethernet MII Transmit Clock/RMII Reference Clock E

PH6 – GPIO/MII PHYINT/RMII MDINT I/O GPIO/Ethernet MII PHY Interrupt/RMII Management Data Interrupt (This pin

should be pulled high when used as a hibernate wake-up.)

PH7 – GPIO/COL I/O GPIO/Ethernet Collision E

PH8 – GPIO/ERxD0 I/O GPIO/Ethernet MII or RMII Receive D0 E

PH9 – GPIO/ERxD1 I/O GPIO/Ethernet MII or RMII Receive D1 E

PH10 – GPIO/ERxD2 I/O GPIO/Ethernet MII Receive D2 E

PH11 – GPIO/ERxD3 I/O GPIO/Ethernet MII Receive D3 E

PH12 – GPIO/ERxDV/TACLK5 I/O GPIO/Ethernet MII Receive Data Valid/Alternate Timer5 Input Clock E

PH13 – GPIO/ERxCLK/TACLK6 I/O GPIO/Ethernet MII Receive Clock/Alternate Timer6 Input Clock E

PH14 – GPIO/ERxER/TACLK7 I/O GPIO/Ethernet MII or RMII Receive Error/Alternate Timer7 Input Clock E

PH15 – GPIO/MII CRS/RMII CRS_DV I/O GPIO/Ethernet MII Carrier Sense/Ethernet RMII Carrier Sense and Receive Data

Valid

Port J: SPORT0/TWI/SPI Select/CAN

PJ0 – MDC O Ethernet Management Channel Clock (On ADSP-BF534 processors, do not

connect this pin.)

PJ1 – MDIO I/O Ethernet Management Channel Serial Data (On ADSP-BF534 processors, tie this

pin to ground.)

PJ2 – SCL I/O TWI Serial Clock (This pin is an open-drain output and requires a pull-up

resistor.)

PJ3 – SDA I/O TWI Serial Data (This pin is an open-drain output and requires a pull-up

resistor.)

PJ4 – DR0SEC/CANRX/TACI0 I SPORT0 Receive Data Secondary/CAN Receive/Timer0 Alternate Input Capture

PJ5 – DT0SEC/CANTX/SPI SSEL7 O SPORT0 Transmit Data Secondary/CAN Transmit/SPI Slave Select Enable 7 C

PJ6 – RSCLK0/TACLK2 I/O SPORT0 Receive Serial Clock/Alternate Timer2 Clock Input D

PJ7 – RFS0/TACLK3 I/O SPORT0 Receive Frame Sync/Alternate Timer3 Clock Input C

PJ8 – DR0PRI/TACLK4 I SPORT0 Receive Data Primary/Alternate Timer4 Clock Input

PJ9 – TSCLK0/TACLK1 I/O SPORT0 Transmit Serial Clock/Alternate Timer1 Clock Input D

PJ10 – TFS0/SPI SSEL3 I/O SPORT0 Transmit Frame Sync/SPI Slave Select Enable 3 C

PJ11 – DT0PRI/SPI SSEL2 O SPORT0 Transmit Data Primary/SPI Slave Select Enable 2 C

Real-Time Clock

RTXI I RTC Crystal Input (This pin should be pulled low when not used.)

RTXO O RTC Crystal Output (Does not three-state in hibernate.)

JTAG Port

TCK I JTAG Clock

TDO O JTAG Serial Data Out C

TDI I JTAG Serial Data In

TMS I JTAG Mode Select

TRST I JTAG Reset (This pin should be pulled low if the JTAG port is not used.)

EMU O Emulation Output C

Table 9. Pin Descriptions (Continued)

Pin Name Type Function

Driver

Type

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 23 of 68 | July 2010

Clock

CLKIN I Clock/Crystal Input

XTAL O Crystal Output (If CLKBUF is enabled, does not three-state during hibernate.)

CLKBUF O Buffered XTAL Output (If enabled, does not three-state during hibernate.) E

Mode Controls

RESET IReset

NMI I Nonmaskable Interrupt (This pin should be pulled high when not used.)

BMODE2–0 I Boot Mode Strap 2-0 (These pins must be pulled to the state required for the

desired boot mode.)

Voltage Regulator

VROUT1–0 O External FET Drive (These pins should be left unconnected when not used and

are driven high during hibernate.)

Supplies

DDEXT

P I/O Power Supply

DDINT

P Internal Power Supply

DDRTC

P Real-Time Clock Power Supply (This pin should be connected to V

DDEXT

when

not used and should remain powered at all times.)

GND G External Ground

See Output Drive Currents on Page 51 for more information about each driver types.

Table 9. Pin Descriptions (Continued)

Pin Name Type Function

Driver

Type

Rev. I | Page 24 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

SPECIFICATIONS

Note that component specifications are subject to change

without notice.

OPERATING CONDITIONS

Parameter Conditions Min Nominal Max Unit

DDINT

Internal Supply Voltage

The regulator can generate V

DDINT

at levels of 0.85 V to 1.2 V with –5% to +10% tolerance, 1.25 V with –4% to +10% tolerance, and 1.3 V with –0% to +10% tolerance. The

required V

DDINT

is a function of speed grade and operating frequency. See Table 10, Table 11, and Table 12 for details.

Nonautomotive 300 MHz, 400 MHz, and 500 MHz speed

grade models

See Ordering Guide on Page 68.

0.8 1.2 1.32 V

DDINT

Internal Supply Voltage

Nonautomotive 533 MHz speed grade models

0.8 1.25 1.375 V

DDINT

Internal Supply Voltage

Nonautomotive 600 MHz speed grade models

0.8 1.3 1.43 V

DDINT

Internal Supply Voltage

Automotive grade models and +105°C nonautomotive

grade models

0.95 1.2 1.32 V

DDEXT

External Supply Voltage Nonautomotive grade models

2.25 2.5 or 3.3 3.6 V

DDEXT

External Supply Voltage Automotive grade models and +105°C nonautomotive

grade models

2.7 3.0 or 3.3 3.6 V

DDRTC

Real-Time Clock Power

Supply Voltage

2.25 3.6 V

High Level Input Voltage

3, 4

Bidirectional pins (DATA15–0, PF15–0, PG15–0, PH15–0, TFS0, TSCLK0, RSCLK0, RFS0, MDIO) and input pins (BR, ARDY, DR0PRI, DR0SEC, RTXI, TCK, TDI, TMS,

TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF534/ADSP-BF536/ADSP-BF537 are 3.3 V-tolerant (always accept up to 3.6 V maximum V

). Voltage

compliance (on outputs, V

) is limited by the V

DDEXT

supply voltage.

Parameter value applies to all input and bidirectional pins except CLKIN, SDA, and SCL.

DDEXT

= Maximum 2.0 V

IHCLKIN

High Level Input Voltage

Parameter value applies to CLKIN pin only.

DDEXT

= Maximum 2.2 V

IH5V

5.0 V Tolerant Pins, High

Level Input Voltage

Applies to pins PJ2/SCL and PJ3/SDA which are 5.0 V tolerant (always accept up to 5.5 V maximum V

). Voltage compliance (on outputs, V

) is limited by the V

DDEXT

supply

voltage.

0.7 × V

DDEXT

IH5V

5.0 V Tolerant Pins, High

Level Input Voltage

Applies to pin PJ4/DR0SEC/CANRX/TACI0 which is 5.0 V tolerant (always accepts up to 5.5 V maximum V

). Voltage compliance (on outputs, V

) is limited by the V

DDEXT

supply voltage.

DDEXT

= Maximum 2.0 V

Low Level Input Voltage

3, 8

Parameter value applies to all input and bidirectional pins except SDA and SCL.

DDEXT

= Minimum +0.6 V

IL5V

5.0 V Tolerant Pins, Low

Level Input Voltage

0.3 × V

DDEXT

IL5V

5.0 V Tolerant Pins, Low

Level Input Voltage

DDEXT

= Minimum +0.8 V

Junction Temperature 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @

AMBIENT

= –40°C to +105°C

–40 +120 °C

Junction Temperature 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @

AMBIENT

= –40°C to +85°C

–40 +105 °C

Junction Temperature 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @

AMBIENT

= 0°C to +70°C

0+95°C

Junction Temperature 182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @

AMBIENT

= –40°C to +85°C

–40 +105 °C

Junction Temperature 182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @

AMBIENT

= 0°C to +70°C

0+100°C

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 25 of 68 | July 2010

Table 10 through Table 12 describe the voltage/frequency

requirements for the ADSP-BF534/ADSP-BF536/ADSP-BF537

processor clocks. Take care in selecting MSEL, SSEL, and CSEL

ratios so as not to exceed the maximum core clock and system

clock. Table 13 describes phase-locked loop operating

conditions.

Table 10. Core Clock Requirements—500 MHz, 533 MHz, and 600 MHz Speed Grades

Parameter Internal Regulator Setting Max Unit

CCLK

Core Clock Frequency (V

DDINT

=1.30 V Minimum)

1.30 V 600 MHz

CCLK

Core Clock Frequency (V

DDINT

= 1.20 V Minimum)

1.25 V 533 MHz

CCLK

Core Clock Frequency (V

DDINT

=1.14 V Minimum) 1.20 V 500 MHz

CCLK

Core Clock Frequency (V

DDINT

=1.045 V Minimum) 1.10 V 444 MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.95 V Minimum) 1.00 V 400 MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.85 V Minimum) 0.90 V 333 MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.8 V Minimum) 0.85 V 250 MHz

See Ordering Guide on Page 68.

Applies to 600 MHz models only. See Ordering Guide on Page 68.

Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 68.

Table 11. Core Clock Requirements—400 MHz Speed Grade

120°C ≥ T

> 105°C All

Other T

UnitParameter Internal Regulator Setting Max Max

CCLK

Core Clock Frequency (V

DDINT

=1.14 V Minimum) 1.20 V 400 400 MHz

CCLK

Core Clock Frequency (V

DDINT

=1.045 V Minimum) 1.10 V 333 363 MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.95 V Minimum) 1.00 V 295 333 MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.85 V Minimum) 0.90 V 280 MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.8 V Minimum) 0.85 V 250 MHz

See Ordering Guide on Page 68.

See Operating Conditions on Page 24.

Table 12. Core Clock Requirements—300 MHz Speed Grade

Parameter Internal Regulator Setting Max Unit

CCLK

Core Clock Frequency (V

DDINT

=1.14 V Minimum) 1.20 V 300 MHz

CCLK

Core Clock Frequency (V

DDINT

=1.045 V Minimum) 1.10 V 255 MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.95 V Minimum) 1.00 V 210 MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.85 V Minimum) 0.90 V 180 MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.8 V Minimum) 0.85 V 160 MHz

See Ordering Guide on Page 68.

Table 13. Phase-Locked Loop Operating Conditions

Parameter Min Max Unit

VCO

Voltage Controlled Oscillator (VCO) Frequency 50 Max f

CCLK

MHz

Table 14. System Clock Requirements

Parameter Condition Max Unit

SCLK1

DDEXT

= 3.3 V or 2.5 V, V

DDINT

≥ 1.14 V 133

MHz

SCLK1

DDEXT

= 3.3 V or 2.5 V, V

DDINT

< 1.14 V 100 MHz

SCLK

must be less than or equal to f

CCLK

and is subject to additional restrictions for SDRAM interface operation. See Table 27 on Page 35.

Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 27 on Page 35.

Rev. I | Page 26 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

ELECTRICAL CHARACTERISTICS

300 MHz/400 MHz

500 MHz/533 MHz/600 MHz

Parameter Test Conditions Min Typ Max Min Typ Max Unit

OH3

High Level

Output Voltage

DDEXT

= 2.5 V/3.0 V/

3.3 V ± 10%, I

= –0.5

DDEXT

– 0.5 V

DDEXT

– 0.5 V

OH4

DDEXT

= 3.3 V ± 10%,

= –8 mA

DDEXT

= 2.5 V/3.0 V ±

10%,

= –6 mA

DDEXT

– 0.5

DDEXT

– 0.5

DDEXT

– 0.5

DDEXT

– 0.5

OH5

DDEXT

= 2.5 V/3.0 V/

3.3 V ± 10%, I

= –2.0

DDEXT

– 0.5 V

DDEXT

– 0.5 V

OH6

High Level

Output Current

= V

DDEXT

– 0.5 V Min –64 –64 mA

OH7

= V

DDEXT

– 0.5 V Min –144 –144 mA

OL3

Low Level

Output Voltage

DDEXT

= 2.5 V/3.0 V/

3.3 V ± 10%, I

= 2.0

0.4 0.4 V

OL4

DDEXT

= 3.3 V ± 10%,

= 8 mA

DDEXT

= 2.5 V/3.0 V ±

10%,

= 6 mA

0.5

OL5

DDEXT

= 2.5 V/3.0 V/

3.3 V ± 10%, I

= 2.0

0.5 0.5 V

OL6

Low Level

Output Current

= 0.5 V Max 64 64 mA

OL7

= 0.5 V Max 144 144 mA

High Level Input

Current

DDEXT

=3.6 V, V

= 3.6

10 10 μA

IH5V

High Level Input

Current

DDEXT

=3.6 V, V

= 5.5

10 10 μA

Low Level Input

Current

DDEXT

=3.6 V, V

= 0 V 10 10 μA

IHP

High Level Input

Current JTAG

DDEXT

= 3.6 V, V

= 3.6

50 50 μA

OZH

Three-State

Leakage

Current

DDEXT

= 3.6 V, V

= 3.6

10 10 μA

OZH5V

Three-State

Leakage

Current

DDEXT

=3.6 V, V

= 5.5

10 10 μA

OZL

Three-State

Leakage

Current

DDEXT

= 3.6 V, V

= 0 V 10 10 μA

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 27 of 68 | July 2010

Input

Capacitance

13, 14

= 1 MHz, T

AMBIENT

25°C, V

= 2.5 V

88pF

DD-IDLE

DDINT

Current in

Idle

DDINT

= 1.0 V, f

CCLK

= 50

MHz,

= 25°C, ASF = 0.43

14 24 mA

DD-TYP

DDINT

Current V

DDINT

= 1.14 V,

CCLK

=300MHz, T

25°C, ASF = 1.00

100 113 mA

DD-TYP

DDINT

Current V

DDINT

= 1.14 V,

CCLK

=400MHz, T

25°C, ASF = 1.00

125 138 mA

DDDEEPSLEEP15

DDINT

Current in

Deep Sleep

Mode

DDINT

= 1.0 V, f

CCLK

= 0

MHz,

= 25°C, ASF = 0.00

616mA

DDSLEEP

DDINT

Current in

Sleep Mode

DDINT

= 1.0 V, f

SCLK

= 25

MHz,

= 25°C

9.5 19.5 mA

DD-TYP

DDINT

Current V

DDINT

= 1.20 V,

CCLK

=533MHz, T

25°C, ASF = 1.00

185 mA

DD-TYP

DDINT

Current V

DDINT

= 1.30 V,

CCLK

=600MHz, T

25°C, ASF = 1.00

227 mA

DDHIBERNATE15,

DDEXT

Current in

Hibernate State

DDEXT

= 3.60 V,

CLKIN=0 MHz,

=maximum, with

voltage regulator off

DDINT

=0 V)

50 100 50 100 μA

DDRTC

Current V

DDRTC

= 3.3 V, T

= 25°C 20 20 μA

DDDEEPSLEEP15

DDINT

Current in

Deep Sleep

Mode

CCLK

= 0 MHz, f

SCLK

MHz

Table 16 Table 15 mA

DDSLEEP15,

DDINT

Current in

Sleep Mode

CCLK

= 0 MHz, f

SCLK

> 0

MHz

DDDEEPSLEEP

+ (0.14

× V

DDINT

× f

SCLK

)

DDDEEPSLEEP

+ (0.14

× V

DDINT

× f

SCLK

)

DDINT18

DDINT

Current f

CCLK

> 0 MHz, f

SCLK

> 0

MHz

DDSLEEP

(Table 18 × ASF)

DDSLEEP

(Table 18 × ASF)

Applies to all 300 MHz and 400 MHz speed grade models. See Ordering Guide on Page 68.

Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 68.

Applies to all output and bidirectional pins except port F pins, port G pins, and port H pins.

Applies to port F pins PF7–0.

Applies to port F pins PF15–8, all port G pins, and all port H pins.

Maximum combined current for Port F7–0.

Maximum total current for all port F, port G, and port H pins.

Applies to all input pins except PJ4.

Applies to input pin PJ4 only.

Applies to JTAG input pins (TCK, TDI, TMS, TRST).

Applies to three-statable pins.

Applies to bidirectional pins PJ2 and PJ3.

Applies to all signal pins.

Guaranteed, but not tested.

See the ADSP-BF537 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.

CLKIN must be tied to V

DDEXT

or GND during hibernate.

In the equations, the f

SCLK

parameter is the system clock in MHz.

See Table 17 for the list of I

DDINT

power vectors covered.

300 MHz/400 MHz

500 MHz/533 MHz/600 MHz

Parameter Test Conditions Min Typ Max Min Typ Max Unit

Rev. I | Page 28 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

System designers should refer to Estimating Power for the

ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297), which

provides detailed information for optimizing designs for lowest

power. All topics discussed in this section are described in detail

in EE-297. Total power dissipation has two components:

1. Static, including leakage current

2. Dynamic, due to transistor switching characteristics

Many operating conditions can also affect power dissipation,

including temperature, voltage, operating frequency, and pro-

cessor activity. Electrical Characteristics on Page 26 shows the

current dissipation for internal circuitry (V

DDINT

). I

DDDEEPSLEEP

specifies static power dissipation as a function of voltage

DDINT

) and temperature (see Table 16 or Table 15), and I

DDINT

specifies the total power specification for the listed test condi-

tions, including the dynamic component as a function of voltage

DDINT

) and frequency (Table 18).

The dynamic component is also subject to an Activity Scaling

Factor (ASF) which represents application code running on the

processor (Table 17).

Table 15. Static Current–500 MHz, 533 MHz, and 600 MHz Speed Grade Devices (mA)

(°C)

Voltage (V

DDINT

)

0.80 V 0.85 V 0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.32 V 1.375 V 1.43 V

–40 3.9 4.7 6.8 8.2 9.9 12.0 14.6 17.3 20.3 24.1 27.1 28.6 36.3 44.4

0 17.0 19.2 21.9 25.0 28.2 32.1 36.9 41.8 47.7 53.8 61.0 63.8 73.2 84.1

25 35.0 39.2 44.3 50.8 56.1 63.3 69.1 76.4 84.7 93.5 104.5 109.1 123.4 138.8

40 53.0 59.2 65.3 71.9 79.1 88.0 96.6 108.0 120.0 130.7 142.6 148.5 166.5 185.6

55 76.7 84.6 93.6 103.1 113.7 123.9 136.3 148.3 162.8 178.4 194.4 201.4 223.7 247.5

70 110.1 120.0 130.9 142.2 156.5 171.3 185.2 201.7 220.6 239.7 259.8 268.8 295.9 325.2

85 150.1 164.5 178.7 193.2 210.4 228.9 247.7 268.8 291.4 314.1 341.1 351.2 384.6 420.3

100 202.3 219.2 236.5 255.8 277.8 299.8 323.8 351.2 378.8 407.5 440.4 453.4 494.3 538.2

105 223.8 241.4 260.4 282.0 303.4 328.7 354.5 381.7 410.8 443.6 477.8 492.2 535.1 581.5

Values are guaranteed maximum I

DDDEEPSLEEP

specifications.

Table 16. Static Current–300 MHz and 400 MHz Speed Grade Devices (mA)

(°C)

Voltage (V

DDINT

)

0.80 V 0.85 V 0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.32 V

–40 2.6 3.2 3.7 4.5 5.5 6.6 7.9 9.3 10.5 12.5 13.9 14.8

0 6.6 7.8 8.4 9.9 10.912.313.815.517.519.621.723.1

25 12.2 13.5 14.8 16.4 18.2 19.9 22.7 25.6 28.4 31.8 35.7 37.2

40 17.2 19.0 20.6 22.9 25.9 28.2 31.6 34.9 38.9 42.9 47.6 49.5

55 25.7 27.8 30.9 33.7 37.3 41.4 44.8 50.0 54.8 59.4 66.1 68.4

70 37.6 41.3 44.8 48.9 53.9 58.6 63.9 69.7 76.9 84.0 92.2 94.9

85 53.7 58.3 63.7 69.0 75.9 82.9 90.5 98.4 106.4 115.3 124.6 128.1

100 75.1 82.3 88.5 95.8 104.0 112.5 121.8 130.6 141.3 153.2 164.8 169.7

105 84.5 91.2 98.2 106.0 114.2 123.0 132.4 143.3 155.0 167.4 179.8 185.4

115

103.8 111.8 120.3 127.6 138.0 148.5 159.6 171.4 184.6 198.8 213.4 219.6

120

115.5 123.6 132.2 141.9 152.3 163.7 175.6 189.3 202.8 217.7 232.3 238.6

Values are guaranteed maximum I

DDDEEPSLEEP

specifications.

Applies to automotive grade models only.

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I | Page 29 of 68 | July 2010

Table 17. Activity Scaling Factors

DDINT

Power Vector

Activity Scaling Factor (ASF)

DD-PEAK

1.33

DD-HIGH

1.29

DD-TYP

1.00

DD-APP

0.88

DD-NOP

0.72

DD-IDLE

0.43

See EE-297 for power vector definitions.

All ASF values determined using a 10:1 CCLK:SCLK ratio.

Table 18. Dynamic Current (mA, with ASF = 1.0)

Frequency

(MHz)

Voltage (V

DDINT

)

0.80 V 0.85 V 0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.32 V 1.375 V 1.43 V

50 11.0 13.7 19.13 18.2 18.67 19.13 19.6 21.2 24.1 25.5 28.5 28.6 28.85 29.2

100 27.922.730.828.429.330.832.935.337.840.643.543.744.1 45.8

200 36.942.655.049.251.555.058.362.967.069.773.074.075.7 80.7

300 N/A 61.5 79.2 70.4 74.6 79.2 84.4 90.7 94.3 99.1 103.9 105.5 108.0 113.4

400 N/A N/A N/A 92.4 97.2 104.3 109.8 116.5 121.9 128.0 134.6 136.6 139.8 145.1

500 N/A N/A N/A N/A N/A N/A N/A 142.3 149.3 157.5 164.7 166.7 169.8 176.9

533 N/A N/A N/A N/A N/A N/A N/A N/A 158.6 167.0 174.3 176.6 180.1 187.9

600 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 193.7 196.5 200.7 210.0

The values are not guaranteed as stand-alone maximum specifications, they must be combined with static current per the equations of Electrical Characteristics on Page 26.

Rev. I | Page 30 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 19 may cause perma-

nent damage to the device. These are stress ratings only.

Functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

ESD SENSITIVITY

PACKAGE INFORMATION

The information presented in Figure 8 and Table 21 provide

details about the package branding for the Blackfin processors.

For a complete listing of product availability, see Ordering

Guide on Page 68.

Table 19. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V

DDINT

) –0.3 V to +1.43 V

External (I/O) Supply Voltage (V

DDEXT

)–0.3 V to +3.8 V

Input Voltage

Applies only when V

DDEXT

is within specifications. When V

DDEXT

is outside speci-

fications, the range is V

DDEXT

± 0.2 V.

–0.5 V to +3.6 V

Input Voltage

Applies to 5 V tolerant pins SCL, SDA, and PJ4. For duty cycles, see Table 20.

–0.5 V to +5.5 V

Output Voltage Swing –0.5 V to V

DDEXT

+ 0.5 V

Storage Temperature Range –65°C to +150°C

Junction Temperature While Biased +125°C

Table 20. Maximum Duty Cycle for Input

Transient Voltage

Applies to all signal pins with the exception of CLKIN, XTAL, and VROUT1–0.

Min (V)

Max (V)

The individual values cannot be combined for analysis of a single instance of

overshoot or undershoot. The worst case observed value must fall within one of

the voltages specified and the total duration of the overshoot or undershoot

(exceeding the 100% case) must be less than or equal to the corresponding

duty cycle.

Maximum Duty Cycle

Duty cycle refers to the percentage of time the signal exceeds the value for the

100% case. This is equivalent to the measured duration of a single instance of

overshoot or undershoot as a percentage of the period of occurrence.

–0.50 +3.80 100%

–0.70 +4.00 40%

–0.80 +4.10 25%

–0.90 +4.20 15%

–1.00 +4.30 10%

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid

performance degradation or loss of functionality.

Figure 8. Product Information on Package

Table 21. Package Brand Information

Nonautomotive only. For branding information specific to Automotive

products, contact Analog Devices Inc.

Brand Key Field Description

t Temperature Range

pp Package Type

Z RoHS Compliant Designation

ccc See Ordering Guide

vvvvvv.x Assembly Lot Code

n.n Silicon Revision

# RoHS Compliant Designation

yyww Date Code

vvvvvv.x n.n

tppZccc

ADSP-BF53x

yyww country_of_origin

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 31 of 68 | July 2010

TIMING SPECIFICATIONS

Component specifications are subject to change

without notice.

Clock and Reset Timing

Table 22. Clock Input and Reset Timing

Parameter MinMaxUnit

Timing Requirements

CKIN

CLKIN Period

Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f

VCO

, f

CCLK

, and f

SCLK

settings discussed in Table 10 through Table 14. Since

by default the PLL is multiplying the CLKIN frequency by 10, 300 MHz and 400 MHz speed grade parts can not use the full CLKIN period range.

Applies to PLL bypass mode and PLL non bypass mode.

CLKIN frequency must not change on the fly.

If the DF bit in the PLL_CTL register is set, then the maximum t

CKIN

period is 50 ns.

20.0100.0ns

CKINL

CLKIN Low Pulse 8.0ns

CKINH

CLKIN High Pulse 8.0ns

BUFDLAY

CLKIN to CLKBUF Delay 10 ns

WRST

RESET Asserted Pulse Width Low 11 × t

CKIN

NOBOOT

RESET Deassertion to First External Access Delay

Applies when processor is configured in No Boot Mode (BMODE2-0 = b#000).

3 × t

CKIN

5 × t

CKIN

Figure 9. Clock and Reset Timing

Table 23. Power-Up Reset Timing

Parameter MinMaxUnit

Timing Requirements

RST_IN_PWR

RESET Deasserted After the V

DDINT

, V

DDEXT

, V

DDRTC

, and CLKIN Pins Are Stable and

Within Specification

3500 × t

CKIN

In Figure 10, V

DD_SUPPLIES

is V

DDINT

, V

DDEXT

, V

DDRTC

Figure 10. Power-Up Reset Timing

CLKIN

tWRST

tCKIN

tCKINL tCKINH

tBUFDLAY

RESET

CLKBUF

tNOBOOT

RESET

tRST_IN_PWR

CLKIN

VDD_SUPPLIES

Rev. I|Page 32 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Asynchronous Memory Read Cycle Timing

Table 24. Asynchronous Memory Read Cycle Timing

Parameter MinMaxUnit

Timing Requirements

SDAT

DATA15–0 Setup Before CLKOUT 2.1ns

HDAT

DATA15–0 Hold After CLKOUT 0.8ns

SARDY

ARDY Setup Before CLKOUT 4.0ns

HARDY

ARDY Hold After CLKOUT 0.0ns

Switching Characteristics

Output Delay After CLKOUT

Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

6.0ns

Output Hold After CLKOUT

0.8ns

Figure 11. Asynchronous Memory Read Cycle Timing

tHARDY

SETUP

2 CYCLES

PROGRAMMED READ

ACCESS 4 CYCLES

ACCESS EXTENDED

3 CYCLES

HOLD

1 CYCLE

tDO tHO

tDO

tHARDY

tSARDY

tSDAT

tHDAT

tSARDY

CLKOUT

AMSx

ABE1–0

ADDR19–1

AOE

ARE

ARDY

DATA 15–0

tHO

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 33 of 68 | July 2010

Asynchronous Memory Write Cycle Timing

Table 25. Asynchronous Memory Write Cycle Timing

Parameter MinMaxUnit

Timing Requirements

SARDY

ARDY Setup Before CLKOUT 4.0ns

HARDY

ARDY Hold After CLKOUT 0.0ns

Switching Characteristics

DDAT

DATA15–0 Disable After CLKOUT 6.0ns

ENDAT

DATA15–0 Enable After CLKOUT 1.0ns

Output Delay After CLKOUT

Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, AWE.

6.0ns

Output Hold After CLKOUT

0.8ns

Figure 12. Asynchronous Memory Write Cycle Timing

SETUP

2 CYCLES

PROGRAMMED

WRITE

ACCESS

2 CYCLES

ACCESS

EXTEND

1 CYCLE

HOLD

1 CYCLE

tDO tHO

CLKOUT

AMSx

ABE1–0

ADDR19–1

AWE

ARDY

DATA 15–0

tSARDY

tDDAT

tENDAT tHARDY

tHO

tDO

tHARDY

Rev. I|Page 34 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

External Port Bus Request and Grant Cycle Timing

Table 26 and Figure 13 describe external port bus request and

bus grant operations.

Table 26. External Port Bus Request and Grant Cycle Timing

Parameter

1, 2

MinMaxUnit

Timing Requirements

BR Asserted to CLKOUT Low Setup4.6ns

CLKOUT Low to BR Deasserted Hold Time 0.0ns

Switching Characteristics

CLKOUT Low to AMSx, Address, and ARE/AWE Disable4.5ns

CLKOUT Low to AMSx, Address, and ARE/AWE Enable4.5ns

DBG

CLKOUT High to BG Asserted Setup3.6ns

EBG

CLKOUT High to BG Deasserted Hold Time 3.6ns

DBH

CLKOUT High to BGH Asserted Setup3.6ns

EBH

CLKOUT High to BGH Deasserted Hold Time 3.6ns

These timing parameters are based on worst-case operating conditions.

The pad loads for these timing parameters are 20 pF.

Figure 13. External Port Bus Request and Grant Cycle Timing

AMSx

CLKOUT

BGH

ADDR 19-1

ABE1-0

tBH

tBS

tSD tSE

tSD

tSE

tEBG

tDBG

tEBH

tDBH

AWE

ARE

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 35 of 68 | July 2010

SDRAM Interface Timing

Table 27. SDRAM Interface Timing

Parameter MinMaxUnit

Timing Requirements

SSDAT

DATA15–0 Setup Before CLKOUT 1.5ns

HSDAT

DATA15–0 Hold After CLKOUT 0.8ns

Switching Characteristics

DCAD

COMMAND

, ADDR19–1, DATA15–0 Delay After CLKOUT

Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

4.0ns

HCAD

COMMAND

, ADDR19–1, DATA15–0 Hold After CLKOUT 1.0ns

DSDAT

DATA15–0 Disable After CLKOUT 6.0ns

ENSDAT

DATA15–0 Enable After CLKOUT 0.5ns

SCLK2

These limits are specific to the SDRAM interface only. In addition, CLKOUT must always comply with the limits in Table 14 on Page 25.

CLKOUT Period when T

≤ +105°C7.5ns

SCLK2

CLKOUT Period when T

> +105°C10 ns

SCLKH

CLKOUT Width High 2.5ns

SCLKL

CLKOUT Width Low 2.5ns

Figure 14. SDRAM Interface Timing

tSCLK

CLKOUT

tSCLKL tSCLKH

tSSDAT tHSDAT

tENSDAT

tDCAD tDSDAT

tHCAD

tDCAD tHCAD

DATA (IN)

DATA (OUT)

COMMAND,

ADDRESS

(OUT)

NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Rev. I|Page 36 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

External DMA Request Timing

Table 28 and Figure 15 describe the external DMA request

operations.

Table 28. External DMA Request Timing

Parameter MinMaxUnit

Timing Requirements

DMARx Asserted to CLKOUT High Setup6.0ns

CLKOUT High to DMARx Deasserted Hold Time 0.0ns

DMARACT

DMARx Active Pulse Width 1.0 × t

SCLK

DMARINACT

DMARx Inactive Pulse Width 1.75 × t

SCLK

Figure 15. External DMA Request Timing

CLKOUT

tDR

DMAR0/1

(ACTIVE LOW)

tDH

DMAR0/1

(ACTIVE HIGH)

tDMARACT tDMARINACT

tDMARINACT

tDMARACT

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 37 of 68 | July 2010

Parallel Peripheral Interface Timing

Table 29 and Figure 16 on Page 37, Figure 20 on Page 40, and

Figure 23 on Page 42 describe parallel peripheral interface

operations.

Table 29. Parallel Peripheral Interface Timing

Parameter MinMaxUnit

Timing Requirements

PCLKW

PPI_CLK Width

6.0ns

PCLK

PPI_CLK Period

15.0ns

Timing Requirements—GP Input and Frame Capture Modes

SFSPE

External Frame Sync Setup Before PPI_CLK 6.7ns

HFSPE

External Frame Sync Hold After PPI_CLK 1.0ns

SDRPE

Receive Data Setup Before PPI_CLK 3.5ns

HDRPE

Receive Data Hold After PPI_CLK 1.5ns

Switching Characteristics—GP Output and Frame Capture Modes

DFSPE

Internal Frame Sync Delay After PPI_CLK 8.0ns

HOFSPE

Internal Frame Sync Hold After PPI_CLK 1.7ns

DDTPE

Transmit Data Delay After PPI_CLK 8.0ns

HDTPE

Transmit Data Hold After PPI_CLK 1.8ns

PPI_CLK frequency cannot exceed f

SCLK

/2.

Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing

Figure 17. PPI GP Rx Mode with External Frame Sync Timing

tHDRPE

tSDRPE

tHOFSPE

FRAME SYNC

DRIVEN

DATA

SAMPLED

PPI_DATA

PPI_CLK

PPI_FS1/2

tDFSPE

tPCLK

tPCLKW

tPCLK

tSFSPE

DATA SAMPLED /

FRAME SYNC SAMPLED

DATA SAMPLED /

FRAME SYNC SAMPLED

PPI_DATA

PPI_CLK

PPI_FS1/2

tHFSPE

tHDRPE

tSDRPE

tPCLKW

Rev. I|Page 38 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Figure 18. PPI GP Tx Mode with Internal Frame Sync Timing

Figure 19. PPI GP Tx Mode with External Frame Sync Timing

tHOFSPE

FRAME SYNC

DRIVEN

DATA

DRIVEN

PPI_DATA

PPI_CLK

PPI_FS1/2

tDFSPE

tDDTPE tHDTPE

tPCLK

tPCLKW

DATA

DRIVEN

tHDTPE

tSFSPE

DATA DRIVEN /

FRAME SYNC SAMPLED

PPI_DATA

PPI_CLK

PPI_FS1/2

tHFSPE

tDDTPE

tPCLK

tPCLKW

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 39 of 68 | July 2010

Serial Port Timing

Table 30 through Table 33 on Page 42 and Figure 20 on Page 40

through Figure 23 on Page 42 describe serial port operations.

Table 30. Serial Ports—External Clock

Parameter MinMaxUnit

Timing Requirements

SFSE

TFSx/RFSx Setup Before TSCLKx/RSCLKx

3.0ns

HFSE

TFSx/RFSx Hold After TSCLKx/RSCLKx

3.0ns

SDRE

Receive Data Setup Before RSCLKx

3.0ns

SCLKEW

TSCLKx/RSCLKx Width 4.54.5

SCLKE

TSCLKx/RSCLKx Period 15.015.0

SUDTE

Start-Up Delay From SPORT Enable To First External TFSx

4.0 × t

SCLKE

SUDRE

Start-Up Delay From SPORT Enable To First External RFSx

4.0 × t

SCLKE

Switching Characteristics

DFSE

TFSx/RFSx Delay After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)

10.0ns

HOFSE

TFSx/RFSx Hold After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)

0ns

DDTE

Transmit Data Delay After TSCLKx

10.0ns

HDTE

Transmit Data Hold After TSCLKx

0ns

Referenced to sample edge.

Verified in design but untested. After being enabled, the serial port requires external clock pulses—before the first external frame sync edge—to initialize the serial port.

Referenced to drive edge.

Table 31. Serial Ports—Internal Clock

2.25 V ≤ V

DDEXT

< 2.70 V

0.80 V ≤ V

DDINT

< 0.95 V

2.70 V ≤ V

DDEXT

≤ 3.60 V

and

0.95 V ≤ V

DDINT

≤ 1.43 V

Parameter MinMaxMinMaxUnit

Timing Requirements

SFSI

TFSx/RFSx Setup Before TSCLKx/RSCLKx

8.58.0ns

HFSI

TFSx/RFSx Hold After TSCLKx/RSCLKx

–1.5–1.5ns

SDRI

Receive Data Setup Before RSCLKx

8.58.0ns

HDRI

Receive Data Hold After RSCLKx

–1.5–1.5ns

Switching Characteristics

DFSI

TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated

TFSx/RFSx)

3.03.0ns

HOFSI

TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated

TFSx/RFSx)

−1.0−1.0ns

DDTI

Transmit Data Delay After TSCLKx

3.03.0ns

HDTI

Transmit Data Hold After TSCLKx

−1.0−1.0ns

SCLKIW

TSCLKx/RSCLKx Width 4.54.5ns

Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.

Applies to all nonautomotive-grade devices when operated within these voltage ranges.

All automotive-grade devices are within these specifications.

Referenced to sample edge.

Referenced to drive edge.

Rev. I|Page 40 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Figure 20. Serial Ports

Figure 21. Serial Port Start Up with External Clock and Frame Sync

tSDRI

RSCLKx

DRx

DRIVE EDGE

tHDRI

tSFSI tHFSI

tDFSI

tHOFSI

tSCLKIW

DATA RECEIVE—INTERNAL CLOCK

tSDRE

DATA RECEIVE—EXTERNAL CLOCK

RSCLKx

DRx

tHDRE

tSFSE tHFSE

tDFSE

tSCLKEW

tHOFSE

tDDTI

tHDTI

TSCLKx

TFSx

(INPUT)

DTx

tSFSI tHFSI

tSCLKIW

tDFSI

tHOFSI

DATA TRANSMIT—INTERNAL CLOCK

tDDTE

tHDTE

TSCLKx

DTx

tSFSE

tDFSE

tSCLKEW

tHOFSE

DATA TRANSMIT—EXTERNAL CLOCK

SAMPLE EDGE

DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE

DRIVE EDGE SAMPLE EDGE

tSCLKE

tHFSE

TFSx

(OUTPUT)

TFSx

(INPUT)

TFSx

(OUTPUT)

RFSx

(INPUT)

RFSx

(OUTPUT)

RFSx

(INPUT)

RFSx

(OUTPUT)

TSCLKx

(INPUT)

TFSx

(INPUT)

RFSx

(INPUT)

RSCLKx

(INPUT)

tSUDTE

tSUDRE

FIRST

TSCLKx/RSCLKx

EDGE AFTER

SPORT ENABLED

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 41 of 68 | July 2010

Table 32. Serial Ports—Enable and Three-State

Parameter MinMaxUnit

Switching Characteristics

DTENE

Data Enable Delay from External TSCLKx

0ns

DDTTE

Data Disable Delay from External TSCLKx

10.0ns

DTENI

Data Enable Delay from Internal TSCLKx

–2.0ns

DDTTI

Data Disable Delay from Internal TSCLKx

3.0ns

Referenced to drive edge.

Figure 22. Enable and Three-State

TSCLKx

DTx

DRIVE EDGE

tDDTTE/I

tDTENE/I

DRIVE EDGE

Rev. I|Page 42 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Table 33. External Late Frame Sync

Parameter MinMaxUnit

Switching Characteristics

DDTLFSE

Data Delay from Late External TFSx or External RFSx with MCMEN = 1, MFD = 0

1, 2

10.0ns

DTENLFS

Data Enable from Late FS or MCMEN = 1, MFD = 0

1, 2

0ns

MCMEN = 1, TFSx enable and TFSx valid follow t

DDTENFS

and t

DDTLFS

If external RFSx/TFSx setup to RSCLKx/TSCLKx > t

SCLKE

/2, then t

DDTE/I

and t

DTENE/I

apply, otherwise t

DDTLFSE

and t

DTENLFS

apply.

Figure 23. External Late Frame Sync

RSCLKx

RFSx

DTx

DRIVE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

EXTERNAL RFSx IN MULTI-CHANNEL MODE

1ST BIT

tDTENLFSE

tDDTLFSE

TSCLKx

TFSx

DTx

DRIVE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

LATE EXTERNAL TFSx

1ST BIT

tDDTLFSE

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 43 of 68 | July 2010

Serial Peripheral Interface Port—Master Timing

Table 34 and Figure 24 describe SPI port master operations.

Table 34. Serial Peripheral Interface (SPI) Port—Master Timing

2.25 V ≤ V

DDEXT

< 2.70 V

0.80 V ≤ V

DDINT

< 0.95 V

2.70 V ≤ V

DDEXT

≤ 3.60 V

and

0.95 V ≤ V

DDINT

≤ 1.43 V

Parameter MinMaxMinMaxUnit

Timing Requirements

SSPIDM

Data Input Valid to SCK Edge (Data Input Setup)8.77.5ns

HSPIDM

SCK Sampling Edge to Data Input Invalid –1.5–1.5ns

Switching Characteristics

SDSCIM

SPISELx Low to First SCK Edge 2 × t

SCLK

–1.52 × t

SCLK

–1.5ns

SPICHM

Serial Clock High Period 2 × t

SCLK

–1.52 × t

SCLK

–1.5ns

SPICLM

Serial Clock Low Period 2 × t

SCLK

–1.52 × t

SCLK

–1.5ns

SPICLK

Serial Clock Period 4 × t

SCLK

–1.54 × t

SCLK

–1.5ns

HDSM

Last SCK Edge to SPISELx High 2 × t

SCLK

–1.52 × t

SCLK

–1.5ns

SPITDM

Sequential Transfer Delay 2 × t

SCLK

–1.52 × t

SCLK

–1.5ns

DDSPIDM

SCK Edge to Data Out Valid (Data Out Delay)6 6ns

HDSPIDM

SCK Edge to Data Out Invalid (Data Out Hold)–1.0–1.0ns

Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.

Applies to all nonautomotive-grade devices when operated within these voltage ranges.

All automotive-grade devices are within these specifications.

Figure 24. Serial Peripheral Interface (SPI) Port—Master Timing

tSDSCIM tSPICLK tHDSM tSPITDM

tSPICLM tSPICHM

tHDSPIDM

tHSPIDM

tSSPIDM

SPIxSELy

(OUTPUT)

SPIxSCK

(OUTPUT)

SPIxMOSI

(OUTPUT)

SPIxMISO

(INPUT)

SPIxMOSI

(OUTPUT)

SPIxMISO

(INPUT)

CPHA = 1

CPHA = 0

tDDSPIDM

tHSPIDM

tSSPIDM

tHDSPIDM

tDDSPIDM

Rev. I|Page 44 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Serial Peripheral Interface Port—Slave Timing

Table 35 and Figure 25 describe SPI port slave operations.

Table 35. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter MinMaxUnit

Timing Requirements

SPICHS

Serial Clock High Period 2 × t

SCLK

–1.5ns

SPICLS

Serial Clock Low Period 2 × t

SCLK

–1.5ns

SPICLK

Serial Clock Period 4 × t

SCLK

HDS

Last SCK Edge to SPISS Not Asserted 2 × t

SCLK

–1.5ns

SPITDS

Sequential Transfer Delay 2 × t

SCLK

–1.5ns

SDSCI

SPISS Assertion to First SCK Edge 2 × t

SCLK

–1.5ns

SSPID

Data Input Valid to SCK Edge (Data Input Setup)1.6ns

HSPID

SCK Sampling Edge to Data Input Invalid 1.6ns

Switching Characteristics

DSOE

SPISS Assertion to Data Out Active08ns

DSDHI

SPISS Deassertion to Data High Impedance 08ns

DDSPID

SCK Edge to Data Out Valid (Data Out Delay)10ns

HDSPID

SCK Edge to Data Out Invalid (Data Out Hold)0ns

Figure 25. Serial Peripheral Interface (SPI) Port—Slave Timing

tSPICLK tHDS tSPITDS

tSDSCI tSPICLS tSPICHS

tDSOE tDDSPID

tDDSPID tDSDHI

tHDSPID

tSSPID

tDSDHI

tHDSPID

tDSOE

tHSPID

tSSPID

tDDSPID

SPIxSS

(INPUT)

SPIxSCK

(INPUT)

SPIxMISO

(OUTPUT)

SPIxMOSI

(INPUT)

SPIxMISO

(OUTPUT)

SPIxMOSI

(INPUT)

CPHA = 1

CPHA = 0

tHSPID

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 45 of 68 | July 2010

General-Purpose Port Timing

Table 36 and Figure 26 describe general-purpose

port operations.

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

For information on the UART port receive and transmit opera-

tions, see the ADSP-BF537 Blackfin Processor Hardware

Reference.

Table 36. General-Purpose Port Timing

Parameter MinMaxUnit

Timing Requirement

WFI

General-Purpose Port Pin Input Pulse Width t

SCLK

+ 1 ns

Switching Characteristic

GPOD

General-Purpose Port Pin Output Delay from CLKOUT Low 06ns

Figure 26. General-Purpose Port Timing

CLKOUT

GPIO OUTPUT

GPIO INPUT

tWFI

tGPOD

Rev. I|Page 46 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Timer Clock Timing

Table 37 and Figure 27 describe timer clock timing.

Timer Cycle Timing

Table 38 and Figure 28 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of (f

SCLK

/2) MHz.

Table 37. Timer Clock Timing

Parameter MinMaxUnit

Switching Characteristic

TODP

Timer Output Update Delay After PPI_CLK High 12 ns

Figure 27. Timer Clock Timing

PPI_CLK

TMRx OUTPUT

tTODP

Table 38. Timer Cycle Timing

2.25 V ≤ V

DDEXT

< 2.70 V

0.80 V ≤ V

DDINT

< 0.95 V

2.70 V ≤ V

DDEXT

≤ 3.60 V

and

0.95 V ≤ V

DDINT

≤ 1.43 V

Parameter MinMaxMinMaxUnit

Timing Characteristics

Timer Pulse Width Input Low (Measured In SCLK Cycles)

1 × t

SCLK

1 × t

SCLK

Timer Pulse Width Input High (Measured In SCLK Cycles)

1 × t

SCLK

1 × t

SCLK

TIS

Timer Input Setup Time Before CLKOUT Low

5.55.0ns

TIH

Timer Input Hold Time After CLKOUT Low

1.51.5ns

Switching Characteristics

HTO

Timer Pulse Width Output (Measured In SCLK Cycles)1 × t

SCLK

–1) × t

SCLK

1 × t

SCLK

–1) × t

SCLK

TOD

Timer Output Update Delay After CLKOUT High 6.56.0ns

Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.

Applies to all nonautomotive-grade devices when operated within these voltage ranges.

All automotive-grade devices are within these specifications.

The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.

Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

Figure 28. Timer Cycle Timing

CLKOUT

TMRx OUTPUT

TMRx INPUT

tTIS tTIH

tWH,tWL

tTOD

tHTO

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 47 of 68 | July 2010

JTAG Test and Emulation Port Timing

Table 39 and Figure 29 describe JTAG port operations.

Table 39. JTAG Port Timing

Parameter MinMaxUnit

Timing Parameters

TCK

TCK Period 20 ns

STAP

TDI, TMS Setup Before TCK High 4ns

HTAP

TDI, TMS Hold After TCK High 4ns

SSYS

System Inputs Setup Before TCK High

4ns

HSYS

System Inputs Hold After TCK High

5ns

TRSTW

TRST Pulse Width

(Measured in TCK Cycles)4TCK

Switching Characteristics

DTDO

TDO Delay From TCK Low 10 ns

DSYS

System Outputs Delay After TCK Low

012ns

System Inputs = DATA15–0, BR, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH15–0, MDIO, TCK, TRST, RESET, NMI, RTXI,

BMODE2–0.

50 MHz maximum

System Outputs = DATA15–0, ADDR19–1, ABE1–0, BG, BGH, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, MDC, MDIO,

TSCLK0, TFS0, RFS0, RSCLK0, DT0PRI, DT0SEC, PF15–0, PG15–0, PH15–0, RTXO, TDO, EMU, XTAL, VROUT1–0.

Figure 29. JTAG Port Timing

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP tHTAP

tDTDO

tSSYS tHSYS

tDSYS

Rev. I|Page 48 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

10/100 Ethernet MAC Controller Timing

Table 40 through Table 45 and Figure 30 through Figure 35

describe the 10/100 Ethernet MAC controller operations. This

feature is only available on the ADSP-BF536 and ADSP-BF537

processors.

Table 40. 10/100 Ethernet MAC Controller Timing: MII Receive Signal

Parameter

MinMaxUnit

ERXCLK

ERxCLK Frequency (f

SCLK

= SCLK Frequency)None 25 + 1%

SCLK

+ 1%

MHz

ERXCLKW

ERxCLK Width (t

ERxCLK

= ERxCLK Period)t

ERxCLK

× 35% t

ERxCLK

× 65% ns

ERXCLKIS

Rx Input Valid to ERxCLK Rising Edge (Data In Setup)7.5ns

ERXCLKIH

ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)7.5ns

MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.

Table 41. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

Parameter

MinMaxUnit

ETXCLK

ETxCLK Frequency (f

SCLK

= SCLK Frequency)None 25 + 1%

SCLK

+ 1%

MHz

ETXCLKW

ETxCLK Width (t

ETXCLK

= ETxCLK Period)t

ETxCLK

× 35% t

ETxCLK

× 65% ns

ETXCLKOV

ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)20ns

ETXCLKOH

ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold)0 ns

MII outputs synchronous to ETxCLK are ETxD3–0.

Table 42. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

Parameter

MinMaxUnit

REFCLK

REF_CLK Frequency (f

SCLK

= SCLK Frequency)None 50 + 1%

2 × f

SCLK

+ 1%

MHz

REFCLKW

REF_CLK Width (t

REFCLK

= REFCLK Period)t

REFCLK

× 35% t

REFCLK

× 65% ns

REFCLKIS

Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup)4 ns

REFCLKIH

RMII REF_CLK Rising Edge to Rx Input Invalid (Data In Hold)2 ns

RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.

Table 43. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

Parameter

MinMaxUnit

REFCLKOV

RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid)7.5ns

REFCLKOH

RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)2 ns

RMII outputs synchronous to RMII REF_CLK are ETxD1–0.

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 49 of 68 | July 2010

Table 44. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal

Parameter

1, 2

MinMaxUnit

ECOLH

COL Pulse Width High t

ETxCLK

× 1.5

ERxCLK

× 1.5

ECOLL

COL Pulse Width Low t

ETxCLK

× 1.5

ERxCLK

× 1.5

ECRSH

CRS Pulse Width High t

ETxCLK

× 1.5ns

ECRSL

CRS Pulse Width Low t

ETxCLK

× 1.5ns

MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both

the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.

The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.

Table 45. 10/100 Ethernet MAC Controller Timing: MII Station Management

Parameter

MinMaxUnit

MDIOS

MDIO Input Valid to MDC Rising Edge (Setup)10ns

MDCIH

MDC Rising Edge to MDIO Input Invalid (Hold)10ns

MDCOV

MDC Falling Edge to MDIO Output Valid 25 ns

MDCOH

MDC Falling Edge to MDIO Output Invalid (Hold)–1ns

MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple

of the system clock SCLK. MDIO is a bidirectional data line.

Figure 30. 10/100 Ethernet MAC Controller Timing: MII Receive Signal

Figure 31. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

tERXCLKIS tERXCLKIH

ERxD3–0

ERxDV

ERxER

ERx_CLK

tERXCLKW

tERXCLK

tETXCLKOH

ETxD3–0

ETxEN

MIITxCLK

tETXCLK

tETXCLKOV

tETXCLKW

Rev. I|Page 50 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Figure 32. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

Figure 33. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

Figure 34. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal

Figure 35. 10/100 Ethernet MAC Controller Timing: MII Station Management

tREFCLKIS tREFCLKIH

ERxD1–0

ERxDV

ERxER

RMII_REF_CLK

tREFCLKW

tREFCLK

tREFCLKOV

tREFCLKOH

RMII_REF_CLK

ETxD1–0

ETxEN

tREFCLK

MIICRS, COL

tECRSH

tECOLH

tECRSL

tECOLL

MDIO (INPUT)

MDIO (OUTPUT)

MDC (OUTPUT)

tMDIOS

tMDCOH

tMDCIH

tMDCOV

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 51 of 68 | July 2010

OUTPUT DRIVE CURRENTS

Figure 36 through Figure 47 show typical current-voltage char-

acteristics for the output drivers of the processors. The curves

represent the current drive capability of the output drivers as a

function of output voltage. See Table 9 on Page 20 for informa-

tion about which driver type corresponds to a particular pin.

Figure 36. Drive Current A (Low V

DDEXT

)

Figure 37. Drive Current A (High V

DDEXT

)

Figure 38. Drive Current B (Low V

DDEXT

)

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0

100

-80

-60

-40

-20

120

- 100

VDDEXT = 2.25V @ 95°C

VDDEXT = 2.50V @ 25°C

VDDEXT = 2.75V @

40°C

VOL

VOH

SOURCECURRENT(mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

150

100

150

100

4.0

DDEXT

= 3.0V @ 95°C

DDEXT

= 3.3V @ 25°C

DDEXT

=3.6V@

40°C

SOURCECURRENT(mA)

SOURCE VOLTAGE (V)

00.51.01.52.02.53.0

150

100

150

VOL

VOH

100

VDDEXT =2.25V@95°C

VDDEXT =2.50V@25°C

VDDEXT =2.75V@

40°C

Figure 39. Drive Current B (High V

DDEXT

)

Figure 40. Drive Current C (Low V

DDEXT

)

Figure 41. Drive Current C (High V

DDEXT

)

SOURCECURRENT(mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

150

100

200

150

4.0

100

200

DDEXT

=3.0V@95°C

DDEXT

=3.3V@25°C

DDEXT

=3.6V@

40°C

SOURCECURRENT(mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0

DDEXT

= 2.25V @ 95°C

DDEXT

= 2.50V @ 25°C

DDEXT

=2.75V@

40°C

SOURCECURRENT(mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

4.0

100

DDEXT

=3.0V@95°C

DDEXT

=3.3V@25°C

DDEXT

=3.6V@

40°C

Rev. I|Page 52 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Figure 42. Drive Current D (Low V

DDEXT

)

Figure 43. Drive Current D (High V

DDEXT

)

Figure 44. Drive Current E (Low V

DDEXT

)

SOURCECURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0

100

DDEXT

=2.25V@95°C

DDEXT

=2.50V@25°C

DDEXT

=2.75V@

40°C

SOURCECURRENT(mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

100

150

4.0

100

150

DDEXT

=3.0V@95°C

DDEXT

=3.3V@25°C

DDEXT

=3.6V@

40°C

SOURCECURRENT(mA)

SOURCE VOLTAGE (V)

00.5 1.0 1.5 2.0 2.5 3.0

DDEXT

= 2.25V @ 95°C

DDEXT

= 2.50V @ 25°C

DDEXT

=2.75V@

40°C

Figure 45. Drive Current E (High V

DDEXT

)

Figure 46. Drive Current F (Low V

DDEXT

)

Figure 47. Drive Current F (High V

DDEXT

)

SOURCECURRENT(mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

DDEXT

=3.0V@95°C

DDEXT

=3.3V@25°C

DDEXT

=3.6V@

40°C

4.0

SOURCECURRENT(mA)

SOURCE VOLTAGE (V)

00.51.01.52.02.53.0

DDEXT

=2.25V@95°C

DDEXT

=2.50V@25°C

DDEXT

=2.75V@

40°C

SOURCECURRENT(mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

4.0

DDEXT

=3.0V@95°C

DDEXT

=3.3V@25°C

DDEXT

=3.6V@

40°C

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 53 of 68 | July 2010

TEST CONDITIONS

All timing parameters appearing in this data sheet were

measured under the conditions described in this section.

Figure 48 shows the measurement point for ac measurements

(other than output enable/disable). The measurement point is

MEAS

= V

DDEXT

/2.

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving. The output enable time t

ENA

is the interval from

the point when a reference signal reaches a high or low voltage

level to the point when the output starts driving as shown in the

Output Enable/Disable diagram (Figure 49). The time

ENA_MEASURED

is the interval from when the reference signal

switches to when the output voltage reaches 2.0 V (output high)

or 1.0 V (output low). Time t

TRIP

is the interval from when the

output starts driving to when the output reaches the 1.0 V or

2.0 V trip voltage. Time t

ENA

is calculated as shown in

the equation:

If multiple pins (such as the data bus) are enabled, the measure-

ment value is that of the first pin to start driving.

Output Disable Time

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

to decay by ΔV is dependent on the capacitive load, C

, and the

load current, I

. This decay time can be approximated by

the equation:

The output disable time t

DIS

is the difference between

DIS_MEASURED

and t

DECAY

as shown in Figure 49. The time

DIS_MEASURED

is the interval from when the reference signal

switches to when the output voltage decays ΔV from the mea-

sured output-high or output-low voltage. The time t

DECAY

calculated with the test loads C

and I

, and with ΔV

equal to 0.5 V.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t

DECAY

using the equation given above. Choose ΔV

to be the difference between the processor’s output voltage and

the input threshold for the device requiring the hold time. A

typical ΔV is 0.4 V. C

is the total bus capacitance (per data line),

and I

is the total leakage or three-state current (per data line).

The hold time is t

DECAY

plus the minimum disable time (for

example, t

DSDAT

for an SDRAM write cycle).

Figure 48. Voltage Reference Levels for AC Measurements (Except

Output Enable/Disable)

INPUT

OUTPUT

MEAS

tENA tENA_MEASURED tTRIP

–=

Figure 49. Output Enable/Disable

tDECAY CLVΔ()IL

⁄=

REFERENCE

SIGNAL

tDIS

OUTPUT STARTS DRIVING

VOH (MEASURED)  V

VOL (MEASURED) + V

tDIS_MEASURED

VOH

(MEASURED)

VOL

(MEASURED)

VTRIP(HIGH)

VOH(MEASURED

)

VOL(MEASURED)

HIGH IMPEDANCE STATE

OUTPUT STOPS DRIVING

tENA

tDECAY

tENA_MEASURED

tTRIP

VTRIP(LOW)

Rev. I|Page 54 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Capacitive Loading

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 50). Figure 51 through Figure 60 on

Page 56 show how output rise time varies with capacitance. The

delay and hold specifications given should be derated by a factor

derived from these figures. The graphs in these figures may not

be linear outside the ranges shown.

Figure 50. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

ZO = 50Ω (impedance)

TD = 4.04 ± 1.18 ns

2pF

TESTER PIN ELECTRONICS

50Ω

0.5pF

70Ω

400Ω

45Ω

4pF

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

LOAD

DUT

OUTPUT

50Ω

Figure 51. Typical Output Delay or Hold for Driver A at V

DDEXT

Min

Figure 52. Typical Output Delay or Hold for Driver A at V

DDEXT

Max

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10%to90%)

0 50 100 150 200 250

FALL TIME

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 55 of 68 | July 2010

Figure 53. Typical Output Delay or Hold for Driver B at V

DDEXT

Min

Figure 54. Typical Output Delay or Hold for Driver B at V

DDEXT

Max

Figure 55. Typical Output Delay or Hold for Driver C at V

DDEXT

Min

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

Figure 56. Typical Output Delay or Hold for Driver C at V

DDEXT

Max

Figure 57. Typical Output Delay or Hold for Driver D at V

DDEXT

Min

Figure 58. Typical Output Delay or Hold for Driver D at V

DDEXT

Max

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

Rev. I|Page 56 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Figure 59. Typical Output Delay or Hold for Driver E at V

DDEXT

Min

Figure 60. Typical Output Delay or Hold for Driver E at V

DDEXT

Max

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

Figure 61. Typical Output Delay or Hold for Driver F at V

DDEXT

Min

Figure 62. Typical Output Delay or Hold for Driver F at V

DDEXT

Max

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

LOAD CAPACITANCE (pF)

RISE TIME

RISE AND FALL TIME ns (10% to 90%)

0 50 100 150 200 250

FALL TIME

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 57 of 68 | July 2010

THERMAL CHARACTERISTICS

To determine the junction temperature on the application

printed circuit board use:

where:

= Junction temperature (°C)

CASE

= Case temperature (°C) measured by customer at top

center of package.

= From Table 46

= Power dissipation (see the power dissipation discussion

and the tables on Page 28 for the method to calculate P

Values of θ

are provided for package comparison and printed

circuit board design considerations. θ

can be used for a first

order approximation of T

by the equation:

where:

= Ambient temperature (°C)

Values of θ

are provided for package comparison and printed

circuit board design considerations when an external heat sink

is required. Values of θ

are provided for package comparison

and printed circuit board design considerations.

In Table 46 through Table 48, airflow measurements comply

with JEDEC standards JESD51-2 and JESD51-6, and the junc-

tion-to-board measurement complies with JESD51-8. Test

board and thermal via design comply with JEDEC standards

JESD51-9 (BGA). The junction-to-case measurement complies

with MIL-STD-883 (Method 1012.1). All measurements use a

2S2P JEDEC test board.

Industrial applications using the 208-ball BGA package require

thermal vias, to an embedded ground plane, in the PCB. Refer to

JEDEC standard JESD51-9 for printed circuit board thermal

ball land and thermal via design information.

TJTCASE ΨJT PD

×()+=

TJTAθJA PD

×()+=

Table 46. Thermal Characteristics (182-Ball BGA)

Parameter ConditionTypical Unit

0 Linear m/s Airflow 32.80 °C/W

JMA

1 Linear m/s Airflow 29.30 °C/W

JMA

2 Linear m/s Airflow 28.00 °C/W

20.10 °C/W

7.92 °C/W

0 Linear m/s Airflow 0.19 °C/W

1 Linear m/s Airflow 0.35 °C/W

2 Linear m/s Airflow 0.45 °C/W

Table 47. Thermal Characteristics (208-Ball BGA without

Thermal Vias in PCB)

Parameter ConditionTypical Unit

0 Linear m/s Airflow 23.30 °C/W

JMA

1 Linear m/s Airflow 20.20 °C/W

JMA

2 Linear m/s Airflow 19.20 °C/W

13.05 °C/W

6.92 °C/W

0 Linear m/s Airflow 0.18 °C/W

1 Linear m/s Airflow 0.27 °C/W

2 Linear m/s Airflow 0.32 °C/W

Table 48. Thermal Characteristics (208-Ball BGA with

Thermal Vias in PCB)

Parameter ConditionTypical Unit

0 Linear m/s Airflow 22.60 °C/W

JMA

1 Linear m/s Airflow 19.40 °C/W

JMA

2 Linear m/s Airflow 18.40 °C/W

13.20 °C/W

6.85 °C/W

0 Linear m/s Airflow 0.16 °C/W

1 Linear m/s Airflow 0.27 °C/W

2 Linear m/s Airflow 0.32 °C/W

Rev. I|Page 58 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

182-BALL CSP_BGA BALL ASSIGNMENT

Table 49 lists the CSP_BGA ball assignment by signal mne-

monic. Table 50 on Page 59 lists the CSP_BGA ball assignment

by ball number.

Table 49. 182-Ball CSP_BGA Ball Assignment (Alphabetically by Signal Mnemonic)

Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No.

ABE0 H13 CLKOUT B14 GNDL6 PG8 E3 SRAS D13

ABE1 H12 DATA0M9 GNDL8 PG9 E4 SWE D12

ADDR1 J14 DATA1N9 GNDL10 PH0 C2TCKP2

ADDR10 M13 DATA10 N6 GNDM4 PH1 C3TDIM3

ADDR11 M14 DATA11 P6 GNDM10 PH10 B6 TDON3

ADDR12 N14 DATA12 M5 GNDP14 PH11 A2TMSN2

ADDR13 N13 DATA13 N5 NMI B10 PH12 A3TRSTN1

ADDR14 N12 DATA14 P5 PF0 M1 PH13 A4V

DDEXT

ADDR15 M11 DATA15 P4 PF1 L1 PH14 A5V

DDEXT

C12

ADDR16 N11 DATA2P9 PF10 J2 PH15 A6V

DDEXT

ADDR17 P13 DATA3M8 PF11 J3 PH2 C4V

DDEXT

E11

ADDR18 P12 DATA4N8 PF12 H1 PH3 C5V

DDEXT

ADDR19 P11 DATA5P8 PF13 H2 PH4 C6V

DDEXT

F12

ADDR2 K14 DATA6M7 PF14 H3 PH5 B1 V

DDEXT

ADDR3 L14 DATA7N7 PF15 H4 PH6 B2 V

DDEXT

H10

ADDR4 J13 DATA8 P7 PF2 L2 PH7 B3 V

DDEXT

J11

ADDR5 K13 DATA9 M6 PF3 L3 PH8 B4 V

DDEXT

J12

ADDR6 L13 EMU M2 PF4 L4 PH9 B5 V

DDEXT

ADDR7 K12 GNDA10 PF5 K1 PJ0 C7V

DDEXT

ADDR8 L12 GNDA14 PF6 K2 PJ1 B7 V

DDEXT

ADDR9 M12 GNDD4PF7K3PJ10D10 V

DDEXT

AMS0E14 GNDE7 PF8 K4 PJ11 D11 V

DDEXT

L11

AMS1F14 GNDE9 PF9 J1 PJ2 B11 V

DDEXT

AMS2F13 GNDF5 PG0 G1 PJ3 C11 V

DDINT

AMS3G12 GNDF6 PG1 G2 PJ4 D7V

DDINT

AOE G13 GNDF10 PG10 D1PJ5D8V

DDINT

E10

ARDYE13 GNDF11 PG11 D2PJ6C8V

DDINT

G10

ARE G14 GNDG4 PG12 D3PJ7B8V

DDINT

AWE H14 GNDG5 PG13 D5PJ8D9V

DDINT

BG P10 GNDG11 PG14 D6PJ9C9V

DDINT

K10

BGH N10 GNDH11 PG15 C1RESET C10 V

DDRTC

BMODE0 N4 GNDJ4 PG2 G3 RTXO A8VROUT0A13

BMODE1 P3 GNDJ5 PG3 F1 RTXI A9VROUT1B12

BMODE2 L5 GNDJ9 PG4 F2 SA10 E12 XTALA11

BR D14 GNDJ10 PG5 F3 SCAS C14

CLKBUF A7GNDK6 PG6 E1 SCKE B13

CLKIN A12 GNDK11 PG7 E2 SMSC13

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 59 of 68 | July 2010

Table 50. 182-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)

Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic

A1V

DDEXT

C10 RESET F5 GNDJ14 ADDR1 M9 DATA0

A2PH11C11 PJ3 F6 GNDK1 PF5 M10 GND

A3PH12C12 V

DDEXT

F10 GNDK2 PF6 M11 ADDR15

A4PH13C13 SMSF11 GNDK3 PF7 M12 ADDR9

A5PH14C14 SCAS F12 V

DDEXT

K4 PF8 M13 ADDR10

A6PH15D1PG10F13AMS2K5 V

DDINT

M14 ADDR11

A7CLKBUF D2PG11F14AMS1K6 GNDN1 TRST

A8RTXOD3 PG12 G1 PG0 K7 V

DDEXT

N2 TMS

A9RTXID4GNDG2 PG1 K8 V

DDINT

N3 TDO

A10 GNDD5 PG13 G3 PG2 K9 V

DDEXT

N4 BMODE0

A11 XTALD6PG14G4GNDK10 V

DDINT

N5 DATA13

A12 CLKIN D7 PJ4 G5 GNDK11 GNDN6 DATA10

A13 VROUT0 D8PJ5G10V

DDINT

K12 ADDR7 N7 DATA7

A14 GNDD9PJ8G11GNDK13 ADDR5 N8 DATA4

B1 PH5 D10 PJ10 G12 AMS3K14 ADDR2 N9 DATA1

B2 PH6 D11 PJ11 G13 AOE L1 PF1 N10 BGH

B3 PH7 D12 SWE G14 ARE L2 PF2 N11 ADDR16

B4 PH8 D13 SRAS H1 PF12 L3 PF3 N12 ADDR14

B5 PH9 D14 BR H2 PF13 L4 PF4 N13 ADDR13

B6 PH10 E1 PG6 H3 PF14 L5 BMODE2 N14 ADDR12

B7 PJ1 E2 PG7 H4 PF15 L6 GNDP1 V

DDEXT

B8 PJ7 E3 PG8 H5 V

DDEXT

L7 V

DDEXT

P2 TCK

B9 V

DDRTC

E4 PG9 H10 V

DDEXT

L8 GNDP3 BMODE1

B10 NMI E5 V

DDINT

H11 GNDL9 V

DDEXT

P4 DATA15

B11 PJ2 E6 V

DDEXT

H12 ABE1 L10 GNDP5 DATA14

B12 VROUT1 E7 GNDH13 ABE0 L11 V

DDEXT

P6 DATA11

B13 SCKE E8 V

DDINT

H14 AWE L12 ADDR8 P7 DATA8

B14 CLKOUT E9 GNDJ1 PF9 L13 ADDR6 P8 DATA5

C1PG15E10V

DDINT

J2 PF10 L14 ADDR3 P9 DATA2

C2PH0E11V

DDEXT

J3 PF11 M1 PF0 P10 BG

C3PH1E12SA10 J4 GNDM2 EMU P11 ADDR19

C4PH2E13ARDYJ5 GNDM3 TDIP12ADDR18

C5PH3E14AMS0J9 GNDM4 GNDP13 ADDR17

C6PH4F1PG3J10GNDM5 DATA12 P14 GND

C7PJ0F2PG4J11V

DDEXT

M6 DATA9

C8PJ6F3PG5J12V

DDEXT

M7 DATA6

C9PJ9F4V

DDEXT

J13 ADDR4 M8 DATA3

Rev. I|Page 60 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Figure 63 shows the top view of the CSP_BGA

ball configuration. Figure 64 shows the bottom view of the

CSP_BGA ball configuration.

Figure 63. 182-Ball CSP_BGA Configuration (Top View)

1234567891011121314

VDDINT

VDDEXT

GND

I/O

KEY:

VROUT

VDDRTC

Figure 64. 182-Ball CSP_BGA Configuration (Bottom View)

1234567891011121314

VDDINT

VDDEXT

GND

I/O

KEY:

VROUT

VDDRTC

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 61 of 68 | July 2010

208-BALL CSP_BGA BALL ASSIGNMENT

Table 51 lists the CSP_BGA ball assignment by signal mne-

monic. Table 52 on Page 62 lists the CSP_BGA ball assignment

by ball number.

Table 51. 208-Ball CSP_BGA Ball Assignment (Alphabetically by Signal Mnemonic)

Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No.

ABE0 P19 DATA12 Y4 GNDM13 PG6 E2 TDIV1

ABE1 P20 DATA13 W4 GNDN9 PG7 D1TDOY2

ADDR1 R19 DATA14 Y3 GNDN10 PG8 D2TMSU2

ADDR10 W18 DATA15 W3 GNDN11 PG9 C1TRSTU1

ADDR11 Y18 DATA2Y9 GNDN12 PH0 B4 V

DDEXT

ADDR12 W17 DATA3W9 GNDN13 PH1 A5V

DDEXT

ADDR13 Y17 DATA4Y8 GNDP11 PH10 B9 V

DDEXT

ADDR14 W16 DATA5W8 GNDV2 PH11 A10 V

DDEXT

G10

ADDR15 Y16 DATA6Y7 GNDW2 PH12 B10 V

DDEXT

ADDR16 W15 DATA7W7 GNDW19 PH13 A11 V

DDEXT

ADDR17 Y15 DATA8Y6 GNDY1 PH14 B11 V

DDEXT

ADDR18 W14 DATA9W6 GNDY13 PH15 A12 V

DDEXT

ADDR19 Y14 EMU T1 GNDY20 PH2 B5 V

DDEXT

ADDR2 T20 GNDA1NMIC20 PH3 A6V

DDEXT

ADDR3 T19 GNDA13 PF0 T2 PH4 B6 V

DDEXT

ADDR4 U20 GNDA20 PF1 R1 PH5 A7V

DDEXT

ADDR5 U19 GNDB2 PF10 L2 PH6 B7 V

DDEXT

ADDR6 V20 GNDG11 PF11 K1 PH7 A8V

DDEXT

ADDR7 V19 GNDH9 PF12 K2 PH8 B8 V

DDEXT

ADDR8 W20 GNDH10 PF13 J1 PH9 A9V

DDEXT

ADDR9 Y19 GNDH11 PF14 J2 PJ0 B12 V

DDEXT

AMS0M20 GNDH12 PF15 H1 PJ1 B13 V

DDEXT

AMS1M19 GNDH13 PF2 R2 PJ10 B19 V

DDEXT

AMS2G20 GNDJ9 PF3 P1 PJ11 C19 V

DDEXT

P10

AMS3G19 GNDJ10 PF4 P2 PJ2 D19 V

DDINT

G12

AOE N20 GNDJ11 PF5 N1 PJ3 E19 V

DDINT

G13

ARDYJ19 GNDJ12 PF6 N2 PJ4 B18 V

DDINT

G14

ARE N19 GNDJ13 PF7 M1 PJ5 A19 V

DDINT

H14

AWE R20 GNDK9 PF8 M2 PJ6 B15 V

DDINT

J14

BG Y11 GNDK10 PF9 L1 PJ7 B16 V

DDINT

K14

BGH Y12 GNDK11 PG0 H2 PJ8 B17 V

DDINT

L14

BMODE0 W13 GNDK12 PG1 G1 PJ9 B20 V

DDINT

M14

BMODE1 W12 GNDK13 PG10 C2RESET D20 V

DDINT

N14

BMODE2 W11 GNDL9 PG11 B1 RTXO A15 V

DDINT

P12

BR F19 GNDL10 PG12 A2RTXIA14 V

DDINT

P13

CLKBUF B14 GNDL11 PG13 A3SA10 L20 V

DDINT

P14

CLKIN A18 GNDL12 PG14 B3 SCAS K20 V

DDRTC

A16

CLKOUT H19 GNDL13 PG15 A4SCKE H20 VROUT0 E20

DATA0Y10 GNDM9 PG2 G2 SMSJ20 VROUT1 F20

DATA1W10 GNDM10 PG3 F1 SRAS K19 XTALA17

DATA10 Y5 GNDM11 PG4 F2 SWE L19

DATA11 W5 GNDM12 PG5 E1 TCKW1

Rev. I|Page 62 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

Table 52 lists the CSP_BGA ball assignment by ball number.

Table 51 on Page 61 lists the CSP_BGA ball assignment by sig-

nal mnemonic.

Table 52. 208-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)

Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic

A1GNDC19 PJ11 J9 GNDM19 AMS1W1 TCK

A2PG12C20 NMI J10 GNDM20 AMS0W2 GND

A3PG13D1PG7J11GNDN1 PF5 W3 DATA15

A4PG15D2PG8J12GNDN2 PF6 W4 DATA13

A5PH1D19 PJ2 J13 GNDN7 V

DDEXT

W5 DATA11

A6PH3D20 RESET J14 V

DDINT

N8 V

DDEXT

W6 DATA9

A7 PH5 E1 PG5 J19 ARDYN9 GNDW7 DATA7

A8 PH7 E2 PG6 J20 SMSN10 GNDW8 DATA5

A9 PH9 E19 PJ3 K1 PF11 N11 GNDW9 DATA3

A10 PH11 E20 VROUT0 K2 PF12 N12 GNDW10 DATA1

A11 PH13 F1 PG3 K7 V

DDEXT

N13 GNDW11 BMODE2

A12 PH15 F2 PG4 K8 V

DDEXT

N14 V

DDINT

W12 BMODE1

A13 GNDF19 BR K9 GNDN19 ARE W13 BMODE0

A14 RTXI F20 VROUT1 K10 GNDN20 AOE W14 ADDR18

A15 RTXO G1 PG1 K11 GNDP1 PF3 W15 ADDR16

A16 V

DDRTC

G2 PG2 K12 GNDP2 PF4 W16 ADDR14

A17 XTALG7 V

DDEXT

K13 GNDP7 V

DDEXT

W17 ADDR12

A18 CLKIN G8 V

DDEXT

K14 V

DDINT

P8 V

DDEXT

W18 ADDR10

A19 PJ5 G9 V

DDEXT

K19 SRAS P9 V

DDEXT

W19 GND

A20 GNDG10 V

DDEXT

K20 SCAS P10 V

DDEXT

W20 ADDR8

B1 PG11 G11 GNDL1 PF9 P11 GNDY1 GND

B2 GNDG12 V

DDINT

L2 PF10 P12 V

DDINT

Y2 TDO

B3 PG14 G13 V

DDINT

L7 V

DDEXT

P13 V

DDINT

Y3 DATA14

B4 PH0 G14 V

DDINT

L8 V

DDEXT

P14 V

DDINT

Y4 DATA12

B5 PH2 G19 AMS3L9 GNDP19 ABE0 Y5 DATA10

B6 PH4 G20 AMS2L10 GNDP20 ABE1 Y6 DATA8

B7 PH6 H1 PF15 L11 GNDR1 PF1 Y7 DATA6

B8 PH8 H2 PG0 L12 GNDR2 PF2 Y8 DATA4

B9 PH10 H7 V

DDEXT

L13 GNDR19 ADDR1 Y9 DATA2

B10 PH12 H8 V

DDEXT

L14 V

DDINT

R20 AWE Y10 DATA0

B11 PH14 H9 GNDL19 SWE T1 EMU Y11 BG

B12 PJ0 H10 GNDL20 SA10 T2 PF0 Y12 BGH

B13 PJ1 H11 GNDM1 PF7 T19 ADDR3 Y13 GND

B14 CLKBUF H12 GNDM2 PF8 T20 ADDR2 Y14 ADDR19

B15 PJ6 H13 GNDM7 V

DDEXT

U1 TRSTY15 ADDR17

B16 PJ7 H14 V

DDINT

M8 V

DDEXT

U2 TMSY16 ADDR15

B17 PJ8 H19 CLKOUT M9 GNDU19 ADDR5 Y17 ADDR13

B18 PJ4 H20 SCKE M10 GNDU20 ADDR4 Y18 ADDR11

B19 PJ10 J1 PF13 M11 GNDV1 TDIY19ADDR9

B20 PJ9 J2 PF14 M12 GNDV2 GNDY20 GND

C1PG9J7 V

DDEXT

M13 GNDV19 ADDR7

C2PG10J8 V

DDEXT

M14 V

DDINT

V20 ADDR6

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 63 of 68 | July 2010

Figure 65 shows the top view of the CSP_BGA ball configura-

tion. Figure 66 shows the bottom view of the CSP_BGA ball

configuration.

Figure 65. 208-Ball CSP_BGA Configuration (Top View)

1234567891011121314 161718192015

DDINT

DDEXT

GND

I/O

KEY:

ROUT

DDRTC

Figure 66. 208-Ball CSP_BGA Configuration (Bottom View)

20 19 18 17 16 15 14 13 12 11 10 9 8 7 5 4 3 2 16

DDINT

DDEXT

GND

I/O

KEY:

ROUT

DDRTC

Rev. I|Page 64 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

OUTLINE DIMENSIONS

Dimensions in Figure 67 and Figure 68 are shown in

millimeters.

Figure 67. 182-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-182)

Dimensions shown in millimeters

DETAIL A

0.50

0.45

0.40

1.31

1.21

1.10

14 13 12 11 10 8 7 6 3 2 1954

A1 CORNER

INDEX AREA

TOP VIEW BOTTOM VIEW

1.70 MAX

12.00 BSC SQ

(BALL

DIAMETER)

SEATING

PLANE

0.25 MIN

0.12

COPLANARITY

PIN A1

INDICATOR

LOCATION

NOTES:

0.80

BSC

TYP

1. COMPLIANT TO JEDEC STANDARD MO-205-AE,

EXCEPT FOR BALL DIAMETER.

2. CENTER DIMENSIONS ARE NOMINAL.

3. THE ACTUAL POSITION OF THE BALL GRID IS

WITHIN 0.15 OF ITS IDEAL POSITION RELATIVE

TO THE PACKAGE EDGES

10.40

BSC

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 65 of 68 | July 2010

Figure 68. 208-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-208-2)

Dimensions shown in millimeters

*COMPLIANT TO JEDEC STANDARDS MO-205-AM WITH

EXCEPTION TO PACKAGE HEIGHT AND BALL DIAMETER.

0.80

BSC

15 14

1716

19 1820 13 12 11 10 987654321

BOTTOM VIEW

15.20

BSC SQ

A1 CORNER

INDEX AREA

COPLANARITY

0.12

DETAIL A

*0.50

0.45

0.40

0.35 NOM

0.30 MIN

BALL

DIAMETER

TOP VIEW

A1 BALL

CORNER

DETAIL A

SEATING

PLANE

17.10

17.00 SQ

16.90

*1.75

1.61

1.46

1.36

1.26

1.16

Rev. I|Page 66 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

SURFACE-MOUNT DESIGN

The following table is provided as an aid to PCB design. For

industry-standard design recommendations, refer to IPC-7351,

Generic Requirements for Surface Mount Design and Land Pat-

tern Standard.

PackagePackage Ball Attach Type

Package Solder Mask

Opening Package Ball Pad Size

182-Ball CSP_BGA (BC-182) Solder Mask Defined 0.40 mm diameter 0.55 mm diameter

208-Ball CSP_BGA (BC-208-2) Solder Mask Defined 0.40 mm diameter 0.55 mm diameter

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. I|Page 67 of 68 | July 2010

AUTOMOTIVE PRODUCTS

The ADBF534W model is available with controlled manufactur-

ing to support the quality and reliability requirements of

automotive applications. Note that these automotive models

may have specifications that differ from the commercial models

and designers should review the Specifications section of this

data sheet carefully. Only the automotive grade products shown

in Table 53 are available for use in automotive applications.

Contact your local ADI account representative for specific

product ordering information and to obtain the specific Auto-

motive Reliability reports for these models.

Table 53. Automotive Products

Product Family

1,2

Temperature Range

Speed Grade (Max)Package Description

Package

Option

ADBF534WBBCZ4Axx –40°C to +85°C400 MHz 182-Ball CSP_BGABC-182

ADBF534WBBCZ4Bxx –40°C to +85°C400 MHz 208-Ball CSP_BGABC-208-2

ADBF534WYBCZ4Bxx –40°C to +105°C400 MHz 208-Ball CSP_BGABC-208-2

Z = RoHS compliant part.

xx denotes silicon revision.

Referenced temperature is ambient temperature.

Rev. I|Page 68 of 68 | July 2010

ADSP-BF534/ADSP-BF536/ADSP-BF537

registered trademarks are the property of their respective owners.

D05317-0-7/10(I)

ORDERING GUIDE

In the following table CSP_BGA = Chip Scale Package Ball Grid Array.

Model

Z = RoHS compliant part.

Temperature Range

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 24 for junction temperature (T

)

specification which is the only temperature specification.

Speed Grade (Max)Package Description

Package

Option

ADSP-BF534BBC-4A –40°C to +85°C400 MHz 182-Ball CSP_BGABC-182

ADSP-BF534BBCZ-4A–40°C to +85°C400 MHz 182-Ball CSP_BGABC-182

ADSP-BF534BBC-5A–40°C to +85°C500 MHz 182-Ball CSP_BGABC-182

ADSP-BF534BBCZ-5A–40°C to +85°C500 MHz 182-Ball CSP_BGABC-182

ADSP-BF534BBCZ-4B –40°C to +85°C400 MHz 208-Ball CSP_BGABC-208-2

ADSP-BF534YBCZ-4B –40°C to +105°C400 MHz 208-Ball CSP_BGABC-208-2

ADSP-BF534BBCZ-5B –40°C to +85°C500 MHz 208-Ball CSP_BGABC-208-2

ADSP-BF536BBC-3A –40°C to +85°C300 MHz 182-Ball CSP_BGABC-182

ADSP-BF536BBCZ-3A–40°C to +85°C300 MHz 182-Ball CSP_BGABC-182

ADSP-BF536BBC-4A–40°C to +85°C400 MHz 182-Ball CSP_BGABC-182

ADSP-BF536BBCZ-4A –40°C to +85°C400 MHz 182-Ball CSP_BGA BC-182

ADSP-BF536BBCZ-3B –40°C to +85°C300 MHz 208-Ball CSP_BGABC-208-2

ADSP-BF536BBCZ3BRL –40°C to +85°C300 MHz 208-Ball CSP_BGA, 13" Tape and ReelBC-208-2

ADSP-BF536BBCZ-4B –40°C to +85°C400 MHz 208-Ball CSP_BGABC-208-2

ADSP-BF537BBC-5A –40°C to +85°C500 MHz 182-Ball CSP_BGABC-182

ADSP-BF537BBCZ-5A–40°C to +85°C500 MHz 182-Ball CSP_BGA BC-182

ADSP-BF537BBCZ-5B –40°C to +85°C500 MHz 208-Ball CSP_BGA BC-208-2

ADSP-BF537BBCZ-5AV–40°C to +85°C533 MHz 182-Ball CSP_BGABC-182

ADSP-BF537BBCZ-5BV –40°C to +85°C533 MHz 208-Ball CSP_BGABC-208-2

ADSP-BF537KBCZ-6AV0

°C to +70°C600 MHz 182-Ball CSP_BGA BC-182

ADSP-BF537KBCZ-6BV 0°C to +70°C600 MHz 208-Ball CSP_BGA BC-208-2