Kinetis K66 Sub-Family
180 MHz ARM® Cortex®-M4F Microcontroller.
The K66 sub-family members provide greater performance,
memory options up to 2 MB total flash and 256 KB of SRAM, as
well as higher peripheral integration with features such as Dual
USB and a 10/100 Mbit/s Ethernet MAC. These devices maintain
hardware and software compatibility with the existing Kinetis
family. This product also offers:
• Integration of a High Speed USB Physical Transceiver
• Greater performance flexibility with a High Speed Run
mode
• Smarter peripherals with operation in Stop modes
Performance
• Up to 180 MHz ARM Cortex-M4 based core with DSP
instructions and Single Precision Floating Point unit
System and Clocks
• Multiple low-power modes to provide power
optimization based on application requirements
• Memory protection unit with multi-master protection
• 3 to 32 MHz main crystal oscillator
• 32 kHz low power crystal oscillator
• 48 MHz internal reference
Security
• Hardware random-number generator
• Supports DES, AES, SHA accelerator (CAU)
• Multiple levels of embedded flash security
Timers
• Four Periodic interrupt timers
• 16-bit low-power timer
• Two 16-bit low-power timer PWM modules
• Two 8-channel motor control/general purpose/PWM
timers
• Two 2-ch quad decoder/general purpose timers
• Real-time clock
Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• General-purpose input/output
Memories and memory expansion
• Up to 2 MB program flash memory on non-
FlexMemory devices with 256 KB RAM
• Up to 1 MB program flash memory and 256 KB of
FlexNVM on FlexMemory devices
• 4 KB FlexRAM on FlexMemory devices
• FlexBus external bus interface and SDRAM controller
Analog modules
• Two 16-bit SAR ADCs and two 12-bit DAC
• Four analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
• Voltage reference 1.2V
Communication interfaces
• Ethernet controller with MII and RMII interface to
external PHY and hardware IEEE 1588 capability
• USB high-/full-/low-speed On-the-Go with on-chip
high speed transceiver
• USB full-/low-speed OTG with on-chip transceiver
• Two CAN, three SPI and four I2C modules
• Low Power Universal Asynchronous Receiver/
Transmitter 0 (LPUART0) and five standard UARTs
• Secure Digital Host Controller (SDHC)
• I2S module
Operating Characteristics
• Voltage/Flash write voltage range:1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
MK66FN2M0VMD18
MK66FX1M0VMD18
MK66FN2M0VLQ18
MK66FX1M0VLQ18
144 MAPBGA (MD)
13 mm x 13 mm Pitch 1
mm
144 LQFP (LQ)
20 mm x 20 mm Pitch
0.5 mm
NXP Semiconductors K66P144M180SF5V2
Data Sheet: Technical Data Rev. 4, 04/2017
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information 1
Part Number Memory Maximum number of I\O's
Flash SRAM
MK66FN2M0VMD18 2 MB 256 KB 100
MK66FX1M0VMD18 1.25 MB 256 KB 100
MK66FN2M0VLQ18 2 MB 256 KB 100
MK66FX1M0VLQ18 1.25 MB 256 KB 100
1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type Description Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Solution Advisor
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K66P144M180SF5RMV21
Data Sheet The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata The chip mask set Errata provides additional or corrective information for
a particular device mask set.
Kinetis_K_0N65N 1
Package
drawing
Package dimensions are provided in package drawings. • MAPBGA 144-pin :
98ASA00222D1
• LQFP 144-pin:
98ASS23177W1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2Kinetis K66 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Memories and Memory Interfaces
Program
flash RAM
12-bit DAC
x2
6-bit DAC
x4
CRC
interface
touch-sensing
Programmable
Analog Timers Communication InterfacesSecurity
and Integrity
SPI
x3
Carrier
modulator
transmitter
FlexMemory
Clocks
Frequency-
Core
Debug
interfaces DSP
Interrupt
controller
comparator
x4
Analog
Voltage
reference
Secure
Digital
Low power
timer
Human-Machine
Interface (HMI)
GPIO
System
protection
Memory
DMA
Internal
watchdogs
and external
Low-leakage
wakeup
locked loop
Serial
programming
interface
Phase-
locked loop
reference
Internal
clocks
delay block
timers
interrupt
Periodic
External
bus
real-time
Independent
clock
oscillators
Low/high
frequency
UART
x5
Xtrinsic
®
Cortex -M4ARM
Low power
TPM x 2 (4ch)
LPUART
SDRAM
®
Kinetis K66 Sub-Family
USB DCD/
USBHSDCD
USB voltage
regulator
USB LS/FS
OTG
controller
with
transceiver
USB LS/FS/HS
OTG
controller
with
transceiver
x1
IS
2
Floating-
point unit
controller
x4
IC
2
Timers
x4 (20ch)
CAN
x2
IEEE 1588
Timers
Ethernet
IEEE 1588
Hardware
encryption
number
Random
generator
Cache
16-bit ADC
x2
Figure 1. K66 Block Diagram
Kinetis K66 Sub-Family, Rev. 4, 04/2017 3
NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1 Voltage and current operating requirements.....7
2.2.2 LVD and POR operating requirements............. 8
2.2.3 Voltage and current operating behaviors.......... 9
2.2.4 Power mode transition operating behaviors......10
2.2.5 Power consumption operating behaviors.......... 12
2.2.6 EMC radiated emissions operating behaviors...16
2.2.7 Designing with radiated emissions in mind....... 17
2.2.8 Capacitance attributes...................................... 17
2.3 Switching specifications...................................................17
2.3.1 Device clock specifications............................... 17
2.3.2 General switching specifications....................... 18
2.4 Thermal specifications.....................................................19
2.4.1 Thermal operating requirements....................... 19
2.4.2 Thermal attributes............................................. 19
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1 Debug trace timing specifications..................... 21
3.1.2 JTAG electricals................................................ 21
3.2 System modules.............................................................. 24
3.3 Clock modules................................................................. 24
3.3.1 MCG specifications........................................... 24
3.3.2 IRC48M specifications...................................... 27
3.3.3 Oscillator electrical specifications..................... 28
3.3.4 32 kHz oscillator electrical characteristics.........31
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash (FTFE) electrical specifications............... 31
3.4.2 EzPort switching specifications......................... 36
3.4.3 Flexbus switching specifications....................... 37
3.4.4 SDRAM controller specifications.......................40
3.5 Security and integrity modules........................................ 43
3.6 Analog............................................................................. 43
3.6.1 ADC electrical specifications.............................43
3.6.2 CMP and 6-bit DAC electrical specifications.....48
3.6.3 12-bit DAC electrical characteristics................. 50
3.6.4 Voltage reference electrical specifications........ 53
3.7 Timers..............................................................................54
3.8 Communication interfaces............................................... 54
3.8.1 Ethernet switching specifications...................... 55
3.8.2 USB Voltage Regulator Electrical
Specifications....................................................58
3.8.3 USB Full Speed Transceiver and High Speed
PHY specifications............................................ 59
3.8.4 USB DCD electrical specifications.................... 60
3.8.5 CAN switching specifications............................ 60
3.8.6 DSPI switching specifications (limited voltage
range)................................................................60
3.8.7 DSPI switching specifications (full voltage
range)................................................................62
3.8.8 Inter-Integrated Circuit Interface (I2C) timing....64
3.8.9 UART switching specifications.......................... 65
3.8.10 Low Power UART switching specifications....... 65
3.8.11 SDHC specifications......................................... 66
3.8.12 I2S switching specifications.............................. 67
3.9 Human-machine interfaces (HMI)....................................73
3.9.1 TSI electrical specifications...............................73
4 Dimensions............................................................................. 73
4.1 Obtaining package dimensions....................................... 73
5 Pinout......................................................................................74
5.1 K66 Signal Multiplexing and Pin Assignments.................74
5.2 Recommended connection for unused analog and
digital pins........................................................................81
5.3 K66 Pinouts..................................................................... 82
6 Ordering parts......................................................................... 84
6.1 Determining valid orderable parts....................................84
7 Part identification.....................................................................85
7.1 Description.......................................................................85
7.2 Format............................................................................. 85
7.3 Fields............................................................................... 85
7.4 Example...........................................................................86
8 Terminology and guidelines.................................................... 86
8.1 Definitions........................................................................86
8.2 Examples.........................................................................87
8.3 Typical-value conditions.................................................. 87
8.4 Relationship between ratings and operating
requirements....................................................................88
8.5 Guidelines for ratings and operating requirements..........88
9 Revision History...................................................................... 89
4Kinetis K66 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
1 Ratings
1.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
-500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Ratings
Kinetis K66 Sub-Family, Rev. 4, 04/2017 5
NXP Semiconductors
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 300 mA
VDIO Digital1 input voltage,including RESET_b –0.3 VDD + 0.3 V
VAIO Analog1 input voltage, including EXTAL32 and XTAL32 –0.3 VDD + 0.3 V
IDMaximum current single pin limit (digital output pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB0_DP USB0_DP input voltage –0.3 3.63 V
VUSB1_DP USB1_DP input voltage –0.3 3.63 V
VUSB0_DM USB0_DM input voltage –0.3 3.63 V
VUSB1_DM USB1_DM input voltage –0.3 3.63 V
VUSB1_VBUS USB1_VBUS detect voltage –0.3 6.0 V
VREG_IN0,
VREG_IN1
USB regulator input –0.3 6.0 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general
purpose I/O port.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
General
6Kinetis K66 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICDIO Digital1 input pin negative DC injection current
(except RTC_WAKEUP pins) — single pin
• VIN < VSS-0.3V
-5 — mA
2
IICAIO Analog1 input pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
-5
—
mA
2
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pin
• Negative current injection -25 — mA
VODPU Pseudo Open drain pullup voltage level VDD VDD V3
VRAM VDD voltage required to retain RAM 1.2 — V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V
General
Kinetis K66 Sub-Family, Rev. 4, 04/2017 7
NXP Semiconductors
1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general
purpose I/O port.
2. All digital and analog I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VSS-0.3V, a current limiting resistor is required. The minimum negative DC
injection current limiting resistor value is calculated as R=(-0.3-VIN)/|IICDIO| or R=(-0.3-VIN)/|IICAIO|. The actual resistor
should be an order of magnitude higher to tolerate transient voltages.
3. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— 80 — mV
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— 60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
General
8Kinetis K66 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
VOH Output high voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤VDD ≤ 2.7 V, IOH = -5mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
Output high voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOHT Output high current total for all ports — — 100 mA
VOH_RTC_WAKEUP Output high voltage— normal drive pad
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -2.5
mA
VBAT – 0.5
VBAT – 0.5
—
—
V
V
IOH_RTC_WAKEUP Output high current total for
RTC_WAKEUP pins
— — 100 mA
VOL Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
—
—
—
—
0.5
0.5
V
V
Output low voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
—
—
0.5
0.5
V
V
IOLT Output low current total for all ports — — 100 mA
VOL_RTC_WAKEUP Output low voltage— normal drive pad
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 2.5mA
—
—
0.5
0.5
V
V
IOL_RTC_WAKEUP Output low current total for
RTC_WAKEUPpins
— — 100 mA
IIN Input leakage current, analog and digital
pins
• VSS ≤ VIN ≤ VDD
— 0.002 0.5 µA 1
IOZ_RTC_WAKEUP Hi-Z (off-state) leakage current (per
RTC_WAKEUP pin)
— — 0.25 µA
RPU Internal pullup resistors 20 — 50 kΩ 2
RPD Internal pulldown resistors 20 — 50 kΩ 3
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
General
Kinetis K66 Sub-Family, Rev. 4, 04/2017 9
NXP Semiconductors
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx –> RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 100MHz
• Bus clock = 50MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode=FEI
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
tPOR After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
— 300 µs
• VLLS0 –> RUN — 172 µs
• VLLS1 –> RUN — 172 µs
• VLLS2 –> RUN — 94 µs
• VLLS3 –> RUN — 94 µs
• LLS2 –> RUN — 5.8 µs
• LLS3 –> RUN — 5.8 µs
• VLPS –> RUN — 5.4 µs
• STOP –> RUN — 5.4 µs
Table 6. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
Table continues on the next page...
General
10 Kinetis K66 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN32KH
z
32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
32 kHz IRC enabled.
52 52 52 52 52 52 µA
IEREFSTEN4MH
z
External 4 MHz crystal clock adder. Measured
by entering STOP or VLPS mode with the
crystal enabled.
206 228 237 245 251 258 uA
IEREFSTEN32K
Hz
External 32 kHz crystal clock adder by means
of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
VLLS1
VLLS3
LLS2
LLS3
VLPS
STOP
440
440
490
490
510
510
490
490
490
490
560
560
540
540
540
540
560
560
560
560
560
560
560
560
570
570
570
570
610
610
580
580
680
680
680
680
nA
I48MIRC 48MHz IRC 511 520 545 556 563 576 µA
ICMP CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP enabled
using the 6-bit DAC and a single external
input for compare. Includes 6-bit DAC power
consumption.
22 22 22 22 22 22 µA
IRTC RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM set
for 1 minute. Includes ERCLK32K (32 kHz
external crystal) power consumption.
432 357 388 475 532 810 nA
IUART UART peripheral adder measured by placing
the device in STOP or VLPS mode with
selected clock source waiting for RX data at
115200 baud rate. Includes selected clock
source power consumption.
MCGIRCLK (4 MHz internal reference clock)
OSCERCLK (4 MHz external crystal)
66
214
66
234
66
246
66
254
66
260
66
268
µA
IBG Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by placing
the device in STOP or VLPS mode. ADC is
configured for low power mode using the
internal clock and continuous conversions.
366 366 366 366 366 366 µA
General
Kinetis K66 Sub-Family, Rev. 4, 04/2017 11
NXP Semiconductors
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard deviation
(mean + 3 sigma)
Table 7. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — See note mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
32.3
32.4
71.03
71.81
mA
mA
2
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 105°C
—
—
—
50.5
50.6
69.7
89.58
55.95
99.85
mA
mA
mA
3, 4
IDD_RUNC
O
Run mode current in compute operation - 120
MHz core / 24 MHz flash / bus clock disabled,
code of while(1) loop executing from flash
• at 3.0 V
— 28.5 67.74 mA
5
IDD_HSRUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
47.2
47.3
91.25
91.62
mA
mA
6
IDD_HSRUN Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 105°C
—
—
—
71.4
71.5
93.3
103.58
79.13
115.08
mA
mA
mA
7, 4
IDD_HSRUN
CO
HSRun mode current in compute operation – 168
MHz core/ 28 MHz flash / bus clock disabled,
code of while(1) loop executing from flash at 3.0V
— 42.9 91.97 mA 5
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
— 16.9 45.2 mA 8
Table continues on the next page...
General
12 Kinetis K66 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Table 7. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks enabled
— 35 62.81 mA 8
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
— 1.1 9.56 mA 9
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
— 2 9.88 mA 10
IDD_VLPRC
O
Very-low-power run mode current in compute
operation - 4 MHz core / 1 MHz flash / bus clock
disabled, LPTMR running with 4 MHz internal
reference clock
• at 3.0 V
— 986 9.47 μA
11
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
— 0.690 9.25 mA 12
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks enabled
— 1.5 10.00 mA
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.791
3.8
13.2
2.39
6.91
18.91
mA
mA
mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
202
1400
5100
353.77
2464.54
8949.06
μA
μA
μA
IDD_LLS3 Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
9.0
76.3
402
16.5
88.63
656.08
μA
μA
μA
IDD_LLS2 Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
5.7
41.3
229
9.7
55.80
276.81
μA
μA
μA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
5.5
46.3
249
7.31
58.33
380.77
μA
μA
μA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
2.7
13.1
76.6
3.24
18.72
84.77
μA
μA
μA
Table continues on the next page...
General
Kinetis K66 Sub-Family, Rev. 4, 04/2017 13
NXP Semiconductors
Table 7. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.847
6.5
46.7
1.48
11.31
81.78
μA
μA
μA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.551
6.3
49.6
.65
7.12
53.68
μA
μA
μA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.254
6.3
48.7
0.445
10.99
85.27
μA
μA
μA
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.19
0.49
2.2
0.22
0.64
3.2
μA
μA
μA
IDD_VBAT Average current when CPU is not accessing RTC
registers
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
—
—
—
0.68
1.2
3.6
0.81
1.45
4.3
0.8
1.56
5.3
0.96
1.89
6.33
μA
μA
μA
μA
μA
μA
13
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. MCG configured for PEE mode.
6. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
7. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
General
14 Kinetis K66 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
8. 120 MHz core and system clock, 60MHz bus clock, and FlexBus. MCG configured for PEE mode.
9. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
10. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
11. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high,
optimized for balanced.
12. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
13. Includes 32kHz oscillator current and RTC operation.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
General
Kinetis K66 Sub-Family, Rev. 4, 04/2017 15
NXP Semiconductors
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors
Symbol Description Frequency
band
(MHz)
Typ. Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 23 dBμV 1, 2
VRE2 Radiated emissions voltage, band 2 50–150 27 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 28 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 14 dBμV
VRE_IEC IEC level 0.15–1000 K — 2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
General
16 Kinetis K66 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = MHz, fBUS = MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions.
1. Go to nxp.com
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol Description Min. Max. Unit Notes
High Speed run mode
fSYS System and core clock — 180 MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS System and core clock — 120 MHz
System and core clock when Full Speed USB in
operation
20 — MHz
fSYS_USBHS System and core clock when High Speed USB in
operation
100 — MHz
fENET System and core clock when ethernet in operation
• 10 Mbps
• 100 Mbps
5
50
—
—
MHz
Table continues on the next page...
General
Kinetis K66 Sub-Family, Rev. 4, 04/2017 17
NXP Semiconductors
Table 10. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fBUS Bus clock — 60 MHz
FB_CLK FlexBus clock — 60 MHz
fFLASH Flash clock — 28 MHz
fLPTMR LPTMR clock — 25 MHz
VLPR mode1
fSYS System and core clock — 4 MHz
fBUS Bus clock — 4 MHz
FB_CLK FlexBus clock — 4 MHz
fFLASH Flash clock — 1 MHz
fERCLK External reference clock — 16 MHz
fLPTMR_pin LPTMR clock — 25 MHz
fFlexCAN_ERCLK FlexCAN external reference clock — 8 MHz
fI2S_MCLK I2S master clock — 12.5 MHz
fI2S_BCLK I2S bit clock — 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, IEEE 1588 timer, timers, and I2C signals.
Table 11. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50 — ns 3
External reset pulse width (digital glitch filter disabled) 100 — ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew enabled
—
—
25
15
ns
ns
4
Table continues on the next page...
General
18 Kinetis K66 Sub-Family, Rev. 4, 04/2017
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Table 11. General switching specifications (continued)
Symbol Description Min. Max. Unit Notes
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
7
7
ns
ns
Port rise and fall time (low drive strength)
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
25
15
7
7
ns
ns
ns
ns
5
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 75 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol Description Min. Max. Unit Notes
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C 1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RθJA x chip power dissipation.
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Kinetis K66 Sub-Family, Rev. 4, 04/2017 19
NXP Semiconductors
2.4.2 Thermal attributes
Board type Symbol Description 144 LQFP 144 MAPBGA Unit Notes
Single-layer
(1s)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
45 48 °C/W 1
Four-layer
(2s2p)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
36 29 °C/W 1
Single-layer
(1s)
RθJMA Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
36 38 °C/W 1
Four-layer
(2s2p)
RθJMA Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
30 25 °C/W 1
— RθJB Thermal
resistance,
junction to
board
24 16 °C/W 2
— RθJC Thermal
resistance,
junction to case
9 9 °C/W 3
—ΨJT Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
2 2 °C/W 4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
General
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3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 13. Debug trace operating behaviors
Symbol Description Min. Max. Unit
Tcyc Clock period Frequency dependent MHz
Twl Low pulse width 2 — ns
Twh High pulse width 2 — ns
TrClock and data rise time — 3 ns
TfClock and data fall time — 3 ns
TsData setup 1.5 — ns
ThData hold 1.0 — ns
TRACECLK
Tr
Twh
Tf
Tcyc
Twl
Figure 5. TRACE_CLKOUT specifications
Th
Ts Ts Th
TRACE_CLKOUT
TRACE_D[3:0]
Figure 6. Trace data specifications
Peripheral operating requirements and behaviors
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