MC74HC165A 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS The MC74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is an 8-bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. * * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 286 FETs or 71.5 Equivalent Gates http://onsemi.com MARKING DIAGRAMS 16 PDIP-16 N SUFFIX CASE 648 16 1 MC74HC165AN AWLYYWW 1 16 SO-16 D SUFFIX CASE 751B 16 1 HC165A AWLYWW 1 16 16 1 HC 165A ALYW TSSOP-16 DT SUFFIX CASE 948F 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORDERING INFORMATION Device Package Shipping MC74HC165AN PDIP-16 2000 / Box MC74HC165AD SOIC-16 48 / Rail MC74HC165ADR2 Semiconductor Components Industries, LLC, 2000 April, 2000 - Rev. 3 1 SOIC-16 2500 / Reel MC74HC165ADT TSSOP-16 96 / Rail MC74HC165ADTR2 TSSOP-16 2500 / Reel Publication Order Number: MC74HC165A/D MC74HC165A LOGIC DIAGRAM A B PARALLEL DATA INPUTS PIN ASSIGNMENT 11 12 13 9 D 14 E 3 7 C QH QH SERIAL SHIFT/ PARALLEL LOAD CLOCK 1 16 VCC 2 15 CLOCK INHIBIT E 3 14 D SERIAL DATA OUTPUTS F 4 13 C G 5 12 B H 6 11 A QH 7 10 SA GND 8 9 QH F 4 G 5 H 6 SERIAL SA 10 DATA INPUT SERIAL SHIFT/ 1 PARALLEL LOAD CLOCK 2 CLOCK INHIBIT PIN 16 = VCC PIN 8 = GND 15 FUNCTION TABLE Serial Shift/ Parallel Load Inputs Clock Inhibit Clock L H H X H H L L H H X H H X L L H X = don't care X L L Internal Stages Output SA X L H A-H QA QB QH a...h X X a L H h L H X X L H b QAn QAn QAn QAn X X X X No Change Inhibited Clock X X No Change No Clock QGn QGn Serial Shift via Clock QGn QGn Serial Shift via Clock Inhibit QAn - QGn = Data shifted from the preceding stage http://onsemi.com 2 Operation Asynchronous Parallel Load MC74HC165A IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0 V Vin DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air 750 500 450 mW Tstg Storage Temperature - 65 to + 150 _C Iin TL Plastic DIP SOIC Package TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII IIIII III IIII IIIIIIIII IIIIIIIII IIII IIIIIIIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIIIIIIII v IIII v III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII III IIII III v IIII IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 2.0 6.0 V 0 VCC V - 55 + 125 _C 0 0 0 1000 600 500 400 ns DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V - 55 to 25_C 85_C 125_C Unit VIH Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.80 0.5 0.9 1.35 1.80 0.5 0.9 1.35 1.80 V Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 V VOH Vin = VIH or VIL |Iout| |Iout| |Iout| 2.4 mA 4.0 mA 5.2 mA http://onsemi.com 3 MC74HC165A IIII IIIIIIIII IIIIIIIII IIII IIIIIIIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIIIIIIII v v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII III IIII III v IIII IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIIIIIIII III IIII III IIII IIIII IIIIIIIIIIIIIIII IIII IIIIIIIII III IIIII IIIIIIIIIIIIIIII IIII IIII III v IIII v III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VOL Parameter Test Conditions Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| |Iout| |Iout| Iin ICC 2.4 mA 4.0 mA 5.2 mA VCC V - 55 to 25_C 2.0 4.5 6.0 85_C 125_C 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Unit V Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 A Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 A 6.0 4 40 160 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V - 55 to 25_C 85_C 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 8) 2.0 3.0 4.5 6.0 6 18 30 35 4.8 17 24 28 4 15 20 24 MHz tPLH, tPHL Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH (Figures 1 and 8) 2.0 3.0 4.5 6.0 150 52 30 26 190 63 38 33 225 65 45 38 ns tPLH, tPHL Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH (Figures 2 and 8) 2.0 3.0 4.5 6.0 175 58 35 30 220 70 44 37 265 72 53 45 ns tPLH, tPHL Maximum Propagation Delay, Input H to QH or QH (Figures 3 and 8) 2.0 3.0 4.5 6.0 150 52 30 26 190 63 38 33 225 65 45 38 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 8) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns Maximum Input Capacitance -- 10 10 10 pF Cin NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 40 pF * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 4 MC74HC165A IIII IIIIIIIIIIIIIIIIII III IIIIIIIII III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIIIIIIII v v IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III IIII IIIIIIIIIIIIIIIIII III IIII IIII III III TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit VCC V - 55 to 25_C Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load (Figure 4) 2.0 3.0 4.5 6.0 tsu Minimum Setup Time, Input SA to Clock (or Clock Inhibit) (Figure 5) tsu 85_C 125_C 75 30 15 13 95 40 19 16 110 55 22 19 ns 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit) (Figure 6) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tsu Minimum Setup Time, Clock to Clock Inhibit (Figure 7) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns th Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs (Figure 4) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Clock (or Clock Inhibit) to Input SA (Figure 5) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load (Figure 6) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns Minimum Recovery Time, Clock to Clock Inhibit (Figure 7) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tw Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 1) 2.0 3.0 4.5 6.0 70 27 15 13 90 32 19 16 100 36 22 19 ns tw Minimum Pulse width, Serial Shift/Parallel Load (Figure 2) 2.0 3.0 4.5 6.0 70 27 15 13 90 32 19 16 100 36 22 19 ns Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns Symbol Parameter tsu trec tr, tf Unit NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 5 MC74HC165A PIN DESCRIPTIONS INPUTS is applied to this pin, data at the Parallel Data inputs are asynchronously loaded into each of the eight internal stages. A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6) Parallel Data inputs. Data on these inputs are asynchronously entered in parallel into the internal flip-flops when the Serial Shift/Parallel Load input is low. Clock, Clock Inhibit (Pins 2, 15) Clock inputs. These two clock inputs function identically. Either may be used as an active-high clock inhibit. However, to avoid double clocking, the inhibit input should go high only while the clock input is high. The shift register is completely static, allowing Clock rates down to DC in a continuous or intermittent mode. SA (Pin 10) Serial Data input. When the Serial Shift/Parallel Load input is high, data on this pin is serially entered into the first stage of the shift register with the rising edge of the Clock. OUTPUTS CONTROL INPUTS QH, QH (Pins 9, 7) Serial Shift/Parallel Load (Pin 1) Complementary Shift Register outputs. These pins are the noninverted and inverted outputs of the eighth stage of the shift register. Data-entry control input. When a high level is applied to this pin, data at the Serial Data input (SA) are shifted into the register with the rising edge of the Clock. When a low level http://onsemi.com 6 MC74HC165A SWITCHING WAVEFORMS tr CLOCK OR CLOCK INHIBIT tf VCC 90% 50% 10% tw GND SERIAL SHIFT/ PARALLEL LOAD tw 1/fmax tPLH GND tPHL QH OR QH tTLH tPHL tPLH 90% 50% 10% QH OR QH VCC 50% 50% 50% tTHL Figure 1. Serial-Shift Mode Figure 2. Parallel-Load Mode VALID tr VCC tf VCC 90% 50% 10% INPUT H INPUTS A-H 50% GND GND tPLH tsu tPHL 90% 50% 10% QH OR QH th VCC SERIAL SHIFT/ PARALLEL LOAD tTLH GND tTHL ASYNCHRONOUS PARALLEL LOAD (LEVEL SENSITIVE) Figure 3. Parallel-Load Mode Figure 4. Parallel-Load Mode VALID SERIAL SHIFT/ PARALLEL LOAD VCC INPUT SA 50% VCC 50% GND tsu GND tsu th VCC CLOCK OR CLOCK INHIBIT VCC CLOCK OR CLOCK INHIBIT 50% th 50% GND GND Figure 5. Serial-Shift Mode Figure 6. Serial-Shift Mode TEST POINT CLOCK 2 INHIBITED CLOCK INHIBIT OUTPUT VCC DEVICE UNDER TEST 50% GND tsu CLOCK CL* trec VCC 50% GND *Includes all probe and jig capacitance Figure 7. Serial-Shift, Clock-Inhibit Mode Figure 8. Test Circuit http://onsemi.com 7 MC74HC165A EXPANDED LOGIC DIAGRAM A B 11 C 12 F 13 G 4 H 5 6 SERIAL SHIFT/ 1 PARALLEL LOAD 9 Q H SERIAL DATA 10 INPUT SA D QA D QB D QC D QF D QG D QH C C C C C C C C C C C C CLOCK 2 CLOCK 15 INHIBIT TIMING DIAGRAM CLOCK CLOCK INHIBIT SA SERIAL SHIFT/ PARALLEL LOAD A H B L C H D L E H F L G H H H PARALLEL DATA INPUTS QH QH H H L H L H L H L L H L H L H L CLOCK INHIBIT MODE SERIAL-SHIFT MODE PARALLEL LOAD http://onsemi.com 8 7 Q H MC74HC165A PACKAGE DIMENSIONS PDIP-16 N SUFFIX CASE 648-08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A - 16 9 1 8 B F C DIM A B C D F G H J K L M S L S -T - SEATING PLANE K H D 16 PL 0.25 (0.010) M M J G T A M INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.85 6.35 0.145 0.175 4.44 3.69 0.015 0.021 0.53 0.39 0.040 0.070 1.77 1.02 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.38 0.21 0.110 0.130 3.30 2.80 0.295 0.305 7.74 7.50 10 0 10 0 0.020 0.040 1.01 0.51 SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A - 16 9 1 8 -B - NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. P 8 PL 0.25 (0.010) M B M G K F R X 45 C -T SEATING - PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 9 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 MC74HC165A PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K EEE CCC CCC EEE K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. 8 1 N 0.25 (0.010) 0.15 (0.006) T U S A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. M N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE DETAIL E H D G http://onsemi.com 10 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC165A Notes http://onsemi.com 11 MC74HC165A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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