ANALOG DEVICES CMOS Serial Input 12-Bit DAC AD7543 FEATURES Resolution: 12 Bits Nonlinearity: +1/2LSB Tin to Tmax Low Gain T.C.: 2ppm/C typ, 5ppm/C max Serial Load on Positive or Negative Strobe Asynchronous CLEAR Input for Initialization Full 4-Quadrant Multiplication Low Multiplying Feedthrough: 1LSB max @ 10kHz Requires no Schottky Diode Output Protection Low Power Dissipation: 40mW max +5V Supply Small Size: Package Low Cost 16-Pin DIP or 20-Terminal Surface Mount GENERAL DESCRIPTION The AD7543 is a precision 12-bit monolithic CMOS multi- plying DAC designed for serial interface applications. The DACs logic circuitry consists of a 12-bit serial-in parallel- out shift register (Register A) and a 12-bit DAC input register (Register B). Serial data at the AD7543 SRI pin is clocked into Register A on the leading or trailing edge (user selected) of the strobe input. Once Register A is full its contents are loaded in- to Register B under control of the LOAD inputs. FUNCTIONAL BLOCK DIAGRAM R AD7543 16) Ree 1) o0uT1 12-BIT D/A CONVERTER 2) ouT2 7 o> 3) AGND DAC REGISTER B LOAD REGISTER A Al 12-BIT SHIFT REGISTER 7)s 14) Voo 12) DGND provides an asynchronous reset of Register B. Packaged in 16-pin DIP and 20-pin LCCC and PLCC, the AD7543 features excellent gain T.C. (2ppm/C typ; Sppm/C max), +5V operation and latch-free operation. (No protection Schottky Diodes required.) Initialization is simplified by the use of the CLR input which | PIN CONFIGURATIONS DIP LCCC PLCC n= Pc . er . > Deo > oF a) es r \4 s582ea oo 2 & oun G e 16] Fre 392 =71 20 19 BIBI ouT2 EE 15] Vaee AGND eB 14] Vop AGND 4 18 Voo acno [4] Voo = STB1 5 17, CLR _ $781 GE] AD7543 [3] CLR NC 6 AD7543 ewe stat [5 | AD7543 cir m7 TOP VIEW TOP VIEW ip1 E 12] DGND _ nc [6] TOP VIEW NC {Not to Scale) ip 7 (Not to Scale) 15 DGND _ (Not to Scale} DGND ne [6 u] sTB4 tp" NC 8 14 STB4 ra sted SRI G 10] STB3 Ne sTB2 [8 9] LD2 9 10 11 12 13 G a S428 8 PETE NC = NOCONNECT in zoe: ls |e NC = NOCONNECT & 8 REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its usex No license is granted by implica- tion or otherwise under any patent or patent rights of Analog Devices. NC = NOCONNECT One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 Telex: 924491 Cable: ANALOG NORWOODMASSAD7543 SPECIFICATIONS (Vop = +5V, Veep = +10V, le = Vourz = OV, unless otherwise noted.) Limit At! Limit At Limit At Ta = -40C Ta = -55C Parameter Ta=425C 10 485C & 4125C Units Conditions/Comments ACCURACY Resolution 12 12 12 Bits Relative Accuracy? J, A, S Versions t1 41 t1 LSB max K, B, T Versions 41/2 1/2 t1/2 LSB max GK, GB, GT Versions 41/2 t1/2 +1/2 LSB max Differential Nonlinearity? J, A, S Versions 2 +2 +2 LSB max Monotonic to 11 bits from Tmin tO Tmax K, B, T Versions t1 +1 +1 LSB max Monotonic to 12 bits from Tin to Tmax GK, GB, GT Versions +1 41 + LSB max Monotonic to 12 bits from Trin t0 Tmax Gain Error? J. K, A, B,S,T 412.3 413.5 +14.5 LSB max Using internal RFB only (gain error can be GK, GB, GT 41 +1 42 LSB max trimmed to zero using circuits of Figures 6 & 7) Gain Temperature Coefficient AGain/ATemperature 5 5 5 ppm/C max Typical value is 2ppm/C Power Supply Rejection AGain/AVpp 0.005 0.01 0.01 % per % max Vpp = +4.75V to +5.25V Output Leakage Current lout: (Pin 4) 1 10 200 nA max DAC Register loaded with all Os louTz2 (Pin 5) 1 10 200 nA max DAC Register loaded with all 1s DYNAMIC PERFORMANCE Current Settling Time? 2.0 2.0 2.0 us max To 1/2LSB. OUT1 load = 10022. DAC output measured from falling edge of LD1 and LD2, see Figure 5. Multiplying Feedthrough Error 2.5 2.5 2.5 mV p-p max VreF = +10V, 10kHz sine wave REFERENCE INPUT Input Resistance (pin 15) 8/15/25 8/15/25 8/15/25 kQ min/ty p/max Typical temperature coefficient is -300ppm/C ANALOG OUTPUTS Output Capacitance / CouTi 75 75 75 pF max Register B loaded to 0000 0000 0000 Cout1? 260 260 260 pF max Register B loaded to 1111 1111 1111 Cout2 75 75 75 pF max Register B loaded to 1111 11111111 Covt2? 260 260 260 pf max Register B loaded to 0000 0000 0000 LOGIC INPUTS VinH (Logic HIGH Voltage) +3.0 +3.0 +3.0 V min VinL (Logic LOW Voltage) +0.8 +0.8 +0.8 V max lin 1 1 1 UA max Vin = OV or Vpp Cn (input Capacitance)? 8 8 8 pF max Input Coding 12-Bit Unipolar Binary or 12-Bit Offset Binary (see Figures 6 and 7), serial load (MSB First) SWITCHING CHARACTERISTICS tps 50 100 100 ns min Seri STB1 used as a strobe erial Input tos4 0 0 ns min STB4 used as a strobe . to Strobe e=a3 tps3 0 0 0 ns min Setup Time STB3 used as a strobe tps2 20 40 40 ns min STB2 used as a strobe tDH1 30 60 60 ns min Serial Input STB1 used as a strobe tpH4 80 160 160 ns min to St P b STB4 used as a strobe tpH3 80 160 160 ns min H lat robe STB3 used as a strobe tpH2 60 120 120 ns min tme STB2 used as a strobe tsRI 80 160 160 ns min SRI data pulse width tse! 80 160 160 ns min STB1 pulse width tsTB4 100 200 200 ns min STB4 pulse width tstB3 100 200 200 ns min STB3 pulse width tsTB2 80 160 160 ns min STB2 pulse width tELD1> LD2 150 300 300 ns min Load pulse width tASB 0 0 0 ns min Min time between strobing LSB into Register A and loading Register B tcCLR 200 400 400 ns min CLR pulse width POWER SUPPLY Vpp (Supply Voltage) +5 +5 +5 v Ipp (Supply Current) 2.5 2.5 2.5 mA max Digital Inputs = Ving or VINL NOTES Temperature ranges as follows: JN, KN, GKN Version; 40C to +85C AQ, BQ, GBQ Versions: 40C to +85C SQ, TQ, GTQ Versions: 55C to +125C *See Terminology on following page. Guaranteed but not tested. Logic inputs are MOS gates. Typical input current (+25C) is less than InA. Sample tested at +25C to ensure compliance. Specifications subject to change without notice. REV. BAD7543 ABSOLUTE MAXIMUM RATINGS* (T, = + 25C unless otherwise noted) ORDERING GUIDE Temperature Relative Gain Package VpptoAGND ...........000 500 0 OV, +7V Model Range Accuracy Error Option* ADD OND Prt ee y Oy AD7543JN 40Cto + 85C. + ILSB) = #12.3LSB_N-16 DGNDtoAGND.......00 ve. + 0. 3V AD7543KN 40Cto+85C +1/2LSB +12.3LSB_ N-16 we TT ee ee es bp: AD7543GKN 40Cto +85C +1/2LSB +1LSB N-16 Digital Input Voltage to DGND 0.3V, Vpp +0.3V anzs43yP 40C to 485C. St ILSB)= + 12.3LSB_P-20A youre Vour2 *o AGND ....... ~0:3V; Vp t0 +0.3V anzs43KP 40C 10 +85C | + 1/2LSB + 12.3LSB_ P-20A REF TO AGND +25V 4D7543GKP 40Cto +85C +1/2LSB +1LSB P-20A Varn toAGND . .. 12-2. ee ee ee *25V 4D7543JR 40Ct0 +85C +1LSB +12.3LSB R-16 Power Dissipation (Package) AD7543KR 40C10 + 85C + 1/2LSB. +12.3LSB_ R-16 Plastic AD7543GKR 40Cto+85C +1/2LSB +1LSB R-16 To $70 ww te 670mW AD7543AQ. 40C10 +85C. + 1LSB-+12.3LSB_Q-16 Derates above +70C by ............ 8.3mW/C AD7543BQ. 40C to +85C- + 1/2LSB_-+12.3LSBQ-16 Cerdip AD7543GBQ -40Cto +85C +1/2LSB +1LSB Q-16 To F75C ww 450mW = AD7543SQ. 55Cto 125C +ILSB +12.3LSB Q-16 Derates above +75C by... .--- +--+. 6mW"C AD7543TQ = 55C to $125C + 1/2LSB -+12.3LSB Q-16 Operating Temperature Range AD7S43GTQ 55Cto +125C +1/2LSB +1LSB Q-16 Commercial (J, K, GK Versions) . . . . . 40C to +85C a7543SE 55Cto +125C +1LSB -+12.3LSB__E-20A Industrial (A, B, GB Versions) . .. . . . 40C to +85C an7543TE 9 55Cto +125C +1/2LSB +12.3LSB E-20A Extended (S, T, GT Versions) ...... 55C to +125C AD7543GTE 55Cto +125C +1/2LSB +I1LSB E-20A Storage Temperature Lead Temperature (Soldering, 10secs) Se ee 65C to + 150C + 300C *E = Leadless Ceramic Chip Carrier (LCCC); N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC (SOIC). *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect- ed; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. WARNING! _ ye ESD SENSITIVE DEVICE PIN | MNEMONIC FUNCTION 1 OUT1 DAC current output bus. Normally terminated at op amp virtual ground 2 OUT2 DAC current output bus. Normally terminated at AGND 3 AGND Analog Ground 4 STB1 Register A Strobe 1 input, see Table II 5 LD1 DAC Register B Load 1 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B 6 N/C No Connection 7 SRI Serial Data Input to Register A 8 STB2 Register A Strobe 2 input, see Table II 9 LD2 DAC Register B Load 2 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B 10 STB3 Register A Strobe 3 input, see Table II 11 STB4 Register A Strobe 4 input, see Table II 12 DGND Digital Ground 13 CLR Register B CLEAR input (active LOW), can be used to asynchronously reset Register B to 0000 0000 0000 14 Vpp +5V Supply Input 15 VREF Reference input. Can be positive or negative dc voltage or ac signal 16 RFR DAC Feedback Resistor REV. B Table |. Pin Function Description, DIP ConfigurationAD7543 TERMINOLOGY RELATIVE ACCURACY Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for ideal zero and full scale and is expressed in % or ppm of full-scale range or (sub) multiples of 1LSB. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the difference between the mea- sured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of +1 LSB max over the operating temperature range ensures monotonicity. GAIN ERROR Gain is defined as the ratio of the DACs Full Scale output to its reference input voltage. An ideal AD7543 would exhibit a gain of -4095/4096. Gain error is adjustable using external trims as shown in Figures 6 and 7. OUTPUT LEAKAGE CURRENT Current which appears at OUT1 with Register B loaded to all 0s or at OUT 2 with Register B loaded to all 1s. MULTIPLYING FEEDTHROUGH ERROR AC error due to capacitive feedthrough from Vappr terminal to OUT1 with DAC register loaded to all 0s. GENERAL CIRCUIT INFORMATION The AD7543, a 12-bit multiplying D/A converter, consists of a highly stable thin film R-2R ladder and twelve N-channel current switches on a monolithic chip. Most applications require the addition of only an output operational amplifier and a voltage or current reference. The simplified D/A circuit is shown in Figure 1. An inverted R-2R ladder structure is usedthat is, the binarily weighted currents are switched between the OUT1 and OUT2 bus lines, thus maintaining a constant current in each ladder leg indepen- dent of the switch state. 2R OUT2 OUT1 RFB DAC REGISTER B Figure 1. AD7543 Functional Diagram One of the current switches is shown in Figure 2. The input resistance at Vprp (Figure 2) is always equal to RLpR (Rupr is the R/2R ladder characteristic resistance and is equal to value R). The reference terminal can be driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. If a current source is used, a low temperature coefficient external Rpg is recommended to define scale factor. TO LADDER FROM INTERFACE LOGIC OUT2 OUT1 Figure 2, N-Channel Current Steering Switch EQUIVALENT CIRCUIT ANALYSIS The equivalent circuits for all digital inputs LOW and all digital inputs HIGH are shown in Figures 3 and 4. In Figure 3 with all digital inputs LOW, the reference current is switched to OUT2. The current source ILEAKAGE 1S composed of sur- face and junction leakages to the substrate, while the 1/4096 current Source represents a constant 1 least significant bit cur- rent drain through the termination resistor on the R-2R ladder. The ON capacitance of the output N-channel switch is 260pF, as shown on the OUT2 terminal. The OFF switch capacitance is 75pF, as shown on the OUT 1 terminal. Analysis of the circuit for all digital inputs HIGH, as shown in Figure 4, is similar to Figure 3; however, the ON switches are now on terminal OUT1, hence the 260pF at that terminal. Ree OUT1 V R = 15k REF T 0 OUT2 IREF | Va096 { ILEAKAGE ue Figure 3. AD7543 DAC Equivalent Circuit All Digital Inputs LOW Ree R~ 15k R Vrer OUT1 IREF | 4096 iio L Figure 4. AD7543 DAC Equivalent Circuit All Digital Inputs HIGH REV. BApplications AD7543 AD7543 Logic Inputs Register A Control Inputs Register B Control Inputs AD7543 Operation Notes STB4 _STB3__STB2__STB1| CLR LD2__LD1 0 1 0 * xX Xx Xx Data Appearing At SRI Strobed Into Register A 2,3 0 i A ) x xX x Data Appearing At SRI Strobed Into Register A 2,3 0 2 0 0 x xX xX Data Appearing At SRI Strobed Into Register A 2,3 1 0 0 x x xX Data Appearing At SRI Strobed Into Register A 2,3 1 xX X X X 0 XxX xX : : x x , x No Operation (Register A) 3 Xx Xx x 1 0 xX X Clear Register B To Code 0000 0000 0000 (Asynchronous Operation) | 1,3 1 1 X . . No Operation (Register B) 3 1 X 1 1 0 0 Load Register B With The Contents Of Register A 3 NOTES: 1, CLR =0 Asynchronously resets Register B to 0000 0000 0000, but has no effect on Register A. 2. Serial data is loaded into Register A MSB first, on edges shown is positive edge Vis negative edge. 3. O= Logic LOW, 1 = Logic HIGH, X = Dont Care. Table Il, AD7543 Truth Table |~etsRi se| SRI tps1, tos2, tos4 tDH1, toH2, toH4 STROBE INPUT Qn Il 2 (STB1, STB2, STB4) | | tsts1 (NOTE) | tsTB2 I | BIT 1 BIT 1 EXE | ; tsTB4 [ere LOADING REGISTER a__ Xx 11 LD1AND LD2 NOTE: STROBE WAVEFORM IS INVERTED IF STB3 IS USED TO STROBE SERIAL DATA BITS INTO REGISTER A. - at LOADING REGISTER B a Ld WITH CONTENTS OF REGISTER A Figure 5. Timing Diagram INTERFACE LOGIC INFORMATION Shown in the AD8543 Functional Diagram Register A is a 12- bit shift register. Serial data appearing at pin SR1 is clocked into the shift register on the leading (rising) edge of STB1, STB2 or STB4 or on the leading (falling) edge of STB3. Table II defines the various logic states required on the Register A control inputs, while Figure 5 illustrates the Register A loading sequence. Once Register A is full, the data is transferred to Register B by bringing LD1 and LD2 momentarily LOW. Register B can be asynchronously reset to 0000 0000 0000 by bringing CLR momentarily LOW. This allows the DAC output voltage to be set to a known condition, thus simplify- ing system initialization procedure. When operating the AD7543 in the unipolar circuit of Figure 6, a CLEAR causes the DAC output voltage to equal OV. When using the bipolar circuit of Figure 7, a CLEAR causes the DAC output to equal -VREF. REV. B APPLYING THE AD7543 UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) Figure 6 shows the analog circuit connections required for uni- polar binary (2-quadrant multiplication) operation. The logic inputs are omitted for clarity. With a de reference voltage or current (positive or negative polarity) applied at pin 15, the circuit is a unipolar D/A converter. With an ac reference volt- age or current (again of + or - polarity) the circuit provides 2-quadrant multiplication (digitally controlled attenuation). The input/output relationship is shown in Table III. R1 provides full scale trim capability [i.e.load the DAC register to 1111 1111 1111, adjust R1 for Vout = -VREF (4095/4096)]. Alternatively, Full Scale can be adjusted by omitting R1 and R2 and trimming the reference voltage magnitude. C1 phase compensation (10pF to 25pF) may be required for stability when using high speed amplifiers. (C1 is used to can- cel the pole formed by the DAC internal! feedback resistance and output capacitance at OUT1).AD7543 +10V Vop VREF +8V R22 R12 C1== 22pF 15 14 16 ouT1 1 - AD7543} Al Vout 2 + 12 3 ouT2 ADS44L (SEE TEXT) OGND AGND NOTES 1. LOGIC INPUTS OMITTED FOR CLARITY. 2. SEE APPLICATION HINT NO. 4. Figure 6. Unipolar Binary Operation (2-Quadrant Multiplication) BINARY NUMBER IN DAC REGISTER ANALOG OUTPUT, Vout MSB LSB 1111 1111 1111 -Vrer(teee 1000 0000 0000 -VREF 2038). -1/2 VrEF 0000 0000 0001 -Vrer (4996) 0000 0000 0000 ov Table I11. Unipolar Binary Code Table for Circuit of Figure 6 Amplifier Al should be selected or trimmed to provide Vos < 10% of the voltage resolution at Vout. Additionally, the amplifier should exhibit a bias current which is low over the temperature range of interest (bias current causes output offset at VouT equal to Ip times the DAC feedback resistance, nominally 15k). The AD544L is a high-speed implanted FET-input op amp with low, factory-trimmed Vos. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) Figure 7 and Table IV illustrate the circuitry and code rela- tionship for bipolar operation. With a dc reference (positive or negative polarity) the circuit provides offset binary operation. With an ac reference, the eleven LSBs provide digitally con- trolled attenuation of the ac reference while the MSB pro- vides polarity control. With the DAC register loaded to 1000 0000 0000, adjust R1 for Vout = OV (alternatively, one can omit R1 and R2 and adjust the ratio of R3 to R4 for Vout = OV). Full scale trim- ming can be accomplished by adjusting the amplitude of VrEF or by varying the value of RS. As in unipolar operation, Al must be chosen for low Vog and low Ip. R3, R4 and R5 must be selected for matching and tracking. Mismatch of 2R3 to R4 causes both offset and Full Scale error. Mismatch of R5 to R4 to 2R3 causes Full Scale error. C1 phase compensation (10pF to 25pF) may be re- quired for stability. ADS44L (SEE TEXT) DGND AGND NOTES 1, LOGIC INPUTS OMITTED FOR CLARITY. 2. SEE APPLICATION HINT NO. 4. Figure 7. Bipolar Operation (4-Quadrant Multiplication) BINARY NUMBER IN DAC REGISTER ANALOG OUTPUT, Vout MSB LSB 1111 1111 1111 +Veer( S045 1000 0000 0001 +Vrer (345) 1000 0000 0000 ov 0111 1111 1111 -Vrer (xoae ) 0000 0000 0000 -VREF 2048. Table IV. Bipolar Code Table for Offset Binary Circuit of Figure 7 APPLICATION HINTS The AD7543 is a precision 12-bit multiplying DAC designed for serial interface. To ensure system performance consistent with AD7543 specifications, careful attention must be given to the following points: 1. GENERAL GROUND MANAGEMENT: Voltage differen- ces between the AD7543 AGND and DGND cause loss of accuracy (dc voltage difference between the grounds intro- duces gain error. AC or transient voltages between the grounds cause noise injection into the analog output). The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7543. In more complex systems where the AGND- DGND connection is on the back-plane, it is recommended that diodes be connected back-to-back between the AD7543 AGND and DGND pins to prevent possible device damage. 2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a code-dependent output resistance which in turn causes a code-dependent amplifier noise gain. The effect is a differ- ential nonlinearity term at the amplifier output which de- pends on Vog (Vos is amplifier input offset voltage). This differential nonlinearity term adds to the R/2R differential nonlinearity. To maintain monotonic operation, it is rec- ommended that amplifier Vos be no greater than 10% of the DACs output resolution over the temperature range of interest [output resolution = Vagp 2 where n is the number of bits exercised] . REV. BAD7543 3. HIGH FREQUENCY CONSIDERATIONS: AD7543 out- put capacitance works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This not only reduces closed loop bandwidth, but can also cause ringing or oscillation if the spurious pole frequency is less than the amplifiers OdB crossover frequency. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor. . GAIN TEMPERATURE COEFFICIENTS: The gain temper- ature coefficient of the AD7543 has a maximum value of Sppm/C and a typical value of 2ppm/C. This corresponds to gain shifts of 2.0LSBs and 0.82LSBs respectively over a 100C temperature range. When trim resistors are used to adjust full-scale range as shown in Figures 6 and 7 the temperature coefficient of R1 and R2 should be taken into account. It may be shown that the additional gain temperature coefficients introduced by R1 and R2 may be approximately expressed as follows: Temperature Coefficient == = Ry contribution due to R1 ~ Rin (1 + 300) Temperature Coefficient Rp contribution duetoR2 ~ * Rw (y2 + 300) Where 7; and 72 are the temperature coefficients in ppm/C of R1 and R2 respectively and Ryy is the DAC input resist- ance at the Vprgr terminal (pin 2). For high quality wire- wound resistors and trimming potentiometers is of the order of 50ppm/C. It will be seen that if R1 and R2 are small com- pared with Ryn, their contribution to gain temperature coef- ficient will also be small. For the standard AD7543 gain error specification of +12.3 LSBs it is recommended that R1 = 1202 and R2 = 6022. With y = 50 these values result in an overall maximum gain error temperature coefficient of: 5 +206 (50 + 300) = 8ppm/C However, if the AD7543GTD is used which has a specified gain error of +1LSB, then with R1 = 1022 and R2 = 5&2 the overall maximum gain temperature coefficient is increased by only 0.25ppm/C. Where possible R1 should be a select on test fixed resistor since the resulting gain temperature coeffi- efficient will be tighter in all cases. For further gain T.C. information refer to application note, Gain Error and Gain Temperature Coefficients of CMOS Multiplying DACs, Publication Number E630106/81 available from Analog Devices. 5. For additional information on multiplying DACS refer to Application Guide to CMOS Multiplying D/A Con- verters, Publication Number G479158/78, available from Analog Devices. REV. B AD7543 INTERFACE TO MC6800 In this example, it is assumed that the 12-bit data is con- tained in two memory locations (0000 and 0001). The four most significant bits are assumed to occupy the lower half of memory location 0000. The eight least significant bits occupy memory location 0001. The data is presented bit by bit on the D7 line and strobed into the AD7543 by executing memory write instructions, In this case the strobe signal (STB1) is sup- plied by decoding address 2000, R/W and 2. A memory write instruction to a different address (4000) loads the data from Register A to the DAC register. Figure 8 shows the interface circuitry and Table V gives a listing of the procedure. ADDRESS BUS (16) A0.15 ADDRESS (16) SZ 8205 E1 6800 $2 DECODER = E3 E2 5 DATA BUS (8) bo 07 DATA (8) SRI LD2 STB1 STB3 Loi STB2 STB4 +5V AD7543 cL FROM SYSTEM RESET Figure 8. AD7543MC6800 Interface LABEL MNEMONIC OPERAND COMMENT LDA B, 04 LDA A, 0000 Load 4 Most Significant Bits LOOP ROL A Reposition in the Data DEC B in ACCA BNE LOOP LDA B, 04 BSR SHIFT Output Data LDA B, 08 LDA A, 0001 Load 8 Least Significant Bits BSR SHIFT Output Data STA A, 4000 Load DAC Register RTS Return to Main Program SHIFT STA A,2000 Strobe Data ROL A into AD7543 DEC B BNE SHIFT RTS Table V. Sample Routine for AD7543MC6800 Interface AD7543 INTERFACE TO MCS-85 Figure 9 shows the AD7543 interfaced to the 8085. This sys- tem makes use of the serial output facility (SOD) on the 8085. The data is presented serially on the SOD line and strobed into the AD7543 by executing memory write instructions. In this example the strobe signal (STB2) is supplied by decod- ing address 8000 and WR. A memory write instruction to a different address (A000) loads the DAC Register with RegisterAD7543 A data. Table VI gives a listing of this procedure. Note, it is assumed that the required serial data is already present in OUTLINE DIMENSIONS Dimensions shown in inches and (mm). right-justified format in Registers H and L when this proce- dure is implemented. Note that the sample routine of Table VI can be speeded up by replacing the SHIFT routine with a DAD H instruction. 16-Pin Plastic DIP (N-16) Package 0.26 (6.61) 0.24 (6.1) e (8) ADDRESS BUS (16) ADDRESS (16) & 0.786 19.18) +3 306 (7. rearren f " t 0.746 (18.93) 0.294747) 294 ren fe 5 0.4 (3.56) o . ALE 82 E1 on (4.32 oe a = a 808: 45V 53 8205 DECODER t_ aaa ip WR | m E2 | 012 (3.05) = 06} / (8) ADO-7 DATA DATA (8) 2.012 (0.305) 0,065 (1.66) 0.02 eo is (2.67) 0.008 (0.203) 0.045 {1.16} 0.016 (0.381) 0.0965 (2.42) soD SRI LD2 sTB2 LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH +5V : STB3 LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42 STB1 AD7543 STB4 : : ii ag 16-Pin Ceramic DIP (D-16) Package FROM SYSTEM RESET: [ ayo . 0.3 (7.62) Figure 9. AD75438085 Interface wae e LABEL MNEMONIC OPERAND COMMENT iii 0.81 (20.58) 0.12 (3.05) MVI B, 05 Shift Data Up to 0.77 (19.56) 0.06 11.63) LOOP CALL SHIFT Most Significant 1 DCR B Segment of HL with 0.17 (4.32) JNZ LOOP MSB as Carry MAX { 77 MVI B, OC j 0.176 (4.45) 0.012 (0.308) LUP MVI A, 80 SOD Enable in ACC lL. = * 0.008 (0.203) RAR Shift in MSB of H | SIM Set Interrupt Mask 0.06 (1.63) 0.02 (0.608) abrlean 0.306 (7.78) STA 8000 Strobe Data into AD7543 0.046 1115) 0.18 (0.389 0.086 12.42) 0.296 (7.47) CALL SHIFT Get Next Bit into Carry 1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH DCR B 2. LEADS WILL BE EITHER GOLD OR TIN PLATED ; . IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS JNZ LUP Go Back if Not Finished STA A000 Load DAC Register of AD7543 : : : . ; \- r (E-20A) Package RET Return to Main Program 20-Pin Leadless Ceramic Chip Carrier (E ) ag SHIFT MOV A,L Shift H and L Left (0.082 * gots, RAL One Place and we fe 0.350 + 0.008 5a of 9.080 x 45 MOV L,A Leave Uppermost Bit 7 tr (8.89 + 0.20) REF 3 PLCS MOV A,H of H in Carry + 025 = 0.003 RAL A (0.635 = 0.075) MOV H,A RET Table VI. Sample Routine for AD75438085 Interface 0.020 x as* BONDING DIAGRAM ~ Cher 0.096 (2.438) | < OuT2 ouT) RFB 20-Pin Plastic Leaded Chip Carrier (P-20A) Package w mm) aso 0.008 (e388 20-188) z + 0.00! [* (9.905 +0.125) 52 | 0.105 +0.015 a (2.665 + 0.375) - (e308 20.076) 8 . eh MN 2 t 8 oc V2 ~ a8 2085 a 7 (a3 eo.07e) = + 9029 =0.003 (0.737 + 0.076) 0.020 + 0.017 +0.004 os FF (0.432 +0.101) 4 2 v TT x LL. L fous) MIN SRI sTB2.LO2 STB 0.02 max 0.060 nay PADS ARE 0.004 x 0.004 INCHES (0.102 X 0.102mm) MIN. (1.53) TO MINIMIZE ESD HAZARD BOND DGND FIRST -3- REV. B