Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as "Cypress" document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com EZ-PDTM CCG2 Datasheet USB Type-C Port Controller USB Type-C Port Controller General Description EZ-PDTM CCG2 is a USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG2 provides a complete USB Type-C and U1SB Power Delivery port control solution for passive cables, active cables, and powered accessories. It can also be used in many upstream and downstream facing port applications. EZ-PD CCG2 uses Cypress's proprietary M0S8 technology with a 32-bit, 48-MHz Arm(R) Cortex(R)-M0 processor with 32-KB flash and integrates a complete Type-C Transceiver including the Type-C termination resistors RP, RD and RA. Applications Type-C Support USB Type-C EMCA cables USB Type-C powered accessories USB Type-C upstream facing ports USB Type-C downstream facing ports Low-Power Operation Features 32-bit MCU Subsystem 48-MHz ARM Cortex-M0 CPU 32-KB Flash 4-KB SRAM In-system reprogrammable 2.7-V to 5.5-V operation Two independent VCONN rails with integrated isolation between the two Independent supply voltage pin for GPIO that allows 1.71-V to 5.5-V signaling on the I/Os Reset: 1.0 A, Deep Sleep: 2.5 A, Sleep: 2.0 mA System-Level ESD on CC and VCONN Pins Integrated Digital Blocks Integrated timers and counters to meet response times required by the USB-PD protocol Run-time reconfigurable serial communication block (SCB) with reconfigurable I2C, SPI, or UART functionality Clocks and Oscillators Integrated transceiver (baseband PHY) Integrated UFP (RD), EMCA (RA) termination resistors, and current sources for DFP (RP) Supports one USB Type-C port Integrated oscillator eliminating the need for external clock 8-kV Contact Discharge and 15-kV Air Gap Discharge based on IEC61000-4-2 level 4C Packages 1.63 mm x 2.03 mm, 20-ball wafer-level CSP (WLCSP) with 0.4-mm ball pitch 2.5 mm x 3.5 mm x 0.6 mm 14-pin DFN 4.0 mm x 4.0 mm, 0.55 mm 24-pin QFN Supports industrial (40 C to +85 C) and extended industrial (40 C to +105 C) temperature ranges Logic Block Diagram CCG2: USB Type-C Cable Controller MCU Subsystem I/O Subsystem Integrated Digital Blocks CC5 TCPWM1 Flash (32 KB) SRAM (4 KB) SCB2 (I2C, SPI, UART) VCONN2 SCB2 (I2C, SPI, UART) Programmable IO Matrix 48 MHz Advanced High-Performance Bus (AHB) VCONN1 CORTEX-M0 Profiles and Configurations Baseband MAC Baseband PHY VDDIO GPIO6 Port Integrated Rd3, Ra4, and Rp7 Serial Wire Debug 1 Timer, counter, pulse-width modulation block Serial communication block configurable as UART, SPI, or I2C Termination resistor denoting a UFP resistor denoting an EMCA 5 Configuration Channel 6 General-purpose input/output 7 Current Sources to indicate a DFP 2 3 4 Termination Cypress Semiconductor Corporation Document Number: 001-93912 Rev. *M * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 11, 2018 EZ-PDTM CCG2 Datasheet Available Firmware and Software Tools EZ-PD Configuration Utility The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through the process of configuring and programming the chip. The utility allows users to: 1. Select and configure the parameters they want to modify 2. Program the resulting configuration onto the target CCGx device. The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port controllers, will be provided in later versions of the utility. You can download the EZ-PD Configuration Utility and its associated documentation at the following link: http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility Document Number: 001-93912 Rev. *M Page 2 of 36 EZ-PDTM CCG2 Datasheet Contents Functional Overview .........................................................4 CPU and Memory Subsystem .....................................4 USB-PD Subsystem (SS) ............................................5 System Resources .......................................................5 Peripherals ..................................................................6 GPIO ............................................................................6 Pinouts............................................................................... 7 Power .................................................................................9 Application Diagrams .....................................................10 Electrical Specifications .................................................19 Absolute Maximum Ratings ....................................... 19 Device Level Specifications .......................................20 Digital Peripherals...................................................... 22 Memory...................................................................... 24 System Resources..................................................... 25 Ordering Information ...................................................... 28 Document Number: 001-93912 Rev. *M Ordering Code Definitions ......................................... 28 Packaging ........................................................................29 Acronyms ........................................................................32 Document Conventions ................................................. 33 Units of Measure ....................................................... 33 References and Links To Applications Collaterals .... 34 Document History Page .................................................35 Sales, Solutions, and Legal Information ...................... 36 Worldwide Sales and Design Support ....................... 36 Products ....................................................................36 PSoC(R)Solutions ........................................................36 Cypress Developer Community .................................36 Technical Support ......................................................36 Page 3 of 36 EZ-PDTM CCG2 Datasheet Figure 1. EZ-PD CCG2 Block Diagram CPU Subsystem AHB-Lite SPCIF FLASH 32 KB SRAM 4 KB SROM 8 KB FAST MUL NVIC, IRQMX Read Accelerator SRAM Controller SROM Controller System Resources Lite Power Sleep Control WIC POR REF PWRSYS System Interconnect (Single Layer AHB) Peripherals Peripheral Interconnect (MMIO) PCLK Clock Clock Control WDT IMO ILO 6 x TCPWM CC BB PHY Test DFT Logic DFT Analog IOSS GPIO (3 x ports) Reset Reset Control XRES USB-PD SS High Speed I/O Matrix Power Modes Active/Sleep Deep Sleep 2 X VCONN 32-bit SWD/TC Cortex M0 48 MHz 2 x SCB CCG2 Pads, ESD 12 x GPIOs, 2 x OVTs I/O Subsystem Functional Overview CPU and Memory Subsystem CPU The Cortex-M0 CPU in EZ-PD CCG2 is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex-M3 and M4, thus enabling upward compatibility. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and also includes a Wakeup Interrupt Controller (WIC). The WIC can wake the processor up from the Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. Document Number: 001-93912 Rev. *M The CPU also includes a serial wire debug (SWD) interface, which is a 2-wire form of JTAG. The debug configuration used for EZ-PD CCG2 has four break-point (address) comparators and two watchpoint (data) comparators. Flash The EZ-PD CCG2 device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. SROM A supervisory ROM that contains boot and configuration routines is provided. Page 4 of 36 EZ-PDTM CCG2 Datasheet USB-PD Subsystem (SS) EZ-PD CCG2 USB-PD sub-system can be configured to respond to SOP, SOP', or SOP" messaging. EZ-PD CCG2 has a USB-PD subsystem consisting of a USB Type-C baseband transceiver and physical-layer logic. This transceiver performs the BMC and the 4b/5b encoding and decoding functions as well as the 1.2-V front end. This subsystem integrates the required termination resistors to identify the role of the EZ-PD CCG2 solution. RA is used to identify EZ-PD CCG2 as an accessory or an electronically marked cable. RD is used to identify EZ-PD CCG2 as a UFP in a hybrid cable or a dongle. When configured as a DFP, integrated current sources perform the role of RP or pull-up resistors. These current sources can be programmed to indicate the complete range of current capacity on VBUS defined in the Type-C spec. EZ-PD CCG2 responds to all USB-PD communication. The The USB-PD sub-system contains a 8-bit SAR (Successive Approximation Register) ADC for analog to digital conversions. The ADC includes a 8-bit DAC and a comparator. The DAC output forms the positive input of the comparator. The negative input of the comparator is from a 4-input multiplexer. The four inputs of the multiplexer are a pair of global analog multiplex busses an internal bandgap voltage and an internal voltage proportional to the absolute temperature. All GPIO inputs can be connected to the global Analog Multiplex Busses through a switch at each GPIO that can enable that GPIO to be connected to the mux bus for ADC use. The CC1, CC2 and RD1 pins are not available to connect to the mux busses. Figure 2. USB-PD Subsystem To/From system Resources vref iref VDDD VCONN power logic To/ from AHB 8-bit ADC VDDD Enable Logic From AMUX Ra Enable VConn1 detect VConn2 detect VCONN1 Ra VCONN Detect Ra VCONN2 TxRx Enable 8kV IEC ESD Digital Baseband PHY Tx_data from AHB Analog Baseband PHY Enable Logic Tx SRAM 4b5b Encoder SOP Insert BMC Encoder Rx_data to AHB Rp TX CRC CC1 RD1 RX Rx SRAM 4b5b Decoder SOP Detect BMC Decoder CC2 Comp CC control CC detect Deep Sleep Reference Enable Deep Sleep Vref & Iref Gen Ref Active Rd DB Rd 8kV IEC ESD vref, iref Functional, Wakeup Interrupts System Resources Power System Clock System The power system is described in detail in the section Power on page 9. It provides assurance that voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (Brown-Out Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). EZ-PD CCG2 can operate from three different power sources over the range of 2.7 to 5.5 V and has three different power modes, transitions between which are managed by the power system. EZ-PD CCG2 provides Sleep and Deep Sleep low-power modes. The clock system for EZ-PD CCG2 consists of the Internal Main Oscillator (IMO) and the Internal Low-power Oscillator (ILO). Document Number: 001-93912 Rev. *M Page 5 of 36 EZ-PDTM CCG2 Datasheet Peripherals GPIO Serial Communication Blocks (SCB) EZ-PD CCG2 has up to 10 GPIOs in addition to the I2C and SWD pins, which can also be used as GPIOs. The I2C pins from SCB 0 are overvoltage-tolerant. The number of available GPIOs vary with the package. The GPIO block implements the following: EZ-PD CCG2 has two SCBs, which can be configured to implement an I2C, SPI, or UART interface. The hardware I2C blocks implement full multi-master and slave interfaces capable of multimaster arbitration. In the SPI mode, the SCB blocks can be configured to act as master or slave. In the I2C mode, the SCB blocks are capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and have flexible buffering options to reduce interrupt overhead and latency for the CPU. These blocks also support I2C that creates a mailbox address range in the memory of EZ-PD CCG2 and effectively reduce I2C communication to reading from and writing to an array in memory. In addition, the blocks support 8-deep FIFOs for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduce the need for clock stretching caused by the CPU not having read data on time. The I2C peripherals are compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/Os are implemented with GPIO in open-drain modes. I2C The port on SCB 1 block of EZ-PD CCG2 is not completely compliant with the I2C spec in the following respects: 2 The GPIO cells for SCB 1's I C port are not overvoltage-tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a VOL maximum of 0.6 V. Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the bus load. Seven drive strength modes: Input only Weak pull-up with strong pull-down Strong pull-up with weak pull-down Open drain with strong pull-down Open drain with strong pull-up Strong pull-up with strong pull-down Weak pull-up with weak pull-down Input threshold select (CMOS or LVTTL) Individual control of input and output buffer enabling/disabling in addition to the drive strength modes Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode) Selectable slew rates for dV/dt related noise control to improve EMI During power-on and reset, the I/O pins are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Timer/Counter/PWM Block (TCPWM) EZ-PD CCG2 has six TCPWM blocks. Each implements a 16-bit timer, counter, pulse-width modulator (PWM), and quadrature decoder functionality. The block can be used to measure the period and pulse width of an input signal (timer), find the number of times a particular event occurs (counter), generate PWM signals, or decode quadrature signals. Document Number: 001-93912 Rev. *M Page 6 of 36 EZ-PDTM CCG2 Datasheet Pinouts Group Name Pin Map 24-QFN Ball Location 20-CSP Pin Map 14-DFN USB Type-C Port CC1 2 B4 3 USB PD connector detect/Configuration Channel 1 CC2 1 A4 N/A USB PD connector detect/Configuration Channel 2 RD1 3 B3 N/A Dedicated Rd resistor pin for CC1 Must be left open for cable applications and connected together with CC1 ball for UFP or DFP with dead battery applications GPIO 22 C3 N/A GPIO / SPI_0_CLK / UART_0_ RX GPIO 18 D3 13 GPIO / SPI_0_MOSI / UART_0_TX GPIO 13 C2 10 GPIO / I2C_1_SDA / SPI_1_MISO / UART_1_RX GPIO 10 D2 N/A GPIO / I2C_1_SCL / SPI_1_CLK / UART_1_TX GPIO 15 B2 11 GPIO 14 N/A N/A GPIO GPIO 17 N/A N/A GPIO GPIO 21 N/A N/A GPIO GPIO 23 N/A N/A GPIO GPIO GPIOs and serial interfaces Description GPIO / SPI_1_SEL / UART_1_RTS GPIO 24 N/A N/A I2C_0_SCL 20 A3 1 GPIO / I2C_0_SCL / SPI_0_MISO / UART_0_RTS I2C_0_SDA 19 A2 14 GPIO / I2C_0_SDA / SPI_0_SEL / UART_0_CTS SWD _IO 11 E2 8 SWD IO / GPIO / UART_1_CTS / SPI_1_MOSI SWD_CLK 12 D1 9 SWD clock / GPIO RESET XRES 16 B1 12 Reset input POWER VCONN1 5 E4 5 VCONN 1 input (4.0 V to 5.5 V) VCONN2 4 C4 4 VCONN 2 input (4.0 V to 5.5 V) VDDIO 8 E1 N/A 1.71-V to 5.5-V supply for I/Os VCCD 7 A1 6 E3 7 N/A EPAD VDDD 9 VDDD 6 VSS VSS EPAD VSS Document Number: 001-93912 Rev. *M D4 C1 2 1.8-V regulator output for filter capacitor VDDD supply input/output (2.7 V to 5.5 V) VDDD supply input/output (2.7 V to 5.5 V) Ground supply Ground supply Ground supply Page 7 of 36 EZ-PDTM CCG2 Datasheet Figure 3. 20-ball WLCSP EZ-PD CCG2 Ball Map (Bottom (Balls Up) View) 4 3 2 1 I2C_0_SCL I2C_0_SDA VCCD A CC1 RD1 GPIO XRES B VCONN2 GPIO GPIO VSS C VSS GPIO GPIO SWD_CLK D VCONN1 VDDD SWD_IO VDDIO E CC2 Figure 4. 14-pin DFN Pin Map (Top View) I2C_0_SCL 1 14 I2C_0_SDA VSS 2 GPIO GPIO GPIO CC1 3 13 12 VCONN2 VCONN1 4 5 11 10 VCCD 6 9 SWD_CLK VDDD 7 8 SWD_IO XRES Document Number: 001-93912 Rev. *M GPIO GPIO GPIO GPIO I2C_0_SCL I2C_0_SDA 24 23 22 21 20 19 Figure 5. 24-Pin QFN Pin Map (Top View) CC2 1 18 GPIO CC1 2 17 GPIO RD1 VCONN2 VCONN1 3 16 15 14 XRES GPIO GPIO VDDD 6 13 GPIO 12 9 VDDD SWD_CLK 8 10 11 7 VCCD VDDIO GPIO SWD_IO EPAD 4 5 Page 8 of 36 EZ-PDTM CCG2 Datasheet Power A separate I/O supply pin, VDDIO, allows the GPIOs to operate at levels from 1.71 to 5.5 V. The VDDIO pin can be equal to or less than the voltages connected to the VCONN1, VCONN2, and VDDD pins. The independent VDDIO supply is not available on the 14-DFN package. On this package, the VDDIO rail is internally connected to the VDDD rails. The following power system diagram shows the set of power supply pins as implemented in EZ-PD CCG2. EZ-PD CCG2 can operate from three different power sources. VCONN1 and VCONN2 pins can be used as connections to the VCONN pins on a Type-C plug of a cable or VCONN-powered accessory. Each of these inputs support operation over 4.0 to 5.5 V. An internal isolation between VCONN1 and VCONN2 pins is provided allowing them to be at different levels simultaneously. CCG2 can be used in EMCA applications with only one or both VCONN pins as power sources. This is illustrated later in the section on Applications. Besides being power inputs, each VCONN pin is also internally connected to a RA termination resistor required for EMCA and VCONN-powered accessories. The VCCD output of EZ-PD CCG2 must be bypassed to ground via an external capacitor (in the range of 1 to 1.6 F; X5R ceramic or better). Bypass capacitors must be used from VDDD and VCONN pins to ground; typical practice for systems in this frequency range is to use a 0.1-F capacitor. Note that these are simply rules of thumb and that for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. EZ-PD CCG2 can also be operate from 2.7 to 5.5 V when operated from the VDDD supply pin. VCONN-powered accessory applications require that CCG2 work down to 2.7 V. In such applications, both the VDDD and VCONN pins should be connected to the VCONN pin of the Type-C plug in the accessory. An example of the power supply bypass capacitors is shown in Figure 6. In UFP, DFP, and DRP applications, CCG2 can be operated from VDDD as the only supply input. In such applications, the VCONN pins are left open. In DFP applications, the lowest VDDD level that CCG2 can operate is 3.0 V due to the need to support disconnect detection thresholds of up to 2.7 V. Figure 6. EZ-PD CCG2 Power and Bypass Scheme Example VCONN1 0.1uF VCONN2 RA 0.1uF RA VDDD 1uF Core Regulator (srsslt) VCCD VDDIO 1uF GPIO Core CC Tx/Rx VSS Document Number: 001-93912 Rev. *M Page 9 of 36 EZ-PDTM CCG2 Datasheet Application Diagrams device can be powered irrespective of which plug is connected to the host (DFP). However, in the application diagrams shown in Figure 9 and Figure 10, the VCONN signal does not run through the entire cable, but only runs to the respective VCONN pin of the CCG2 device at each end of the plug. Also, only one CCG2 device is powered at any given instance, depending on which one is nearer to the DFP that supplies VCONN. Figure 7 to Figure 10 show the application diagrams of a Passive EMCA application using CCG2 devices. Figure 7 and Figure 8 show the application using a single CCG2 device per cable present at one of the two plugs, whereas Figure 9 and Figure 10 show the same with two CCG2 devices per cable present at each plug. The VBUS signal, the SuperSpeed lines, HighSpeed lines, and CC lines are connected directly from one end to another. Note: Application diagram in Figure 8 requires external diodes to operate in the extended VCONN voltage range of 2.7V to 5.5V. The application diagrams shown in Figure 7 and Figure 8 require a single VCONN wire to run through the cable so that the CCG2 Figure 7. Passive EMCA Application - Single EZ-PD CCG2 Per Cable (VCONN range between 4.0V to 5.5V) Type-C Plug Type-C Plug VBUS VCONN 2 VCONN 1 1uF E4 E3 E1 VDDD VDDIO VCONN2 VCONN1 0.1uF C3 A1 VDDIO 4.7 k 1uF GPIO GPIO GPIO GPIO VCCD CCG2 B1 20-CSP XRES CC2 0.1uF C2 D2 B2 A4 CC1 B4 D4 VSS C1 VSS I2C_0 I2C_0 _SCL _SDA A2 A3 GPIO C4 D3 RD1 B3 SWD_ SWD_ IO CLK D1 E2 CC SuperSpeed and HighSpeed Lines GND Document Number: 001-93912 Rev. *M Page 10 of 36 EZ-PDTM CCG2 Datasheet Figure 8. Passive EMCA Application - Single EZ-PD CCG2 Per Cable (VCONN range between 2.7V to 5.5V) Type-C Plug Type-C Plug VBUS Select a diode with VF less than 0.3V at 10mA VCONN 1 NSR0620P2T5G NSR0620P2T5G 1 2 1 VCONN 2 2 1uF E4 E3 E1 VDDD VDDIO VCONN2 VCONN1 0.1uF C3 GPIO GPIO GPIO GPIO A1 1uF B1 D4 VCCD CCG2 CC2 XRES 0.1uF C2 D2 B2 A4 CC1 B4 VSS C1 VSS I2C_0 I2C_0 _SCL _SDA A2 A3 GPIO C4 D3 RD1 B3 SWD_ SWD_ IO CLK D1 E2 CC SuperSpeed and HighSpeed Lines GND Document Number: 001-93912 Rev. *M Page 11 of 36 EZ-PDTM CCG2 Datasheet Figure 9. Passive EMCA Application - Single EZ-PD CCG2 Per Plug (VCONN range between 4.0V to 5.5V) Type-C Plug Type-C Plug VBUS VCONN VCONN 1uF 1uF E4 E3 E1 VDDD VDDIO C4 VCONN2 VCONN1 0.1uF A1 1uF VDDIO GPIO GPIO VCCD GPIO GPIO CCG2 4.7k B1 CC2 XRES D4 VSS C1 VSS C3 C2 A1 D2 1uF VDDIO E4 VCONN1 GPIO D3 GPIO GPIO CCG2 4.7k A4 B1 B3 C1 VSS D2 B2 A4 CC2 XRES D4 VSS 0.1uF C2 GPIO VCCD CC1 B4 RD1 E1 VDDIO B2 CC1 B4 RD1 I2C_0 I2C_0 _SCL _SDA A2 A3 SWD_ SWD_ IO CLK E2 D1 I2C_0 I2C_0 _SCL _SDA A2 A3 E3 VDDD VCONN2 GPIO D3 GPIO C3 C4 B3 SWD_ SWD_ IO CLK D1 E2 CC SuperSpeed and HighSpeed Lines GND Figure 10. Passive EMCA Application - Single EZ-PD CCG2 Per Plug (VCONN range between 2.7V to 5.5V) Type-C Plug Type-C Plug VBUS VCONN2 VCONN1 1uF 1uF B1 A1 A2 VDDD VDDIO VCONN2 VCONN1 0.1uF GPIO GPIO D1 1uF D3 A1 D2 GPIO GPIO 1uF XRES CC1 C1 VSS I2C_SCL I2C_SDA C4 B4 RD1 VCONN2 C2 CCG2 CC2 A2 VDDIO B2 D1 VCCD B1 VDDD VCONN1 C3 D3 CC2 D4 C1 VSS B3 0.1uF B2 CCG2 VCCD XRES CC1 RD1 I2C_SCL I2C_SDA SWD_IO SWD_CLK A4 A3 D2 C2 B4 C4 C3 D4 B3 SWD_IO SWD_CLK A3 A4 CC SuperSpeed and HighSpeed Lines GND Document Number: 001-93912 Rev. *M Page 12 of 36 EZ-PDTM CCG2 Datasheet Figure 11 shows a CCG2 device being used in a UFP application (tablet with a Type-C port) only as a power consumer. The Type-C receptacle brings in HighSpeed and SuperSpeed lines, which are connected directly to the applications processor. The VBUS line from the Type-C receptacle goes directly to the UFP (tablet) charger circuitry. The applications processor communicates over the I2C signal with the CCG2 device, and the CC1 and CC2 lines from the Type-C receptacle are connected directly to the respective CC1/2 pins of the CCG2 device. Figure 11. Upstream Facing Port (UFP) Application - Tablet with a Type-C Port Charger VBUS 5.0 V 1.8 V 1 uF 1 uF E3 C4 E4 1.8 V E2 D1 4.7 k 4.7 k INT Application Processor VCONN2 E1 VDDD VDDIO VCONN1 GPIO GPIO SWD_IO GPIO SWD_CLK GPIO CCG2 D3 C2 D2 B2 CC2 A3 I2C_0_SCL CC1 B4 A2 I2C_0_SDA RD1 VSS D4 VSS C1 VCCD A1 1 uF Type-C Receptacle A4 C3 GPIO B3 XRES B1 390 pF 390 pF 1.8 V 4.7 k HighSpeed Lines Application Processor/ Graphics Controller SuperSpeed Lines Figure 12 shows a Notebook DRP application diagram using a CCG2 device. The Type-C port can be used as a power provider or a power consumer. The CCG2 device communicates with the Embedded controller (EC) over I2C. It also controls the Data Mux to route the High Speed signals either to the USB chipset (during normal mode) or the DisplayPort Chipset (during Alternate Mode). The SBU lines, SuperSpeed and HighSpeed lines are routed directly from the Display Mux of the notebook to the Type-C receptacle. Document Number: 001-93912 Rev. *M Optional FETs are provided for applications that need to provide power for accessories and cables using the VCONN pin of the Type-C receptacle. VBUS FETs are also used for providing power over VBUS and for consuming power over VBUS. A VBUS_DISCHARGE FET controlled by CCG2 device is used to quickly discharge VBUS after the Type-C connection is detached. Page 13 of 36 EZ-PDTM CCG2 Datasheet Figure 12. Dual Role Port (DRP) Application VBUS_SINK CHARGER VBUS FETs for CONSUMER PATH VBUS_C_CTRL VBUS FETs for PROVIDER PATH VBUS_SOURCE DC/DC 3.3V VBUS (5-20V) VBUS VDDIO VBUS_P_CTRL 4 11 2.2k 2.2k 12 2.2k I2C_INT 14 20 Embedded Controller 19 VDDIO 4.7k 16 7 VCCD 8 VDDIO VDDD VCONN1 VDDD 5 VDDIO 9 1uF 6 1uF GPIO VCONN2 GPIO SWD_IO GPIO SWD_CLK GPIO CCG2 24-QFN GPIO I2C_0_SCL GPIO CC2 I2C_0_SDA CC1 XRES RD1 15 VBUS_P_CTRL 18 VBUS_C_CTRL 22 VBUS_DISCHARGE 21 CC2_VCONN_CTRL 24 CC1_VCONN_CTRL 5.0V VBUS_DISCHARGE 5.0V OPTIONAL FETS for DFPs SUPPORTING VCONN 1 CC2 2 3 Type-C Receptacle CC1 VBUS 390pF 390pF USB Chipset D+/- 13 GPIO 10 GPIO VSS 23 GPIO 100k EPAD GPIO 17 VBUS_MON 10k HPD SS SS D+/- DisplayPort Chipset SCL SDA HPD HS/SS/DP/ SBU Lines DP/DN GND SS Data Mux DP0/1/2/3 AUX+/- Document Number: 001-93912 Rev. *M Page 14 of 36 EZ-PDTM CCG2 Datasheet Figure 13 shows a CCG2 receptacle-based Power Adapter application in which the CCG2 device is used as a DFP. CCG2 integrates all termination resistors and uses GPIOs (VSEL_0 and VSEL_1) to indicate the negotiated power profile. The VBUS voltage on the Type-C port is monitored using internal ADC to detect undervoltage and overvoltage conditions on VBUS. To ensure quick discharge of VBUS when the power adapter cable is detached, a discharge path is also provided. Figure 13. Downstream Facing Port (DFP) Application VSEL_1 VSEL_0 DC/DC OR AC-DC SECONDARY (5-20V) VBUS (5-20V) VBUS_IN OPTIONAL VDDIO SUPPLY. CAN SHORT VDDIO TO VDDD IN SINGLE SUPPLY SYSTEMS 3.3V VBUS_P_CTRL 11 VBUS_IN 5V 9V 15V 20V 12 14 VSEL_1 20 VSEL_0 19 VDDIO 4.7k 16 EPAD Document Number: 001-93912 Rev. *M 7 VCCD 8 VDDIO VDDD VDDD GPIO VCONN2 GPIO SWD_IO GPIO SWD_CLK GPIO CCG2 24-QFN GPIO GPIO GPIO CC2 GPIO CC1 XRES RD1 VSS 13 GPIO VSEL_0 0 1 0 1 4 VCONN1 10 GPIO VSEL_1 0 0 1 1 5 23 GPIO VSEL_1 and VSEL_0 CONTROL THE SECONDARY SIDE OF AN AC-DC OR A DC-DC TO SELECT THE VOLTAGE ON VBUS_IN. AN EXAMPLE IS SHOWN BELOW: 9 1uF 6 1uF 15 VBUS_P_CTRL 5.0V 18 22 VBUS_DISCHARGE 21 CC2_VCONN_CTRL 24 CC1_VCONN_CTRL VBUS_DISCHARGE Type-C Receptacle 5.0V OPTIONAL FETS for DFPs SUPPORTING VCONN 1 2 3 VBUS 390pF 390pF 100k GPIO 17 VBUS_MON 10k Page 15 of 36 EZ-PDTM CCG2 Datasheet Figure 14 shows a USB Type-C to HDMI/DVI/VGA adapter application, which enables connectivity between a PC that supports a Type-C port with DisplayPort Alternate Mode support and a legacy monitor that has HDMI/DVI/VGA interface. It enables users of any Notebook that implements USB-Type C to connect to other display types. cation meets the requirements described in Section 4.3 of the VESA DisplayPort Alt Mode on USB Type-C Standard Version 1.0. This application supports display output at a resolution of up to 4K Ultra HD (3840x2160) at 60 Hz. It also supports the USB Billboard Device Class, which is required by the USB PD specification for enumeration of any accessories that support Alternate Mode when connected to a host PC. This application has a Type-C plug on one end and the legacy video (HDMI/DVI/VGA) receptacle on the other end. This appli- Figure 14. USB Type-C to HDMI/DVI/VGA Dongle Application Diagram 5V VBUS_VCONN 1.2V VBUS 3.3V Power OR Regulator BuckBoost VCONN VBUS D+/- USB-Billboard CY7C65210 XRES INT SDA 3.3V SCL 2.2k: 5% 2.2k: 5% VBUS_VCONN VCONN Type-C Plug 0.1F 1F 3.3V 1F CC VBUS 2.2k: 5% 18 22 10 13 P1.7 P2.1 P1.3 P1.0 14 4 P1.4 VCONN2 4.7K 16 17 XRES P1.6 5 12 VCONN1 SWD_CLK 6 11 VDDD1 SWD_IO 9 21 VDDD2 CYPD2119 P2.0 24QFN 8 23 VDDIO P2.2 2 CC1 7 VCCD 3 RD1 1 CC2 EPAD P2.3:P0.0 P0.1 P1.5 15 [24:19] 20 100K, 1% HDMI/DVI/ VGA Receptacle 10K, 1% 1F HotPlug Detect 3.3V 1.2V SBU_1/2 Display Port Data Lanes Document Number: 001-93912 Rev. *M SW for AUX DP to HDMI/ DVI/VGA Convertor Page 16 of 36 EZ-PDTM CCG2 Datasheet Type-C to DisplayPort Cables). It also supports the USB Billboard Device Class, which is required by the USB PD specification for enumeration of any accessories that support Alternate Mode when connected to a host PC. Figure 15 shows a USB Type-C to DisplayPort adapter application, which enables connectivity between a PC that supports a Type-C port with DisplayPort Alternate Mode support and a legacy monitor that has a DisplayPort interface. Figure 15 shows a Type-C plug on one end and a DP/mDP plug on the other end. The application meets the requirements described in Section 4.2 of the VESA DisplayPort Alt Mode on USB Type-C Standard Version 1.0 (Scenarios 2a and 2b USB Figure 15. USB Type-C to Display Port Application Diagram Paddle Card VBUS_VCONN VBUS Power OR VCONN VBUS D+/USB-Billboard CY7C65210 XRES INT SDA VBUS_VCONN SCL 2.2k: 5% 2.2k: 5% VBUS Type-C Plug VCONN 0.1F VBUS_VCONN 1F CC 2.2k: 5% 18 22 10 13 P1.7 P2.1 P1.3 P1.0 14 4 P1.4 VCONN2 4.7K 16 17 XRES P1.6 5 12 VCONN1 SWD_CLK 6 11 VDDD1 SWD_IO 9 21 VDDD2 CYPD2120 P2.0 24QFN 8 23 VDDIO P2.2 2 CC1 7 VCCD 3 RD1 1 CC2 EPAD P2.3:P0.0 P0.1 P1.5 15 [24:19] 20 100K, 1% mDP/ DP 10K, 1% 1F HotPlug Detect SBU_1/2 Display Port Data Lanes Document Number: 001-93912 Rev. *M SW for AUX AUX_P/N Display Port Data Lanes Page 17 of 36 EZ-PDTM CCG2 Datasheet Figure 16 shows a CCG2 Monitor/Dock application diagram. It enables connectivity between a USB Type-C host system on the Upstream port and multiple Display/Data devices on the Downstream port. This application has a USB Type-C receptacle on the Upstream port, which supports data, power, and display. On the Downstream port, this application supports: USB Type-A, Gigabit Ethernet, DisplayPort, and USB Type-C receptacle. The main features of this solution are: Powered from an external 24-V DC power adapter Provides up to 45 W (15 V at 3A) on the Upstream Type-C port and up to 15 W (5 V at 3A) on the Downstream USB Type-C port Provides simultaneous 4K display output with USB 3.1 Gen 1 on the USB Type-A port Four-lane display on the DisplayPort connector Multi-Stream support on DisplayPort and Downstream Type-C port USB 3.1 Gen 1 hub for USB port expansion Gigabit Ethernet using RJ45 connector Supports firmware upgrade of CCG2 controllers, HX3 Hub controller, and Billboard controller Figure 16. CCG2 in Dock/Monitor Application Diagram 5-20V 5.0V DS_I2C_INT VSEL_0 Regulator 5-20V 5V 1.2V 3.3V VBUS_DS VSEL_1 VBUS_US Power In Brick 5V 100K Power INT2 100K USB-Billboard CY7C65210 100 INT1 SDA HS_DS2 6 9 16 0.1F CC1 CC2 2 3 1 US_VBUS_DIS XRES Cypress USB3.0 HUB CYPD2121 24QFN CC1 P1.6 17 SWD_IO_P1.1 11 VCCD 7 RD1 HUB_VBUS_US 10K, 1% USB D+/SS Data Lines 1F CC2 EPAD 22 P2.1 SWD_CLK_P1.2 P2.2 12 23 USB Type-A Receptacle 100K, 1% CYUSB3304 -68LTXC DS1 HS_DS2 DS3 HS_DS4 SS_DS4 Ethernet GX3 10K, 1% CYUSB361068LTXC SCL 1F DS_HotPlug Detect SDA SDA SCL HPD DP2 SBU_1/2 DP Port Type-C Mux SS Data Lanes DP Spliter 20 19 22 24 P1.3 P0.1 P0.0 P2.1 P2.3 15 P1.5 10 P1.0 5 18 P1.7 VCONN1 8 VDDIO 6 4 VCONN2 VDDD1 DFP 9 VDDD2 CYPD2125 16 17 P1.6 XRES 24QFN 11 3 SWD_IO RD1 7 VCCD 2 CC1 200K 13 I2C Master DS_HotPlug Detect HPD 2.2k: 5% VBUS USB Hub HotPlug Detect USB D+/- 2.2k: 5% 100K 3.3V Type-C to Device VCONN 100K 1F 0.1F 200K 0.1F CC1 CC2 1 CC2 EPAD 21 P2.2 P1.4 SWD_CLK P2.0 14 12 23 DS_I2C_INT 1F 2.2k: 5% 20 14 19 2.2k: 5% 13 P1.4 P0.0 P0.1 P1.3 I2C Master P1.5 P1.0 10 18 VSEL_0 VCONN1 P1.7 24 VSEL_1 VBUS P2.3 VDDIO 21 HUB_VBUS_US P2.0 VDDD1 DRP VCONN2 4 100K, 1% VDDD2 VCONN 100K 4.7K 0.1F 4.7K 8 SYS_I2C_SCL SYS_I2C_SDA 5 3.3V 2.2k: 5% 100K DS_VBUS_DIS 3.3V SYS_I2C_SCL 15 I2C Slave 2.2k: 5% SYS_I2C_SDA 100K Type-C to Notebook 2.2k: 5% US_VBUS_P_CTRL SYS_I2C_SCL SYS_I2C_SCL US_VBUS_DIS DS_VBUS_DIS US_VBUS_P_CTRL 1K Discharge NFET Discharge NFET 1K 3.3V SCL Type-C Mux SS_DS4 HS_DS4 SS Data Lines_1 SS Data Lines_2 DP2 CCG2 connected on the Downstream Port CCG2 connected on the Upstream Port Document Number: 001-93912 Rev. *M Page 18 of 36 EZ-PDTM CCG2 Datasheet Electrical Specifications Absolute Maximum Ratings Table 1. Absolute Maximum Ratings[1] Parameter Description Min Typ Max Units Details/Conditions VDDD_MAX Digital supply relative to VSS -0.5 - 6 V Absolute max VCONN1_MAX Max supply voltage relative to VSS - - 6 V Absolute max VCONN2_MAX Max supply voltage relative to VSS - - 6 V Absolute max VDDIO_MAX Max supply voltage relative to VSS - - 6 V Absolute max VGPIO_ABS GPIO voltage -0.5 - VDDIO + 0.5 V Absolute max VCC_ABS Absolute max voltage for CC1 and CC2 pins - - 6 V Absolute max IGPIO_ABS Maximum current per GPIO -25 - 25 mA Absolute max IGPIO_injection GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS -0.5 - 0.5 mA Absolute max, current injected per pin ESD_HBM Electrostatic discharge human body model 2200 - - V - ESD_CDM Electrostatic discharge charged device model 500 - - V - LU Pin current for latch-up -200 - 200 mA - ESD_IEC_CON Electrostatic discharge IEC61000-4-2 8000 - - V Contact discharge on CC1, CC2, VCONN1, and VCONN2 pins ESD_IEC_AIR Electrostatic discharge IEC61000-4-2 15000 - - V Air discharge for pins CC1, CC2, VCONN1, and VCONN2 Note 1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 001-93912 Rev. *M Page 19 of 36 EZ-PDTM CCG2 Datasheet Device Level Specifications All specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 3.0 V to 5.5 V, except where noted. Table 2. DC Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions SID.PWR#1 VDDD Power supply input voltage 2.7 - 5.5 V UFP Applications SID.PWR#1_A VDDD Power supply input voltage 3.0 - 5.5 V DFP/DRP Applications SID.PWR#23 VCONN1 Power supply input voltage 4.0 - 5.5 V - SID.PWR#23_A VCONN2 Power supply input voltage 4.0 - 5.5 V - SID.PWR#13 VDDIO GPIO power supply 1.71 - 5.5 V - SID.PWR#24 VCCD Output voltage (for core logic) - 1.8 - V - SID.PWR#15 CEFC External regulator voltage bypass on VCCD 1 1.3 1.6 F X5R ceramic or better SID.PWR#16 CEXC Power supply decoupling capacitor on VDDD - 1 - F X5R ceramic or better Power Supply Decoupling Capacitor on VCONN1 and VCONN2 - 0.1 - F X5R ceramic or better SID.PWR#25 Active Mode, VDDD = 2.7 to 5.5 V. Typical values measured at VDD = 3.3 V. SID.PWR#12 IDD12 Supply current - 7.5 - mA VCONN1 or VCONN2 = 5 V, TA = 25 C, CC I/O IN Transmit or Receive, RA disconnected, no I/O sourcing current, CPU at 12 MHz - 2.0 3.0 mA VDDD = 3.3 V, TA = 25 C, all blocks except CPU are ON, CC I/O ON, no I/O sourcing current Sleep Mode, VDDD = 2.7 to 5.5 V SID25A IDD20A I2C wakeup. WDT ON. IMO at 48 MHz Deep Sleep Mode, VDDD = 2.7 to 3.6 V (Regulator on) SID_DS_RA IDD_DS_RA VCONN1 = 5.0, RA termination disabled - 100 - A VCONN1, VCONN2 = 5 V, TA = 25 C. RA termination disabled on VCONN1 and VCONN2, see SID.PD.7. VCONN leaker circuits turned off during deep sleep SID34 IDD29 VDDD = 2.7 to 3.6 V. I2C wakeup and WDT ON - 50 - A RA switch disabled on VCONN1 and VCONN2. VDDD = 3.3 V, TA = 25 C SID_DS IDD_DS VDDD = 2.7 to 3.6 V. CC wakeup ON - 2.5 - A Power source = VDDD, Type-C not attached, CC enabled for wakeup, RP disabled IDD_XR Supply current while XRES asserted - 1 10 A XRES Current SID307 Document Number: 001-93912 Rev. *M - Page 20 of 36 EZ-PDTM CCG2 Datasheet Table 3. AC Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions DC - 48 MHz 3.0 V VDDD 5.5 V - 0 - s Guaranteed by characterization TDEEPSLEEP Wakeup from Deep Sleep mode - - 35 s 24-MHz IMO. Guaranteed by characterization SID.XRES#5 TXRES External reset pulse width 5 - - s Guaranteed by characterization SYS.FES#1 T_PWR_RDY Power-up to "Ready to accept I2C / CC command" - 5 25 ms Guaranteed by characterization SID.CLK#4 FCPU CPU frequency SID.PWR#20 TSLEEP Wakeup from sleep mode SID.PWR#21 I/O Table 4. I/O DC Specifications Spec ID Parameter Description VIH[2] Input voltage HIGH threshold SID.GIO#38 VIL Input voltage LOW threshold SID.GIO#39 VIH[2] LVTTL input, VDDIO < 2.7 V SID.GIO#37 Min Typ Max Units 0.7 x VDDIO - - V CMOS input Details/Conditions - - 0.3 x VDDIO V CMOS input 0.7x VDDIO - - V - SID.GIO#40 VIL LVTTL input, VDDIO < 2.7 V - - 0.3 x VDDIO V - SID.GIO#41 VIH[2] LVTTL input, VDDIO 2.7 V 2.0 - - V - SID.GIO#42 VIL LVTTL input, VDDIO 2.7 V - - 0.8 V - SID.GIO#33 VOH Output voltage HIGH level VDDIO - 0.6 - - V IOH = 4 mA at 3-V VDDIO SID.GIO#34 VOH Output voltage HIGH level VDDIO - 0.5 - - V IOH = 1 mA at 1.8-V VDDIO SID.GIO#35 VOL Output voltage LOW level - - 0.6 V IOL = 4 mA at 1.8-V VDDIO SID.GIO#36 VOL Output voltage LOW level - - 0.6 V IOL = 8 mA at 3 V VDDIO SID.GIO#5 RPULLUP Pull-up resistor 3.5 5.6 8.5 k - SID.GIO#6 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k - SID.GIO#16 IIL Input leakage current (absolute value) - - 2 nA 25 C, VDDIO = 3.0 V.Guaranteed by characterization SID.GIO#17 CIN Input capacitance - - 7 pF Guaranteed by characterization SID.GIO#43 VHYSTTL Input hysteresis LVTTL 25 40 - mV VDDIO 2.7 V. Guaranteed by characterization. SID.GPIO#44 VHYSCMOS Input hysteresis CMOS 0.05 x VDDIO - - mV Guaranteed by characterization SID69 IDIODE Current through protection diode to VDDIO/Vss - - 100 A Guaranteed by characterization SID.GIO#45 ITOT_GPIO Maximum total source or sink chip current - - 200 mA Guaranteed by characterization Note 2. VIH must not exceed VDDIO + 0.2 V. Document Number: 001-93912 Rev. *M Page 21 of 36 EZ-PDTM CCG2 Datasheet Table 5. I/O AC Specifications (Guaranteed by Characterization) Min Typ Max Units SID70 Spec ID TRISEF Parameter Rise time Description 2 - 12 ns 3.3-V VDDIO, Cload = 25 pF Details/Conditions SID71 TFALLF Fall time 2 - 12 ns 3.3-V VDDIO, Cload = 25 pF XRES Table 6. XRES DC Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions - - V CMOS input SID.XRES#1 VIH Input voltage HIGH threshold 0.7 x VDDIO SID.XRES#2 VIL Input voltage LOW threshold - - 0.3 x VDDIO V CMOS input SID.XRES#3 CIN Input capacitance - - 7 pF Guaranteed by characterization SID.XRES#4 VHYSXRES Input voltage hysteresis - - 0.05 x VDDIO mV Guaranteed by characterization Digital Peripherals The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode. Pulse Width Modulation (PWM) for GPIO Pins Table 7. PWM AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units Details/Conditions Fc max = CLK_SYS. Maximum = 48 MHz. SID.TCPWM.3 TCPWMFREQ Operating frequency - Fc - MHz SID.TCPWM.4 TPWMENEXT Input trigger pulse width - 2/Fc - ns For all Trigger Events SID.TCPWM.5 TPWMEXT Output trigger pulse width - 2/Fc - ns Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) outputs SID.TCPWM.5A TCRES Resolution of counter - 1/Fc - ns Minimum time between successive counts SID.TCPWM.5B PWMRES PWM resolution - 1/Fc - ns Minimum pulse width of PWM output SID.TCPWM.5C QRES Quadrature inputs resolution - 1/Fc - ns Minimum pulse width between quadrature-phase inputs Document Number: 001-93912 Rev. *M Page 22 of 36 EZ-PDTM CCG2 Datasheet I2C Table 8. Fixed I2C DC Specifications (Guaranteed by Characterization) Description Min Typ Max Units Details/Conditions SID149 Spec ID II2C1 Block current consumption at 100 kbps - - 60 A - SID150 II2C2 Block current consumption at 400 kbps - - 185 A - SID151 II2C3 Block current consumption at 1 Mbps - - 390 A - - - 1.4 A - Min Typ Max Units Details/Conditions - - 1 Mbps - Typ Max Units SID152 Parameter II2C4 2 I C enabled in Deep Sleep mode Table 9. Fixed I2C AC Specifications (Guaranteed by Characterization) Spec ID SID153 Parameter FI2C1 Description Bit rate Table 10. Fixed UART DC Specifications (Guaranteed by Characterization) Spec ID Parameter Description SID160 IUART1 Block current consumption at 100 Kbps SID161 IUART2 Block current consumption at 1000 Kbps Min Details/Conditions - - 125 A Guaranteed by characterization - - 312 A Guaranteed by characterization Table 11. Fixed UART AC Specifications (Guaranteed by Characterization) Spec ID SID162 Parameter FUART Description Min Typ Max Units Bit rate - - 1 Mbps Description Min Typ Max Details/Conditions Guaranteed by characterization Table 12. Fixed SPI DC Specifications (Guaranteed by Characterization) Spec ID Parameter Units Details/Conditions SID163 ISPI1 Block current consumption at 1 Mbps - - 360 A Guaranteed by characterization SID164 ISPI2 Block current consumption at 4 Mbps - - 560 A Guaranteed by characterization SID165 ISPI3 Block current consumption at 8 Mbps - - 600 A Guaranteed by characterization Min Typ Max Units Table 13. Fixed SPI AC Specifications (Guaranteed by Characterization) Spec ID SID166 Parameter FSPI Description SPI Operating frequency (Master; 6X oversampling) Document Number: 001-93912 Rev. *M - - 8 MHz Details/Conditions Guaranteed by characterization Page 23 of 36 EZ-PDTM CCG2 Datasheet Table 14. Fixed SPI Master Mode AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units Details/Conditions SID167 TDMO MOSI Valid after SClock driving edge - - 15 ns Guaranteed by characterization SID168 TDSI MISO Valid before SClock capturing edge 20 - - ns Full clock, late MISO sampling. Guaranteed by characterization ns Referred to Slave capturing edge. Guaranteed by characterization SID169 THMO Previous MOSI data hold time 0 - - Table 15. Fixed SPI Slave Mode AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units Details/Conditions SID170 TDMI MOSI Valid before Sclock Capturing edge 40 - - ns Guaranteed by characterization SID171 TDSO MISO Valid after Sclock driving edge - - 42 + 3 * TCPU ns TCPU = 1/FCPU. Guaranteed by characterization. SID171A TDSO_EXT MISO Valid after Sclock driving edge in Ext Clk mode - - 48 ns Guaranteed by characterization SID172 THSO Previous MISO data hold time 0 - - ns Guaranteed by characterization SID172A TSSELSCK SSEL Valid to first SCK Valid edge 100 - - ns Guaranteed by characterization Typ Max Memory Table 16. Flash AC Specifications Spec ID Parameter Description Min Units Details/Conditions SID.MEM#4 TROWWRITE[3] Row (block) write time (erase and program) Row (block) = 128 bytes - - 20 ms SID.MEM#3 TROWERASE[3] Row erase time - - 13 ms - SID.MEM#8 Row program time after erase - - 7 ms - SID178 TROWPROGRAM[3] TBULKERASE[3] Bulk erase time (32 KB) - - 35 ms - SID180 TDEVPROG[3] Total device program time - - 7.5 seconds Guaranteed by characterization SID181 FEND Flash endurance 100 K - - cycles Guaranteed by characterization SID182 FRET1 Flash retention. TA 55 C, 100 K P/E cycles 20 - - years Guaranteed by characterization SID182A FRET2 Flash retention. TA 85 C, 10 K P/E cycles 10 - - years Guaranteed by characterization Note 3. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 001-93912 Rev. *M Page 24 of 36 EZ-PDTM CCG2 Datasheet System Resources Power-on-Reset (POR) with Brown Out Table 17. Imprecise Power On Reset (PRES) Spec ID Parameter Description Min Typ Max Units Details/Conditions SID185 VRISEIPOR Rising trip voltage 0.80 - 1.50 V Guaranteed by characterization SID186 VFALLIPOR Falling trip voltage 0.75 - 1.4 V Guaranteed by characterization Min Typ Max Table 18. Precise Power On Reset (POR) Spec ID Parameter Description SID190 VFALLPPOR BOD trip voltage in active and sleep modes SID192 VFALLDPSLP BOD trip voltage in Deep Sleep Units Details/Conditions 1.48 - 1.62 V Guaranteed by characterization 1.1 - 1.5 V Guaranteed by characterization Min Typ Max Units SWD Interface Table 19. SWD Interface Specifications Spec ID Parameter Description Details/Conditions SID.SWD#1 F_SWDCLK1 3.3 V VDDIO 5.5 V - - 14 MHz SWDCLK 1/3 CPU clock frequency SID.SWD#2 F_SWDCLK2 1.8 V VDDIO 3.3 V - - 7 MHz SWDCLK 1/3 CPU clock frequency SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK 0.25*T - - ns Guaranteed by characterization SID.SWD#4 T_SWDI_HOLD T = 1/f SWDCLK 0.25*T - - ns Guaranteed by characterization SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK - - 0.5 * T ns Guaranteed by characterization SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK 1 - - ns Guaranteed by characterization Internal Main Oscillator Table 20. IMO DC Specifications (Guaranteed by Design) Spec ID SID218 Parameter IIMO Description Min Typ Max Units Details/Conditions IMO operating current at 48 MHz - - 1000 A - Table 21. IMO AC Specifications Spec ID Min Typ Max Units Details/Conditions SID.CLK#13 FIMOTOL Frequency variation at 24, 36, and 48 MHz (trimmed) - - 2 % - SID226 TSTARTIMO IMO startup time - - 7 s Guaranteed by characterization SID229 TJITRMSIMO RMS jitter at 48 MHz - 145 - ps Guaranteed by characterization IMO frequency 24 - 48 MHz FIMO Parameter - Description Document Number: 001-93912 Rev. *M - Page 25 of 36 EZ-PDTM CCG2 Datasheet Internal Low-Speed Oscillator Table 22. ILO DC Specifications (Guaranteed by Design) Spec ID Parameter Description Min Typ Max Units Details/Conditions SID231 IILO ILO operating current at 32 kHz - 0.3 1.05 A Guaranteed by Characterization SID233 IILOLEAK ILO leakage current - 2 15 nA Guaranteed by Design Details/Conditions Table 23. ILO AC Specifications Spec ID Parameter Description Min Typ Max Units SID234 TSTARTILO ILO startup time - - 2 ms Guaranteed by characterization SID236 TILODUTY ILO duty cycle 40 50 60 % Guaranteed by characterization ILO Frequency 20 40 80 kHz SID.CLK#5 FILO - Power Down Table 24. PD DC Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions SID.PD.1 Rp_std DFP CC termination for default USB Power 64 80 96 A - SID.PD.2 Rp_1.5A DFP CC termination for 1.5A power 166 180 194 A - SID.PD.3 Rp_3.0A DFP CC termination for 3.0A power 304 330 356 A - SID.PD.4 Rd UFP CC termination 4.59 5.1 5.61 k - SID.PD.5 Rd_DB UFP Dead Battery CC termination on RD1 and CC2 4.08 5.1 6.12 k All supplies forced to 0 V and 0.6 V applied at RD1 or CC2 SID.PD.6 RA Power cable termination 0.8 1.0 1.2 k All supplies forced to 0 V and 0.2 V applied at VCONN1 or VCONN2 SID.PD.7 Ra_OFF Power cable termination Disabled 0.4 0.75 - M 2.7 V applied at VCONN1 or VCONN2 with RA disabled SID.PD.8 Rleak_1 VCONN leaker for 0.1-F load - - 216 k SID.PD.9 Rleak_2 VCONN leaker for 0.5-F load - - 41.2 k SID.PD.10 Rleak_3 VCONN leaker for 1.0-F load - - 19.6 k SID.PD.11 Rleak_4 VCONN leaker for 2.0-F load - - 9.8 k SID.PD.12 Rleak_5 VCONN leaker for 5.0-F load - - 4.1 k SID.PD.13 Rleak_6 VCONN leaker for 10-F load - - 2.0 k SID.PD.14 Ileak Leaker on VCONN1 and VCONN2 for discharge upon cable detach 150 - - A Document Number: 001-93912 Rev. *M Managed Active Cable (MAC) discharge - Page 26 of 36 EZ-PDTM CCG2 Datasheet Analog-to-Digital Converter Table 25. ADC DC Specifications Spec ID Parameter Description Min Typ Max Units - 8 - bits Guaranteed by characterization Integral non-linearity -1.5 - 1.5 LSB Guaranteed by characterization Differential non-linearity -2.5 - 2.5 LSB Guaranteed by characterization -1 - 1 LSB Guaranteed by characterization Min Typ Max Units - - 3 SID.ADC.1 Resolution ADC resolution SID.ADC.2 INL SID.ADC.3 DNL SID.ADC.4 Gain Error Gain error Details/Conditions Table 26. ADC AC Specifications Spec ID Parameter Description Rate of change of sampled voltage SID.ADC.5 SLEW_Max signal Document Number: 001-93912 Rev. *M Details/Conditions V/ms Guaranteed by characterization Page 27 of 36 EZ-PDTM CCG2 Datasheet Ordering Information The EZ-PD CCG2 part numbers and features are listed in Table 27. Table 27. EZ-PD CCG2 Ordering Information Part Number Application CYPD2103-20FNXIT Type-C Ports Termination Resistor Cable 1 CYPD2103-14LHXIT Cable 1 CYPD2104-20FNXIT Accessory 1 CYPD2105-20FNXIT Active Cable 1 CYPD2119-24LQXIT C-DP 1 CYPD2120-24LQXIT C-HDMI 1 CYPD2121-24LQXIT Dock/Monitor Upstream port 1 CYPD2122-20FNXIT Tablet 1 Notebook 1 CYPD2122-24LQXIT Notebook 1 CYPD2125-24LQXIT Dock/Monitor Downstream port 1 CYPD2134-24LQXIT DFP 1 CYPD2134-24LQXQT DFP 1 CYPD2122-24LQXI RA[4] RA[4] RD[5] RA[4] RD[5] RD[5] [6] RP , RD[5] RP[6], RD[5] RP[6], RD[5] RP[6], RD[5] RP[6] RP[6] RP[6] Role Package Cable 20-ball CSP Cable 14-pin DFN Accessory 20-ball CSP Active Cable 20-ball CSP UFP 24-pin QFN UFP 24-pin QFN DRP 24-pin QFN DRP 20-ball CSP DRP 24-pin QFN DRP 24-pin QFN DFP 24-pin QFN DFP 24-pin QFN DFP 24-pin QFN Ordering Code Definitions CY PD 2 1 X X - XX XX X I T T = Tape and Reel Temperature Grade: I = Industrial (40 C to 85 C), Q = Extended Industrial (40 C to105 C) Pb-free Package Type: XX = FN, LH or LQ FN = CSP; LH = DFN; LQ = QFN Number of pins in the package: XX = 14, 20, or 24 Device Role: Unique combination of role and termination: X = 0 or 1 or 2 or 3 or 4 or 5 or 9 Feature: Unique Applications: X = 0 or 1 or 2 or 3 Number of Type-C Ports: 1 = 1 Port Product Type: 2 = Second-generation product family, CCG2 Marketing Code: PD = Power Delivery product family Company ID: CY = Cypress Notes 4. Termination resistor denoting an EMCA. 5. Termination resistor denoting an accessory or upstream facing port. 6. Termination resistor denoting a downstream facing port. Document Number: 001-93912 Rev. *M Page 28 of 36 EZ-PDTM CCG2 Datasheet Packaging Table 28. Package Characteristics Parameter Description Conditions Industrial Min Typ -40 25 -40 - TA Operating ambient temperature TJ Operating junction temperature TJA Package JA (20-ball WLCSP) - - TJC Package JC (20-ball WLCSP) - - TJA Package JA (14-pin DFN) - - TJC Package JC (14-pin DFN) - - TJA Package JA (24-pin QFN) - TJC Package JC (24-pin QFN) - Extended Industrial Industrial Extended Industrial Max Units 85 C 105 C 100 C 125 C 66 - C/W 0.7 - C/W 31 - C/W 59 - C/W - 22 - C/W - 29 - C/W Table 29. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time within 5 C of Peak Temperature 260 C 30 seconds 20-ball WLCSP 14-pin DFN 260 C 30 seconds 24-pin QFN 260 C 30 seconds Table 30. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package 20-ball WLCSP MSL MSL 1 14-pin DFN MSL 3 24-pin QFN MSL 3 Document Number: 001-93912 Rev. *M Page 29 of 36 EZ-PDTM CCG2 Datasheet Figure 17. 20-ball WLCSP (1.63 x 2.03 x 0.55 mm) FN20B Package Outline, 001-95010 001-95010 *B Document Number: 001-93912 Rev. *M Page 30 of 36 EZ-PDTM CCG2 Datasheet Figure 18. 14-pin DFN (2.5 x 3.5 x 0.6 mm), LH14A, 0.95 x 3.00 E-Pad (Sawn) Package Outline, 001-96312 001-96312 ** Figure 19. 24-Pin QFN (4 x 4 x 0.55 mm), LQ24A, 2.65 x 2.65 E-Pad (Sawn) Package Outline, 001-13937 001-13937 *G Document Number: 001-93912 Rev. *M Page 31 of 36 EZ-PDTM CCG2 Datasheet Acronyms Table 31. Acronyms Used in this Document (continued) Table 31. Acronyms Used in this Document Acronym Description ADC analog-to-digital converter API application programming interface ARM(R) advanced RISC machine, a CPU architecture CC configuration channel CCG2 Cable Controller Generation 2 CPU central processing unit CRC cyclic redundancy check, an error-checking protocol CS current sense Acronym Description NVIC nested vectored interrupt controller opamp operational amplifier OCP overcurrent protection OVP overvoltage protection PCB printed circuit board PD power delivery PGA programmable gain amplifier PHY physical layer POR power-on reset PRES (R) precise power-on reset Programmable System-on-ChipTM DFP downstream facing port PSoC DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. PWM pulse-width modulator DRP dual role port RAM random-access memory RISC reduced-instruction-set computing EEPROM electrically erasable programmable read-only memory RMS root-mean-square a USB cable that includes an IC that reports cable characteristics (e.g., current rating) to the Type-C ports RTC real-time clock EMCA RX receive EMI electromagnetic interference SAR successive approximation register ESD electrostatic discharge SCL I2C serial clock FPB flash patch and breakpoint SDA I2C serial data FS full-speed S/H sample and hold GPIO general-purpose input/output SPI Serial Peripheral Interface, a communications protocol IC integrated circuit SRAM static random access memory IDE integrated development environment SWD serial wire debug, a test protocol I2C, or IIC Inter-Integrated Circuit, a communications protocol TX transmit ILO internal low-speed oscillator, see also IMO Type-C IMO internal main oscillator, see also ILO a new standard with a slimmer USB connector and a reversible cable, capable of sourcing up to 100 W of power I/O input/output, see also GPIO UART LVD low-voltage detect Universal Asynchronous Transmitter Receiver, a communications protocol LVTTL low-voltage transistor-transistor logic USB Universal Serial Bus MCU microcontroller unit USBIO USB input/output, CCG2 pins used to connect to a USB port XRES external reset I/O pin NC no connect NMI nonmaskable interrupt Document Number: 001-93912 Rev. *M Page 32 of 36 EZ-PDTM CCG2 Datasheet Document Conventions Table 32. Units of Measure (continued) Symbol Units of Measure Table 32. Units of Measure Symbol Unit of Measure C degrees Celsius Hz hertz KB 1024 bytes kHz kilohertz k kilo ohm Mbps megabits per second MHz megahertz M mega-ohm Msps megasamples per second A microampere F microfarad s microsecond Document Number: 001-93912 Rev. *M Unit of Measure V microvolt W microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second V volt Page 33 of 36 EZ-PDTM CCG2 Datasheet References and Links To Applications Collaterals AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PDTM CCG2 AN95599 - Hardware Design Guidelines for EZ-PDTM CCG2 AN210403 - Hardware Design Guidelines for Dual Role Port Applications Using EZ-PDTM USB Type-C Controllers AN210771 - Getting Started with EZ-PDTM CCG4 Knowledge Base Articles Key Differences Among EZ-PDTM CCG1, CCG2, CCG3 and CCG4 - KBA210740 Programming EZ-PDTM CCG2, EZ-PDTM CCG3 and EZ-PDTM CCG4 Using PSoC(R) Programmer and MiniProg3 - KBA96477 CCGX Frequently Asked Questions (FAQs) - KBA97244 Reference Designs Handling Precautions for CY4501 CCG1 DVK - KBA210560 Cypress EZ-PDTM CCGx Hardware - KBA204102 EZ-PDTM CCG2 Electronically Marked Cable Assembly (EMCA) Paddle Card Reference Design Difference between USB Type-C and USB-PD - KBA204033 EZ-PDTM CCG2 USB Type-C to DisplayPort Cable Solution CCGx Programming Methods - KBA97271 CCG1 USB Type-C to DisplayPort Cable Solution Getting started with Cypress USB Type-C Products KBA04071 CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution Type-C to DisplayPort Cable Electrical Requirements EZ-PDTM CCG2 USB Type-C to HDMI Adapter Solution Dead Battery Charging Implementation in USB Type-C Solutions - KBA97273 CCG1 Electronically Marked Cable Assembly (EMCA) Paddle Card Reference Design Termination Resistors Required for the USB Type-C Connector - KBA97180 CCG1 USB Type-C to Legacy USB Device Cable Paddle Card Reference Schematics VBUS Bypass Capacitor Recommendation for Type-C Cable and Type-C to Legacy Cable/Adapter Assemblies - KBA97270 EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle EZ-PDTM CCG2 USB Type-C Monitor/Dock Solution Need for Regulator and Auxiliary Switch in Type-C to DisplayPort (DP) Cable Solution - KBA97274 CCG2 20W Power Adapter Reference Design Need for a USB Billboard Device in Type-C Solutions - KBA97146 CCG2 18W Power Adapter Reference Design CCG1 Devices in Type-C to Legacy Cable/Adapter Assemblies - KBA97145 EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference Design Kit Cypress USB Type-C Controller Supported Solutions - KBA97179 Termination Resistors for Type-C to Legacy Ports - KBA97272 Handling Instructions for CY4502 CCG2 Development Kit - KBA97916 ThunderboltTM Cable Application Using CCG3 Devices KBA210976 Power Adapter Application Using CCG3 Devices - KBA210975 Methods to Upgrade Firmware on CCG3 Devices - KBA210974 Device Flash Memory Size and Advantages - KBA210973 Applications of EZ-PDTM CCG4 - KBA210739 Application Notes Kits CY4501 CCG1 Development Kit CY4502 EZ-PDTM CCG2 Development Kit CY4531 EZ-PD CCG3 Evaluation Kit CY4541 EZ-PDTM CCG4 Evaluation Kit Datasheets CCG1 Datasheet: USB Type-C Port Controller with Power Delivery CYPD1120 Datasheet: USB Power Delivery Alternate Mode Controller on Type-C CCG3: USB Type-C Controller Datasheet CCG4: Two-Port USB Type-C Controller Datasheet AN96527 - Designing USB Type-C Products Using Cypress's CCG1 Controllers Document Number: 001-93912 Rev. *M Page 34 of 36 EZ-PDTM CCG2 Datasheet Document History Page Description Title: EZ-PDTM CCG2 Datasheet USB Type-C Port Controller Document Number: 001-93912 Orig. of Submission Revision ECN Description of Change Change Date *E 4680071 GAYA 03/07/2015 Release to web *F 4718374 AKN 04/09/2015 AKN Changed datasheet status from Preliminary to Final. Updated Logic Block Diagram. Changed number of GPIOs to 10 and added a note about the number of GPIOs varying depending on the package. 06/15/2015 Updated Power and Digital Peripherals section. Updated Application diagrams. Added SID.PWR#1_A parameter. Added CYPD2122-20FNXIT part in Ordering Information. Removed Errata. VGT Updated Figure 1 and Figure 5. Added VCC_ABS spec and updated the SID.ADC.4 parameter. 10/23/2015 Added "Guaranteed by characterization" note for the following specs: SID.GIO#16, SID.GIO#17, SID.XRES#3, SID 160 to SID 172A, SID 2226, SID 229, SID.ADC.1 to SID.ADC.5. *G *H 4774142 4979175 Added 24-pin QFN pin and package information. Added DRP and DFP Application diagrams *I 5028128 VGT Updated Application Diagrams: Added Figure 14. Added Figure 15. 12/04/2015 Added Figure 16. Updated Ordering Information. Added part numbers CYPD2119-24LQXIT, CYPD2120-24LQXIT, CYPD2121-24LQXIT, CYPD2125-24LQXIT. *J 5186972 VGT Updated temperature ranges in Features. 03/28/2016 Updated Table 28. Updated Ordering Information. *K 5303957 VGT Added Available Firmware and Software Tools. Updated Figure 8: Per the USB PD3.0 spec, SOP" implementation is no longer valid for passive cables. Updated Figure 11, Figure 12, and Figure 13. 06/13/2016 Added descriptive notes for the application diagrams. Added References and Links To Applications Collaterals. Updated Ordering Information. Updated Cypress logo and copyright information. *L 5387677 VGT 08/02/2016 Added CYPD2122-24LQXI part number in Ordering Information. VGT Added Figure 8 and Figure 10. Updated the title of Figure 7 and Figure 9. Added "Note: Application diagram in Figure 8 requires external diodes to operate in the extended VCONN voltage range of 2.7V to 5.5V" in Application 07/11/2018 Diagrams. Updated Figure 17 (Spec 001-95010 from *A to *B). Updated Figure 19 (Spec 001-13937 from *F to *G). Added compliance to USB Specification. Updated Cypress Logo and Copyright year. *M 6097993 Document Number: 001-93912 Rev. *M Page 35 of 36 EZ-PDTM CCG2 Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R)Solutions Products Arm(R) Cortex(R) Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB Type-CTM Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). 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Document Number: 001-93912 Rev. *M Revised July 11, 2018 Page 36 of 36