XCV812E-6BG560C - Xilinx - Datasheet.Directory

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DS025-1 (v1.5) July 17, 2002 www.xilinx.com Module 1 of 4

Production Product Specification 1-800-255-7778 1

Features

• Fast, Extended Block RAM, 1.8 V FPGA Family

- 560 Kb and 1,120 Kb embedded block RAM

- 130 MHz internal performance (four LUT levels)

- PCI compliant 3.3 V, 32/64-bit, 33/66-MHz

• Sophisticated SelectRAM+™ Memory Hierarchy

- 294 Kb of internal configurable distributed RAM

- Up to 1,120 Kb of synchronous internal block RAM

- True Dual-Port block RAM

- Memory bandwidth up to 2.24 Tb/s (equivalent

bandwidth of over 100 RAMBUS channels)

- Designed for high-performance Interfaces to

external memories

·200 MHz ZBT* SRAMs

·200 Mb/s DDR SDRAMs

•Highly Flexible SelectIO+™ Technology

- Supports 20 high-performance interface standards

- Up to 556 singled-ended I/Os or up to 201

differential I/O pairs for an aggregate bandwidth of

>100 Gb/s

•Complete Industry-Standard Differential Signalling

Support

- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL

- Al I/O signals can be input, output, or bi-directional

- LVPECL and LVDS clock inputs for 300+ MHz

clocks

•Proprietary High-Performance SelectLink™

Technology

- 80 Gb/s chip-to-chip communication link

- Support for Double Data Rate (DDR) interface

- Web-based HDL generation methodology

•Eight Fully Digital Delay-Locked Loops (DLLs)

•IEEE 1149.1 boundary-scan logic

•Supported by Xilinx Foundation Series™ and Alliance

Series™ Development Systems

- Internet Team Design (Xilinx iTD™) tool ideal for

million-plus gate density designs

- Wide selection of PC or workstation platforms

•SRAM-based In-System Configuration

- Unlimited re-programmability

•Advanced Packaging Options

- 1.0 mm FG676 and FG900

- 1.27 mm BG560

•0.18 µm 6-layer Metal Process with Copper

Interconnect

•100% Factory Tested

* ZBT is a trademark of Integrated Device Technology, Inc.

Introduction

The Virtex™-E Extended Memory (Virtex-EM) family of

FPGAs is an extension of the highly successful Virtex-E

family architecture. The Virtex-EM family (devices shown in

Table 1) includes all of the features of Virtex-E, plus addi-

tional block RAM, useful for applications such as network

switches and high-performance video graphic systems.

Xilinx developed the Virtex-EM product family to enable

customers to design systems requiring high memory band-

width, such as 160 Gb/s network switches. Unlike traditional

ASIC devices, this family also supports fast time-to-market

delivery, because the development engineering is already

completed. Just complete the design and program the

device. There is no NRE, no silicon production cycles, and no

additional delays for design re-work. In addition, designers

can update the design over a network at any time, providing

product upgrades or updates to customers even sooner.

The Virtex-EM family is the result of more than fifteen years

of FPGA design experience. Xilinx has a history of support-

ing customer applications by providing the highest level of

logic, RAM, and features available in the industry. The Vir-

tex-EM family, first FPGAs to deploy copper interconnect,

offers the performance and high memory bandwidth for

advanced system integration without the initial investment,

long development cycles, and inventory risk expected in tra-

ditional ASIC development.

Virtex™-E 1.8 V Extended Memory

Field Programmable Gate Arrays

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Virtex-E Compared to Virtex Devices

The Virtex-E family offers up to 43,200 logic cells in devices

up to 30% faster than the Virtex family.

I/O performance is increased to 622 Mb/s using Source

Synchronous data transmission architectures and synchro-

nous system performance up to 240 MHz using sin-

gled-ended SelectI/O technology. Additional I/O standards

are supported, notably LVPECL, LVDS, and BLVDS, which

use two pins per signal. Almost all signal pins can be used

for these new standards.

Virtex-E devices have up to 640 Kb of faster (250MHz)

block SelectRAM, but the individual RAMs are the same

size and structure as in the Virtex family. They also have

eight DLLs instead of the four in Virtex devices. Each indi-

vidual DLL is slightly improved with easier clock mirroring

and 4x frequency multiplication.

VCCINT

, the supply voltage for the internal logic and mem-

ory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced

processing and 0.18 µm design rules have resulted in

smaller dice, faster speed, and lower power consumption.

I/O pins are 3 V tolerant, and can be 5 V tolerant with an

external 100 Ω resistor. PCI 5 V is not supported. With the

addition of appropriate external resistors, any pin can toler-

ate any voltage desired.

Banking rules are different. With Virtex devices, all input

buffers are powered by VCCINT

. With Virtex-E devices, the

LVTTL, LVCMOS2, and PCI input buffers are powered by

the I/O supply voltage VCCO.

The Virtex-E family is not bitstream-compatible with the Vir-

tex family, but Virtex designs can be compiled into equiva-

lent Virtex-E devices.

The same device in the same package for the Virtex-E and

Virtex families are pin-compatible with some minor excep-

tions. See the data sheet pinout section for details.

General Description

The Virtex-E FPGA family delivers high-performance,

high-capacity programmable logic solutions. Dramatic

increases in silicon efficiency result from optimizing the new

architecture for place-and-route efficiency and exploiting an

aggressive 6-layer metal 0.18 µm CMOS process. These

advances make Virtex-E FPGAs powerful and flexible alter-

natives to mask-programmed gate arrays. The Virtex-E fam-

ily includes the nine members in Ta bl e 1 .

Building on experience gained from Virtex FPGAs, the Vir-

tex-E family is an evolutionary step forward in programma-

ble logic design. Combining a wide variety of programmable

system features, a rich hierarchy of fast, flexible intercon-

nect resources, and advanced process technology, the Vir-

tex-E family delivers a high-speed and high-capacity

programmable logic solution that enhances design flexibility

while reducing time-to-market.

Virtex-E Architecture

Virtex-E devices feature a flexible, regular architecture that

comprises an array of configurable logic blocks (CLBs) sur-

rounded by programmable input/output blocks (IOBs), all

interconnected by a rich hierarchy of fast, versatile routing

resources. The abundance of routing resources permits the

Virtex-E family to accommodate even the largest and most

complex designs.

Virtex-E FPGAs are SRAM-based, and are customized by

loading configuration data into internal memory cells. Con-

figuration data can be read from an external SPROM (mas-

ter serial mode), or can be written into the FPGA

(SelectMAP™, slave serial, and JTAG modes).

The standard Xilinx Foundation Series™ and Alliance

Series™ Development systems deliver complete design

support for Virtex-E, covering every aspect from behavioral

and schematic entry, through simulation, automatic design

translation and implementation, to the creation and down-

loading of a configuration bit stream.

Higher Performance

Virtex-E devices provide better performance than previous

generations of FPGAs. Designs can achieve synchronous

system clock rates up to 240 MHz including I/O or 622 Mb/s

using Source Synchronous data transmission architech-

tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-

tions, and interfaces can be implemented that operate at

33 MHz or 66 MHz.

While performance is design-dependent, many designs

operate internally at speeds in excess of 133 MHz and can

achieve over 311 MHz. Table 2, page 3, shows perfor-

mance data for representative circuits, using worst-case

timing parameters.

Table 1: Virtex-E Extended Memory Field-Programmable Gate Array Family Members

Device Logic Gates CLB Array

Logic

Cells

Differential

I/O Pairs User I/O

BlockRAM

Bits

Distributed

RAM Bits

XCV405E 129,600 40 x 60 10,800 183 404 573,440 153,600

XCV812E 254,016 56 x 84 21,168 201 556 1,146,880 301,056

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-1 (v1.5) July 17, 2002 www.xilinx.com Module 1 of 4

Production Product Specification 1-800-255-7778 3

Virtex-E Extended Memory Device/Package Combinations and Maximum I/O

Virtex-E Extended Memory Ordering Information

Table 2: Performance for Common Circuit Functions

Function Bits Virtex-E -7

Adder 16

4.3 ns

6.3 ns

Pipelined Multiplier 8 x 8

16 x 16

4.4 ns

5.1 ns

Address Decoder 16

3.8 ns

5.5 ns

16:1 Multiplexer 4.6 ns

Parity Tree

3.5 ns

4.3 ns

5.9 ns

Chip-to-Chip

HSTL Class IV

LVTTL,16mA, fast slew

LV D S

LVPECL

Table 3: Virtex-EM Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)

Package XCV405E XCV812E

BG560 404 404

FG676 404

FG900 556

Figure 1: Virtex Ordering Information

Example: XCV405E-6BG560C

Device Type Temperature Range

C = Commercial (TJ = 0˚C to +85˚C)

I = Industrial (TJ = −40˚C to +100˚C)

Number of Pins

Package Type

BG = Ball Grid Array

FG = Fine Pitch Ball Grid Array

Speed Grade

(-6, -7, -8)

DS025_001_112000

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays R

Module 1 of 4 www.xilinx.com DS025-1 (v1.5) July 17, 2002

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Revision History

The following table shows the revision history for this document.

Virtex-E Extended Memory Data Sheet

The Virtex-E Extended Memory Data Sheet contains the following modules:

•DS025-1, Virtex-E 1.8V Extended Memory FPGAs:

Introduction and Ordering Information (Module 1)

•DS025-2, Virtex-E 1.8V Extended Memory FPGAs:

Functional Description (Module 2)

•DS025-3, Virtex-E 1.8V Extended Memory FPGAs:

DC and Switching Characteristics (Module 3)

•DS025-4, Virtex-E 1.8V Extended Memory FPGAs:

Pinout Tables (Module 4)

Date Version Revision

03/23/00 1.0 Initial Xilinx release.

08/01/00 1.1 Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.

Reformatted to adhere to corporate documentation style guidelines. Minor changes in

BG560 pin-out table.

09/19/00 1.2 •In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no

longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.

•Min values added to Virtex-E Electrical Characteristics tables.

11/20/00 1.3 •Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables

(Module 3).

•Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).

•Added to note 2 of Absolute Maximum Ratings (Module 3).

•Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL

Standard, with DLL (Module 3).

•Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).

04/02/01 1.4 •In Ta b le 4 , FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF,

and pin G16 is now labeled as VREF.

•Updated values in Virtex-E Switching Characteristics tables.

•Converted data sheet to modularized format. See Virtex-E Extended Memory Data

Sheet, below.

07/17/02 1.5 •Data sheet designation upgraded from Preliminary to Production.

DS025-2 (v2.3) November 19, 2002 www.xilinx.com Module 2 of 4

1-800-255-7778 1

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Architectural Description

Virtex-E Array

The Virtex-E user-programmable gate array (see Figure 1)

comprises two major configurable elements: configurable

logic blocks (CLBs) and input/output blocks (IOBs).

• CLBs provide the functional elements for constructing

logic.

• IOBs provide the interface between the package pins

and the CLBs.

CLBs interconnect through a general routing matrix (GRM).

The GRM comprises an array of routing switches located at

the intersections of horizontal and vertical routing channels.

Each CLB nests into a VersaBlock™ that also provides local

routing resources to connect the CLB to the GRM.

The VersaRing™ I/O interface provides additional routing

resources around the periphery of the device. This routing

improves I/O routability and facilitates pin locking.

The Virtex-E architecture also includes the following circuits

that connect to the GRM:

• Dedicated block memories of 4096 bits each

• Clock DLLs for clock-distribution delay compensation

and clock domain control

• 3-State buffers (BUFTs) associated with each CLB that

drive dedicated segmentable horizontal routing resources

Values stored in static memory cells control the configurable

logic elements and interconnect resources. These values

load into the memory cells on power-up, and can reload if

necessary to change the function of the device.

Input/Output Block

The Virtex-E IOB, Figure 2, features SelectIO+™ inputs and

outputs that support a wide variety of I/O signalling stan-

dards (see Table 1).

The three IOB storage elements function either as

edge-triggered D-type flip-flops or as level-sensitive latches.

Each IOB has a clock signal (CLK) shared by the three

flip-flops and independent clock enable signals for each

flip-flop.

Virtex™-E 1.8 V Extended Memory

Field Programmable Gate Arrays

DS025-2 (v2.3) November 19, 2002 00Production Product Specification

Figure 1: Virtex-E Architecture Overview

DLLDLL

IOBs

VersaRing

ds022_001_121099

CLBs

BRAMs

CLBs

BRAMs

CLBs

DLLDLL

Figure 2: Virtex-E Input/Output Block (IOB)

OBUFT

IBUF

Vref

ds022_02_091300

CLK

ICE

OCE

TCE

PAD

Programmable

Delay

Weak

Keeper

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In addition to the CLK and CE control signals, the three

flip-flops share a Set/Reset (SR). For each flip-flop, this sig-

nal can be independently configured as a synchronous Set,

a synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear.

The output buffer and all of the IOB control signals have

independent polarity controls.

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. After

configuration, clamping diodes are connected to VCCO with

the exception of LVCMOS18, LVCMOS25, GTL, GTL+,

LVDS, and LVPECL.

Optional pull-up, pull-down and weak-keeper circuits are

attached to each pad. Prior to configuration all outputs not

involved in configuration are forced into their high-imped-

ance state. The pull-down resistors and the weak-keeper

circuits are inactive, but IOs can optionally be pulled up.

The activation of pull-up resistors prior to configuration is

controlled on a global basis by the configuration mode pins.

If the pull-up resistors are not activated, all the pins are in a

high-impedance state. Consequently, external pull-up or

pull-down resistors must be provided on pins required to be

at a well-defined logic level prior to configuration.

All Virtex-E IOBs support IEEE 1149.1-compatible bound-

ary scan testing.

Input Path

The Virtex-E IOB input path routes the input signal directly

to internal logic and/ or through an optional input flip-flop.

An optional delay element at the D-input of this flip-flop elim-

inates pad-to-pad hold time. The delay is matched to the

internal clock-distribution delay of the FPGA, and when

used, assures that the pad-to-pad hold time is zero.

Each input buffer can be configured to conform to any of the

low-voltage signalling standards supported. In some of

these standards the input buffer utilizes a user-supplied

threshold voltage, VREF

. The need to supply VREF imposes

constraints on which standards can be used in close prox-

imity to each other. See "I/O Banking" on page 2.

There are optional pull-up and pull-down resistors at each

user I/O input for use after configuration. Their value is in

the range 50 - 100 kΩ.

Output Path

The output path includes a 3-state output buffer that drives

the output signal onto the pad. The output signal can be

routed to the buffer directly from the internal logic or through

an optional IOB output flip-flop.

The 3-state control of the output can also be routed directly

from the internal logic or through a flip-flip that provides syn-

chronous enable and disable.

Each output driver can be individually programmed for a

wide range of low-voltage signalling standards. Each output

buffer can source up to 24 mA and sink up to 48 mA. Drive

strength and slew rate controls minimize bus transients.

In most signalling standards, the output High voltage

depends on an externally supplied VCCO voltage. The need

to supply VCCO imposes constraints on which standards

can be used in close proximity to each other. See "I/O Bank-

ing" on page 2.

An optional weak-keeper circuit is connected to each out-

put. When selected, the circuit monitors the voltage on the

pad and weakly drives the pin High or Low to match the

input signal. If the pin is connected to a multiple-source sig-

nal, the weak keeper holds the signal in its last state if all

drivers are disabled. Maintaining a valid logic level in this

way eliminates bus chatter.

Since the weak-keeper circuit uses the IOB input buffer to

monitor the input level, an appropriate VREF voltage must be

provided if the signalling standard requires one. The provi-

sion of this voltage must comply with the I/O banking rules.

I/O Banking

Some of the I/O standards described above require VCCO

and/or VREF voltages. These voltages are externally sup-

plied and connected to device pins that serve groups of

Table 1: Supported I/O Standards

I/O

Standard

Output

VCCO

Input

VCCO

Input

VREF

Board

Termination

Vol tage

(VTT)

LVTTL 3.3 3.3 N/A N/A

LVCMOS2 2.5 2.5 N/A N/A

LVCMOS18 1.8 1.8 N/A N/A

SSTL3 I & II 3.3 N/A 1.50 1.50

SSTL2 I & II 2.5 N/A 1.25 1.25

GTL N/A N/A 0.80 1.20

GTL+ N/A N/A 1.0 1.50

HSTL I 1.5 N/A 0.75 0.75

HSTL III & IV 1.5 N/A 0.90 1.50

CTT 3.3 N/A 1.50 1.50

AGP-2X 3.3 N/A 1.32 N/A

PCI33_3 3.3 3.3 N/A N/A

PCI66_3 3.3 3.3 N/A N/A

BLVDS & LVDS 2.5 N/A N/A N/A

LVPECL 3.3 N/A N/A N/A

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IOBs, called banks. Consequently, restrictions exist about

which I/O standards can be combined within a given bank.

Eight I/O banks result from separating each edge of the

FPGA into two banks, as shown in Figure 3. Each bank has

multiple VCCO pins, all of which must be connected to the

same voltage. This voltage is determined by the output

standards in use.

Within a bank, output standards can be mixed only if they

use the same VCCO. Compatible standards are shown in

Table 2. GTL and GTL+ appear under all voltages because

their open-drain outputs do not depend on VCCO.

Some input standards require a user-supplied threshold

voltage, VREF

. In this case, certain user-I/O pins are auto-

matically configured as inputs for the VREF voltage. Approx-

imately one in six of the I/O pins in the bank assume this

role.

The VREF pins within a bank are interconnected internally

and consequently only one VREF voltage can be used within

each bank. All VREF pins in the bank, however, must be con-

nected to the external voltage source for correct operation.

Within a bank, inputs that require VREF can be mixed with

those that do not. However, only one VREF voltage can be

used within a bank.

In Virtex-E, input buffers with LVTTL, LVCMOS2,

LVCMOS18, PCI33_3, PCI66_3 standards are supplied by

VCCO rather than VCCINT

. For these standards, only input

and output buffers that have the same VCCO can be mixed

together.

The VCCO and VREF pins for each bank appear in the device

pin-out tables and diagrams. The diagrams also show the

bank affiliation of each I/O.

Within a given package, the number of VREF and VCCO pins

can vary depending on the size of device. In larger devices,

more I/O pins convert to VREF pins. Since these are always

a super set of the VREF pins used for smaller devices, it is

possible to design a PCB that permits migration to a larger

device if necessary. All the VREF pins for the largest device

anticipated must be connected to the VREF voltage, and not

used for I/O.

In smaller devices, some VCCO pins used in larger devices

do not connect within the package. These unconnected pins

can be left unconnected externally, or they can be con-

nected to the VCCO voltage to permit migration to a larger

device, if necessary.

Configurable Logic Block

The basic building block of the Virtex-E CLB is the logic cell

(LC). An LC includes a 4-input function generator, carry

logic, and a storage element. The output from the function

generator in each LC drives both the CLB output and the D

input of the flip-flop. Each Virtex-E CLB contains four LCs,

organized in two similar slices, as shown in Figure 4.

Figure 5 shows a more detailed view of a single slice.

Figure 3: Virtex-E I/O Banks

Table 2: Compatible Output Standards

VCCO Compatible Standards

3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,

GTL+, LVPECL

2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,

BLVDS, LVDS

1.8 V LVCMOS18, GTL, GTL+

1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+

ds022_03_121799

Bank 0

GCLK3 GCLK2

GCLK1 GCLK0

Bank 1

Bank 5 Bank 4

VirtexE

Device

Bank 7Bank 6

Bank 2Bank 3

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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In addition to the four basic LCs, the Virtex-E CLB contains

logic that combines function generators to provide functions

of five or six inputs. Consequently, when estimating the

number of system gates provided by a given device, each

CLB counts as 4.5 LCs.

Look-Up Tables

Virtex-E function generators are implemented as 4-input

look-up tables (LUTs). In addition to operating as a function

generator, each LUT can provide a 16 x 1-bit synchronous

RAM. Furthermore, the two LUTs within a slice can be com-

Figure 4: 2-Slice Virtex-E CLB

Carry &

Control

Carry &

Control

Carry &

Control

Carry &

Control

LUT

CINCIN

COUT COUT

YBYB

Slice 1 Slice 0

LUT

LUT D

ds022_04_121799

Figure 5: Detailed View of Virtex-E Slice

F5IN

CLK

CIN

F5 F5

ds022_05_092000

COUT

CK WSO

WSH

BY DG

BX DI

LUT

INIT

REV

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1-800-255-7778 5

bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,

or a 16 x 1-bit dual-port synchronous RAM.

The Virtex-E LUT can also provide a 16-bit shift register that

is ideal for capturing high-speed or burst-mode data. This

mode can also be used to store data in applications such as

Digital Signal Processing.

Storage Elements

The storage elements in the Virtex-E slice can be config-

ured either as edge-triggered D-type flip-flops or as

level-sensitive latches. The D inputs can be driven either by

the function generators within the slice or directly from slice

inputs, bypassing the function generators.

In addition to Clock and Clock Enable signals, each Slice

has synchronous set and reset signals (SR and BY). SR

forces a storage element into the initialization state speci-

fied for it in the configuration. BY forces it into the opposite

state. Alternatively, these signals can be configured to oper-

ate asynchronously. All of the control signals are indepen-

dently invertible, and are shared by the two flip-flops within

the slice.

Additional Logic

The F5 multiplexer in each slice combines the function gen-

erator outputs. This combination provides either a function

generator that can implement any 5-input function, a 4:1

multiplexer, or selected functions of up to nine inputs.

Similarly, the F6 multiplexer combines the outputs of all four

function generators in the CLB by selecting one of the

F5-multiplexer outputs. This permits the implementation of

any 6-input function, an 8:1 multiplexer, or selected func-

tions of up to 19 inputs.

Each CLB has four direct feedthrough paths, two per slice.

These paths provide extra data input lines or additional local

routing that does not consume logic resources.

Arithmetic Logic

Dedicated carry logic provides fast arithmetic carry capabil-

ity for high-speed arithmetic functions. The Virtex-E CLB

supports two separate carry chains, one per Slice. The

height of the carry chains is two bits per CLB.

The arithmetic logic includes an XOR gate that allows a

2-bit full adder to be implemented within a slice. In addition,

a dedicated AND gate improves the efficiency of multiplier

implementation.

The dedicated carry path can also be used to cascade func-

tion generators for implementing wide logic functions.

BUFTs

Each Virtex-E CLB contains two 3-state drivers (BUFTs)

that can drive on-chip busses. See "Dedicated Routing" on

page 7. Each Virtex-E BUFT has an independent 3-state

control pin and an independent input pin.

Block SelectRAM+ Memory

Virtex-E FPGAs incorporate large block SelectRAM memo-

ries. These complement the Distributed SelectRAM memo-

ries that provide shallow RAM structures implemented in

CLBs.

Block SelectRAM memory blocks are organized in columns,

starting at the left (column 0) and right outside edges and

inserted every four CLB columns (see notes for smaller

devices). Each memory block is four CLBs high, and each

memory column extends the full height of the chip, immedi-

ately adjacent (to the right, except for column 0) of the CLB

column locations indicated in Table 3.

Table 4 shows the amount of block SelectRAM memory that

is available in each Virtex-E device.

Each block SelectRAM cell, as illustrated in Figure 6, is a

fully synchronous dual-ported (True Dual Port) 4096-bit

RAM with independent control signals for each port. The

data widths of the two ports can be configured indepen-

dently, providing built-in bus-width conversion.

Table 3: CLB/Block RAM Column Locations

Virtex-E Device 04812162024283236404448525660646872768084

XCV405E √√√√√√√ √√√√√√√

XCV812E √√√√√√√√√√ √√√√√√√√√√

Table 4: Virtex-E Block SelectRAM Amounts

Virtex-E Device # of Blocks Block SelectRAM Bits

XCV405E 140 573,440

XCV812E 280 1,146,880

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 2 of 4 www.xilinx.com DS025-2 (v2.3) November 19, 2002

6 1-800-255-7778

Table 5 shows the depth and width aspect ratios for the

block SelectRAM. The Virtex-E block SelectRAM also

includes dedicated routing to provide an efficient interface

with both CLBs and other block SelectRAM modules. Refer

to XAPP130 for block SelectRAM timing waveforms.

Programmable Routing Matrix

It is the longest delay path that limits the speed of any

worst-case design. Consequently, the Virtex-E routing

architecture and its place-and-route software were defined

in a joint optimization process. This joint optimization mini-

mizes long-path delays, and consequently, yields the best

system performance.

The joint optimization also reduces design compilation

times because the architecture is software-friendly. Design

cycles are correspondingly reduced due to shorter design

iteration times.

Local Routing

The VersaBlock, shown in Figure 7, provides local routing

resources with the following types of connections:

•Interconnections among the LUTs, flip-flops, and GRM

•Internal CLB feedback paths that provide high-speed

connections to LUTs within the same CLB, chaining

them together with minimal routing delay

•Direct paths that provide high-speed connections

between horizontally adjacent CLBs, eliminating the

delay of the GRM

General Purpose Routing

Most Virtex-E signals are routed on the general purpose

routing, and consequently, the majority of interconnect

resources are associated with this level of the routing hier-

archy. The general routing resources are located in horizon-

tal and vertical routing channels associated with the CLB

rows and columns. The general-purpose routing resources

are listed below.

•Adjacent to each CLB is a General Routing Matrix

(GRM). The GRM is the switch matrix through which

horizontal and vertical routing resources connect, and

is also the means by which the CLB gains access to

the general purpose routing.

•24 single-length lines route GRM signals to adjacent

GRMs in each of the four directions.

•72 buffered Hex lines route GRM signals to another

GRMs six-blocks away in each one of the four

directions. Organized in a staggered pattern, Hex lines

are driven only at their endpoints. Hex-line signals can

be accessed either at the endpoints or at the midpoint

(three blocks from the source). One third of the Hex

lines are bidirectional, while the remaining ones are

uni-directional.

•12 Longlines are buffered, bidirectional wires that

distribute signals across the device quickly and

efficiently. Vertical Longlines span the full height of the

device, and horizontal ones span the full width of the

device.

I/O Routing

Virtex-E devices have additional routing resources around

their periphery that form an interface between the CLB array

and the IOBs. This additional routing, called the VersaRing,

facilitates pin-swapping and pin-locking, such that logic

redesigns can adapt to existing PCB layouts. Time-to-mar-

ket is reduced, since PCBs and other system components

can be manufactured while the logic design is still in

progress.

Figure 6: Dual-Port Block SelectRAM

Table 5: Block SelectRAM Port Aspect Ratios

Width Depth ADDR Bus Data Bus

1 4096 ADDR<11:0> DATA<0>

2 2048 ADDR<10:0> DATA<1:0>

4 1024 ADDR<9:0> DATA<3:0>

8 512 ADDR<8:0> DATA<7:0>

16 256 ADDR<7:0> DATA<15:0>

WEB

ENB

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

WEA

ENA

RSTA

CLKA

ADDRA[#:0]

DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

ds022_06_121699

Figure 7: Virtex-E Local Routing

XCVE_ds_007

CLB

GRM

Adjacent

GRM

To Adjacent

GRM

Direct

Connection

To Adjacent

CLB

To Adjacent

GRM

To Adjacent

GRM

Direct Connection

To Adjacent

CLB

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Dedicated Routing

Some signal classes require dedicated routing resources to

maximize performance. In the Virtex-E architecture, dedi-

cated routing resources are provided for two signal classes.

•Horizontal routing resources are provided for on-chip

3-state busses. Four partitionable bus lines are

provided per CLB row, permitting multiple busses

within a row, as shown in Figure 8.

•Two dedicated nets per CLB propagate carry signals

vertically to the adjacent CLB. Global Clock Distribution

Network.

•DLL Location

Clock Routing

Clock Routing resources distribute clocks and other signals

with very high fanout throughout the device. Virtex-E

devices include two tiers of clock routing resources referred

to as global and local clock routing resources.

•The global routing resources are four dedicated global

nets with dedicated input pins that are designed to

distribute high-fanout clock signals with minimal skew.

Each global clock net can drive all CLB, IOB, and block

RAM clock pins. The global nets can be driven only by

global buffers. There are four global buffers, one for

each global net.

•The local clock routing resources consist of 24

backbone lines, 12 across the top of the chip and 12

across bottom. From these lines, up to 12 unique

signals per column can be distributed via the 12

longlines in the column. These local resources are

more flexible than the global resources since they are

not restricted to routing only to clock pins.

Global Clock Distribution

Virtex-E provides high-speed, low-skew clock distribution

through the global routing resources described above. A

typical clock distribution net is shown in Figure 9.

Four global buffers are provided, two at the top center of the

device and two at the bottom center. These drive the four

global nets that in turn drive any clock pin.

Four dedicated clock pads are provided, one adjacent to

each of the global buffers. The input to the global buffer is

selected either from these pads or from signals in the gen-

eral purpose routing.

Digital Delay-Locked Loops

There are eight DLLs (Delay-Locked Loops) per device,

with four located at the top and four at the bottom,

Figure 10. The DLLs can be used to eliminate skew

between the clock input pad and the internal clock input pins

throughout the device. Each DLL can drive two global clock

networks.The DLL monitors the input clock and the distrib-

uted clock, and automatically adjusts a clock delay element.

Additional delay is introduced such that clock edges arrive

at internal flip-flops synchronized with clock edges arriving

at the input.

In addition to eliminating clock-distribution delay, the DLL

provides advanced control of multiple clock domains. The

Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes

CLB CLB CLB CLB

buft_c.eps

Tri-State

Lines

Figure 9: Global Clock Distribution Network

Global Clock Spine

Global Clock Column

GCLKPAD2

GCLKBUF2

GCLKPAD3

GCLKBUF3

GCLKBUF1

GCLKPAD1

GCLKBUF0

GCLKPAD0

Global Clock Rows

XCVE_009

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DLL provides four quadrature phases of the source clock,

and can double the clock or divide the clock by 1.5, 2, 2.5, 3,

4, 5, 8, or 16.

The DLL also operates as a clock mirror. By driving the output

from a DLL off-chip and then back on again, the DLL can be

used to de-skew a board level clock among multiple devices.

In order to guarantee that the system clock is operating cor-

rectly prior to the FPGA starting up after configuration, the

DLL can delay the completion of the configuration process

until after it has achieved lock.

For more information about DLL functionality, see the

Design Consideration section of the data sheet.

Boundary Scan

Virtex-E devices support all the mandatory boundary-scan

instructions specified in the IEEE standard 1149.1. A Test

Access Port (TAP) and registers are provided that imple-

ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,

IDCODE, USERCODE, and HIGHZ instructions. The TAP

also supports two internal scan chains and configura-

tion/readback of the device.

The JTAG input pins (TDI, TMS, TCK) do not have a VCCO

requirement, and operate with either 2.5 V or 3.3 V input

signalling levels. The output pin (TDO) is sourced from the

VCCO in bank 2, and for proper operation of LVTTL 3.3 V

levels, the bank should be supplied with 3.3 V.

Boundary-scan operation is independent of individual IOB

configurations, and unaffected by package type. All IOBs,

including un-bonded ones, are treated as independent

3-state bidirectional pins in a single scan chain. Retention of

the bidirectional test capability after configuration facilitates

the testing of external interconnections, provided the user

design or application is turned off.

Ta ble 6 lists the boundary-scan instructions supported in

Virtex-E FPGAs. Internal signals can be captured during

EXTEST by connecting them to un-bonded or unused IOBs.

They can also be connected to the unused outputs of IOBs

defined as unidirectional input pins.

Before the device is configured, all instructions except

USER1 and USER2 are available. After configuration, all

instructions are available. During configuration, it is recom-

mended that those operations using the boundary-scan

performed.

In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to configure the

FPGA, and also to read back the configuration data.

Figure 10: DLL Locations

XCVE_0010

DLLDLL

Primary DLLs

Secondary DLLs

DLLDLL

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Figure 11 is a diagram of the Virtex-E Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE

1149.1 Test Access Port controller, and the Instruction Register with decodes.

Figure 11: Virtex-E Family Boundary Scan Logic

D Q

IOB

BYPASS

IOB IOB

TDO

TDI

IOB IOB IOB

D Q

IOB

D Q

0DQ

IOB.T

DATA IN

IOB.I

IOB.Q

IOB.T

IOB.I

SHIFT/

CAPTURE

CLOCK DATA

DATAOUT UPDATE EXTEST

X9016

INSTRUCTION REGISTER

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Instruction Set

The Virtex-E Series boundary scan instruction set also

includes instructions to configure the device and read back

configuration data (CFG_IN, CFG_OUT, and JSTART). The

complete instruction set is coded as shown in Ta b l e 6 .

Data Registers

The primary data register is the boundary scan register. For

each IOB pin in the FPGA, bonded or not, it includes three

bits for In, Out, and 3-State Control. Non-IOB pins have

appropriate partial bit population if input-only or output-only.

Each EXTEST CAPTURED-OR state captures all In, Out,

and 3-state pins.

The other standard data register is the single flip-flop

BYPASS register. It synchronizes data being passed

through the FPGA to the next downstream boundary scan

device.

The FPGA supports up to two additional internal scan

chains that can be specified using the BSCAN macro. The

macro provides two user pins (SEL1 and SEL2) which are

decodes of the USER1 and USER2 instructions respec-

tively. For these instructions, two corresponding pins (T

DO1 and TDO2) allow user scan data to be shifted out of

TDO.

Likewise, there are individual clock pins (DRCK1 and

DRCK2) for each user register. There is a common input pin

(TDI) and shared output pins that represent the state of the

TAP controller (RESET, SHIFT, and UPDATE).

Bit Sequence

The order within each IOB is: In, Out, 3-State. The

input-only pins contribute only the In bit to the boundary

scan I/O data register, while the output-only pins contributes

all three bits.

From a cavity-up view of the chip (as shown in EPIC), start-

ing in the upper right chip corner, the boundary scan

data-register bits are ordered as shown in Figure 12.

BSDL (Boundary Scan Description Language) files for Vir-

tex-E Series devices are available on the Xilinx web site in

the File Download area.

Table 6: Boundary Scan Instructions

Boundary-Scan

Command

Binary

Code (4:0) Description

EXTEST 00000 Enable boundary-scan

EXTEST operation.

SAMPLE/

PRELOAD

00001 Enable boundary-scan

SAMPLE/PRELOAD

operation.

USER1 00010 Access user-defined

USER2 00011 Access user-defined

CFG_OUT 00100 Access the

configuration bus for

read operations.

CFG_IN 00101 Access the

configuration bus for

write operations.

INTEST 00111 Enable boundary-scan

INTEST operation.

USERCODE 01000 Enable shifting out

USER code.

IDCODE 01001 Enable shifting out of ID

Code.

HIGHZ 01010 3-state output pins while

enabling the Bypass

JSTART 01100 Clock the start-up

sequence when

StartupClk is TCK.

BYPASS 11111 Enable BYPASS.

RESERVED All other

codes

Xilinx reserved

instructions.

Figure 12: Boundary Scan Bit Sequence

Bit 0 ( TDO end)

Bit 1

Bit 2

Right half of top-edge IOBs (Right to Left)

GCLK2

GCLK3

Left half of top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom)

Left half of bottom-edge IOBs (Left to Right)

GCLK1

GCLK0

Right half of bottom-edge IOBs (Left to Right)

DONE

PROG

Right-edge IOBs (Bottom to Top)

CCLK

(TDI end)

990602001

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Identification Registers

The IDCODE register is supported. By using the IDCODE,

the device connected to the JTAG port can be determined.

The IDCODE register has the following binary format:

vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1

where

v = the die version number

f = the family code (05 for Virtex-E family)

a = the number of CLB rows (ranges from 16 for

XCV50E to 104 for XCV3200E)

c = the company code (49h for Xilinx)

The USERCODE register is supported. By using the USER-

CODE, a user-programmable identification code can be

loaded and shifted out for examination. The identification

code (see Table 7) is embedded in the bitstream during bit-

stream generation and is valid only after configuration.

Note:

Attempting to load an incorrect bitstream causes

configuration to fail and can damage the device.

Including Boundary Scan in a Design

Since the boundary scan pins are dedicated, no special ele-

ment needs to be added to the design unless an internal

data register (USER1 or USER2) is desired.

If an internal data register is used, insert the boundary scan

symbol and connect the necessary pins as appropriate.

Development System

Virtex-E FPGAs are supported by the Xilinx Foundation and

Alliance Series CAE tools. The basic methodology for Vir-

tex-E design consists of three interrelated steps: design

entry, implementation, and verification. Industry-standard

tools are used for design entry and simulation (for example,

Synopsys FPGA Express), while Xilinx provides proprietary

architecture-specific tools for implementation.

The Xilinx development system is integrated under the Xil-

inx Design Manager (XDM™) software, providing designers

with a common user interface regardless of their choice of

entry and verification tools. The XDM software simplifies the

selection of implementation options with pull-down menus

and on-line help.

Application programs ranging from schematic capture to

Placement and Routing (PAR) can be accessed through the

XDM software. The program command sequence is gener-

ated prior to execution, and stored for documentation.

Several advanced software features facilitate Virtex-E design.

RPMs, for example, are schematic-based macros with relative

location constraints to guide their placement. They help

ensure optimal implementation of common functions.

For HDL design entry, the Xilinx FPGA Foundation develop-

ment system provides interfaces to the following synthesis

design environments.

•Synopsys (FPGA Compiler, FPGA Express)

•Exemplar (Spectrum)

•Synplicity (Synplify)

For schematic design entry, the Xilinx FPGA Foundation

and Alliance development system provides interfaces to the

following schematic-capture design environments.

•Mentor Graphics V8 (Design Architect, QuickSim II)

•Viewlogic Systems (Viewdraw)

Third-party vendors support many other environments.

A standard interface-file specification, Electronic Design

Interchange Format (EDIF), simplifies file transfers into and

out of the development system.

Virtex-E FPGAs are supported by a unified library of stan-

dard functions. This library contains over 400 primitives and

macros, ranging from 2-input AND gates to 16-bit accumu-

lators, and includes arithmetic functions, comparators,

counters, data registers, decoders, encoders, I/O functions,

latches, Boolean functions, multiplexers, shift registers, and

barrel shifters.

The “soft macro” portion of the library contains detailed

descriptions of common logic functions, but does not con-

tain any partitioning or placement information. The perfor-

mance of these macros depends, therefore, on the

partitioning and placement obtained during implementation.

RPMs, on the other hand, do contain predetermined parti-

tioning and placement information that permits optimal

implementation of these functions. Users can create their

own library of soft macros or RPMs based on the macros

and primitives in the standard library.

The design environment supports hierarchical design entry,

with high-level schematics that comprise major functional

blocks, while lower-level schematics define the logic in

these blocks. These hierarchical design elements are auto-

matically combined by the implementation tools. Different

design entry tools can be combined within a hierarchical

design, thus allowing the most convenient entry method to

be used for each portion of the design.

Design Implementation

The place-and-route tools (PAR) automatically provide the

implementation flow described in this section. The parti-

tioner takes the EDIF net list for the design and maps the

logic into the architectural resources of the FPGA (CLBs

and IOBs, for example). The placer then determines the

best locations for these blocks based on their interconnec-

Table 7 : IDCODEs Assigned to Virtex-E FPGAs

FPGA IDCODE

XCV405EM v0C28093h

XCV812EM v0C38093h

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tions and the desired performance. Finally, the router inter-

connects the blocks.

The PAR algorithms support fully automatic implementation

of most designs. For demanding applications, however, the

user can exercise various degrees of control over the pro-

cess. User partitioning, placement, and routing information

is optionally specified during the design-entry process. The

implementation of highly structured designs can benefit

greatly from basic floor planning.

The implementation software incorporates Timing Wizard®

timing-driven placement and routing. Designers specify tim-

ing requirements along entire paths during design entry.

The timing path analysis routines in PAR then recognize

these user-specified requirements and accommodate them.

Timing requirements are entered on a schematic in a form

directly relating to the system requirements, such as the tar-

geted clock frequency, or the maximum allowable delay

between two registers. In this way, the overall performance

of the system along entire signal paths is automatically tai-

lored to user-generated specifications. Specific timing infor-

mation for individual nets is unnecessary.

Design Verification

In addition to conventional software simulation, FPGA users

can use in-circuit debugging techniques. Because Xilinx

devices are infinitely reprogrammable, designs can be veri-

fied in real time without the need for extensive sets of soft-

ware simulation vectors.

The development system supports both software simulation

and in-circuit debugging techniques. For simulation, the

system extracts the post-layout timing information from the

design database, and back-annotates this information into

the net list for use by the simulator. Alternatively, the user

can verify timing-critical portions of the design using the

TRCE® static timing analyzer.

For in-circuit debugging, an optional download and read-

back cable is available. This cable connects the FPGA in the

target system to a PC or workstation. After downloading the

design into the FPGA, the designer can single-step the

logic, readback the contents of the flip-flops, and so observe

the internal logic state. Simple modifications can be down-

loaded into the system in a matter of minutes.

Configuration

Virtex-E devices are configured by loading configuration

data into the internal configuration memory. Note that

attempting to load an incorrect bitstream causes configura-

tion to fail and can damage the device.

Some of the pins used for configuration are dedicated pins,

while others can be re-used as general purpose inputs and

outputs once configuration is complete.

The following are dedicated pins:

•Mode pins (M2, M1, M0)

•Configuration clock pin (CCLK)

•PROGRAM pin

•DONE pin

•Boundary-scan pins (TDI, TDO, TMS, TCK)

Depending on the configuration mode chosen, CCLK can

be an output generated by the FPGA, or it can be generated

externally and provided to the FPGA as an input. The

PROGRAM pin must be pulled High prior to reconfiguration.

Note that some configuration pins can act as outputs. For

correct operation, these pins require a VCCO of 3.3 V to per-

mit LVTTL operation. All of the pins affected are in banks 2

or 3. The configuration pins needed for SelectMap (CS,

Write) are located in bank 1.

Configuration Modes

Virtex-E supports the following four configuration modes.

•Slave-serial mode

•Master-serial mode

•SelectMAP mode

•Boundary-scan mode (JTAG)

The Configuration mode pins (M2, M1, M0) select among

these configuration modes with the option in each case of

having the IOB pins either pulled up or left floating prior to

configuration. The selection codes are listed in Ta b l e 8 .

Configuration through the boundary-scan port is always

available, independent of the mode selection. Selecting the

boundary-scan mode simply turns off the other modes. The

three mode pins have internal pull-up resistors, and default

to a logic High if left unconnected. However, it is recom-

mended to drive the configuration mode pins externally.

Table 8: Configuration Codes

Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial Dout Configuration Pull-ups

Master-serial mode 0 0 0 Out 1 Yes No

Boundary-scan mode 1 0 1 N/A 1 No No

SelectMAP mode 1 1 0 In 8 No No

Slave-serial mode 1 1 1 In 1 Yes No

Master-serial mode 1 0 0 Out 1 Yes Yes

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Table 9 lists the total number of bits required to configure

each device.

Slave-Serial Mode

In slave-serial mode, the FPGA receives configuration data

in bit-serial form from a serial PROM or other source of

serial configuration data. The serial bitstream must be set

up at the DIN input pin a short time before each rising edge

of an externally generated CCLK.

For more detailed information on serial PROMs see the

PROM data sheet at http://www.xilinx.com/bvdocs/publica-

tions/ds026.pdf.

Multiple FPGAs can be daisy-chained for configuration from

a single source. After a particular FPGA has been config-

ured, the data for the next device is routed to the DOUT pin.

Data on the DOUT pin changes on the rising edge of CCLK.

The change of DOUT on the rising edge of CCLK differs

from previous families but does not cause a problem for

mixed configuration chains. This change was made to

improve serial configuration rates for Virtex and Virtex-E

only chains.

Figure 13 shows a full master/slave system. A Virtex-E

device in slave-serial mode should be connected as shown

in the right-most device.

Slave-serial mode is selected by applying <111> or <011>

to the mode pins (M2, M1, M0). A weak pull-up on the mode

pins makes slave-serial the default mode if the pins are left

unconnected. However, it is recommended to drive the con-

figuration mode pins externally. Figure 14 shows

slave-serial mode programming switching characteristics.

Ta ble 10 provides more detail about the characteristics

shown in Figure 14. Configuration must be delayed until the

INIT pins of all daisy-chained FPGAs are High.

Boundary-scan mode 0 0 1 N/A 1 No Yes

SelectMAP mode 0 1 0 In 8 No Yes

Slave-serial mode 0 1 1 In 1 Yes Yes

Table 8: Configuration Codes

Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial Dout Configuration Pull-ups

Table 9: Virtex-E Bitstream Lengths

Device # of Configuration Bits

XCV405E 3,430,400

XCV812E 6,519,648

Table 10: Master/Slave Serial Mode Programming Switching

Description

Figure

References Symbol Values Units

CCLK

DIN setup/hold, slave mode 1/2 TDCC/TCCD 5.0/0.0 ns, min

DIN setup/hold, master mode 1/2 TDSCK/TCKDS 5.0/0.0 ns, min

DOUT 3T

CCO 12.0 ns, max

High time 4T

CCH 5.0 ns, min

Low time 5T

CCL 5.0 ns, min

Maximum Frequency FCC 66 MHz, max

Frequency Tolerance, master mode with respect to nominal +45% –30%

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Master-Serial Mode

In master-serial mode, the CCLK output of the FPGA drives

a Xilinx Serial PROM that feeds bit-serial data to the DIN

input. The FPGA accepts this data on each rising CCLK

edge. After the FPGA has been loaded, the data for the next

device in a daisy-chain is presented on the DOUT pin after

the rising CCLK edge.

The interface is identical to slave-serial except that an inter-

nal oscillator is used to generate the configuration clock

(CCLK). A wide range of frequencies can be selected for

CCLK which always starts at a slow default frequency. Con-

figuration bits then switch CCLK to a higher frequency for

the remainder of the configuration. Switching to a lower fre-

quency is prohibited.

The CCLK frequency is set using the ConfigRate option in

the bitstream generation software. The maximum CCLK fre-

quency that can be selected is 60 MHz. When selecting a

CCLK frequency, ensure that the serial PROM and any

daisy-chained FPGAs are fast enough to support the clock

rate.

On power-up, the CCLK frequency is approximately

2.5 MHz. This frequency is used until the ConfigRate bits

have been loaded when the frequency changes to the

selected ConfigRate. Unless a different frequency is speci-

fied in the design, the default ConfigRate is 4 MHz.

Figure 13 shows a full master/slave system. In this system,

the left-most device operates in master-serial mode. The

remaining devices operate in slave-serial mode. The SPROM

RESET pin is driven by INIT, and the CE input is driven by

DONE. There is the potential for contention on the DONE pin,

depending on the start-up sequence options chosen.

Figure 13: Master/Slave Serial Mode Circuit Diagram

VIRTEX-E

MASTER

SERIAL

VIRTEX-E,

XC4000XL,

SLAVE

XC1701L

PROGRAM

M0 M1

DOUT

CCLK CLK

3.3V

DATA

CE CEO

RESET/OE DONE

DIN

INIT INIT

DONE

PROGRAM PROGRAM

CCLK

DIN DOUT

M0 M1

(Low Reset Option Used)

4.7 K

XCVE_ds_013

N/C

Figure 14: Slave-Serial Mode Programming Switching Characteristics

4TCCH

3TCCO

5TCCL

2TCCD

1TDCC

DIN

CCLK

DOUT

(Output)

X5379_a

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The sequence of operations necessary to configure a

Virtex-E FPGA serially appears in Figure 15.

Figure 16 shows the timing of master-serial configuration.

Master-serial mode is selected by a <000> or <100> on the

mode pins (M2, M1, M0). Table 10 shows the timing infor-

mation for Figure 16

At power-up, VCC must rise from 1.0 V to VCC min in less

than 50 ms, otherwise delay configuration by pulling

PROGRAM Low until VCC is valid.

SelectMAP Mode

The SelectMAP mode is the fastest configuration option.

Byte-wide data is written into the FPGA with a BUSY flag

controlling the flow of data.

An external data source provides a byte stream, CCLK, a

Chip Select (CS) signal and a Write signal (WRITE). If

BUSY is asserted (High) by the FPGA, the data must be

held until BUSY goes Low.

Data can also be read using the SelectMAP mode. If

WRITE is not asserted, configuration data is read out of the

FPGA as part of a readback operation.

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained to permit high-speed 8-bit readback.

Retention of the SelectMAP port is selectable on a

design-by-design basis when the bitstream is generated. If

retention is selected, PROHIBIT constraints are required to

prevent SelectMAP-port pins from being used as user I/O.

Multiple Virtex-E FPGAs can be configured using the

SelectMAP mode, and be made to start-up simultaneously.

To configure multiple devices in this way, wire the individual

CCLK, Data, WRITE, and BUSY pins of all the devices in

parallel. The individual devices are loaded separately by

asserting the CS pin of each device in turn and writing the

appropriate data. See Ta bl e 1 1 for SelectMAP Write Timing

Characteristics.

Write

Write operations send packets of configuration data into the

FPGA. The sequence of operations for a multi-cycle write

operation is shown below. Note that a configuration packet

can be split into many such sequences. The packet does

not have to complete within one assertion of CS, illustrated

in Figure 17.

1. Assert WRITE and CS Low. Note that when CS is

asserted on successive CCLKs, WRITE must remain

Figure 15: Serial Configuration Flowchart

Apply Power

Set PROGRAM = High

Release INIT If used to delay

configuration

Load a Configuration Bit

High

Low

FPGA makes a final

clearing pass and releases

INIT when finished.

FPGA starts to clear

configuration memory.

ds009_15_111799

Configuration Completed

End of

Bitstream?

Yes

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

If no CRC errors found,

FPGA enters start-up phase

causing DONE to go High.

INIT?

Figure 16: Master-Serial Mode Programming Switching Characteristics

Serial Data In

CCLK

(Output)

Serial DOUT

(Output)

1TDSCK

TCKDS

DS022_44_071201

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either asserted or de-asserted. Otherwise an abort is

initiated, as described below.

2. Drive data onto D[7:0]. Note that to avoid contention,

the data source should not be enabled while CS is Low

and WRITE is High. Similarly, while WRITE is High, no

more that one CS should be asserted.

3. At the rising edge of CCLK: If BUSY is Low, the data is

accepted on this clock. If BUSY is High (from a previous

write), the data is not accepted. Acceptance instead

occurs on the first clock after BUSY goes Low, and the

data must be held until this has happened.

4. Repeat steps 2 and 3 until all the data has been sent.

5. De-assert CS and WRITE.

A flowchart for the write operation appears in Figure 18.

Note that if CCLK is slower than fCCNH, the FPGA never

asserts BUSY, In this case, the above handshake is unnec-

essary, and data can simply be entered into the FPGA every

CCLK cycle.

Abort

During a given assertion of CS, the user cannot switch from

a write to a read, or vice-versa. This action causes the cur-

rent packet command to be aborted. The device remains

BUSY until the aborted operation has completed. Following

an abort, data is assumed to be unaligned to word bound-

aries, and the FPGA requires a new synchronization word

prior to accepting any new packets.

To initiate an abort during a write operation, de-assert

WRITE. At the rising edge of CCLK, an abort is initiated, as

shown in Figure 19.

Table 11: SelectMAP Write Timing Characteristics

Description Symbol Values Units

CCLK

D0-7 Setup/Hold 1/2 TSMDCC/TSMCCD 5.0 / 1.7 ns, min

CS Setup/Hold 3/4 TSMCSCC/TSMCCCS 7.0 / 1.7 ns, min

WRITE Setup/Hold 5/6 TSMCCW/TSMWCC 7.0 / 1.7 ns, min

BUSY Propagation Delay 7 TSMCKBY 12.0 ns, max

Maximum Frequency FCC 66 MHz, max

Maximum Frequency with no handshake FCCNH 50 MHz, max

Figure 17: Write Operations

DS022_45_071702

CCLK

No Write Write No Write Write

DATA[0:7]

WRITE

BUSY

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Boundary-Scan Mode

In the boundary-scan mode, configuration is done through

the IEEE 1149.1 Test Access Port. Note that the

PROGRAM pin must be pulled High prior to reconfiguration.

A Low on the PROGRAM pin resets the TAP controller and

no JTAG operations can be performed.

Figure 18: SelectMAP Flowchart for Write Operations

Apply Power

Release INIT If used to delay

configuration

On first FPGA

PROGRAM

from Low

to High

Set WRITE = Low

Enter Data Source

Set CS = Low

On first FPGA

Set CS = High

Apply Configuration Byte

INIT?

High

Low

Yes

Busy?

Low

High

Disable Data Source

Set WRITE = High

When all DONE pins

are released, DONE goes High

and start-up sequences complete.

If no errors,

later FPGAs enter start-up phase

releasing DONE.

If no errors,

first FPGAs enter start-up phase

releasing DONE.

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

FPGA makes a final

clearing pass and releases

INIT when finished.

FPGA starts to clear

configuration memory.

For any other FPGAs

ds003_17_090602

Repeat Sequence A

Configuration Completed

Sequence A

End of Data?

Yes

Figure 19: SelectMAP Write Abort Waveforms

CCLK

WRITE

Abort

DATA[0:7]

BUSY

DS022_46_071702

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Configuration through the TAP uses the CFG_IN instruc-

tion. This instruction allows data input on TDI to be con-

verted into data packets for the internal configuration bus.

The following steps are required to configure the FPGA

through the boundary-scan port (when using TCK as a

start-up clock).

1. Load the CFG_IN instruction into the boundary-scan

instruction register (IR)

2. Enter the Shift-DR (SDR) state

3. Shift a configuration bitstream into TDI

4. Return to Run-Test-Idle (RTI)

5. Load the JSTART instruction into IR

6. Enter the SDR state

7. Clock TCK through the startup sequence

8. Return to RTI

Configuration and readback via the TAP is always available.

The boundary-scan mode is selected by a <101> or <001>

on the mode pins (M2, M1, M0). For details on TAP charac-

teristics, refer to XAPP139.

Configuration Sequence

The configuration of Virtex-E devices is a three-phase pro-

cess. First, the configuration memory is cleared. Next, con-

figuration data is loaded into the memory, and finally, the

logic is activated by a start-up process.

Configuration is automatically initiated on power-up unless

it is delayed by the user, as described below. The configura-

tion process can also be initiated by asserting PROGRAM.

The end of the memory-clearing phase is signalled by INIT

going High, and the completion of the entire process is sig-

nalled by DONE going High.

The power-up timing of configuration signals is shown in

Figure 20.

The corresponding timing characteristics are listed in

Table 12.

Delaying Configuration

INIT can be held Low using an open-drain driver. An

open-drain is required since INIT is a bidirectional

open-drain pin that is held Low by the FPGA while the con-

figuration memory is being cleared. Extending the time that

the pin is Low causes the configuration sequencer to wait.

Thus, configuration is delayed by preventing entry into the

phase where data is loaded.

Start-Up Sequence

The default Start-up sequence is that one CCLK cycle after

DONE goes High, the global 3-state signal (GTS) is

released. This permits device outputs to turn on as neces-

sary.

One CCLK cycle later, the Global Set/Reset (GSR) and Glo-

bal Write Enable (GWE) signals are released. This permits

Figure 20: Power-Up Timing Configuration Signals

VALI

PROGRAM

Vcc

CCLK OUTPUT or INPUT

M0, M1, M2

(Required)

TPL

TICCK

ds022_020_071201

TPOR

INIT

Table 12: Power-up Timing Characteristics

Description Symbol Value Units

Power-on Reset1TPOR 2.0 ms, max

Program Latency TPL 100.0 µs, max

CCLK (output) Delay TICCK

0.5 µs, min

4.0 µs, max

Program Pulse Width TPROGRAM 300 ns, min

Notes:

1. TPOR delay is the initialization time required after VCCINT

reaches the recommended operating voltage.

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1-800-255-7778 19

the internal storage elements to begin changing state in

response to the logic and the user clock.

The relative timing of these events can be changed. In addi-

tion, the GTS, GSR, and GWE events can be made depen-

dent on the DONE pins of multiple devices all going High,

forcing the devices to start synchronously. The sequence

can also be paused at any stage until lock has been

achieved on any or all DLLs.

Readback

The configuration data stored in the Virtex-E configuration

memory can be readback for verification. Along with the

configuration data it is possible to readback the contents all

flip-flops/latches, LUT RAMs, and block RAMs. This capa-

bility is used for real-time debugging. For more detailed

information, see application note XAPP138 “Virtex FPGA

Series Configuration and Readback”.

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Design Considerations

This section contains more detailed design information on

the following features.

•Delay-Locked Loop . . . see page 20

•BlockRAM . . . see page 24

•SelectI/O . . . see page 31

Using DLLs

The Virtex-E FPGA series provides up to eight fully digital

dedicated on-chip Delay-Locked Loop (DLL) circuits which

provide zero propagation delay, low clock skew between

output clock signals distributed throughout the device, and

advanced clock domain control. These dedicated DLLs can

be used to implement several circuits which improve and

simplify system level design.

Introduction

As FPGAs grow in size, quality on-chip clock distribution

becomes increasingly important. Clock skew and clock

delay impact device performance and the task of managing

clock skew and clock delay with conventional clock trees

becomes more difficult in large devices. The Virtex-E series

of devices resolve this potential problem by providing up to

eight fully digital dedicated on-chip DLL circuits which pro-

vide zero propagation delay and low clock skew between

output clock signals distributed throughout the device.

Each DLL can drive up to two global clock routing networks

within the device. The global clock distribution network min-

imizes clock skews due to loading differences. By monitor-

ing a sample of the DLL output clock, the DLL can

compensate for the delay on the routing network, effectively

eliminating the delay from the external input port to the indi-

vidual clock loads within the device.

In addition to providing zero delay with respect to a user

source clock, the DLL can provide multiple phases of the

source clock. The DLL can also act as a clock doubler or it

can divide the user source clock by up to 16.

Clock multiplication gives the designer a number of design

alternatives. For instance, a 50 MHz source clock doubled

by the DLL can drive an FPGA design operating at 100

MHz. This technique can simplify board design because the

clock path on the board no longer distributes such a

high-speed signal. A multiplied clock also provides design-

ers the option of time-domain-multiplexing, using one circuit

twice per clock cycle, consuming less area than two copies

of the same circuit. Two DLLs in can be connected in series

to increase the effective clock multiplication factor to four.

The DLL can also act as a clock mirror. By driving the DLL

output off-chip and then back in again, the DLL can be used

to de-skew a board level clock between multiple devices.

In order to guarantee the system clock establishes prior to

the device “waking up,” the DLL can delay the completion of

the device configuration process until after the DLL

achieves lock.

By taking advantage of the DLL to remove on-chip clock

delay, the designer can greatly simplify and improve system

level design involving high-fanout, high-performance clocks.

Library DLL Symbols

Figure 21 shows the simplified Xilinx library DLL macro

symbol, BUFGDLL. This macro delivers a quick and effi-

cient way to provide a system clock with zero propagation

delay throughout the device. Figure 22 and Figure 23 show

the two library DLL primitives. These symbols provide

access to the complete set of DLL features when imple-

menting more complex applications.

Figure 21: Simplified DLL Macro Symbol BUFGDLL

Figure 22: Standard DLL Symbol CLKDLL

Figure 23: High Frequency DLL Symbol

0ns

ds022_25_121099

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_26_121099

CLKDLL

CLK0

CLK180

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_027_121099

CLKDLLHF

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BUFGDLL Pin Descriptions

Use the BUFGDLL macro as the simplest way to provide

zero propagation delay for a high-fanout on-chip clock from

an external input. This macro uses the IBUFG, CLKDLL and

BUFG primitives to implement the most basic DLL applica-

tion as shown in Figure 24.

This symbol does not provide access to the advanced clock

domain controls or to the clock multiplication or clock divi-

sion features of the DLL. This symbol also does not provide

access to the RST, or LOCKED pins of the DLL. For access

to these features, a designer must use the library DLL prim-

itives described in the following sections.

Source Clock Input — I

The I pin provides the user source clock, the clock signal on

which the DLL operates, to the BUFGDLL. For the BUF-

GDLL macro the source clock frequency must fall in the low

frequency range as specified in the data sheet. The BUF-

GDLL requires an external signal source clock. Therefore,

only an external input port can source the signal that drives

the BUFGDLL I pin.

Clock Output — O

The clock output pin O represents a delay-compensated

version of the source clock (I) signal. This signal, sourced by

a global clock buffer BUFG symbol, takes advantage of the

dedicated global clock routing resources of the device.

The output clock has a 50-50 duty cycle unless you deacti-

vate the duty cycle correction property.

CLKDLL Primitive Pin Descriptions

The library CLKDLL primitives provide access to the com-

plete set of DLL features needed when implementing more

complex applications with the DLL.

Source Clock Input — CLKIN

The CLKIN pin provides the user source clock (the clock

signal on which the DLL operates) to the DLL. The CLKIN

frequency must fall in the ranges specified in the data sheet.

A global clock buffer (BUFG) driven from another CLKDLL,

one of the global clock input buffers (IBUFG), or an

IO_LVDS_DLL pin on the same edge of the device (top or

bottom) must source this clock signal. There are four

IO_LVDS_DLL input pins that can be used as inputs to the

DLLs. This makes a total of eight usable input pins for DLLs

in the Virtex-E family.

Feedback Clock Input — CLKFB

The DLL requires a reference or feedback signal to provide

the delay-compensated output. Connect only the CLK0 or

CLK2X DLL outputs to the feedback clock input (CLKFB)

pin to provide the necessary feedback to the DLL. The feed-

back clock input can also be provided through one of the fol-

lowing pins.

IBUFG - Global Clock Input Pad

IO_LVDS_DLL - the pin adjacent to IBUFG

If an IBUFG sources the CLKFB pin, the following special

rules apply.

1. An external input port must source the signal that drives

the IBUFG I pin.

2. The CLK2X output must feedback to the device if both

the CLK0 and CLK2X outputs are driving off chip

devices.

3. That signal must directly drive only OBUFs and nothing

else.

These rules enable the software determine which DLL clock

output sources the CLKFB pin.

Reset Input — RST

When the reset pin RST activates the LOCKED signal deac-

tivates within four source clock cycles. The RST pin, active

High, must either connect to a dynamic signal or tied to

ground. As the DLL delay taps reset to zero, glitches can

occur on the DLL clock output pins. Activation of the RST

pin can also severely affect the duty cycle of the clock out-

put pins. Furthermore, the DLL output clocks no longer

de-skew with respect to one another. For these reasons,

rarely use the reset pin unless re-configuring the device or

changing the input frequency.

2x Clock Output — CLK2X

The output pin CLK2X provides a frequency-doubled clock

with an automatic 50/50 duty-cycle correction. Until the

CLKDLL has achieved lock, the CLK2X output appears as a

1x version of the input clock with a 25/75 duty cycle. This

behavior allows the DLL to lock on the correct edge with

respect to source clock. This pin is not available on the

CLKDLLHF primitive.

Clock Divide Output — CLKDV

The clock divide output pin CLKDV provides a lower fre-

quency version of the source clock. The CLKDV_DIVIDE

property controls CLKDV such that the source clock is

divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.

This feature provides automatic duty cycle correction such

that the CLKDV output pin always has a 50/50 duty cycle,

with the exception of noninteger divides in HF mode, where

the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5.

Figure 24: BUFGDLL Schematic

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_28_121099

CLKDLL BUFG

IBUFG

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1x Clock Outputs — CLK[0|90|180|270]

The 1x clock output pin CLK0 represents a delay-compen-

sated version of the source clock (CLKIN) signal. The

CLKDLL primitive provides three phase-shifted versions of

the CLK0 signal while CLKDLLHF provides only the 180

phase-shifted version. The relationship between phase shift

and the corresponding period shift appears in Table 13.

The timing diagrams in Figure 25 illustrate the DLL clock

output characteristics.

The DLL provides duty cycle correction on all 1x clock out-

puts such that all 1x clock outputs by default have a 50/50

duty cycle. The DUTY_CYCLE_CORRECTION property

(TRUE by default), controls this feature. In order to deacti-

vate the DLL duty cycle correction, attach the

DUTY_CYCLE_CORRECTION=FALSE property to the

DLL symbol. When duty cycle correction deactivates, the

output clock has the same duty cycle as the source clock.

The DLL clock outputs can drive an OBUF, a BUFG, or they

can route directly to destination clock pins. The DLL clock

outputs can only drive the BUFGs that reside on the same

edge (top or bottom).

Locked Output — LOCKED

To achieve lock, the DLL might need to sample several thou-

sand clock cycles. After the DLL achieves lock, the

LOCKED signal activates. The DLL timing parameter sec-

tion of the data sheet provides estimates for locking times.

To guarantee that the system clock is established prior to

the device “waking up,” the DLL can delay the completion of

the device configuration process until after the DLL locks.

The STARTUP_WAIT property activates this feature.

Until the LOCKED signal activates, the DLL output clocks

are not valid and can exhibit glitches, spikes, or other spuri-

ous movement. In particular the CLK2X output appears as a

1x clock with a 25/75 duty cycle.

DLL Properties

Properties provide access to some of the Virtex-E series

DLL features, (for example, clock division and duty cycle

correction).

Duty Cycle Correction Property

The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,

use the duty-cycle corrected default, exhibiting a 50/50 duty

cycle. The DUTY_CYCLE_CORRECTION property (by

default TRUE) controls this feature. To deactivate the DLL

duty-cycle correction for the 1x clock outputs, attach the

DUTY_CYCLE_CORRECTION=FALSE property to the

DLL symbol.

Clock Divide Property

The CLKDV_DIVIDE property specifies how the signal on

the CLKDV pin is frequency divided with respect to the

CLK0 pin. The values allowed for this property are 1.5, 2,

2.5, 3, 4, 5, 8, or 16; the default value is 2.

Startup Delay Property

This property, STARTUP_WAIT, takes on a value of TRUE

or FALSE (the default value). When TRUE the device con-

figuration DONE signal waits until the DLL locks before

going to High.

Virtex-E DLL Location Constraints

As shown in Figure 26, there are four additional DLLs in the

Virtex-E devices, for a total of eight per Virtex-E device.

These DLLs are located in silicon, at the top and bottom of

the two innermost block SelectRAM columns. The location

constraint LOC, attached to the DLL symbol with the identi-

fier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S,

or DLL3P, controls the DLL location.

The LOC property uses the following form:

LOC = DLL0P

Table 13: Relationship of Phase-Shifted Output Clock

to Period Shift

Phase (degrees) Period Shift (percent)

00%

90 25%

180 50%

270 75%

Figure 25: DLL Output Characteristics

ds022_29_121099

CLKIN

CLK2X

CLK0

CLK90

CLK180

CLK270

CLKDV

CLKDV_DIVIDE=2

DUTY_CYCLE_CORRECTION=FALSE

CLK0

CLK90

CLK180

CLK270

DUTY_CYCLE_CORRECTION=TRUE

0 90 180 270 0 90 180 270

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Design Factors

Use the following design considerations to avoid pitfalls and

improve success designing with Xilinx devices.

Input Clock

The output clock signal of a DLL, essentially a delayed ver-

sion of the input clock signal, reflects any instability on the

input clock in the output waveform. For this reason the qual-

ity of the DLL input clock relates directly to the quality of the

output clock waveforms generated by the DLL. The DLL

input clock requirements are specified in the data sheet.

In most systems a crystal oscillator generates the system

clock. The DLL can be used with any commercially available

quartz crystal oscillator. For example, most crystal oscilla-

tors produce an output waveform with a frequency tolerance

of 100 PPM, meaning 0.01 percent change in the clock

period. The DLL operates reliably on an input waveform with

a frequency drift of up to 1 ns — orders of magnitude in

excess of that needed to support any crystal oscillator in the

industry. However, the cycle-to-cycle jitter must be kept to

less than 300 ps in the low frequencies and 150 ps for the

high frequencies.

Input Clock Changes

Changing the period of the input clock beyond the maximum

drift amount requires a manual reset of the CLKDLL. Failure

to reset the DLL produces an unreliable lock signal and out-

put clock.

It is possible to stop the input clock with little impact to the

DLL. Stopping the clock should be limited to less than

100 µs to keep device cooling to a minimum. The clock

should be stopped during a Low phase, and when restored

the full High period should be seen. During this time

LOCKED stays High and remains High when the clock is

restored.

When the clock is stopped, one to four more clocks are still

observed as the delay line is flushed. When the clock is

restarted, the output clocks are not observed for one to four

clocks as the delay line is filled. The most common case is

two or three clocks.

In a similar manner, a phase shift of the input clock is also

possible. The phase shift propagates one to four clocks to

the output after the original shift, with no disruption to the

CLKDLL control.

Output Clocks

As mentioned earlier in the DLL pin descriptions, some

restrictions apply regarding the connectivity of the output

pins. The DLL clock outputs can drive an OBUF, a global

clock buffer BUFG, or they can route directly to destination

clock pins. The only BUFGs that the DLL clock outputs can

drive are the two on the same edge of the device (top or bot-

tom). In addition, the CLK2X output of the secondary DLL

can connect directly to the CLKIN of the primary DLL in the

same quadrant.

Do not use the DLL output clock signals until after activation

of the LOCKED signal. Prior to the activation of the

LOCKED signal, the DLL output clocks are not valid and

can exhibit glitches, spikes, or other spurious movement.

Useful Application Examples

The Virtex-E DLL can be used in a variety of creative and

useful applications. The following examples show some of

the more common applications. The Verilog and VHDL

example files are available at:

ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip

Standard Usage

The circuit shown in Figure 27 resembles the BUFGDLL

macro implemented to provide access to the RST and

LOCKED pins of the CLKDLL.

Board Level De-Skew of Multiple Non-Virtex-E

Devices

The circuit shown in Figure 28 can be used to de-skew a

system clock between a Virtex-E chip and other non-Vir-

tex-E chips on the same board. This application is com-

monly used when the Virtex-E device is used in conjunction

with other standard products such as SRAM or DRAM

devices. While designing the board level route, ensure that

the return net delay to the source equals the delay to the

other chips involved.

Figure 26: Virtex Series DLLs

x132_14_100799

DLL-3P

DLL-1P

DLL-3S

DLL-1S

DLL-2S

DLL-0S

DLL-2P

DLL-0P

Bottom Right

Half Edge

Figure 27: Standard DLL Implementation

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_028_121099

CLKDLL BUFG

IBUFG

IBUF OBUF

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Board-level de-skew is not required for low-fanout clock net-

works. It is recommended for systems that have fanout lim-

itations on the clock network, or if the clock distribution chip

cannot handle the load.

Do not use the DLL output clock signals until after activation

of the LOCKED signal. Prior to the activation of the

LOCKED signal, the DLL output clocks are not valid and

can exhibit glitches, spikes, or other spurious movement.

The dll_mirror_1 files in the xapp132.zip file show the VHDL

and Verilog implementation of this circuit.

De-Skew of Clock and Its 2x Multiple

The circuit shown in Figure 29 implements a 2x clock multi-

plier and also uses the CLK0 clock output with zero ns skew

between registers on the same chip. A clock divider circuit

could alternatively be implemented using similar connec-

tions.

Because any single DLL can access only two BUFGs at

most, any additional output clock signals must be routed

from the DLL in this example on the high speed backbone

routing.

The dll_2x files in the xapp132.zip file show the VHDL and

Verilog implementation of this circuit.

Virtex-E 4x Clock

Two DLLs located in the same half-edge (top-left, top-right,

bottom-right, bottom-left) can be connected together, with-

out using a BUFG between the CLKDLLs, to generate a 4x

clock as shown in Figure 30. Virtex-E devices, like the Virtex

devices, have four clock networks that are available for inter-

nal de-skewing of the clock. Each of the eight DLLs have

access to two of the four clock networks. Although all the

DLLs can be used for internal de-skewing, the presence of

two GCLKBUFs on the top and two on the bottom indicate

that only two of the four DLLs on the top (and two of the four

DLLs on the bottom) can be used for this purpose.

The dll_4xe files in the xapp 32.zip file show the DLL imple-

mentation in Verilog for Virtex-E devices. These files can be

found at:

ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip

Using Block SelectRAM+ Features

The Virtex FPGA Series provides dedicated blocks of

on-chip, true dual-read/write port synchronous RAM, with

4096 memory cells. Each port of the block SelectRAM+

memory can be independently configured as a read/write

port, a read port, a write port, and can be configured to a

specific data width. block SelectRAM+ memory offers new

capabilities, allowing FPGA designers to simplify designs.

Figure 28: DLL De-skew of Board Level Clock

Figure 29: DLL De-skew of Clock and 2x Multiple

ds022_029_121099

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

CLKDLL OBUFIBUFG

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

CLKDLL BUFG

IBUFG

Non-Virtex-E Chip

Other Non_Virtex-E Chips

Virtex-E Device

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_030_121099

CLKDLL BUFG

IBUFG

IBUF OBUF

BUFG

Figure 30: DLL Generation of 4x Clock in Virtex-E

Devices

ds022_031_041901

RST

CLKFB

CLKIN

CLKDLL-S

LOCKED

CLKDV

INV

BUFG

OBUF

IBUFG

CLK2X

CLK0

CLK90

CLK180

CLK270

RST

CLKFB

CLKIN

CLKDLL-P

LOCKED

CLKDV

CLK2X

CLK0

CLK90

CLK180

CLK270

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1-800-255-7778 25

Operating Modes

Virtex-E block SelectRAM+ memory supports two operating

modes.

•Read Through

•Write Back

Read Through (one clock edge)

The read address is registered on the read port clock edge

and data appears on the output after the RAM access time.

Some memories might place the latch/register at the out-

puts, depending on the desire to have a faster clock-to-out

versus set-up time. This is generally considered to be an

inferior solution, since it changes the read operation to an

asynchronous function with the possibility of missing an

address/control line transition during the generation of the read

pulse clock.

Write Back (one clock edge)

The write address is registered on the write port clock edge

and the data input is written to the memory and mirrored on

the output.

Block SelectRAM+ Characteristics

1. All inputs are registered with the port clock and have a

set-up to clock timing specification.

2. All outputs have a read through or write back function

depending on the state of the port WE pin. The outputs

relative to the port clock are available after the

clock-to-out timing specification.

3. The block SelectRAM elements are true SRAM

memories and do not have a combinatorial path from

the address to the output. The LUT SelectRAM+ cells in

the CLBs are still available with this function.

4. The ports are completely independent from each other

(i.e., clocking, control, address, read/write function, and

data width) without arbitration.

5. A write operation requires only one clock edge.

6. A read operation requires only one clock edge.

The output ports are latched with a self-timed circuit to guar-

antee a glitch-free read. The state of the output port does

not change until the port executes another read or write

operation.

Library Primitives

Figure 31 and Figure 32 show the two generic library block

SelectRAM+ primitives. Table 14 describes all of the avail-

able primitives for synthesis and simulation.

Figure 31: Dual-Port Block SelectRAM+ Memory

Figure 32: Single-Port Block SelectRAM+ Memory

Table 14: Available Library Primitives

Primitive Port A Width Port B Width

RAMB4_S1

RAMB4_S1_S1

RAMB4_S1_S2

RAMB4_S1_S4

RAMB4_S1_S8

RAMB4_S1_S16

1N/A

RAMB4_S2

RAMB4_S2_S2

RAMB4_S2_S4

RAMB4_S2_S8

RAMB4_S2_S16

2N/A

RAMB4_S4

RAMB4_S4_S4

RAMB4_S4_S8

RAMB4_S4_S16

4N/A

RAMB4_S8

RAMB4_S8_S8

RAMB4_S8_S16

8N/A

RAMB4_S16

RAMB4_S16_S16

16 N/A

WEB

ENB

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

WEA

ENA

RSTA

CLKA

ADDRA[#:0]

DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

ds022_032_121399

ds022_033_121399

DO[#:0]

RST

CLK

ADDR[#:0]

DI[#:0]

RAMB4_S#

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Port Signals

Each block SelectRAM+ port operates independently of the

others while accessing the same set of 4096 memory cells.

Table 15 describes the depth and width aspect ratios for the

block SelectRAM+ memory.

Clock—CLK[A|B]

Each port is fully synchronous with independent clock pins.

All port input pins have setup time referenced to the port

CLK pin. The data output bus has a clock-to-out time refer-

enced to the CLK pin.

Enable—EN[A|B]

The enable pin affects the read, write and reset functionality

of the port. Ports with an inactive enable pin keep the output

pins in the previous state and do not write data to the mem-

ory cells.

Write Enable—WE[A|B]

Activating the write enable pin allows the port to write to the

memory cells. When active, the contents of the data input

bus are written to the RAM at the address pointed to by the

address bus, and the new data also reflects on the data out

bus. When inactive, a read operation occurs and the con-

tents of the memory cells referenced by the address bus

reflect on the data out bus.

Reset—RST[A|B]

The reset pin forces the data output bus latches to zero syn-

chronously. This does not affect the memory cells of the

RAM and does not disturb a write operation on the other

port.

Address Bus—ADDR[A|B]<#:0>

The address bus selects the memory cells for read or write.

The width of the port determines the required width of this

bus as shown in Ta bl e 1 5 .

Data In Bus—DI[A|B]<#:0>

The data in bus provides the new data value to be written

into the RAM. This bus and the port have the same width, as

shown in Ta bl e 1 5 .

Data Output Bus—DO[A|B]<#:0>

The data out bus reflects the contents of the memory cells

referenced by the address bus at the last active clock edge.

During a write operation, the data out bus reflects the data

in bus. The width of this bus equals the width of the port.

The allowed widths appear in Ta bl e 1 5 .

Inverting Control Pins

The four control pins (CLK, EN, WE and RST) for each port

have independent inversion control as a configuration option.

Address Mapping

Each port accesses the same set of 4096 memory cells

using an addressing scheme dependent on the width of the

port. The physical RAM location addressed for a particular

width are described in the following formula (of interest only

when the two ports use different aspect ratios).

Start = ((ADDRport +1) * Widthport) –1

End = ADDRport * Widthport

Ta ble 16 shows low order address mapping for each port

width.

Creating Larger RAM Structures

The block SelectRAM+ columns have specialized routing to

allow cascading blocks together with minimal routing

delays. This achieves wider or deeper RAM structures with

a smaller timing penalty than when using normal routing

channels.

Location Constraints

Block SelectRAM+ instances can have LOC properties

attached to them to constrain the placement. The block

SelectRAM+ placement locations are separate from the

CLB location naming convention, allowing the LOC proper-

ties to transfer easily from array to array.

The LOC properties use the following form.

LOC = RAMB4_R#C#

RAMB4_R0C0 is the upper left RAMB4 location on the

device.

Table 15: Block SelectRAM+ Port Aspect Ratios

Width Depth ADDR Bus Data Bus

1 4096 ADDR<11:0> DATA<0>

2 2048 ADDR<10:0> DATA<1:0>

4 1024 ADDR<9:0> DATA<3:0>

8 512 ADDR<8:0> DATA<7:0>

16 256 ADDR<7:0> DATA<15:0>

Table 16: Port Address Mapping

Port

Width

Port

Addresses

1 4095...

2 2047... 07 06 05 04 03 02 01 00

4 1023... 03 02 01 00

8511... 01 00

16 255... 00

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1-800-255-7778 27

Conflict Resolution

The block SelectRAM+ memory is a true dual-read/write

port RAM that allows simultaneous access of the same

memory cell from both ports. When one port writes to a

given memory cell, the other port must not address that

memory cell (for a write or a read) within the clock-to-clock

setup window. The following lists specifics of port and mem-

ory cell write conflict resolution.

•If both ports write to the same memory cell

simultaneously, violating the clock-to-clock setup

requirement, consider the data stored as invalid.

•If one port attempts a read of the same memory cell

the other simultaneously writes, violating the

clock-to-clock setup requirement, the following occurs.

- The write succeeds

- The data out on the writing port accurately reflects

the data written.

- The data out on the reading port is invalid.

Conflicts do not cause any physical damage.

Single Port Timing

Figure 33 shows a timing diagram for a single port of a block

SelectRAM+ memory. The block SelectRAM+ AC switching

characteristics are specified in the data sheet. The block

SelectRAM+ memory is initially disabled.

At the first rising edge of the CLK pin, the ADDR, DI, EN,

WE, and RST pins are sampled. The EN pin is High and the

WE pin is Low indicating a read operation. The DO bus con-

tains the contents of the memory location, 0x00, as indi-

cated by the ADDR bus.

At the second rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN and WE pins

are High indicating a write operation. The DO bus mirrors

the DI bus. The DI bus is written to the memory location

0x0F.

At the third rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN pin is High

and the WE pin is Low indicating a read operation. The DO

bus contains the contents of the memory location 0x7E as

indicated by the ADDR bus.

At the fourth rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN pin is Low

indicating that the block SelectRAM+ memory is now dis-

abled. The DO bus retains the last value.

Dual Port Timing

Figure 34 shows a timing diagram for a true dual-port

read/write block SelectRAM+ memory. The clock on port A

has a longer period than the clock on Port B. The timing

parameter TBCCS, (clock-to-clock set-up) is shown on this

diagram. The parameter, TBCCS is violated once in the dia-

gram. All other timing parameters are identical to the single

port version shown in Figure 33.

TBCCS is only of importance when the address of both ports

are the same and at least one port is performing a write

operation. When the clock-to-clock set-up parameter is vio-

lated for a WRITE-WRITE condition, the contents of the

memory at that location are invalid. When the clock-to-clock

set-up parameter is violated for a WRITE-READ condition,

the contents of the memory are correct, but the read port

has invalid data. At the first rising edge of CLKA, memory

location 0x00 is to be written with the value 0xAAAA and is

mirrored on the DOA bus. The last operation of Port B was

a read to the same memory location 0x00. The DOB bus of

Port B does not change with the new value on Port A, and

retains the last read value. A short time later, Port B exe-

cutes another read to memory location 0x00, and the DOB

bus now reflects the new memory value written by Port A.

At the second rising edge of CLKA, memory location 0x7E

is written with the value 0x9999 and is mirrored on the DOA

bus. Port B then executes a read operation to the same

memory location without violating the TBCCS parameter and

the DOB reflects the new memory values written by Port A.

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At the third rising edge of CLKA, the TBCCS parameter is

violated with two writes to memory location 0x0F. The DOA

and DOB busses reflect the contents of the DIA and DIB

busses, but the stored value at 0x0F is invalid.

At the fourth rising edge of CLKA, a read operation is per-

formed at memory location 0x0F and invalid data is present

on the DOA bus. Port B also executes a read operation to

memory location 0x0F and also reads invalid data.

At the fifth rising edge of CLKA a read operation is per-

formed that does not violate the TBCCS parameter to the

previous write of 0x7E by Port B. THe DOA bus reflects the

recently written value by Port B.

Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory

ds022_0343_121399

CLK

TBPWH

TBACK

ADDR 00

DDDD

MEM (00) CCCC MEM (7E)

CCCC

7E 8F

BBBB 2222

DIN

DOUT

RST

DISABLED READ WRITE READ DISABLED

TBDCK

TBECK

TBWCK

TBCKO

TBPWL

Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory

ds022_035_121399

CLK_A

PORT APORT B

ADDR_A 00 7E 0F

00 00 7E 7E 1A0F 0F

0F 7E

AAAA 9999 AAAA 0000 1111

2222

AAAA 9999 AAAA UNKNOWN

EN_A

WE_A

DI_A

DO_A

1111 1111 1111 2222 FFFFBBBB 1111

AAAAMEM (00) 9999 2222 FFFFBBBB UNKNOWN

CLK_B

ADDR_B

EN_B

WE_B

DI_B

DO_B

TBCCS

VIOLATION

TBCCS

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1-800-255-7778 29

Initialization

The block SelectRAM+ memory can initialize during the

device configuration sequence. The 16 initialization properties

of 64 hex values each (a total of 4096 bits) set the initialization

of each RAM. These properties appear in Ta b l e 1 7 . Any initial-

ization properties not explicitly set configure as zeros. Partial

initialization strings pad with zeros. Initialization strings

greater than 64 hex values generate an error. The RAMs can

be simulated with the initialization values using generics in

VHDL simulators and parameters in Verilog simulators.

Initialization in VHDL and Synopsys

The block SelectRAM+ structures can be initialized in VHDL

for both simulation and synthesis for inclusion in the EDIF

output file. The simulation of the VHDL code uses a generic

to pass the initialization. Synopsys FPGA compiler does not

presently support generics. The initialization values instead

attach as attributes to the RAM by a built-in Synopsys

dc_script. The translate_off statement stops synthesis

translation of the generic statements. The following code

illustrates a module that employs these techniques.

Initialization in Verilog and Synopsys

The block SelectRAM+ structures can be initialized in Verilog

for both simulation and synthesis for inclusion in the EDIF

output file. The simulation of the Verilog code uses a def-

param to pass the initialization. The Synopsys FPGA com-

piler does not presently support defparam. The initialization

values instead attach as attributes to the RAM by a built-in

Synopsys dc_script. The translate_off statement stops syn-

thesis translation of the defparam statements. The following

code illustrates a module that employs these techniques.

Design Examples

Creating a 32-bit Single-Port RAM

The true dual-read/write port functionality of the block

SelectRAM+ memory allows a single port, 128 deep by

32-bit wide RAM to be created using a single block

SelectRAM+ cell as shown inTable 35.

Interleaving the memory space, setting the LSB of the

address bus of Port A to 1 (VCC), and the LSB of the

address bus of Port B to 0 (GND), allows a 32-bit wide sin-

gle port RAM to be created.

Creating Two Single-Port RAMs

The true dual-read/write port functionality of the block

SelectRAM+ memory allows a single RAM to be split into two

single port memories of 2K bits each as shown in Figure 36.

In this example, a 512K x 4 RAM (Port A) and a 128 x 16

RAM (Port B) are created out of a single block SelectRAM+.

The address space for the RAM is split by fixing the MSB of

Port A to 1 (VCC) for the upper 2K bits and the MSB of Port

B to 0 (GND) for the lower 2K bits.

Block Memory Generation

The CoreGen program generates memory structures using

the block SelectRAM+ features. This program outputs

VHDL or Verilog simulation code templates and an EDIF file

for inclusion in a design.

Table 17: RAM Initialization Properties

Property Memory Cells

INIT_00 255 to 0

INIT_01 511 to 256

INIT_02 767 to 512

INIT_03 1023 to 768

INIT_04 1279 to 1024

INIT_05 1535 to 1280

INIT_06 1791 to 2047

INIT_07 2047 to 1792

INIT_08 2303 to 2048

INIT_09 2559 to 2304

INIT_0a 2815 to 2560

INIT_0b 3071 to 2816

INIT_0c 3327 to 3072

INIT_0d 3583 to 3328

INIT_0e 3839 to 3584

INIT_0f 4095 to 3840

Figure 35: Single Port 128 x 32 RAM

Figure 36: 512 x 4 RAM and 128 x 16 RAM

WEB

ENB

RSTB

CLKB

ADDRB[7:0]

DIB[15:0]

WEA

ENA

RSTA

CLKA

ADDRA[7:0]

DIA[15:0]

ADDR[6:0], VCC

CLK

RST

CLK

RST

DI[31:16]

ADDR[6:0], GND

DI[15:0]

DOA[15:0] DO[31:16]

DO[15:0]

DOB[15:0]

RAMB4_S16_S16

ds022_036_121399

WEB

ENB

RSTB

CLKB

ADDRB[7:0]

DIB[15:0]

WEA

ENA

RSTA

CLKA

ADDRA[9:0]

DIA[3:0]

, ADDR1[8:0]

DI1[3:0]

WE1

EN1

RST1

CLK1

WE2

EN2

RST2

CLK2

GND, ADDR2[6:0]

DI2[15:0]

DOA[3:0] DO1[3:0]

DO2[15:0]

DOB[15:0]

RAMB4_S4_S16

ds022_037_121399

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30 1-800-255-7778

VHDL Initialization Example

library IEEE;

use IEEE.std_logic_1164.all;

entity MYMEM is

port (CLK, WE:in std_logic;

ADDR: in std_logic_vector(8 downto 0);

DIN: in std_logic_vector(7 downto 0);

DOUT: out std_logic_vector(7 downto 0));

end MYMEM;

architecture BEHAVE of MYMEM is

signal logic0, logic1: std_logic;

component RAMB4_S8

--synopsys translate_off

generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07,

INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255

downto 0)

:= X"0000000000000000000000000000000000000000000000000000000000000000");

--synopsys translate_on

port (WE, EN, RST, CLK: in STD_LOGIC;

ADDR: in STD_LOGIC_VECTOR(8 downto 0);

DI: in STD_LOGIC_VECTOR(7 downto 0);

DO: out STD_LOGIC_VECTOR(7 downto 0));

end component;

--synopsys dc_script_begin

--set_attribute ram0 INIT_00

"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string

--set_attribute ram0 INIT_01

"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string

--synopsys dc_script_end

begin

logic0 <=’0’;

logic1 <=’1’;

ram0: RAMB4_S8

--synopsys translate_off

generic map (

INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",

INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")

--synopsys translate_on

port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT);

end BEHAVE;

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1-800-255-7778 31

Verilog Initialization Example

module MYMEM (CLK, WE, ADDR, DIN, DOUT);

input CLK, WE;

input [8:0] ADDR;

input [7:0] DIN;

output [7:0] DOUT;

wire logic0, logic1;

//synopsys dc_script_begin

//set_attribute ram0 INIT_00

"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string

//set_attribute ram0 INIT_01

"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string

//synopsys dc_script_end

assign logic0 = 1’b0;

assign logic1 = 1’b1;

RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN),

.DO(DOUT));

//synopsys translate_off

defparam ram0.INIT_00 =

256h’0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF;

defparam ram0.INIT_01 =

256h’FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210;

//synopsys translate_on

endmodule

Using SelectI/O

The Virtex-E FPGA series includes a highly configurable,

high-performance I/O resource, called SelectI/O™ to pro-

vide support for a wide variety of I/O standards. The

SelectI/O resource is a robust set of features including pro-

grammable control of output drive strength, slew rate, and

input delay and hold time. Taking advantage of the flexibility

and SelectI/O features and the design considerations

described in this document can improve and simplify sys-

tem level design.

Introduction

As FPGAs continue to grow in size and capacity, the larger

and more complex systems designed for them demand an

increased variety of I/O standards. Furthermore, as system

clock speeds continue to increase, the need for high perfor-

mance I/O becomes more important. While chip-to-chip

delays have an increasingly substantial impact on overall

system speed, the task of achieving the desired system per-

formance becomes more difficult with the proliferation of

low-voltage I/O standards.

SelectI/O, the revolutionary input/output resource of Vir-

tex-E devices, has resolved this potential problem by provid-

ing a highly configurable, high-performance alternative to

the I/O resources of more conventional programmable

devices. The Virtex-E SelectI/O features combine the flexi-

bility and time-to-market advantages of programmable logic

with the high performance previously available only with

ASICs and custom ICs.

Each SelectI/O block can support up to 20 I/O standards.

Supporting such a variety of I/O standards allows the support

of a wide variety of applications, from general purpose stan-

dard applications to high-speed low-voltage memory busses.

SelectI/O blocks also provide selectable output drive

strengths and programmable slew rates for the LVTTL out-

put buffers, as well as an optional, programmable weak

pull-up, weak pull-down, or weak “keeper” circuit ideal for

use in external bussing applications.

Each input/output block (IOB) includes three registers, one

each for the input, output, and 3-state signals within the

IOB. These registers are optionally configurable as either a

D-type flip-flop or as a level sensitive latch.

The input buffer has an optional delay element used to guar-

antee a zero hold time requirement for input signals regis-

tered within the IOB.

The Virtex-E SelectI/O features also provide dedicated

resources for input reference voltage (VREF) and output

source voltage (VCCO), along with a convenient banking

system that simplifies board design.

By taking advantage of the built-in features and wide variety

of I/O standards supported by the SelectI/O features, sys-

tem-level design and board design can be greatly simplified

and improved.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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32 1-800-255-7778

Fundamentals

Modern bus applications, pioneered by the largest and most

influential companies in the digital electronics industry, are

commonly introduced with a new I/O standard tailored spe-

cifically to the needs of that application. The bus I/O stan-

dards provide specifications to other vendors who create

products designed to interface with these applications.

Each standard often has its own specifications for current,

voltage, I/O buffering, and termination techniques.

The ability to provide the flexibility and time-to-market

advantages of programmable logic is increasingly depen-

dent on the capability of the programmable logic device to

support an ever increasing variety of I/O standards

The SelectI/O resources feature highly configurable input

and output buffers which provide support for a wide variety

of I/O standards. As shown in Ta bl e 1 8 , each buffer type can

support a variety of voltage requirements.

Overview of Supported I/O Standards

This section provides a brief overview of the I/O standards

supported by all Virtex-E devices.

While most I/O standards specify a range of allowed volt-

ages, this document records typical voltage values only.

Detailed information on each specification can be found on

the Electronic Industry Alliance Jedec website at:

http://www.jedec.org

LVTTL — Low-Voltage TTL

The Low-Voltage TTL, or LVTTL standard is a general pur-

pose EIA/JESDSA standard for 3.3 V applications that uses

an LVTTL input buffer and a Push-Pull output buffer. This

standard requires a 3.3 V output source voltage (VCCO), but

does not require the use of a reference voltage (VREF) or a

termination voltage (VTT).

LV C M O S2 — Low-Voltage CMOS for 2.5 Volts

The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2

standard is an extension of the LVCMOS standard (JESD

8.-5) used for general purpose 2.5 V applications. This stan-

dard requires a 2.5 V output source voltage (VCCO), but

does not require the use of a reference voltage (VREF) or a

board termination voltage (VTT).

LV C M O S1 8 — 1.8 V Low Voltage CMOS

This standard is an extension of the LVCMOS standard. It is

used in general purpose 1.8 V applications. The use of a

reference voltage (VREF) or a board termination voltage

(VTT) is not required.

PCI — Peripheral Component Interface

The Peripheral Component Interface, or PCI standard spec-

ifies support for both 33 MHz and 66 MHz PCI bus applica-

tions. It uses a LVTTL input buffer and a Push-Pull output

buffer. This standard does not require the use of a reference

voltage (VREF) or a board termination voltage (VTT), how-

ever, it does require a 3.3 V output source voltage (VCCO).

GTL — Gunning Transceiver Logic Terminated

The Gunning Transceiver Logic, or GTL standard is a

high-speed bus standard (JESD8.3) invented by Xerox. Xil-

inx has implemented the terminated variation for this stan-

dard. This standard requires a differential amplifier input

buffer and a Open Drain output buffer.

GTL+ — Gunning Transceiver Logic Plus

The Gunning Transceiver Logic Plus, or GTL+ standard is a

high-speed bus standard (JESD8.3) first used by the Pen-

tium Pro processor.

HSTL — High-Speed Transceiver Logic

The High-Speed Transceiver Logic, or HSTL standard is a

general purpose high-speed, 1.5 V bus standard sponsored

by IBM (EIA/JESD 8-6). This standard has four variations or

classes. SelectI/O devices support Class I, III, and IV. This

Table 18: Virtex-E Supported I/O Standards

I/O

Standard

Output

VCCO

Input

VCCO

Input

VREF

Board

Termination

Voltage (VTT)

LVTTL 3.3 3.3 N/A N/A

LVCMOS2 2.5 2.5 N/A N/A

LVCMOS18 1.8 1.8 N/A N/A

SSTL3 I & II 3.3 N/A 1.50 1.50

SSTL2 I & II 2.5 N/A 1.25 1.25

GTL N/A N/A 0.80 1.20

GTL+ N/A N/A 1.0 1.50

HSTL I 1.5 N/A 0.75 0.75

HSTL III & IV 1.5 N/A 0.90 1.50

CTT 3.3 N/A 1.50 1.50

AGP-2X 3.3 N/A 1.32 N/A

PCI33_3 3.3 3.3 N/A N/A

PCI66_3 3.3 3.3 N/A N/A

BLVDS & LVDS 2.5 N/A N/A N/A

LVPECL 3.3 N/A N/A N/A

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standard requires a Differential Amplifier input buffer and a

Push-Pull output buffer.

SSTL3 — Stub Series Terminated Logic for 3.3V

The Stub Series Terminated Logic for 3.3 V, or SSTL3 stan-

dard is a general purpose 3.3 V memory bus standard also

sponsored by Hitachi and IBM (JESD8-8). This standard has

two classes, I and II. SelectI/O devices support both classes

for the SSTL3 standard. This standard requires a Differential

Amplifier input buffer and an Push-Pull output buffer.

SSTL2 — Stub Series Terminated Logic for 2.5V

The Stub Series Terminated Logic for 2.5 V, or SSTL2 stan-

dard is a general purpose 2.5 V memory bus standard

sponsored by Hitachi and IBM (JESD8-9). This standard

has two classes, I and II. SelectI/O devices support both

classes for the SSTL2 standard. This standard requires a

Differential Amplifier input buffer and an Push-Pull output

buffer.

CTT — Center Tap Terminated

The Center Tap Terminated, or CTT standard is a 3.3 V

memory bus standard sponsored by Fujitsu (JESD8-4).

This standard requires a Differential Amplifier input buffer

and a Push-Pull output buffer.

AGP-2X — Advanced Graphics Port

The Intel AGP standard is a 3.3 V Advanced Graphics

Port-2X bus standard used with the Pentium II processor for

graphics applications. This standard requires a Push-Pull

output buffer and a Differential Amplifier input buffer.

LV DS — Low Voltage Differential Signal

LVDS is a differential I/O standard. It requires that one data

bit is carried through two signal lines. As with all differential

signaling standards, LVDS has an inherent noise immunity

over single-ended I/O standards. The voltage swing

between two signal lines is approximately 350 mV. The use

of a reference voltage (VREF) or a board termination voltage

(VTT) is not required. LVDS requires the use of two pins per

input or output. LVDS requires external resistor termination.

BLVDS — Bus LVDS

This standard allows for bidirectional LVDS communication

between two or more devices. The external resistor termi-

nation is different than the one for standard LVDS.

LV P EC L — Low Voltage Positive Emitter Coupled

Logic

LVPECL is another differential I/O standard. It requires two

signal lines for transmitting one data bit. This standard

specifies two pins per input or output. The voltage swing

between these two signal lines is approximately 850 mV.

The use of a reference voltage (VREF) or a board termina-

tion voltage (VTT) is not required. The LVPECL standard

requires external resistor termination.

Library Symbols

The Xilinx library includes an extensive list of symbols

designed to provide support for the variety of SelectI/O fea-

tures. Most of these symbols represent variations of the five

generic SelectI/O symbols.

•IBUF (input buffer)

•IBUFG (global clock input buffer)

•OBUF (output buffer)

•OBUFT (3-state output buffer)

•IOBUF (input/output buffer)

IBUF

Signals used as inputs to the Virtex-E device must source

an input buffer (IBUF) via an external input port. The generic

Virtex-E IBUF symbol appears in Figure 37. The extension

to the base name defines which I/O standard the IBUF

uses. The assumed standard is LVTTL when the generic

IBUF has no specified extension.

The following list details the variations of the IBUF symbol:

•IBUF

•IBUF_LVCMOS2

•IBUF_PCI33_3

•IBUF_PCI66_3

•IBUF_GTL

•IBUF_GTLP

•IBUF_HSTL_I

•IBUF_HSTL_III

•IBUF_HSTL_IV

•IBUF_SSTL3_I

•IBUF_SSTL3_II

•IBUF_SSTL2_I

•IBUF_SSTL2_II

•IBUF_CTT

•IBUF_AGP

•IBUF_LVCMOS18

•IBUF_LVDS

•IBUF_LVPECL

When the IBUF symbol supports an I/O standard that

requires a VREF

, the IBUF automatically configures as a dif-

ferential amplifier input buffer. The VREF voltage must be

supplied on the VREF pins. In the case of LVDS, LVPECL,

and BLVDS, VREF is not required.

Figure 37: Input Buffer (IBUF) Symbols

IBUF

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The voltage reference signal is “banked” within the Virtex-E

device on a half-edge basis such that for all packages there

are eight independent VREF banks internally. See Figure 38

for a representation of the Virtex-E I/O banks. Within each

bank approximately one of every six I/O pins is automati-

cally configured as a VREF input. After placing a differential

amplifier input signal within a given VREF bank, the same

external source must drive all I/O pins configured as a VREF

input.

IBUF placement restrictions require that any differential

amplifier input signals within a bank be of the same stan-

dard. How to specify a specific location for the IBUF via the

LOC property is described below. Table 19 summarizes the

Virtex-E input standards compatibility requirements.

An optional delay element is associated with each IBUF.

When the IBUF drives a flip-flop within the IOB, the delay

element by default activates to ensure a zero hold-time

requirement. The NODELAY=TRUE property overrides this

default.

When the IBUF does not drive a flip-flop within the IOB, the

delay element de-activates by default to provide higher per-

formance. To delay the input signal, activate the delay ele-

ment with the DELAY=TRUE property.

IBUFG

Signals used as high fanout clock inputs to the Virtex-E

device should drive a global clock input buffer (IBUFG) via

an external input port in order to take advantage of one of

the four dedicated global clock distribution networks. The

output of the IBUFG should only drive a CLKDLL,

CLKDLLHF, or a BUFG symbol. The generic Virtex-E

IBUFG symbol appears in Figure 39.

The extension to the base name determines which I/O stan-

dard is used by the IBUFG. With no extension specified for

the generic IBUFG symbol, the assumed standard is

LVTTL.

The following list details variations of the IBUFG symbol.

•IBUFG

•IBUFG_LVCMOS2

•IBUFG_PCI33_3

•IBUFG_PCI66_3

•IBUFG_GTL

•IBUFG_GTLP

•IBUFG_HSTL_I

•IBUFG_HSTL_III

•IBUFG_HSTL_IV

•IBUFG_SSTL3_I

•IBUFG_SSTL3_II

•IBUFG_SSTL2_I

•IBUFG_SSTL2_II

•IBUFG_CTT

•IBUFG_AGP

•IBUFG_LVCMOS18

•IBUFG_LVDS

•IBUFG_LVPECL

When the IBUFG symbol supports an I/O standard that

requires a differential amplifier input, the IBUFG automati-

cally configures as a differential amplifier input buffer. The

low-voltage I/O standards with a differential amplifier input

require an external reference voltage input VREF

The voltage reference signal is “banked” within the Virtex-E

device on a half-edge basis such that for all packages there

are eight independent VREF banks internally. See Figure 38

for a representation of the Virtex-E I/O banks. Within each

bank approximately one of every six I/O pins is automati-

cally configured as a VREF input. After placing a differential

amplifier input signal within a given VREF bank, the same

external source must drive all I/O pins configured as a VREF

input.

IBUFG placement restrictions require any differential ampli-

fier input signals within a bank be of the same standard. The

LOC property can specify a location for the IBUFG.

Figure 38: Virtex-E I/O Banks

Table 19: Xilinx Input Standards Compatibility

Requirements

Rule 1 Standards with the same input VCCO, output VCCO,

and VREF can be placed within the same bank.

ds022_42_012100

Bank 0

GCLK3 GCLK2

GCLK1 GCLK0

Bank 1

Bank 5 Bank 4

Virtex-E

Device

Bank 7Bank 6

Bank 2Bank 3

Figure 39: Virtex-E Global Clock Input Buffer (IBUFG)

Symbol

IBUFG

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As an added convenience, the BUFGP can be used to

instantiate a high fanout clock input. The BUFGP symbol

represents a combination of the LVTTL IBUFG and BUFG

symbols, such that the output of the BUFGP can connect

directly to the clock pins throughout the design.

Unlike previous architectures, the Virtex-E BUFGP symbol

can only be placed in a global clock pad location. The LOC

property can specify a location for the BUFGP.

OBUF

An OBUF must drive outputs through an external output

port. The generic output buffer (OBUF) symbol appears in

Figure 40.

The extension to the base name defines which I/O standard

the OBUF uses. With no extension specified for the generic

OBUF symbol, the assumed standard is slew rate limited

LVTTL with 12 mA drive strength.

The LVTTL OBUF additionally can support one of two slew

rate modes to minimize bus transients. By default, the slew

rate for each output buffer is reduced to minimize power bus

transients when switching non-critical signals.

LVTTL output buffers have selectable drive strengths.

The format for LVTTL OBUF symbol names is as follows.

OBUF_<slew_rate>_<drive_strength>

<slew_rate> is either F (Fast), or S (Slow) and

<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,

or 24).

The following list details variations of the OBUF symbol.

•OBUF

•OBUF_S_2

•OBUF_S_4

•OBUF_S_6

•OBUF_S_8

•OBUF_S_12

•OBUF_S_16

•OBUF_S_24

•OBUF_F_2

•OBUF_F_4

•OBUF_F_6

•OBUF_F_8

•OBUF_F_12

•OBUF_F_16

•OBUF_F_24

•OBUF_LVCMOS2

•OBUF_PCI33_3

•OBUF_PCI66_3

•OBUF_GTL

•OBUF_GTLP

•OBUF_HSTL_I

•OBUF_HSTL_III

•OBUF_HSTL_IV

•OBUF_SSTL3_I

•OBUF_SSTL3_II

•OBUF_SSTL2_I

•OBUF_SSTL2_II

•OBUF_CTT

•OBUF_AGP

•OBUF_LVCMOS18

•OBUF_LVDS

•OBUF_LVPECL

The Virtex-E series supports eight banks for the HQ and PQ

packages. The CS packages support four VCCO banks.

OBUF placement restrictions require that within a given

VCCO bank each OBUF share the same output source drive

voltage. Input buffers of any type and output buffers that do

not require VCCO can be placed within any VCCO bank.

Ta ble 20 summarizes the Virtex-E output compatibility

requirements. The LOC property can specify a location for

the OBUF.

OBUFT

The generic 3-state output buffer OBUFT, shown in

Figure 41, typically implements 3-state outputs or bidirec-

tional I/O.

The extension to the base name defines which I/O standard

OBUFT uses. With no extension specified for the generic

OBUFT symbol, the assumed standard is slew rate limited

LVTTL with 12 mA drive strength.

Figure 40: Virtex-E Output Buffer (OBUF) Symbol

OBUF

x133_04_111699

Table 20: Output Standards Compatibility

Requirements

Rule 1 Only outputs with standards that share compatible

VCCO can be used within the same bank.

Rule 2 There are no placement restrictions for outputs

with standards that do not require a VCCO.

VCCO Compatible Standards

3.3 LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,

GTL+, PCI33_3, PCI66_3

2.5 SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+

1.5 HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+

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The LVTTL OBUFT additionally can support one of two slew

rate modes to minimize bus transients. By default, the slew

rate for each output buffer is reduced to minimize power bus

transients when switching non-critical signals.

LVTTL 3-state output buffers have selectable drive

strengths.

The format for LVTTL OBUFT symbol names is as follows.

OBUFT_<slew_rate>_<drive_strength>

<slew_rate> can be either F (Fast), or S (Slow) and

<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,

or 24).

The following list details variations of the OBUFT symbol.

•OBUFT

•OBUFT_S_2

•OBUFT_S_4

•OBUFT_S_6

•OBUFT_S_8

•OBUFT_S_12

•OBUFT_S_16

•OBUFT_S_24

•OBUFT_F_2

•OBUFT_F_4

•OBUFT_F_6

•OBUFT_F_8

•OBUFT_F_12

•OBUFT_F_16

•OBUFT_F_24

•OBUFT_LVCMOS2

•OBUFT_PCI33_3

•OBUFT_PCI66_3

•OBUFT_GTL

•OBUFT_GTLP

•OBUFT_HSTL_I

•OBUFT_HSTL_III

•OBUFT_HSTL_IV

•OBUFT_SSTL3_I

•OBUFT_SSTL3_II

•OBUFT_SSTL2_I

•OBUFT_SSTL2_II

•OBUFT_CTT

•OBUFT_AGP

•OBUFT_LVCMOS18

•OBUFT_LVDS

•OBUFT_LVPECL

The Virtex-E series supports eight banks for the HQ and PQ

packages. The CS package supports four VCCO banks.

The SelectI/O OBUFT placement restrictions require that

within a given VCCO bank each OBUFT share the same out-

put source drive voltage. Input buffers of any type and out-

put buffers that do not require VCCO can be placed within

the same VCCO bank.

The LOC property can specify a location for the OBUFT.

3-state output buffers and bidirectional buffers can have

either a weak pull-up resistor, a weak pull-down resistor, or

a weak “keeper” circuit. Control this feature by adding the

appropriate symbol to the output net of the OBUFT (PUL-

LUP, PULLDOWN, or KEEPER).

The weak “keeper” circuit requires the input buffer within the

IOB to sample the I/O signal. So, OBUFTs programmed for

an I/O standard that requires a VREF have automatic place-

ment of a VREF in the bank with an OBUFT configured with

a weak “keeper” circuit. This restriction does not affect most

circuit design as applications using an OBUFT configured

with a weak “keeper” typically implement a bidirectional I/O.

In this case the IBUF (and the corresponding VREF) are

explicitly placed.

The LOC property can specify a location for the OBUFT.

IOBUF

Use the IOBUF symbol for bidirectional signals that require

both an input buffer and a 3-state output buffer with an

active high 3-state pin. The generic input/output buffer

IOBUF appears in Figure 42.

The extension to the base name defines which I/O standard

the IOBUF uses. With no extension specified for the generic

IOBUF symbol, the assumed standard is LVTTL input buffer

and slew rate limited LVTTL with 12 mA drive strength for

the output buffer.

The LVTTL IOBUF additionally can support one of two slew

rate modes to minimize bus transients. By default, the slew

rate for each output buffer is reduced to minimize power bus

transients when switching non-critical signals.

LVTTL bidirectional buffers have selectable output drive

strengths.

The format for LVTTL IOBUF symbol names is as follows.

IOBUF_<slew_rate>_<drive_strength>

<slew_rate> can be either F (Fast), or S (Slow) and

<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,

or 24).

Figure 41: 3-State Output Buffer Symbol (OBUFT)

OBUFT

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The following list details variations of the IOBUF symbol.

•IOBUF

•IOBUF_S_2

•IOBUF_S_4

•IOBUF_S_6

•IOBUF_S_8

•IOBUF_S_12

•IOBUF_S_16

•IOBUF_S_24

•IOBUF_F_2

•IOBUF_F_4

•IOBUF_F_6

•IOBUF_F_8

•IOBUF_F_12

•IOBUF_F_16

•IOBUF_F_24

•IOBUF_LVCMOS2

•IOBUF_PCI33_3

•IOBUF_PCI66_3

•IOBUF_GTL

•IOBUF_GTLP

•IOBUF_HSTL_I

•IOBUF_HSTL_III

•IOBUF_HSTL_IV

•IOBUF_SSTL3_I

•IOBUF_SSTL3_II

•IOBUF_SSTL2_I

•IOBUF_SSTL2_II

•IOBUF_CTT

•IOBUF_AGP

•IOBUF_LVCMOS18

•IOBUF_LVDS

•IOBUF_LVPECL

When the IOBUF symbol used supports an I/O standard

that requires a differential amplifier input, the IOBUF auto-

matically configures with a differential amplifier input buffer.

The low-voltage I/O standards with a differential amplifier

input require an external reference voltage input VREF

The voltage reference signal is “banked” within the Virtex-E

device on a half-edge basis such that for all packages there

are eight independent VREF banks internally. See Figure 38

on page 34 for a representation of the Virtex-E I/O banks.

Within each bank approximately one of every six I/O pins is

automatically configured as a VREF input. After placing a dif-

ferential amplifier input signal within a given VREF bank, the

same external source must drive all I/O pins configured as a

VREF input.

IOBUF placement restrictions require any differential ampli-

fier input signals within a bank be of the same standard.

The Virtex-E series supports eight banks for the HQ and PQ

packages. The CS package supports four VCCO banks.

Additional restrictions on the Virtex-E SelectI/O IOBUF

placement require that within a given VCCO bank each

IOBUF must share the same output source drive voltage.

Input buffers of any type and output buffers that do not

require VCCO can be placed within the same VCCO bank.

The LOC property can specify a location for the IOBUF.

An optional delay element is associated with the input path

in each IOBUF. When the IOBUF drives an input flip-flop

within the IOB, the delay element activates by default to

ensure a zero hold-time requirement. Override this default

with the NODELAY=TRUE property.

In the case when the IOBUF does not drive an input flip-flop

within the IOB, the delay element de-activates by default to

provide higher performance. To delay the input signal, acti-

vate the delay element with the DELAY=TRUE property.

3-state output buffers and bidirectional buffers can have

either a weak pull-up resistor, a weak pull-down resistor, or

a weak “keeper” circuit. Control this feature by adding the

appropriate symbol to the output net of the IOBUF (PUL-

LUP, PULLDOWN, or KEEPER).

SelectI/O Properties

Access to some of the SelectI/O features (for example, loca-

tion constraints, input delay, output drive strength, and slew

rate) is available through properties associated with these

features.

Input Delay Properties

An optional delay element is associated with each IBUF.

When the IBUF drives a flip-flop within the IOB, the delay

element activates by default to ensure a zero hold-time

requirement. Use the NODELAY=TRUE property to over-

ride this default.

In the case when the IBUF does not drive a flip-flop within

the IOB, the delay element by default de-activates to pro-

vide higher performance. To delay the input signal, activate

the delay element with the DELAY=TRUE property.

Figure 42: Input/Output Buffer Symbol (IOBUF)

IOBUF

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IOB Flip-Flop/Latch Property

The Virtex-E series I/O block (IOB) includes an optional reg-

ister on the input path, an optional register on the output

path, and an optional register on the 3-state control pin. The

design implementation software automatically takes advan-

tage of these registers when the following option for the Map

program is specified.

map -pr b <filename>

Alternatively, the IOB = TRUE property can be placed on a

Location Constraints

Specify the location of each SelectI/O symbol with the loca-

tion constraint LOC attached to the SelectI/O symbol. The

external port identifier indicates the value of the location

constrain. The format of the port identifier depends on the

package chosen for the specific design.

The LOC properties use the following form.

LOC=A42

LOC=P37

Output Slew Rate Property

As mentioned above, a variety of symbol names provide the

option of choosing the desired slew rate for the output buff-

ers. In the case of the LVTTL output buffers (OBUF, OBUFT,

and IOBUF), slew rate control can be alternatively pro-

gramed with the SLEW= property. By default, the slew rate

for each output buffer is reduced to minimize power bus

transients when switching non-critical signals. The SLEW=

property has one of the two following values.

SLEW=SLOW

SLEW=FAST

Output Drive Strength Property

The desired output drive strength can be additionally speci-

fied by choosing the appropriate library symbol. The Xilinx

library also provides an alternative method for specifying

this feature. For the LVTTL output buffers (OBUF, OBUFT,

and IOBUF, the desired drive strength can be specified with

the DRIVE= property. This property could have one of the

following seven values.

DRIVE=2

DRIVE=4

DRIVE=6

DRIVE=8

DRIVE=12 (Default)

DRIVE=16

DRIVE=24

Design Considerations

Reference Voltage (VREF) Pins

Low-voltage I/O standards with a differential amplifier input

buffer require an input reference voltage (VREF). Provide the

VREF as an external signal to the device.

The voltage reference signal is “banked” within the device on

a half-edge basis such that for all packages there are eight

independent VREF banks internally. See Figure 38 for a rep-

resentation of the Virtex-E I/O banks. Within each bank

approximately one of every six I/O pins is automatically con-

figured as a VREF input. After placing a differential amplifier

input signal within a given VREF bank, the same external

source must drive all I/O pins configured as a VREF input.

Within each VREF bank, any input buffers that require a

VREF signal must be of the same type. Output buffers of any

type and input buffers can be placed without requiring a ref-

erence voltage within the same VREF bank.

Output Drive Source Voltage (VCCO) Pins

Many of the low voltage I/O standards supported by

SelectI/O devices require a different output drive source

voltage (VCCO). As a result each device can often have to

support multiple output drive source voltages.

The Virtex-E series supports eight banks for the HQ and PQ

packages. The CS package supports four VCCO banks.

Output buffers within a given VCCO bank must share the

same output drive source voltage. Input buffers for LVTTL,

LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the

VCCO voltage for Input VCCO voltage.

Transmission Line Effects

The delay of an electrical signal along a wire is dominated

by the rise and fall times when the signal travels a short dis-

tance. Transmission line delays vary with inductance and

capacitance, but a well-designed board can experience

delays of approximately 180 ps per inch.

Transmission line effects, or reflections, typically start at

1.5" for fast (1.5 ns) rise and fall times. Poor (or non-exis-

tent) termination or changes in the transmission line imped-

ance cause these reflections and can cause additional

delay in longer traces. As system speeds continue to

increase, the effect of I/O delays can become a limiting fac-

tor and therefore transmission line termination becomes

increasingly more important.

Termination Techniques

A variety of termination techniques reduce the impact of

transmission line effects.

The following are output termination techniques:

•None

•Series

•Parallel (Shunt)

•Series and Parallel (Series-Shunt)

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Input termination techniques include the following:

•None

•Parallel (Shunt)

These termination techniques can be applied in any combi-

nation. A generic example of each combination of termina-

tion methods appears in Figure 43.

Simultaneous Switching Guidelines

Ground bounce can occur with high-speed digital ICs when

multiple outputs change states simultaneously, causing

undesired transient behavior on an output, or in the internal

logic. This problem is also referred to as the Simultaneous

Switching Output (SSO) problem.

Ground bounce is primarily due to current changes in the

combined inductance of ground pins, bond wires, and

ground metallization. The IC internal ground level deviates

from the external system ground level for a short duration (a

few nanoseconds) after multiple outputs change state

simultaneously.

Ground bounce affects stable Low outputs and all inputs

because they interpret the incoming signal by comparing it

to the internal ground. If the ground bounce amplitude

exceeds the actual instantaneous noise margin, then a

non-changing input can be interpreted as a short pulse with

a polarity opposite to the ground bounce.

Table 21 provides the guidelines for the maximum number

of simultaneously switching outputs allowed per output

power/ground pair to avoid the effects of ground bounce.

Refer to Table 22 for the number of effective output

power/ground pairs for each Virtex-E device and package

combination.

Figure 43: Overview of Standard Input and Output

Termination Methods

x133_07_111699

Unterminated Double Parallel Terminated

Series-Parallel Terminated Output

Driving a Parallel Terminated Input

VTT

VREF

Series Terminated Output Driving

a Parallel Terminated Input

VTT

VREF

Unterminated Output Driving

a Parallel Terminated Input

VTT

VREF

VTT

VREF

Series Terminated Output

VREF

Z=50

Table 21: Guidelines for Maximum Number of

Simultaneously Switching Outputs per

Power/Ground Pair

Standard

Package

BGA, FGA

LVTTL Slow Slew Rate, 2 mA drive 68

LVTTL Slow Slew Rate, 4 mA drive 41

LVTTL Slow Slew Rate, 6 mA drive 29

LVTTL Slow Slew Rate, 8 mA drive 22

LVTTL Slow Slew Rate, 12 mA drive 17

LVTTL Slow Slew Rate, 16 mA drive 14

LVTTL Slow Slew Rate, 24 mA drive 9

LVTTL Fast Slew Rate, 2 mA drive 40

LVTTL Fast Slew Rate, 4 mA drive 24

LVTTL Fast Slew Rate, 6 mA drive 17

LVTTL Fast Slew Rate, 8 mA drive 13

LVTTL Fast Slew Rate, 12 mA drive 10

LVTTL Fast Slew Rate, 16 mA drive 8

LVTTL Fast Slew Rate, 24 mA drive 5

LVC MO S 10

PCI 8

GTL 4

GTL+ 4

HSTL Class I 18

HSTL Class III 9

HSTL Class IV 5

SSTL2 Class I 15

SSTL2 Class II 10

SSTL3 Class I 11

SSTL3 Class II 7

CTT 14

AGP 9

Note: This analysis assumes a 35 pF load for each output.

Table 22: Virtex-E Extended Memory Family

Equivalent Power/Ground Pairs

Pkg/Part XCV405E XCV812E

BG560 56

FG676 56

FG900

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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40 1-800-255-7778

Application Examples

Creating a design with the SelectI/O features requires the

instantiation of the desired library symbol within the design

code. At the board level, designers need to know the termi-

nation techniques required for each I/O standard.

This section describes some common application examples

illustrating the termination techniques recommended by

each of the standards supported by the SelectI/O features.

Termination Examples

Circuit examples involving typical termination techniques for

each of the SelectI/O standards follow. For a full range of

accepted values for the DC voltage specifications for each

standard, refer to the table associated with each figure.

The resistors used in each termination technique example

and the transmission lines depicted represent board level

components and are not meant to represent components

on the device.

GTL

A sample circuit illustrating a valid termination technique for

GTL is shown in Figure 44. Ta bl e 2 3 lists DC voltage speci-

fications.

GTL+

A sample circuit illustrating a valid termination technique for

GTL+ appears in Figure 45. DC voltage specifications

appear in Ta b l e 2 4 .

Figure 44: Terminated GTL

VREF = 0.8V

VTT = 1.2V

50Ω

VCCO = N/A

Z = 50

GTL

x133_08_111699

VTT = 1.2V

Table 23: GTL Voltage Specifications

Parameter Min Typ Max

VCCO -N/A-

VREF = N × VTT10.74 0.8 0.86

VTT 1.14 1.2 1.26

VIH = VREF + 0.05 0.79 0.85 -

VIL = VREF – 0.05 - 0.75 0.81

VOH ---

VOL -0.20.4

IOH at VOH(mA) ---

IOLat VOL(mA) at 0.4V 32 - -

IOLat VOL(mA) at 0.2V - - 40

Note: N must be greater than or equal to 0.653 and less than

or equal to 0.68.

Figure 45: Terminated GTL+

Table 24: GTL+ Voltage Specifications

Parameter Min Typ Max

VCCO -- -

VREF = N × VTT10.88 1.0 1.12

VTT 1.35 1.5 1.65

VIH = VREF + 0.1 0.98 1.1 -

VIL = VREF – 0.1 - 0.9 1.02

VOH -- -

VOL 0.3 0.45 0.6

IOH at VOH (mA) - - -

IOLat VOL (mA) at 0.6V 36 - -

IOLat VOL (mA) at 0.3V - - 48

Note: N must be greater than or equal to 0.653 and less than

or equal to 0.68.

VREF = 1.0V

VTT = 1.5V

50Ω

VCCO = N/A Z = 50

GTL+

x133_09_012400

50Ω

VTT = 1.5V

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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1-800-255-7778 41

HSTL

A sample circuit illustrating a valid termination technique for

HSTL_I appears in Figure 46. A sample circuit illustrating a

valid termination technique for HSTL_III appears in

Figure 47.

A sample circuit illustrating a valid termination technique for

HSTL_IV appears in Figure 48.

Figure 46: Terminated HSTL Class I

Table 25: HSTL Class I Voltage Specification

Parameter Min Typ Max

VCCO 1.40 1.50 1.60

VREF 0.68 0.75 0.90

VTT -V

CCO × 0.5 -

VIH VREF + 0.1 - -

VIL --V

REF – 0.1

VOH VCCO – 0.4 - -

VOL 0.4

IOH at VOH (mA) −8- -

IOLat VOL (mA) 8 - -

Figure 47: Terminated HSTL Class III

VREF = 0.75V

VTT= 0.75V

50Ω

VCCO = 1.5V

Z = 50

HSTL Class I

x133_10_111699

VREF = 0.9V

VTT= 1.5V

50Ω

VCCO = 1.5V

Z = 50

HSTL Class III

x133_11_111699

Table 26: HSTL Class III Voltage Specification

Parameter Min Typ Max

VCCO 1.40 1.50 1.60

VREF (1) -0.90-

VTT -V

CCO -

VIH VREF + 0.1 - -

VIL --V

REF – 0.1

VOH VCCO – 0.4 - -

VOL --0.4

IOH at VOH (mA) −8--

IOLat VOL (mA) 24 - -

Note: Per EIA/JESD8-6, “The value of VREF is to be selected

by the user to provide optimum noise margin in the use

conditions specified by the user.”

Figure 48: Terminated HSTL Class IV

Table 27: HSTL Class IV Voltage Specification

Parameter Min Typ Max

VCCO 1.40 1.50 1.60

VREF -0.90 -

VTT -V

CCO -

VIH VREF + 0.1 - -

VIL --V

REF – 0.1

VOH VCCO – 0.4 - -

VOL --0.4

IOH at VOH (mA) −8- -

IOLat VOL (mA) 48 - -

Note: Per EIA/JESD8-6, “The value of VREF is to be selected

by the user to provide optimum noise margin in the use

conditions specified by the user.

50Ω

Z = 50

HSTL Class IV

x133_12_111699

50Ω

VREF = 0.9V

VTT= 1.5VVTT= 1.5V

VCCO = 1.5V

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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42 1-800-255-7778

SSTL3_I

A sample circuit illustrating a valid termination technique for

SSTL3_I appears in Figure 49. DC voltage specifications

appear in Ta bl e 2 8 .

SSTL3_II

A sample circuit illustrating a valid termination technique for

SSTL3_II appears in Figure 50. DC voltage specifications

appear in Ta bl e 2 9 .

SSTL2_I

A sample circuit illustrating a valid termination technique for

SSTL2_I appears in Figure 51. DC voltage specifications

appear in Ta b l e 3 0 .

Figure 49: Terminated SSTL3 Class I

Table 28: SSTL3_I Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF = 0.45 × VCCO 1.3 1.5 1.7

VTT = VREF 1.3 1.5 1.7

VIH = VREF + 0.2 1.5 1.7 3.9(1)

VIL = VREF – 0.2 −0.3(2) 1.3 1.5

VOH = VREF + 0.6 1.9 - -

VOL = VREF – 0.6 - - 1.1

IOH at VOH (mA) −8- -

IOLat VOL (mA) 8 - -

Notes:

1. VIH maximum is VCCO + 0.3

2. VIL minimum does not conform to the formula

Figure 50: Terminated SSTL3 Class II

50Ω

Z = 50

SSTL3 Class I

x133_13_111699

25Ω

REF

= 1.5V

CCO

= 3.3V

50Ω

Z = 50

SSTL3 Class II

x133_14_111699

25Ω50Ω

VREF = 1.5V

VTT= 1.5VVTT= 1.5V

VCCO = 3.3V

Table 29: SSTL3_II Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF = 0.45 × VCCO 1.3 1.5 1.7

VTT = VREF 1.3 1.5 1.7

VIH = VREF + 0.2 1.5 1.7 3.9(1)

VIL= VREF – 0.2 −0.3(2) 1.3 1.5

VOH = VREF + 0.8 2.1 - -

VOL= VREF – 0.8 - - 0.9

IOH at VOH (mA) −16 - -

IOLat VOL (mA) 16 - -

Notes:

1. VIH maximum is VCCO + 0.3

2. VIL minimum does not conform to the formula

Figure 51: Terminated SSTL2 Class I

Table 30: SSTL2_I Voltage Specifications

Parameter Min Typ Max

VCCO 2.3 2.5 2.7

VREF = 0.5 × VCCO 1.15 1.25 1.35

VTT = VREF + N(1) 1.11 1.25 1.39

VIH = VREF + 0.18 1.33 1.43 3.0(2)

VIL = VREF – 0.18 −0.3(3) 1.07 1.17

VOH = VREF + 0.61 1.76 - -

VOL= VREF – 0.61 - - 0.74

IOH at VOH (mA) −7.6 - -

IOLat VOL (mA) 7.6 - -

Notes:

1. N must be greater than or equal to –0.04 and less than or

equal to 0.04.

2. VIH maximum is VCCO + 0.3.

3. VIL minimum does not conform to the formula.

50Ω

Z = 50

SSTL2 Class I

xap133_15_011000

25Ω

VREF = 1.25V

VTT= 1.25V

VCCO = 2.5V

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1-800-255-7778 43

SSTL2_II

A sample circuit illustrating a valid termination technique for

SSTL2_II appears in Figure 52. DC voltage specifications

appear in Ta bl e 3 1 .

CTT

A sample circuit illustrating a valid termination technique for

CTT appear in Figure 53. DC voltage specifications appear

in Table 32.

PCI33_3 & PCI66_3

PCI33_3 or PCI66_3 require no termination. DC voltage

specifications appear in Ta b l e 3 3 .

Figure 52: Terminated SSTL2 Class II

Table 31: SSTL2_II Voltage Specifications

Parameter Min Typ Max

VCCO 2.3 2.5 2.7

VREF = 0.5 × VCCO 1.15 1.25 1.35

VTT = VREF + N(1) 1.11 1.25 1.39

VIH = VREF + 0.18 1.33 1.43 3.0(2)

VIL = VREF – 0.18 −0.3(3) 1.07 1.17

VOH = VREF + 0.8 1.95 - -

VOL = VREF – 0.8 - - 0.55

IOH at VOH (mA) −15.2 - -

IOLat VOL (mA) 15.2 - -

Notes:

1. N must be greater than or equal to –0.04 and less than or

equal to 0.04.

2. VIH maximum is VCCO + 0.3.

3. VIL minimum does not conform to the formula.

Figure 53: Terminated CTT

50Ω

Z = 50

SSTL2 Class II

x133_16_111699

25Ω50Ω

VREF = 1.25V

VTT= 1.25VVTT= 1.25V

VCCO = 2.5V

VREF= 1.5V

VTT = 1.5V

50Ω

VCCO = 3.3V

Z = 50

CTT

x133_17_111699

Table 32: CTT Voltage Specifications

Parameter Min Typ Max

VCCO 2.05(1) 3.3 3.6

VREF 1.35 1.5 1.65

VTT 1.35 1.5 1.65

VIH = VREF + 0.2 1.55 1.7 -

VIL = VREF – 0.2 - 1.3 1.45

VOH = VREF + 0.4 1.75 1.9 -

VOL= VREF – 0.4 - 1.1 1.25

IOH at VOH (mA) −8--

IOLat VOL (mA) 8 - -

Notes:

1. Timing delays are calculated based on VCCO min of 3.0V.

Table 33: PCI33_3 and PCI66_3 Voltage

Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF -- -

VTT -- -

VIH = 0.5 × VCCO 1.5 1.65 VCCO+ 0.5

VIL = 0.3 × VCCO −0.5 0.99 1.08

VOH = 0.9 × VCCO 2.7 - -

VOL= 0.1 × VCCO - - 0.36

IOH at VOH (mA) Note 1 - -

IOLat VOL (mA) Note 1 - -

Note 1: Tested according to the relevant specification.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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44 1-800-255-7778

LVTTL

LVTTL requires no termination. DC voltage specifications

appears in Table 34.

LV CM O S 2

LVCMOS2 requires no termination. DC voltage specifica-

tions appear in Ta bl e 3 5.

LV C M O S1 8

LVCMOS18 does not require termination. Ta bl e 3 6 lists DC

voltage specifications.

AGP-2X

The specification for the AGP-2X standard does not docu-

ment a recommended termination technique. DC voltage

specifications appear in Ta b l e 3 7 .

Table 34: LVTTL Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF ---

VTT -- -

VIH 2.0 - 3.6

VIL −0.5 - 0.8

VOH 2.4 - -

VOL --0.4

IOH at VOH (mA) −24 - -

IOLat VOL (mA) 24 - -

Note: VOLand VOH for lower drive currents sample tested.

Table 35: LVCMOS2 Voltage Specifications

Parameter Min Typ Max

VCCO 2.3 2.5 2.7

VREF ---

VTT -- -

VIH 1.7 - 3.6

VIL −0.5 - 0.7

VOH 1.9 - -

VOL --0.4

IOH at VOH (mA) −12 - -

IOLat VOL (mA) 12 - -

Table 36: LVCMOS18 Voltage Specifications

Parameter Min Typ Max

VCCO 1.70 1.80 1.90

VREF ---

VTT ---

VIH 0.65 x VCCO -1.95

VIL – 0.5 - 0.2 x VCCO

VOH VCCO – 0.4 - -

VOL --0.4

IOH at VOH (mA) –8- -

IOLat VOL (mA) 8 - -

Table 37: AGP-2X Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF = N × VCCO(1) 1.17 1.32 1.48

VTT ---

VIH = VREF + 0.2 1.37 1.52 -

VIL = VREF – 0.2 - 1.12 1.28

VOH = 0.9 × VCCO 2.7 3.0 -

VOL = 0.1 × VCCO - 0.33 0.36

IOH at VOH (mA) Note 2 - -

IOLat VOL (mA) Note 2 - -

Notes:

1. N must be greater than or equal to 0.39 and less than or

equal to 0.41.

2. Tested according to the relevant specification.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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1-800-255-7778 45

LVDS

Depending on whether the device is transmitting an LVDS

signal or receiving an LVDS signal, there are two different

circuits used for LVDS termination. A sample circuit illustrat-

ing a valid termination technique for transmitting LVDS sig-

nals appears in Figure 54. A sample circuit illustrating a

valid termination for receiving LVDS signals appears in

Figure 55. Ta bl e 3 8 lists DC voltage specifications. Further

information on the specific termination resistor packs shown

can be found on Table 40.

LV P E CL

Depending on whether the device is transmitting or receiv-

ing an LVPECL signal, two different circuits are used for

LVPECL termination. A sample circuit illustrating a valid ter-

mination technique for transmitting LVPECL signals

appears in Figure 56. A sample circuit illustrating a valid ter-

mination for receiving LVPECL signals appears in

Figure 57. Ta bl e 3 9 lists DC voltage specifications. Further

information on the specific termination resistor packs shown

can be found on Table 40.

Figure 54: Transmitting LVDS Signal Circuit

Figure 55: Receiving LVDS Signal Circuit

Table 38: LVDS Voltage Specifications

Parameter Min Typ Max

VCCO 2.375 2.5 2.625

VICM(2) 0.2 1.25 2.2

VOCM(1) 1.125 1.25 1.375

VIDIFF (1) 0.1 0.35 -

VODIFF (1) 0.25 0.35 0.45

VOH(1) 1.25 - -

VOL(1) --1.25

Notes:

1. Measured with a 100 Ω resistor across Q and Q.

2. Measured with a differential input voltage = +/− 350 mV.

x133_19_122799

QZ0 = 50Ω

Z0 = 50Ω

Virtex-E

FPGA

to LVDS Receiver

RDIV

140

165

2.5V

VCCO = 2.5V

LVDS

Output

DATA

Transmit

1/4 of Bourns

Part Number

CAT16-LV4F12

x133_29_122799

QZ0 = 50ΩLVDS_IN

LVDS_IN

Z0 = 50Ω

100Ω

DATA

Receive

from

LVDS

Driver

VIRTEX-E

FPGA

–

Figure 56: Transmitting LVPECL Signal Circuit

Figure 57: Receiving LVPECL Signal Circuit

Table 39: LVPECL Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF -- -

VTT -- -

VIH 1.49 - 2.72

VIL 0.86 - 2.125

VOH 1.8 - -

VOL - - 1.57

Note: For more detailed information, see LVPECL DC

Specifications

x133_20_122799

QZ0 = 50ΩLVPECL_OUT

LVPECL_OUT

Z0 = 50Ω

Virtex-E

FPGA

to LVPECL Receiver

RDIV

187

100

3.3V

DATA

Transmit

1/4 of Bourns

Part Number

CAT16-PC4F12

x133_21_122799

QZ0 = 50Ω

LVPECL_IN

Z0 = 50Ω

100Ω

DATA

Receive

from

LVPECL

Driver

VIRTEX-E

FPGA

–

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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46 1-800-255-7778

Termination Resistor Packs

Resistor packs are available with the values and the config-

uration required for LVDS and LVPECL termination from

Bourns, Inc., as listed in Table. For pricing and availability,

please contact Bourns directly at www.bourns.com.

LVDS Design Guide

The SelectI/O library elements have been expanded for Vir-

tex-E devices to include new LVDS variants. At this time all

of the cells might not be included in the Synthesis libraries.

The 2.1i-Service Pack 2 update for Alliance and Foundation

software includes these cells in the VHDL and Verilog librar-

ies. It is necessary to combine these cells to create the

P-side (positive) and N-side (negative) as described in the

input, output, 3-state and bidirectional sections.

Creating LVDS Global Clock Input Buffers

The global clock input buffer can be combined with the adja-

cent IOB to form an LVDS clock input buffer. The P-side

resides in the GCLKPAD location and the N-side resides in

the adjacent IO_LVDS_DLL site.

HDL Instantiation

Only one global clock input buffer is required to be instanti-

ated in the design and placed on the correct GCLKPAD

location. The N-side of the buffer is reserved and no other

IOB is allowed to be placed on this location.

In the physical device, a configuration option is enabled that

routes the pad wire to the differential input buffer located in

the GCLKIOB. The output of this buffer then drives the out-

put of the GCLKIOB cell. In EPIC it appears that the second

buffer is unused. Any attempt to use this location for another

purpose leads to a DRC error in the software.

VHDL Instantiation

gclk0_p : IBUFG_LVDS port map

(I=>clk_external, O=>clk_internal);

Verilog Instantiation

IBUFG_LVDS gclk0_p (.I(clk_external),

.O(clk_internal));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the global clock input buffers this can be done with the fol-

lowing constraint in the UCF or NCF file.

NET clk_external LOC = GCLKPAD3;

GCLKPAD3 can also be replaced with the package pin

name, such as D17 for the BG432 package.

Optional N-Side

Some designers might prefer to also instantiate the N-side

buffer for the global clock buffer. This allows the top-level net

list to include net connections for both PCB layout and sys-

tem-level integration. In this case, only the output P-side

IBUFG connection has a net connected to it. Since the

N-side IBUFG does not have a connection in the EDIF net

list, it is trimmed from the design in MAP.

VHDL Instantiation

gclk0_p : IBUFG_LVDS port map

(I=>clk_p_external, O=>clk_internal);

gclk0_n : IBUFG_LVDS port map

(I=>clk_n_external, O=>clk_internal);

Verilog Instantiation

IBUFG_LVDS gclk0_p (.I(clk_p_external),

.O(clk_internal));

IBUFG_LVDS gclk0_n (.I(clk_n_external),

.O(clk_internal));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the global clock input buffers this can be done with the fol-

lowing constraint in the UCF or NCF file.

NET clk_p_external LOC = GCLKPAD3;

NET clk_n_external LOC = C17;

Table 40: Bourns LVDS/LVPECL Resistor Packs

Part Number I/O Standard

Term.

for:

Pairs/

Pack Pins

CAT16−LV2 F6 LVDS Driver 2 8

CAT16−LV4 F12 LVDS Driver 4 16

CAT16−PC2F6 LVPECL Driver 2 8

CAT16−PC4F12 LVPECL Driver 4 16

CAT16−PT2F2 LVDS/LVPECL Receiver 2 8

CAT16−PT4F4 LVDS/LVPECL Receiver 4 16

Figure 58: LV DS E le m ents

Table 41: Global Clock Input Buffer Pair Locations

Pkg

Pair 3 Pair 2 Pair 2 Pair 0

PNPNPNPN

BG560 A17 C18 D17 E17 AJ17 AM18 AL17 AM17

FG676 E13 B13 C13 F14 AB13 AF13 AA14 AC14

FG900C15A15E15E16AK16AH16 AJ16 AF16

IBUF_LVDS

OBUF_LVDS IOBUF_LVDS

OBUFT_LVDS

IBUFG_LVDS

x133_22_122299

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1-800-255-7778 47

GCLKPAD3 can also be replaced with the package pin

name, such as D17 for the BG432 package.

Creating LVDS Input Buffers

An LVDS input buffer can be placed in a wide number of IOB

locations. The exact location is dependent on the package

that is used. The Virtex-E package information lists the pos-

sible locations as IO_L#P for the P-side and IO_L#N for the

N-side where # is the pair number.

HDL Instantiation

Only one input buffer is required to be instantiated in the

design and placed on the correct IO_L#P location. The

N-side of the buffer is reserved and no other IOB is allowed

to be placed on this location. In the physical device, a con-

figuration option is enabled that routes the pad wire from the

IO_L#N IOB to the differential input buffer located in the

IO_L#P IOB. The output of this buffer then drives the output

of the IO_L#P cell or the input register in the IO_L#P IOB. In

EPIC it appears that the second buffer is unused. Any

attempt to use this location for another purpose leads to a

DRC error in the software.

VHDL Instantiation

data0_p : IBUF_LVDS port map (I=>data(0),

O=>data_int(0));

Verilog Instantiation

IBUF_LVDS data0_p (.I(data[0]),

.O(data_int[0]));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the input buffers this can be done with the following con-

straint in the UCF or NCF file.

NET data<0> LOC = D28; # IO_L0P

Optional N-side

Some designers might prefer to also instantiate the N-side

buffer for the input buffer. This allows the top-level net list to

include net connections for both PCB layout and sys-

tem-level integration. In this case, only the output P-side

IBUF connection has a net connected to it. Since the N-side

IBUF does not have a connection in the EDIF net list, it is

trimmed from the design in MAP.

VHDL Instantiation

data0_p : IBUF_LVDS port map

(I=>data_p(0), O=>data_int(0));

data0_n : IBUF_LVDS port map

(I=>data_n(0), O=>open);

Verilog Instantiation

IBUF_LVDS data0_p (.I(data_p[0]),

.O(data_int[0]));

IBUF_LVDS data0_n (.I(data_n[0]), .O());

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the global clock input buffers this can be done with the fol-

lowing constraint in the UCF or NCF file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Adding an Input Register

All LVDS buffers can have an input register in the IOB. The

input register is in the P-side IOB only. All the normal IOB

FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,

LDP, LDPE). The register elements can be inferred or

explicitly instantiated in the HDL code.

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using “map -pr

[i|o|b]”, where “i” is inputs only, “o” is outputs only, and “b” is

both inputs and outputs.

To improve design coding times VHDL and Verilog synthe-

sis macro libraries available to explicitly create these struc-

tures. The input library macros are listed in Table 42. The I

and IB inputs to the macros are the external net connec-

tions.

Table 42: Input Library Macros

Name Inputs Outputs

IBUFDS_FD_LVDS I, IB, C Q

IBUFDS_FDE_LVDS I, IB, CE, C Q

IBUFDS_FDC_LVDS I, IB, C, CLR Q

IBUFDS_FDCE_LVDS I, IB, CE, C, CLR Q

IBUFDS_FDP_LVDS I, IB, C, PRE Q

IBUFDS_FDPE_LVDS I, IB, CE, C, PRE Q

IBUFDS_FDR_LVDS I, IB, C, R Q

IBUFDS_FDRE_LVDS I, IB, CE, C, R Q

IBUFDS_FDS_LVDS I, IB, C, S Q

IBUFDS_FDSE_LVDS I, IB, CE, C, S Q

IBUFDS_LD_LVDS I, IB, G Q

IBUFDS_LDE_LVDS I, IB, GE, G Q

IBUFDS_LDC_LVDS I, IB, G, CLR Q

IBUFDS_LDCE_LVDS I, IB, GE, G, CLR Q

IBUFDS_LDP_LVDS I, IB, G, PRE Q

IBUFDS_LDPE_LVDS I, IB, GE, G, PRE Q

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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48 1-800-255-7778

Creating LVDS Output Buffers

LVDS output buffer can be placed in wide number of IOB

locations. The exact location are dependent on the package

that is used. The Virtex-E package information lists the pos-

sible locations as IO_L#P for the P-side and IO_L#N for the

N-side where # is the pair number.

HDL Instantiation

Both output buffers are required to be instantiated in the

design and placed on the correct IO_L#P and IO_L#N loca-

tions. The IOB must have the same net source the following

pins, clock (C), set/reset (SR), output (O), output clock

enable (OCE). In addition, the output (O) pins must be

inverted with respect to each other, and if output registers

are used, the INIT states must be opposite values (one

HIGH and one LOW). Failure to follow these rules leads to

DRC errors in software.

VHDL Instantiation

data0_p : OBUF_LVDS port map

(I=>data_int(0), O=>data_p(0));

data0_inv: INV port map

(I=>data_int(0), O=>data_n_int(0));

data0_n : OBUF_LVDS port map

(I=>data_n_int(0), O=>data_n(0));

Verilog Instantiation

OBUF_LVDS data0_p (.I(data_int[0]),

.O(data_p[0]));

INV data0_inv (.I(data_int[0],

.O(data_n_int[0]);

OBUF_LVDS data0_n (.I(data_n_int[0]),

.O(data_n[0]));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the output buffers this can be done with the following con-

straint in the UCF or NCF file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous Outputs

If the outputs are synchronous (registered in the IOB), then

any IO_L#P|N pair can be used. If the outputs are asynchro-

nous (no output register), then they must use one of the

pairs that are part of the same IOB group at the end of a

ROW or at the top/bottom of a COLUMN in the device.

The LVDS pairs that can be used as asynchronous outputs

are listed in the Virtex-E pinout tables. Some pairs are

marked as asynchronous-capable for all devices in that

package, and others are marked as available only for that

device in the package. If the device size might change at

some point in the product lifetime, then only the common

pairs for all packages should be used.

Adding an Output Register

All LVDS buffers can have an output register in the IOB. The

output registers must be in both the P-side and N-side IOBs.

All the normal IOB register options are available (FD, FDE,

FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,

LDE, LDC, LDCE, LDP, LDPE). The register elements can

be inferred or explicitly instantiated in the HDL code.

Special care must be taken to insure that the D pins of the

registers are inverted and that the INIT states of the regis-

ters are opposite. The clock pin (C), clock enable (CE) and

set/reset (CLR/PRE or S/R) pins must connect to the same

source. Failure to do this leads to a DRC error in the soft-

ware.

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using the “map

-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”

is both inputs and outputs.

To improve design coding times VHDL and Verilog synthe-

sis macro libraries have been developed to explicitly create

these structures. The output library macros are listed in

Ta ble 43 . The O and OB inputs to the macros are the exter-

nal net connections.

Table 43: Output Library Macros

Name Inputs Outputs

OBUFDS_FD_LVDS D, C O, OB

OBUFDS_FDE_LVDS DD, CE, C O, OB

OBUFDS_FDC_LVDS D, C, CLR O, OB

OBUFDS_FDCE_LVDS D, CE, C, CLR O, OB

OBUFDS_FDP_LVDS D, C, PRE O, OB

OBUFDS_FDPE_LVDS D, CE, C, PRE O, OB

OBUFDS_FDR_LVDS D, C, R O, OB

OBUFDS_FDRE_LVDS D, CE, C, R O, OB

OBUFDS_FDS_LVDS D, C, S O, OB

OBUFDS_FDSE_LVDS D, CE, C, S O, OB

OBUFDS_LD_LVDS D, G O, OB

OBUFDS_LDE_LVDS D, GE, G O, OB

OBUFDS_LDC_LVDS D, G, CLR O, OB

OBUFDS_LDCE_LVDS D, GE, G, CLR O, OB

OBUFDS_LDP_LVDS D, G, PRE O, OB

OBUFDS_LDPE_LVDS D, GE, G, PRE O, OB

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1-800-255-7778 49

Creating LVDS Output 3-State Buffers

LVDS output 3-state buffers can be placed in a wide number

of IOB locations. The exact locations are dependent on the

package used. The Virtex-E package information lists the

possible locations as IO_L#P for the P-side and IO_L#N for

the N-side, where # is the pair number.

HDL Instantiation

Both output 3-state buffers are required to be instantiated in

the design and placed on the correct IO_L#P and IO_L#N

locations. The IOB must have the same net source the fol-

lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state

clock enable (TCE), output (O), output clock enable (OCE).

In addition, the output (O) pins must be inverted with

respect to each other, and if output registers are used, the

INIT states must be opposite values (one High and one

Low). If 3-state registers are used, they must be initialized to

the same state. Failure to follow these rules leads to DRC

errors in the software.

VHDL Instantiation

data0_p: OBUFT_LVDS port map

(I=>data_int(0), T=>data_tri,

O=>data_p(0));

data0_inv: INV port map

(I=>data_int(0), O=>data_n_int(0));

data0_n: OBUFT_LVDS port map

(I=>data_n_int(0), T=>data_tri,

O=>data_n(0));

Verilog Instantiation

OBUFT_LVDS data0_p (.I(data_int[0]),

.T(data_tri), .O(data_p[0]));

INV data0_inv (.I(data_int[0],

.O(data_n_int[0]);

OBUFT_LVDS data0_n (.I(data_n_int[0]),

.T(data_tri), .O(data_n[0]));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the output buffers this can be done with the following con-

straint in the UCF or NCF file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous 3-State Outputs

If the outputs are synchronous (registered in the IOB), then

any IO_L#P|N pair can be used. If the outputs are asynchro-

nous (no output register), then they must use one of the

pairs that are part of the same IOB group at the end of a

ROW or at the top/bottom of a COLUMN in the device. This

applies for either the 3-state pin or the data out pin.

LVDS pairs that can be used as asynchronous outputs are

listed in the Virtex-E pinout tables. Some pairs are marked

as “asynchronous capable” for all devices in that package,

and others are marked as available only for that device in

the package. If the device size might be changed at some

point in the product lifetime, then only the common pairs for

all packages should be used.

Adding Output and 3-State Registers

All LVDS buffers can have an output register in the IOB. The

output registers must be in both the P-side and N-side IOBs.

All the normal IOB register options are available (FD, FDE,

FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,

LDE, LDC, LDCE, LDP, LDPE). The register elements can

be inferred or explicitly instantiated in the HDL code.

Special care must be taken to insure that the D pins of the

registers are inverted and that the INIT states of the regis-

ters are opposite. The 3-state (T), 3-state clock enable

(CE), clock pin (C), output clock enable (CE) and set/reset

(CLR/PRE or S/R) pins must connect to the same source.

Failure to do this leads to a DRC error in the software.

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using the “map

-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”

is both inputs and outputs.

To improve design coding times VHDL and Verilog synthe-

sis macro libraries have been developed to explicitly create

these structures. The input library macros are listed below.

The 3-state is configured to be 3-stated at GSR and when

the PRE,CLR,S or R is asserted and shares it's clock

enable with the output register. If this is not desirable, the

library can be updated by the user for the desired function-

ality. The O and OB inputs to the macros are the external

net connections.

Creating LVDS Bidirectional Buffer

LVDS bidirectional buffers can be placed in a wide number

of IOB locations. The exact locations are dependent on the

package used. The Virtex-E package information lists the

possible locations as IO_L#P for the P-side and IO_L#N for

the N-side, where # is the pair number.

HDL Instantiation

Both bidirectional buffers are required to be instantiated in

the design and placed on the correct IO_L#P and IO_L#N

locations. The IOB must have the same net source the fol-

lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state

clock enable (TCE), output (O), output clock enable (OCE).

In addition, the output (O) pins must be inverted with

respect to each other, and if output registers are used, the

INIT states must be opposite values (one HIGH and one

LOW). If 3-state registers are used, they must be initialized

to the same state. Failure to follow these rules leads to DRC

errors in the software.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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50 1-800-255-7778

VHDL Instantiation

data0_p: IOBUF_LVDS port map

(I=>data_out(0), T=>data_tri,

IO=>data_p(0), O=>data_int(0));

data0_inv: INV port map

(I=>data_out(0), O=>data_n_out(0));

data0_n : IOBUF_LVDS port map

(I=>data_n_out(0), T=>data_tri,

IO=>data_n(0), O=>open);

Verilog Instantiation

IOBUF_LVDS data0_p(.I(data_out[0]),

.T(data_tri), .IO(data_p[0]),

.O(data_int[0]);

INV data0_inv (.I(data_out[0],

.O(data_n_out[0]);

IOBUF_LVDS

data0_n(.I(data_n_out[0]),.T(data_tri),.

IO(data_n[0]).O());

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the output buffers this can be done with the following con-

straint in the UCF or NCF file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous Bidirectional

Buffers

If the output side of the bidirectional buffers are synchro-

nous (registered in the IOB), then any IO_L#P|N pair can be

used. If the output side of the bidirectional buffers are asyn-

chronous (no output register), then they must use one of the

pairs that is a part of the asynchronous LVDS IOB group.

This applies for either the 3-state pin or the data out pin.

The LVDS pairs that can be used as asynchronous bidirec-

tional buffers are listed in the Virtex-E pinout tables. Some

pairs are marked as asynchronous capable for all devices in

that package, and others are marked as available only for

that device in the package. If the device size might change

at some point in the product’s lifetime, then only the com-

mon pairs for all packages should be used.

Adding Output and 3-State Registers

All LVDS buffers can have output and input registers in the

IOB. The output registers must be in both the P-side and

N-side IOBs, the input register is only in the P-side. All the

normal IOB register options are available (FD, FDE, FDC,

FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE,

LDC, LDCE, LDP, LDPE). The register elements can be

inferred or explicitly instantiated in the HDL code. Special

care must be taken to insure that the D pins of the registers

are inverted and that the INIT states of the registers are

opposite. The 3-state (T), 3-state clock enable (CE), clock

pin (C), output clock enable (CE), and set/reset (CLR/PRE

or S/R) pins must connect to the same source. Failure to do

this leads to a DRC error in the software.

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using the “map

-pr [i|o|b]”, where “i” is inputs only, “o” is outputs only, and “b”

is both inputs and outputs. To improve design coding times,

VHDL and Verilog synthesis macro libraries have been

developed to explicitly create these structures. The bidirec-

tional I/O library macros are listed in Ta bl e 4 4 .

The 3-state is configured to be 3-stated at GSR and when

the PRE, CLR, S, or R is asserted and shares its clock

enable with the output and input register. If this is not desir-

able, then the library can be updated with the desired func-

tionality by the user. The I/O and IOB inputs to the macros

are the external net connections.

Table 44: Bidirectional I/O Library Macros

Name Inputs Bidirectional Outputs

IOBUFDS_FD_LVDS D, T, C IO, IOB Q

IOBUFDS_FDE_LVDS D, T, CE, C IO, IOB Q

IOBUFDS_FDC_LVDS D, T, C, CLR IO, IOB Q

IOBUFDS_FDCE_LVDS D, T, CE, C, CLR IO, IOB Q

IOBUFDS_FDP_LVDS D, T, C, PRE IO, IOB Q

IOBUFDS_FDPE_LVDS D, T, CE, C, PRE IO, IOB Q

IOBUFDS_FDR_LVDS D, T, C, R IO, IOB Q

IOBUFDS_FDRE_LVDS D, T, CE, C, R IO, IOB Q

IOBUFDS_FDS_LVDS D, T, C, S IO, IOB Q

IOBUFDS_FDSE_LVDS D, T, CE, C, S IO, IOB Q

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1-800-255-7778 51
R
Revision History
The following table shows the revision history for this document.  
IOBUFDS_LD_LVDS D, T, G IO, IOB Q
IOBUFDS_LDE_LVDS D, T, GE, G IO, IOB Q
IOBUFDS_LDC_LVDS D, T, G, CLR IO, IOB Q
IOBUFDS_LDCE_LVDS D, T, GE, G, CLR IO, IOB Q
IOBUFDS_LDP_LVDS D, T, G, PRE IO, IOB Q
IOBUFDS_LDPE_LVDS D, T, GE, G, PRE IO, IOB Q
Date Version Revision
03/23/00 1.0 Initial Xilinx release.
08/01/00 1.1 Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added. 
Reformatted to adhere to corporate documentation style guidelines. Minor changes in 
BG560 pin-out table.
09/19/00 1.2 •In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no 
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1. 
•Min values added to Virtex-E Electrical Characteristics tables.
11/20/00 1.3 •Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables 
(Module 3).
•Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
•Added to note 2 of Absolute Maximum Ratings (Module 3).
•Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL 
Standard, with DLL (Module 3).
•Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).
04/02/01 1.4 •In Ta b le 4 , FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF, 
and pin G16 is now labeled as VREF. 
•Updated values in Virtex-E Switching Characteristics tables. 
•Converted data sheet to modularized format.
04/19/01 1.5 •Modified Figure 30, which shows “DLL Generation of 4x Clock in Virtex-E Devices.”
07/23/01 1.6 •Made minor edits to text under Configuration.
11/16/01 2.0 •Added warning under Configuration section that attempting to load an incorrect 
bitstream causes configuration to fail and can damage the device.
07/17/02 2.1 •Data sheet designation upgraded from Preliminary to Production.
09/10/02 2.2 •Added clarifications in the Input/Output Block, Configuration, Boundary-Scan Mode, 
and Block SelectRAM+ Memory sections. Revised Figure 18, Table 11, and Ta b l e 3 6 .
11/19/02 2.3 •Added clarification in the Boundary Scan section.
•Removed last sentence regarding deactivation of duty-cycle correction in Duty Cycle 
Correction Property section.
Table  44:  Bidirectional I/O Library Macros  (Continued)
Name Inputs Bidirectional Outputs

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52 1-800-255-7778

Virtex-E Extended Memory Data Sheet

The Virtex-E Extended Memory Data Sheet contains the following modules:

•DS025-1, Virtex-E 1.8V Extended Memory FPGAs:

Introduction and Ordering Information (Module 1)

•DS025-2, Virtex-E 1.8V Extended Memory FPGAs:

Functional Description (Module 2)

•DS025-3, Virtex-E 1.8V Extended Memory FPGAs:

DC and Switching Characteristics (Module 3)

•DS025-4, Virtex-E 1.8V Extended Memory FPGAs:

Pinout Tables (Module 4)

DS025-3 (v2.3.2) March 14, 2003 www.xilinx.com Module 3 of 4

1-800-255-7778 1

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Virtex-E Extended Memory Electrical Characteristics

Definition of Terms

Electrical and switching characteristics are specified on a

per-speed-grade basis and can be designated as Advance,

Preliminary, or Production. Each designation is defined as

follows:

Advance: These speed files are based on simulations only

and are typically available soon after device design specifi-

cations are frozen. Although speed grades with this desig-

nation are considered relatively stable and conservative,

some under-reporting might still occur.

Preliminary: These speed files are based on complete ES

(engineering sample) silicon characterization. Devices and

speed grades with this designation are intended to give a

better indication of the expected performance of production

silicon. The probability of under-reporting delays is greatly

reduced as compared to Advance data.

Production: These speed files are released once enough

production silicon of a particular device family member has

been characterized to provide full correlation between

speed files and devices over numerous production lots.

There is no under-reporting of delays, and customers

receive formal notification of any subsequent changes. Typ-

ically, the slowest speed grades transition to Production

before faster speed grades.

All specifications are representative of worst-case supply

voltage and junction temperature conditions. The parame-

ters included are common to popular designs and typical

applications. Contact the factory for design considerations

requiring more detailed information.

Ta ble 1 correlates the current status of each Virtex-E

Extended Memory device with a corresponding speed file

designation.

All specifications are subject to change without notice.

DC Characteristics

Absolute Maximum Ratings

Virtex™-E 1.8 V Extended Memory

Field Programmable Gate Arrays

DS025-3 (v2.3.2) March 14, 2003 00Production Product Specification

Table 1 : Virtex-E Extended Memory Device

Speed Grade Designations

Device

Speed Grade Designations

Advance Preliminary Production

XCV405E –8, –7, –6

XCV812E –8, –7, –6

Symbol Description(1) Units

VCCINT Internal Supply voltage relative to GND –0.5 to 2.0 V

VCCO Supply voltage relative to GND –0.5 to 4.0 V

VREF Input Reference Voltage –0.5 to 4.0 V

VIN (3) Input voltage relative to GND –0.5 to VCCO +0.5 V

VTS Voltage applied to 3-state output –0.5 to 4.0 V

VCC Longest Supply Voltage Rise Time from 0 V – 1.71 V 50 ms

TSTG Storage temperature (ambient) –65 to +150 °C

TJJunction temperature (2) Plastic packages +125 °C

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.

2. For soldering guidelines and thermal considerations, see the device packaging information on www.xilinx.com.

3. Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the

device is not PCI compliant.

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2 1-800-255-7778

Recommended Operating Conditions

DC Characteristics Over Recommended Operating Conditions

Power-On Power Supply Requirements

Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual

current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal

power supply voltage of the device1 from 0 V. The fastest ramp rate is 0 V to nominal voltage in 2 ms and the slowest allowed

ramp rate is 0 V to nominal voltage in 50 ms. For more details on power supply requirements, see XAPP158 on

www.xilinx.com.

Symbol Description Min Max Units

VCCINT Internal Supply voltage relative to GND, TJ = 0 °C to +85°C Commercial 1.8 – 5% 1.8 + 5% V

Internal Supply voltage relative to GND, TJ = –40°C to +100°C Industrial 1.8 – 5% 1.8 + 5% V

VCCO Supply voltage relative to GND, TJ = 0 °C to +85°C Commercial 1.2 3.6 V

Supply voltage relative to GND, TJ = –40°C to +100°C Industrial 1.2 3.6 V

TIN Input signal transition time 250 ns

Symbol Description(1) Device Min Max Units

VDRINT

Data Retention VCCINT Vo lta ge

(below which configuration data might be lost) All 1.5 V

VDRIO

Data Retention VCCO Voltage

(below which configuration data might be lost) All 1.2 V

ICCINTQ Quiescent VCCINT supply current1XCV405E 400 mA

XCV812E 500 mA

ICCOQ Quiescent VCCO supply current1XCV405E 2 mA

XCV812E 2 mA

ILInput or output leakage current All –10 +10 µA

CIN Input capacitance (sample tested) BGA, PQ, HQ, packages All 8 pF

IRPU Pad pull-up (when selected) @ Vin = 0 V, VCCO = 3.3 V (sample tested) All Note 2 0.25 mA

IRPD Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) Note 2 0.25 mA

Notes:

1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.

2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors

do not guarantee valid logic levels when input pins are connected to other circuits.

Product (Commercial Grade) Description(2) Current Requirement(3)

XCV50E - XCV600E Minimum required current supply 500 mA

XCV812E - XCV2000E Minimum required current supply 1 A

XCV2600E - XCV3200E Minimum required current supply 1.2 A

Virtex-E Family, Industrial Grade Minimum required current supply 2 A

Notes:

1. Ramp rate used for this specification is from 0 - 1.8 V DC. Peak current occurs on or near the internal power-on reset threshold and

lasts for less than 3 ms.

2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.

3. Larger currents might result if ramp rates are forced to be faster.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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1-800-255-7778 3

DC Input and Output Levels

Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended

operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that

all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and

VOH voltage levels shown. Other standards are sample tested.

Input/Output

Standard

VIL VIH VOL VOH IOL IOH

V, min V, max V, min V, max V, Max V, Min mA mA

LV T T L (1) – 0.5 0.8 2.0 3.6 0.4 2.4 24 – 24

LV C M O S 2 – 0.5 0.7 1.7 2.7 0.4 1.9 12 – 12

LV C M O S 18 – 0.5 20% VCCO 70% VCCO 1.95 0.4 VCCO – 0.4 8 – 8

PCI, 3.3 V – 0.5 30% VCCO 50% VCCO VCCO + 0.5 10% VCCO 90% VCCO Note 2 Note 2

GTL – 0.5 VREF – 0.05 VREF + 0.05 3.6 0.4 n/a 40 n/a

GTL+ – 0.5 VREF – 0.1 VREF + 0.1 3.6 0.6 n/a 36 n/a

HSTL I(3) – 0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 8 –8

HSTL III – 0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 24 –8

HSTL IV – 0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 48 –8

SSTL3 I – 0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.6 VREF + 0.6 8 –8

SSTL3 II – 0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 16 –16

SSTL2 I – 0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.61 VREF + 0.61 7.6 –7.6

SSTL2 II – 0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.80 VREF + 0.80 15.2 –15.2

CTT – 0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.4 VREF + 0.4 8 –8

AGP – 0.5 VREF – 0.2 VREF + 0.2 3.6 10% VCCO 90% VCCO Note 2 Note 2

Notes:

1. VOL and VOH for lower drive currents are sample tested.

2. Tested according to the relevant specifications.

3. DC input and output levels for HSTL18 (HSTL I/O standard with VCCO of 1.8 V) are provided in an HSTL white paper on

www.xilinx.com.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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LVDS DC Specifications

LVPECL DC Specifications

These values are valid at the output of the source termination pack shown under LV PE C L , with a 100 Ω differential load only.

The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode

ranges. The following table summarizes the DC output specifications of LVPECL.

DC Parameter Symbol Conditions Min Typ Max Units

Supply Voltage VCCO 2.375 2.5 2.625 V

Output High Voltage for Q and Q VOH RT = 100 Ω across Q and Q signals 1.25 1.425 1.6 V

Output Low Voltage for Q and Q VOL RT = 100 Ω across Q and Q signals 0.9 1.075 1.25 V

Differential Output Voltage (Q – Q),

Q = High (Q – Q), Q = High

VODIFF RT = 100 Ω across Q and Q signals 250 350 450 mV

Output Common-Mode Voltage VOCM RT = 100 Ω across Q and Q signals 1.125 1.25 1.375 V

Differential Input Voltage (Q – Q),

Q = High (Q – Q), Q = High

VIDIFF Common-mode input voltage = 1.25 V 100 350 NA mV

Input Common-Mode Voltage VICM Differential input voltage = ±350 mV 0.2 1.25 2.2 V

Notes:

1. Refer to the Design Consideration section for termination schematics.

DC Parameter Min Max Min Max Min Max Units

VCCO 3.0 3.3 3.6 V

VOH 1.8 2.11 1.92 2.28 2.13 2.41 V

VOL 0.96 1.27 1.06 1.43 1.30 1.57 V

VIH 1.49 2.72 1.49 2.72 1.49 2.72 V

VIL 0.86 2.125 0.86 2.125 0.86 2.125 V

Differential Input Voltage 0.3 - 0.3 - 0.3 - V

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Virtex-E Switching Characteristics

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed

below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported

by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All

timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all

Virtex-E devices unless otherwise noted.

IOB Input Switching Characteristics

Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values

shown in ‘‘IOB Input Switching Characteristics Standard Adjustments’’ on page 6.

Speed Grade(2)

UnitsDescription(1) Symbol Device Min -8 -7 -6

Propagation Delays

Pad to I output, no delay TIOPI All 0.43 0.8 0.8 0.8 ns, max

Pad to I output, with delay TIOPID

XCV405E 0.51 1.0 1.0 1.0 ns, max

XCV812E 0.55 1.1 1.1 1.1 ns, max

Pad to output IQ via transparent latch,

no delay TIOPLI All 0.75 1.4 1.5 1.6 ns, max

Pad to output IQ via transparent latch,

with delay TIOPLID

XCV405E 1.55 3.5 3.6 3.7 ns, max

XCV812E 1.55 3.5 3.6 3.7 ns, max

Propagation Delays

Clock

Minimum Pulse Width, High TCH All 0.56 1.2 1.3 1.4 ns, min

Minimum Pulse Width, Low TCL 0.56 1.2 1.3 1.4 ns, min

Clock CLK to output IQ TIOCKIQ 0.18 0.4 0.7 0.7 ns, max

Setup and Hold Times with respect to Clock at IOB Input Register

Pad, no delay TIOPICK /

TIOICKP

All 0.69 / 0 1.3 / 0 1.4 / 0 1.5 / 0 ns, min

Pad, with delay TIOPICKD /

TIOICKPD

XCV405E 1.49 / 0 3.4 / 0 3.5 / 0 3.5 / 0 ns, min

XCV812E 1.49 / 0 3.4 / 0 3.5 / 0 3.5 / 0 ns, min

ICE input TIOICECK /

TIOCKICE

All 0.28 /

0.0

0.55 /

0.01

0.7 /

0.01

0.7 /

0.01

ns, min

SR input (IFF, synchronous) TIOSRCKI All 0.38 0.8 0.9 1.0 ns, min

Set/Reset Delays

SR input to IQ (asynchronous) TIOSRIQ All 0.54 1.1 1.2 1.4 ns, max

GSR to output IQ TGSRQ All 3.88 7.6 8.5 9.7 ns, max

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

2. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.

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IOB Input Switching Characteristics Standard Adjustments

Speed Grade(1)

UnitsDescription Symbol Standard Min -8 -7 -6

Data Input Delay Adjustments

Standard-specific data input delay

adjustments

TILVTTL LVTTL 0.0 0.0 0.0 0.0 ns

TILVCMOS2 LVC MOS2 –0.02 0.0 0.0 0.0 ns

TILVCMOS18 LVCM OS 18 –0.02 +0.20 +0.20 +0.20 ns

TILVDS LVDS 0.00 +0.15 +0.15 +0.15 ns

TILVPECL LVPECL 0.00 +0.15 +0.15 +0.15 ns

TIPCI33_3 PCI, 33 MHz, 3.3 V –0.05 +0.08 +0.08 +0.08 ns

TIPCI66_3 PCI, 66 MHz, 3.3 V –0.05 –0.11 –0.11 –0.11 ns

TIGTL GTL +0.10 +0.14 +0.14 +0.14 ns

TIGTLPLUS GTL+ +0.06 +0.14 +0.14 +0.14 ns

TIHSTL HSTL +0.02 +0.04 +0.04 +0.04 ns

TISSTL2 SSTL2 –0.04 +0.04 +0.04 +0.04 ns

TISSTL3 SSTL3 –0.02 +0.04 +0.04 +0.04 ns

TICTT CTT +0.01 +0.10 +0.10 +0.10 ns

TIAGP AGP –0.03 +0.04 +0.04 +0.04 ns

Notes:

1. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.

Figure 1: Virtex-E Input/Output Block (IOB)

OBUFT

IBUF

Vref

ds022_02_091300

CLK

ICE

OCE

PAD

Programmable

Delay

Weak

Keeper

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IOB Output Switching Characteristics, Figure 1

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust

the delays with the values shown in ‘‘IOB Output Switching Characteristics Standard Adjustments’’ on page 8..

Speed Grade(2)

UnitsDescription(1) Symbol Min3-8 -7 -6

Propagation Delays

O input to Pad TIOOP 1.04 2.5 2.7 2.9 ns, max

O input to Pad via transparent latch TIOOLP 1.24 2.9 3.1 3.4 ns, max

3-State Delays

T input to Pad high-impedance (Note 2) TIOTHZ 0.73 1.5 1.7 1.9 ns, max

T input to valid data on Pad TIOTON 1.13 2.7 2.9 3.1 ns, max

T input to Pad high-impedance via

transparent latch (Note 2) TIOTLPHZ 0.86 1.8 2.0 2.2 ns, max

T input to valid data on Pad via

transparent latch TIOTLPON 1.26 3.0 3.2 3.4 ns, max

GTS to Pad high impedance (Note 2) TGTS 1.94 4.1 4.6 4.9 ns, max

Sequential Delays

Clock CLK

Minimum Pulse Width, High TCH 0.56 1.2 1.3 1.4 ns, min

Minimum Pulse Width, Low TCL 0.56 1.2 1.3 1.4 ns, min

Clock CLK to Pad TIOCKP 0.97 2.4 2.8 2.9 ns, max

Clock CLK to Pad high-impedance

(synchronous) (Note 2) TIOCKHZ 0.77 1.6 2.0 2.2 ns, max

Clock CLK to valid data on Pad

(synchronous) TIOCKON 1.17 2.8 3.2 3.4 ns, max

Setup and Hold Times before/after

Clock CLK

O input TIOOCK / TIOCKO 0.43 / 0 0.9 / 0 1.0 / 0 1.1 / 0 ns, min

OCE input TIOOCECK / TIOCKOCE 0.28 / 0 0.55 / 0.01 0.7 / 0 0.7 / 0 ns, min

SR input (OFF) TIOSRCKO / TIOCKOSR 0.40 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min

3-State Setup Times, T input TIOTCK / TIOCKT 0.26 / 0 0.51 / 0 0.6 / 0 0.7 / 0 ns, min

3-State Setup Times, TCE input TIOTCECK / TIOCKTCE 0.30 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min

3-State Setup Times, SR input (TFF) TIOSRCKT / TIOCKTSR 0.38 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min

Set/Reset Delays

SR input to Pad (asynchronous) TIOSRP 1.30 3.1 3.3 3.5 ns, max

SR input to Pad high-impedance

(asynchronous) (Note 2) TIOSRHZ 1.08 2.2 2.4 2.7 ns, max

SR input to valid data on Pad

(asynchronous) TIOSRON 1.48 3.4 3.7 3.9 ns, max

GSR to Pad TIOGSRQ 3.88 7.6 8.5 9.7 ns, max

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

2. 3-state turn-off delays should not be adjusted.

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IOB Output Switching Characteristics Standard Adjustments

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust

the delays by the values shown.

Speed Grade

UnitsDescription Symbol Standard Min -8 -7 -6

Output Delay Adjustments

Standard-specific adjustments for

output delays terminating at pads

(based on standard capacitive load,

Csl)

TOLVTTL_S2 LVTTL, Slow, 2 mA 4.2 +14.7 +14.7 +14.7 ns

TOLVTTL_S4 4 mA 2.5 +7.5 +7.5 +7.5 ns

TOLVTTL_S6 6 mA 1.8 +4.8 +4.8 +4.8 ns

TOLVTTL_S8 8 mA 1.2 +3.0 +3.0 +3.0 ns

TOLVTTL_S12 12 mA 1.0 +1.9 +1.9 +1.9 ns

TOLVTTL_S16 16 mA 0.9 +1.7 +1.7 +1.7 ns

TOLVTTL_S24 24 mA 0.8 +1.3 +1.3 +1.3 ns

TOLVTTL_F2 LVTTL, Fast, 2 mA 1.9 +13.1 +13.1 +13.1 ns

TOLVTTL_F4 4 mA 0.7 +5.3 +5.3 +5.3 ns

TOLVTTL_F6 6 mA 0.20 +3.1 +3.1 +3.1 ns

TOLVTTL_F8 8 mA 0.10 +1.0 +1.0 +1.0 ns

TOLVTTL_F12 12 mA 0.0 0.0 0.0 0.0 ns

TOLVTTL_F16 16 mA –0.10 –0.05 –0.05 –0.05 ns

TOLVTTL_F24 24 mA –0.10 –0.20 –0.20 –0.20 ns

TOLVCMOS_2 LV CM OS 2 0.10 +0.09 +0.09 +0.09 ns

TOLVCMOS_18 LV C M O S 1 8 0.10 +0.7 +0.7 +0.7 ns

TOLVDS LV D S –0.39 –1.2 –1.2 –1.2 ns

TOLVPECL LVPE CL –0.20 –0.41 –0.41 –0.41 ns

TOPCI33_3 PCI, 33 MHz, 3.3 V 0.50 +2.3 +2.3 +2.3 ns

TOPCI66_3 PCI, 66 MHz, 3.3 V 0.10 –0.41 –0.41 –0.41 ns

TOGTL GTL 0.6 +0.49 +0.49 +0.49 ns

TOGTLP GTL+ 0.7 +0.8 +0.8 +0.8 ns

TOHSTL_I HSTL I 0.10 –0.51 –0.51 –0.51 ns

TOHSTL_IIII HSTL III –0.10 –0.91 –0.91 –0.91 ns

TOHSTL_IV HSTL IV –0.20 –1.01 –1.01 –1.01 ns

TOSSTL2_I SSTL2 I –0.10 –0.51 –0.51 –0.51 ns

TOSSTL2_II SSTL2 II –0.20 –0.91 –0.91 –0.91 ns

TOSSTL3_I SSTL3 I –0.20 –0.51 –0.51 –0.51 ns

TOSSTL3_II SSTL3 II –0.30 –1.01 –1.01 –1.01 ns

TOCTT CTT 0.0 –0.61 –0.61 –0.61 ns

TOAGP AGP –0.1 –0.91 –0.91 –0.91 ns

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Calculation of Tioop as a Function of Capacitance

Tioop is the propagation delay from the O Input of the IOB to the

pad. The values for Tioop are based on the standard capacitive

load (Csl) for each I/O standard as listed in Ta bl e 2 .

For other capacitive loads, use the formulas below to calcu-

late the corresponding Tioop.

Tioop = Tioop + Topadjust + (Cload – Csl) * fl

where:

Topadjust is reported above in the Output Delay

Adjustment section.

Cload is the capacitive load for the design.

Table 2: Constants for Use in Calculation of Tioop

Standard

Csl

(pF)

(ns/pF)

LVTTL Fast Slew Rate, 2mA drive 35 0.41

LVTTL Fast Slew Rate, 4mA drive 35 0.20

LVTTL Fast Slew Rate, 6mA drive 35 0.13

LVTTL Fast Slew Rate, 8mA drive 35 0.079

LVTTL Fast Slew Rate, 12mA drive 35 0.044

LVTTL Fast Slew Rate, 16mA drive 35 0.043

LVTTL Fast Slew Rate, 24mA drive 35 0.033

LVTTL Slow Slew Rate, 2mA drive 35 0.41

LVTTL Slow Slew Rate, 4mA drive 35 0.20

LVTTL Slow Slew Rate, 6mA drive 35 0.10

LVTTL Slow Slew Rate, 8mA drive 35 0.086

LVTTL Slow Slew Rate, 12mA drive 35 0.058

LVTTL Slow Slew Rate, 16mA drive 35 0.050

LVTTL Slow Slew Rate, 24mA drive 35 0.048

LV C M O S 2 3 5 0 . 0 4 1

LVCMOS18 35 0.050

PCI 33 MHZ 3.3 V 10 0.050

PCI 66 MHz 3.3 V 10 0.033

GTL 0 0.014

GTL+ 0 0.017

HSTL Class I 20 0.022

HSTL Class III 20 0.016

HSTL Class IV 20 0.014

SSTL2 Class I 30 0.028

SSTL2 Class II 30 0.016

SSTL3 Class I 30 0.029

SSTL3 Class II 30 0.016

CTT 20 0.035

AGP 10 0.037

Notes:

1. I/O parameter measurements are made with the capacitance

values shown above. See the Application Examples for

appropriate terminations.

2. I/O standard measurements are reflected in the IBIS model

information except where the IBIS format precludes it.

Table 3 : Delay Measurement Methodology

Standard VL1VH1

Meas.

Point

VREF

(Typ)2

LVTTL 031.4-

LVCM OS2 02.51.125-

PCI33_3 Per PCI Spec -

PCI66_3 Per PCI Spec -

GTL VREF –0.2 VREF +0.2 VREF 0.80

GTL+ VREF –0.2 VREF +0.2 VREF 1.0

HSTL Class I VREF –0.5 VREF +0.5 VREF 0.75

HSTL Class III VREF –0.5 VREF +0.5 VREF 0.90

HSTL Class IV VREF –0.5 VREF +0.5 VREF 0.90

SSTL3 I & II VREF –1.0 VREF +1.0 VREF 1.5

SSTL2 I & II VREF –0.75 VREF +0.75 VREF 1.25

CTT VREF –0.2 VREF +0.2 VREF 1.5

AGP VREF –

(0.2xVCCO)

VREF +

(0.2xVCCO)VREF

Per

AGP

Spec

LVDS 1.2 – 0.125 1.2 + 0.125 1.2

LVPECL 1.6 – 0.3 1.6 + 0.3 1.6

Notes:

1. Input waveform switches between VLand VH.

2. Measurements are made at VREF (Typ), Maximum, and

Minimum. Worst-case values are reported.

I/O parameter measurements are made with the capacitance

values shown in Tabl e 2 . See the Application Examples for

appropriate terminations.

I/O standard measurements are reflected in the IBIS model

information except where the IBIS format precludes it.

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Clock Distribution Switching Characteristics

I/O Standard Global Clock Input Adjustments

Description Symbol

Speed Grade

UnitsMin-8-7-6

GCLK IOB and Buffer

Global Clock PAD to output. TGPIO 0.38 0.7 0.7 0.7 ns, max

Global Clock Buffer I input to O output TGIO 0.11 0.19 0.45 0.50 ns, max

Description(1) Symbol Standard

Speed Grade

UnitsMin-8-7-6

Data Input Delay Adjustments

Standard-specific global clock

input delay adjustments

TGPLVTTL LVTTL 0.0 0.0 0.0 0.0 ns, max

TGPLVCMOS2 LVC MOS2 –0.02 0.0 0.0 0.0 ns, max

TGPLVCMOS18 LVCMOS2 0.12 0.20 0.20 0.20 ns, max

TGLVDS LVDS 0.23 0.38 0.38 0.38 ns, max

TGLVPECL LVPECL 0.23 0.38 0.38 0.38 ns, max

TGPPCI33_3 PCI, 33 MHz, 3.3 V –0.05 0.08 0.08 0.08 ns, max

TGPPCI66_3 PCI, 66 MHz, 3.3 V –0.05 –0.11 –0.11 –0.11 ns, max

TGPGTL GTL 0.20 0.37 0.37 0.37 ns, max

TGPGTLP GTL+ 0.20 0.37 0.37 0.37 ns, max

TGPHSTL HSTL 0.18 0.27 0.27 0.27 ns, max

TGPSSTL2 SSTL2 0.21 0.27 0.27 0.27 ns, max

TGPSSTL3 SSTL3 0.18 0.27 0.27 0.27 ns, max

TGPCTT CTT 0.22 0.33 0.33 0.33 ns, max

TGPAGP AGP 0.21 0.27 0.27 0.27 ns, max

Notes:

1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Ta b le 3 .

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CLB Switching Characteristics

Delays originating at F/G inputs vary slightly according to the input used, see Figure 2. The values listed below are

worst-case. Precise values are provided by the timing analyzer.

Description(1) Symbol

Speed Grade

UnitsMin -8 -7 -6

Combinatorial Delays

4-input function: F/G inputs to X/Y outputs TILO 0.19 0.40 0.42 0.47 ns, max

5-input function: F/G inputs to F5 output TIF5 0.36 0.76 0.8 0.9 ns, max

5-input function: F/G inputs to X output TIF5X 0.35 0.74 0.8 0.9 ns, max

6-input function: F/G inputs to Y output via F6 MUX TIF6Y 0.35 0.74 0.9 1.0 ns, max

6-input function: F5IN input to Y output TF5INY 0.04 0.11 0.20 0.22 ns, max

Incremental delay routing through transparent latch

to XQ/YQ outputs TIFNCTL 0.27 0.63 0.7 0.8 ns, max

BY input to YB output TBYYB 0.19 0.38 0.46 0.51 ns, max

Sequential Delays

FF Clock CLK to XQ/YQ outputs TCKO 0.34 0.78 0.9 1.0 ns, max

Latch Clock CLK to XQ/YQ outputs TCKLO 0.40 0.77 0.9 1.0 ns, max

Setup and Hold Times before/after Clock CLK

4-input function: F/G Inputs TICK /

TCKI

0.39 / 0 0.9 / 0 1.0 / 0 1.1 / 0 ns, min

5-input function: F/G inputs TIF5CK /

TCKIF5

0.55 / 0 1.3 / 0 1.4 / 0 1.5 / 0 ns, min

6-input function: F5IN input TF5INCK

TCKF5IN

0.27 / 0 0.6 / 0 0.8 / 0 0.8 / 0 ns, min

6-input function: F/G inputs via F6 MUX TIF6CK /

TCKIF6

0.58 / 0 1.3 / 0 1.5 / 0 1.6 / 0 ns, min

BX/BY inputs TDICK /

TCKDI

0.25 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min

CE input TCECK /

TCKCE

0.28 / 0 0.55 / 0 0.7 / 0 0.7 / 0 ns, min

SR/BY inputs (synchronous) TRCK /

TCKR

0.24 / 0 0.46 / 0 0.52 / 0 0.6 / 0 ns, min

Clock CLK

Minimum Pulse Width, High TCH 0.56 1.2 1.3 1.4 ns, min

Minimum Pulse Width, Low TCL 0.56 1.2 1.3 1.4 ns, min

Set/Reset

Minimum Pulse Width, SR/BY inputs TRPW 0.94 1.9 2.1 2.4 ns, min

Delay from SR/BY inputs to XQ/YQ outputs

(asynchronous) TRQ 0.39 0.8 0.9 1.0 ns, max

Toggle Frequency (MHz) (for export control) FTOG - 416 400 357 MHz

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

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Figure 2: Detailed View of Virtex-E Slice

F5IN

CLK

CIN

F5 F5

ds022_05_092000

COUT

CK WSO

WSH

BY DG

BX DI

LUT

INIT

REV

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CLB Arithmetic Switching Characteristics

Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment

listed. Precise values are provided by the timing analyzer.

Description(1) Symbol

Speed Grade

UnitsMin -8 -7 -6

Combinatorial Delays

F operand inputs to X via XOR TOPX 0.32 0.68 0.8 0.8 ns, max

F operand input to XB output TOPXB 0.35 0.65 0.8 0.9 ns, max

F operand input to Y via XOR TOPY 0.59 1.07 1.4 1.5 ns, max

F operand input to YB output TOPYB 0.48 0.89 1.1 1.3 ns, max

F operand input to COUT output TOPCYF 0.37 0.71 0.9 1.0 ns, max

G operand inputs to Y via XOR TOPGY 0.34 0.72 0.8 0.9 ns, max

G operand input to YB output TOPGYB 0.47 0.78 1.2 1.3 ns, max

G operand input to COUT output TOPCYG 0.36 0.60 0.9 1.0 ns, max

BX initialization input to COUT TBXCY 0.19 0.36 0.51 0.57 ns, max

CIN input to X output via XOR TCINX 0.27 0.50 0.6 0.7 ns, max

CIN input to XB TCINXB 0.02 0.04 0.07 0.08 ns, max

CIN input to Y via XOR TCINY 0.26 0.45 0.7 0.7 ns, max

CIN input to YB TCINYB 0.16 0.28 0.38 0.43 ns, max

CIN input to COUT output TBYP 0.05 0.10 0.14 0.15 ns, max

Multiplier Operation

F1/2 operand inputs to XB output via AND TFANDXB 0.10 0.30 0.35 0.39 ns, max

F1/2 operand inputs to YB output via AND TFANDYB 0.28 0.56 0.7 0.8 ns, max

F1/2 operand inputs to COUT output via AND TFANDCY 0.17 0.38 0.46 0.51 ns, max

G1/2 operand inputs to YB output via AND TGANDYB 0.20 0.46 0.55 0.7 ns, max

G1/2 operand inputs to COUT output via AND TGANDCY 0.09 0.28 0.30 0.34 ns, max

Setup and Hold Times before/after Clock CLK

CIN input to FFX TCCKX/TCKCX 0.47 / 0 1.0 / 0 1.2 / 0 1.3 / 0 ns, min

CIN input to FFY TCCKY/TCKCY 0.49 / 0 0.92 / 0 1.2 / 0 1.3 / 0 ns, min

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

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CLB Distributed RAM Switching Characteristics

Description(1) Symbol

Speed Grade

UnitsMin -8 -7 -6

Sequential Delays

Clock CLK to X/Y outputs (WE active) 16 x 1 mode TSHCKO16 0.67 1.38 1.5 1.7 ns, max

Clock CLK to X/Y outputs (WE active) 32 x 1 mode TSHCKO32 0.84 1.66 1.9 2.1 ns, max

Shift-Register Mode

Clock CLK to X/Y outputs TREG 1.25 2.39 2.9 3.2 ns, max

Setup and Hold Times before/after Clock CLK

F/G address inputs TAS/TAH 0.19 / 0 0.38 / 0 0.42 / 0 0.47 / 0 ns, min

BX/BY data inputs (DIN) TDS/TDH 0.44 / 0 0.87 / 0 0.97 / 0 1.09 / 0 ns, min

SR input (WE) TWS/TWH 0.29 / 0 0.57 / 0 0.7 / 0 0.8 / 0 ns, min

Clock CLK

Minimum Pulse Width, High TWPH 0.96 1.9 2.1 2.4 ns, min

Minimum Pulse Width, Low TWPL 0.96 1.9 2.1 2.4 ns, min

Minimum clock period to meet address write cycle time TWC 1.92 3.8 4.2 4.8 ns, min

Shift-Register Mode

Minimum Pulse Width, High TSRPH 1.0 1.9 2.1 2.4 ns, min

Minimum Pulse Width, Low TSRPL 1.0 1.9 2.1 2.4 ns, min

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

Figure 3: Dual-Port Block SelectRAM

WEB

ENB

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

WEA

ENA

RSTA

CLKA

ADDRA[#:0]

DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

ds022_06_121699

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-3 (v2.3.2) March 14, 2003 www.xilinx.com Module 3 of 4

1-800-255-7778 15

Block RAM Switching Characteristics

TBUF Switching Characteristics

JTAG Test Access Port Switching Characteristics

Description(1) Symbol

Speed Grade

UnitsMin-8-7-6

Sequential Delays

Clock CLK to DOUT output TBCKO 0.63 2.46 3.1 3.5 ns, max

Setup and Hold Times before Clock CLK

ADDR inputs TBACK/TBCKA 0.42 / 0 0.9 / 0 1.0 / 0 1.1 / 0 ns, min

DIN inputs TBDCK/TBCKD 0.42 / 0 0.9 / 0 1.0 / 0 1.1 / 0 ns, min

EN input TBECK/TBCKE 0.97 / 0 2.0 / 0 2.2 / 0 2.5 / 0 ns, min

RST input TBRCK/TBCKR 0.9 / 0 1.8 / 0 2.1 / 0 2.3 / 0 ns, min

WEN input TBWCK/TBCKW 0.86 / 0 1.7 / 0 2.0 / 0 2.2 / 0 ns, min

Clock CLK

Minimum Pulse Width, High TBPWH 0.6 1.2 1.35 1.5 ns, min

Minimum Pulse Width, Low TBPWL 0.6 1.2 1.35 1.5 ns, min

CLKA -> CLKB setup time for different ports TBCCS 1.2 2.4 2.7 3.0 ns, min

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

Description Symbol

Speed Grade

UnitsMin -8 -7 -6

Combinatorial Delays

IN input to OUT output TIO 0.0 0.0 0.0 0 .0 ns, max

TRI input to OUT output high-impedance TOFF 0.05 0.092 0.10 0.11 ns, max

TRI input to valid data on OUT output TON 0.05 0.092 0.10 0.11 ns, max

Description Symbol Value Units

TMS and TDI Setup times before TCK TTA P T K 4.0 ns, min

TMS and TDI Hold times after TCK TTCKTAP 2.0 ns, min

Output delay from clock TCK to output TDO TTCKTDO 11.0 ns, max

Maximum TCK clock frequency FTCK 33 MHz, max

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4 www.xilinx.com DS025-3 (v2.3.2) March 14, 2003
16 1-800-255-7778
R
Virtex-E Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
 Description(1) Symbol Device(3)
Speed Grade(2)
UnitsMin -8 -7 -6
LVTTL Global Clock Input to Output Delay using 
Output Flip-flop, 12 mA, Fast Slew Rate, with 
DLL. 
For data output with different standards, adjust 
the delays with the values shown in ‘‘IOB Output 
Switching Characteristics Standard Adjustments’’ 
on page 8.
TICKOFDLL XCV405E 1.0 3.1 3.1 3.1 ns
XCV812E 1.0 3.1 3.1 3.1 ns
Notes: 
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and 
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see 
Ta b l e 2  and Ta bl e 3 .
3. DLL output jitter is already included in the timing calculation.
 Description(1) Symbol Device
 Speed Grade(2)
UnitsMin -8 -7 -6
LVTTL Global Clock Input to Output Delay using 
Output Flip-flop, 12 mA, Fast Slew Rate, without 
DLL. 
For data output with different standards, adjust 
the delays with the values shown in ‘‘IOB Output 
Switching Characteristics Standard Adjustments’’ 
on page 8.
TICKOF XCV405E 1.6 4.5 4.7 4.9 ns
XCV812E 1.8 4.8 5.0 5.2 ns
Notes: 
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and 
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see 
Ta b l e 2  and Ta bl e 3 .

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-3 (v2.3.2) March 14, 2003 www.xilinx.com Module 3 of 4

1-800-255-7778 17

Virtex-E Pin-to-Pin Input Parameter Guidelines

All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock

loading. Values are expressed in nanoseconds unless otherwise noted.

Global Clock Set-Up and Hold for LVTTL Standard, with DLL

Global Clock Set-Up and Hold for LVTTL Standard, without DLL

Description(1) Symbol Device(3)

Speed Grade(2)

UnitsMin-8-7-6

Input Setup and Hold Time Relative to Global Clock Input Signal

for LVTTL Standard.

For data input with different standards, adjust the setup time

delay by the values shown in ‘‘IOB Input Switching

Characteristics Standard Adjustments’’ on page 6.

No Delay TPSDLL/TPHDLL XCV405E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 ns

Global Clock and IFF, with DLL XCV812E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 ns

Notes:

1. IFF = Input Flip-Flop or Latch

2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured

relative to the Global Clock input signal with the slowest route and heaviest load.

3. DLL output jitter is already included in the timing calculation.

Description(1) Symbol Device(3)

Speed Grade(2)

UnitsMin -8 -7 -6

Input Setup and Hold Time Relative to Global Clock Input Signal

for LVTTL Standard.

For data input with different standards, adjust the setup time delay

by the values shown in ‘‘IOB Input Switching Characteristics

Standard Adjustments’’ on page 6.

Full Delay TPSFD/TPHFD XCV405E 2.3 / 0 2.3 / 0 2.3 / 0 2.3 / 0 ns

Global Clock and IFF, without DLL XCV812E 2.5 / 0 2.5 / 0 2.5 / 0 2.5 / 0 ns

Notes:

1. IFF = Input Flip-Flop or Latch

2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured

relative to the Global Clock input signal with the slowest route and heaviest load.

3. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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18 1-800-255-7778

DLL Timing Parameters

All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those

parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the

recommended operating conditions.

Description Symbol FCLKIN

Speed Grade

Units

-8 -7 -6

Min Max Min Max Min Max

Input Clock Frequency (CLKDLLHF) FCLKINHF 60 320 60 320 60 260 MHz

Input Clock Frequency (CLKDLL) FCLKINLF 25 160 25 160 25 135 MHz

Input Clock Low/High Pulse Width TDLLPW ≥25 MHz 5.0 5.0 5.0 ns

≥50 MHz 3.0 3.0 3.0 ns

≥100 MHz 2.4 2.4 2.4 ns

≥150 MHz 2.0 2.0 2.0 ns

≥200 MHz 1.8 1.8 1.8 ns

≥250 MHz 1.5 1.5 1.5 ns

≥300 MHz 1.3 1.3 NA ns

Figure 4: DLL Timing Waveforms

TCLKIN TCLKIN + T

IPTOL

Period Tolerance: the allowed input clock period change in nanoseconds.

Output Jitter: the difference between an ideal

reference clock edge and the actual design.

ds022_24_091200

Ideal Period

Actual Period

+ Jitter

+/- Jitter

+ Maximum

Phase Difference

Phase Offset and Maximum Phase Difference

+ Phase Offset

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-3 (v2.3.2) March 14, 2003 www.xilinx.com Module 3 of 4

1-800-255-7778 19

DLL Clock Tolerance, Jitter, and Phase Information

All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock

mirror configuration and matched drivers.

Revision History

The following table shows the revision history for this document.

CLKDLLHF CLKDLL

UnitsDescription Symbol FCLKIN Min Max Min Max

Input Clock Period Tolerance TIPTOL - 1.0 - 1.0 ns

Input Clock Jitter Tolerance (Cycle to Cycle) TIJITCC -± 150 - ± 300 ps

Time Required for DLL to Acquire Lock(6) TLOCK > 60 MHz - 20 - 20 µs

50 - 60 MHz - - - 25 µs

40 - 50 MHz - - - 50 µs

30 - 40 MHz - - - 90 µs

25 - 30 MHz - - - 120 µs

Output Jitter (cycle-to-cycle) for any DLL Clock Output(1) TOJITCC ± 60 ± 60 ps

Phase Offset between CLKIN and CLKO(2) TPHIO ± 100 ± 100 ps

Phase Offset between Clock Outputs on the DLL(3) TPHOO ± 140 ± 140 ps

Maximum Phase Difference between CLKIN and CLKO(4) TPHIOM ± 160 ± 160 ps

Maximum Phase Difference between Clock Outputs on the DLL(5) TPHOOM ± 200 ± 200 ps

Notes:

1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution, excluding

input clock jitter.

2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,

excluding Output Jitter and input clock jitter.

3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL

outputs, excluding Output Jitter and input clock jitter.

4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,

or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).

5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL

clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).

6. Add 30% to the value for Industrial grade parts.

Date Version Revision

03/23/00 1.0 Initial Xilinx release.

08/01/00 1.1 Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.

Reformatted to adhere to corporate documentation style guidelines. Minor changes in

BG560 pin-out table.

09/19/00 1.2 •In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no

longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.

•Min values added to Virtex-E Electrical Characteristics tables.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4 www.xilinx.com DS025-3 (v2.3.2) March 14, 2003
20 1-800-255-7778
R
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules:
•DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
Introduction and Ordering Information (Module 1)
•DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
•DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
•DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4) 
11/20/00 1.3 •Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables 
(Module 3).
•Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
•Added to note 2 of Absolute Maximum Ratings (Module 3).
•Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL 
Standard, with DLL (Module 3).
•Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).
04/02/01 1.4 •In Ta b le 4 , FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF, 
and pin G16 is now labeled as VREF. 
•Updated values in Virtex-E Switching Characteristics tables. 
•Converted data sheet to modularized format. See the Virtex-E Extended Memory Data 
Sheet section.
04/19/01 1.5 •Updated values in Virtex-E Switching Characteristics tables. 
07/23/01 1.6 •Under Absolute Maximum Ratings, changed (TSOL) to 220 °C .
•Changes made to SSTL symbol names in IOB Input Switching Characteristics Standard 
Adjustments table. 
07/26/01 1.7 •Removed TSOL parameter and added footnote to Absolute Maximum Ratings table.
09/18/01 1.8 •Reworded power supplies footnote to Absolute Maximum Ratings table.
10/25/01 1.9 •Updated the speed grade designations used in data sheets, and added Table 1, which 
shows the current speed grade designation for each device.
•Updated Power-On Power Supply Requirements table.
11/09/01 2.0 •Updated the XCV405E device speed grade designation to Preliminary in Ta ble 1 .
•Updated Power-On Power Supply Requirements table.
02/01/02 2.1 •Updated footnotes to the DC Input and Output Levels and DLL Clock Tolerance, Jitter, 
and Phase Information tables.
07/17/02 2.2 •Data sheet designation upgraded from Preliminary to Production.
•Removed mention of MIL-M-38510/605 specification.
•Added link to XAPP158 from the Power-On Power Supply Requirements section.
09/10/02 2.3 •Revised VIN in Absolute Maximum Ratings Table. Added Clock CLK switching 
characteristics to ‘‘IOB Input Switching Characteristics’’ on page 5 and ‘‘IOB Output 
Switching Characteristics, Figure 1’’ on page 7.
12/22/02 2.3.1 •Added footnote regarding VIN PCI compliance to Absolute Maximum Ratings table.
03/14/03 2.3.2 •Under Power-On Power Supply Requirements, the fastest ramp rate is no longer a 
"suggested" rate.
Date Version Revision

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 1

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Virtex-E Pin Definitions

Virtex™-E 1.8 V Extended Memory

Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 00Production Product Specification

Pin Name Dedicated Pin Direction Description

GCK0, GCK1,

GCK2, GCK3

Yes Input Clock input pins that connect to Global Clock Buffers. These pins become

user inputs when not needed for clocks.

M0, M1, M2 Yes Input Mode pins are used to specify the configuration mode.

CCLK Yes Input or

Output

The configuration Clock I/O pin: it is an input for SelectMAP and slave-serial

modes, and output in master-serial mode. After configuration, it is input only,

logic level = Don’t Care.

PROGRAM Yes Input Initiates a configuration sequence when asserted Low.

DONE Yes Bidirectional Indicates that configuration loading is complete, and that the start-up

sequence is in progress. The output can be open drain.

INIT No Bidirectional

(Open-drain)

When Low, indicates that the configuration memory is being cleared. The pin

becomes a user I/O after configuration.

BUSY/DOUT No Output In SelectMAP mode, BUSY controls the rate at which configuration data is

loaded. The pin becomes a user I/O after configuration unless the

SelectMAP port is retained.

In bit-serial modes, DOUT provides preamble and configuration data to

downstream devices in a daisy-chain. The pin becomes a user I/O after

configuration.

D0/DIN,

D1, D2,

D3, D4,

D5, D6,

No Input or

Output

In SelectMAP mode, D0-7 are configuration data pins. These pins become

user I/Os after configuration unless the SelectMAP port is retained.

In bit-serial modes, DIN is the single data input. This pin becomes a user I/O

after configuration.

WRITE No Input In SelectMAP mode, the active-low Write Enable signal. The pin becomes a

user I/O after configuration unless the SelectMAP port is retained.

CS No Input In SelectMAP mode, the active-low Chip Select signal. The pin becomes a

user I/O after configuration unless the SelectMAP port is retained.

TDI, TDO,

TMS, TCK

Yes Mixed Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1.

DXN, DXP Yes N/A Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)

VCCINT Yes Input Power-supply pins for the internal core logic.

VCCO Yes Input Power-supply pins for the output drivers (subject to banking rules)

VREF No Input Input threshold voltage pins. Become user I/Os when an external threshold

voltage is not needed (subject to banking rules).

GND Yes Input Ground

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

2 1-800-255-7778

BG560 Ball Grid Array Packages

XCV405E and the XCV812E Virtex-E Extended Memory

devices are available in the BG560 BGA package. Pins

labeled I0_VREF can be used as either in all parts unless

device-dependent as indicated in the footnotes. If the pin is

not used as VREF

, it can be used as general I/O. Immedi-

ately following Ta b l e 1 , see Table 2 for BG560 package Dif-

ferential Pair information.

Table 1: BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

0GCK3A17

0IOA27

0IOB25

0IOC28

0IOC30

0IOD30

0IOE18

0 IO_L0N E28

0 IO_L0P D29

0 IO_L1N_YY D28

0 IO_L1P_YY A31

0 IO_VREF_L2N_YY E27

0 IO_L2P_YY C29

0 IO_L3N_Y B30

0 IO_L3P_Y D27

0 IO_L4N_YY E26

0 IO_L4P_YY B29

0 IO_VREF_L5N_YY D26

0 IO_L5P_YY C27

0 IO_L6N E25

0 IO_L6P A28

0 IO_L7N_YY D25

0 IO_L7P_YY C26

0 IO_VREF_L8N_YY E241

0 IO_L8P_YY B26

0 IO_L9N_Y C25

0 IO_L9P_Y D24

0 IO_VREF_L10N_YY E23

0 IO_L10P_YY A25

0 IO_L11N_YY D23

0 IO_L11P_YY B24

0 IO_L12N E22

0 IO_L12P C23

0 IO_L13N_YY A23

0 IO_L13P_YY D22

0 IO_VREF_L14N_YY E211

0 IO_L14P_YY B22

0 IO_L15N_Y D21

0 IO_L15P_Y C21

0 IO_L16N_YY B21

0 IO_L16P_YY E20

0 IO_VREF_L17N_YY D20

0 IO_L17P_YY C20

0 IO_L18N B20

0 IO_L18P E19

0 IO_L19N_YY D19

0 IO_L19P_YY C19

0 IO_VREF_L20N_YY A19

0 IO_L20P_YY D18

0 IO_LVDS_DLL_L21N C18

1GCK2D17

1IOA3

1IOD9

1IOE8

1IOE11

1 IO_LVDS_DLL_L21P E17

1 IO_L22N_Y C17

1 IO_L22P_Y B17

1 IO_L23N_YY B16

1 IO_VREF_L23P_YY D16

1 IO_L24N_YY E16

1 IO_L24P_YY C16

1 IO_L25N A15

1 IO_L25P C15

1 IO_L26N_YY D15

1 IO_VREF_L26P_YY E15

Table 1 : BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 3

1 IO_L27N_YY C14

1 IO_L27P_YY D14

1 IO_L28N_Y A13

1 IO_L28P_Y E14

1 IO_L29N_YY C13

1 IO_VREF_L29P_YY D131

1 IO_L30N_YY C12

1 IO_L30P_YY E13

1 IO_L31N A11

1 IO_L31P D12

1 IO_L32N_YY B11

1 IO_L32P_YY C11

1 IO_L33N_YY B10

1 IO_VREF_L33P_YY D11

1 IO_L34N C10

1 IO_L34P A9

1 IO_L35N_YY C9

1 IO_VREF_L35P_YY D101

1 IO_L36N_YY A8

1 IO_L36P_YY B8

1 IO_L37N_Y E10

1 IO_L37P_Y C8

1 IO_L38N_YY B7

1 IO_VREF_L38P_YY A6

1 IO_L39N_YY C7

1 IO_L39P_YY D8

1 IO_L40N A5

1 IO_L40P B5

1 IO_L41N_YY C6

1 IO_VREF_L41P_YY D7

1 IO_L42N_YY A4

1 IO_L42P_YY B4

1 IO_L43N_Y C5

1 IO_L43P_Y E7

1 IO_WRITE_L44N_YY D6

1 IO_CS_L44P_YY A2

Table 1: BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

2IOD3

2IOF3

2IOG1

2IOJ2

2 IO_DOUT_BUSY_L45P_YY D4

2 IO_DIN_D0_L45N_YY E4

2 IO_L46P_Y F5

2 IO_L46N_Y B3

2 IO_L47P F4

2 IO_L47N C1

2 IO_VREF_L48P_Y G5

2 IO_L48N_Y E3

2 IO_L49P_Y D2

2 IO_L49N_Y G4

2 IO_L50P_Y H5

2 IO_L50N_Y E2

2 IO_VREF_L51P_YY H4

2 IO_L51N_YY G3

2 IO_L52P_Y J5

2 IO_L52N_Y F1

2 IO_L53P J4

2 IO_L53N H3

2 IO_VREF_L54P_YY K51

2 IO_L54N_YY H2

2 IO_L55P_Y J3

2 IO_L55N_Y K4

2 IO_VREF_L56P_YY L5

2 IO_D1_L56N_YY K3

2 IO_D2_L57P_YY L4

2 IO_L57N_YY K2

2 IO_L58P_Y M5

2 IO_L58N_Y L3

2 IO_L59P L1

2 IO_L59N M4

2 IO_VREF_L60P_Y N51

2 IO_L60N_Y M2

2 IO_L61P_Y N4

Table 1 : BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

4 1-800-255-7778

2 IO_L61N_Y N3

2 IO_L62P_Y N2

2 IO_L62N_Y P5

2 IO_VREF_L63P_YY P4

2 IO_D3_L63N_YY P3

2 IO_L64P_Y P2

2 IO_L64N_Y R5

2 IO_L65P_Y R4

2 IO_L65N_Y R3

2 IO_VREF_L66P_Y R1

2 IO_L66N_Y T4

2 IO_L67P_Y T5

2 IO_L67N_Y T3

2 IO_L68P_YY T2

2 IO_L68N_YY U3

3IOU4

3 IO AE3

3IOAF3

3IOAH3

3 IO AK3

3 IO_L69P_Y U1

3 IO_L69N_Y U2

3 IO_L70P_Y V2

3 IO_VREF_L70N_Y V4

3 IO_L71P_Y V5

3 IO_L71N_Y V3

3 IO_L72P W1

3 IO_L72N W3

3 IO_D4_L73P_YY W4

3 IO_VREF_L73N_YY W5

3 IO_L74P_Y Y3

3 IO_L74N_Y Y4

3 IO_L75P AA1

3 IO_L75N Y5

3 IO_L76P_Y AA3

3 IO_VREF_L76N_Y AA41

Table 1: BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

3 IO_L77P AB3

3 IO_L77N AA5

3 IO_L78P AC1

3 IO_L78N AB4

3 IO_L79P_YY AC3

3 IO_D5_L79N_YY AB5

3 IO_D6_L80P_YY AC4

3 IO_VREF_L80N_YY AD3

3 IO_L81P_Y AE1

3 IO_L81N_Y AC5

3 IO_L82P_YY AD4

3 IO_VREF_L82N_YY AF11

3 IO_L83P_Y AF2

3 IO_L83N_Y AD5

3 IO_L84P_Y AG2

3 IO_L84N_Y AE4

3 IO_L85P_YY AH1

3 IO_VREF_L85N_YY AE5

3 IO_L86P_Y AF4

3 IO_L86N_Y AJ1

3 IO_L87P_Y AJ2

3 IO_L87N_Y AF5

3 IO_L88P_Y AG4

3 IO_VREF_L88N_Y AK2

3 IO_L89P_Y AJ3

3 IO_L89N_Y AG5

3 IO_L90P_Y AL1

3 IO_L90N_Y AH4

3 IO_D7_L91P_YY AJ4

3 IO_INIT_L91N_YY AH5

4GCK0AL17

4IOAJ8

4IOAJ11

4IOAK6

4IOAK9

4 IO_L92P_YY AL4

Table 1 : BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 5

4 IO_L92N_YY AJ6

4 IO_L93P AK5

4 IO_L93N AN3

4 IO_L94P_YY AL5

4 IO_L94N_YY AJ7

4 IO_VREF_L95P_YY AM4

4 IO_L95N_YY AM5

4 IO_L96P_Y AK7

4 IO_L96N_Y AL6

4 IO_L97P_YY AM6

4 IO_L97N_YY AN6

4 IO_VREF_L98P_YY AL7

4 IO_L98N_YY AJ9

4 IO_L99P AN7

4 IO_L99N AL8

4 IO_L100P_YY AM8

4 IO_L100N_YY AJ10

4 IO_VREF_L101P_YY AL91

4 IO_L101N_YY AM9

4 IO_L102P_Y AK10

4 IO_L102N_Y AN9

4 IO_VREF_L103P_YY AL10

4 IO_L103N_YY AM10

4 IO_L104P_YY AL11

4 IO_L104N_YY AJ12

4 IO_L105P AN11

4 IO_L105N AK12

4 IO_L106P_YY AL12

4 IO_L106N_YY AM12

4 IO_VREF_L107P_YY AK131

4 IO_L107N_YY AL13

4 IO_L108P_Y AM13

4 IO_L108N_Y AN13

4 IO_L109P_YY AJ14

4 IO_L109N_YY AK14

4 IO_VREF_L110P_YY AM14

4 IO_L110N_YY AN15

Table 1: BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

4 IO_L111P AJ15

4 IO_L111N AK15

4 IO_L112P_YY AL15

4 IO_L112N_YY AM16

4 IO_VREF_L113P_YY AL16

4 IO_L113N_YY AJ16

4 IO_L114P_Y AK16

4 IO_L114N_Y AN17

4 IO_LVDS_DLL_L115P AM17

5GCK1AJ17

5IOAL18

5IOAL25

5IOAL28

5IOAL30

5IOAN28

5 IO_LVDS_DLL_L115N AM18

5 IO_L116P_YY AK18

5 IO_VREF_L116N_YY AJ18

5 IO_L117P_YY AN19

5 IO_L117N_YY AL19

5 IO_L118P AK19

5 IO_L118N AM20

5 IO_L119P_YY AJ19

5 IO_VREF_L119N_YY AL20

5 IO_L120P_YY AN21

5 IO_L120N_YY AL21

5 IO_L121P_Y AJ20

5 IO_L121N_Y AM22

5 IO_L122P_YY AK21

5 IO_VREF_L122N_YY AN231

5 IO_L123P_YY AJ21

5 IO_L123N_YY AM23

5 IO_L124P AK22

5 IO_L124N AM24

5 IO_L125P_YY AL23

5 IO_L125N_YY AJ22

Table 1 : BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

6 1-800-255-7778

5 IO_L126P_YY AK23

5 IO_VREF_L126N_YY AL24

5 IO_L127P_Y AN26

5 IO_L127N_Y AJ23

5 IO_L128P_YY AK24

5 IO_VREF_L128N_YY AM261

5 IO_L129P_YY AM27

5 IO_L129N_YY AJ24

5 IO_L130P_Y AL26

5 IO_L130N_Y AK25

5 IO_L131P_YY AN29

5 IO_VREF_L131N_YY AJ25

5 IO_L132P_YY AK26

5 IO_L132N_YY AM29

5 IO_L133P_Y AM30

5 IO_L133N_Y AJ26

5 IO_L134P_YY AK27

5 IO_VREF_L134N_YY AL29

5 IO_L135P_YY AN31

5 IO_L135N_YY AJ27

5 IO_L136P_Y AM31

5 IO_L136N_Y AK28

6IOU29

6IOAE33

6IOAF31

6IOAJ32

6 IO AL33

6 IO_L137N_YY AH29

6 IO_L137P_YY AJ30

6 IO_L138N_Y AK31

6 IO_L138P_Y AH30

6 IO_L139N_Y AG29

6 IO_L139P_Y AJ31

6 IO_VREF_L140N_Y AK32

6 IO_L140P_Y AG30

6 IO_L141N_Y AH31

Table 1: BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

6 IO_L141P_Y AF29

6 IO_L142N_Y AH32

6 IO_L142P_Y AF30

6 IO_VREF_L143N_YY AE29

6 IO_L143P_YY AH33

6 IO_L144N_Y AG33

6 IO_L144P_Y AE30

6 IO_L145N_Y AD29

6 IO_L145P_Y AF32

6 IO_VREF_L146N_Y AE311

6 IO_L146P_Y AD30

6 IO_L147N_Y AE32

6 IO_L147P_Y AC29

6 IO_VREF_L148N_YY AD31

6 IO_L148P_YY AC30

6 IO_L149N_YY AB29

6 IO_L149P_YY AC31

6 IO_L150N_Y AC33

6 IO_L150P_Y AB30

6 IO_L151N_Y AB31

6 IO_L151P_Y AA29

6 IO_VREF_L152N_Y AA301

6 IO_L152P_Y AA31

6 IO_L153N_Y AA32

6 IO_L153P_Y Y29

6 IO_L154N_Y AA33

6 IO_L154P_Y Y30

6 IO_VREF_L155N_YY Y32

6 IO_L155P_YY W29

6 IO_L156N_Y W30

6 IO_L156P_Y W31

6 IO_L157N_Y W33

6 IO_L157P_Y V30

6 IO_VREF_L158N_Y V29

6 IO_L158P_Y V31

6 IO_L159N_Y V32

6 IO_L159P_Y U33

Table 1 : BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 7

7IOE30

7IOF29

7IOF33

7IOG30

7IOK30

7 IO_L160N_YY U31

7 IO_L160P_YY U32

7 IO_L161N_Y T32

7 IO_L161P_Y T30

7 IO_L162N_Y T29

7 IO_VREF_L162P_Y T31

7 IO_L163N_Y R33

7 IO_L163P_Y R31

7 IO_L164N_Y R30

7 IO_L164P_Y R29

7 IO_L165N_YY P32

7 IO_VREF_L165P_YY P31

7 IO_L166N_Y P30

7 IO_L166P_Y P29

7 IO_L167N_Y M32

7 IO_L167P_Y N31

7 IO_L168N_Y N30

7 IO_VREF_L168P_Y L331

7 IO_L169N_Y M31

7 IO_L169P_Y L32

7 IO_L170N_Y M30

7 IO_L170P_Y L31

7 IO_L171N_YY M29

7 IO_L171P_YY J33

7 IO_L172N_YY L30

7 IO_VREF_L172P_YY K31

7 IO_L173N_Y L29

7 IO_L173P_Y H33

7 IO_L174N_Y J31

7 IO_VREF_L174P_Y H321

7 IO_L175N_Y K29

Table 1: BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

7 IO_L175P_Y H31

7 IO_L176N_Y J30

7 IO_L176P_Y G32

7 IO_L177N_YY J29

7 IO_VREF_L177P_YY G31

7 IO_L178N_Y E33

7 IO_L178P_Y E32

7 IO_L179N_Y H29

7 IO_L179P_Y F31

7 IO_L180N_Y D32

7 IO_VREF_L180P_Y E31

7 IO_L181N_Y G29

7 IO_L181P_Y C33

7 IO_L182N_Y F30

7 IO_L182P_Y D31

2 CCLK C4

3DONEAJ5

NA DXN AK29

NA DXP AJ28

NA M0 AJ29

NA M1 AK30

NA M2 AN32

NA PROGRAM AM1

NA TCK E29

NA TDI D5

2TDOE6

NA TMS B33

NA NC C31

NA NC AC2

NA NC AK4

NA NC AL3

NA VCCINT A21

NA VCCINT B12

NA VCCINT B14

Table 1 : BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

8 1-800-255-7778

NA VCCINT B18

NA VCCINT B28

NA VCCINT C22

NA VCCINT C24

NA VCCINT E9

NA VCCINT E12

NA VCCINT F2

NA VCCINT H30

NA VCCINT J1

NA VCCINT K32

NA VCCINT M3

NA VCCINT N1

NA VCCINT N29

NA VCCINT N33

NA VCCINT U5

NA VCCINT U30

NA VCCINT Y2

NA VCCINT Y31

NA VCCINT AB2

NA VCCINT AB32

NA VCCINT AD2

NA VCCINT AD32

NA VCCINT AG3

NA VCCINT AG31

NA VCCINT AJ13

NA VCCINT AK8

NA VCCINT AK11

NA VCCINT AK17

NA VCCINT AK20

NA VCCINT AL14

NA VCCINT AL22

NA VCCINT AL27

NA VCCINT AN25

0VCCOA22

0VCCOA26

0VCCOA30

Table 1: BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

0 VCCO B19

0 VCCO B32

1 VCCO A10

1 VCCO A16

1 VCCO B13

1 VCCO C3

1 VCCO E5

2 VCCO B2

2 VCCO D1

2 VCCO H1

2 VCCO M1

2 VCCO R2

3 VCCO V1

3 VCCO AA2

3 VCCO AD1

3 VCCO AK1

3 VCCO AL2

4 VCCO AN4

4 VCCO AN8

4 VCCO AN12

4 VCCO AM2

4 VCCO AM15

5 VCCO AL31

5 VCCO AM21

5 VCCO AN18

5 VCCO AN24

5 VCCO AN30

6 VCCO W32

6 VCCO AB33

6 VCCO AF33

6 VCCO AK33

6 VCCO AM32

7 VCCO C32

7 VCCO D33

7 VCCO K33

7 VCCO N32

7 VCCO T33

Table 1 : BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 9

NA GND A1

NA GND A7

NA GND A12

NA GND A14

NA GND A18

NA GND A20

NA GND A24

NA GND A29

NA GND A32

NA GND A33

NA GND B1

NA GND B6

NA GND B9

NA GND B15

NA GND B23

NA GND B27

NA GND B31

NA GND C2

NA GND E1

NA GND F32

NA GND G2

NA GND G33

NA GND J32

NA GND K1

NA GND L2

NA GND M33

NA GND P1

NA GND P33

NA GND R32

NA GND T1

NA GND V33

NA GND W2

NA GND Y1

NA GND Y33

NA GND AB1

NA GND AC32

Table 1: BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

NA GND AD33

NA GND AE2

NA GND AG1

NA GND AG32

NA GND AH2

NA GND AJ33

NA GND AL32

NA GND AM3

NA GND AM7

NA GND AM11

NA GND AM19

NA GND AM25

NA GND AM28

NA GND AM33

NA GND AN1

NA GND AN2

NA GND AN5

NA GND AN10

NA GND AN14

NA GND AN16

NA GND AN20

NA GND AN22

NA GND AN27

NA GND AN33

Notes:

1. VREF or I/O option only in the XCV812E.

Table 1 : BG560 BGA — XCV405E and XCV812E

Bank Pin Description Pin#

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

10 1-800-255-7778

BG560 Differential Pin Pairs

Virtex-E Extended Memory devices have differential pin

pairs that can also provide other functions when not used as

a differential pair. A √ in the AO column indicates that the pin

pair can be used as an asynchronous output for all devices

provided in this package.

Pairs with a note number in the AO column are device

dependent. They can have asynchronous outputs if the pin

pair is in the same CLB row and column in the device. Num-

bers in this column refer to footnotes that indicate which

devices have pin pairs that can be asynchronous outputs.

The Other Functions column indicates alternative func-

tion(s) not available when the pair is used as a differential

pair or differential clock.

Table 2: BG560 Package Differential Pin Pair Summary

XCV405E and XCV812E

Pair Bank P

AO Other

Functions

Global Differential Clock

3 0 A17 C18 NA IO LVDS 21

2 1 D17 E17 NA IO LVDS 21

1 5 AJ17 AM18 NA IO LVDS 115

0 4 AL17 AM17 NA IO LVDS 115

IO LVDS

Total Outputs: 183, Asyncronous Outputs: 79

00D29E28NA -

10A31D28√-

20C29E27√VREF_0

30D27B301 -

40B29E26√-

50C27D26√VREF_0

60A28E25NA -

70C26D251 -

80B26E241 VREF_0

90D24C251 -

100A25E23√VREF_0

110B24D23√-

12 0 C23 E22 NA -

13 0 D22 A23 √-

140B22E21√VREF_0

15 0 C21 D21 1 -

16 0 E20 B21 √-

170C20D20√VREF_0

18 0 E19 B20 NA -

190C19D191 -

20 0 D18 A19 1 VREF_0

21 1 E17 C18 NA GCLK LVDS 3/2

22 1 B17 C17 1 -

23 1 D16 B16 1 VREF_1

241C16E161 -

251C15A15NA -

26 1 E15 D15 √VREF_1

271D14C14√-

28 1 E14 A13 1 -

291D13C13√VREF_1

30 1 E13 C12 √-

311D12A11NA -

321C11B11√-

331D11B10√VREF_1

34 1 A9 C10 2 -

35 1 D10 C9 1 VREF_1

36 1 B8 A8 1 -

37 1 C8 E10 NA -

38 1 A6 B7 √VREF_1

39 1 D8 C7 √-

40 1 B5 A5 2 -

41 1 D7 C6 √VREF_1

42 1 B4 A4 √-

43 1 E7 C5 NA -

44 1 A2 D6 √CS

45 2 D4 E4 √DIN_D0

46 2 F5 B3 2 -

47 2 F4 C1 NA -

48 2 G5E31 VREF_2

49 2 D2 G4 1 -

Table 2 : BG560 Package Differential Pin Pair Summary

XCV405E and XCV812E

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 11

50 2 H5 E2 NA -

51 2 H4 G3 √VREF_2

52 2 J5 F1 NA -

53 2 J4 H3 2 -

54 2 K5 H2 NA VREF_2

55 2 J3 K4 NA -

56 2 L5 K3 √D1

57 2 L4 K2 √D2

58 2 M5 L3 2 -

59 2 L1 M4 NA -

60 2 N5 M2 1 VREF_2

61 2 N4 N3 1 -

62 2 N2 P5 NA -

63 2 P4 P3 √D3

64 2 P2 R5 2 -

65 2 R4 R3 NA -

66 2 R1 T4 NA VREF_2

67 2 T5 T3 NA -

68 2 T2 U3 √IRDY

69 3 U1 U2 NA -

70 3 V2 V4 NA VREF_3

71 3 V5 V3 NA -

72 3 W1 W3 2 -

73 3 W4 W5 √VREF_3

74 3 Y3 Y4 NA -

75 3 AA1 Y5 1 -

76 3 AA3 AA4 1 VREF_3

77 3 AB3 AA5 NA -

78 3 AC1 AB4 2 -

79 3 AC3 AB5 √D5

80 3 AC4 AD3 √VREF_3

81 3 AE1 AC5 1 -

82 3 AD4 AF1 NA VREF_3

83 3 AF2 AD5 NA -

Table 2: BG560 Package Differential Pin Pair Summary

XCV405E and XCV812E

84 3 AG2 AE4 NA -

85 3 AH1 AE5 √VREF_3

863AF4AJ1NA -

87 3 AJ2 AF5 2 -

88 3 AG4 AK2 1 VREF_3

89 3 AJ3 AG5 NA -

90 3 AL1 AH4 NA -

91 3 AJ4 AH5 √INIT

92 4 AL4 AJ6 √-

93 4 AK5 AN3 NA -

94 4 AL5 AJ7 √-

95 4 AM4 AM5 √VREF_4

96 4 AK7 AL6 1 -

97 4 AM6 AN6 √-

98 4 AL7 AJ9 √VREF_4

99 4 AN7 AL8 NA -

100 4 AM8 AJ10 1 -

101 4 AL9 AM9 1 VREF_4

102 4 AK10 AN9 1 -

103 4 AL10 AM10 √VREF_4

104 4 AL11 AJ12 √-

105 4 AN11 AK12 NA -

106 4 AL12 AM12 √-

107 4 AK13 AL13 √VREF_4

108 4 AM13 AN13 1 -

109 4 AJ14 AK14 √-

110 4 AM14 AN15 √VREF_4

111 4 AJ15 AK15 NA -

112 4 AL15 AM16 1 -

113 4 AL16 AJ16 1 VREF_4

114 4 AK16 AN17 1 -

115 5 AM17 AM18 NA GCLK LVDS 1/0

116 5 AK18 AJ18 1 VREF_5

117 5 AN19 AL19 1 -

Table 2 : BG560 Package Differential Pin Pair Summary

XCV405E and XCV812E

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

12 1-800-255-7778

118 5 AK19 AM20 NA -

119 5 AJ19 AL20 √VREF_5

120 5 AN21 AL21 √-

121 5 AJ20 AM22 1 -

122 5 AK21 AN23 √VREF_5

123 5 AJ21 AM23 √-

124 5 AK22 AM24 NA -

125 5 AL23 AJ22 √-

126 5 AK23 AL24 √VREF_5

127 5 AN26 AJ23 2 -

128 5 AK24 AM26 1 VREF_5

129 5 AM27 AJ24 1 -

130 5 AL26 AK25 NA -

131 5 AN29 AJ25 √VREF_5

132 5 AK26 AM29 √-

133 5 AM30 AJ26 2 -

134 5 AK27 AL29 √VREF_5

135 5 AN31 AJ27 √-

136 5 AM31 AK28 NA -

137 6 AJ30 AH29 √-

138 6 AH30 AK31 2 -

139 6 AJ31 AG29 NA -

140 6 AG30 AK32 1 VREF_6

141 6 AF29 AH31 1 -

142 6 AF30 AH32 NA -

143 6 AH33 AE29 √VREF_6

144 6 AE30 AG33 2 -

145 6 AF32 AD29 NA -

146 6 AD30 AE31 NA VREF_6

147 6 AC29 AE32 NA -

148 6 AC30 AD31 √VREF_6

149 6 AC31 AB29 √-

150 6 AB30 AC33 2 -

151 6 AA29 AB31 NA -

Table 2: BG560 Package Differential Pin Pair Summary

XCV405E and XCV812E

152 6 AA31 AA30 1 VREF_6

153 6 Y29 AA32 1 -

154 6 Y30 AA33 NA -

155 6 W29 Y32 √VREF_6

156 6 W31 W30 2 -

157 6 V30 W33 NA -

158 6 V31 V29 NA VREF_6

159 6 U33 V32 NA -

160 7 U32 U31 √IRDY

161 7 T30 T32 NA -

162 7 T31 T29 NA VREF_7

163 7 R31 R33 NA -

164 7 R29 R30 2 -

165 7 P31 P32 √VREF_7

166 7 P29 P30 NA -

167 7 N31 M32 1 -

168 7 L33 N30 1 VREF_7

169 7 L32 M31 NA -

170 7 L31 M30 2 -

171 7 J33 M29 √-

172 7 K31 L30 √VREF_7

173 7 H33 L29 1 -

174 7 H32 J31 NA VREF_7

175 7 H31 K29 NA -

176 7 G32 J30 NA -

177 7 G31 J29 √VREF_7

178 7 E32 E33 NA -

179 7 F31 H29 2 -

180 7 E31 D32 1 VREF_7

181 7 C33 G29 NA -

182 7 D31 F30 NA -

Notes:

1. AO in the XCV812E

2. AO in the XCV405E

Table 2 : BG560 Package Differential Pin Pair Summary

XCV405E and XCV812E

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 13

FG676 Fine-Pitch Ball Grid Array Package

XCV405E Virtex-E Extended Memory devices are available

in the FG676 fine-pitch BGA package. Pins labeled

I0_VREF can be used as either. If the pin is not used as

VREF

, it can be used as general I/O. Immediately following

Table 3, see Ta b l e 4 for FG676 package Differential Pair

information.

Table 3: FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

0GCK3E13

0IOA6

0IOB3

0IOC6

0IOC8

0IOD5

0IOG13

0IO_L0N_YC4

0 IO_L0P_Y F7

0 IO_L1N_YY G8

0 IO_L1P_YY C5

0 IO_VREF_L2N_YY D6

0 IO_L2P_YY E7

0 IO_L3N A4

0 IO_L3P F8

0 IO_L4N B5

0 IO_L4P D7

0 IO_VREF_L5N_YY E8

0 IO_L5P_YY G9

0 IO_L6N_YY A5

0 IO_L6P_YY F9

0IO_L7N_YD8

0 IO_L7P_Y C7

0IO_L8N_YB7

0 IO_L8P_Y E9

0 IO_L9N A7

0 IO_L9P D9

0 IO_L10N B8

0 IO_VREF_L10P G10

0 IO_L11N_YY C9

0 IO_L11P_YY F10

0 IO_L12N_Y A8

0 IO_L12P_Y E10

0 IO_L13N_YY G11

0 IO_L13P_YY D10

0 IO_L14N_YY B10

0 IO_L14P_YY F11

0 IO_L15N C10

0 IO_L15P E11

0 IO_L16N_YY G12

0 IO_L16P_YY D11

0 IO_VREF_L17N_YY C11

0 IO_L17P_YY F12

0 IO_L18N_YY A11

0 IO_L18P_YY E12

0 IO_L19N_Y D12

0 IO_L19P_Y C12

0 IO_VREF_L20N_Y A12

0 IO_L20P_Y H13

0 IO_LVDS_DLL_L21N B13

1GCK2C13

1IOA19

1IOA20

1IOA22

1IOB23

1 IO_LVDS_DLL_L21P F14

1 IO_L22N E14

1 IO_L22P F13

1 IO_L23N_Y D14

1 IO_VREF_L23P_Y A14

1 IO_L24N_Y C14

1 IO_L24P_Y H14

1 IO_L25N_YY G14

Table 3 : FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

14 1-800-255-7778

1 IO_L25P_YY C15

1 IO_L26N_YY E15

1 IO_VREF_L26P_YY D15

1 IO_L27N_YY C16

1 IO_L27P_YY F15

1 IO_L28N G15

1 IO_L28P D16

1 IO_L29N_YY E16

1 IO_L29P_YY A17

1 IO_L30N_YY C17

1 IO_L30P_YY E17

1 IO_L31N_Y F16

1 IO_L31P_Y D17

1 IO_L32N_YY F17

1 IO_L32P_YY C18

1 IO_L33N_YY A18

1 IO_VREF_L33P_YY G16

1 IO_L34N_YY C19

1 IO_L34P_YY G17

1 IO_L35N_Y D18

1 IO_L35P_Y B19

1 IO_L36N_Y D19

1 IO_L36P_Y E18

1 IO_L37N_YY F18

1 IO_L37P_YY B20

1 IO_L38N_YY G19

1 IO_VREF_L38P_YY C20

1 IO_L39N_YY G18

1 IO_L39P_YY E19

1 IO_L40N_YY A21

1 IO_L40P_YY D20

1 IO_L41N_YY F19

1 IO_VREF_L41P_YY C21

1 IO_L42N_YY B22

1 IO_L42P_YY E20

Table 3: FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

1 IO_L43N_Y A23

1 IO_L43P_Y D21

1 IO_WRITE_L44N_YY C22

1 IO_CS_L44P_YY E21

2IOD26

2IOE26

2IOF26

2IO_D1K24

2 IO_DOUT_BUSY_L45P_YY E23

2 IO_DIN_D0_L45N_YY F22

2 IO_L46P_YY E24

2 IO_L46N_YY F20

2 IO_L47P_Y G21

2 IO_L47N_Y G22

2 IO_VREF_L48P_Y F24

2 IO_L48N_Y H20

2 IO_L49P_Y E25

2 IO_L49N_Y H21

2 IO_L50P_YY F23

2 IO_L50N_YY G23

2 IO_VREF_L51P_YY H23

2 IO_L51N_YY J20

2 IO_L52P_YY G24

2 IO_L52N_YY H22

2 IO_L53P_Y J21

2 IO_L53N_Y G25

2 IO_L54P_Y G26

2 IO_L54N_Y J22

2 IO_L55P_YY H24

2 IO_L55N_YY J23

2 IO_L56P_YY J24

2 IO_VREF_L56N_YY K20

2 IO_D2_L57P_YY K22

2 IO_L57N_YY K21

Table 3 : FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 15

2 IO_L58P_YY H25

2 IO_L58N_YY K23

2 IO_L59P_Y L20

2 IO_L59N_Y J26

2 IO_L60P_Y K25

2 IO_L60N_Y L22

2 IO_L61P_Y L21

2 IO_L61N_Y L23

2 IO_L62P_Y M20

2 IO_L62N_Y L24

2 IO_VREF_L63P_YY M23

2 IO_D3_L63N_YY M22

2 IO_L64P_YY L26

2 IO_L64N_YY M21

2 IO_L65P_Y N19

2 IO_L65N_Y M24

2 IO_VREF_L66P_Y M26

2 IO_L66N_Y N20

2 IO_L67P_YY N24

2 IO_L67N_YY N21

2 IO_L68P_YY N23

2 IO_L68N_YY N22

3IOP24

3IOW25

3IOY26

3IOAB25

3IOAC26

3 IO_L69P_YY P21

3 IO_L69N_YY P23

3 IO_L70P_Y P22

3 IO_VREF_L70N_Y R25

3 IO_L71P_Y P19

3 IO_L71N_Y P20

3 IO_L72P_YY R21

Table 3: FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

3 IO_L72N_YY R22

3 IO_D4_L73P_YY R24

3 IO_VREF_L73N_YY R23

3 IO_L74P_Y T24

3 IO_L74N_Y R20

3 IO_L75P_Y T22

3 IO_L75N_Y U24

3 IO_L76P_Y T23

3 IO_L76N_Y U25

3 IO_L77P_Y T21

3 IO_L77N_Y U20

3 IO_L78P_YY U22

3 IO_L78N_YY V26

3 IO_L79P_YY T20

3 IO_D5_L79N_YY U23

3 IO_D6_L80P_YY V24

3 IO_VREF_L80N_YY U21

3 IO_L81P_YY V23

3 IO_L81N_YY W24

3 IO_L82P_Y V22

3 IO_L82N_Y W26

3 IO_L83P_Y Y25

3 IO_L83N_Y V21

3 IO_L84P_YY V20

3 IO_L84N_YY AA26

3 IO_L85P_YY Y24

3 IO_VREF_L85N_YY W23

3 IO_L86P_Y AA24

3 IO_L86N_Y Y23

3 IO_L87P_Y AB26

3 IO_L87N_Y W21

3 IO_L88P_Y Y22

3 IO_VREF_L88N_Y W22

3 IO_L89P_Y AA23

3 IO_L89N_Y AB24

Table 3 : FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

16 1-800-255-7778

3 IO_L90P_YY W20

3 IO_L90N_YY AC24

3 IO_D7_L91P_YY AB23

3 IO_INIT_L91N_YY Y21

4GCK0AA14

4IOAC18

4IOAE20

4IOAE23

4IOAF21

4 IO_L92P_YY AC22

4 IO_L92N_YY AD26

4 IO_L93P_Y AD23

4 IO_L93N_Y AA20

4 IO_L94P_YY Y19

4 IO_L94N_YY AC21

4 IO_VREF_L95P_YY AD22

4 IO_L95N_YY AB20

4 IO_L96P AE22

4 IO_L96N Y18

4 IO_L97P AF22

4 IO_L97N AA19

4 IO_VREF_L98P_YY AD21

4 IO_L98N_YY AB19

4 IO_L99P_YY AC20

4 IO_L99N_YY AA18

4 IO_L100P_Y AC19

4 IO_L100N_Y AD20

4 IO_L101P_Y AF20

4 IO_L101N_Y AB18

4 IO_L102P AD19

4 IO_L102N Y17

4 IO_L103P AE19

4 IO_VREF_L103N AD18

4 IO_L104P_YY AF19

Table 3: FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

4 IO_L104N_YY AA17

4 IO_L105P_Y AC17

4 IO_L105N_Y AB17

4 IO_L106P_YY Y16

4 IO_L106N_YY AE17

4 IO_L107P_YY AF17

4 IO_L107N_YY AA16

4 IO_L108P AD17

4 IO_L108N AB16

4 IO_L109P_YY AC16

4 IO_L109N_YY AD16

4 IO_VREF_L110P_YY AC15

4 IO_L110N_YY Y15

4 IO_L111P_YY AD15

4 IO_L111N_YY AA15

4 IO_L112P_Y W14

4 IO_L112N_Y AB15

4 IO_VREF_L113P_Y AF15

4 IO_L113N_Y Y14

4 IO_L114P AD14

4 IO_L114N AB14

4 IO_LVDS_DLL_L115P AC14

5 GCK1 AB13

5IOAD7

5IOAD13

5IOAE4

5IOAE7

5IOAF5

5 IO_LVDS_DLL_L115N AF13

5 IO_L116P_Y AA13

5 IO_VREF_L116N_Y AF12

5 IO_L117P_Y AC13

5 IO_L117N_Y W13

5 IO_L118P_YY AA12

Table 3 : FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 17

5 IO_L118N_YY AD12

5 IO_L119P_YY AC12

5 IO_VREF_L119N_YY AB12

5 IO_L120P_YY AD11

5 IO_L120N_YY Y12

5 IO_L121P AB11

5 IO_L121N AD10

5 IO_L122P_YY AC11

5 IO_L122N_YY AE10

5 IO_L123P_YY AC10

5 IO_L123N_YY AA11

5 IO_L124P_Y Y11

5 IO_L124N_Y AD9

5 IO_L125P_YY AB10

5 IO_L125N_YY AF9

5 IO_L126P_YY AD8

5 IO_VREF_L126N_YY AA10

5 IO_L127P_YY AE8

5 IO_L127N_YY Y10

5 IO_L128P_Y AC9

5 IO_L128N_Y AF8

5 IO_L129P_Y AF7

5 IO_L129N_Y AB9

5 IO_L130P_YY AA9

5 IO_L130N_YY AF6

5 IO_L131P_YY AC8

5 IO_VREF_L131N_YY AC7

5 IO_L132P_YY AD6

5 IO_L132N_YY Y9

5 IO_L133P_YY AE5

5 IO_L133N_YY AA8

5 IO_L134P_YY AC6

5 IO_VREF_L134N_YY AB8

5 IO_L135P_YY AD5

5 IO_L135N_YY AA7

Table 3: FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

5 IO_L136P_Y AF4

5 IO_L136N_Y AC5

6IOP3

6IOAA3

6IOW3

6IOY2

6IOY6

6 IO_L137N_YY AA5

6 IO_L137P_YY AC3

6 IO_L138N_YY AC2

6 IO_L138P_YY AB4

6 IO_L139N_Y W6

6 IO_L139P_Y AA4

6 IO_VREF_L140N_Y AB3

6 IO_L140P_Y Y5

6 IO_L141N_Y AB2

6 IO_L141P_Y V7

6 IO_L142N_YY AB1

6 IO_L142P_YY Y4

6 IO_VREF_L143N_YY V5

6 IO_L143P_YY W5

6 IO_L144N_YY AA1

6 IO_L144P_YY V6

6 IO_L145N_Y W4

6 IO_L145P_Y Y3

6 IO_L146N_Y Y1

6 IO_L146P_Y U7

6 IO_L147N_YY W1

6 IO_L147P_YY V4

6 IO_L148N_YY W2

6 IO_VREF_L148P_YY U6

6 IO_L149N_YY V3

6 IO_L149P_YY T5

6 IO_L150N_YY U5

Table 3 : FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

18 1-800-255-7778

6 IO_L150P_YY U4

6 IO_L151N_Y T7

6 IO_L151P_Y U3

6 IO_L152N_Y U2

6 IO_L152P_Y T6

6 IO_L153N_Y U1

6 IO_L153P_Y T4

6 IO_L154N_Y R7

6 IO_L154P_Y T3

6 IO_VREF_L155N_YY R4

6 IO_L155P_YY R6

6 IO_L156N_YY R3

6 IO_L156P_YY R5

6 IO_L157N_Y P8

6 IO_L157P_Y P7

6 IO_VREF_L158N_Y R1

6 IO_L158P_Y P6

6 IO_L159N_YY P5

6 IO_L159P_YY P4

7IOD2

7IOD3

7IOE1

7IOG1

7IOH2

7 IO_L160N_YY N5

7 IO_L160P_YY N8

7 IO_L161N_YY N6

7 IO_L161P_YY N3

7 IO_L162N_Y N4

7 IO_VREF_L162P_Y M2

7 IO_L163N_Y N7

7 IO_L163P_Y M7

7 IO_L164N_YY M6

7 IO_L164P_YY M3

Table 3: FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

7 IO_L165N_YY M4

7 IO_VREF_L165P_YY M5

7 IO_L166N_Y L3

7 IO_L166P_Y L7

7 IO_L167N_Y L6

7 IO_L167P_Y K2

7 IO_L168N_Y L4

7 IO_L168P_Y K1

7 IO_L169N_Y K3

7 IO_L169P_Y L5

7 IO_L170N_YY K5

7 IO_L170P_YY J3

7 IO_L171N_YY K4

7 IO_L171P_YY J4

7 IO_L172N_YY H3

7 IO_VREF_L172P_YY K6

7 IO_L173N_YY K7

7 IO_L173P_YY G3

7 IO_L174N_Y J5

7 IO_L174P_Y H1

7 IO_L175N_Y G2

7 IO_L175P_Y J6

7 IO_L176N_YY J7

7 IO_L176P_YY F1

7 IO_L177N_YY H4

7 IO_VREF_L177P_YY G4

7 IO_L178N_Y F3

7 IO_L178P_Y H5

7 IO_L179N_Y E2

7 IO_L179P_Y H6

7 IO_L180N_Y G5

7 IO_VREF_L180P_Y F4

7 IO_L181N_Y H7

7 IO_L181P_Y G6

7 IO_L182N_YY E3

Table 3 : FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 19

7 IO_L182P_YY E4

2 CCLK D24

3DONEAB21

NA DXN AB7

NA DXP Y8

NA M0 AD4

NA M1 W7

NA M2 AB6

NA PROGRAM AA22

NA TCK E6

NA TDI D22

2 TDO C23

NA TMS F5

0NCA9

0NCA10

0NCB4

0NCB12

0NCD13

1NCA13

1NCA16

1NCA24

1NCB15

1NCB17

2NCD25

2NCH26

2NCK26

2NCM25

2NCN26

3NCAC25

3NCP26

3NCR26

3NCT26

3NCU26

Table 3: FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

4 NC AE15

4NCAF14

4NCAF16

4NCAF18

4NCAF23

5 NC AE12

5NCAF3

5NCAF10

5NCAF11

5NCY13

6NCAC1

6NCP1

6NCR2

6NCT1

6NCV1

7NCD1

7NCJ1

7NCL1

7NCM1

7NCN1

NA NC T25

NA NC T2

NA NC P2

NA NC N25

NA NC L25

NA NC L2

NA NC F6

NA NC F25

NA NC F21

NA NC F2

NA NC C26

NA NC C25

NA NC C2

NA NC C1

NA NC B6

Table 3 : FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

20 1-800-255-7778

NA NC B26

NA NC B24

NA NC B21

NA NC B16

NA NC B11

NA NC B1

NA NC AF25

NA NC AF24

NA NC AF2

NA NC AE6

NA NC AE3

NA NC AE26

NA NC AE24

NA NC AE21

NA NC AE16

NA NC AE14

NA NC AE11

NA NC AE1

NA NC AD25

NA NC AD2

NA NC AD1

NA NC AA6

NA NC AA25

NA NC AA21

NA NC AA2

NA NC A3

NA NC A25

NA NC A2

NA NC A15

NA VCCINT G7

NA VCCINT G20

NA VCCINT H8

NA VCCINT H19

NA VCCINT J9

Table 3: FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

NA VCCINT J10

NA VCCINT J11

NA VCCINT J16

NA VCCINT J17

NA VCCINT J18

NA VCCINT K9

NA VCCINT K18

NA VCCINT L9

NA VCCINT L18

NA VCCINT T9

NA VCCINT T18

NA VCCINT U9

NA VCCINT U18

NA VCCINT V9

NA VCCINT V10

NA VCCINT V11

NA VCCINT V16

NA VCCINT V17

NA VCCINT V18

NA VCCINT Y7

NA VCCINT Y20

NA VCCINT W8

NA VCCINT W19

0 VCCO J13

0 VCCO J12

0 VCCO H9

0 VCCO H12

0 VCCO H11

0 VCCO H10

1 VCCO J15

1 VCCO J14

1 VCCO H18

1 VCCO H17

1 VCCO H16

Table 3 : FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 21

1 VCCO H15

2 VCCO N18

2 VCCO M19

2 VCCO M18

2 VCCO L19

2 VCCO K19

2 VCCO J19

3 VCCO V19

3 VCCO U19

3 VCCO T19

3 VCCO R19

3 VCCO R18

3 VCCO P18

4 VCCO W18

4 VCCO W17

4 VCCO W16

4 VCCO W15

4 VCCO V15

4 VCCO V14

5 VCCO W9

5 VCCO W12

5 VCCO W11

5 VCCO W10

5 VCCO V13

5 VCCO V12

6 VCCO V8

6 VCCO U8

6 VCCO T8

6 VCCO R9

6 VCCO R8

6 VCCO P9

7 VCCO N9

7 VCCO M9

7 VCCO M8

7 VCCO L8

Table 3: FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

7 VCCO K8

7 VCCO J8

NA GND V25

NA GND V2

NA GND U17

NA GND U16

NA GND U15

NA GND U14

NA GND U13

NA GND U12

NA GND U11

NA GND U10

NA GND T17

NA GND T16

NA GND T15

NA GND T14

NA GND T13

NA GND T12

NA GND T11

NA GND T10

NA GND R17

NA GND R16

NA GND R15

NA GND R14

NA GND R13

NA GND R12

NA GND R11

NA GND R10

NA GND P25

NA GND P17

NA GND P16

NA GND P15

NA GND P14

NA GND P13

Table 3 : FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

22 1-800-255-7778

NA GND P12

NA GND P11

NA GND P10

NA GND N2

NA GND N17

NA GND N16

NA GND N15

NA GND N14

NA GND N13

NA GND N12

NA GND N11

NA GND N10

NA GND M17

NA GND M16

NA GND M15

NA GND M14

NA GND M13

NA GND M12

NA GND M11

NA GND M10

NA GND L17

NA GND L16

NA GND L15

NA GND L14

NA GND L13

NA GND L12

NA GND L11

NA GND L10

NA GND K17

NA GND K16

NA GND K15

NA GND K14

NA GND K13

NA GND K12

NA GND K11

Table 3: FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

NA GND K10

NA GND J25

NA GND J2

NA GND E5

NA GND E22

NA GND D4

NA GND D23

NA GND C3

NA GND C24

NA GND B9

NA GND B25

NA GND B2

NA GND B18

NA GND B14

NA GND AF26

NA GND AF1

NA GND AE9

NA GND AE25

NA GND AE2

NA GND AE18

NA GND AE13

NA GND AD3

NA GND AD24

NA GND AC4

NA GND AC23

NA GND AB5

NA GND AB22

NA GND A26

NA GND A1

Table 3 : FG676 Fine-Pitch BGA — XCV405E

Bank Pin Description Pin #

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 23

FG676 Differential Pin Pairs

Virtex-E Extended Memory devices have differential pin

pairs that can also provide other functions when not used as

a differential pair. A √ in the AO column indicates that the pin

pair can be used as an asynchronous output for all devices

provided in this package.

Pairs with a note number in the AO column are device

dependent. They can have asynchronous outputs if the pin

pair is in the same CLB row and column in the device. Num-

bers in this column refer to footnotes that indicate which

devices have pin pairs that can be asynchronous outputs.

The Other Functions column indicates alternative func-

tion(s) not available when the pair is used as a differential

pair or differential clock.

Table 4: FG676 Fine-Pitch BGA Differential Pin Pair

Summary — XCV405E

Pair Bank

Pin AO

Other

Functions

Global Differential Clock

3 0 E13 B13 NA IO_DLL_L21N

2 1 C13 F14 NA IO_DLL_L21P

1 5 AB13 AF13 NA IO_DLL_L115

0 4 AA14 AC14 NA IO_DLL_L115P

IOLVDS

Total Pairs: 183, Asynchronous Output Pairs: 97

0 0 F7 C4 NA -

10C5G8√-

20E7D6√VREF

30F8A4NA -

4 0 D7 B5 NA -

50G9E8√VREF

60F9A5√-

7 0 C7 D8 NA -

8 0 E9 B7 NA -

9 0 D9 A7 NA -

10 0 G10 B8 NA VREF

11 0 F10 C9 √-

12 0 E10 A8 NA -

13 0 D10 G11 √-

14 0 F11 B10 √-

15 0 E11 C10 NA -

16 0 D11 G12 √-

17 0 F12 C11 √VREF

18 0 E12 A11 √-

19 0 C12 D12 NA -

20 0 H13 A12 NA VREF

21 1 F14 B13 NA IO_LVDS_DLL

22 1 F13 E14 NA -

23 1 A14 D14 NA VREF

24 1 H14 C14 NA -

25 1 C15 G14 √-

26 1 D15 E15 √VREF

27 1 F15 C16 √-

28 1 D16 G15 - -

29 1 A17 E16 √-

30 1 E17 C17 √-

31 1 D17 F16 NA -

32 1 C18 F17 √-

33 1 G16 A18 √VREF

34 1 G17 C19 √-

35 1 B19 D18 NA -

36 1 E18 D19 NA -

37 1 B20 F18 √-

38 1 C20 G19 √VREF

39 1 E19 G18 √-

40 1 D20 A21 √-

41 1 C21 F19 √VREF

42 1 E20 B22 √-

43 1 D21 A23 2 -

44 1 E21 C22 √CS

45 2 E23 F22 √DIN, D0

46 2 E24 F20 √-

47 2 G21 G22 2 -

48 2 F24 H20 1 VREF

49 2 E25 H21 1 -

Table 4 : FG676 Fine-Pitch BGA Differential Pin Pair

Summary — XCV405E

Pair Bank

Pin AO

Other

Functions

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

24 1-800-255-7778

50 2 F23 G23 √-

51 2 H23 J20 √VREF

52 2 G24 H22 √-

53 2 J21 G25 2 -

54 2 G26 J22 1 -

55 2 H24 J23 √-

56 2 J24 K20 √VREF

57 2 K22 K21 √D2

58 2 H25 K23 √-

59 2 L20 J26 2 -

60 2 K25 L22 1 -

61 2 L21 L23 1 -

62 2 M20 L24 1 -

63 2 M23 M22 √D3

64 2 L26 M21 √-

65 2 N19 M24 2 -

66 2 M26 N20 1 VREF

67 2 N24 N21 √-

68 2 N23 N22 √-

69 3 P21 P23 √-

70 3 P22 R25 1 VREF

71 3 P19 P20 2 -

72 3 R21 R22 √-

73 3 R24 R23 √VREF

74 3 T24 R20 1 -

75 3 T22 U24 1 -

76 3 T23 U25 1 -

77 3 T21 U20 2 -

78 3 U22 V26 √-

79 3 T20 U23 √D5

80 3 V24 U21 √VREF

81 3 V23 W24 √-

82 3 V22 W26 NA -

83 3 Y25 V21 NA -

Table 4: FG676 Fine-Pitch BGA Differential Pin Pair

Summary — XCV405E

Pair Bank

Pin AO

Other

Functions

84 3 V20 AA26 √-

85 3 Y24 W23 √VREF

86 3 AA24 Y23 NA -

87 3 AB26 W21 NA -

88 3 Y22 W22 NA VREF

89 3 AA23 AB24 NA -

90 3 W20 AC24 √-

91 3 AB23 Y21 √INIT

92 4 AC22 AD26 √-

93 4 AD23 AA20 NA1 -

94 4 Y19 AC21 √-

95 4 AD22 AB20 √VREF

96 4 AE22 Y18 NA -

97 4 AF22 AA19 NA -

98 4 AD21 AB19 √VREF

99 4 AC20 AA18 √-

100 4 AC19 AD20 NA -

101 4 AF20 AB18 NA -

102 4 AD19 Y17 NA -

103 4 AE19 AD18 NA VREF

104 4 AF19 AA17 √-

105 4 AC17 AB17 NA -

106 4 Y16 AE17 √-

107 4 AF17 AA16 √-

108 4 AD17 AB16 NA -

109 4 AC16 AD16 √-

110 4 AC15 Y15 √VREF

111 4 AD15 AA15 √-

112 4 W14 AB15 NA -

113 4 AF15 Y14 NA VREF

114 4 AD14 AB14 NA -

115 5 AC14 AF13 NA IO_LVDS_DLL

116 5 AA13 AF12 NA VREF

117 5 AC13 W13 NA -

Table 4 : FG676 Fine-Pitch BGA Differential Pin Pair

Summary — XCV405E

Pair Bank

Pin AO

Other

Functions

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 25

118 5 AA12 AD12 √-

119 5 AC12 AB12 √VREF

120 5 AD11 Y12 √-

121 5 AB11AD10NA -

122 5 AC11 AE10 √-

123 5 AC10 AA11 √-

124 5 Y11 AD9 NA -

125 5 AB10 AF9 √-

126 5 AD8 AA10 √VREF

127 5 AE8 Y10 √-

128 5 AC9 AF8 NA -

129 5 AF7 AB9 NA -

130 5 AA9 AF6 √-

131 5 AC8 AC7 √VREF

132 5 AD6 Y9 √-

133 5 AE5 AA8 √-

134 5 AC6 AB8 √VREF

135 5 AD5 AA7 √-

136 5 AF4 AC5 NA -

137 6 AC3 AA5 √-

138 6 AB4 AC2 √-

139 6 AA4 W6 NA -

140 6 Y5 AB3 NA VREF

141 6 V7 AB2 NA -

142 6 Y4 AB1 √-

143 6 W5 V5 √VREF

144 6 V6 AA1 √-

145 6 Y3 W4 NA -

146 6 U7 Y1 NA -

147 6 V4 W1 √-

148 6 U6 W2 √VREF

149 6 T5 V3 √-

150 6 U4 U5 √-

151 6 U3 T7 NA -

Table 4: FG676 Fine-Pitch BGA Differential Pin Pair

Summary — XCV405E

Pair Bank

Pin AO

Other

Functions

152 6 T6 U2 NA -

153 6 T4 U1 NA -

154 6 T3 R7 NA -

155 6 R6 R4 √VREF

156 6 R5 R3 √-

157 6 P7 P8 NA -

158 6 P6 R1 NA VREF

159 6 P4 P5 √-

160 7 N8 N5 √-

161 7 N3 N6 √-

162 7 M2 N4 NA VREF

163 7 M7 N7 NA -

164 7 M3 M6 √-

165 7 M5 M4 √VREF

166 7 L7 L3 NA -

167 7 K2 L6 NA -

168 7 K1 L4 NA -

169 7 L5 K3 NA -

170 7 J3 K5 √-

171 7 J4 K4 √-

172 7 K6 H3 √VREF

173 7 G3 K7 √-

174 7 H1 J5 NA -

175 7 J6 G2 NA -

176 7 F1 J7 √-

177 7 G4 H4 √VREF

178 7 H5 F3 NA -

179 7 H6 E2 NA -

180 7 F4 G5 NA VREF

181 7 G6 H7 NA -

182 7 E4 E3 √-

Table 4 : FG676 Fine-Pitch BGA Differential Pin Pair

Summary — XCV405E

Pair Bank

Pin AO

Other

Functions

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

26 1-800-255-7778

FG900 Fine-Pitch Ball Grid Array Package

The XCV812E Virtex-E Extended Memory devices are

available in the FG900 fine-pitch BGA package. Pins

labeled I0_VREF can be used as either. If the pin is not

used as VREF

, it can be used as general I/O. Immediately

following Table 5, see Ta bl e 6 for FG900 package Differen-

tial Pair information.

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

0GCK3C15

0IOA7

0IOA13

0IOC9

0IOC10

0IOD10

0IOE6

0IOF7

0IOF9

0IOF15

0IOG12

0IOG15

0IOH15

0IOJ10

0IOK12

0 IO_VREF A9

0 IO_L1N_Y D5

0 IO_L1P_Y G8

0 IO_L2N_Y A3

0 IO_L2P_Y H9

0 IO_L4N_YY A4

0 IO_L4P_YY D6

0 IO_VREF_L5N_YY E7

0 IO_L5P_YY B5

0IO_L6NA5

0 IO_L6P F8

0IO_L7ND7

0 IO_L7P N11

0 IO_L8N_YY G9

0 IO_L8P_YY E8

0 IO_VREF_L9N_YY A6

0 IO_L9P_YY J11

0 IO_L10N C7

0 IO_L10P B7

0 IO_L11N C8

0 IO_L11P H10

0 IO_L12N_YY G10

0 IO_L12P_YY F10

0 IO_VREF_L13N_YY A8

0 IO_L13P_YY H11

0 IO_L15N B9

0 IO_L15P J12

0 IO_L17N G11

0 IO_L17P B10

0 IO_L19N_Y H13

0 IO_L19P_Y F11

0 IO_L20N_Y E11

0 IO_L20P_Y D11

0 IO_L22N_YY F12

0 IO_L22P_YY C11

0 IO_VREF_L23N_YY A10

0 IO_L23P_YY D12

0 IO_L24N E12

0 IO_L24P A11

0 IO_L25N G13

0 IO_L25P B12

0 IO_L26N_YY A12

0 IO_L26P_YY K13

0 IO_VREF_L27N_YY F13

0 IO_L27P_YY B13

0 IO_L28N G14

0 IO_L28P E13

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 27

0 IO_L29N D14

0 IO_L29P B14

0 IO_L30N_YY A14

0 IO_L30P_YY J14

0 IO_VREF_L31N_YY K14

0 IO_L31P_YY J15

0 IO_LVDS_DLL_L34N A15

1GCk2E15

1IOB18

1IOB21

1IOB28

1IOC23

1IOC26

1IOD20

1IOD23

1 IO_LVDS_DLL_L34P E16

1 IO_L35N B16

1 IO_L35P F16

1 IO_L36N A16

1 IO_L36P H16

1 IO_L37N_YY C16

1 IO_VREF_L37P_YY K15

1 IO_L38N_YY K16

1 IO_L38P_YY G16

1 IO_L39N A17

1 IO_L39P E17

1 IO_L40N F17

1 IO_L40P C17

1 IO_L41N_YY E18

1 IO_VREF_L41P_YY A18

1 IO_L42N_YY D18

1 IO_L42P_YY A19

1 IO_L43N B19

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

1 IO_L43P G18

1 IO_L44N D19

1 IO_L44P H18

1 IO_L45N_YY F18

1 IO_VREF_L45P_YY F19

1 IO_L46N_YY B20

1 IO_L46P_YY K17

1 IO_L48N_Y G19

1 IO_L48P_Y C20

1 IO_L49N_Y K18

1 IO_L49P_Y E20

1 IO_L51N_YY F20

1 IO_L51P_YY A21

1 IO_L52N_YY C21

1 IO_VREF_L52P_YY A22

1 IO_L53N H19

1 IO_L53P B22

1 IO_L54N E21

1 IO_L54P D22

1 IO_L55N_YY F21

1 IO_VREF_L55P_YY C22

1 IO_L56N_YY H20

1 IO_L56P_YY E22

1 IO_L57N G21

1 IO_L57P A23

1 IO_L58N A24

1 IO_L58P K19

1 IO_L59N_YY C24

1 IO_VREF_L59P_YY B24

1 IO_L60N_YY H21

1 IO_L60P_YY G22

1 IO_L61N E23

1 IO_L61P C25

1 IO_L62N D24

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

28 1-800-255-7778

1 IO_L62P A26

1 IO_L63N_YY B26

1 IO_VREF_L63P_YY K20

1 IO_L64N_YY D25

1 IO_L64P_YY J21

1 IO_L66N_Y B27

1 IO_L66P_Y G23

1 IO_L67N_Y A27

1 IO_L67P_Y F24

1 IO_WRITE_L69N_YY K21

1 IO_CS_L69P_YY C27

2IOD28

2IOF27

2IOH25

2IOJ25

2IOJ28

2IOK28

2IOK30

2IOM23

2ION20

2ION23

2IOR27

2IOR28

2IOR30

2 IO_DOUT_BUSY_L70P_YY J22

2 IO_DIN_D0_L70N_YY E27

2 IO_L72P_Y G25

2 IO_L72N_Y E25

2 IO_L73P E28

2 IO_L73N C30

2 IO_L75P D30

2 IO_L75N J23

2 IO_VREF_L76P_Y L21

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

2 IO_L76N_Y F28

2 IO_L77P_YY G28

2 IO_L77N_YY E30

2 IO_L78P G27

2 IO_L78N E29

2 IO_L79P K23

2 IO_L79N H26

2 IO_VREF_L80P_YY F30

2 IO_L80N_YY L22

2 IO_L81P_YY H27

2 IO_L81N_YY G29

2 IO_L82P_Y G30

2 IO_L82N_Y M21

2 IO_L83P J24

2 IO_L83N J26

2 IO_VREF_L84P H30

2 IO_L84N L23

2 IO_L86P J29

2 IO_L86N K24

2 IO_VREF J30

2 IO_D1_L88P M22

2 IO_D2_L88N K29

2 IO_L90P_Y N21

2 IO_L90N_Y K25

2 IO_L91P L24

2 IO_L91N L27

2 IO_L93P L26

2 IO_L93N L28

2 IO_VREF_L94P_Y L30

2 IO_L94N_Y M27

2 IO_L95P_YY M26

2 IO_L95N_YY M29

2 IO_L96P N29

2 IO_L96N M30

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 29

2 IO_L97P N25

2 IO_L97N N27

2 IO_VREF_L98P_YY N30

2 IO_D3_L98N_YY P21

2 IO_L99P_YY N26

2 IO_L99N_YY P28

2 IO_L100P_Y P29

2 IO_L100N_Y N24

2 IO_L101P P22

2 IO_L101N R26

2 IO_VREF_2_L102P P25

2 IO_L102N R29

2 IO_L104P R25

2 IO_L104N T30

2 IO_L106P R24

3IOT24

3IOV24

3IOY21

3IOY27

3IOAB27

3IOAF28

3IOAG30

3 IO_L106N U29

3 IO_L107P R22

3 IO_L107N T27

3 IO_L108P R23

3 IO_L108N T28

3 IO_L109P T21

3 IO_VREF_L109N T25

3 IO_L110P U28

3 IO_L110N U30

3 IO_L111P_Y T23

3 IO_L111N_Y U27

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

3 IO_L112P_YY U25

3 IO_L112N_YY V27

3 IO_D4_L113P_YY U24

3 IO_VREF_L113N_YY V29

3 IO_L114P W30

3 IO_L114N U22

3 IO_L115P U21

3 IO_L115N W29

3 IO_L116P_YY V26

3 IO_L116N_YY W27

3 IO_L117P_Y W26

3 IO_VREF_L117N_Y Y29

3 IO_L118P W25

3 IO_L118N Y30

3 IO_L120P AA30

3 IO_L120N W24

3 IO_L121P_Y AA29

3 IO_L121N_Y V20

3 IO_L123P_YY Y26

3 IO_D5_L123N_YY AB30

3 IO_D6_L124P_YY V21

3 IO_VREF_L124N_YY AA28

3 IO_L125P Y25

3 IO_L125N AA27

3 IO_L126P W22

3 IO_L126N Y23

3 IO_L127P Y24

3 IO_VREF_L127N AB28

3 IO_L128P AC30

3 IO_L128N AA25

3 IO_L129P_Y W21

3 IO_L129N_Y AA24

3 IO_L130P_YY AB26

3 IO_L130N_YY AD30

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

30 1-800-255-7778

3 IO_L131P_YY Y22

3 IO_VREF_L131N_YY AC27

3 IO_L132P AD28

3 IO_L132N AB25

3 IO_L133P AC26

3 IO_L133N AE30

3 IO_L134P_YY AD27

3 IO_L134N_YY AF30

3 IO_L135P_Y AF29

3 IO_VREF_L135N_Y AB24

3 IO_L136P AB23

3 IO_L136N AE28

3 IO_L138P AE26

3 IO_L138N AG29

3 IO_L139P_Y AH30

3 IO_L139N_Y AC24

3 IO_D7_L141P_YY AH29

3 IO_INIT_L141N_YY AA22

4GCK0AJ16

4IOAB19

4IOAC16

4IOAC19

4IOAD19

4IOAD20

4IOAE21

4IOAF19

4IOAH17

4IOAH23

4IOAH26

4IOAH27

4IOAK18

4 IO_VREF_4 AA18

4 IO_L142P_YY AF27

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

4 IO_L142N_YY AK28

4 IO_L144P_Y AD23

4 IO_L144N_Y AJ27

4 IO_L145P_Y AB21

4 IO_L145N_Y AF25

4 IO_L147P_YY AA21

4 IO_L147N_YY AG25

4 IO_VREF_4_L148P_YY AJ26

4 IO_L148N_YY AD22

4 IO_L149P AA20

4 IO_L149N AH25

4 IO_L150P AC21

4 IO_L150N AF24

4 IO_L151P_YY AG24

4 IO_L151N_YY AK26

4 IO_VREF_4_L152P_YY AJ24

4 IO_L152N_YY AF23

4 IO_L153P AE23

4 IO_L153N AB20

4 IO_L154P AC20

4 IO_L154N AG23

4 IO_L155P_YY AF22

4 IO_L155N_YY AE22

4 IO_VREF_4_L156P_YY AJ22

4 IO_L156N_YY AG22

4 IO_L158P AA19

4 IO_L158N AF21

4 IO_L160P AG21

4 IO_L160N AK23

4 IO_L162P_Y AE20

4 IO_L162N_Y AJ21

4 IO_L163P_Y AG20

4 IO_L163N_Y AF20

4 IO_L165P_YY AJ20

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 31

4 IO_L165N_YY AE19

4 IO_VREF_4_L166P_YY AK22

4 IO_L166N_YY AH20

4 IO_L167P AG19

4 IO_L167N AB17

4 IO_L168P AJ19

4 IO_L168N AD17

4 IO_L169P_YY AA16

4 IO_L169N_YY AA17

4 IO_VREF_4_L170P_YY AK21

4 IO_L170N_YY AB16

4 IO_L171P AG18

4 IO_L171N AK20

4 IO_L172P AK19

4 IO_L172N AD16

4 IO_L173P_YY AE16

4 IO_L173N_YY AE17

4 IO_VREF_4_L174P_YY AG17

4 IO_L174N_YY AJ17

4 IO_L176P AG16

4 IO_L176N AK17

4 IO_LVDS_DLL_L177P AF16

5GCK1AK16

5IOAD8

5IOAD14

5IOAE10

5IOAE12

5IOAG15

5IOAH5

5IOAH8

5IOAK12

5 IO_LVDS_DLL_L177N AH16

5 IO_L179P AB15

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

5 IO_L179N AF15

5 IO_L180P_YY AA15

5 IO_VREF_5_L180N_YY AF14

5 IO_L181P_YY AH15

5 IO_L181N_YY AK15

5 IO_L182P AB14

5 IO_L182N AF13

5 IO_L183P AH14

5 IO_L183N AJ14

5 IO_L184P_YY AE14

5 IO_VREF_5_L184N_YY AG13

5 IO_L185P_YY AK13

5 IO_L185N_YY AD13

5 IO_L186P AE13

5 IO_L186N AF12

5 IO_L187P AC13

5 IO_L187N AA13

5 IO_L188P_YY AA12

5 IO_VREF_5_L188N_YY AJ12

5 IO_L189P_YY AB12

5 IO_L189N_YY AE11

5 IO_L191P_Y AG11

5 IO_L191N_Y AF11

5 IO_L192P_Y AH11

5 IO_L192N_Y AJ11

5 IO_L194P_YY AD12

5 IO_L194N_YY AK11

5 IO_L195P_YY AJ10

5 IO_VREF_5_L195N_YY AC12

5 IO_L196P AK10

5 IO_L196N AD11

5 IO_L197P AJ9

5 IO_L197N AE9

5 IO_L198P_YY AH10

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

32 1-800-255-7778

5 IO_VREF_5_L198N_YY AF9

5 IO_L199P_YY AH9

5 IO_L199N_YY AK9

5 IO_L200P AF8

5 IO_L200N AB11

5 IO_L201P AC11

5 IO_L201N AG8

5 IO_L202P_YY AK8

5 IO_VREF_5_L202N_YY AF7

5 IO_L203P_YY AG7

5 IO_L203N_YY AK7

5 IO_L204P AJ7

5 IO_L204N AD10

5 IO_L205P AH6

5 IO_L205N AC10

5 IO_L206P_YY AD9

5 IO_VREF_5_L206N_YY AG6

5 IO_L207P_YY AB10

5 IO_L207N_YY AJ5

5 IO_L209P_Y AC9

5 IO_L209N_Y AJ4

5 IO_L210P_Y AG5

5 IO_L210N_Y AK4

6IOT6

6IOU1

6IOU6

6IOV7

6IOV8

6IOW10

6IOY10

6 IO AA2

6 IO AA4

6IOAD1

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

6IOAD6

6IOAG2

6 IO_L212N_YY AF3

6 IO_L212P_YY AC6

6 IO_L214N_Y AB9

6 IO_L214P_Y AE4

6 IO_L215N AE3

6 IO_L215P AH1

6 IO_L217N AG1

6 IO_L217P AA10

6 IO_VREF_L218N_Y AA9

6 IO_L218P_Y AD4

6 IO_L219N_YY AD5

6 IO_L219P_YY AD2

6 IO_L220N AD3

6 IO_L220P AF2

6 IO_L221N AA8

6 IO_L221P AA7

6 IO_VREF_L222N_YY AF1

6 IO_L222P_YY Y9

6 IO_L223N_YY AB6

6 IO_L223P_YY AC4

6 IO_L224N_Y AE1

6 IO_L224P_Y W8

6 IO_L225N Y8

6 IO_L225P AB4

6 IO_VREF_L226N AB3

6 IO_L226P W9

6 IO_L228N AB1

6 IO_L228P V10

6 IO_VREF AC1

6 IO_L230N V11

6 IO_L230P AA3

6 IO_L232N_Y W7

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 33

6 IO_L232P_Y AA6

6 IO_L233N Y6

6 IO_L233P Y4

6 IO_L235N Y3

6 IO_L235P Y2

6 IO_VREF_L236N_Y Y5

6 IO_L236P_Y W5

6 IO_L237N_YY W4

6 IO_L237P_YY W6

6 IO_L238N V6

6 IO_L238P W2

6 IO_L239N U9

6 IO_L239P V4

6 IO_VREF_L240N_YY AB2

6 IO_L240P_YY T8

6 IO_L241N_YY U5

6 IO_L241P_YY W1

6 IO_L242N_Y Y1

6 IO_L242P_Y T9

6 IO_L243N T7

6 IO_L243P U3

6 IO_VREF_L244N T5

6 IO_L244P V2

6 IO_L246N T4

6 IO_L246P U2

6 IO_L247N T1

7IOD1

7IOE3

7IOJ4

7IOJ6

7IOK10

7IOL3

7IOM7

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

7ION8

7IOR5

7 IO_L247P R10

7 IO_L249N R8

7 IO_L249P R4

7 IO_L250N R7

7 IO_L250P R3

7 IO_L251N P10

7 IO_VREF_L251P P6

7 IO_L252N P5

7 IO_L252P P2

7 IO_L253N_Y P7

7 IO_L253P_Y P4

7 IO_L254N_YY N4

7 IO_L254P_YY R2

7 IO_L255N_YY N7

7 IO_VREF_L255P_YY P1

7 IO_L256N M6

7 IO_L256P N6

7 IO_L257N N5

7 IO_L257P N1

7 IO_L258N_YY M4

7 IO_L258P_YY M5

7 IO_L259N_Y M2

7 IO_VREF_L259P_Y M1

7 IO_L260N L4

7 IO_L260P L2

7 IO_L262N L1

7 IO_L262P M8

7 IO_L263N_Y K2

7 IO_L263P_Y M9

7 IO_L265N_YY K5

7 IO_L265P_YY K1

7 IO_L266N_YY L6

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

34 1-800-255-7778

7 IO_VREF_L266P_YY K3

7 IO_L267N L7

7 IO_L267P K4

7 IO_L268N L8

7 IO_L268P J5

7 IO_L269N K6

7 IO_VREF_L269P H4

7 IO_L270N H1

7 IO_L270P K7

7 IO_L271N_Y J7

7 IO_L271P_Y J2

7 IO_L272N_YY H5

7 IO_L272P_YY G2

7 IO_L273N_YY L9

7 IO_VREF_L273P_YY G5

7 IO_L274N F3

7 IO_L274P K8

7 IO_L275N G3

7 IO_L275P E1

7 IO_L276N_YY H6

7 IO_L276P_YY E2

7 IO_L277N_Y E4

7 IO_VREF_L277P_Y K9

7 IO_L278N J8

7 IO_L278P F4

7 IO_L280N G6

7 IO_L280P C2

7 IO_L281N_Y D2

7 IO_L281P_Y F5

2DONEAJ28

NA DXN AJ3

NA DXP AH4

3 CCLK F26

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

NA M0 AF4

NA M1 AC7

NA M2 AK3

NA PROGRAM AG28

NA TCK B3

NA TDI H22

2 TDO D26

NA TMS C1

NA VCCINT L11

NA VCCINT L12

NA VCCINT L19

NA VCCINT L20

NA VCCINT M11

NA VCCINT M12

NA VCCINT M19

NA VCCINT M20

NA VCCINT N13

NA VCCINT N14

NA VCCINT N15

NA VCCINT N16

NA VCCINT N17

NA VCCINT N18

NA VCCINT P13

NA VCCINT P18

NA VCCINT R13

NA VCCINT R18

NA VCCINT T13

NA VCCINT T18

NA VCCINT U18

NA VCCINT U13

NA VCCINT V13

NA VCCINT V14

NA VCCINT V15

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 35

NA VCCINT V16

NA VCCINT V17

NA VCCINT V18

NA VCCINT W11

NA VCCINT W12

NA VCCINT W19

NA VCCINT W20

NA VCCINT Y11

NA VCCINT Y12

NA VCCINT Y19

NA VCCINT Y20

NA VCCO_0 B6

NA VCCO_0 M15

NA VCCO_0 M14

NA VCCO_0 L15

NA VCCO_0 L14

NA VCCO_0 H14

NA VCCO_0 M13

NA VCCO_0 C12

NA VCCO_1 B25

NA VCCO_1 C19

NA VCCO_1 M18

NA VCCO_1 M17

NA VCCO_1 L17

NA VCCO_1 H17

NA VCCO_1 L16

NA VCCO_1 M16

NA VCCO_2 F29

NA VCCO_2 M28

NA VCCO_2 P23

NA VCCO_2 R20

NA VCCO_2 P20

NA VCCO_2 R19

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

NA VCCO_2 N19

NA VCCO_2 P19

NA VCCO_3 AE29

NA VCCO_3 W28

NA VCCO_3 U23

NA VCCO_3 U20

NA VCCO_3 T20

NA VCCO_3 V19

NA VCCO_3 T19

NA VCCO_3 U19

NA VCCO_4 AJ25

NA VCCO_4 AH19

NA VCCO_4 W18

NA VCCO_4 AC17

NA VCCO_4 Y17

NA VCCO_4 W17

NA VCCO_4 W16

NA VCCO_4 Y16

NA VCCO_5 AJ6

NA VCCO_5 Y15

NA VCCO_5 W15

NA VCCO_5 AC14

NA VCCO_5 Y14

NA VCCO_5 W14

NA VCCO_5 W13

NA VCCO_5 AH12

NA VCCO_6 AE2

NA VCCO_6 V12

NA VCCO_6 U12

NA VCCO_6 T12

NA VCCO_6 U11

NA VCCO_6 T11

NA VCCO_6 U8

NA VCCO_6 W3

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

36 1-800-255-7778

NA VCCO_7 F2

NA VCCO_7 R12

NA VCCO_7 P12

NA VCCO_7 N12

NA VCCO_7 R11

NA VCCO_7 P11

NA VCCO_7 P8

NA VCCO_7 M3

NA GND Y18

NA GND AH7

NA GND AK30

NA GND AJ30

NA GND B30

NA GND A30

NA GND AK29

NA GND AJ29

NA GND AC29

NA GND H29

NA GND B29

NA GND A29

NA GND AH28

NA GND V28

NA GND N28

NA GND C28

NA GND AG27

NA GND D27

NA GND AF26

NA GND E26

NA GND F25

NA GND AE25

NA GND G24

NA GND AJ23

NA GND AD24

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

NA GND H23

NA GND B23

NA GND AC23

NA GND AB22

NA GND V22

NA GND N22

NA GND AH18

NA GND AB18

NA GND J18

NA GND C18

NA GND U17

NA GND T17

NA GND R17

NA GND P17

NA GND U16

NA GND T16

NA GND R16

NA GND P16

NA GND U15

NA GND T15

NA GND R15

NA GND P15

NA GND U14

NA GND T14

NA GND R14

NA GND P14

NA GND AH13

NA GND AB13

NA GND J13

NA GND C13

NA GND V9

NA GND N9

NA GND J9

NA GND AJ8

Table 5 : FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 37

FG900 Differential Pin Pairs

Virtex-E Extended Memory devices have differential pin

pairs that can also provide other functions when not used as

a differential pair. A √ in the AO column indicates that the pin

pair can be used as an asynchronous output for all devices

provided in this package.

Pairs with a note number in the AO column are device

dependent. They can have asynchronous outputs if the pin

pair is in the same CLB row and column in the device. Num-

bers in this column refer to footnotes that indicate which

devices have pin pairs that can be asynchronous outputs.

The Other Functions column indicates alternative func-

tion(s) not available when the pair is used as a differential

pair or differential clock.

NA GND AC8

NA GND H8

NA GND AD7

NA GND B8

NA GND AE6

NA GND G7

NA GND F6

NA GND AF5

NA GND E5

NA GND AG4

NA GND D4

NA GND V3

NA GND N3

NA GND C3

NA GND AK2

NA GND AH3

NA GND AC2

NA GND H2

NA GND B2

NA GND A2

NA GND AK1

NA GND AJ2

NA GND AJ1

NA GND A1

NA GND B1

Table 5: FG900 Fine-Pitch BGA Package — XCV812E

Bank Description Pin

Table 6 : FG900 Differential Pin Pair Summary —

XCV812E

Pair Bank

Pin AO

Other

Functions

GCLK LVDS

3 0 C15 A15 NA IO LVDS 34

2 1 E15 E16 NA IO LVDS 34

1 5 AK16 AH16 NA IO LVDS 177

0 4 AJ16 AF16 NA IO LVDS 177

IO LVDS

Total Pairs: 235, Asynchronous Output Pairs: 85

10G8D5√-

20H9A3√-

40D6A4√-

50B5E7√VREF

60F8A5- -

70N11D7- -

80E8G9√-

90J11A6√VREF

100B7C7- -

110H10C8 - -

12 0 F10 G10 √-

130H11A8 √VREF

15 0 J12 B9 - -

17 0 B10 G11 - -

19 0 F11 H13 √-

200D11E11√-

220C11F12√-

230D12A10√VREF

24 0 A11 E12 - -

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

38 1-800-255-7778

25 0 B12 G13 - -

26 0 K13 A12 √-

27 0 B13 F13 √VREF

28 0 E13 G14 - -

29 0 B14 D14 - -

30 0 J14 A14 √-

31 0 J15 K14 √VREF

34 1 E16 A15 - GCLK LVDS 3/2

35 1 F16 B16 - -

36 1 H16 A16 - -

37 1 K15 C16 √VREF

38 1 G16 K16 √-

39 1 E17 A17 - -

40 1 C17 F17 - -

41 1 A18 E18 √VREF

42 1 A19 D18 √-

43 1 G18 B19 - -

44 1 H18 D19 - -

45 1 F19 F18 √VREF

46 1 K17 B20 √-

48 1 C20 G19 √-

49 1 E20 K18 √-

51 1 A21 F20 √-

52 1 A22 C21 √VREF

53 1 B22 H19 - -

54 1 D22 E21 - -

55 1 C22 F21 √VREF

56 1 E22 H20 √-

57 1 A23 G21 - -

58 1 K19 A24 - -

59 1 B24 C24 √VREF

60 1 G22 H21 √-

61 1 C25 E23 - -

62 1 A26 D24 - -

63 1 K20 B26 √VREF

64 1 J21 D25 √-

66 1 G23 B27 √-

Table 6: FG900 Differential Pin Pair Summary —

XCV812E

Pair Bank

Pin AO

Other

Functions

67 1 F24 A27 √-

691C27K21√CS

70 2 J22 E27 √DIN_D0

72 2 G25 E25 √-

732E28C30- -

752D30J23 - -

76 2 L21 F28 √VREF

77 2 G28 E30 √-

78 2 G27 E29 - -

792K23H26- -

80 2 F30 L22 √VREF

812H27G29√-

82 2 G30 M21 √-

832J24J26- -

84 2 H30 L23 - VREF

86 2 J29 K24 - -

88 2 M22 K29 - D2

902N21K25√-

91 2 L24 L27 - -

93 2 L26 L28 - -

94 2 L30 M27 √VREF

95 2 M26 M29 √-

962N29M30- -

972N25N27- -

982N30P21√D3

992N26P28√-

100 2 P29 N24 √-

101 2 P22 R26 - -

102 2 P25 R29 - VREF

104 2 R25 T30 - -

106 3 R24 U29 - TRDY

107 3 R22 T27 - -

108 3 R23 T28 - -

109 3 T21 T25 - VREF

110 3 U28 U30 - -

111 3 T23 U27 √-

112 3 U25 V27 √-

Table 6 : FG900 Differential Pin Pair Summary —

XCV812E

Pair Bank

Pin AO

Other

Functions

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 39

113 3 U24 V29 √VREF

114 3 W30 U22 - -

115 3 U21 W29 - -

116 3 V26 W27 √-

117 3 W26 Y29 √VREF

118 3 W25 Y30 - -

120 3 AA30 W24 - -

121 3 AA29 V20 √-

123 3 Y26 AB30 √D5

124 3 V21 AA28 √VREF

125 3 Y25 AA27 - -

126 3 W22 Y23 - -

127 3 Y24 AB28 - VREF

128 3 AC30 AA25 - -

129 3 W21 AA24 √-

130 3 AB26 AD30 √-

131 3 Y22 AC27 √VREF

132 3 AD28 AB25 - -

133 3 AC26 AE30 - -

134 3 AD27 AF30 √-

1353AF29AB24√VREF

136 3 AB23 AE28 - -

138 3 AE26 AG29 - -

139 3 AH30 AC24 √-

141 3 AH29 AA22 √INIT

1424AF27AK28√-

144 4 AD23 AJ27 √-

145 4 AB21 AF25 √-

147 4 AA21 AG25 √-

148 4 AJ26 AD22 √VREF

149 4 AA20 AH25 - -

150 4 AC21 AF24 - -

151 4 AG24 AK26 √-

152 4 AJ24 AF23 √VREF

153 4 AE23 AB20 - -

154 4 AC20 AG23 - -

1554AF22AE22√-

Table 6: FG900 Differential Pin Pair Summary —

XCV812E

Pair Bank

Pin AO

Other

Functions

156 4 AJ22 AG22 √VREF

158 4 AA19 AF21 - -

160 4 AG21 AK23 - -

162 4 AE20 AJ21 √-

163 4 AG20 AF20 √-

165 4 AJ20 AE19 √-

166 4 AK22 AH20 √VREF

167 4 AG19 AB17 - -

168 4 AJ19 AD17 - -

169 4 AA16 AA17 √-

170 4 AK21 AB16 √VREF

171 4 AG18 AK20 - -

172 4 AK19 AD16 - -

173 4 AE16 AE17 √-

174 4 AG17 AJ17 √VREF

176 4 AG16 AK17 - -

177 5 AF16 AH16 - GCLK LVDS 1/0

179 5 AB15 AF15 - -

180 5 AA15 AF14 √VREF

181 5 AH15 AK15 √-

182 5 AB14 AF13 - -

183 5 AH14 AJ14 - -

184 5 AE14 AG13 √VREF

185 5 AK13 AD13 √-

186 5 AE13 AF12 - -

187 5 AC13 AA13 - -

188 5 AA12 AJ12 √VREF

189 5 AB12 AE11 √-

191 5 AG11 AF11 √-

192 5 AH11 AJ11 √-

194 5 AD12 AK11 √-

195 5 AJ10 AC12 √VREF

196 5 AK10 AD11 - -

197 5 AJ9 AE9 - -

198 5 AH10 AF9 √VREF

199 5 AH9 AK9 √-

200 5 AF8 AB11 - -

Table 6 : FG900 Differential Pin Pair Summary —

XCV812E

Pair Bank

Pin AO

Other

Functions

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

40 1-800-255-7778

201 5 AC11 AG8 - -

202 5 AK8 AF7 √VREF

203 5 AG7 AK7 √-

204 5 AJ7 AD10 - -

205 5 AH6 AC10 - -

206 5 AD9 AG6 √VREF

207 5 AB10 AJ5 √-

209 5 AC9 AJ4 √-

210 5 AG5 AK4 √-

212 6 AC6 AF3 √-

214 6 AE4 AB9 √-

215 6 AH1 AE3 - -

217 6 AA10 AG1 - -

218 6 AD4 AA9 √VREF

219 6 AD2 AD5 √-

220 6 AF2 AD3 - -

221 6 AA7 AA8 - -

222 6 Y9 AF1 √VREF

223 6 AC4 AB6 √-

224 6 W8 AE1 √-

225 6 AB4 Y8 - -

226 6 W9 AB3 - VREF

228 6 V10 AB1 - -

230 6 AA3 V11 - -

232 6 AA6 W7 √-

233 6 Y4 Y6 - -

235 6 Y2 Y3 - -

236 6 W5 Y5 √VREF

237 6 W6 W4 √-

238 6 W2 V6 - -

239 6 V4 U9 - -

240 6 T8 AB2 √VREF

241 6 W1 U5 √-

242 6 T9 Y1 √-

243 6 U3 T7 - -

244 6 V2 T5 - VREF

246 6 U2 T4 - -

Table 6: FG900 Differential Pin Pair Summary —

XCV812E

Pair Bank

Pin AO

Other

Functions

247 7 R10 T1 - IRDY

249 7 R4 R8 - -

250 7 R3 R7 - -

251 7 P6 P10 - VREF

2527P2P5- -

253 7 P4 P7 √-

254 7 R2 N4 √-

255 7 P1 N7 √VREF

256 7 N6 M6 - -

257 7 N1 N5 - -

258 7 M5 M4 √-

259 7 M1 M2 √VREF

260 7 L2 L4 - -

262 7 M8 L1 - -

263 7 M9 K2 √-

265 7 K1 K5 √-

266 7 K3 L6 √VREF

267 7 K4 L7 - -

2687J5L8- -

269 7 H4 K6 - VREF

2707K7H1- -

271 7 J2 J7 √-

272 7 G2 H5 √-

273 7 G5 L9 √VREF

274 7 K8 F3 - -

275 7 E1 G3 - -

276 7 E2 H6 √-

277 7 K9 E4 √VREF

278 7 F4 J8 - -

280 7 C2 G6 - -

281 7 F5 D2 - -

Table 6 : FG900 Differential Pin Pair Summary —

XCV812E

Pair Bank

Pin AO

Other

Functions

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-4 (v1.6) July 17, 2002 www.xilinx.com Module 4 of 4

1-800-255-7778 41

Virtex-E Extended Memory Device/Package Combinations and Maximum I/O

Virtex-E Ordering Information

Virtex-II ordering information is shown in Figure 1

Virtex-E Extended Memory Series Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)

Package XCV405E XCV812E

BG560 404 404

FG676 404

FG900 556

Figure 1: Virtex Ordering Information

Example: XCV405E-6BG560C

Device Type Temperature Range

C = Commercial (TJ = 0˚C to +85˚C)

I = Industrial (TJ = −40˚C to +100˚C)

Number of Pins

Package Type

BG = Ball Grid Array

FG = Fine Pitch Ball Grid Array

Speed Grade

(-6, -7, -8)

DS025_001_112000

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 4 of 4 www.xilinx.com DS025-4 (v1.6) July 17, 2002

42 1-800-255-7778

Revision History

The following table shows the revision history for this document.

Virtex-E Extended Memory Data Sheet

The Virtex-E Extended Memory Data Sheet contains the following modules:

•DS025-1, Virtex-E 1.8V Extended Memory FPGAs:

Introduction and Ordering Information (Module 1)

•DS025-2, Virtex-E 1.8V Extended Memory FPGAs:

Functional Description (Module 2)

•DS025-3, Virtex-E 1.8V Extended Memory FPGAs:

DC and Switching Characteristics (Module 3)

•DS025-4, Virtex-E 1.8V Extended Memory FPGAs:

Pinout Tables (Module 4)

Date Version Revision

03/23/00 1.0 Initial Xilinx release.

08/01/00 1.1 Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added. Reformatted

to adhere to corporate documentation style guidelines. Minor changes in BG560 pin-out table.

09/19/00 1.2 •In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no longer

labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.

•Min values added to Virtex-E Electrical Characteristics tables.

11/20/00 1.3 •Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables (Module 3).

•Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).

•Added to note 2 of Absolute Maximum Ratings (Module 3).

•Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL

Standard, with DLL (Module 3).

•Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).

04/02/01 1.4 •In Tabl e 4, FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF, and

pin G16 is now labeled as VREF.

•Updated values in Virtex-E Switching Characteristics tables.

•Converted data sheet to modularized format. See the Virtex-E Extended Memory Data

Sheet section.

07/23/01 1.5 •Changed definition of T31 and T32 pins in Table 1 for XCV405E and the XCV812E devices.

07/17/02 1.6 •Data sheet designation upgraded from Preliminary to Production.