SECTION 6 Neuron CHIP ELECTRICAL AND MECHANICAL SPECIFICATIONS 6.1 INTRODUCTION The Neuron Chip processor family consists of two device types: MC143150 and MC 143120. Within these device types are different versions, each with its own electrical and mechanical specifications. The MC143150B1FU/B1FU1 and MC143120B1/E2DW operate up to 10 MHz over the full industrial tempera- ture range of 40 to + 85C, including writes to EEPROM down to 40C. Memory interface timing is differ- ent for all MC143150xx devices. (See Sections 6.2.4 and 6.2.9) Refer to Appendix C in this data book for more information on external memory interfacing. When deciding at what speed to operate the MC 143150, the cost of the external memory will be an impor- tant consideration. There is a cost difference between a 200 ns memory (EPROM access time required at 5 MHz) and a 120 ns memory (10 MHz access time) which is rated over the full industrial temperature range, particularly in surface mount packages. For multiple memory configurations (external EPROM, EEPROM, flash, and/or SRAM), additional cost savings due to slower memory map decode logic, and lower cost of the memory, can be realized at 5 MHz operation. Power consumption will be 30 40% lower at 5 MHz than at 10 MHz. Issues such as required data rate and I/O response time must be considered. Running the Neuron Chip ata higher clock rate decreases the processing time. Proper prioritizing of when statements in the application program and use of timer counter objects can help to minimize latency. Refer to Section D.2 regarding handling precautions and moisture sensitivity of the various Neuron de- vices. NOTE: The MC143150FU, MC143150FU1, and MC143150B1FU devices are no longer available, but data regarding these devices are included in this section. The MC143150B1FU1 is recommended for new designs. MOTOROLA LonWorks TECHNOLOGY MC143150eMC143120 SECTION 6 6-3 MB 6367253 0103bb4 334 a a6.2 ELECTRICAL SPECIFICATIONS 6.2.1 Absolute Maximum Ratings Parameter Symbol Value Unit Supply Voltage Range (Referenced to Vgs) Vpp -0.3 to 7.0V v Input Voltage Range (Referenced to Vss) Vin - ~- 0.3 to Vop + 0.3 vo Maximum Drain Current : lop 200 mA Maximum Source Current Iss "300 | mA Maximum Power Dissipation Pp 800 mw Operating Temperature Ta 40 to + 85 C Storage Temperature Range : Tstg -65 to+150 C 6.2.2 Recommended Operating Conditions (Voltages referenced to Vgs, Ta = 40 to + 85C) Parameter Symbol Min . Max Unit Supply Voltage VoD : 4.5 5.5 : v TTL Low-Level Input Voltage Vit Vss . 0.8 v TTL High-Level Input Voltage VIH 2.0 Vpb Vv CMOS Low-Level Input Voltage Vit Ves 0.8 Vv CMOS High-Level Input Voltage VIH Vpp - 0.8 of Vpb Vv Operating FreeAir Temperature Ta 40 +85 C *Writes to EEPROM are guaranteed down to - 20C @ all frequencies for MC143150FU and MC1431 20DW devices and down to - 40C @ all frequencies for alt other Neuron Chip devices. 6.2.3 Electrical Characteristics (Vpp = 4.5 to 5.5 V) Parameter Symbol Min Typ Max Unit input Low Voltage VIL Vv 100 - 1010, DO ~ D7, CPO, CP3, CP4, SERVICE 0.8 CPO, CP1 (Differential) (See Section 6.2.10) _ _ Programmable Reset (MC143150FU, FU1, MC143120DW) 0.8 Reset (MC143150B1FU, B1FU1, E2)} 0.3 Vpp Input High Voltage VIH Vv 100 - 1010, DO~ D7, CPO, CP3, CP4, service pin 2.0 ~~ _ CPO, CP1 (Differential) (See Section 6.2.10) Programmable _ _ Reset (MC143150FU, FU1, MC143120DW) : Vpp 0.7 Reset (MC143150B1FU, BIFU1, E2) - Vpb -0.7 Low-Level Output Voltage VOL Vv Standard Outputs (IoL = 1.4 mA) (Note 1) _ _ 0.4 High Sink (100 103), SERVICE, RESET (IoL= 20 mA) _~ _ 0.8 High Sink (100 - 103), SERVICE, RESET (loL= 10 mA) - _ 0.4 Maximum Sink (CP2, CP3) (IgoL= 40 mA) 1.0 Maximum Sink (CP2, CP3) (lo, = 15 mA) _ 0.4 High-Level Output Voltage VOH Vv Standard Outputs (IoH = 1.4 mA) (Note 1) Vop - 0.4 - _ High Sink (100 - 103), SERVICE (lop = 1.4 mA) Vop - 0.4 _ _ Maximum Source (CP2, CP3) (loH = 40 mA) Vpp - 1.0 - - Maximum Source (CP2, CP3) (loy = 15 mA) Vpp 0.4 _ _ Hysteresis (Excluding CLK1, RESET) Vhys 175 _ _ mV Input Current (Excluding pullups) (Vgg to Vpp) (Note 2) lin - 10 _ 10 pA MC143150eMC143120 SECTION 6 MOTOROLA LonWorks TECHNOLOGY 6-4 MB 6367253 0103665 270Parameter Symbol M MC143150B1FU, B1FU1 in Typ Max | Unit Pullup Source Current (Vout = 0 V, Output = High-Z) (Note 2) 'pu 60 _ 260 pA Operating Mode Supply Current (Notes 3, 4) mA 10 MHz Clock _ 15 25 5 MHz Clock _ 8 13 2.5 MHz Clock _ 45 7 1.25 MHz Clack _ 2.4 4.2 0.625 MHz Clock _ 1.5 2.5 Sleep Mode Supply Current (Notes 3, 4) ~~? 15 100 pA wer MC143150FU, FU1 se Pullup Source Current (Voyt = 0 V, Output = High-Z) (Note 2) Ipu Ley 30 300 pA Operating Mode Supply Current (Notes 3, 4) a mA TOMHz Clock] _ 32 60 5 MHz Clock eo 22 40 2.5 MHz Clock _ 16 32 1.25 MHz Cl _ 13 27 0.625 MHasiock = 12 25 Sleep Mode Supply Current (Notes 3, 4) & _ 0.5 2 mA MC143120B1DW g Pullup Source Current (Vout = 0 V, Output = High-Z) (Note 2) Ipu 60 _ 260 pA Operating Mode Supply Current (Notes 3, 4, and 5) mA 10 MHz Clock _ 14 25 5 MHz Clock : _ 7.5 13 2.5 MHz Clock _ 45 7 1.25 MHz Clock _ 3.2 4.2 0.625 MHz Clock _ 1.6 2.5 Sleep Mode Supply Current (Note 3,4) , 9 100 pA MC143120DW RA Pullup Source Current (Voyt = 0 V, Output = High-Z) (Note 2) 'bu LOY 30 _ 300 pA Operating Mode Supply Current (Notes 3, 5) a mA 10 MHz Clock ow = 36 60 5 MHz Clock oe _ 22 38 2.5 MHz Clock }/ _ 16 26 1.25 MHz Cl _ 10 22 0.625 MHefiock - 8 18 Sleep Mode Supply Current (Notes 3, 5) oe - 0.6 2 mA MC143120E2DW g Pullup Source Current (Voyt = 0 V, Output = High-Z)} (Note 2) pu 60 260 pA Operating Mode Supply Current (Notes 3, 5) mA 10 MHz Clock _ 16 N/A 5 MHz Clock ad B 2.5 MHz Clock _ 5.0 1.25 MHz Clock _ 3.5 0.625 MHz Clock _ 1.8 Sleep Mode Supply Current (Notes 3, 5) _ 9 100 pA NOTES: _ _ 1. Standard outputs are AO A15, DO- D7, 104-1010, CPO, CP1, CP4, E, and R/W. (RESET is a CMOS open drain input/output. CLK2 must have < 15 pF. 2. 104 -107 and SERVICE have configurable pullups. RESET has a permanent pullup. 3. Supply current measurement conditions: all outputs under noload conditions, all inputs < 0.2 V or 2 (Vpp 0.2 V}), configurable pullups off, crystal oscillator clock input, differential receiver disabled. The differential receiver adds approximately 200 pA typical and 600 A maximum when enabled. It is enabled on either of the following conditions: Neuron Chip in Operating mode and Comm Port in Differential mode. Neuron Chip in Sleep mode and Comm Port in Differential mode and Comm Port Wakeup not masked, 4. Typical values are at midpoint of voltage range and 25C only. MOTOROLA LonWorks TECHNOLOGY MC143150MC143120 SECTION 6 6-5 MB 6367253 O103bbb6 107Vpp Trip Point for Reset Part Number Min Typ Max - Unit MC143150B1FU1 21 3.3 4.4 Vv MC143120B1DW 2.1 3.3 4.4 v MC143120E2DW , 3.8 44 4.4 Vv 6.2.4 External Memory Interface Timing MC143150B1FU1, Vpp + 10% (Vop=4-5 to 5.5 V, Ta = 40 to+ 85C) Symbol Parameter Min Max Unit toyc Memory Cycle Time (System Clock Period) (Note 1) 200 3200 ns PWey | Pulse Width, E High teyol2-5 teyc/2 +5 ns PWEL Pulse Width, E Low toyo/2 - 5 teyc/2 + 5 ns tad Delay, E High to Address Valid - 50 ns taH Address Hold Time after E High : 10 _ ns tAD Delay, E High to RAW Valid Read = 45 | ons tRH RW Hold Time Read after E High 5 ns twa Delay, E High to R/W Valid Write _ 45 ns tWH RAW Hold Time Write after E High 5 ~ ns tosA Read Data Setup Time to E High 20 ns tpHR Data Hold Time Read after E High 0 = ns toHw Data Hold Time Write after E High (Note 4,5) 20 _ ns tppw Delay, E Low to Data Valid _ 60 ns toHz Data Three State Hold Time after E Low (Note 3) i) - ns topz Delay, E High to Data Three~State (Note 4) . _ 60 ns tace External Memory Access Time (tage = teye ~ (AD - toSR) 130 ~ ns NOTES: 1. teye = 2e1/f, where fis the input clock (CLK1) frequency (10, 5, 2.5, 1.25, or 0.625 MHz). Refer to Clocking System for more details on the CLK1 input clock, including the accuracy requirements (in ppm) and duty cycle requirements. 2. Refer to Figure 6-3, Test Point Levels for E Pulse Width Measurements, for detailed measurement information. 3. The three-state condition is when the device is not actively driving data. Refer to Figure 6-2, Signal Loading for Timing Specifications Unless Otherwise Specified, and Figure 6-5, Test Point Levels for ThreeState to Driven Time Measurements, for detailed measurement information. 4. Refer to Figure 6-6, Signal Loading for Driven to Three-State Time Measurements, and Figure 6-7, Test Point Levels for Driven to Three State Time Measurements, for detailed measurement information. 5. The data hold parameter, tpyw, is measured to the disable levels shown in Figure 6-7, Test Point Levels for Driven to ThreeState Time Measurements, rather than to the traditional data invalid levels. MC1431500eMC143120 SECTION 6 MOTOROLA LonWorks TECHNOLOGY 6-6 MM #6367253 O103bb7 O43SLUM Alowey SLM Aioway, Gvay Aloway, Gvay Aoway | | of bet | rts mx I ssalppy + [ma >s Hama | + 940 | peo| 4d 0S (za - 00) {ng) ee (za - 00) (ul) Bea peo| 4d og me peo} 4d os (S1v - ov) ssalppy peo} 4d 02 a Figure 61. External Memory Interface Timing Diagram MC143150eMC143120 SECTION 6 MOTOROLA LonWorks TECHNOLOGY 6-7 MH 6367253 0103668 ToT6.2.5 External Memory Interface Timing* MC143150B1FU1, Over Specified Voltage (Vpp=3.8 to 5.5 V, Ta = 40 to+'85C) Symbol Parameter Min Max Unit teye Memory Cycle Time (System Clock Period) (Note 1) TBD TBD ns PWeH _| Pulse Width, E High (Note 2) TBD TBD ns PWeL Pulse Width, E Low (Note 2) TBD TBD ns taD Delay, E High to Address Valid = TBD ns tAH Address Hold Time After E High TBD ns tRb Delay, E High to RAV Valid Read - TBD ns tRH R/W Hold Time Read after E High TBD _ ns twR Delay, E High to RW Valid Write TBD ns tWH RAW Hold Time Write after E High TBD ns tosR Read Data Setup Time to E High TBD _ ns tDHR Data Hold Time Read after E High TBD = ns tpHw Data Hold Time Write after E High (Note 4,5) TBD - ns topw Delay, E Low to Data Valid . _ TBD | os tpHz Data Three State Hold Time after E Low (Note 3) TBD - ns tppz Delay, E High to Data Three-State (Note 4) - TBD ns tace External Memory Access Time (taco = eye tap-tpsR) | TBD _ ns NOTES: 1. toyg = 20144, where fis the input clock (CLK1) frequency 6, 2.5, 1.25, or 0.625 MHz), Refer to Clocking System for more details on the CLK1 input clock, including the accuracy requirements (in.ppm) and duty cycle requirements. 2. Refer to Figure 6-3, Test Point Levels for E Pulse Width Measurements for detaited measurement information. 3. The three-state condition is when the device is not actively driving data. Refer to Figure 6-2, Signal Loading for Timing Specifications Unless Otherwise Specified and Figure 6-5, Test Point Levels for ThreeState to Driven Time Measurements for detailed measurement information. 4. Refer to Figure 6-6, Signal Loading for Driven to ThreeState Time Measurements and Figure 6-7, Test Point Levels for Driven to Three State Time Measurements for detailed measurement information. 5. The data hold parameter, tp}w, is measured to the disable levels shown in Figure 6-7 Test Point Levels for Driven to ThreeState Time Mea- surements, rather than to the traditional data invalid levels. 6. LVI Reset occurs between 3.8 < Vpp < 4.4 V. 7, This timing is for the range of 3.8 < Vpp < 5.5 V. Table 6.2.4 reflects timing values for 4.5 < Vpp < 5.5 V. MC1431506MC143120 SECTION 6 MOTOROLA LonWorks TECHNOLOGY 6-8 MM 63567253 0103669 Ib6.2.6 External Memory Interface Timing* MC143150B1FU, Vpp + 10% (Vpp=4.5 to 5.5 V, Ta = 40 to+ 85C) Symbol Parameter Min 3 Min Max Unit toye Memory Cycle Time (System Clock Period) (Note 1) 200 3200 ns PWEH Pulse Width, E High toyo/2-5 | tayo/2+5 | ns PWet Pulse Width, E Low teyol2-5 | teyo/2+5 | ns tAD Delay, E High to Address Valid & _ 32 | ns taH Address Hold Time . ss Soe 0 40 _ ns tap Delay, E High to R/W Valid Read AP _ 25 ns tRH R/W Hold Time Read > 0 5 ns tosA Read Data Setup Time ow 34 - ns tpHR Data Hold Time Read oO 0 - ns twR Delay, E High to RAV Valid wee 25 ns topw Delay, E Low to Data vate 60 ns WH UW Hold Time Writes 0 5 ns tpHW Data Hold Time Write 9 40 ns tace External Memory Access Time (tacc = teye - tap - toSR) 134 _ ns NOTES: * All values are preliminary and subject to change. 1. teye = 2e1/f, where fis the input clock frequency (10, 5, 2.5, 1.25, or 0.625 MHz). _ 2. twop spec has been eliminated. When R/W goes low, the data bus is not driven until E clock goes low. 3. New Parameters. The $C143150B1FU is only being shipped against a Requirad Order Authorization from the customer. 6.2.7 External Memory Interface Timing MC143150FU, Vpp + 10% (Vop = 4.5 to 5.5 V, Ta = 40 to + 85C) Symbol Parameter Min Max Unit toyc Memory Cycle Time (System Clock Period) (Note 1) 200 3200 ns PWEH Pulse Width, E High AY teyol2 - 5 toyc/2 +5 ns PWEL Pulse Width, E Low we teyol2-5 toyo/2 +5 ns taD Delay, E High to Address Valid ys _ 55 | ons taH Address Hold Time oS 7 _ ns tRD Delay, E High to R/W Valid Read Oo _ 25 ns tRH R/W Hold Time Read LW - 5 ns tpSR Read Data Setup Time wo 55 ns toHR Data Hold Time Read Ze 0 ns twR Delay, E High to RAW Valid Write 25 ns twobD Delay, R/W Low to Data Drivers On (Note 2) 10 - ns tppw Delay, E Low to Data Valid 60 ns twH RW Hold Time Write 5 ns NOTES: 1. toeye = 201/f, where f is the input clock frequency. _ 2. See Figure 6-1. The Neuron Chip drives the previously read data until after the falling edge of E. Therefore, an external memory and the Neuron Chip may both be driving the data lines to the same levels during this time without contention. MOTOROLA LonWorks TECHNOLOGY MC143150eMC143120 SECTION 6 6-9 MH 63567253 0103670 4346.2.8 External Memory Interface Timing MC143150FU, Vpp + 5% (Vpp = 4.75 to 5.25 V, Ta = 40 to + 85C) Symbol Parameter Min Max Unit toyc Memory Cycle Time (System Clock Period) (Note 1) 200 3200 ns PWey Pulse Width, E High teyo/2- 5 teyo2 +5 ns PWEL Pulse Width, E Low . toyo/2 - 5 teyo/2 +5 ns taD Delay, E High to Address Valid . 2 45 ns tau Address Hold Time . an 8 - ns tap Delay, E High to RAW Valid Read . ye _ 25 ns tRH RW Hold Time Read & : 5 _ ns tpsR Read Data Setup Time Vv _ 50 - ns tDHR Data Hold Time Read nw 0 _ ns twr Delay, E High to R/W Valid Write Pr _ 25 ns twop Delay, R/AW Low to Data Driverg@it (Note 2) 10 ns tppw Delay, E Low to Data Valid 60 ns twH RAW Hold Time Write 5 _ ns NOTES: : 1. teye = 201/f, where f Is the input clock frequency, 2. See Figure 6-1. The Neuron Chip drives the previously read data until after the falling edge of E. Therefore, an external memory and the Neuron Chip may both be driving the data lines to the same levels during this time without contention. 6.2.9 External Memory Interface Timing MC1431 50FU1, Vpp + 10% (Vpp = 4.5 to 5.5 V, Ta = 40 to + 85C) Symbol Parameter Min Max Unit teyc Memory Cycle Time (System Clock Period) (Note 1) 400 3200 ns PWEH Pulse Width, E High teye/2-5 toyo/2 + ns PWeL Pulse Width, E Low or teyo/25 teyo/2 +5 ns tAD Delay, E High to Address Valid wy 80 ns TAH Address Hold Time ~~ 7 ~ ns iAD Delay, E High to RAW Valid Read * ~ 50 ns 1RH R/W Hold Time Read wY 5 ns iDsSR Read Data Setup Time 2 we 80 - ns toHR Data Hold Time Read - 0 ns wR Delay, E High to RAW Valid ee 50 ns twop Delay, R/W Low to Data Drivers On (Note 2) 10 - ns tppw Delay, E Low to Data Valid _ 100 ns WH R/W Hold Time Write 5 ns NOTES: 1. ieye = 201/f, where f is the input clock frequency. _ 2. See Figure 6-1. The Neuron Chip drives the previously read data until after the falling edge of E. Therefore, an extemal memory and the Neuron Chip may both be driving the data lines to the same levels during this time without contention. MC143150eMC143120 SECTION 6 MOTOROLA LonWorks TECHNOLOGY 6-10 MB 6367253 0103671 574TEST SIGNAL a TL cL =20pF tore = C_ = 50 pF for all other signals Figure 6-2. Signal Loading for Timing Specifications Unless Otherwise Specified Figure 6-3. Test Point Levels for E Pulse Width Measurements DRIVE TO 2.4V > OV DRIVE TO.0.4V 08 A B A Signal valid to signal valid specification (maximum or minimum) B Signal valid to signal invalid specification (maximum or minimum) Figure 64. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified Pin under test in High-2 and pulled to Vpp. Vpp - 0.5V Pin under test driving to alow state. Pin under test driving to Pin under test in High-2 Veg +0.5V ahigh state. and pulled to Vgs. Figure 6-5. Test Point Levels for ThreeState To Driven Time Measurements TEST SIGNAL 1O- Vppi2 =1.4mA CL = 50 pF r LOAD Figure 6-6. Signal Loading for Driven to Three-State Time Measurements Vou - 0.5V VoL +0.5V VOH - Measured high output drive level VoL - Measured low output drive level Figure 6-7. Test Point Levels for Driven To Three-State Time Measurements MOTOROLA LonWorks TECHNOLOGY MC143150eMC143120 SECTION 6 6-11 MB 6367253 0103672 4O06.2.10 Communications Port Programmable Hysteresis Values (Expressed as differential peak to peak voltages in terms of Vpp) Hysteresis* Viys Min Vays Typ Vhys Max 0 0.019 Vpp 0.027 Vop 0.035 Vpp 1 0.040 Vpp 0.054 Vop 0.068 Vop 2 0.061 Vpp 0.081 Vpp 0.101 Vop 3 0.081 Vop 0.108 Vop 0.135 Vop 4 0.101 Vpp 0.135 Vop 0.169 Vop 5 0.121 Vpp 0.162 Vop 0.203 Vpp 6 0.142 Vop 0.189 Vop 0.236 Vop 7 0.162 Vpp 0.216 Vop 0.270 Vop Hysteresis values are under the conditions that the input signal swing is 200 mV greater than the programmed value. 6.2.11 Communications Port Programmable Glitch Filter Values* {Receiver (end-to-end) filter values expressed as transient pulse suppression times] Filter (F) Min Typ Max Unit 0 10 75 140 ns 1 120 410 700 ns 2 240 800 1350 ns 3 480 1500 2600 ns *Must be disabled if data rate is 1.25 Mbps. 6 6.2.12 Receiver* (End-to-End) Absolute Asymmetry (Worst case across hysteresis) Filter (F) Max (| tpLytpHL!) 0 35 ns 1 150 ns 2 250 | ns 3 400 ns *Receiver input, Vp = Vopo Vcpzi. at least 200 mV greater than hysteresis levels. See Figure 6-4, IcPo-cPi| = Vhys + 200 mV CPO Vppy cPi | h < 3ns Figure 6-8. Receiver Input Waveform MC143150eMC143120 SECTION 6 MOTOROLA LonWorks TECHNOLOGY 6~12 MB 6367253 0105673 3476.2.13 Differential Receiver (EndtoEnd) Absolute Symmetry Filter (F) Hysteresis (H) Max (| tpn - tpHL!) Unit 0 0 24 ns NOTES: 1. CPO and CP1 inputs each 0.60 V pp, 1.25 MHz sine wave 180 out of phase with each other as shown in Figure 6-9. Vpp = 5.00 V+ 5% 2. tPLH: Time from input switching states from low to high to output switching states tPHL: Time from input switching states from high to low to output switching states CPO, CP1 {Inputs Yop ba 400 ns ~->+a 400ns el Time Figure 6-9. Communications Port Signal Input for Table 6.2.13 6.2.14 Differential Transceiver Electrical Characteristics Characteristic Min Max Receiver Common Mode Voltage Range to maintain hysteresis as 1.2V Vop -2.2V specified in Table 44* Receiver Common Mode Range to operate with unspecified hysteresis 0.9V Vpp - 1.75 V Input Offset Voltage 0.05 Vays ~ 35 mv 0.05 Vhys +35 mV Propagation Delay (F = 0, Vip = Viys/2 + 200 mV) _ 230 ns Input Resistance 5 MQ _ Wake-Up Time _ 10 us * Common mode voltage is defined as the average value of the waveform at each input at the time switching occurs. MOTOROLA LonWorks TECHNOLOGY MC143150MC143120 SECTION 6 6-13 Me 367253 01303674 243 a a6.3 MECHANICAL SPECIFICATIONS . 6.3.1 Pin Descriptions MC143120 / MC143150. Pin Name vo Pin Function Pin Number Pin Number CLK1 Input Oscillator connection or extemal clock input. 24 15 CLK2 Output Oscillator connection. Leave open when external _ 23 14 clock is input to CLK1, One Load. RESET vO Reset pin (active low). 6 1 (Built-In Pullup) SERVICE vo Service pin. Indicator output during operation. 17 8 {Built-In : Configurable Pullup) ; 100 - 103 Vo Large currentsink capacity (20 mA). General I/O . 12,3,4,5 7,6, 5,4 port. a : . 104 -107 vo General I/O port. One of 104 to 107 can be specified 10, 11, 12, 13 3, 30, 29, 28 (Built-in as No. 1 timer/counter input with 100 as output.104. |. 7 : Configurable can be used as the No. 2 timer/counter input with 101 Pullup) as output. 108-1010 vO General I/O port. Can be used for serial 14,15, 16 27, 26, 24 : communication with other devices. bo- D7 vo Memory data bus. 43, 42,38, 37, N/A 36, 35, 34, 33 . RW Output Read/write control output port for external memory. 45 N/A E Output Control output port for-external memory. 46 N/A A15A0 Output Address output port. 47, 50, 51, 52, 53, N/A 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 . Vop Input Power input. (5 V nom). All Vop pins must be 7, 20, 22, 26, 2, 11, 12, 18, 25, 32 . connected together externally. 40, 41, 44 : Vss Input Power input (0 V, GND). All Vgg pins must be 8, 9,19, 21, 25, 39 9, 10, 13, 16, 23, 31 connected together externally. CPO ~CP4 Communication | Bidirectional port that supports communications 28, 29, 30, 31, 32 19, 20, 17, 21, 22 Network Interface | protocols by specifying mode. Nc N/A No internal connection. Leave open. 1, 18, 27, 48, 49 N/A CAUTION: Pin 18 of the MC143150 MUST NOT have any external connection. MCi43150eMC143120 SECTION 6 MB 63672539 0103675 117 6-14 MOTOROLA LonWorks TECHNOLOGY6.3.2 MC143150 Pin Assignments MC143150 64-LEAD QUAD FLAT-PACK a oa gfweSestS8agages UL UE ( 48 4746 45 44 43 42 41 40 39 38 37 36 35 34 33. \ nc [___] 49 6 } cpa Ai4 (| 50 31 [____] cp3 Ai3 ((__] 51 30 [___] cp2 Ai2 [ 52 29 [crt Au ((__] 538 23 [___] cro aio (__] 54 27 [-__] no 49 (1) 55 26 {__] Ypp ss | 56 (SY 25 [1] Ves ATL__] 57 24 [~~] cLKi AG [| 58 23 } cuKe As] 59 MC143150 22 [_] Yop as __] 0 21 ] Vsg aC 6 20 [___} Ypp A2[___ | e 19 [1] Vgg Al Co] 83 18 } NC a 17 [| SERVICE 123 4 5 6 7 8 9 1011 12 1314 15 16 Pint Indicator 2 8 3 *Pin 18 must NOT be connected. The larger dimple at the bottom left of the marking indicates pin 1. MOTOROLA LonWorks TECHNOLOGY MC143150MC143120 SECTION 6 6-15 MB 6367253 0103b7b O56 OEE EOS OSS Sc s:;~~=s se6.3.3 MC143150 Package Dimensions MC143150FU1/B1FU/B1FU1 PLASTIC 64-LEAD QUAD FLAT-PACK CASE 8406-04 5 8B r 1 7 TUeT NX TI 3 lk a a = @ @ | iL a co < < _ P B= DETAILA ale] Ve wW S 5 8 s [< F> / ETAL 5|8 g 1 99470). sis co J y Gy y N efi} Lda + < Dr ime OaIHD A SECTION B-B -| NOTES: e 0.20 (0.008) @| a] AS | D 9] 1. QIMENSIONING AND TOLERANCING PER ANSI 1] 0.05 (0.002)/ 4-8] YIASM, 1982. 2. CONTROLUNG DIMENSION: MILUMETER. s | * a Suen gta - WHERE THE LEAD EXITS THE PLASTIC BODY AT 6 0.20 (0.008) @ THE BOTTOM OF THE PARTING LINE. 4. DATUMS A-& AND -D- TO BE DETERMINED AT DATUM PLANE -H-, 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. . : 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 _ 1 ERE) DATUM PLANE (0.019) PER SIDE. DIMENSIONS A AND B DO INGLUDE MOLD MISMATCH AND ARE DIMENSION D DOES NOT INGLUDE GAMBAR 7. DIMENSION D DOE! O} 0.40 (0.004) PROTRUSION. DAMBAR PROTRUSION SHALL C] SEATING PLANE NOT CAUSE THE D DIMENSION TO EXCEED 0.53 DETAIL C (OWA RADIUS OR THE FOOT GIMENSION K IS TO BE MEASURED FROM THE THEORETICAL INTERSECTION OF LEAD FOOT AND LEG CENTERLNES. DETAIL C MC143150eMC143120 SECTION 6 MOTOROLA LonWorks TECHNOLOGY 6-16 M@@ 6367253 0103677 Tie6.3.4 MC143150 Pad Layout MC143150 64-LEAD QUAD FLAT PACK 0.5mm 0.8 mm WIDTH PITCH eo wm 14.0mm 40.1 mm XK 17.7 mm 40.1 mm MOTOROLA LonWorks TECHNOLOGY MC143150eMC143120 SECTION 6 6-17 MP 6367253 0103678 9129 aaa6.3.5 MC143120 Pin Assignment MC143120 32-LEAD SOG RESET (_]1 32] Vpp Vpp CL] 2 31 [J vss loa C7} 3 30 {__] los 103 (-] 4 29 [_] 106 lo2 ([] 5 28 [_] 107 101 ( J6 27 {_] 108 oo 7 = o26f_] 109 o SERVICE [_] 8 = 25[_] Vpp VegCj9 S$ 24f) 1010 Veg L_] 10 23 (77) Veg Vop CJ 11 22 [_] cps Vpp (J 12 21 []) cps Vsg C_] 13 20 (_] cpt cux2 [7] 14 19 [7] cpo cuxi [7] 15 18] Vop Vgg [J 16 17 {_] cre 6.3.6 MC143120 Package Dimensions MC143120 PLASTIC 32-LEAD SOG CASE 855-01 DETAIL X *P SSsararss D 32 PL [4+]o.20 (0.00) @ [7] BOTA] NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI {=A} Y14.5M, 1982. - 2 CONTROLLING DIMENSION: MILLIMETERS. 32 17| M J 3. oan AND B DO NOT INCLUDE MOLD AAA AAA AAA RA AR AAA Vd an LD PROTON 15 a5 ER =F a - DETAIL Z oe + _ouunUUUEUEUUUHE Ls 025 (0.01)@ | B | DETAIL X DETAIL Z = tom ( SELETUUUESTY os =] 0.10 (0.004) yh r MC143150eMC143120 SECTION 6 MOTOROLA LonWorks TECHNOLOGY 6-18 Mi 6367253 0103679 6656.3.7 MC143120 Pad Layout MC143120 32-LEAD SOG 11.3 mm +01mm , , ammo: = =. 0.6 mm _ wn} WiOTH 1) = = = 214 = fein) = = aan = = 7 = = = i =! 7 =_ 7 _ = emm = = 74.27 mm i) a, - , PITCH , a 175mm 6.3.8 Sockets for Neuron Chips NOTE: Motorola cannot recommend one supplier over another and in no way suggests that these are the only suppliers. Integrated Circuit Manufacturer Part Number MC143120 Yamaichi 1C51-0322-667-2 MC143150 Enplas FPQ-64-0.8-10A MC143150 Enpias FPQ-64-0.8-02" * This is a tighterfitting socket than the one above, and is used on Motorolas M143120EVK Test Board. MOTOROLA LonWorks TECHNOLOGY MC143150eMC143120 SECTION 6 6-19 MB 6367253 0103680 5a? a