MT18HTS25672CHY-40EXX - Micron Technology, Inc.

1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Features

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DDR2 SDRAM SOCDIMM

MT18HTS12872CH – 1GB

MT18HTS25672CH – 2GB

For component data sheets, refer to Micron’s Web site: www.micron.com/products/ddr2sdram

Features

• 200-pin, small outline, dual in-line memory module

(SODIMM)

• Fast data transfer rates: PC2-3200, PC2-4200, and

PC2-5300

• 1GB (128 Meg x 72), 2GB (256 Meg x 72)

• Supports ECC error detection and correction

•V

DD = VDDQ = +1.8V

•V

DDSPD = +3.0V to +3.6V

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

• Four-bit prefetch ar chitectur e

• DLL to align DQ and DQS transitions with CK

• Multiple internal device banks for concurrent

operation

• Programmable CAS# latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength

• 64ms, 8,192-cycle refresh

• On-die termination (ODT)

• Serial presence-detect (SPD) with EEPROM

• Phase-lock loop (PLL) to re duce sys tem clock line

• Gold edge cont acts

•Dual rank

•I

2C temperature sensor

Figure 1: 200-Pin SOCDIMM (MO-224 R/C “B”)

Notes: 1. CL = CAS (READ) latency.

Options Marking

•Package

–200-pin SODIMM (Pb-free) Y

•Frequency/CL

–3.0ns @ CL = 5 (DDR2-667) -667

–3.75ns @ CL = 4 (DDR2-533) -53E

–5.0ns @ CL = 3 (DDR2-400) -40E

•PCB height

– 30.0mm (1.18in)

Height 30.0mm (1.18in)

Table 1: Address Table

1GB 2GB

Refresh count 8K 8K

Row address ing 16K (A0–A13) 16K (A0–A13)

Device bank addressing 4 (BA0, BA1) 8 (BA0, BA1, BA2)

Device page size per ba nk 1KB 1KB

Device configuration 1Gb TwinDie (128 Meg x 8) 2Gb TwinDie (256 Meg x 8)

Column addressing 1K (A0–A9) 1K (A0–A9)

Module rank addressing 2 (S0#, S1#) 2 (S0#, S1#)

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Features

Notes: 1. All part numbers end with a two-place code (not shown), designating component and PCB

revisions. Consult factory for current revision code s. Example: MT18HTS25672CHY-40EC2.

2. For the latest component data sheets, see Micron’s Web site: www.micron.com/products/

ddr2sdram

Table 2: Key Timing Parameters

Speed

Grade Industry Nomenclature

Data Rate (MT/s) tRCD

(ns) tRP

(ns) tRC

(ns)CL = 5 CL = 4 CL = 3

-667 PC2-5300 667 533 400 15 15 55

-53E PC2-4200 – 533 400 15 15 55

-40E PC2-3200 – 400 400 15 15 55

Table 3: Part Numbers and Timing Parameters – 1GB Modules

Base device: MT47H128M8T HK, 1Gb TwinDie™ DDR2 SDRAM

Part Number1Module

Density Configuration Module

Bandwidth Memory Clock/

Data Rate Latency

(CL - tRCD - tRP)

MT18HTS12872CHY-667__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5

MT18HTS12872CHY-53E__ 1GB 128 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT18HTS12872CHY-40E__ 1GB 128 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3

Table 4: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT47H256M8THJ, 2Gb TwinDie DDR2 SDRAM

Part Number1Module

Density Configuration Module

Bandwidth Memory C lock/

Data Rate Latency

(CL - tRCD - tRP)

MT18HTS25672CHY-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/66 7 MT /s 5-5-5

MT18HTS25672CHY-53E__ 2GB 256 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT18HTS25672CHY-40E__ 2GB 256 Meg x 72 3.2 GB/s 5.0ns/40 0 MT /s 3-3-3

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Pin Assignments and Descriptions

Notes: 1. Pin 92 is NC for 1GB, BA2 for 2GB.

Table 5: Pin Assignments

200-Pin SODIMM Front 200-Pin SODIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

REF 51 DQ18 101 VDD 151 VSS 2VSS 52 VSS 102 A6 152 VSS

3 DQ0 53 DQ19 103 A5 153 DQS5# 4 DQ4 54 DQ28 104 A4 154 DM5

5 Vss 55 Vss 105 A3 155 DQS5 6 DQ5 56 DQ29 106 VDD 156 VSS

7 DQ1 57 DQ24 107 A2 157 VSS 8VSS 58 VSS 108 A1 158 DQ46

9 DQS0# 59 DQ25 109 VDD 159 DQ42 10 DM0 60 DM3 110 A0 160 DQ47

11 DQS0 61 Vss 111 A10 161 DQ43 12 VSS 62 VSS 112 BA1 162 VSS

13 Vss 63 DQS3# 113 BA0 163 VSS 14 DQ6 64 DQ30 114 VDD 164 DQ52

15 DQ2 65 DQS3 115 RAS# 165 DQ48 16 DQ7 66 DQ31 116 WE# 166 DQ53

17 DQ3 67 Vss 117 VDD 167 DQ49 18 VSS 68 VSS 118 S0# 168 VSS

19 Vss 69 DQ26 119 CAS# 169 VSS 20 DQ12 70 CB4 120 ODT0 170 DM6

21 DQ8 71 DQ27 121 S1# 171 DQS6# 22 DQ13 72 CB5 122 A13 172 VSS

23 DQ9 73 Vss 123 VDD 173 DQS6 24 VSS 74 VSS 124 VDD 174 DQ54

25 Vss 75 CB0 125 ODT1 175 VSS 26 DM1 76 DM8 126 CK0 176 DQ55

27 DQS1# 77 CB1 127 NC 177 DQ50 28 VSS 78 VSS 128 CK0# 178 VSS

29 DQS1 79 Vss 129 DQ32 179 DQ51 30 DQ14 80 CB6 130 VSS 180 DQ60

31 Vss 81 DQS8# 131 VSS 181 VSS 32 DQ15 82 CB7 132 DQ36 182 DQ61

33 DQ10 83 DQS8 133 DQ33 183 DQ56 34 VSS 84 VSS 134 DQ37 184 VSS

35 DQ11 85 Vss 135 DQS4# 185 DQ57 36 DQ20 86 CB2 136 VSS 186 DM7

37 Vss 87 CKE0 137 DQS4 187 VSS 38 DQ21 88 CB3 138 DM4 188 DQ62

39 DQ16 89 CKE1 139 VSS 189 DQS7# 40 VSS 90 VSS 140 VSS 190 VSS

41 DQ17 91 EVENT# 141 DQ34 191 DQS7 42 RESET# 92 NC/BA2 142 DQ38 192 DQ63

43 Vss 93 VDD 143 DQ35 193 DQ58 44 DM2 94 NC/A14 144 DQ39 194 SDA

45 DQS2# 95 A12 145 VSS 195 VSS 46 Vss 96 A11 146 VSS 196 SCL

47 DQS2 97 A9 147 DQ40 197 DQ59 48 DQ22 98 VDD 148 DQ44 198 SA1

49 Vss 99 A7 149 DQ41 199 VDDSPD 50 DQ23 100 A8 150 DQ45 200 SA0

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Pin Assignments and Descriptions

Table 6: Pin Descriptions

Refer to Table 5 for pin assignments

Symbol Type Description

ODT0, ODT1 Input On-die termination: ODT (registered HIGH) enables termination resistance

internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the

following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled

via the LOAD MODE command.

CK0, CK0# Input Clock: CK and CK# are differenti al clock inputs. All address and control input si gnals

are sampled on the crossing of the positive edge of CK and negative edge of CK#.

Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.

CKE0, CKE1 Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW)

deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is

enabled/disabled is dependent on the DDR2 SDRAM configuration and operating

mode. CKE LOW provides PRECHARGE power-down and SELF REFRESH operations

(all device banks idle), or ACTIVE power-down (row ACTIVE in any device bank). CKE

is synchronous for power-down entry, power-down exit, output disable, and for

SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers

(excluding CK, CK#, CKE, and ODT) are disabled during powe r-down . Inpu t buffers

(excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 inpu t but will

detect a LVCMOS LOW level once VDD is applied during f irst power-up. After VREF

has become stable during the power on and initialization sequence, it must be

maintained for proper operation of the CKE receiver. For proper SELF-REFRESH

operation VREF must be maintained to this input.

S0#, S1# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when S# is registered HIGH. S#

provides for external rank selection on systems with multiple ranks. S# is considered

part of the command code.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command

being entered.

BA0, BA1

(1GB)

BA0, BA1, BA2

(2GB)

Input Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ,

WRITE, or PRECHARGE command is being applied BA0–BA1/BA2 define which mode

command.

A0–A13 Input Address inputs: Provide the row address for ACTIVE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank . A1 0 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one device

bank (A10 LOW, device bank selected by BA0–BA1/BA2) or all device banks (A10

HIGH). The address inputs also provide the op-code during a LOAD MODE

command.

DM0–DM8 Input Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with that input data during a WRITE access. DM is

sampled on both edges of DQS. Although DM pins are input-only, the DM loading is

designed to match that of DQ and DQS pins.

DQ0–DQ63 I/O Data input/output: Bidirectional data bus.

CB0–CB7 I/O Check bits

DQS0–DQS8,

DQS0#–DQS8# I/O Data strobe: Output with read data, input with write data for source synchronous

operation. Edge-aligned with read data, center aligned with write data. DQS# is

only used when differential data strobe mode is enabled via the LOAD MODE

command.

EVENT# Output Temp sensor alarm output

SCL Input Serial clock for presence-detect: SCL is used to synchron ize the presence-detec t

data transfer to and from the module.

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Pin Assignments and Descriptions

SA0–SA1 Input Presence-detect address inputs: These pins are used to configure the presence-

detect device.

SDA Input/

Output Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses

and data into an d out of the presence-detect portion of the module.

VDD Supply Power supply: +1.8V ±0.1V.

VREF Supply SSTL_ 18 reference voltage

VSS Supply Ground

VDDSPD Supply Serial EEPROM positive power supply: +3.0V to +3.6V.

Table 6: Pin Descriptions (Continued)

Refer to Table 5 for pin assignments

Symbol Type Description

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Functional Block Diagram

Figure 2: Functional Block Diagram

Notes: 1. Unless otherwise noted, resist or values are 22Ω.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1b

DM CS# DQ DQS#

U1t

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

U7b

DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U13b

DM CS# DQ DQS#

U13t

DM CS# DQ DQS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U2b

DM CS# DQ DQS#

U2t

DM CS# DQ DQS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U12b

DM CS# DQ DQS#

U12t

DM CS# DQ DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U10b

U10t

DM CS# DQ DQS# DM CS# DQ DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

U8b

U8t

DM CS# DQ DQS# DM CS# DQ DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

U9b

U9t

DM CS# DQ DQS# DM CS# DQ DQS#

DQS0#

DQS0

DM0

S0#

S1#

DQS1#

DQS1

DM1

DQS2#

DQS2

DM2

DQS3#

DQS3

DM3

DQS4#

DQS4

DM4

DQS5#

DQS5

DM5

DQS6#

DQS6

DM6

DQS7#

DQS7

DM7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

U11b

DM CS# DQ DQS#

U11t

DM CS# DQ DQS#

DQS8#

DQS8

DM8

BA0-BA1/BA2

A0-A12/A13

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

BA0-BA1/BA2: DDR2 SDRAMs

A0-A12/A13: DDR2 SDRAMs

RAS#: DDR2 SDRAMs

CAS#: DDR2 SDRAMs

WE#: DDR2 SDRAMs

CKE0: DDR2 SDRAMs Rank 0

CKE1: DDR2 SDRAMs Rank 1

ODT0: DDR2 SDRAMs Rank 0

ODT1: DDR2 SDRAMs Rank 1

VREF

VSS

DDR2 SDRAMS

VDD

DDR2 SDRAMS

VDDSPD Serial PD, Temp Sensor

VDDQ

DDR2 SDRAMS

3Ω

PLL

CK0

CK0#

TBD

CLK0/CLK0#

CLK1/CLK1#

CLK2/CLK2#

CLK3/CLK3#

CLK4/CLK4#

120ΩU1, U13

U2, U12

U11

U7, U10

U8, U9

Rank 0 = U1b, U2b, U7b - U13b

Rank 1 = U1t, U2t, U7t - U13t

Serial PD

A1 A2

SA0

Event#

SA1

SDA

SCL

Temp Sensor

A1 A2

SA0 SA1

EVT

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

General Description

The MT18HTS12872CH and MT18HTS25672CH DDR2 SDRAM modules are high-speed,

CMOS, dynamic random-access 1GB and 2GB memory modules, organized in a x72

configuration. These DDR2 SDRAM modules use TwinDie™ DDR2 SDRAM devices

internally configured as quad-bank (1Gb) or 8-bank (2Gb).

DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-

tion. The double data rate archi t ecture is essentially a 4n-prefetch architecture with an

interface designed to transfer two data words per clock cy cle at the I/O pins. A single

read or write access for the DDR2 SDRAM module effectively cons is ts of a single 4 n-bit-

wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding

n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM

device during READs and by the memory controller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with data for WRITEs.

DDR2 SDRAM modul es operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands (addre ss and control signals) are registered at every positive edge of CK.

Input data is regist ered on both edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

Phase-Lock Loop Operation

A PLL chip on the module r eceives and r edrives the differential cl ock signals (CK, CK#) to

the DDR2 SDRAM devices. The PLL minim izes system clock line loading. PLL clock

timing is defined by JEDEC specifications and is ensured by the use of a JEDEC clock

re ference board.

Serial Presence-Detect Op eration

DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD func tion is

implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256

b ytes. The first 128 bytes ar e programmed by Micr on to identify the module type and

various SDRAM organizat ions and timing parame ters. The remai ning 128 bytes of

storage are available for use by the customer. System READ/WRITE operations between

the master (system logic) and the slave EEPROM device occur via a standar d I 2C bus

extended mode register 2 (EMR2).

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Electrical Specifications

S tresses greater than those listed in Table 7 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this spe c ifi cat ion is not

implied. Exposure to absolute maximum rating conditions for extended periods may

affect reli ability.

Capacitance

At DDR2 data rates, Micron encourages desig ners to simulate the performance of the

module to achieve optimum values. When inductance and delay parameters associated

with trace lengths are used in simulations, they are significantly more accurate and real-

istic than a gross estimation of module capacitance. Simulations can then render a

considerably more accurate result. JEDEC modules are now designed by using simula-

tions to close timing budgets.

Table 7: Absolute Maximum DC Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –1.0 +2.3 V

VDDQVDDQ suppl y voltage relative to VSS –0.5 +2.3 V

VDDLVDDL supply voltage relative to Vss –0.5 +2.3 V

VIN, VOUT Voltage on any pin relative to VSS –0.5 +2.3 V

TSTG Storage temperature –55 +100 °C

Tcase DDR2 SDRAM device operating temperature 085°C

TOPR Operating temperature (ambient) 065°C

IIInput leakage current; Any input 0V ≤ VIN ≤ VDD;

VREF input 0V ≤ VIN ≤0.95V; (All other pins not under

test = 0V)

Command/Address,

RAS#, CAS#, WE# –90 +90 µA

S#, CKE –45 +45

CK0, CK0# –10 +10

DM –10 +10

IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs and

ODT are disabled DQ, DQS, D QS# –10 +10 µA

IVREF VREF leakage curr ent; VREF = Valid VREF level –36 +36 µA

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Electrical Specifications

Table 8: DDR2 IDD Specifications and Conditions – 1GB

Values shown for DDR2 TwinDie SDRAM compo nents only

Parameter/Condition Symbol -667 -53E -40E Units

Operating one bank active-precharge current; tCK = tCK (IDD), tRC = tRC

(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are switching

IDD0 918 828 828 mA

Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address

bus inputs are SWITCHING; Data pattern is same as IDD4W

IDD1 1,053 963 918 mA

Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE

is LOW; Other control and address bus inputs are stable; Data bus inputs are

floating

IDD2P 126 126 126 mA

Precha rge quiet standby curren t; All device banks idle; tCK = tCK (IDD); CKE

is HIGH, S# is HIGH; Other con t ro l an d address bus inputs are stable; Data bus

inputs are floating

IDD2Q 513 468 423 mA

Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and ad dress bus inputs are switching; Data

bus inputs are switching

IDD2N 558 513 468 mA

Active power-down current; All device banks open; tCK =

tCK (IDD); CKE is LOW; Other control and address bus inputs

are stable; Data bus inputs are floating

Fast PDN Exit

MR[12] = 0 IDD3P 378 333 288 mA

Slow PDN Exit

MR[12] = 1 171 171 171 mA

Active standby current; All device banks open; tCK = tCK(IDD), tRAS = tRAS

MAX (IDD), tRP = tRP(IDD); CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are

switching

IDD3N 693 603 513 mA

Operating burst write current; All device banks open, continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP

= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

IDD4W 1,638 1,368 1,143 mA

Operating burst read current; All device banks open, continuous burst

reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS

MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are switching

IDD4R 1,728 1,413 1,143 mA

Burst refr esh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD)

interval; CKE is HIGH, S# is HIGH between valid commands; Other control and

address bus inputs are switching; Data bus inputs ar e switching

IDD5 1,728 1,638 1,593 mA

Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and

address bus inputs are floating; Dat a bus inputs are floating IDD6 126 126 126 mA

Operating bank interleave read current; All device banks interleaving

reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK =

tCK (IDD), tRC = tRC (IDD), tRRD = tRR D (I DD), tRCD = tRCD (IDD); CKE is HIGH, S#

is HIGH between valid commands; Address bus inputs are stable during

deselects; Data bus inputs are switching; See IDD7 conditions for detail

IDD7 2,268 2,133 2,088 mA

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Electrical Specifications

Table 9: DDR2 IDD Specifications and Conditions – 2GB

Values shown for DDR2 TwinDie SDRAM components only

Parameter/Condition Symbol -667 -53E -40E Units

Operating one bank active-precharge current; tCK = tCK (IDD), tRC = tRC

(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are switching

IDD0 918 828 738 mA

Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address

bus inputs are switching; Data pattern is same as IDD4W

IDD1 1,008 963 828 mA

Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE

is LOW; Other control and address bus inputs are stable; Data bus inputs are

floating

IDD2P 126 126 126 mA

Precha rge quiet standby curr ent; All device banks idle; tCK = tCK (IDD); CKE

is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus

inputs are floating

IDD2Q 603 477 423 mA

Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and ad dress bus inputs are switching; Data

bus inputs are switching

IDD2N 648 513 468 mA

Active power-down current; All device banks open; tCK =

tCK (IDD); CKE is LOW; Other control and address bus inputs

are stable; Data bus inputs are floating

Fast PDN Exit

MR[12] = 0 IDD3P 468 378 333 mA

Slow PDN Exit

MR[12] = 1 153 153 153 mA

Active standby current; All device banks open; tCK = tCK(IDD), tRAS = tRAS

MAX (IDD), tRP = tRP(IDD); CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are

switching

IDD3N 738 603 513 mA

Operating burst write current; All device banks open, continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (I DD), tRP

= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

IDD4W 1,548 1,278 1,098 mA

Operating burst read current; All device banks open, continuous burst

READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS

MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are switching

IDD4R 1,548 1,413 1,098 mA

Burst refr esh curr ent; tCK = tCK (IDD); REFRESH command at every tRFC (IDD)

interval; CKE is HIGH, S# is HIGH between valid commands; Other control and

address bus inputs are switching; Data bus inputs are switching

IDD5 2,448 2,358 2,088 mA

Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and

address bus inputs are floating; Dat a bus inputs are floating IDD6 126 126 126 mA

Operating bank interleave read current; All device banks interleaving

READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK =

tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S#

is HIGH between valid commands; Address bus inputs are stable during

deselects; Data bus inputs are switching; See IDD7 conditions for detail

IDD7 2,808 2,718 2,448 mA

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

AC Timing and Operating Conditions

Re commended AC operating conditions are given in the DDR2 component data sheets.

Component specifications are available on Micron’s Web site. Module speed grades

correlate with component speed grades as shown in Table 10.

Table 10: Module and Component Speed Grade Table

Module Speed Grade Component Speed Grade

-667 -3

-53E -37E

-40E -5E

Table 11: SPD Temp Sensor Select Code

The most significant bit (b7) is sent first

Select Code

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory area select code (two arrays) 1 0 1 0 SA2 SA1 SA0 RW

Protecti on register se le ct code 0 1 1 0 SA2 SA1 SA0 RW

Table 12: SPD Operating Modes

Mode RW Bit WC Bytes Initial Sequence

Current address read 1V

IH or VIL 1Start, device select, RW = 1

Random address read 0V

IH or VIL 1Start, device select, RW = 0, address

IH or VIL 1Restart, device select, RW = 1

Sequential read 1V

IH or VIL ≥1Similar to current or random address read

Byte write 0V

IL 1Start, device select, RW = 0

Page write 0V

IL ≤16 Start, device select, RW = 0

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

AC Timing and Operating Conditions

Notes: 1. T o avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and

the falling or rising edge of SDA.

2. This parameter is sampled.

3. For a restart condition, or following a WRITE cycl e.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write

sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle,

the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and

the EEPROM does not respond to its slave address.

Table 13: Serial Presence-Detect EEPROM and Temperature Sensor DC Operating Conditions

All voltages referen ced to VSS; VDDSPD = +3.0V to +3.6V

Parameter/Condition Symbol Min Max Units

Supply voltage with temperature sensor option VDDSPD 3.0 3.6 V

Input high voltage: Logic 1; All inputs VIH 2.1 VDDSPD + 0.5 V

Input low voltage: Logic 0; All inputs VIL –0.6 0.8 V

Output low voltage: IOUT = 3mA VOL –0.4V

SPD input leakage current: VIN = GND to VDD ILI 0.10 3 µA

SPD output leakage current: VOUT = GND to VDD ILO 0.05 3 µA

SPD standby current ISB 1.6 4 µA

Power supply current, READ: SCL clock frequenc y = 100 KHz ICCR0.4 1 mA

Power supply current, WRITE: SCL clock frequency = 100 KHz ICCW23mA

Average temperature sensor current 500 µA

Table 14: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referen ced to VSS; VDDSPD = +3.0V to +3.6V

Parameter/Condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 µs

Data-out hold time tDH 200 ns

SDA and SCL fall time tF 300 ns 2

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 0.6 µs

Clock HIGH period tHIGH 0.6 µs

Noise suppression time constant at SCL, SDA inputs tI50ns

Clock LOW period tLOW 1.3 µs

SDA and SCL rise time tR0.3µs2

SCL clock frequency fSCL 400 KHz

Data-in setup time tSU:DAT 100 ns

Start condition setup time tSU:STA 0.6 µs 3

Stop condition setup time tSU:STO 0.6 µs

WRITE cycle time tWRC 10 ms 4

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

PLL Specifications

Table 15: PLL Device Specifications

Uses a 97ULP845AHL or equivalent JEDEC device

Parameter Symbol Pins Condition Min Max Units

DC high-level input voltage VIH RESET# LVCMOS 0.65 × VDD –mV

DC low-level input voltage VIL RESET# LVCMOS – 0.35 × VDD mV

Input voltage (limits) VIN RESET#, CK, CK# –0.3 VDDQ + 0.3 mV

DC high-level input voltage VIH CK, CK# Differential in pu t 0.65 × VDD –mV

DC low-level input voltage VIL CK, CK# Differential input – 0.35 × VDD mV

Input differential-pair cross

voltage VIX CK, CK# D ifferential input (VDDQ/2) - 0.15 (VDDQ/2) + 0.15 V

Input differential voltage VID(DC) CK, CK# Differential input 0.3 VDDQ + 0.4 V

Input differential voltage VID(AC) CK, CK# Differential input 0.6 VDDQ + 0.4 V

Input current IIRESET# VI = VDDQ or VSSQ –10 10 µA

CK, CK# VI = VDDQ or VSSQ –250 250 µA

Output disabled current IODL RESET# = VSSQ;

VI = VIH(AC) or VIL(DC)100 – µA

Static supply current IDDLD CK = CK# = LOW – 500 µA

Dynamic supply IDD N/A CK , CK# = 270 MHz, all

outputs open

(not connected to PCB)

–300mA

Input capacitance CIN Each input VI = VDDQ or VSSQ2 3pF

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

PLL Specifications

Table 16: Serial Presence-Detect Matrix

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”

Byte Description Entry (Version) MT18HTS12872CH MT18HTS25672CH

0Number of SPD bytes used by Mi cron 128 80 80

1Total number of bytes in SPD device 256 08 08

2Fundamental memory type DDR2 SDRAM 08 08

3Number of row addresses on assembly 14 0E 0E

4Number of column addresses on assembly 10 0A 0A

5DIMM height and module ranks 30mm, dual rank 61 61

6Module data width 72 48 48

7Module data width (continued) 00000

8Module voltage interface levels SSTL 1.8V 05 05

9SDRAM cycle time, tCK (CL = maximum value, see

byte 18) -667

-53E

-40E

10 SDRAM access from clock,tAC (CL = maximum value,

see byte 18) -667

-53E

-40E

11 Module configuration type ECC 02 02

12 Refresh rate/type 7.81µs/SELF 82 82

13 SDRAM device width (pri mary SDRAM) 80808

14 Error-checking SDRAM data width 80808

15 Minimum clock delay, back-to-back random column

access 1 clock 00 00

16 Burst lengths supported 4, 8 0C 0C

17 Number of banks on SDRAM device 4

804

––

18 CAS latencies supported -667 (5, 4, 3)

-53E/-40E (4, 3) 38

18 38

19 Module thickness 01 01

20 DDR2 DIMM type SODIMM 04 04

21 SDRAM module attributes No register, 1 PLL 04 04

22 SDRAM device attributes: weak driver (01) or 50Ω

ODT (03) -667

-53E/-40E 03

01 03

23 SDRAM cycle time, tCK, MAX CL - 1 -667

-53E/-40E 3D

50 3D

24 SDRAM access from CK, tAC,

MAX CL - 1 -667

-53E

-40E

25 SDRAM cycle time, tCK, MAX CL - 2 -667

-53E/-40E(N/S) 50

00 50

26 SDRAM access from CK, tAC,

MAX CL - 2 -667

-53E/-40E(N/S) 45

00 45

27 Minimum row precharge time, tRP 3C 3C

28 Minimum row active to row active, tRRD 1E 1E

29 Minimum RAS#-to-CA S# del ay, tRCD 3C 3C

30 Minimum RAS# pulse width, tRAS -667/-53E

-40E 2D

28 2D

31 Module rank density 512MB

1GB 80

––

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

PLL Specifications

Notes: 1. The tRC SPD values shown are JEDEC DDR2 device specification values. The actual Micron

DDR2 device specification is tRC = 55ns for all speed grades.

32 Address and command setup time, tISb-667

-53E

-40E

33 Address and command hold time, tIHb-667

-53E

-40E

34 Data/data mask input setup time, tDSb-667/-53E

-40E 10

15 10

35 Data/data mask input hold time, tDHb-667

-53E

-40E

36 Write recovery time, tWR 3C 3C

37 WRITE-to-READ command delay, tWTR -667/-53E

-40E 1E

28 1E

38 READ-to-PRECHARGE CMD delay, tRTP 1E 1E

39 Memory analysis probe 00 00

40 Extension for bytes 41 and 42 -667

-53E/-40E 00

00 06

41 MIN active auto refresh time, tRC1-667/-53E

-40E 3C

37 3C

42 Minimum AUTO REFRESH to ACTIVE/AUTO REFRESH

command period, tRFC 69 7F

43 SDRAM device MAX cycle time, tCK (MAX) 80 80

44 SDRAM device MAX DQS-DQ skew time, tDQSQ -667

-53E

-40E

45 SDRAM device MAX read data hold skew factor,

tQHS -667

-53E

-40E

46 PLL relock time 0F 0F

47–61 Optional features, not supported 00 00

62 SPD revision Release 1.2 12 12

63 Checksum for bytes 0–62 -667

-53E

-40E

64 Manufacturer’s JEDEC ID code MICRON 2C 2C

65-71 Manufacturer’s JEDEC ID code (continued) FF FF

72 Manufacturing location 01–12 01–0C 01–0C

73-90 Module part number (ASCII) Variable data Variable data

91 PCB identification code 1–9 01–09 01–09

92 Identification code (Continued) 00000

93 Year of manufacture in BCD Variable data Variable data

94 Week of manufacture in BCD Variable data Variable data

95-98 Module serial number Variable data Variable data

99–127 Manufacturer-specific data (RSVD) 00 00

128-255 Customer reserved FF FF

Table 16: Serial Presence-Detect Matrix

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”

Byte Description Entry (Version) MT18HTS12872CH MT18HTS25672CH

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Temperature Sensor

The optional temperature sensor continuously monitors the module’s temperature and

can be read back at any time over the I2C bus shar e d with the SPD. This sensor compl i es

with the JEDEC standard JC-42.4, covering a range from –20°C to +125°C.

EVENT# Pin

The temperatur e sensor also adds the EVENT# pin. N ot used b y the SPD, the EVENT# is a

temperature sensor output used to flag critical events that can be set up in the sensor’s

configuration register.

EVENT# has thre e defined modes of operation: interrupt mode, compare mode, and

critical temperature mode. The open-drain output of EVENT# under the three separate

operating modes is illustrated in Figure 3 on page 17. Event thresholds are programmed

in the 0x01 register using a hysteresis. The alarm window provides a comparison

window, with upper and lower limits set in the alarm upper boundary register and the

alarm lower boundary register, respectively. When the alarm window is enabled,

EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by

the user.

The interrupt mode allows software to reset EVENT# after a critical temperature

threshold has been detected. Threshold points ar e set in the configuration r egister b y the

user. This mode triggers the critical temper ature limit and both the MIN and MAX of the

temperature window.

The compar e mode is similar to the inte rrupt mode, except EVENT # cannot be reset by

the user and only returns to the logic HIGH state once temperature falls below the

programmed thresholds.

Critical te m perature mode tr iggers EVENT# only when th e te mperature has exceeded

the programmed critical trip point. Once the critical trip point has been reached, the

temperature sensor goes into comparator mode and the critical EVENT # cannot be

cleared through software.

Table 17: Temperature Sensor EEPROM AC Timing

Parameter/Condition Symbol Min Max Units

Time the bus must be free before a new

transition can start

tBUF 4.7 – µs

SDA and SCL fall time tF–300ns

Data hold time tHD:DAT 300 – ns

Start condition hold time tHD:STA 4.0 – µs

Clock HIGH period tHIGH 4 50 µs

Clock LOW period tLOW 4.7 – µs

SDA and SCL rise time tR – 1000 ns

SCL clock frequency fSCL – 400 KHz

Data setup time tSU:DAT 250 – ns

Start condition setup time tSU:STA 4.7 – µs

Stop condition setup time tSU:STO 4 – µs

Clock frequency tCK 10 100 KHz

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Temperature Sensor

SM Bus Slave Subaddress Decoding

The temperature sensor’s physical address differ s from current SPD device physical

addresses: 0011 for A0, A1, A2 and RW in binary wher e A2, A1, and A0 are the three slave

subaddress pins and the RW pin is the READ/WRITE flag.

If the slave base address is fixed for the SPD and temperature sensor, then the pins set

the subaddress bits of the slave address, allowing the devices to be located anywhere

within the 8 slave address locations. For example, they could be set from 30h to 3Eh.

Figure 3: EVENT# Pin Functionality

Table 18: Temperature Sensor Registers

Name Address (Hex) Power-On Default

Pointer register Not applicable Undefined

Capability register 0x00 0x0001

Configuration register 0x01 0x0000

Alarm temperature upper boundary register 0x02 0x0000

Alarm temperature lower boundary register 0x03 0x0000

Critical temperature register 0x04 0x0000

Temperature register 0x05 Undefined

Time

Temp

Critical

Alarm Window (MAX)

Alarm Window (MIN)

EVENT#

Interrupt Mode

EVENT#

Comparator Mode

EVENT#

Critical Temperature Only Mode

S/v clears event

Hysteresis affects

these trip points

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Pointer Register

Pointer Register The pointer register selec ts which of the 16-bi t registers is being acc ess ed in subse quent

READ and WRITE operations. It is a write-only register.

Capability Register

The capability register indicates the features and functionality supported b y the te mper-

ature sensor. It is a read-only re gister.

Table 19: Pointer Register Bits 0–7

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

0000Register

select Register

select

Table 20: Pointer Register Bits 0–2 Descriptions

Bit2 Bit1 Bit0 Register

00 0

Capability register

00 1

Configuration register

01 0

Alarm temp upper boundary register

01 1

Alarm temp lower boundary register

10 0

Critical temp register

10 1

Temperature register

Table 21: Capability Register Bits

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

RFU

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

RFU TRES1 TRES0 Wider range Precision Has alarm and

critical

temperature

Table 22: Capability Register Bit Descriptions

Bit Description and Values

0Basic capability

1: Has alarm and critical trip-point capabilities.

1Accuracy

0: ±2°C over the active range and ±3°C over the monitor range.

1: ±1°C over the active range and ±2°C over the monitor range.

2Wider range

0: Values lower than 0°C ar e c lamped to a binary value of 0.

1: Temperatures below 0°C can be read.

4:3 Temperature resolution

00: 0.5°C LSB

01: 0.25°C LCB

10: 0.125°C LSB

11: 0.0625°C LSB

15:5 0: Must be set to zero.

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Configuration Register

Table 23: Configuration Register Bits 0–15

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

RFU Hysteresis Shutdown

mode

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Critical lock

bit Alarm lock bit Clear event Event output status Critical

event only Event

polarity Event mode

Table 24: Configuration Register Bit Descriptions

Bit Description and Values Notes

0Event mode

0: Comparator mode

1: Interrupt mode

Cannot be changed if either of the lock bits are set.

1EVENT# polarity

0: Active LOW

1: Active HIGH

Cannot be changed if either of the lock bits are set.

2Critical event only

0: EVENT# trips on alarm or critical temperature event.

1: EVENT# trips only if critical temperature is reached.

3Event output control

0: Event output disabled

1: Event output enabled

4Event status

0: EVENT# has not been asserted by this device.

1: EVENT# is being asserted due to an alarm window or

critical temperature cond ition.

This is a read-only field; the event causing the event can be

determined from the read temperature register.

5Clear event

0: No effect

1: Clears the event when the temperature sensor is in

interrupt mode.

This is a write-only field and is self clearing.

6Alarm window lock bit

0: Alarm trips are not locked and can be changed.

1: Alarm trips are not locked and cannot be changed.

7Critical trip lock bit

0: Critical trip is not locked and can be changed.

1: Critical trip is not locked and cannot be changed.

8Shutdown mode

0: Enabled

1: Shutdown

The shutdown mode is a power saving mode that disables

the temperature sensor.

10:9 Hysteresis enable

00: Disable

01: Enable at 1.5°C

10: Enable at 3°C

11: Enable at 6°C

When enabled, a hysteresis is applied to temperature

movement around the trip points. For example, if the

hysteresis register is enabled to a delta of 6°C, the preset trip

points will toggle once the temperature reaches the

programmed value. These values will reset once the

temperature drops below the trip points minus the set

hysteresis level. In this case, critical temperature - 6°C.

The hysteresis is applied to both the above alarm window

and below alarm window bits found in the read-only

temperature register. EVENT# is also affected by this register.

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Configuration Register

Figure 4: Hysteresis

Notes: 1. TH - Value set in the alarm temperature upper boun dary trip register

2. TL - Value set in the alarm temperature lower boundary trip register

3. Hyst - Value set in the hyst eresis bits of the co nfiguration r egister

Table 25: Hysteresis

Condition Below Alarm Window Bit Above Alarm Window Bit

Temperature gradient Critical temperature Temperature gradient Critical temperature

Sets Falling TL - Hyst Rising TH

Clears Rising TLFalling TH - Hyst

TH - Hyst

TL - Hyst

Below Window Bit

Above Window Bit

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Temperature Format

The temperature trip-point registers and temperature re adout register use a two’s

complement format to enable negative numbers. The least significant bit is equal to

0.0625°C or 0.25°C, depending on which register is referenced. For example, assuming a

LSB of 0.0625°C:

• A value of 0x018C would equal +24.75°C

• A value of 0x06C0 would equal +108°C

• A value of 0x1E74 would equal –24.75°C

Upper Temperature Boundary Register

The upper temperatur e b oundary register is used to set the maximum val ue of the alarm

windo w. The least significant bit for this register i s 0.25°C. All RFU bits in the r eg ister will

always report zero.

Lower Temperature Boundary Register

The lower temperature boundary register is used to set the minimum value of the alarm

windo w. The least significant bit for this register is 0.25°C. All RFU bits in the r egister wi ll

always report zero.

Critical Temperature Register

The critical temperature register is used to set the maximum temperature above the

alarm window. The least significant bit for this register is 0.25°C. All RFU bits in the

Table 26: Upper Temperature Boundary Register Bits

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Alarm window upper boundary temperature

Table 27: Lower Temperature Boundary Register Bits

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Alarm window lower boundary temperature

Table 28: Critical Temperature Register Bits

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Critical temperature trip point

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1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Temperature Format

Temperature Register

The temperature r egister is a read-only register that provides the current temperature

detected by the temperature sensor. The least significant bit for this register is 0.0625°C

with a resolution of 0.0625°C. The most significant bit is 128°C in the readout section of

this register.

The upper three bits of the register are used to monitor the trip points that are set in the

prev ious t hree reg isters.

Table 29: Temperature Register Bits

15 14 13 12 11 10 9876543210

Above

critical

trip

Above

alarm

window

Below

alarm

window

MSB LSB

Temperature

Table 30: Temp erature Register Bit Descriptions

Bit Description and Values

13 Below alarm window

0: Temperature is equal to or above the lower boundary.

1: Temperature is below ala rm window.

41 Above alarm window

0: Temperature is equal to or belo w the upper boundary.

1: Temperature is above alarm window.

15 Above critical trip point

0: Temperature is below critical trip point.

1: Temperature is above critical trip point.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Com m ent Line: 800-93 2-4992

Micron, the M logo, TwinDie, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the

property of their respective owners.

1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM

Module Dimensions

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Module Dimensions

The dimensional diagram is for reference only. Refer to the MO document for complete

design dimensions.

Figure 5: 200-Pin DDR2 SOCDIMM Dimensions

Notes: 1. All dimensions are in millimeters (inches) MAX/MIN or typical (TYP) where noted.

3.80 (0.150) MAX

PIN 1

67.75 (2.667)

20.0 (0.787)

TYP

1.80 (0.071)

(2X)

0.60 (0.024)

TYP

0.45 (0.018)

TYP

2.0 (0.079) R

(2X)

PIN 199

PIN 200 PIN 2

FRONT VIEW

2.00 (0.079)

TYP

6.0 (0.236)

TYP

63.60 (2.504)

TYP

3.50 (0.138) TYP

30.15 (1.187)

29.85 (1.175)

BACK VIEW

1.10 (0.043)

0.90 (0.035)

47.4 (1.87)

TYP 11.4 (0.45)

TYP

4.2 (0.165)

TYP

0.50 (0.0197) R

16.26 (0.64)

TYP

U1 U2 U5

U7 U8

U9 U10 U11 U12 U13

1.0 (0.039)

TYP

10.00 (0.787)

TYP

1.0 (0.039) R

(2X)