1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Features DDR2 SDRAM SOCDIMM MT18HTS12872CH - 1GB MT18HTS25672CH - 2GB For component data sheets, refer to Micron's Web site: www.micron.com/products/ddr2sdram Features Figure 1: * 200-pin, small outline, dual in-line memory module (SODIMM) * Fast data transfer rates: PC2-3200, PC2-4200, and PC2-5300 * 1GB (128 Meg x 72), 2GB (256 Meg x 72) * Supports ECC error detection and correction * VDD = VDDQ = +1.8V * VDDSPD = +3.0V to +3.6V * JEDEC standard 1.8V I/O (SSTL_18-compatible) * Differential data strobe (DQS, DQS#) option * Four-bit prefetch architecture * DLL to align DQ and DQS transitions with CK * Multiple internal device banks for concurrent operation * Programmable CAS# latency (CL) * Posted CAS additive latency (AL) * WRITE latency = READ latency - 1 tCK * Programmable burst lengths: 4 or 8 * Adjustable data-output drive strength * 64ms, 8,192-cycle refresh * On-die termination (ODT) * Serial presence-detect (SPD) with EEPROM * Phase-lock loop (PLL) to reduce system clock line loading * Gold edge contacts * Dual rank * I2C temperature sensor Table 1: 200-Pin SOCDIMM (MO-224 R/C "B") Height 30.0mm (1.18in) Options Marking * Package - 200-pin SODIMM (Pb-free) * Frequency/CL1 - 3.0ns @ CL = 5 (DDR2-667) - 3.75ns @ CL = 4 (DDR2-533) - 5.0ns @ CL = 3 (DDR2-400) * PCB height - 30.0mm (1.18in) Y -667 -53E -40E Notes: 1. CL = CAS (READ) latency. Address Table Refresh count Row addressing Device bank addressing Device page size per bank Device configuration Column addressing Module rank addressing PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 1GB 2GB 8K 16K (A0-A13) 4 (BA0, BA1) 1KB 1Gb TwinDie (128 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) 8K 16K (A0-A13) 8 (BA0, BA1, BA2) 1KB 2Gb TwinDie (256 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Features Table 2: Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 5 CL = 4 CL = 3 RCD (ns) t RP (ns) t RC (ns) -667 -53E -40E PC2-5300 PC2-4200 PC2-3200 667 - - 533 533 400 400 400 400 15 15 15 15 15 15 55 55 55 Table 3: t Part Numbers and Timing Parameters - 1GB Modules Base device: MT47H128M8THK, 1Gb TwinDieTM DDR2 SDRAM Part Number1 MT18HTS12872CHY-667__ MT18HTS12872CHY-53E__ MT18HTS12872CHY-40E__ Table 4: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL - tRCD - tRP) 1GB 1GB 1GB 128 Meg x 72 128 Meg x 72 128 Meg x 72 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 4-4-4 3-3-3 Part Numbers and Timing Parameters - 2GB Modules Base device: MT47H256M8THJ, 2Gb TwinDie DDR2 SDRAM Part Number1 MT18HTS25672CHY-667__ MT18HTS25672CHY-53E__ MT18HTS25672CHY-40E__ Notes: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL - tRCD - tRP) 2GB 2GB 2GB 256 Meg x 72 256 Meg x 72 256 Meg x 72 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 4-4-4 3-3-3 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18HTS25672CHY-40EC2. 2. For the latest component data sheets, see Micron's Web site: www.micron.com/products/ ddr2sdram PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 200-Pin SODIMM Front 200-Pin SODIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 VREF DQ0 Vss DQ1 DQS0# DQS0 Vss DQ2 DQ3 Vss DQ8 DQ9 Vss DQS1# DQS1 Vss DQ10 DQ11 Vss DQ16 DQ17 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 DQ18 DQ19 Vss DQ24 DQ25 Vss DQS3# DQS3 Vss DQ26 DQ27 Vss CB0 CB1 Vss DQS8# DQS8 Vss CKE0 CKE1 EVENT# 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 VDD A5 A3 A2 VDD A10 BA0 RAS# VDD CAS# S1# VDD ODT1 NC DQ32 VSS DQ33 DQS4# DQS4 VSS DQ34 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 43 45 47 49 Vss DQS2# DQS2 Vss 93 95 97 99 VDD A12 A9 A7 143 145 147 149 DQ35 VSS DQ40 DQ41 193 195 197 199 DQ58 VSS DQ59 VDDSPD 44 46 48 50 Notes: VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS RESET# DM2 Vss DQ22 DQ23 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 VSS DQ28 DQ29 VSS DM3 VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 VSS CB6 CB7 VSS CB2 CB3 VSS NC/BA2 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 A6 A4 VDD A1 A0 BA1 VDD WE# S0# ODT0 A13 VDD CK0 CK0# VSS DQ36 DQ37 VSS DM4 VSS DQ38 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 VSS DM5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 DQ62 VSS DQ63 94 NC/A14 144 96 A11 146 148 98 VDD 100 A8 150 DQ39 VSS DQ44 DQ45 194 196 198 200 SDA SCL SA1 SA0 1. Pin 92 is NC for 1GB, BA2 for 2GB. PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Refer to Table 5 for pin assignments Symbol Type Description ODT0, ODT1 Input CK0, CK0# Input CKE0, CKE1 Input S0#, S1# Input RAS#, CAS#, WE# Input BA0, BA1 (1GB) BA0, BA1, BA2 (2GB) A0-A13 Input DM0-DM8 Input DQ0-DQ63 CB0-CB7 DQS0-DQS8, DQS0#-DQS8# I/O I/O I/O EVENT# SCL Output Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all device banks idle), or ACTIVE power-down (row ACTIVE in any device bank). CKE is synchronous for power-down entry, power-down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down . Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level once VDD is applied during first power-up. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH operation VREF must be maintained to this input. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Bank address inputs: BA0-BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied BA0-BA1/BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command. Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0-BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. Data input/output: Bidirectional data bus. Check bits Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Temp sensor alarm output Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions (Continued) Refer to Table 5 for pin assignments Symbol Type Description SA0-SA1 Input SDA Input/ Output Supply Supply Supply Supply Presence-detect address inputs: These pins are used to configure the presencedetect device. Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Power supply: +1.8V 0.1V. SSTL_18 reference voltage Ground Serial EEPROM positive power supply: +3.0V to +3.6V. VDD VREF VSS VDDSPD PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# S0# DQS0# DQS0 DM0 DQS4# DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U1b CS# DQ DM DQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1t DQS1# DQS1 DM1 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U7b CS# DQ DQS# U7b DQS5# DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U13b CS# DQ DM DQS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U13t DQS2# DQS2 DM2 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U10b CS# DQ DQS# U10t DQS6# DQS6 DM6 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U2b CS# DQ DM DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2t DQS3# DQS3 DM3 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U8b CS# DQ DQS# U8t DQS7# DQS7 DM7 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U12b CS# DQ DM DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U12t CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U9b CS# DQ DQS# U9t DQS8# DQS8 DM8 DM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ U11b DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ 120 DQS# CK0 CK0# U11t TBD U4 Serial PD WP A0 SCL CAS#: DDR2 SDRAMs WE#: DDR2 SDRAMs CKE0: DDR2 SDRAMs Rank 0 CKE1: DDR2 SDRAMs Rank 1 ODT0: DDR2 SDRAMs Rank 0 ODT1: DDR2 SDRAMs Rank 1 SDA A2 A1 SDA A2 SA0 SA1 Event# 3 BA0-BA1/BA2: DDR2 SDRAMs A0-A12/A13: DDR2 SDRAMs RAS#: DDR2 SDRAMs U1, U13 U2, U12 U11 U7, U10 U8, U9 SA0 SA1 EVT A0 Notes: A1 U3 Temp Sensor Rank 0 = U1b, U2b, U7b - U13b Rank 1 = U1t, U2t, U7t - U13t BA0-BA1/BA2 A0-A12/A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 CLK0/CLK0# CLK1/CLK1# CLK2/CLK2# CLK3/CLK3# CLK4/CLK4# U6 PLL VDDSPD Serial PD, Temp Sensor VDD DDR2 SDRAMS VDDQ DDR2 SDRAMS VREF DDR2 SDRAMS VSS DDR2 SDRAMS 1. Unless otherwise noted, resistor values are 22. PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM General Description General Description The MT18HTS12872CH and MT18HTS25672CH DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 1GB and 2GB memory modules, organized in a x72 configuration. These DDR2 SDRAM modules use TwinDieTM DDR2 SDRAM devices internally configured as quad-bank (1Gb) or 8-bank (2Gb). DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Phase-Lock Loop Operation A PLL chip on the module receives and redrives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The PLL minimizes system clock line loading. PLL clock timing is defined by JEDEC specifications and is ensured by the use of a JEDEC clock reference board. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus extended mode register 2 (EMR2). PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 7: Symbol VDD VDDQ VDDL VIN, VOUT TSTG Tcase TOPR II IOZ IVREF Absolute Maximum DC Ratings Parameter Min Max Units VDD supply voltage relative to VSS VDDQ supply voltage relative to VSS VDDL supply voltage relative to Vss Voltage on any pin relative to VSS Storage temperature DDR2 SDRAM device operating temperature Operating temperature (ambient) Command/Address, Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 0.95V; (All other pins not under RAS#, CAS#, WE# test = 0V) S#, CKE CK0, CK0# DM Output leakage current; 0V VOUT VDDQ; DQs and DQ, DQS, DQS# ODT are disabled VREF leakage current; VREF = Valid VREF level -1.0 -0.5 -0.5 -0.5 -55 0 0 -90 +2.3 +2.3 +2.3 +2.3 +100 85 65 +90 V V V V C C C A -45 -10 -10 -10 +45 +10 +10 +10 A -36 +36 A Capacitance At DDR2 data rates, Micron encourages designers to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Electrical Specifications Table 8: DDR2 IDD Specifications and Conditions - 1GB Values shown for DDR2 TwinDie SDRAM components only Parameter/Condition tCK tCK tRC tRC = (IDD), = Operating one bank active-precharge current; (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; tCK = Fast PDN Exit tCK (IDD); CKE is LOW; Other control and address bus inputs MR[12] = 0 are stable; Data bus inputs are floating Slow PDN Exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open, continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = t CK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching; See IDD7 conditions for detail PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 9 Symbol -667 -53E -40E Units IDD0 918 828 828 mA IDD1 1,053 963 918 mA IDD2P 126 126 126 mA IDD2Q 513 468 423 mA IDD2N 558 513 468 mA IDD3P 378 333 288 mA 171 171 171 mA IDD3N 693 603 513 mA IDD4W 1,638 1,368 1,143 mA IDD4R 1,728 1,413 1,143 mA IDD5 1,728 1,638 1,593 mA IDD6 126 126 126 mA IDD7 2,268 2,133 2,088 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Electrical Specifications Table 9: DDR2 IDD Specifications and Conditions - 2GB Values shown for DDR2 TwinDie SDRAM components only Parameter/Condition tCK tCK tRC tRC = (IDD), = Operating one bank active-precharge current; (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; tCK = Fast PDN Exit tCK (IDD); CKE is LOW; Other control and address bus inputs MR[12] = 0 are stable; Data bus inputs are floating Slow PDN Exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open, continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open, continuous burst READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current; All device banks interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = t CK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching; See IDD7 conditions for detail PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 10 Symbol -667 -53E -40E Units IDD0 918 828 738 mA IDD1 1,008 963 828 mA IDD2P 126 126 126 mA IDD2Q 603 477 423 mA IDD2N 648 513 468 mA IDD3P 468 378 333 mA 153 153 153 mA IDD3N 738 603 513 mA IDD4W 1,548 1,278 1,098 mA IDD4R 1,548 1,413 1,098 mA IDD5 2,448 2,358 2,088 mA IDD6 126 126 126 mA IDD7 2,808 2,718 2,448 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM AC Timing and Operating Conditions AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades as shown in Table 10. Table 10: Table 11: Module and Component Speed Grade Table Module Speed Grade Component Speed Grade -667 -53E -40E -3 -37E -5E SPD Temp Sensor Select Code The most significant bit (b7) is sent first Device Type Identifier Select Code Memory area select code (two arrays) Protection register select code Table 12: Chip Enable RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW SPD Operating Modes Mode Current address read Random address read Sequential read Byte write Page write PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN RW Bit WC Bytes 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 1 1 16 11 Initial Sequence Start, device select, RW = 1 Start, device select, RW = 0, address Restart, device select, RW = 1 Similar to current or random address read Start, device select, RW = 0 Start, device select, RW = 0 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM AC Timing and Operating Conditions Table 13: Serial Presence-Detect EEPROM and Temperature Sensor DC Operating Conditions All voltages referenced to VSS; VDDSPD = +3.0V to +3.6V Parameter/Condition Supply voltage with temperature sensor option Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA SPD input leakage current: VIN = GND to VDD SPD output leakage current: VOUT = GND to VDD SPD standby current Power supply current, READ: SCL clock frequency = 100 KHz Power supply current, WRITE: SCL clock frequency = 100 KHz Average temperature sensor current Table 14: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 3.0 2.1 -0.6 - 0.10 0.05 1.6 0.4 2 3.6 VDDSPD + 0.5 0.8 0.4 3 3 4 1 3 500 V V V V A A A mA mA A Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +3.0V to +3.6V Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: Symbol Min Max Units Notes tAA 0.2 1.3 200 0.9 s s ns ns s s s ns s s KHz ns s s ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT tSU:STA t SU:STO t WRC 100 0.6 0.6 10 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM PLL Specifications PLL Specifications Table 15: PLL Device Specifications Uses a 97ULP845AHL or equivalent JEDEC device Parameter Symbol Pins Condition DC high-level input voltage DC low-level input voltage Input voltage (limits) DC high-level input voltage DC low-level input voltage Input differential-pair cross voltage Input differential voltage Input differential voltage Input current VIH VIL VIN VIH VIL VIX RESET# RESET# RESET#, CK, CK# CK, CK# CK, CK# CK, CK# LVCMOS LVCMOS VID(DC) VID(AC) II CK, CK# CK, CK# RESET# CK, CK# Output disabled current IODL Static supply current Dynamic supply IDDLD IDD N/A CIN Each input Input capacitance PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN Differential input Differential input Differential input Differential input Differential input VI = VDDQ or VSSQ VI = VDDQ or VSSQ RESET# = VSSQ; VI = VIH(AC) or VIL(DC) CK = CK# = LOW CK, CK# = 270 MHz, all outputs open (not connected to PCB) VI = VDDQ or VSSQ 13 Min Max 0.65 x VDD - - 0.35 x VDD -0.3 VDDQ + 0.3 0.65 x VDD - - 0.35 x VDD (VDDQ/2) - 0.15 (VDDQ/2) + 0.15 Units mV mV mV mV mV V 0.3 0.6 -10 -250 100 VDDQ + 0.4 VDDQ + 0.4 10 250 - V V A A A - - 500 300 A mA 2 3 pF Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM PLL Specifications Table 16: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW" Byte Description Entry (Version) 0 1 2 3 4 5 6 7 8 9 Number of SPD bytes used by Micron Total number of bytes in SPD device Fundamental memory type Number of row addresses on assembly Number of column addresses on assembly DIMM height and module ranks Module data width Module data width (continued) Module voltage interface levels SDRAM cycle time, tCK (CL = maximum value, see byte 18) 10 SDRAM access from clock,tAC (CL = maximum value, see byte 18) 11 12 13 14 15 16 17 Module configuration type Refresh rate/type SDRAM device width (primary SDRAM) Error-checking SDRAM data width Minimum clock delay, back-to-back random column access Burst lengths supported Number of banks on SDRAM device 18 CAS latencies supported 19 20 21 22 Module thickness DDR2 DIMM type SDRAM module attributes SDRAM device attributes: weak driver (01) or 50 ODT (03) SDRAM cycle time, tCK, MAX CL - 1 23 24 SDRAM access from CK, tAC, MAX CL - 1 25 SDRAM cycle time, tCK, MAX CL - 2 26 27 28 29 30 SDRAM access from CK, tAC, MAX CL - 2 Minimum row precharge time, tRP Minimum row active to row active, tRRD Minimum RAS#-to-CAS# delay, tRCD Minimum RAS# pulse width, tRAS 31 Module rank density PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 128 256 DDR2 SDRAM 14 10 30mm, dual rank 72 0 SSTL 1.8V -667 -53E -40E -667 -53E -40E ECC 7.81s/SELF 8 8 1 clock 80 08 08 0E 0A 61 48 00 05 30 3D 50 45 50 60 02 82 08 08 00 80 08 08 0E 0A 61 48 00 05 30 3D 50 45 50 60 02 82 08 08 00 4, 8 4 8 -667 (5, 4, 3) -53E/-40E (4, 3) 0C 04 - 38 18 01 04 04 03 01 3D 50 45 50 60 50 00 45 00 3C 1E 3C 2D 28 80 - 0C - 08 38 18 01 04 04 03 01 3D 50 45 50 60 50 00 45 00 3C 1E 3C 2D 28 - 01 SODIMM No register, 1 PLL -667 -53E/-40E -667 -53E/-40E -667 -53E -40E -667 -53E/-40E(N/S) -667 -53E/-40E(N/S) -667/-53E -40E 512MB 1GB 14 MT18HTS12872CH MT18HTS25672CH Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM PLL Specifications Table 16: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW" Byte Description Entry (Version) t 32 Address and command setup time, ISb 33 Address and command hold time, tIHb 34 Data/data mask input setup time, tDSb 35 Data/data mask input hold time, tDHb 36 37 Write recovery time, tWR WRITE-to-READ command delay, tWTR 38 39 40 READ-to-PRECHARGE CMD delay, tRTP Memory analysis probe Extension for bytes 41 and 42 41 MIN active auto refresh time, tRC1 42 Minimum AUTO REFRESH to ACTIVE/AUTO REFRESH command period, tRFC SDRAM device MAX cycle time, tCK (MAX) SDRAM device MAX DQS-DQ skew time, tDQSQ 43 44 45 -667 -53E -40E -667 -53E -40E -667/-53E -40E -667 -53E -40E -667/-53E -40E -667 -53E/-40E -667/-53E -40E SDRAM device MAX read data hold skew factor, tQHS 46 47-61 62 63 PLL relock time Optional features, not supported SPD revision Checksum for bytes 0-62 64 65-71 72 73-90 91 92 93 94 95-98 99-127 128-255 Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (Continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Manufacturer-specific data (RSVD) Customer reserved Notes: -667 -53E -40E -667 -53E -40E Release 1.2 -667 -53E -40E MICRON (continued) 01-12 1-9 0 MT18HTS12872CH MT18HTS25672CH 20 25 35 27 37 47 10 15 17 22 27 3C 1E 28 1E 00 00 00 3C 37 69 20 25 35 27 37 47 10 15 17 22 27 3C 1E 28 1E 00 06 06 3C 37 7F 80 18 1E 23 22 28 2D 0F 00 12 73 1E 85 2C FF 01-0C Variable data 01-09 00 Variable data Variable data Variable data 00 FF 80 18 1E 23 22 28 2D 0F 00 12 14 BF 26 2C FF 01-0C Variable data 01-09 00 Variable data Variable data Variable data 00 FF 1. The tRC SPD values shown are JEDEC DDR2 device specification values. The actual Micron DDR2 device specification is tRC = 55ns for all speed grades. PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor Temperature Sensor The optional temperature sensor continuously monitors the module's temperature and can be read back at any time over the I2C bus shared with the SPD. This sensor complies with the JEDEC standard JC-42.4, covering a range from -20C to +125C. Table 17: Temperature Sensor EEPROM AC Timing Parameter/Condition Symbol Time the bus must be free before a new transition can start SDA and SCL fall time Data hold time Start condition hold time Clock HIGH period Clock LOW period SDA and SCL rise time SCL clock frequency Data setup time Start condition setup time Stop condition setup time Clock frequency t BUF t F tHD:DAT tHD:STA t HIGH tLOW tR fSCL tSU:DAT tSU:STA tSU:STO tCK Min Max Units 4.7 - s - 300 4.0 4 4.7 - - 250 4.7 4 10 300 - - 50 - 1000 400 - - - 100 ns ns s s s ns KHz ns s s KHz EVENT# Pin The temperature sensor also adds the EVENT# pin. Not used by the SPD, the EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor's configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. The open-drain output of EVENT# under the three separate operating modes is illustrated in Figure 3 on page 17. Event thresholds are programmed in the 0x01 register using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. The interrupt mode allows software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and only returns to the logic HIGH state once temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. Once the critical trip point has been reached, the temperature sensor goes into comparator mode and the critical EVENT# cannot be cleared through software. PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor SM Bus Slave Subaddress Decoding The temperature sensor's physical address differs from current SPD device physical addresses: 0011 for A0, A1, A2 and RW in binary where A2, A1, and A0 are the three slave subaddress pins and the RW pin is the READ/WRITE flag. If the slave base address is fixed for the SPD and temperature sensor, then the pins set the subaddress bits of the slave address, allowing the devices to be located anywhere within the 8 slave address locations. For example, they could be set from 30h to 3Eh. Figure 3: EVENT# Pin Functionality Temp Critical Hysteresis affects these trip points Alarm Window (MAX) Alarm Window (MIN) S/v clears event Time EVENT# Interrupt Mode EVENT# Comparator Mode EVENT# Critical Temperature Only Mode Table 18: Temperature Sensor Registers Name Address (Hex) Power-On Default Pointer register Capability register Configuration register Alarm temperature upper boundary register Alarm temperature lower boundary register Critical temperature register Temperature register Not applicable 0x00 0x01 0x02 0x03 0x04 0x05 Undefined 0x0001 0x0000 0x0000 0x0000 0x0000 Undefined PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Pointer Register Pointer Register The pointer register selects which of the 16-bit registers is being accessed in subsequent READ and WRITE operations. It is a write-only register. Table 19: Pointer Register Bits 0-7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 Register select Register select Register select Register select Table 20: Pointer Register Bits 0-2 Descriptions Bit2 Bit1 Bit0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Register Capability register Configuration register Alarm temp upper boundary register Alarm temp lower boundary register Critical temp register Temperature register Capability Register The capability register indicates the features and functionality supported by the temperature sensor. It is a read-only register. Table 21: Bit15 Capability Register Bits Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit4 Bit3 Bit2 Bit1 Bit0 TRES1 TRES0 Wider range Precision Has alarm and critical temperature RFU Bit7 Bit6 RFU Table 22: Bit 0 1 2 4:3 15:5 Bit5 Capability Register Bit Descriptions Description and Values Basic capability 1: Has alarm and critical trip-point capabilities. Accuracy 0: 2C over the active range and 3C over the monitor range. 1: 1C over the active range and 2C over the monitor range. Wider range 0: Values lower than 0C are clamped to a binary value of 0. 1: Temperatures below 0C can be read. Temperature resolution 00: 0.5C LSB 01: 0.25C LCB 10: 0.125C LSB 11: 0.0625C LSB 0: Must be set to zero. PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Configuration Register Configuration Register Table 23: Bit15 Configuration Register Bits 0-15 Bit14 Bit13 Bit12 Bit11 RFU Bit7 Bit6 Bit5 Critical lock bit Alarm lock bit Clear event Table 24: Bit10 Bit9 Hysteresis Bit4 Bit3 Event output status Bit8 Shutdown mode Bit2 Bit1 Bit0 Critical event only Event polarity Event mode Configuration Register Bit Descriptions Bit Description and Values Notes 0 Event mode 0: Comparator mode 1: Interrupt mode 1 EVENT# polarity 0: Active LOW 1: Active HIGH 2 Critical event only 0: EVENT# trips on alarm or critical temperature event. 1: EVENT# trips only if critical temperature is reached. 3 Event output control 0: Event output disabled 1: Event output enabled 4 Event status 0: EVENT# has not been asserted by this device. 1: EVENT# is being asserted due to an alarm window or critical temperature condition. 5 Clear event 0: No effect 1: Clears the event when the temperature sensor is in interrupt mode. 6 Alarm window lock bit 0: Alarm trips are not locked and can be changed. 1: Alarm trips are not locked and cannot be changed. 7 Critical trip lock bit 0: Critical trip is not locked and can be changed. 1: Critical trip is not locked and cannot be changed. 8 Shutdown mode 0: Enabled 1: Shutdown 10:9 Hysteresis enable 00: Disable 01: Enable at 1.5C 10: Enable at 3C 11: Enable at 6C Cannot be changed if either of the lock bits are set. Cannot be changed if either of the lock bits are set. This is a read-only field; the event causing the event can be determined from the read temperature register. This is a write-only field and is self clearing. The shutdown mode is a power saving mode that disables the temperature sensor. When enabled, a hysteresis is applied to temperature movement around the trip points. For example, if the hysteresis register is enabled to a delta of 6C, the preset trip points will toggle once the temperature reaches the programmed value. These values will reset once the temperature drops below the trip points minus the set hysteresis level. In this case, critical temperature - 6C. The hysteresis is applied to both the above alarm window and below alarm window bits found in the read-only temperature register. EVENT# is also affected by this register. PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Configuration Register Figure 4: Hysteresis TH TH - Hyst TL TL - Hyst Below Window Bit Above Window Bit Notes: Table 25: 1. TH - Value set in the alarm temperature upper boundary trip register 2. TL - Value set in the alarm temperature lower boundary trip register 3. Hyst - Value set in the hysteresis bits of the configuration register Hysteresis Condition Sets Clears Below Alarm Window Bit Temperature gradient Falling Rising PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN Above Alarm Window Bit Critical temperature TL - Hyst TL 20 Temperature gradient Rising Falling Critical temperature TH TH - Hyst Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Temperature Format Temperature Format The temperature trip-point registers and temperature readout register use a two's complement format to enable negative numbers. The least significant bit is equal to 0.0625C or 0.25C, depending on which register is referenced. For example, assuming a LSB of 0.0625C: * A value of 0x018C would equal +24.75C * A value of 0x06C0 would equal +108C * A value of 0x1E74 would equal -24.75C Upper Temperature Boundary Register The upper temperature boundary register is used to set the maximum value of the alarm window. The least significant bit for this register is 0.25C. All RFU bits in the register will always report zero. Table 26: Upper Temperature Boundary Register Bits 15 14 13 12 11 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Alarm window upper boundary temperature Lower Temperature Boundary Register The lower temperature boundary register is used to set the minimum value of the alarm window. The least significant bit for this register is 0.25C. All RFU bits in the register will always report zero. Table 27: Lower Temperature Boundary Register Bits 15 14 13 12 0 0 0 MSB 11 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Alarm window lower boundary temperature Critical Temperature Register The critical temperature register is used to set the maximum temperature above the alarm window. The least significant bit for this register is 0.25C. All RFU bits in the register will always report zero. Table 28: Critical Temperature Register Bits 15 14 13 12 0 0 0 MSB 11 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Critical temperature trip point PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Temperature Format Temperature Register The temperature register is a read-only register that provides the current temperature detected by the temperature sensor. The least significant bit for this register is 0.0625C with a resolution of 0.0625C. The most significant bit is 128C in the readout section of this register. The upper three bits of the register are used to monitor the trip points that are set in the previous three registers. Table 29: 15 Temperature Register Bits 14 13 Above Above Below critical alarm alarm trip window window Table 30: 12 11 10 9 8 5 4 3 2 1 0 LSB Temperature Temperature Register Bit Descriptions Description and Values 13 Below alarm window 0: Temperature is equal to or above the lower boundary. 1: Temperature is below alarm window. Above alarm window 0: Temperature is equal to or below the upper boundary. 1: Temperature is above alarm window. Above critical trip point 0: Temperature is below critical trip point. 1: Temperature is above critical trip point. 15 6 MSB Bit 41 7 PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM Module Dimensions Module Dimensions The dimensional diagram is for reference only. Refer to the MO document for complete design dimensions. Figure 5: 200-Pin DDR2 SOCDIMM Dimensions FRONT VIEW 3.80 (0.150) MAX 67.75 (2.667) 67.75 (2.667) U3 2.0 (0.079) R (2X) U5 U1 1.0 (0.039) R (2X) 1.80 (0.071) (2X) U7 U2 U8 30.15 (1.187) 29.85 (1.175) 20.0 (0.787) TYP U6 6.0 (0.236) TYP 0.50 (0.0197) R 2.00 (0.079) TYP 1.10 (0.043) 0.90 (0.035) 0.45 (0.018) TYP 0.60 (0.024) TYP PIN 199 PIN 1 63.60 (2.504) TYP BACK VIEW U9 U10 U11 U12 U13 10.00 (0.787) TYP 3.50 (0.138) TYP 4.2 (0.165) TYP PIN 200 47.4 (1.87) TYP 1.0 (0.039) TYP PIN 2 11.4 (0.45) TYP 16.26 (0.64) TYP Notes: 1. All dimensions are in millimeters (inches) MAX/MIN or typical (TYP) where noted. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, TwinDie, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. PDF: 09005aef8253e3ea/ Source: 09005aef8253e404 HTS18C128_256x72CH.fm - Rev. A 9/06 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.