© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 5 1Publication Order Number:
NB4N840M/D
NB4N840M
3.3V 3.2Gb/s Dual
Differential Clock/Data 2 x 2
Crosspoint Switch with
CML Output and Internal
Termination
Description
The NB4N840M is a high−bandwidth fully differential dual
2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
applications such as SDH/SONET, DWDM, Gigabit Ethernet and
high speed switching. Fully differential design techniques are used to
minimize jitter accumulation, crosstalk, and signal skew, which make
this device ideal for loop−through and protection channel switching
applications.
Internally terminated differential CML inputs accept AC−coupled
LVPECL (Positive ECL) or direct coupled CML signals. By providing
internal 50 W input and output termination resistor, the need for
external components is eliminated and interface reflections are
minimized. Differential 16 mA CML outputs provide matching
internal 50 W terminations, and 400 mV output swings when
externally terminated, 50 W to VCC.
Single−ended LVCMOS/LVTTL SEL inputs control the routing of
the signals through the crosspoint switch which makes this device
configurable as 1:2 fan−out, repeater or 2 x 2 crosspoint switch. The
device is housed in a low profile 5 x 5 mm 32−pin QFN package.
Features
•Plug−in compatible to the MAX3840 and SY55859L
•Maximum Input Clock Frequency 2.7 GHz
•Maximum Input Data Frequency 3.2 Gb/s
•225 ps Typical Propagation Delay
•80 ps Typical Rise and Fall Times
•7 ps Channel to Channel Skew
•430 mW Power Consumption
•< 0.5 ps RMS Jitter
•7 ps Peak−to−Peak Data Dependent Jitter
•Power Saving Feature with Disabled Outputs
•Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
•CML Output Level (400 mV Peak−to−Peak Output), Differential
Output
•These are Pb−Free Devices
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 8 o
f
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
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32
1NB4N
840M
ALYWG
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
CML
CML
CML
CML
CML
CML
CML
CML
0
1
0
1
0
1
0
1
Figure 1. Functional Block Diagram
QA0
QA0
ENA0
SELA0
QA1
QA1
ENA1
SELA1
QB0
QB0
ENB0
SELB0
QB1
QB1
ENB1
SELB1
DA0
DA0
DA1
DA1
DB0
DB0
DB1
DB1
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Table 1. TRUTH TABLE
SELA0/SELB0 SELA1/SELB1 ENA0/ENA1 ENB0/ENB1 QA0/QB0 QA1/QB1 Function
L L H H DA0/DB0 DA0/DB0 1:2 Fanout
L H H H DA0/DB0 DA1/DB1 Quad Repeater
H L H H DA1/DB1 DA0/DB0 Crosspoint Switch
H H H H DA1/DB1 DA1/DB1 1:2 Fanout
X X L L Disable/Power Down Disable/Power Down No output (@ VCC)
Figure 2. Pin Configuration (Top View)
32 31 30 29 28 27 26 25
9 10 11121314 1516
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ENB1
SELB1
DB1
DB1
DB0
ENB0
SELB0
DB0
GND
VCC
QA0
QA1
QA1
VCC
QA0
VCC
GND
VCC
VCC
QB0
QB0
QB1
QB1
VCC
ENA1
DA1
DA1
DA0
DA0
ENA0
SELA0
SELA1
NB4N840M
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Table 2. PIN DESCRIPTION
Pin Name I/O Description
1 ENB1 LVTTL Channel B1 Output Enable. LVTTL low input powers down B1 output stage.
2 DB1 CML Input Channel B1 Positive Signal Input
3 DB1 CML Input Channel B1 Negative Signal Input
4 ENB0 LVTTL Channel B0 Output Enable. LVTTL low input powers down B0 output stage.
5 SELB0 LVTTL Channel B0 Output Select. See Table 1.
6 DB0 CML Input Channel B0 Positive Signal Input
7 DB0 CML Input Channel B0 Negative Signal Input
8 SELB1 LVTTL Channel B1 Output Select. See Table 1.
9,24 GND − Supply Ground. All GND pins must be externally connected to power supply to guarantee
proper operation.
10, 13, 16,
17, 20, 23 VCC −Positive Supply. All VCC pins must be externally connected to power supply to guarantee
proper operation.
11 QB0 CML Output Channel B0 Negative Output.
12 QB0 CML Output Channel B0 Positive Output.
14 QB1 CML Output Channel B1 Negative Output.
15 QB1 CML Output Channel B1 Positive Output.
18 QA1 CML Output Channel A1 Negative Output.
19 QA1 CML Output Channel A1 Positive Output.
21 QA0 CML Output Channel A0 Negative Output.
22 QA0 CML Output Channel A0 Positive Output.
25 SELA1 LVTTL Channel A1 Output Select, LVTTL Input. See Table 1.
26 DA0 CML Input Channel A0 Positive Signal Input.
27 DA0 CML Input Channel A0 Negative Signal Input.
28 SELA0 LVTTL Channel A0 Output Select, LVTTL Input. See Table 1.
29 ENA0 LVTTL Channel A0 Output Enable. LVTTL low input powers down A0 output stage.
30 DA1 CML Input Channel A1 Positive Signal Input.
31 DA1 CML Input Channel A1 Negative Signal Input.
32 ENA1 LVTTL Channel A1 Output Enable. LVTTL low input powers down A1 output stage.
− EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing)
must be attached to a heat−sinking conduit. The exposed pad must be soldered to the
circuit board GND for proper electrical and thermal operation.
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Table 3. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model > 2000 V
> 110 V
Moisture Sensitivity (Note 1) QFN−32 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 380
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Power Supply GND = 0 V 3.8 V
VIPositive Input GND = 0 V GND = VI = VCC 3.8 V
VINPP Differential Input Voltage |D − D| 3.8 V
IIN Input Current Through Internal 50 W Resistor Static
Surge 45
80 mA
mA
IOUT Output Current Continuous
Surge 25
80 mA
mA
TAOperating Temperature Range QFN−32 −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient)
(Note 2) 0 lfpm
500 lfpm QFN−32
QFN−32 31
27 °C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 3) QFN−32 12 °C/W
Tsol Wave Solder Pb−Free <3 sec @ 260 C 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
2. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 5. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS VCC = 3.0 V to 3.6 V, TA = −40°C to +85°C
Symbol Characteristic Min Typ Max Unit
ICC Power Supply Current (All outputs enabled) 130 170 mA
Voutdiff CML Differential Output Swing (Note 4, Figures 5 and 12) 640 800 1000 mV
VCMR
(Note 6) CML Output Common Mode Voltage (Loaded 50 W to VCC)VCC − 200 mV
CML Single−Ended Input Voltage Range VCC − 800 VCC + 400 mV
VID Differential Input Voltage (VIHD − VILD) 300 1600 mV
LVTTL CONTROL INPUT PINS
VIH Input HIGH Voltage (LVTTL Inputs) 2000 mV
VIL Input LOW Voltage (LVTTL Inputs) 800 mV
IIH Input HIGH Current (LVTTL Inputs) −10 10 mA
IIL Input LOW Current (LVTTL Inputs) −10 10 mA
RTIN CML Single−Ended Input Resistance 42.5 50 57.5 W
RTOUT Differential Output Resistance 85 100 115 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. CML outputs require 50 W receiver termination resistors to VCC for proper operation (Figure 10).
5. Input and output parameters vary 1:1 with VCC.
6. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC.
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, VEE = 0 V (Note 7, Figure 9)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
VOUTPP Output Voltage Amplitude (@ VINPPmin)f
in ≤ 2 GHz
(See Figure 3) fin ≤ 3 GHz
fin ≤ 3.5 GHz
280
235
170
365
310
220
280
235
170
365
310
220
280
235
170
365
310
220
mV
fDATA Maximum Operating Data Rate 3.2 3.2 3.2 Gb/s
tPLH,
tPHL Propagation Delay to Output Differential D/D to Q/Q 140 225 340 140 225 340 140 225 340 ps
tSKEW Duty Cycle Skew (Note 8)
Within−Device Skew (Figure 4)
Device−to−Device Skew (Note 12)
5
5
20
25
25
85
5
5
20
25
25
85
5
5
20
25
25
85
ps
tJITTER RMS Random Clock Jitter (Note 10) fin v 3.2 GHz
Peak−to−Peak Data Dependent Jitter fin = 2.5 Gb/s
(Note 11) fin = 3.2 Gb/s
0.15
7
7
0.5
20
20
0.15
7
7
0.5
20
20
0.15
7
7
0.5
20
20
ps
Crosstalk−Induced RMS Jitter (Note 13) 0.5 0.5 0.5 ps
VINPP Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 9) 150 800 150 800 150 800 mV
tr
tfOutput Rise/Fall Times @ 0.5 GHz Q, Q
(20% − 80%) 80 135 80 135 80 135 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Measured b y forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
9. VINPP (MAX) cannot exceed 800 mV. Input voltage swing is a single−ended measurement operating in differential mode.
10.Additive RMS jitter using 50% duty cycle clock input signal.
11.Additive peak−to−peak data dependent jitter using input data pattern with PRBS 223−1 and K28.5, VINPP = 400 mV.
12.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13.Data taken on the same device under identical condition.
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Figure 3. Output Voltage Amplitude (VOUTPP)
vs. Input Clock Frequency (fIN) at Ambient
Temperature (Typ)
0
50
100
150
200
250
300
350
400
450
0.05 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT CLOCK FREQUENCY (GHz)
OUTPUT VOLTAGE AMPLITUDE (mV)
Figure 4. Within−Device Skew vs. Temperature
at VCC = 3.3 V
0
2
4
6
8
10
12
14
16
18
20
−40 25 85
TEMPERATURE (°C)
TIME (ps)
Channel B
Channel A
Figure 5. CML Differential Voltage vs.
Temperature
0
100
200
300
400
500
600
700
800
900
−40 25 85
TEMPERATURE (°C)
VOLTAGE (mV)
Figure 6. Supply Current vs. Temperature
(All 4 Outputs Enabled)
110
120
130
140
150
160
170
−40 25 85
TEMPERATURE (°C)
CURRENT (mA)
Figure 7. Typical Output Waveform at 2.488 Gb/s
with PRBS 223−1 (Input Signal DDJ = 12 ps) Figure 8. Typical Output Waveform at 3.2 Gb/s
with K28.5 (Input Signal DDJ = 14 ps)
TIME (80.4 ps/div)
VOLTAGE (50 mV/div)
TIME (62.5 ps/div)
VOLTAGE (50 mV/div)
DDJ = 4 ps DDJ = 3 ps
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Figure 9. AC Reference Measurement
Dx
Dx
Qx
Qx
tPHL
tPLH
VINPP = VIH(DX) − VIL(DX)
VOUTPP = VOH(QX) − VOL(QX)
Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8173/D)
Driver
Device Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VCC
QX
QX
VCC
16 mA
50 W50 W
Figure 11. CML Input and Output Structure
GND
VCC
50 W
GND GND
DX
DX
50 W
Input Output
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(QX − QX)
640 mV
MIN
320 mV
MIN
500 mV
MAX
1000 mV
MAX
QX
QX
Figure 12. CML Output Levels
QX
QX
(QX − QX)
ORDERING INFORMATION
Device Package Shipping
NB4N840MMNG QFN32
(Pb−Free) 74 Units / Rail
NB4N840MMNR4G QFN32
(Pb−Free) 1000 / Tape & Reel
NB4N840MMNTWG QFN32
(Pb−Free) 1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM
ISSUE A
SEATING
NOTE 4
K
0.15 C
(A3)
A
A1
D2
b
1
9
17
32
E2
32X
8
L
32X
BOTTOM VIEW
TOP VIEW
SIDE VIEW
DA
B
E
0.15 C
ÉÉ
PIN ONE
LOCATION
0.10 C
0.08 C
C
25
e
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PLANE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
3.35
0.30
3.35
32X
0.63
32X
5.30
5.30
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ÉÉ
ÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTION
DETAIL B
DET AIL A
DIM
AMIN
MILLIMETERS
0.80
A1 −−−
A3 0.20 REF
b0.18
D5.00 BSC
D2 2.95
E5.00 BSC
2.95
E2
e0.50 BSC
0.30
L
K0.20
1.00
0.05
0.30
3.25
3.25
0.50
−−−
MAX
−−−
L1 0.15
e/2 NOTE 3
PITCH DIMENSION: MILLIMETERS
RECOMMENDED
A
M
0.10 BC
M
0.05 C
P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NB4N840M/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loc
al
Sales Representative
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