REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7302
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
2.7 V to 5.5 V, Parallel Input
Dual Voltage Output 8-Bit DAC
FUNCTIONAL BLOCK DIAGRAM
POWER ON
RESET
CS
WR
D0
REFIN V
DD
AD7302
V
OUT
A
DGND
D7
AGND
A/B
CLR LDAC
PD
I/V
V
OUT
B
MUX
÷2
INPUT
REGISTER DAC
REGISTER I DAC A
DAC
REGISTER I DAC B I/V
INPUT
REGISTER
CONTROL
LOGIC
FEATURES
Two 8-Bit DACs In One Package
20-Lead DIP/SOIC/TSSOP Package
+2.7 V to +5.5 V Operation
Internal and External Reference Capability
DAC Power-Down Function
Parallel Interface
On-Chip Output Buffer
Rail-to-Rail Operation
Low Power Operation 3 mA max @ 3.3 V
Power-Down to 1 mA max @ 258C
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD7302 is a dual, 8-bit voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision
output buffers allow the DAC outputs to swing rail to rail. The
AD7302 has a parallel microprocessor and DSP-compatible
interface with high speed registers and double buffered interface
logic. Data is loaded to the registers on the rising edge of CS or
WR and the A/B pin selects either DAC A or DAC B.
Reference selection for AD7302 can be either an internal
reference derived from the V
DD
or an external reference applied
at the REFIN pin. Both DACs can be simultaneously updated
using the asynchronous LDAC input and can be cleared by
using the asynchronous CLR input.
The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consump-
tion is less than 10 mW at 3.3 V, reducing to 3 µW in power-
down mode.
The AD7302 is available in a 20-pin plastic dual-in-line package,
20-lead SOIC and a 20-lead TSSOP package.
PRODUCT HIGHLIGHTS
1.␣ Low Power, Single Supply Operation. This part operates
from a single +2.7 V to +5.5 V supply and typically consumes
15 mW at 5 V, making it ideal for battery powered applications.
2.␣ The on-chip output buffer amplifiers allow the outputs of the
DACs to swing rail to rail with a settling time of typically 1.2 µs.
3.␣ Internal or external reference capability.
4.␣ High speed parallel interface.
5. Power-Down Capability. When powered down the DAC
consumes less than 1 µA at 25°C.
6. Packaged in 20-lead DIP, SOIC and TSSOP packages.
–2– REV. 0
AD7302–SPECIFICATIONS
(VDD = +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 kV to VDD and GND;
to TMAX unless otherwise noted)
Parameter B Versions
1
Units Conditions/Comments
STATIC PERFORMANCE
Resolution 8 Bits
Relative Accuracy ±1 LSB max Note 2
Differential Nonlinearity ±1 LSB max Guaranteed Monotonic
Full-Scale Error –0.75 LSB typ
Zero Code Error @ 25°C 3 LSB typ All Zeroes Loaded to DAC Register
Gain Error
3
±1 % FSR typ
Zero Code Temperature Coefficient 100 µV/°C typ
DAC REFERENCE INPUT
REFIN Input Range 1.0 to V
DD
/2 V min to max
REFIN Input Impedance 10 MΩ typ
OUTPUT CHARACTERISTICS
Output Voltage Range 0 to V
DD
V min to max
Output Voltage Settling Time 2 µs max Typically 1.2 µs
Slew Rate 7.5 V/µs typ
Digital to Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around Major Carry
Digital Feedthrough 0.2 nV-s typ
Digital Crosstalk 0.2 nV-s typ
Analog Crosstalk ±0.2 LSB typ
DC Output Impedance 40 Ω typ
Short Circuit Current 14 mA typ
Power Supply Rejection Ratio
4
0.0003 %/% max ∆V
DD
= ±10%
LOGIC INPUTS
Input Current ±10 µA max
V
INL
, Input Low Voltage 0.8 V max V
DD
= +5 V
V
INL
, Input Low Voltage 0.6 V max V
DD
= +3␣ V
V
INH
, Input High Voltage 2.4 V min V
DD
= +5 V
V
INH
, Input High Voltage 2.1 V min V
DD
= +3 V
Pin Capacitance 7 pF max
POWER REQUIREMENTS
V
DD
2.7/5.5 V min/max
I
DD
Both DACs Active and Excluding Load Currents
V
DD
= 3.3 V V
IH
= V
DD
and V
IL
= GND
@ 25°C 2.8 mA max Typically 2.3 mA
@ T
MIN
to T
MAX
3 mA max See Figures 6 and 7
V
DD
= 5.5 V V
IH
= V
DD
and V
IL
= GND
@ 25°C 4.5 mA max Typically 2.8 mA
@ T
MIN
to T
MAX
5 mA max See Figures 6 and 7
I
DD
(Full Power-Down)
@ 25°C1µA max V
IH
= V
DD
and V
IL
= GND
T
MIN
to T
MAX
2µA max See Figure 18
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +105°C.
2
Relative Accuracy is calculated using a reduced code range of 15 to 245.
3
Gain error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.
4
Guaranteed by characterization at product release, not production tested.
Specifications subject to change without notice.
AD7302
–3–
REV. 0
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter (B Version) Units Conditions/Comments
t
1
0 ns min Address to Write Setup Time
t
2
0 ns min Address Valid to Write Hold Time
t
3
0 ns min Chip Select to Write Setup Time
t
4
0 ns min Chip Select to Write Hold Time
t
5
20 ns min Write Pulse Width
t
6
15 ns min Data Setup Time
t
7
4.5 ns min Data Hold Time
t
8
20 ns min Write to LDAC Setup Time
t
9
20 ns min LDAC Pulse Width
t
10
20 ns min CLR Pulse Width
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of
(V
IL
+ V
IH
)/2. tr and tf should not exceed 1 µs on any digital input.
2
See Figure 1.
A/B
CS
WR
D7–D0
LDAC
CLR
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
t
10
t
9
Figure 1. Timing Diagram for Parallel Data Write
(VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD/2 Reference;
all specifications TMIN to TMAX unless otherwise noted)
AD7302
–4– REV. 0
ORDERING GUIDE
Temperature Package
Model Range Options*
AD7302BN –40°C to +105°C N-20
AD7302BR –40°C to +105°C R-20
AD7302BRU –40°C to +105°C RU-20
*N = Plastic DIP; R = Small Outline; RU =Thin Shrink Small Outline.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Reference Input Voltage to AGND . . . .–0.3 V to V
DD
+ 0.3␣ V
Digital Input Voltage to DGND . . . . . –0.3 V to V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 0.3 V
V
OUT
A, V
OUT
B to AGND . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 900 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 102°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . .+260°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 700 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature, Soldering
␣ ␣ Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
␣ ␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering
␣ ␣ Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
␣ ␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7302 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD7302
–5–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1-8 D7–D0 Parallel Data Inputs. Eight-bit data is loaded to the input register of the AD7302 under the control of CS
and WR.
9CS Chip Select. Active low logic input.
10 WR Write Input. WR is an active low logic input used in conjunction with CS and A/B to write data to the selected
DAC register.
11 A/B DAC Select. Address pin used to select writing to either DAC A or DAC B.
12 PD Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.
13 LDAC Load DAC Logic Input. When this logic input is taken low both DAC outputs are simultaneously updated with
the contents of their DAC registers. If LDAC is permanently tied low, the DACs are updated on the rising
edge of WR.
14 CLR Asynchronous Clear Input (Active Low). When this input is taken low the DAC registers are loaded with all
zeroes and the DAC outputs are cleared to zero volts.
15 V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and should be decoupled to AGND.
16 REFIN External Reference Input. This can used as the reference for both DACs. The range on this reference input is
1 V to V
DD
/2. If REFIN is directly tied to V
DD
the internal V
DD
/2 reference is selected.
17 AGND Analog Ground reference point and return point for all analog current on the part.
18 V
OUT
B Analog output voltage from DAC B. The output amplifier can swing rail to rail on its output.
19 V
OUT
A Analog output voltage from DAC A. The output amplifier can swing rail to rail on its output.
20 DGND Digital Ground reference point and return point for all digital current on the part.
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7302
(MSB) DB7
AGND
VOUTB
VOUTA
DGND
DB6
DB5
DB4
CLR
VDD
REFIN
DB3
DB2
DB1
(LSB) DB0
CS
WR A/B
PD
LDAC
AD7302
–6– REV. 0
TERMINOLOGY
INTEGRAL NONLINEARITY
For the DACs, relative accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A graphical representation of the transfer curve is shown in
Figure 14.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity.
ZERO CODE ERROR
Zero Code Error is the measured output voltage from V
OUT
of
either DAC when zero code (all zeros) is loaded to the DAC
latch. It is due to a combination of the offset errors in the DAC
and output amplifier. Zero scale error is expressed in LSBs.
GAIN ERROR
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from ideal, expressed
as a percent of the full-scale value. It includes full-scale errors
but not offset errors.
DIGITAL-TO-ANALOG GLITCH IMPULSE
Digital-to-Analog Glitch Impulse is the impulse injected into the
analog output when the digital inputs change state with the
DAC selected and the LDAC used to update the DAC. It is
normally specified as the area of the glitch in nV-s and is
measured when the digital input code is changed by 1 LSB at
the major carry transition.
DIGITAL FEEDTHROUGH
Digital Feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital inputs of the same
DAC, but is measured when the DAC is not updated. It is
specified in nV-s and measured with a full-scale code change on
the data bus, i.e., from all 0s to all 1s and vice versa.
DIGITAL CROSSTALK
Digital Crosstalk is the glitch impulse transferred to the output
of one converter due to a digital code change to another DAC.
It is specified in nV-s.
ANALOG CROSSTALK
Analog Crosstalk is a change in output of any DAC in response
to a change in the output of the other DAC. It is measured in
LSBs.
POWER SUPPLY REJECTION RATIO (PSRR)
This specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power supply
rejection ratio is quoted in terms of % change in output per %
change in V
DD
for full-scale output of the DAC. V
DD
is varied
±10%.
Typical Performance Characteristics–
AD7302
SINK CURRENT – mA
VOUT – mV
800
00824 6
720
400
240
160
80
640
560
320
480
VDD = 5V AND 3V
INTERNAL REFERENCE
TA = +25 C
DAC LOADED WITH 00HEX
␣ Figure 2. Output Sink Current Capa-
␣ bility with V
DD
= 3 V and V
DD
= 5 V
REFERENCE VOLTAGE – Volts
ERROR – LSBs
0.5
01.0 1.2 2.8
1.4 1.6 1.8 2.2 2.4 2.62.0
0.45
0.25
0.15
0.1
0.05
0.4
0.35
0.2
0.3
V
DD
= 5V
T
A
= +258C
INL ERROR
DNL ERROR
␣␣␣␣Figure 5. Relative Accuracy vs.
␣␣␣␣External Reference
FREQUENCY – Hz
ATTENUATION – dB
1 10 10k100 1k
10
5
–40
0
–5
–10
–15
–20
–25
–30
–35
VDD = 5V
EXTERNAL SINEWAVE REFERENCE
DAC REGISTER LOADED WITH FFHEX
TA = +25°C
␣␣␣␣␣␣Figure 8. Large Scale Signal
␣␣␣␣␣␣Frequency Response
SOURCE CURRENT – mA
VOUT – Volts
02 846
5
4.92
4.2
4.84
4.76
4.68
4.6
4.52
4.44
4.36
4.28
VDD = 5V
INTERNAL REFERENCE
DAC REGISTER LOADED
WITH FFHEX
TA = +25°C
Figure 3. Output Source Current
Capability with V
DD
= 5 V
–50 –25 100
TEMPERATURE – C
5.0
3.5
2.0
IDD – mA
4.5
4.0
3.0
2.5
INTERNAL REFERENCE
LOGIC INPUTS = VDD OR GND
BOTH DACS ACTIVE
VDD = 5.5V
VDD = 3.3V
1.5
1.0
0.5
00 255075 125
Figure 6. Typical Supply Current
vs. Temperature
T
←
VOUT
VDD = 3V
INTERNAL VOLTAGE
REFERENCE
FULL SCALE CODE
CHANGE 00H-FFH
TA = +25°C
1
←
3
←
2
←
VOUT
CH1 5V, CH2 1V, CH3 20mV
TIME BASE = 200 ns/Div
WR
Figure 9. Full-Scale Settling Time
SOURCE CURRENT – mA
3.5
1.0 01 8234567
3.25
2.5
2.25
1.75
1.25
3.0
2.75
2.0
1.5
VOUT – Volts
VDD = 3V
INTERNAL REFERENCE
DAC REGISTER LOADED
WITH FFHex
TA = +25°C
Figure 4. Output Source Current
Capability with V
DD
= 3 V
VDD – Volts
IDD – mA
5.0
3.0
1.0
4.0
2.5 3.0 5.53.5 4.0 4.5 5.0
LOGIC INPUTS = VDD OR GND
LOGIC INPUTS = VIH OR VIL
BOTH DACS ACTIVE
INTERNAL REFERENCE USED
TA = +25°C
2.0
6.0
7.0
Figure 7. Typical Supply Current
vs. Supply Voltage
PD
VOUT
AD7302 POWER-UP TIME
VDD = 5V
INTERNAL REFERENCE
DAC IN POWER-DOWN INITIALLY
1
2
CH1 = 2V/div, CH2 = 5V/Div,
TIME BASE = 2 µs/Div
␣ Figure 10. Exiting Power-Down (Full
␣ Power-Down)
–7–
REV. 0
AD7302
–8– REV. 0
1
2
VOB
M20.0ms
VOA
VDD
3
CH1
CH3 5.00V
5.00V CH2 5.00V CH1
T
T
T
Figure 11. Power-On—RESET
INPUT CODE (10 to 245)
INL ERROR – LSB
0256
32 64 96 128 160 192 224
DAC B
DAC A
VDD = 5V
INTERNAL REFERENCE
5kΩ 100pf. LOAD
LIMITED CODE RANGE (10–245)
TA = +25°C
–0.5
0.4
0.1
–0.1
–0.3
–0.4
0.3
0.2
0
–0.2
0.5
Figure 14. Integral Linearity Plot
–25
4
0
7
6
2
1
5
3
8
9
10
–50 0 25 50 75 100 125
TEMPERATURE – C
DAC A
DAC B
ZERO CODE ERROR – LSB
VDD = 2.7 TO 5.5V
DAC LOADED WITH ALL ZEROES
INTERNAL REFERENCE
Figure 12. Zero Code Error vs.
Temperature
VDD = 5V
INTERNAL REFERENCE
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–60 –40 –20 0 20 40 60 80 100 120 140
INL ERROR – LSB
TEMPERATURE – 8C
Figure 15. Typical INL vs. Temperature
2
←
1
←
WR
V
OUT
V
DD
= 5V
INTERNAL VOLTAGE
REFERENCE
10 LSB STEP CHANGE
T
A
= +258C
CH1 5.00V, CH2 50.0mV, M 250ns
Figure 13. Small-Scale Settling Time
VDD = 5V
INTERNAL REFERENCE
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
DNL ERROR – LSB
Figure 16. Typical DNL vs. Temperature
VDD = 5V
0.6
0.4
0.2
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
INT REFERENCE ERROR – 6%
0.8
1.0
Figure 17. Typical Internal Reference
Error vs. Temperature
TEMPERATURE – C
0
–50 –25 0 100 125
VDD = 5V
LOGIC INPUTS = VDD OR GND
100
200
300
400
500
600
700
800
900
1000
25 50 75
POWER-DOWN CURRENT – nA
Figure 18. Power-Down Current vs.
Temperature
AD7302
–9–
REV. 0
GENERAL DESCRIPTION
D/A Section
The AD7302 is a dual 8-bit voltage output digital-to-analog
converter. The architecture consists of a reference amplifier, a
current source DAC followed by a current-to-voltage converter
capable of generating rail-to-rail voltages on the output of the
DAC. Figure 19 shows a block diagram of the basic DAC
architecture.
REFERENCE
AMPLIFIER
+
-VO A/B
VDD
REFIN
AD7302
CURRENT
DAC I/V
30kΩ
30kΩ
11.7kΩ
11.7kΩ
Figure 19. DAC Architecture
Both DAC A and DAC B outputs are internally buffered and
these output buffer amplifiers have rail-to-rail output character-
istics. The output amplifier is capable driving a load of 10 kΩ to
both V
DD
and ground in parallel with a 100 pF to ground. The
reference selection for the DAC can either be internally generated
from V
DD
or externally applied through the REFIN pin. A
comparator on the REFIN pin detects whether the required
reference is the internally generated reference or the externally
applied voltage to the REFIN pin. If REFIN is connected to
V
DD
, the reference selected is the internally generated V
DD
/2
reference. When an externally applied voltage is more than one
volt below V
DD
, the comparator selection switches to the
externally applied voltage to the REFIN pin. The range on the
external reference input is from 1.0 V to V
DD
/2. The output
voltage from either DAC is given by:
V
O
A/B = 2 × V
REF
× (N/256)
where:
V
REF
is the voltage applied to the external REFIN pin or
V
DD
/2 when the internal reference is selected.
␣␣ N is the decimal equivalent of the code loaded to the DAC
register and ranges from 0 to 255.
Reference
The AD7302 has the facility to use either an external reference
applied through the REFIN pin or an internal reference
generated from V
DD
. Figure 20 shows the reference input
arrangement where either the internal V
DD
/2 reference or the
externally applied reference can be selected.
COMPARATOR
VTH
PMOS
MUX
INT
REF
SELECTED
REFERENCE OUTPUT
VDD
REFIN
INT REF
EXT REF
Figure 20. Reference Selection Circuitry
The internal reference is selected by tying the REFIN pin to
V
DD
. If an external reference is to be used, this can be directly
applied to the REFIN pin; if this is 1 V below V
DD
, the internal
circuitry will select this externally applied reference as the
reference source for the DAC.
Digital Interface
The AD7302 contains a fast parallel interface allowing this dual
DAC to interface to industry standard microprocessors, micro-
controllers and DSP machines. There are two modes in which
this parallel interface can be configured to update the DAC
outputs. The simultaneous update mode allows simultaneous
updating of both DAC outputs. The automatic update mode
allows each DAC to be individually updated following a write
cycle. Figure 21 shows the internal logic associated with the
digital interface. The PON STRB signal is internally generated
from the power on reset circuitry and is low during the power-
on reset phase of the power-up procedure.
CLR
PON STRB
LDAC
A/B
CS
WR
CLEAR
LDAC
DAC A SEL
DAC A
CONTROL
LOGIC
ENABLE
SET SLE MLE A
SLE A
CLR
CLEAR
LDAC
DAC B SEL
DAC B
CONTROL
LOGIC
ENABLE
SET SLE MLE B
SLE B
Figure 21. Logic Interface
The AD7302 has a double buffered interface, which allows
for simultaneous updating of the DAC outputs. Figure 22 shows
a block diagram of the register arrangement within the AD7302.
DB7–DB0
INPUT
REGISTER
LOWER
NIBBLE
4 TO 15
DECODER
DAC
REGISTER
DRIVERS
4
15
15
30
8
UPPER
NIBBLE
4 TO 15
DECODER
DAC
REGISTER
DRIVERS
4
15
15
30
CONTROL
LOGIC
SLEMLE
A/B
CS
WR
LDAC
CLR
Figure 22. Register Arrangement
AD7302
–10– REV. 0
Automatic Update Mode
In this mode of operation the LDAC signal is permanently tied
low. The state of the LDAC is sampled on the rising edge of
WR. LDAC being low allows the selected DAC register to be
automatically updated on the rising edge of WR. The output
update occurs on the rising edge of WR. Figure 23 shows the
timing associated with the automatic update mode of operation
and also the status of the various registers during this frame.
A/B
CS
WR
D7–D0
LDAC = 0
HOLD HOLDTRACK
I/P REG (MLE)
TRACKHOLD
DAC REG (SLE) TRACK
VOUT
Figure 23. Timing and Register Arrangement for Auto-
matic Update Mode
Simultaneous Update Mode
In this mode of operation the LDAC signal is used to update both
DAC outputs simultaneously. The state of the LDAC is sampled
on the rising edge of WR. If LDAC is high, the automatic update
mode is disabled and both DAC latches are updated at any time
after the write by taking LDAC low. The output update occurs
on the falling edge of LDAC. LDAC must be taken back high
again before the next data transfer takes place. Figure 24
shows the timing associated with the simultaneous update mode
of operation and also the status of the various registers during
this frame.
A/B
CS
WR
D7–D0
LDAC
HOLD HOLDTRACK
I/P REG (MLE)
TRACKHOLD
DAC REG (SLE)
VOUT
HOLD
Figure 24. Timing and Register Arrangement for Simulta-
neous Update Mode
POWER-ON RESET
The AD7302 has a power-on reset circuit designed to allow
output stability during power-up. This circuit holds the DACs
in a reset state until a write takes place to the DAC. In the reset
state all zeros are latched into the input registers of each DAC
and the DAC registers are in transparent mode, thus the output
of both DACs is held at ground potential until a write takes
place to the DAC. The power-on reset circuitry generates a
PON STRB signal, which is a gating signal used within the logic
to identify a power-on condition.
POWER-DOWN FEATURES
The AD7302 has a power-down feature. This is implemented
by exercising the external PD pin; an active low signal puts the
complete DAC into power-down mode. When in power-down
the current consumption of the device is reduced to 1 µA max at
25°C and 2 µA max over temperature, making the device
suitable for use in portable battery powered equipment. When
power-down is activated, the reference bias servo loop and the
output amplifiers with their associated linear circuitry are
powered down, the reference resistors are open circuited to
further reduce the power consumption. The output sees a load
of approximately 23 kΩ to GND when in power-down mode as
shown in Figure 25. The contents of the data registers are
unaffected when in power-down mode. The device comes out
of power-down in typically 13 µs (see Figure 10).
IDAC
11.7kΩ
11.7kΩ
VREF
VDD
Figure 25. Output Stage During Power-Down
Analog Outputs
The AD7302 contains two independent voltage output DACs
with 8-bit resolution and rail-to-rail operation. The output buffer
provides a gain of two at the output. Figures 2 to 4 show the
source and sink capabilities of the output amplifier. The slew
rate of the output amplifier is typically 7.5 V/µs and has a full-
scale settling to 8 bits with a 100 pF capacitive load in typically
1.2 µs.
The input coding to the DAC is straight binary. Table I shows
the binary transfer function for the AD7302. Figure 26 shows
the DAC transfer function for binary coding. Any DAC output
voltage can be expressed as:
V
OUT
= 2 × V
REF
(N/256)
where:
␣␣N is the decimal equivalent of the binary input code.
N ranges from 0 to 255.
AD7302
–11–
REV. 0
␣␣V
REF
is the voltage applied to the external REFIN pin when
the external reference is selected and is V
DD
/2 if the
internal reference is used.
Table I. Output Voltage for Selected Input Codes
Digital Input
MSB . . . LSB Analog Output
1111 1111 2 × 255/256 × V
REF
V
1111 1110 2 × 254/256 × V
REF
V
1000 0001 2 × 129/256 × V
REF
V
1000 0000 V
REF
V
0111 1111 2 × 127/256 × V
REF
V
0000 0001 2 × V
REF
/256␣ V
0000 0000 0 V
00 01
DAC INPUT
CODE FF80 81 FE7F
0
2.V
REF
V
REF
DAC OUTPUT VOLTAGE
Figure 26. DAC Transfer Function
Figure 27 shows a typical setup for the AD7302 when using its
internal reference. The internal reference is selected by tying the
REFIN pin to V
DD
. Internally in the reference section there is a
reference detect circuit that will select the internal V
DD
/2 based
on the voltage connected to the REFIN pin. If REFIN is within
a threshold voltage of a PMOS device (approximately 1 V) of
V
DD
the internal reference is selected. When the REFIN voltage
is more than 1 V below V
DD
, the externally applied voltage at
this pin is used as the reference for the DAC. The internal
reference on the AD7302 is V
DD
/2, the output current to voltage
converter within the AD7302 provides a gain of two. Thus the
output range of the DAC is from 0 V to V
DD
, based on Table I.
AD7302
VOUTA
VOUTB
10µF
0.1µF
VDD = 3 TO 5V
VDD
A/B
REF IN
CLR
PD
VDD
AGND DGND
CS WR LDAC
D7–D0
VOUTA
VOUTB
DATA BUS CONTROL INPUTS
Figure 27. Typical Configuration Selecting the Internal
Reference
Figure 28 shows a typical setup for the AD7302 when using an
external reference. The reference range for the AD7302 is from
1 V to V
DD
/2 V. Higher values of reference can be incorporated,
but will saturate the output at both the top and bottom end of
the transfer function. There is a gain of two from input to output
on the AD7302. Suitable references for 5 V operation are the
AD780 and REF192. For 3 V operation a suitable external
reference would be the AD589 a 1.23 V bandgap reference.
AD7302
VOUTA
VOUTB
10µF
0.1µF
VDD = 3 TO 5V
VDD
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
REF IN
GND
VOUT
VIN
0.1µF
EXT REF
VDD
AGND DGND
D7–D0
VOUTA
VOUTB
DATA BUS CONTROL INPUTS
A/B
CLR
PD
CS WR LDAC
Figure 28. Typical Configuration Using An External
Reference
AD7302
–12– REV. 0
MICROPROCESSOR INTERFACING
AD7302–ADSP-2101/ADSP-2103 Interface
Figure 29 shows an interface between the AD7302 and the
ADSP-2101/ADSP-2103. The fast interface timing associated
with the AD7302 allows easy interface to the ADSP-2101/
ADSP-2103.
ADDR
DECODE
DATA BUS
ADDRESS BUS
CS
DB0
DB7
AD7302*
A/B
DMA0
DMA14
WR
EN
DMD0
DMD15
ADSP-2101*/
ADSP-2103*
WR
DMS
A**
A+1**
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
LDAC
Figure 29. AD7302–ADSP-2101/ADSP-2103 Interface
Two addresses are decoded to select loading data to either
DAC A or DAC B. LDAC is permanently tied low in this
circuit, so the selected DAC output is updated on the rising
edge of the WR signal.
Data is loaded to the AD7302 input register using the following
ADSP-21xx instruction:
DM (DAC) = MR0
MR0 = ADSP-21xx MR0 Register.
DAC = Decoded DAC Address.
AD7302–TMS32020 Interface
Figure 30 shows an interface between the AD7302 and the
TMS32020. The address decoder is used to decode the
addresses for DAC A and DAC B. Data is loaded to the
AD7302 using the following instruction:
OUT DAC, D
DAC = Decoded DAC Address.
D = Data Memory Address.
ADDR
DECODE
DATA BUS
ADDRESS BUS
CS
DB0
DB7
AD7302*
A/B
A0
A15
STRB
EN
DMD0
DMD15
TMS32020
WR
IS
A**
A+1**
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
LDAC
R/W
Figure 30. AD7302–TMS32020 Interface
In the circuit shown the LDAC is hardwired low, thus the
selected DAC output is updated on the rising edge of WR.
Some applications may require simultaneous updating of both
DACs in the AD7302. In this case the LDAC signal can be
driven from an external timer or can be controlled by the
microprocessor. One option for simultaneous updating is to
decode the LDAC from the address bus so that a write opera-
tion at this address will simultaneously update both DAC
outputs. A simple OR gate with one input driven from the
decoded address and the second input from the WR signal will
implement this function.
AD7302–8051/8088 Interface
Figure 31 shows a serial interface between the AD7302 and the
8051/8088 processors. The address decoder is used to decode
the addresses for DAC A and DAC B.
ADDR
DECODE
ADDRESS/DATA BUS
ADDRESS BUS
DB0
DB7
AD7302*
/B
A8
A15
AD0
AD7
8051/8088
OR
A**
A+1**
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
ALE OCTAL
LATCH
Figure 31. AD7302–8051//8088 Interface
AD7302
–13–
REV. 0
APPLICATIONS
Bipolar Operation Using the AD7302
The AD7302 has been designed for single supply operation,
but bipolar operation is achievable using the circuit shown in
Figure 32. The circuit shown has been configured to achieve an
output voltage range of –5 V < V
O
< +5 V. Rail-to-rail operation
at the amplifier output is achievable using an AD820 or OP295
as the output amplifier.
The output voltage for any input code can be calculated as
follows:
V
O
= [(1+R4/R3)
×
(R2/(R1+R2)
×
(2
×
V
REF
×
D/256)] – R4
×
V
REF
/R3
where
␣␣D is the decimal equivalent of the code loaded to the DAC
and
␣␣V
REF
is the reference voltage input.
With V
REF
= 2.5 V, R1 = R3 = 10␣ kΩ and R2 = R4 = 20 kΩ and
V
DD
= 5␣ V.
V
OUT
= (10 × D/256) – 5 V
AD7302 VOUTA
10µF
0.1µF
VDD = 5V
VDD
AGND
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
REF IN
GND
VOUT
VIN
0.1µF
EXT REF
R1
10kΩ
R2
20kΩ
R4
20kΩ
R3
10kΩ+5V
–5V
±5V
DGND
AD820/
OP295
Figure 32. Bipolar Operation Using the AD7302
Decoding Multiple AD7302 in a System
The CS pin on the AD7302 can be used in applications to
decode a number of DACs. In this application all DACs in the
system receive the same input data, but only the CS to one of
the DACs will be active at any one time allowing access to two
channels in the system. The 74HC139 is used as a two-to-four
line decoder to address any of the DACs in the system. To
prevent timing errors from occurring, the enable input should
be brought to its inactive state while the coded address inputs are
changing state. Figure 33 shows a diagram of a typical setup for
decoding multiple AD7302 devices in a system. The built-in
power-on reset circuit on the AD7302 ensures that the outputs
of all DACs in the system power up with zero volts on their
outputs.
Figure 33. Decoding Multiple AD7302 DACs in a System
AD7302 As a Digitally Programmable Window Detector
A digitally programmable upper/lower limit detector using the
two DACs in the AD7302 is shown in Figure 34. The upper
and lower limits for the test are loaded to DACs A and B, which
in turn set the limits on the CMP04. If a signal at the V
IN
input
is not within the programmed window an LED will indicate the
fail condition.
AD7302
VDD
+5V
VOUTA
DGND
REFIN
VIN
PASS/FAIL
1/2 CMP04
1/6 74HC05
FAIL PASS
1k
0.1µF 10µF
WR
CS
A/B
1k
VOUTB
LDAC
CLR
DVDD
PD
AGND
D0
D7
Figure 34. Programmable Window Detector
AD7302
–14– REV. 0
Programmable Current Source
Figure 35 shows the AD7302 used as the control element of a
programmable current source. In this circuit the full-scale
current is set to 1 mA. The output voltage from the DAC is
applied across the current setting resistor of 4.7 kΩ in series
with the full-scale setting resistor of 470 Ω. Transistors suitable
to place in the feedback loop of the amplifier include the BC107
or the 2N3904, which enable the current source to operate from
a min V
SOURCE
of 6 V. The operating range is determined by
the operating characteristics of the of the transistor. Suitable
amplifiers include the AD820 and the OP295 both having rail-
to-rail operation on their outputs. The current for any digital
input code can be calculated as follows:
I = 2 × V
REF
× D/(5E +3 × 256) mA
AD7302 VOUTA
10µF0.1µF
VDD = 5V
VDD
AGND
AD780/REF192
WITH VDD = 5V
REF IN
GND
VOUT
VIN
0.1µF
EXT REF
4.7kΩ
470Ω
+5V LOAD
VSOURCE
AD820/
OP295
DGND
Figure 35. Programmable Current Source
Coarse and Fine Adjustment Using the AD7302
The DACs on the AD7302 can be paired together to form a
coarse and fine adjustment function as shown in Figure 36. In
this circuit DAC A is used to provide the coarse function while
DAC B is used to provide the fine adjustment. Varying the ratio
of R1 and R2 will vary the relative effect of the coarse and fine
tune elements in the circuit. For the resistor values shown
DAC B has a resolution of 148 µV giving a fine tune range of
approximately 2 LSBs for operation with a V
DD
of 5 V and a
reference of 2.5 V. The amplifiers shown allow a rail-to-rail
output voltage to be achieved on the output. A typical applica-
tion for such a circuit would be in a setpoint controller.
AD7302
VOUTA
10µF
0.1µF
VDD = 5V
VDD
AGND
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
REF IN
GND
VOUT
VIN
0.1µF
EXT REF
R2
51.2kΩ
R4
390Ω
R1
390Ω
+5V
VOUT
DGND
AD820/
OP295
VOUTB
R3
51.2kΩ
Figure 36. Coarse/Fine Adjust Circuit
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7302 is mounted should be designed so the analog and
digital sections are separated and confined to certain areas of the
board. If the AD7302 is in a system where multiple devices
require an AGND to DGND connection, the connection should
be made at one point only, a star ground point that should be
established as closely as possible to the AD7302. The AD7302
should have ample supply bypassing of 10 µF in parallel with
0.1 µF on the supply located as close to the package as possible,
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. The 0.1 µF capacitor should have low
Effective Series Resistance (ESR) and Effective Series Induc-
tance (ESI), such as the common ceramic types, which provide
a low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
The power supply lines of the AD7302 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching sig-
nals like clocks should be shielded with digital ground to avoid
radiating noise to other parts of the board and should never be
run near the reference inputs. Avoid crossover of digital and
analog signals. Traces on opposite sides of the board should run
at right angles to each other. This reduces the effects of feed-
through through the board. A microstrip technique is by far the
best, but not always possible with a double-sided board. In this
technique, the component side of the board is dedicated to
ground plane while signal traces are placed on the solder side.
AD7302
–15–
REV. 0
20-Lead Plastic DIP
(N-20)
20
110
11
1.060 (26.90)
0.925 (23.50)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.210 (5.33)
MAX 0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
20-Lead SO
(R-20)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10) 0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC 0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25) x 45°
20 11
101
0.5118 (13.00)
0.4961 (12.60)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
20-Lead TSSOP
(RU-20)
20 11
10
1
0.260 (6.60)
0.252 (6.40)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
–16–
C2990–12–4/97
PRINTED IN U.S.A.