Datashee t AS5013 Low Power Integrated Hall IC for Human Interface Applications 1 General Description 2 Key Features 2.7V to 3.6V operating voltage The AS5013 is a complete Hall Sensor IC for smart navigation key applications to meet the low power requirements and host SW integration challenges for products such as cell phones and smart handheld devices. Down to 1.7V peripheral supply voltage Two operating modes: - Idle mode - Low power mode Due to the on chip processing engine, system designers are not tasked with integrating complex SW algorithms on their host processor thus leading to rapid development cycles. Less than 3A current consumption in Idle mode The AS5013 single-chip IC includes 5 integrated Hall sensing elements for detecting up to 2mm lateral displacement, high resolution ADC, XY coordinate and motion detection engine combined with a smart power management controller. Low power mode with selectable readout rate Two interrupt modes - Motion detect - Data ready The X and Y positions coordinates and magnetic field information for each Hall sensor element is transmitted over a 2-wire IC compliant interface to the host processor. Lateral magnet movement radius up to 2mm High-speed IC interface The AS5013 is available in a small 16-pin 4x4x0.55mm QFN package and specified over an operating temperature of -20C to +80C. 3 Applications The AS5013 is ideal for small form-factor manual input devices in battery operated equipment, such as Mobile phones, MP3 players, PDAs, GPS receivers and Gaming consoles. Figure 1. AS5013 Block Diagram VDD C2 C1 C5 C3 AS5013 ADC RESETn Processing Engine INTn C4 Hall Sensors Power Management ADDR VSS www.austriamicrosystems.com/AS5013 I C Interface Clock Generator Revision 1.11 SDA VDDp SCL 1 - 32 AS5013 Datasheet - C o n t e n t s Contents 1 General Description .................................................................................................................................................................. 1 2 Key Features............................................................................................................................................................................. 1 3 Applications............................................................................................................................................................................... 1 4 Pin Assignments ....................................................................................................................................................................... 3 4.1 Pin Descriptions.................................................................................................................................................................................... 3 5 Absolute Maximum Ratings ...................................................................................................................................................... 4 6 Electrical Characteristics........................................................................................................................................................... 5 6.1 Operating Conditions............................................................................................................................................................................ 5 6.2 Digital IO pads DC/AC Characteristics ................................................................................................................................................. 6 7 Detailed Description.................................................................................................................................................................. 7 7.1 Operating the AS5013 .......................................................................................................................................................................... 7 7.2 XY Coordinates Interpretation .............................................................................................................................................................. 8 7.3 Transfer Function.................................................................................................................................................................................. 8 7.4 Power Modes........................................................................................................................................................................................ 9 7.5 IC Interface........................................................................................................................................................................................ 10 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 Interface Operation .................................................................................................................................................................... 10 IC Electrical Specification ......................................................................................................................................................... 11 IC Timing .................................................................................................................................................................................. 11 IC Modes .................................................................................................................................................................................. 12 SDA, SCL Input Filters............................................................................................................................................................... 16 8 IC Registers........................................................................................................................................................................... 17 8.1 Control Register 1 (0Fh) ..................................................................................................................................................................... 17 8.2 X Register (10h) ................................................................................................................................................................................. 19 8.3 Y_res_int Register (11h)..................................................................................................................................................................... 19 8.4 Xp Register (12h) ............................................................................................................................................................................... 19 8.5 Xn Register (13h) ............................................................................................................................................................................... 19 8.6 Yp Register (14h)................................................................................................................................................................................ 20 8.7 Yn Register (15h) ............................................................................................................................................................................... 20 8.8 M_ctrl Register (2Bh).......................................................................................................................................................................... 20 8.9 J_ctrl Register (2Ch)........................................................................................................................................................................... 20 8.10 T_ctrl Register (2Dh) ........................................................................................................................................................................ 21 8.11 Control Register 2 (2Eh) ................................................................................................................................................................... 22 8.12 Hall Element Direct Read Registers (16h to 29h)............................................................................................................................. 22 8.13 Hall Element Direct Read Registers (2Ah) ....................................................................................................................................... 23 8.14 Power ON ......................................................................................................................................................................................... 23 8.15 Registers Initialization....................................................................................................................................................................... 24 8.16 Registers Table................................................................................................................................................................................. 24 9 Package Drawings and Markings ........................................................................................................................................... 27 9.1 Recommended Footprint .................................................................................................................................................................... 28 9.2 Recommended Mounting ................................................................................................................................................................... 28 10 Ordering Information............................................................................................................................................................. www.austriamicrosystems.com/AS5013 Revision 1.11 31 2 - 32 AS5013 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments Figure 2. Pin Assignments (Top View) PDIO OTP PCLK MODE OTP VSS 16 15 14 VDDp 13 SDA 1 12 VDD SCL 2 11 VDDp RESETn 3 Epad 10 ADDR INTn 4 9 TB0 TB1 7 8 TB3 6 TB2 5 TEST COIL 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Number Pin Name Pin Type ESD 1 SDA Digital I/O / Open drain 2kV IC Data line, open drain 2 SCL 2kV IC Clock line 3 RESETn 2kV General Reset input 0: Reset 1: Normal mode 4 INTn 2kV Interrupt line, open drain, active low 5 TB0 6 TB1 7 TB2 8 TB3 9 TEST COIL Special 2kV Test pin, leave unconnected or connect to VSS 10 ADDR Digital input with Schmitt trigger functionality 2kV IC address selection input. Read in at each reset 11 VDDp 2kV 1.7 ~ 3.6V IO power supply 12 VDD 2kV 2.7 ~ 3.6V Core power supply 13 VSS 2kV Power supply ground 14 MODE OTP 2kV 15 PCLK 16 PDIO OTP EPAD Exposure Pad www.austriamicrosystems.com/AS5013 Digital input Digital output open drain Description 2kV Analog I/O 2kV 2kV Test pin, leave unconnected 2kV Supply pad Digital I/O 2kV Test pin, leave unconnected 2kV - - Revision 1.11 Internally not connected. Leave open or connect to VSS 3 - 32 AS5013 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Operating Conditions on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Symbol Parameter Min Max Units DC supply voltage Comments -0.3 5 V -0.3 5 VDD +0.3 V -0.3 VDDp +0.3 V - 3.6 V -100 100 mA Norm: JEDEC 78 Electrical Parameters VDD VDDp Peripheral supply voltage Vin Input pin voltage Iscr Input current (latchup immunity) Electrostatic Discharge ESD Electrostatic discharge - 2 kV Norm: MIL 883 E method 3015, direct pad contact JA Package thermal resistance - 32 K/W Velocity=0, Multi Layer PCB; JEDEC Standard Testboard -55 125 C Temperature Ranges and Storage Conditions Tstrg Tbody Storage temperature Package body temperature Humidity non-condensing www.austriamicrosystems.com/AS5013 5 260 C 85 % Revision 1.11 The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020 "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". The lead finish for Pb-free leaded packages is matte tin (100% Sn). 4 - 32 AS5013 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics 6.1 Operating Conditions TAMB = -20C to +80C, VDD = 3.3V, RESETn = HIGH Table 3. Operating Conditions Symbol Parameter VDD Core supply voltage VDDp Peripheral supply voltage IDDs Maximal average current consumption on VDD, Pulsed peaks = IDDf depends on the sampling time ts[ms] TAMB = -20C to +50C 3+3760/ts [ms] TAMB = 50C to +80C 10+3760/ts [ms] IDDI Current consumption on core supply, Idle mode, no readout (ts = infinite) TAMB = -20C to +50C 3 TAMB = 50C to +80C 10 IDDf Current consumption on core supply, Idle mode, continuous readout (ts=450s) Continuous current pin VDD Maximum sampling ts = 450s 10 mA Tpua Power up time analog Step on VDD to Data_Ready 1000 s Tconv Conversion time Read X/Y coordinate IC Y_res_int ACK bit of to Data_Ready 450 s tP,W Nominal wakeup time 320 ms dx dy Lateral movement radius The range depends on the magnet and the distance to the surface, dx+dy <= 4mm 2 mm d Type of magnet Cylindrical; axial magnetized 3 mm RH Hall array diameter BZ Magnetic field strength TAMB Ambient temperature range PSSR Conditions Input: RESETn Open drain outputs: SCL, SDA, INTn. External I2C pull up resistor to be connected to VDDp. Min Typ Max Units 2.7 3.6 V 1.7 VDD V 20 2 A 2.2 Vertical magnetic field at magnet center; measured at chip surface A mm 30 120 mT -20 +80 C Resolution of XY displacement Over 2*dx and 2*dy axis Noise (RMS) C1..C5 channel data (result from two measurement - positive and negative current spinning) 100 T Power Supply Rejection Ratio VDD=3.3V; Temp = 25C dVDD= 100 mVpp at 10.30 kHz 0.2 %/ 100mV IC package Power supply filtering capacitors www.austriamicrosystems.com/AS5013 8 bit QFN16 4x4x0.55mm Ceramic capacitor VDD - VSS 100 nF Ceramic capacitor VDDp - VSS 100 nF Revision 1.11 5 - 32 AS5013 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.2 Digital IO pads DC/AC Characteristics Table 4. DC/AC Characteristics Symbol Parameter Conditions Min Max Units VIH High level input voltage IIC 0.7 * VDDp VIL Low level input voltage IIC 0.3 * VDDp V ILEAK Input leakage current VDDp = 3.6V 1 A Inputs: SCL, SDA V Inputs: ADDR, RESETn (JEDEC76) VIH High level input voltage JEDEC VIL Low level input voltage JEDEC 0.65 * VDDp 0.35 * VDDp V V ILEAK Input leakage current VDDp = 3.6V 1 A High level output voltage High level output voltage Outputs: SDA VOH Leakage current 1 A Open drain VOL1 -6mA; VDDP > 2V; fast mode VSS + 0.4 V VOL3 -6mA; VDDP 2V; fast mode VDDP*0.2 V VOL1 -3mA; VDDP > 2V; high speed VSS + 0.4 V VOL3 -3mA; VDDP 2V; high speed VDDP*0.2 V standard mode (100 kHz) 400 pF fast mode (400 kHz) 400 pF high speed mode (3.4 MHz) 100 pF Low level output voltage CL Capacitive load Outputs: INTn (JEDEC76) VOH VOL VOL CL High level output voltage Low level output voltage Capacitive load www.austriamicrosystems.com/AS5013 High level output voltage Leakage current 1A Open drain -100A VSS + 0.2 V -2mA VSS + 0.45 V standard mode (100 kHz) 30 pF Revision 1.11 6 - 32 AS5013 Datasheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description The benefits of the AS5013 device are as follows: Complete system-on-chip High reliability due to non-contact sensing Low power consumption Figure 3. Typical Arrangement of AS5013 and Axial Magnet 7.1 Operating the AS5013 Typical Application. The AS5013 requires only a few external components in order to operate immediately when connected to the host microcontroller. Only 4 wires are needed for a simple application using a single power supply: two wires for power and two wires for the IC communication. A fifth connection can be added in order to send an interrupt to the host CPU when the magnet is moving away from the center and to inform that a new valid coordinate can be read. Figure 4. Electrical Connection of AS5013 with Microcontroller DC 2.7 ~3.6V 100n C2 C1 VDD DC 1.7 ~3.6V VDDp AS5013 Supply : peripherals 100n C5 ADC C3 C4 Processing Engine INTn Hall Sensors Clock Generator Power Management VSS TestCoil www.austriamicrosystems.com/AS5013 SDA Revision 1.11 C RESETn IC Interface ADDR Interrupt SCL SCL SDA IC Interface 7 - 32 AS5013 Datasheet - D e t a i l e d D e s c r i p t i o n 7.2 XY Coordinates Interpretation The movement of the magnet over the Hall elements causes response which is geometrically distributed like a bell-shaped curve. The maximum magnet travel is a circle of 2mm radius around the center of the AS5013. The hall elements C1..C4 are placed on a circle centered on the middle of the package. The hall element C5, placed exactly in the middle is used for better linearity response with magnet displacement larger than 1.0mm. Figure 5. Hall Element Placement and Magnetic Field when the Magnet is Centered over each Hall Element 7.3 Transfer Function AS5013 has the possibility to adjust the transfer function for the used magnet and a specific range to optimize the linearity and resolution. The value will be provided from austriamicrosystems AG and has to be written in the algorithm related registers M_ctrl [0x2B], J_ctrl [0x2C], T_ctrl [0x2D] during the initialization phase. Please contact austriamicrosystems for parameter settings. Below is the optimal setup for a range of 0.6 mm to obtain the best dynamic range from XY registers -128~+127 with one given magnet airgap, with d2x0.8mm axial magnet. Figure 6. Example of Transfer Function Y_displacement vs. Y_register, Optimized for 0.6mm Travel Radius -50 90 0 11 00 13 00 0 -100 -150 mechanical y [um] www.austriamicrosystems.com/AS5013 150 100 50 0 -50 -100 -150 Revision 1.11 mechanical y [um] 90 0 11 00 13 00 50 -1 30 0 -1 10 0 -9 00 -7 00 -5 00 -3 00 -1 00 10 0 30 0 50 0 70 0 dy [LSB] 100 dy @ movement in y direction at constant x dy [LSB] 150 Series1 Series2 Series3 Series4 Series5 Series6 Series7 Series8 Series9 Series10 Series11 Series12 Series13 Series14 Series15 Series16 Series17 Series18 Series19 Series20 Series21 -1 30 0 -1 10 0 -9 00 -7 00 -5 00 -3 00 -1 00 10 0 30 0 50 0 70 0 dy @ movement in x direction at constant y Series1 Series2 Series3 Series4 Series5 Series6 Series7 Series8 Series9 Series10 Series11 Series12 Series13 Series14 Series15 Series16 Series17 Series18 Series19 Series20 Series21 8 - 32 AS5013 Datasheet - D e t a i l e d D e s c r i p t i o n 7.4 Power Modes The AS5013 can operate in two different power modes, depending on the power consumption requirements of the whole system. Figure 7. Readout Cycle Depending on Power Mode (idle bit) POR_n | soft_RES | RESETn START-UP: reset internal reg Tstartup (1000s) ( Idle=0 & Timebase_trigger ) | ( Idle=1 & Read y) WAIT MEASURE SET INTERRUPT Tconv (450s) START-UP. After power up and after applying a soft reset (Reg 0Fh [1]) or hardware reset (RESETn input, LOW pulse >100ns), AS5013 enters the STARTUP state. During this state the internal registers are loaded with their reset values. After min. Tstartup = 1000s, the AS5013 will perform one measurement and switches automatically into the WAIT state. MEASURE. The hall element data are measured, x/y coordinates are calculated and available in registers 10h and 11h after Tconv = 450s max. SET INTERRUPT. The INTn output is set, depending on the interrupt mode configured in the control register Reg 0Fh [2] and Reg 0Fh [3] WAIT. The module is now in waiting status. A new measurement will occur depending on the power mode (Reg 0Fh [7] Idle = 0 or 1) and the Timebase Reg 0Fh [6:4] www.austriamicrosystems.com/AS5013 Revision 1.11 9 - 32 AS5013 Datasheet - D e t a i l e d D e s c r i p t i o n 7.5 IC Interface The AS5013 supports the 2-wire high-speed IC protocol in device mode, according to the NXP specification UM10204. The host MCU (master) has to initiate the data transfers. The 7-bit device address of the AS5013 depends on the state at the pin ADDR. ADDR = 0 Slave address =`1000 000' (40h) ADDR = 1 Slave address =`1000 001' (41h) For other IC addresses, please contact austriamicrosystems. Supported modes (slave mode): Random/Sequential Read Byte/Page Write Standard Mode: 0 to 100kHz clock frequency Fast Mode: 0 to 400kHz clock frequency High Speed: 0 to 3.4MHz clock frequency The SDA signal is bidirectional and is used to read and write the serial data. The SCL signal is the clock generated by the host MCU, to synchronize the SDA data in read and write mode. The maximum IC clock frequency is 3.4MHz, data are triggered on the rising edge of SCL. 7.5.1 Interface Operation Figure 8. IC Timing Diagram for FS-mode SDA tBUF tLOW tR tHD.STA tF SCL tSU.DAT tHD.STA Stop Start tHD.DAT tHIGH tSU.STA tSU.STO Repeated Start Figure 9. Timing Diagram for HS-mode www.austriamicrosystems.com/AS5013 Revision 1.11 10 - 32 AS5013 Datasheet - D e t a i l e d D e s c r i p t i o n 7.5.2 IC Electrical Specification Standard-mode, Fast-mode, High Speed-mode Symbol Parameter Condition Min Max Unit VIL LOW-level input voltage -0.5 0.3VDDp V VIH HIGH-level input voltage 0.7VDDp VDDp + 0.5 (see note 1) V Vhys Hysteresis of Schmitt Trigger inputs VDDp < 2V 0.1VDDp VOL LOW-level output voltage (open-drain or open-collector) at 3mA sink current VDDp < 2V - 0.2VDDp V IOL LOW-level output current VOL = 0.4V - - mA ICS Pull-up current of SCLH current source SCLH output levels between 0.3VDDp and 0.7VDDp 3 12 mA In HS-mode - 10 (see note 2) ns tSP Pulse width of spikes that must be suppressed by the input filter In Fast-mode 50 (see note 2) ns Input voltage between 0.1VDDp and 0.9VDDp 10 (see note 3) A Ii Input current at each I/O Pin V CB Total capacitive load for each bus line - 400 pF CI/O I/O capacitance (SDA, SCL) - 10 pF Notes: 1. Maximum VIH = VDDpmax +0.5V or 5.5V, which ever is lower. 2. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50ns in Fast-mode and 10ns in HS-mode. 3. I/O pins of Fast-mode and Fast-mode plus devices must not obstruct the SDA and SCL lines if VDDp is switched off. 7.5.3 IC Timing Symbol Parameter Condition Fast-mode HS-mode CB=100pF HS-mode 1 CB=400pF Min Max Min Max Min Max Unit fSCLK SCL clock Frequency - 400 - 3400 - 1700 kHz tBUF Bus Free Time; time between STOP and START Condition 500 - 500 - 500 - ns 600 - 160 - 160 - ns tHD;STA Hold Time; (Repeated) START Condition 2 tLOW LOW Period of SCL Clock 1300 - 160 - 320 - ns tHIGH HIGH Period of SCL Clock 600 - 60 - 120 - ns tSU;STA Setup Time for a Repeated START condition 600 - 160 - 160 - ns tHD;DAT Data Hold Time 0 900 0 70 0 150 ns tSU;DAT Data Setup Time 100 - 10 - 10 - ns - - 10 40 20 80 ns trCL 3 4 Rise time of SCLH signal www.austriamicrosystems.com/AS5013 External pull-up source of 3mA Revision 1.11 11 - 32 AS5013 Datasheet - D e t a i l e d D e s c r i p t i o n Symbol trCL1 Parameter Rise time of SCLH signal after repeated START condition and after an acknowledge bit Condition External pull-up source of 3mA Fast-mode HS-mode CB=100pF HS-mode 1 CB=400pF Unit Min Max Min Max Min Max - - 10 80 20 160 ns tR Rise Time of SDA and SCL Signals 20+0.1CB 120 - - - - ns tF Fall time of SDA and SCL signals 20+0.1CB 120 - - - - ns 600 - 160 - 160 - ns 0.1VDDp - 0.1VDDp - 0.1VDDp - V 0.2VDDp - 0.2VDDp - 0.2VDDp - V tSU;STO Setup Time for STOP Condition Noise margin at LOW level For each connected device (including Noise margin at HIGH hysteresis) level VnL VnH 1. For bus line loads CB between 100pF and 400 pF the timing parameters must be linearly interpolated. 2. After this time the first clock is generated. 3. A device must internally provide a minimum hold time (300n for Fast-mode, 80ns / max 150ns for High-speed mode) for the SDA signal (referred to the VIHmin of the SCL) to bridge the undefined region of the falling edge of SCL. 4. A fast-mode device can be used in standard-mode system, but the requirement tSU;DAT = 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRmax + tSU;DAT = 1000 + 250 = 1250ns before the SCL line is released. 7.5.4 IC Modes The AS5013 supports the IC bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The AS5013 operates as a slave on the IC bus. Connections to the bus are made through the open-drain I/O lines SDA and the input SCL. Clock stretching is not included. Automatic Increment of Address Pointer. The AS5013 slave automatically increments the address pointer after each byte transferred. The increase of the address pointer is independent from the address being valid or not. Invalid Addresses. If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or write cycle is possible. The address pointer is increased after each byte. Reading. When reading from a wrong address, the AS5013 slave data returns all zero. The address pointer is increased after each byte. Sequential read over the whole address range is possible including address overflow. Writing. A write to a wrong address is not acknowledged by the AS5013 slave, although the address pointer is increased. When the address pointer points to a valid address again, a successful write access is acknowledged. Page write over the whole address range is possible including address overflow. The following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as start or stop signals. Accordingly, the following bus conditions have been defined: www.austriamicrosystems.com/AS5013 Revision 1.11 12 - 32 AS5013 Datasheet - D e t a i l e d D e s c r i p t i o n Bus Not Busy: Both data and clock lines remain HIGH. Start Data Transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of READ access to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Figure 10. Data Read (Write Pointer, Then Read) - Slave Receive and Transmit Slave Address SDA MSB SCL 1 2 Repeated if more Bytes are transferred 6 LSB R/W ACK 7 8 9 Start Condition ACK 1 7 8 9 Stop Condition or Repeated Start Condition Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver: The first byte transmitted by the master is the slave address, followed by R/ W = 0. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. If the slave does not understand the command or data it sends a "not acknowledge". Data is transferred with the most significant bit (MSB) first. Data transfer from a slave transmitter to a master receiver: The master transmits the first byte (the slave address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The AS5013 can operate in the following two modes: Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. Each byte is followed by an acknowledge bit (or by a not acknowledge depending on the address-pointer pointing to a valid position). START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see Figure 11). The slave address byte is the first byte received after the START condition. The slave address byte contains the 7-bit AS5013 address, which is stored in the OTP memory. The 7-bit slave address is followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA. After the AS5013 acknowledges the slave address + write bit, the master transmits a register address to the AS5013. This sets the address pointer on the AS5013. If the address is a valid readable address the AS5013 answers by sending an acknowledge. If the address-pointer points to an invalid position a "not acknowledge" is sent. The master may then transmit zero or more bytes of data. In case of the address pointer pointing to an invalid address the received data are not stored. The address pointer will increment after each byte transferred independent from the address being valid. If the address-pointer reaches a valid position again, the AS5013 answers with an acknowledge and stores the data. The master generates a STOP condition to terminate the data write. www.austriamicrosystems.com/AS5013 Revision 1.11 13 - 32 AS5013 Datasheet - D e t a i l e d D e s c r i p t i o n S <Slave address> <RW> Figure 11. Data Write - Slave Receiver Mode 1000000 0 <Word address (n)> A XXXXXXXX <Data(n)> A <Data(n+1)> XXXXXXXX S - Start A - Acknowledge (ACK) P - Stop A XXXXXXXX <Data(n+X)> A XXXXXXXX NA P Data transferred: X+1 Bytes + Acknowledge Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the AS5013 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit AS5013 address. The default address is 80h. The 7-bit slave address is followed by the direction bit (R/W), which, for a read, is 1. After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA line. The AS5013 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The AS5013 must receive a "not acknowledge" to end a read. S <Slave address> <RW> Figure 12. Data Read (from Current Pointer Location) - Slave Transmitter Mode 1000000 1 <Data(n)> A XXXXXXXX <Data(n+1)> A XXXXXXXX S - Start A - Acknowledge (ACK) NA - Not Acknowledge (NACK) P - Stop <Data(n+2)> A XXXXXXXX <Data(n+X)> A XXXXXXXX NA P Data transferred: X+1 Bytes + Acknowledge Note: Last data byte is followed by NACK 1000000 0 <Word Address (n)> A XXXXXXXX S - Start SA - Repeated Start A - Acknowledge (ACK) NA - Not Acknowledge (NACK) P - Stop www.austriamicrosystems.com/AS5013 A Sr <Slave Address> <RW> S <Slave address> <RW> Figure 13. Data Read (from New Pointer Location) - Slave Transmitter Mode 1000000 1 <Data(n)> A XXXXXXXX <Data(n+X)> <Data(n+1)> A XXXXXXXX A XXXXXXXX NA P Data transferred: X+1 Bytes + Acknowledge Note: Last data byte is followed by NACK Revision 1.11 14 - 32 AS5013 Datasheet - D e t a i l e d D e s c r i p t i o n High Speed Mode. The AS5013 is capable to work in HS-mode. For switching to HS-mode the Master has to send the sequence: START, MASTER CODE, NACK. This sequence is sent in FS-mode. As no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge. After a device receives the master code it has to switch from FS-settings to HS-settings within tSU.STA which is 160ns for HS-mode. The device stays in HS-mode as long as it does not receive a STOP command. After receiving a STOP command it has to switch back form HS-settings to FS-settings, which has to be competed within the minimum bus free time tBUF which is 500ns. When switching to HS-mode the slave has to: Adapt the SDAH and SCLH input filters according to the spike suppression requirement required in HS-mode. In HS-mode spikes up to 10ns, in FS-mode spikes up to 50ns have to be suppressed. Adapt the setup and hold times according to the HS-mode requirement. In HS-mode an internal hold time for SDA for START/STOP detection of 80ns (max. 150ns), in FS-mode an internal hold time of 160ns (max. 250ns) has to be provided. Adapt the slope control for SDAH output stage. Figure 14. Data Transfer Format in HS-mode F/S mode S Master code Hs mode (current source for SCLH enabled) NA Sr Slave Address R/W A DATA F/S mode A/ P NA Hs mode continues < n bytes + ack > Sr Slave Address Figure 15. A Complete HS-mode Transfer www.austriamicrosystems.com/AS5013 Revision 1.11 15 - 32 AS5013 Datasheet - D e t a i l e d D e s c r i p t i o n Automatic Increment of Address Pointer. The AS5013 slave automatically increments the address pointer after each byte transferred. The increase of the address pointer is independent from the address being valid or not. Invalid Addresses. If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or write cycle is possible. The address pointer is increased after each byte. Reading: When reading from a wrong address, the AS5013 slave returns all zero. The address pointer is increased after each byte. Sequential read over the whole address range is possible including address overflow. Writing: A write to a wrong address is not acknowledged by the AS5013 slave, although the address pointer is increased. When the address pointer points to a valid address again, a successful write accessed is acknowledged. Page write over the whole address range is possible including address overflow. 7.5.5 SDA, SCL Input Filters Input filters for SDA and SCL inputs are included to suppress noise spikes of less than 50ns. Furthermore, the SDA line is delayed by 120ns to provide an internal hold time for Start/Stop detection to bridge the undefined region of the falling edge of SCL. The delay needs to be smaller than tHD.STA 260ns. www.austriamicrosystems.com/AS5013 Revision 1.11 16 - 32 AS5013 Datasheet - I C R e g i s t e r s 8 IC Registers 8.1 Control Register 1 (0Fh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Idle Time base bit[2] Time base bit[1] Time base bit[0] INT_disable INT_function Soft_rst Data_valid R/W R/W R/W R/W R/W R R/W R/W Reset value: 1111 0000 Bit 7 6:4 3 Bit Description 0 = Low Power Mode The measurements are triggered with an internal low power oscillator - the user can select between 8 different timings by setting the low power timebase (Control Register 1 [6:4]) 1 = Idle Mode (default) A new measurement cycle is started after the IC ACK bit following the read out of the Y_res_int register 11h. The readout rate and thus the power consumption is externally controlled by the host MCU. Configure the time base of the automatic wakeup in Low Power Mode (see Table 5). 0 = Interrupt output INTn is enabled (default) 1 = Interrupt output INTn is disabled and is fixed to Hi-Z 0 = Interrupt output INTn is active `0' after each measurement (default): - Automatically triggered in Low Power mode, depending on the time base chosen - 450s after Y readout in Idle mode The interrupt is cleared by the IC ACK bit after reading the Y_res_int 11h. In block read mode, the several other bytes could be transferred before the interrupt is cleared. 2 1 = Interrupt output INTn is active `0' when the movement of the magnet exceeds the Dead Zone area (see Figure 16). The Dead Zone area is set by registers Xp (Reg 12h), Xn (Reg 13h), Yp (Reg 14h), Yn (Reg 15h). The interrupt is cleared by the IC ACK bit after reading the Y_res_int register 11h, and will be active `0' at the next measurement if the magnet is still in the Detection Area. In block read mode, several other bytes could be transferred before the interrupt is cleared when the Y_res_int register is read. It is recommended to use this mode with the Low Power mode (Idle = 0), in order to wake up automatically a system when the magnet has been moved away from the center. The polling time is set by the Low Power time base bit [6:4]. 0 = Normal mode (default) 1 0 1 = Reset mode. All the internal registers are loaded with their reset value. The Control Register 1 is loaded as well with the value 1111 0000, then the Soft_rst bit goes back to 0 (Normal mode) once the internal reset sequence is finished. 0 = Conversion of new coordinates ongoing, no valid coordinate is present in the X and Y_res_int registers. Reading those registers at that moment can give wrong values. 1 = New coordinate values are ready in X and Y_res_int registers. Note: The values in Control Register 1, X_register and Y_res_int register are frozen when the IC address pointer is set to 0Fh, 10h or 11h. This ensures that the Data_valid bit, X and Y values are taken at the same time. In order to get updated values from those registers, set the address pointer to any other address. www.austriamicrosystems.com/AS5013 Revision 1.11 17 - 32 AS5013 Datasheet - I C R e g i s t e r s Table 5. Configuration Low Power time base CONFIG_REG1 0Fh [6:4] ttimebase (ms) Average Core Current IDD (A) @TAMB = 25C 000b 20 190 001b 40 97 010b 80 50 011b 100 40 100b 140 30 101b 200 22 110b 260 17 111b (default) 320 15 Figure 16. Dead Zone Representation with INT_function=1 www.austriamicrosystems.com/AS5013 Revision 1.11 18 - 32 AS5013 Datasheet - I C R e g i s t e r s 8.2 X Register (10h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X[7] X[6] X[5] X[4] X[3] X[2] X[1] X[0] R R R R R R R R Reset value: 0000 0000 Bit 7:0 Bit Description X coordinate, Two's complement format (signed -128 ~ +127). 8.3 Y_res_int Register (11h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] Y[0] R R R R R R R R Reset value: 0000 0000 Bit 7:0 Bit Description Y coordinate, Two's complement format (signed -128 ~ +127). Reading this register will reset the INTn output to Hi-Z after the ACK bit of Y_res_int register readback. 8.4 Xp Register (12h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Xp[7] Xp[6] Xp[5] Xp[4] Xp[3] Xp[2] Xp[1] Xp[0] R/W R/W Reset value: 0000 0101 (5d) R/W R/W R/W R/W R/W R/W Bit Bit Description Xp range value, Two's complement (signed: -128 ~ +127). 7:0 Determines the LEFT threshold for the activation of INTn output (if output enabled), when bit INT_function = 1 (see Control Register 1 (0Fh) on page 17). 8.5 Xn Register (13h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Xn[7] Xn[6] Xn[5] Xn[4] Xn[3] Xn[2] Xn[1] Xn[0] R/W R/W Reset value: 1111 1011 (-5d) R/W R/W R/W R/W R/W R/W Bit Bit Description Xn range value, Two's complement (signed: -128 ~ +127). 7:0 Determines the RIGHT threshold for the activation of INTn output (if output enabled), when bit INT_function = 1 (see Control Register 1 (0Fh) on page 17). www.austriamicrosystems.com/AS5013 Revision 1.11 19 - 32 AS5013 Datasheet - I C R e g i s t e r s 8.6 Yp Register (14h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Yp[7] Yp[6] Yp[5] Yp[4] Yp[3] Yp[2] Yp[1] Yp[0] R/W R/W Reset value: 0000 0101 (5d) R/W R/W R/W R/W R/W R/W Bit 7:0 Bit Description Yp range value, Two's complement (signed: -128 ~ +127). Determines the TOP threshold for the activation of INTn output (if output enabled), when bit INT_function = 1 (see Control Register 1 (0Fh) on page 17). 8.7 Yn Register (15h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Yn[7] Yn[6] Yn[5] Yn[4] Yn[3] Yn[2] Yn[1] Yn[0] R/W R/W Reset value: 1111 1011 (-5d) R/W R/W R/W R/W R/W R/W Bit 7:0 Bit Description Yn range value, Two's complement (signed: -128 ~ +127). Determines the BOTTOM threshold for the activation of INTn output (if output enabled), when bit INT_function = 1 (see Control Register 1 (0Fh) on page 17). 8.8 M_ctrl Register (2Bh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M_ctrl[7] M_ctrl[6] M_ctrl[5] M_ctrl[4] M_ctrl[3] M_ctrl[2] M_ctrl[1] M_ctrl[0] R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 0000 0000 (00h) Bit Bit Description 7:0 Middle hall element C5 control register to improve the linearity of XY outputs for the whole mechanical XY displacement of the magnet. Use the default value for d=2*0.8mm standard axial magnet. For more information on how to configure this parameter, please contact austriamicrosystems. 8.9 J_ctrl Register (2Ch) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 J_ctrl[7] J_ctrl[6] J_ctrl[5] J_ctrl[4] J_ctrl[3] J_ctrl[2] J_ctrl[1] J_ctrl[0] R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 0000 0110 (06h) Bit 7:0 Bit Description Sector dependent attenuation of the outer Hall elements C1..C4 in order to improve the linearity of XY outputs for the whole mechanical XY displacement of the magnet. Use the default value for d=2*0.8mm standard axial magnet. For more information on how to configure this parameter, please contact austriamicrosystems. www.austriamicrosystems.com/AS5013 Revision 1.11 20 - 32 AS5013 Datasheet - I C R e g i s t e r s 8.10 T_ctrl Register (2Dh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T_ctrl[7] T_ctrl[6] T_ctrl[5] T_ctrl[4] T_ctrl[3] T_ctrl[2] T_ctrl[1] T_ctrl[0] R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 0000 1001 (09h) Bit Bit Description Scaling control register. This register controls the scaling factor of the XY coordinates to fit to the 8-bit X and Y_res_int register (full dynamic range). The following table includes scaling factors referenced to the default setting T_ctrl = 9 (100% scaling). 7:0 T_ctrl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Scaling Factor % 31.3 32.2 33.4 34.6 35.7 37.1 38.5 40.0 41.6 43.6 45.5 47.7 50.0 52.5 55.5 58.8 62.5 66.6 71.5 77.0 83.4 90.8 100.0 111.1 www.austriamicrosystems.com/AS5013 T_ctrl 47 7 45 6 43 5 41 4 79 39 77 3 75 37 73 2 71 35 69 1 67 Revision 1.11 Scaling Factor % 117.6 125.0 133.4 142.8 153.9 166.6 181.8 200.0 210.5 222.3 235.4 250.0 266.6 285.7 307.6 333.4 363.7 400.0 444.5 500.0 571.5 21 - 32 AS5013 Datasheet - I C R e g i s t e r s 8.11 Control Register 2 (2Eh) Bit 7 Bit 6 Bit 5 Bit 4 Test Test Test ext_clk_en R/W R/W Reset value: 1000 0100 R/W R/W Bit 7 6:4 Bit 3 Bit 2 use_static_offset EN_offset_comp R/W R/W Bit 1 Bit 0 inv_spinning pptrim_en R/W R/W Bit Description Test bit. Must configured `1'. Test bit. Must configured `000'. 3 Test bit. Must configured `0'. 2 Test bit. Must configured `1'. 1 Magnet Polarity bit. Must be set after power up, depending on how the magnet is placed (see Figure 17). 0 Test bit. Must configured `0'. Figure 17. Magnet Configuration S N N S N S AS5013 S N AS5013 AS5013 Magnet configuration 1 AS5013 Magnet configuration 2 Magnet configuration 3 Magnet configuration 4 (e.g. EasyPoint modules) Bit Inv_spinning = 0 (default) Bit Inv_spinning = 1 Note: In order to know the polarity of the magnet without any testing device, please refer to Registers Initialization on page 24. 8.12 Hall Element Direct Read Registers (16h to 29h) Each hall element C1..C5 can be read independently, after each interrupt (data ready). One hall element value consists of two 12-bit signed-registers: Cx_neg and Cx_pos. For each conversion cycle (i.e. after a readout or Y_res in idle mode, or at each time-based conversion cycle in Low Power mode), each hall element is read twice: With normal spin (result Cx_pos) and then with inverted spin (result Cx_neg) in order to remove any hall voltage offset from the hall elements. The formula to read any hall element Cx: Cx = (Cx_pos - Cx_neg) / 2 (EQ 1) Where: Cx_pos = (Cx_pos[11:8] << 8) | Cx_pos[7:0] Cx_neg = (Cx_neg[11:8] << 8) | Cx_neg[7:0] www.austriamicrosystems.com/AS5013 Revision 1.11 22 - 32 AS5013 Datasheet - I C R e g i s t e r s 8.13 Hall Element Direct Read Registers (2Ah) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 AGC5 AGC4 AGC3 AGC2 AGC1 AGC0 R/W R/W R/W R/W R/W R/W R R Reset value: 0010 0000 The AGC register controls the sensitivity of each hall element C1..C5, in order to stay in the larger dynamic range of the 12-bit ADC of the AS5013. In order to determine the best value to be set during the AS5013 initialization, place your magnet on the 0,0 position (centered on C5 hall element), and increase the AGC value to obtain the nearest value to 2867 (= 70% of 4096). It is possible that this value cannot be reached with small magnets or with large airgaps. In that case set AGC to 3Fh, which is the maximum sensitivity. 8.14 Power ON The AS5013 has a Power ON Reset (POR) cell to monitor the VDD voltage at startup and reset all the internal registers. After the internal reset is completed, the POR cell is disabled in order to save current during normal operation. If VDD drops below 2.7V down to 0.2V, the POR cell will not be enabled back, and the registers will not be correctly reseted or can get random values. Note: It is highly recommended to control the external RESETn signal by applying a LOW pulse of >100ns once VDD reached 2.7V and VDDp reached 1.7V. 2.7V Internal reset completed VDD 0V VDDp (>1.7V) RESETn 0 Power up phase >100ns VDD >1000us 2.7V 0.2V 0V Power up phase >1000us Internal reset completed Figure 18. Power-up Sequence VDD @ t=0 between 0V and 0.2V VDD @ t=0 between 0V and 2.7V External RESETn pin, and without Power on Reset (POR) www.austriamicrosystems.com/AS5013 Revision 1.11 Power on Reset (POR) only 23 - 32 AS5013 Datasheet - I C R e g i s t e r s 8.15 Registers Initialization After Power Up, the following sequence must be performed: 1. VDD and VDDp Power up, and reached their nominal values (VDD>2.7V, VDDp>1.7V). 2. RESETn LOW during >100ns 3. Delay 1000s 4. Loop check register [0Fh] until the value F0h or F1h is present (reset finished, registers to their default values) 5. Optional: Write value 86h into register [2Eh] Invert magnet polarity. See Control Register 2 (2Eh) on page 22. 6. Configure register [2Bh] Configure M_ctrl middle hall element control 7. Configure register [2Ch] Configure J_ctrl attenuation factor 8. Configure register [2Dh] Configure T_ctrl scaling factor 9. Configure the wanted Power Mode into register [0Fh] (Idle mode or Low Power Mode with Timebase configuration) 10. X Y coordinates are ready to be read. Note: In order to detect if the magnet polarity is correct, read the C5 middle hall element when the magnet is centered. C5 = (C5_pos - C5_neg) / 2 With: C5_pos = (c5_pos[11:8] << 8) | c5_pos[7:0] C5_neg = (c5_neg[11:8] << 8) | c5_neg[7:0] C5 must always be positive. If C5 is negative, then invert the bit inv_spinning in the Control Register 2 (2Eh). C5 will become positive. 8.16 Registers Table The following registers / functions are accessible over the serial IC interface. Table 6. Registers Register Number Access Address of bits Format Reset Value Bit Description IC Identification ID Version 8 R 0D 0Dh <7:0> 8-bit Manufacture ID Code <7:0> 8-bit Component ID Version Silicon Revision 8 R 0E 00h <7:0> 8-bit Silicon Revision ID Code 8 R 0C 0Ch Control_register_1 Idle 1 R/W 0Fh 1b Low_power_timebase 3 R/W 0Fh 111b INT_disable 1 R/W 0Fh 0b INT_function 1 R/W 0Fh 0b soft_rst 1 R/W 0Fh 0b 1 R 0Fh 0b data_valid www.austriamicrosystems.com/AS5013 1: Idle mode 0: Low Power mode <6:4> Low Power readout time base register Disables the interrupt functionality. <3> 1: Interrupt disabled 0: Interrupt enabled Interrupt control register 0: interrupt goes low with every new calculated x/y coordinates <2> 1: interrupt pin goes low in when new x/y coordinates are calculated and the magnet has exited the xp, xn, yp, yn threshold values Soft Reset <1> 0: Normal mode 1: all registers return to their respective reset value <0> Data valid indicator 0: X/Y calculation ongoing 1: X/Y calculation finished, coordinates ready Revision 1.11 <7> 24 - 32 AS5013 Datasheet - I C R e g i s t e r s Table 6. Registers Register Number Access Address of bits Reset Value Format Bit Description X/Y Coordinate Registers x 8 R 10h two's comp. 00h y_res_int 8 R 11h two's comp. 00h <7:0> Result <7:0> Result, resets the interrupt flag at the value ACK Range Settings xp 8 R/W 12h two's comp. 5h (5 dec) xn 8 R/W 13h two's comp. FBh <7:0> wake up threshold @ negative X -direction (-5 dec) yp 8 R/W 14h two's comp. 5h (5 dec) yn 8 R/W 15h two's comp. FBh <7:0> wake up threshold @ negative Y -direction (-5 dec) <7:0> wake up threshold @ positive X -direction <7:0> wake up threshold @ positive Y -direction Channel voltages (3) c4_neg <11:8> 4 R 16h two's comp. 00h c4_neg <7:0> 8 R 17h two's comp. 00h c4_pos <11:8> 4 R 18h two's comp. 00h c4_pos <7:0> 8 R 19h two's comp. 00h c3_neg <11:8> 4 R 1Ah two's comp. 00h c3_neg <7:0> 8 R 1Bh two's comp. 00h c3_pos <11:8> 4 R 1Ch two's comp. 00h c3_pos <7:0> 8 R 1Dh two's comp. 00h c2_neg <11:8> 4 R 1Eh two's comp. 00h c2_neg <7:0> 8 R 1Fh two's comp. 00h c2_pos <11:8> 4 R 20h two's comp. 00h c2_pos <7:0> 8 R 21h two's comp. 00h c1_neg <11:8> 4 R 22h two's comp. 00h c1_neg <7:0> 8 R 23h two's comp. 00h c1_pos <11:8> 4 R 24h two's comp. 00h c1_pos <7:0> 8 R 25h two's comp. 00h c5_neg <11:8> 4 R 26h two's comp. 00h c5_neg <7:0> 8 R 27h two's comp. 00h c5_pos <11:8> 4 R 28h two's comp. 00h c5_pos <7:0> 8 R 29h two's comp. 00h www.austriamicrosystems.com/AS5013 <3:0> Voltage @ channel 4, negative current spinning <7:4> Sign extended to 8 bit <7:0> Voltage @ channel 4, negative current spinning <3:0> Voltage @ channel 4, positive current spinning <7:4> Sign extended to 8 bit <7:0> Voltage @ channel 4, positive current spinning <3:0> Voltage @ channel 3, negative current spinning <7:4> Sign extended to 8 bit <7:0> Voltage @ channel 3, negative current spinning <3:0> Voltage @ channel 3, positive current spinning <7:4> Sign extended to 8 bit <7:0> Voltage @ channel 3, positive current spinning <3:0> Voltage @ channel 2, negative current spinning <7:4> Sign extended to 8 bit <7:0> Voltage @ channel 2, negative current spinning <3:0> Voltage @ channel 2, positive current spinning <7:4> Sign extended to 8 bit <7:0> Voltage @ channel 2, positive current spinning <3:0> Voltage @ channel 1, negative current spinning <7:4> Sign extended to 8 bit <7:0> Voltage @ channel 1, negative current spinning <3:0> Voltage @ channel 1, positive current spinning <7:4> Sign extended to 8 bit <7:0> Voltage @ channel 1, positive current spinning <3:0> Voltage @ channel 5, negative current spinning <7:4> Sign extended to 8 bit <7:0> Voltage @ channel 5, negative current spinning <3:0> Voltage @ channel 5, positive current spinning <7:4> Sign extended to 8 bit <7:0> Voltage @ channel 5, positive current spinning Revision 1.11 25 - 32 AS5013 Datasheet - I C R e g i s t e r s Table 6. Registers Register Number Access Address of bits Format Reset Value Bit Description Hall Bias Currents AGC 8 RW 2Ah 00b 20h <7:6> Not implemented (read 00b) <5:0> 6 bit AGC value (if an AGC algorithm implemented in the C) M_ctrl 8 R/W J_ctrl 8 R/W T_ctrl 8 R/W Control Register for the Algorithm Control register for the middle Hall element C5. If the 2Bh 00h <7:0> register is zero the middle Hall element is not used for the XY calculation Control register for the sector dependent attenuation 2Ch 06h <7:0> of the outer Hall elements 2Dh 09h <7:0> Scale input to fit to the 8 Bit result register Test 1 R/W 2Eh 1b <7> Test only, must be `1' Test 1 R/W 2Eh 0b <6> Test only, must be `0' Test 1 R/W 2Eh 0b <5> Test only, must be `0' Control_register_2 ext_clk_en 1 R/W 2Eh 0b <4> Test only, must be `0' use_static_offset 1 R/W 2Eh 0b <3> Test only, must be `0' EN_offset_comp 1 R/W 2Eh 1b <2> inv_spinning 1 R/W 2Eh 0b <1> pptrim_en 1 R/W 2Eh 0b <0> Test only, must be `1' Invert the channel voltage. Set to invert the magnet polarity Factory only, must be `0' www.austriamicrosystems.com/AS5013 Revision 1.11 26 - 32 AS5013 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 9 Package Drawings and Markings The device is available in a 16-pin QFN (4x4x0.55mm) package. Figure 19. Drawings and Dimensions YYWWIZZ AS5013 Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. 3. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.15mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional. 6. N is the total number of terminals. www.austriamicrosystems.com/AS5013 Revision 1.11 Symbol A A1 A3 L L1 b D E e D2 E2 aaa bbb ccc ddd eee fff N Min 0.50 0 0.35 0 0.25 2.60 2.60 - Nom 0.55 0.02 0.40 0.30 4.00 BSC 4.00 BSC 0.65 BSC 2.70 2.70 0.15 0.10 0.10 0.05 0.08 0.10 16 Max 0.65 0.05 0.22 0.45 0.15 0.35 2.80 2.80 - 27 - 32 AS5013 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s Marking: YYWWIZZ. YY WW I ZZ Last two digits of the current year Manufacturing Week Assembly plant identifier Assembly traceability code 9.1 Recommended Footprint Figure 20. Footprint C1 X2 Y2 C2 1 X1 Recommended Footprint Data Symbol (mm) Typ C1 3.7 C2 3.7 E 0.65 X1 0.40 Y1 0.7 X2 2.6 Y2 2.6 Y1 E 9.2 Recommended Mounting The typical mounting configuration of the AS5013 with the mechanics is on both sides of the PCB: - Mechanics + Magnet on the top side - AS5013 IC on the bottom side A thickness of 0.3mm to 1.0mm for the PCB is recommended. A dome switch for push button function can be added as well. Figure 21. AS5013 Mounting Example for Low Profile Joystick Knob Magnet Adhesive tape Dome switch PCB AS 5013 www.austriamicrosystems.com/AS5013 Revision 1.11 28 - 32 AS5013 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s Figure 22. Layout Example for Low Profile Joystick Bottom SIDE View (AS5013) GND via for dome switch contact on bottom layer VDD & VDDp 100nF capacitors ADDR to GND (example) Top SIDE View (mechanics side) Dome switch contact on PCB (GND) Dome switch placement www.austriamicrosystems.com/AS5013 Revision 1.11 29 - 32 AS5013 Datasheet - R e v i s i o n H i s t o r y Revision History Revision Date 0.2 06 Apr, 2010 Owner Description Preliminary 1.0 15 Jun, 2010 Y_res_int ACK resets INTn, not STOP bit Bit Soft_rst description inverted (soft_rst = Normal mode) Control register 2 bit 7: always 1 and Test bits fixed to `0' Added PSSR and Noise values 1.1 02 Jul, 2010 Registers Initialization (refer to page 24) - step 5: Write 86h to Control register 2, for magnet polarity inversion 1.2 19 Jul, 2010 IC Interface (refer to page 10) - IC address inverted (40h and 41h for 1000 000 and 1000 001) 1.3 22 Jul, 2010 Added chapter Power ON (page 23) 1.4 16 Aug, 2010 Pin Assignments (page 3) and Absolute Maximum Ratings (page 4): ESD direct pad contact 2kV 1.5 20 Sep, 2010 Updated IC Timing diagrams 1.10 08 Jul, 2011 Updated the entire datasheet according to the latest specification 1.11 05 Jan, 2012 rph Updated Figure 3 and Table 6 Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com/AS5013 Revision 1.11 30 - 32 AS5013 Datasheet - O r d e r i n g I n f o r m a t i o n 10 Ordering Information The devices are available as the standard products shown in Table 7. Table 7. Ordering Information Ordering Code Description AS5013-IQFT Delivery Form Package Tape & Reel 16-pin QFN (4x4x0.55mm) Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Technical Support is available at http://www.austriamicrosystems.com/Technical-Support For further information and requests, please contact us mailto: sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com/AS5013 Revision 1.11 31 - 32 AS5013 Datasheet - C o p y r i g h t s Copyrights Copyright (c) 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com/AS5013 Revision 1.11 32 - 32