a
AD7660
16-Bit, 100 kSPS PulSAR
®
Unipolar CMOS ADC
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
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may result from its use. No license is granted by implication or otherwise
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REV. E
FUNCTIONAL BLOCK DIAGRAM
SWITCHED
CAP DAC 16
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CLOCK
AD7660
D[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
OGND
OVDD
DGNDDVDD
AVDD AGND REF REFGND
IN
INGND
PD
RESET
SERIAL
PORT
PARALLEL
INTERFACE
CNVST
FEATURES
Throughput: 100 kSPS
INL: 3 LSB Max (0.0046% of Full-Scale)
16-Bit Resolution with No Missing Codes
S/(N+D): 87 dB Min @ 10 kHz, 90 dB Typ @ 45 kHz
THD: –96 dB Max @ 10 kHz
Analog Input Voltage Range: 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Single 5 V Supply Operation
21 mW Typical Power Dissipation, 21 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flatpack (LQFP)
48-Lead Chip Scale Package (LFCSP)
Pin-to-Pin Compatible with the AD7664
APPLICATIONS
Data Acquisition
Battery-Powered Systems
PCMCIA
Instrumentation
Automatic Test Equipment
Scanners
Medical Instruments
Process Control
GENERAL DESCRIPTION
The AD7660 is a 16-bit, 100 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. The part contains an internal conversion clock, error cor-
rection circuits, and both serial and parallel system interface ports.
The AD7660 is hardware factory-calibrated and is comprehen-
sively tested to ensure ac parameters such as signal-to-noise ratio
(SNR) and total harmonic distortion (THD), in addition to the
more traditional dc parameters of gain, offset, and linearity.
It is fabricated using Analog Devices’ high performance,
0.6 micron CMOS process with correspondingly low cost and is
available in a 48-lead LQFP and a tiny 48-lead LFCSP with
operation specified from –40∞C to +85∞C.
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD7660 is a 100 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Superior INL
The AD7660 has a maximum integral nonlinearity of 3 LSBs
with no missing 16-bit code.
3. Single-Supply Operation
The AD7660 operates from a single 5 V supply and only
dissipates 21 mW typical. Its power dissipation decreases
with the throughput to, for instance, only 21 mW at a 100 SPS
throughput. It consumes 7 mW maximum when in power-down.
4. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement com-
patible with both 3 V or 5 V logic.
Table I. PulSAR Selection
Type/kSPS 100–250 500–570 800–1000
Pseudo AD7651 AD7650/AD7652 AD7653
Differential AD7660/AD7661 AD7664/AD7666 AD7667
True Bipolar AD7663 AD7665 AD7671
True AD7675 AD7676 AD7677
Differential
18-Bit AD7678 AD7679 AD7674
Simultaneous/ AD7654
Multichannel AD7655
AD7660–SPECIFICATIONS
(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
REV. E
–2–
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range V
IN
– V
INGND
0V
REF
V
Operating Input Voltage V
IN
–0.1 +3 V
V
INGND
–0.1 +0.5 V
Analog Input CMRR f
IN
= 25 kHz 70 dB
Input Current 100 kSPS Throughput 325 nA
Input Impedance See Analog Input Section
THROUGHPUT SPEED
Complete Cycle 10 ms
Throughput Rate 0 100 kSPS
DC ACCURACY
Integral Linearity Error –3 +3 LSB
1
Differential Linearity Error –1 +1.75 LSB
No Missing Codes 16 Bits
Transition Noise
2
0.75 LSB
Full-Scale Error
3
REF = 2.5 V ±0.045 ±0.08 % of FSR
Unipolar Zero Error
3
±1±5LSB
Power Supply Sensitivity AVDD = 5 V ±5% ±3LSB
AC ACCURACY
Signal-to-Noise f
IN
= 10 kHz 87 90 dB
4
f
IN
= 45 kHz 90 dB
Spurious-Free Dynamic Range f
IN
= 10 kHz 96 dB
f
IN
= 45 kHz 100 dB
Total Harmonic Distortion f
IN
= 10 kHz –96 dB
f
IN
= 45 kHz –100 dB
Signal-to-(Noise+Distortion) f
IN
= 10 kHz 87 dB
f
IN
= 45 kHz 90 dB
–60 dB Input 30 dB
–3 dB Input Bandwidth 820 kHz
SAMPLING DYNAMICS
Aperture Delay 2ns
Aperture Jitter 5ps rms
Transient Response Full-Scale Step 8 ms
REFERENCE
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 100 kSPS Throughput 22 mA
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25 V
Operating Current 100 kSPS Throughput
AVDD 3.2 mA
DVDD
5
1mA
OVDD
5
10 mA
Power Dissipation
5
100 kSPS Throughput 21 25 mW
100 SPS Throughput 21 mW
in Power-Down Mode
5, 6
7mW
DIGITAL INPUTS
Logic Levels
V
IL
–0.3 +0.8 V
V
IH
+2.0 OVDD + 0.3 V
I
IL
–1 +1 mA
I
IH
–1 +1 mA
DIGITAL OUTPUTS
Data Format Parallel or Serial 16-Bit
Pipeline Delay Conversion Results Available Immediately
after Completed Conversion
V
OL
I
SINK
= 1.6 mA 0.4 V
V
OH
I
SOURCE
= –500 mAOVDD – 0.6 V
REV. E–3–
AD7660
Parameter Conditions Min Typ Max Unit
TEMPERATURE RANGE
Specified Performance T
MIN
to T
MAX
–40 +85 ∞C
NOTES
1
LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15 mV.
2
Typical rms noise at worst-case transitions and temperatures.
3
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
4
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
5
Tested in Parallel Reading Mode.
6
With all digital inputs forced to DVDD or DGND respectively.
Specifications subject to change without notice.
(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
TIMING SPECIFICATIONS
Parameter
Symbol Min Typ Max Unit
REFER TO FIGURES 11 AND 12
Convert Pulsewidth t
1
5ns
Time between Conversions t
2
10 ms
CNVST LOW to BUSY HIGH Delay t
3
15 ns
BUSY HIGH All Modes Except in t
4
2ms
Master Serial Read after Convert Mode
Aperture Delay t
5
2ns
End of Conversion to BUSY LOW Delay t
6
10 ns
Conversion Time t
7
2ms
Acquisition Time t
8
8ms
RESET Pulsewidth t
9
10 ns
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t
10
2ms
DATA Valid to BUSY LOW Delay t
11
45 ns
Bus Access Request to DATA Valid t
12
40 ns
Bus Relinquish Time t
13
515ns
REFER TO FIGURE 16 AND 17 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay t
14
10 ns
CS LOW to Internal SCLK Valid Delay t
15
10 ns
CS LOW to SDOUT Delay t
16
10 ns
CNVST LOW to SYNC Delay t
17
500 ns
SYNC Asserted to SCLK First Edge Delay t
18
4ns
Internal SCLK Period t
19
40 75 ns
Internal SCLK HIGH (INVSCLK Low)
2
t
20
30 ns
Internal SCLK LOW (INVSCLK Low)
2
t
21
9.5 ns
SDOUT Valid Setup Time t
22
4.5 ns
SDOUT Valid Hold Time t
23
3ns
SCLK Last Edge to SYNC Delay t
24
3
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read after Convert t
28
3.2 ms
CNVST LOW to SYNC Asserted Delay t
29
1.5 ms
SYNC Deasserted to BUSY LOW Delay t
30
50 ns
REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)
1
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
316ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
NOTES
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
REV. E
AD7660
–4–
ABSOLUTE MAXIMUM RATINGS
1
Analog Inputs
IN
2
, REF, INGND, REFGND . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD,
AVDD to OVDD . . . . . . . . . . . . . ±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V
Digital Inputs
Except the Databus D(7:4) . . . –0.3 V to DVDD + 0.3 V
Databus Inputs D(7:4) . . . . . . –0.3 V to OVDD + 0.3 V
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation
4
. . . . . . . . . . . . . . . . . . . . . 2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
See Analog Input section.
3
Specification is for device in free air: 48-Lead LQFP: q
JA
= 91∞C/W, q
JC
= 30∞C/W.
4
Specification is for device in free air: 48-Lead LFCSP: q
JA
= 26∞C/W.
I
OH
500A
1.6mA I
OL
TO OUTPUT
PIN 1.4V
C
L
60pF
*
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing
PIN CONFIGURATION
t
DELAY
t
DELAY
0.8V
0.8V 0.8V
2V2V
2V
Figure 2. Voltage Reference Levels for Timings
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7660 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model1Temperature Range Package Description Package Option
–40∞C to +85∞CST-48
–40∞C to +85∞CST-48
–40∞C to +85∞C
AD7660ASTZ
AD7660ASTZRL
AD7660ACPZRL
NOTES
1Z = RoHS Compliant Part.
CP-48-4
48-Lead LQFP
48-Lead LQFP
48-Lead LFCSP
AGND
AVDD
NC
DGND
OB/2C
NC
NC
SER/PAR
D0
D1
D2
D3
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
NC
NC
NC
NC
NC
IN
NC
NC
NC
INGND
REFGND
REF
24
23
22
21
20
19
18
17
16
15
14
13
44
45
46
47
48
43
42
41
40
39
38
37
AD7660
TOP V I EW
(Not to Scale)
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
10
11
12
NOTES
1. NC = NO CO NNECT. DO NO T CO NNECT TO THI S PIN.
2. T HE EPAD IS CONNECTED TO GROUND; HOW EVER,
T HI S CO NNE CTION I S NOT RE Q UIREDTO ME E T
SPE CIF I E D P E RF ORMANCE.
REV. E
AD7660
–5–
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Type Description
1AGND P Analog Power Ground Pin
2AVDD P Input Analog Power Pins. Nominally 5 V.
3, 6, 7, NC No Connect
40–42,
44–48
4DGND DI Must Be Tied to Digital Ground
5OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a twos complement output from
its internal shift register.
8SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the
Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.
9–12 D[0:3] DO Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs regardless
of the state of SER/PAR.
13 D4 DI/O When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
or EXT/INT When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal
clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is
synchronized to an external clock signal connected to the SCLK input.
14 D5 DI/O When SER/PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.
or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state
of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
15 D6 DI/O When SER/PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.
or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK
signal. It is active in both Master and Slave Modes.
16 D7 DI/O When SER/PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data
input or a Read Mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the
conversion results from two or more ADCs onto a single SDOUT line. The digital data level
on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read
sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is
HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the
data is output on SDOUT only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground
21 D8 DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7660
provides the conversion result, MSB first, from its internal shift register. The DATA format
is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT
is valid on both edges of SCLK.
In Serial Mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next
rising edge.
REV. E
AD7660
–6–
PIN FUNCTION DESCRIPTIONS (continued)
Pin
No. Mnemonic Type Description
22 D9 DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
or SCLK When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
23 D10 DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
or SYNC When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output
frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When
a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains
HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is
HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid.
24 D11 DO When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is
used as an incomplete read error flag. In Slave Mode, when a data read is started and not
complete when the following conversion is complete, the current data is lost and RDERROR is
pulsed HIGH.
25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regard-
less of the state of SER/PAR.
29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data-ready clock signal.
30 DGND P Must Be Tied to Digital Ground
31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled. CS is also used to gate the external clock.
33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7660. Current conversion, if any, is aborted.
34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t
8
) is complete, the next
falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a
conversion. This mode is the most appropriate if low sampling jitter is desired. If CNVST is
LOW when the acquisition phase (t
8
) is complete, the internal sample-and-hold is put into the
hold state and a conversion is immediately started.
36 AGND P Must Be Tied to Analog Ground
37 REF AI Reference Input Voltage
38 REFGND AI Reference Input Analog Ground
39 INGND AI Analog Input Ground
43 IN AI Primary Analog Input with a Range of 0 V to V
REF
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
EPAD
Exposed Pad. The EPAD is connected to ground; however, this connection is not required to meet
specified performance.
REV. E
AD7660
–7–
DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code from
a line drawn from “negative full scale” through “positive full
scale.” The point used as negative full scale occurs 1/2 LSB before
the first code transition. Positive full scale is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It is
often specified in terms of resolution for which no missing codes
are guaranteed.
Full-Scale Error
The last transition (from 011 . . . 10 to 011 . . . 11 in twos
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.49994278 V for the 0 V–2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.
Unipolar Zero Error
The first transition should occur at a level 1/2 LSB above analog
ground (19.073 mV for the 0 V–2.5 V range). Unipolar zero error is
the deviation of the actual transition from that point.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/[N+D] by the following formula:
ENOB = S/ N + D dB
[]
()
–. /.176 602
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
The time required for the AD7660 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Overvoltage Recovery
The time required for the ADC to recover to full accuracy after
an analog input signal 150% of full-scale is reduced to 50% of
the full-scale value.
REV. E
AD7660
–8–
–Typical Performance Characteristics
CODE
–3 0
INL – LSB
16384
–2
–1
0
1
2
3
32768 49152 65536
TPC 1. Integral Nonlinearity
vs. Code
CODE
–1.00 0
DNL – LSB
16384
0.00
32768 49152 65536
–0.75
0.50
1.00
1.75
1.50
1.25
0.75
0.25
–0.50
–0.25
TPC 4. Differential Nonlinearity
vs. Code
FREQUENCY – kHz
01020304050
AMPLITUDE – dB of Full Scale
–180
–120
–40
0
–80
–140
–60
–20
–100
–160
4096 POINT FFT
f
S
= 100kHz
f
IN
= 45kHz
SNR = 90.14dB
SINAD = 89.94dB
THD = –101.37dB
SFDR = 110dB
TPC 7. FFT Plot
POSITIVE INL – LSB
00
NUMBER OF UNITS
0.6
5
10
15
20
25
30
1.2 1.8 2.4 3.0
TPC 2. Typical Positive INL
Distribution (350 Units)
NEGATIVE INL – LSB
00
NUMBER OF UNITS
–0.6
5
10
15
20
25
30
–1.2–1.8–2.4–3.0
35
TPC 5. Typical Negative INL
Distribution (350 Units)
–130 1
THD, HARMONICS – dB
10 100 1000
–90
–80
–60
–70
–100
–120
–110
SFDR
THD
60
SFDR – dB
90
100
120
110
80
70
SECOND HARMONIC
THIRD HARMONIC
FREQUENCY – kHz
TPC 8. THD, Harmonics, and SFDR
vs. Frequency
CODE – Hex
0
COUNTS
8008
8000
7000
6000
5000
4000
3000
2000
1000
0
8009
800A
800B
800C
800D
800E
800F
8010
8011
013 9 0 0
879
1213
7051
7219
TPC 3. Histogram of 16,384
Conversions of a DC Input
at the Code Transition
CODE – Hex
0
COUNTS
10000
8000
6000
4000
0
8009
800A
800B
800C
800D
800E
800F
8010
8011
0188 00
161
2000
9026
3520
3489
TPC 6. Histogram of 16,384
Conversions of a DC Input
at the Code Center
INPUT LEVEL – dB
–140
–90
THD, HARMONICS – dB
–90
–80
–60
–70
–100
–120
–110 THD
SECOND HARMONIC
THIRD HARMONIC
–80 0–10–20–30–40–50–60–70
–130
TPC 9. THD, Harmonics vs.
Input Level
REV. E
AD7660
–9–
FREQUENCY – Hz
1
SNR AND S/(N+D) – dB
10 100 1k
SNR
S/(N+D)
13.0
ENOB – Bits
14.5
15.0
16.0
15.5
14.0
13.5
70
85
90
100
95
80
75
ENOB
TPC 10. SNR, S/(N+D), and ENOB
vs. Frequency
SAMPLING RATE – SPS
10M
0.1
OPERATING CURRENTS – nA
1M
100k
10k
1k
100
10
1110100 1k 10k 100k 1M
AVD D
DVDD
OVDD
TPC 13. Operating Currents
vs. Sample Rate
C
L
– pF
0
t12
DELAY – ns
50 100 200
0
20
30
50
40
10
150
OVDD @ 2.7V, 85C
OVDD @ 2.7V, 25C
OVDD @ 5V, 85C
OVDD @ 5V, 25C
TPC 12. Typical Delay vs. Load
Capacitance C
L
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (C)
ZERO ERROR, FULL SCALE ERROR (LSB)
FULL SCALE ERROR
ZERO ERROR
TPC 15. Zero Error, Full Scale vs.
Temperature
INPUT LEVEL – dB
–50
SNR (REFERRED TO FULL SCALE) – dB
–40 –20 0
86
90
92
88
–30 –10
TPC 11. SNR vs. Input Level
(Referred to Full Scale)
TEMPERATURE – C
–10
–40
POWER-DOWN OPERATING CURRENTS – nA
10 60 110
50
60
100
80
20
0
10
–15 35 85
30
40
70
90
DVDD
AVD D
OVDD
TPC 14. Power-Down Operating
Currents vs. Temperature
REV. E
AD7660
–10–
CIRCUIT INFORMATION
The AD7660 is a fast, low power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7660 is capable of
converting 100,000 samples per second (100 kSPS) and allows
power saving between conversions. When operating at 100 SPS,
for example, it consumes typically only 21 mW. This feature
makes the AD7660 ideal for battery-powered applications.
The AD7660 provides the user with an on-chip track-and-
hold, successive-approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7660 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package or a 48-lead LFCSP package that com-
bines space savings and allows flexible configurations as either
serial or parallel interface. The AD7660 is pin-to-pin compatible
with the AD7664.
CONVERTER OPERATION
The AD7660 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
LSB capacitor. The comparator’s negative input is connected to
a “dummy” capacitor of the same value as the capacitive
DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SW
A
. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling capaci-
tor and acquires the analog signal on IN input. Similarly, the
dummy capacitor acquires the analog signal on the INGND input.
When the acquisition phase is complete and the CNVST input
goes or is LOW, a conversion phase is initiated. When the con-
version phase begins, SW
A
and SW
B
are opened first. The
capacitor array and the dummy capacitor are then disconnected
from the inputs and connected to the REFGND input. There-
fore, the differential voltage between IN and INGND captured
at the end of the acquisition phase is applied to the comparator
inputs, causing the comparator to become unbalanced.
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (V
REF
/2, V
REF
/4 . . . V
REF
/65536). The control logic toggles
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition. After the comple-
tion of this process, the control logic generates the ADC output
code and brings BUSY output LOW.
SWA
COMP
SWB
IN
REF
REFGND
LSBLSBMSB
32768C
INGND
16384C 4C 2C C
65536C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
C
Figure 3. ADC Simplified Schematic
REV. E
AD7660
–11–
100nF
10F100nF 10F
AVDD
10F100nF
AGND DGND DVDD OVDD OGND
CS
RD
SER/PAR
CNVST
BUSY
SDOUT
SCLK
RESETPD
IN
INGND
NOTE 2 U1
REFGND
CREF
NOTE 1
2.5V REF
NOTE 1 REF
100
D
NOTE 3
CLOCK
AD7660
ANALOG INPUT
(0V TO 2.5V)
C/P/DSP
SERIAL
PORT
DIGITAL SUPPLY
(3.3V OR 5V)
ANALOG
SUPPLY
(5V)
DVDD
OB/2C
NOTES
1. WITH THE AD780 OR THE ADR291 VOLTAGE REFERENCE, CREF IS 47F,
SEE VOLTAGE REFERENCE INPUT SECTION.
2. THE OP184 IS RECOMMENDED.
3. OPTIONAL LOW JITTER CNVST.
Figure 5. Typical Connection Diagram
Transfer Functions
Using the OB/2C digital input, the AD7660 offers two output
codings: straight binary and twos complement. The LSB size is
V
REF
/65536, which is about 38.15 mV. The ideal transfer charac-
teristic for the AD7660 is shown in Figure 4 and Table II.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE – Straight Binary
ANALOG INPUT
V
REF
–1.5 LSB
V
REF
–1 LSB
1 LSB0V
0.5 LSB
1 LSB = V
REF
/65536
Figure 4. ADC Ideal Transfer Function
Table II. Output Codes and Ideal Input Voltages
Digital Output Code (Hex)
Analog Straight Twos
Description Input Binary Complement
FSR – 1 LSB 2.499962 V FFFF
1
7FFF
1
FSR – 2 LSB 2.499923 V FFFE 7FFE
Midscale + 1 LSB 1.250038 V 8001 0001
Midscale 1.25 V 8000 0000
Midscale – 1 LSB 1.249962 V 7FFF FFFF
–FSR + 1 LSB 38 mV0001 8001
–FSR 0 V 0000
2
8000
2
NOTES
1
This is also the code for overrange analog input (V
IN
– V
INGND
above
V
REF
– V
REFGND
).
2
This is also the code for underrange analog input (V
IN
below V
INGND
).
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7660.
REV. E
AD7660
–12–
Analog Input
Figure 6 shows an equivalent circuit of the input structure of the
AD7660.
C2
R1
D1
D2
C1
IN
OR INGND
AGND
AVDD
Figure 6. Equivalent Analog Input Circuit
The two diodes D1 and D2 provide ESD protection for the
analog inputs IN and INGND. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more than
0.3 V. This will cause these diodes to become forward-biased and
start conducting current. These diodes can handle a forward-
biased current of 100 mA maximum. For instance, these
conditions could eventually occur when the input buffer’s (U1)
supplies are different from AVDD. In such cases, an input buffer
with a short circuit current limitation can be used to protect the part.
This analog input structure allows the sampling of the differential
signal between IN and INGND. Unlike other converters, the
INGND input is sampled at the same time as the IN input. By
using this differential input, small signals common to both inputs
are rejected as shown in Figure 7, which represents the typical
CMRR over frequency. For instance, by using INGND to sense
a remote signal ground, difference of ground potentials between
the sensor and the local ADC ground is eliminated.
FREQUENCY – Hz
CMRR – dB
45
75
10k 10M1k 1M
80
65
100k
55
85
70
60
50
40
Figure 7. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog input
IN can be modeled as a parallel combination of capacitor C1 and
the network formed by the series connection of R1 and C2.
Capacitor C1 is primarily the pin capacitance. The resistor R1 is
typically 3242 W and is a lumped component made up of some
serial resistors and the on resistance of the switches. The capacitor
C2 is typically 60 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened, the
input impedance is limited to C1. It has to be noted that the input
impedance of the AD7660, unlike other SAR ADCs, is not a pure
capacitance and thus, inherently reduces the kickback transient at
the beginning of the acquisition phase. The R1, C2 makes a one-
pole low-pass filter with a typical cutoff frequency of 820 kHz that
reduces undesirable aliasing effect and limits the noise.
When the source impedance of the driving circuit is low, the
AD7660 can be driven directly. Large source impedances will
significantly affect the ac performances, especially the total
harmonic distortion (THD). The maximum source impedance
depends on the amount of THD that can be tolerated. The
THD degrades in function of the source impedance and the
maximum input frequency as shown in Figure 8.
INPUT FREQUENCY – kHz
–100
1 10010
THD – dB
–95
–90
–85
–80
–75
–70
RS = 500
RS = 100
RS = 50
RS = 20
Figure 8. THD vs. Analog Input Frequency and
Source Resistance
Driver Amplifier Choice
Although the AD7660 is easy to drive, the driver amplifier needs
to meet at least the following requirements:
•
The driver amplifier and the AD7660 analog input circuit
must be able, together, to settle for a full-scale step of
the capacitor array at a 16-bit level (0.0015%). For
instance, operation at the maximum throughput of 100 kSPS
requires a minimum gain bandwidth product of 5 MHz.
•
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7660. The noise
coming from the driver is filtered by the AD7660 analog
input circuit one-pole low-pass filter made by R1 and C2.
For instance, a driver with an equivalent input noise of
4 nV/÷Hz like the OP184 and configured as a buffer, thus
with a noise gain of +1, degrades the SNR by only 0.1 dB.
•
The driver needs to have a THD performance suitable to
that of the AD7660. TPC 8 gives the THD versus frequency
that the driver should preferably exceed.
The SNR degradation due to the amplifier is:
SNR
fNe
LOSS
dB N
=
+
Ê
Ë
Á
Á
Á
Á
ˆ
¯
˜
˜
˜
˜
20 28
784 23
2
log
()
–
p
where:
f
–3 dB
is the –3 dB input bandwidth in MHz of the AD7660
(0.82 MHz) or the cutoff frequency of the input filter if any
are used.
N is the noise factor of the amplifier (1 if in buffer configuration).
e
N
is the equivalent input noise voltage of the op amp in
nV/÷Hz.
REV. E
AD7660
–13–
The AD8519, OP162, or the OP184 meet these requirements
and are usually appropriate for almost all applications. As an
alternative, in very high speed and noise-sensitive applications,
the AD8021 with an external compensation capacitor of 10 pF
or the AD829 with an external compensation capacitor of 82 pF
can be used. This capacitor should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
+1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.
Voltage Reference Input
The AD7660 uses an external 2.5 V voltage reference.
The voltage reference input REF of the AD7660 has a dynamic
input impedance; it should therefore be driven by a low impedance
source with an efficient decoupling between REF and REFGND
inputs. This decoupling depends on the choice
of the voltage
reference but usually consists of a 1 mF
ceramic capacitor and a
low ESR tantalum capacitor connected to the REF and REFGND
inputs with minimum parasitic inductance. 47 mF is an appropriate
value for the tantalum capacitor when used with one of the
recommended reference voltages:
∑The low noise, low temperature drift ADR421 and AD780
voltage references
∑The low power ADR291 voltage reference
∑The low cost AD1582 voltage reference
For applications using multiple AD7660s, it is more effective to
buffer the reference voltage with a low noise, very stable op amp
like the AD8031.
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference that directly affects the full-scale
accuracy if this parameter matters. For instance, a ±15 ppm/∞C
tempco of the reference changes the full scale by ±1 LSB/∞C.
V
REF
, as mentioned in the specification table, could be increased
to AVDD – 1.85 V. The benefit here is the increased SNR
obtained as a result of this increase. Since the input range is
defined in terms of V
REF
, this would essentially increase the
range to make it a ±3 V input range with an AVDD above 4.85 V.
The theoretical improvement as a result of this increase in
reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical
quantization noise, however, the observed improvement is
approximately 1 dB. The AD780 can be selected with a 3 V
reference voltage.
Power Supply
The AD7660 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.7 V and 5.25 V.
To reduce the number of supplies needed, the digital core
(DVDD) can be supplied through a simple RC filter from the
analog supply, as shown in Figure 5. The AD7660 is independent
of power supply sequencing and thus free from supply voltage
induced latch-up. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 9.
INPUT FREQUENCY – Hz
PSRR – dB
–80
1k 10k 100k 1M
–75
–70
–65
–60
–55
–50
Figure 9. PSRR vs. Frequency
POWER DISSIPATION VS. THROUGHPUT
The AD7660 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows a significant
power saving when the conversion rate is reduced, as shown in
Figure 10. This feature makes the AD7660 ideal for very low
power battery applications. It should be noted that the digital
interface remains active even during the acquisition phase. To
reduce the operating digital supply currents even further, the
digital inputs need to be driven close to the power rails (i.e.,
DVDD and DGND for all inputs except EXT/INT, INVSYNC,
INVSCLK, RDC/SDIN, and OVDD or OGND for the last
four inputs.
THROUGHPUT – SPS
10 100000
POWER DISSIPATION – W
100000
1000
10000
100
1
10
100 1000 10000
Figure 10. Power Dissipation vs. Sample Rate
REV. E
AD7660
–14–
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7660 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The CNVST signal operates independently of
CS and RD signals.
CNVST
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7 t8
ACQUIRE CONVERT ACQUIRE CONVERT
Figure 11. Basic Conversion Timing
For a true sampling application, the recommended operation of
the CNVST signal is the following:
CNVST must be held HIGH from the previous falling edge
of BUSY, and during a minimum delay corresponding to the
acquisition time t
8
; then, when CNVST is brought LOW, a
conversion is initiated and the BUSY signal goes HIGH until
the completion of the conversion. Although CNVST is a digital
signal, it should be designed with special care with fast, clean
edges and levels, with minimum overshoot and undershoot or
ringing. For applications where the SNR is critical, the CNVST
signal should have a very low jitter. This may be achieved by
using a dedicated oscillator for CNVST generation or, at least,
to clock it with a high frequency low jitter clock, as shown in
Figure 5.
t
9
t
8
RESET
DATABUS
BUSY
CNVST
Figure 12. RESET Timing
For other applications, conversions can be automatically initiated.
If CNVST is held LOW when BUSY is LOW, the AD7660
controls the acquisition phase and then automatically initiates a
new conversion. By keeping CNVST LOW, the AD7660 keeps
the conversion process running by itself. It should be noted that
the analog input has to be settled when BUSY goes LOW. Also,
at power-up, CNVST should be brought LOW once to initiate
the conversion process. In this mode, the AD7660 could some-
times run slightly faster than the guaranteed limit of 100 kSPS.
DIGITAL INTERFACE
The AD7660 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7660 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7660
to the host system interface digital supply. Finally, by using the
OB/2C input pin, both twos complement or straight binary
coding can be used.
The two signals CS and RD control the interface. CS and RD
have a similar effect because they are together internally. When
at least one of these signals is HIGH, the interface outputs are
in high impedance. Usually, CS allows the selection of each
AD7660 in multicircuit applications and is held LOW in a
single AD7660 design. RD is generally used to enable the con-
version result on the data bus.
t1
t3
t4
t11
CNVST
BUSY
D
ATA BUS
CS = RD = 0
t10
PREVIOUS CONVERSION DATA NEW DATA
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
PARALLEL INTERFACE
The AD7660 is configured to use the parallel interface when the
SER/PAR is held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or during
the following conversion as shown, respectively, in Figures 14 and
15. When the data is read during the conversion, however, it is
recommended that it is read-only during the first half of the
conversion phase. This avoids any potential feedthrough between
voltage transients on the digital interface and the most critical
analog conversion circuitry.
CURRENT
CONVERSION
BUSY
DATA BUS
CS
RD
t12 t13
Figure 14. Slave Parallel Data Timing for Reading
(Read after Convert)
REV. E
AD7660
–15–
PREVIOUS
CONVERSION
t
1
t
3
t
12
t
13
t
4
CS = 0
CNVST,
RD
BUSY
DATA BUS
Figure 15. Slave Parallel Data Timing for Reading
(Read during Convert)
SERIAL INTERFACE
The AD7660 is configured to use the serial interface when the
SER/PAR is held HIGH. The AD7660 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7660 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. The AD7660
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. The output data is valid on both the
rising and falling edge of the data clock. Depending on RDC/
SDIN input, the data can be read after each conversion or during
the following conversion. Figures 16 and 17 show the detailed timing
diagrams of these two modes.
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
123 141516
D15 D14 D2 D1 D0
X
EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
25
t
30
Figure 16. Master Serial Data Timing for Reading (Read after Convert)
EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0
t3
t1
t17
t14 t19
t20 t21 t24 t26
t25
t27
t23
t22
t16
t15
D15 D14 D2 D1 D0X
12 3 141516
t18
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
REV. E
AD7660
–16–
Usually, because the AD7660 has a longer acquisition phase
than the conversion phase, the data is read immediately after
conversion. This makes the Master Read after conversion the
most recommended Serial Mode when it can be used. In this
mode, it should be noted that, unlike in other modes, the signal
BUSY returns LOW after the 16 data bits are pulsed out and
not at the end of the conversion phase, which results in a longer
BUSY width.
In Read-during-Conversion Mode, the serial clock and data
toggle at appropriate instants, which minimizes potential
feedthrough between digital activity and the critical conversion
decisions.
SLAVE SERIAL INTERFACE
External Clock
The AD7660 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/INT pin is held
HIGH. In this mode, several methods can be used to read the
data. When CS and RD are both LOW, the data can be read
after each conversion or during the following conversion. The
external clock can be either a continuous or discontinuous clock.
A discontinuous clock can be either normally HIGH or normally
LOW when inactive. Figures 18 and 20 show the detailed timing
diagrams of these methods. Usually, because the AD7660 has a
longer acquisition phase than the conversion phase, the data are
read immediately after conversion.
While the AD7660 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is par-
ticularly important during the second half of the conversion
phase because the AD7660 provides error correction circuitry that
can correct for an improper bit decision made during the first half
of the conversion phase. For this reason, it is recommended
that when an external clock is being provided, it is a discon-
tinuous clock that is toggling only when BUSY is LOW or, more
importantly, that it does not transition during the latter half of
BUSY HIGH.
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 18 shows the detailed timing diagrams of this method. After
a conversion is complete, indicated by BUSY returning LOW,
the result of this conversion can be read while both CS and RD are
LOW. The data is shifted out, MSB first, with 16 clock pulses and
is valid on both the rising and falling edge of the clock.
Among the advantages of this method, the conversion performance
is not degraded because there are no voltage transients on the
digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 40 MHz, which accommodates both slow digital host inter-
face and the fastest serial reading.
Finally, in this mode only, the AD7660 provides a “daisy-chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when it is desired as it is, for
instance, in isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift out
the data on SDOUT. Therefore, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter on
the next SCLK cycle. Up to 20 AD7660s running at 100 kSPS
can be daisy-chained using this method.
SCLK
SDOUTRDC/SDIN
BUSYBUSY
DATA OUT
AD7660
#1
(DOWNSTREAM)
BUSY OUT
CNVST
CS
SCLK
AD7660
#2
(UPSTREAM)
RDC/SDIN SDOUT
SCLK IN
CS IN
CNVST IN
CNVST
CS
Figure 19. Two AD7660s in a Daisy-Chain Configuration
SCLK
SDOUT D15 D14 D1 D0
D13
X15 X14 X13 X1 X0 Y15 Y14
CS
BUSY
SDIN
EXT/INT = 1 INVSCLK = 0
t35
t36 t37
t31 t32
t16
t33
X15 X14
X
123 14151617 18
RD = 0
t34
Figure 18. Slave Serial Data Timing for Reading (Read after Convert)
REV. E
AD7660
–17–
External Clock Data Read during Conversion
Figure 20 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are LOW, the
result of the previous conversion can be read. The data is shifted
out, MSB first, with 16 clock pulses, and is valid on both the
rising and falling edges of the clock. The 16 bits have to be read
before the current conversion is complete; this, otherwise,
RDERROR is pulsed HIGH and can be used to interrupt the host
interface to prevent incomplete data reading. There is no daisy-
chain feature in this mode, and RDC/SDIN input should always
be tied either HIGH or LOW.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 18 MHz is recommended to ensure
that all the bits are read during the first half of the conversion
phase. For this reason, this mode is more difficult to use.
MICROPROCESSOR INTERFACING
The AD7660 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal pro-
cessing applications interfacing to a digital signal processor.
The AD7660 is designed to interface either with a parallel 8-bit or
16-bit wide interface, or with a general-purpose serial port or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7660 to prevent digital noise from coupling
into the ADC. The following section discusses the use of an
AD7660 with an ADSP-219x SPI equipped DSP.
SDOUT
CS
SCLK
D1 D0
XD15 D14 D13
123 141516
t
3
t
35
t
36
t
37
t
31
t
32
t
16
CNVST
BUSY
EXT/INT = 1 INVSCLK = 0 RD = 0
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
SPI Interface (ADSP-219x)
Figure 21 shows an interface diagram between the AD7660 and
an SPI-equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7660 acts as a slave device and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command can be initiated in response
to an internal timer interrupt. The reading process cab be initi-
ated in response to the end-of-conversion signal (BUSY going
LOW) using an interrupt line of the DSP. The serial interface
(SPI) on the ADSP-219x is configured for master mode—
(MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit
(CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00— by
writing to the SPI control register (SPICLTx). To meet all
timing requirements, the SPI clock should be limited to 17
Mbps, which allows it to read an ADC result in less than 1 ms.
When a higher sampling rate is desired, use of one of the paral-
lel interface modes is recommended.
SPIxSEL (PFx)
ADSP-219x*
CNVST
AD7660*
CS
BUSY
MISOx
SCKx
PFx or TFSx
SDOUT
SCLK
RD
INVSCLK
EXT/INT
SER/PAR
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
PFx
Figure 21. Interfacing the AD7660 to an SPI Interface
REV. E
AD7660
–18–
APPLICATION HINTS
Bipolar and Wider Input Ranges
In some applications, it is desired to use a bipolar or wider
analog input range like, for instance, ±10 V, ±5 V, or 0 V to
5 V. Although the AD7660 has only one unipolar range, by simple
modifications of the input driver circuitry, bipolar and wider
input ranges can be used without any performance degradation.
Figure 22 shows a connection diagram that allows this. Compo-
nent values required and resulting full-scale ranges are shown in
Table III.
U1
2.5V REF
ANALOG
INPUT
R2
R3 R4 100nF
R1
C
F
U2
C
REF
IN
INGND
REF
REFGND
100nF
AD7660
Figure 22. Using the AD7660 in 16-Bit Bipolar and/or
Wider Input Ranges
Table III. Component Values and Input Ranges
Input Range R1 (kW)R2 (
k
W)R3 (
k
W)R4 (
k
W)
±10 V 1 8 10 8
±5 V 1 4 10 6.67
0 V to –5 V 1 2 None 0
For bipolar range applications where accurate gain and offset
are desired, they can be calibrated by acquiring a ground and a
voltage reference using an analog multiplexer U2, as shown in
Figure 22. Also, C
F
can be used as a one-pole antialiasing filter.
Layout
The AD7660 has very good immunity to noise on the power
supplies as can be seen in Figure 9. However, care should still
be taken with regard to grounding layout.
The printed circuit board that houses the AD7660 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. Digital and ana-
log ground planes should be joined in only one place,
preferably underneath the AD7660, or, at least, as close as
possible to the AD7660. If the AD7660 is in a system where
multiple devices require analog to digital ground connections,
the connection should still be made at one point only, a star
ground point that should be established as close as possible to
the AD7660.
It is recommended to avoid running digital lines under the device
as these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7660 to avoid noise
coupling. Fast switching signals like CNVST or clocks should
be shielded with digital ground to avoid radiating noise to other
sections of the board and should never run near analog signal
paths. Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run at right
angles to each other. This will reduce the effect of feedthrough
through the board.
The power supply lines to the AD7660 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the supply’s impedance presented to the
AD7660 and to reduce the magnitude of the supply spikes.
Decoupling ceramic capacitors, typically 100 nF, should be placed
on each power supply pins AVDD, DVDD, and OVDD close to,
and ideally right up against, these pins and their corresponding
ground pins. Additionally, low ESR 10 mF capacitors should
be located in the vicinity of the ADC to further reduce low
frequency ripple.
The DVDD supply of the AD7660 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, it is recom-
mended if no separate supply is available, to connect the DVDD
digital supply to the analog supply AVDD through an RC filter as
shown in Figure 6 and to connect the system supply to the interface
digital supply OVDD and the remaining digital circuitry. When
DVDD is powered from the system supply, it is useful to insert
a bead to further reduce high frequency spikes.
The AD7660 has five different ground pins: INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the
analog input signal. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must be
connected with the least resistance to the analog ground plane.
DGND must be tied to the analog or digital ground plane depend-
ing on the configuration. OGND is connected to the digital
system ground.
REV. E
AD7660
–19–
OUTLINE DIMENSIONS
COM PL IANT TO JEDEC STANDARDS M S -026- BBC
TOP VIE W
(PINS DOWN)
1
12 13 25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD P IT CH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
RO TATE D 90 ° CC W
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
9.20
9.00 SQ
8.80
7.20
7.00 S Q
6.80
051706-A
Figure 40. 48-Lead Plastic Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
112408-B
FO R PRO P ER CO NNECT ION O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COM PL IANT T O JEDE C ST ANDARDS MO-220-W KKD .
1
0.50
BSC
BOTTOM VI EW
TO P VI EW
PIN 1
INDICATOR
7.00
BSC SQ
48
13
24
25
36
37
12
EXPOSED
PAD
PIN 1
INDICATOR
5.20
5.10 S Q
5.00
0.45
0.40
0.35
SEATING
PLANE
0.80
0.75
0.70 0.05 M AX
0.02 NOM
0.25 M I N
0.20 RE F
COPLANARITY
0.08
0.30
0.23
0.18
Figure 41. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 x 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
REV. E
–20–
AD7660
D01928-0-2/16(E)
Revision History
Location Page
10/03—Data Sheet changed from REV. C to REV. D.
Update format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Added PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Added Overvoltage Recovery section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Added TPC 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to CIRCUIT INFORMATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Renamed Table I to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Changes to Figure 5 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Changes to Figure 8 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Changes to Driver Amplifier Choise section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Replaced Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Changes to DIGITAL INTERFACE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Replaced Figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Deleted Figure 22 and renumbered successive figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Replaced MICROPROCESSOR INTERFACING section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Changes in Bipolar and Wider Input Ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Changes to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Added CP-48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Update OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1/02—Data Sheet changed from REV. B to REV. C.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to Driver Amplifier Choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
New Voltage Reference Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Edits to DIGITAL INTERFACE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
New ST-48 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9/01—Data Sheet changed from REV. A to REV. B.
Edit to Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edit to Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edit to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edit to TYPICAL PERFORMANCE CHARACTERISTICS graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 10
Edit to DRIVER AMPLIFIER CHOICE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Edit to Figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Edit to Figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Edit to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Edit to Bipolar and Wider Input Ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/16—Data Sheet changed from REV. D to REV. E.
Update OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Deleted Evaluating the AD7660 Performance Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
