Product Brief April 2003 MARS1G2 P-LT (TDAT161G2) SONET/SDH 155/622 Mbits/s Data Interface Features One of the next generation system on a chip devices of Agere Systems' multiapplication & rate solutions MARSTM family of framers. Transmission convergence and SONET/SDH terminal functionality for linear networks. Versatile IC supports 155/622 Mbits/s SONET/ SDH interface solutions for packet over SONET (POS), packet over fiber (POF), or asynchronous transfer mode (ATM) applications. Low-power 1.6/3.3 V operation. SONET/SDH Interface Termination of quad STS-3/STM-1 or dual STS-12/ STM-4. Supports overhead processing for transport and path overhead bytes. Optional insertion and extraction of overhead bytes via serial overhead interface. STS pointer processing to align the receive frame to the system frame. Support for 1+1 and 1:1 linear networks. Full path termination and SPE extraction/insertion. SONET/SDH compliant condition and alarm reporting. Handles all concatenation levels of STS-3c to STS-24c (in multiples of 3: e.g., 3c, 6c, 9c, etc.). Built-in diagnostic loopback modes. Compliant with the following Telcordia Technologies(R), ANSI(R), and ITU standards: -- GR-253 CORE: SONET Transport Systems: Common Generic Criteria. -- ITU-T G.707: Network Node Interface for the Synchronous Digital Hierarchy. -- ITU-T G.803: Architecture of Transport Networks Based on the Synchronous Digital Hierarchy. -- T1.105: SONET-Basic Description including Multiplex Structure, Rates, and Formats. -- T1.105.02 SONET-Payload Mappings. -- T1.105.03 SONET-Jitter at Network Interfaces. -- T1.105.06 SONET Physical Layer Specifications. -- T1.105.07 SONET-Sub-STS-1 Interface Rates and Formats Specification. -- ITU-T I.432: B-ISDN User-Network InterfacePhysical Layer Specification. -- IETF RFC 2615: PPP over SONET/SDH. -- IETF RFC 1661: The Point-to-Point Protocol (PPP). -- IETF RFC 1662: PPP in HDLC-like Framing. Data Processing Provisionable data engine supports payload insertion/extraction for PPP, ATM, or HDLC streams. Extraction and insertion of DS3 frames containing HDLC or ATM datastreams for up to 16 channels. Integrated UTOPIA Level 2 and Level 3 compatible physical layer interface for packets or ATM cells. Provides/supports internal E3 mapping. Supports DS3/PLCP and clear channel DS3 mapping. Insertion and extraction of up to 16 separate data channels. Direct cell/packet over fiber interface device. Compliant with ATM forum, ITU standards, and IETF standards. Interfaces Enhanced UTOPIA interface for cell and packet transfer. IEEE(R) 1149.1 port with BIST, scan, and boundry scan. Microprocessor Interface Up to 66 MHz synchronous. 16-bit address and 16-bit data interface. Synchronous or asynchronous modes available. Configurable to operate with most commercial microprocessors. MARS1G2 P-LT (TDAT161G2) SONET/SDH 155/622 Mbits/s Data Interface Product Brief April 2003 Description The MARS1G2 P-LT SONET/SDH interface device provides a versatile solution for quad OC-3 and dual OC-12 linear datacom/telecom applications. Constructed using COM2 CMOS modular process, this device incorporates integrated SONET/SDH framing, section/line/path termination, pointer processing, and data engine blocks. The device provides complete encapsulation and de-encapsulation for packet and ATM streams into and out of SONET/SDH payloads. Communication with the MARS1G2 P-LT device is accomplished through a generic microprocessor interface. The device supports separate address and data buses. With the MARS1G2 P-LT device, support for different types of applications for OC-3/OC-12 data equipment is possible, enabling dramatic system cost reduction and the ease of development of extremely competitive solutions. This device integrates the SONET/SDH network termination functions with a generic cell/packet delineation circuit. The interface rates supported are dual STS-12/STM-4 and quad STS-3/STM-1. The UTOPIA interface can process and hand off up to 16 channels transported within an STS-N payload. The concatenation levels supported by this device are STS-1, STS-3c, STS-6c, STS-9c, STS-12c, STS-15c, . . . , STS-21c, and STS-24c. The data formats processed by this device are ATM cells or HDLC framed packets such as PPP framed packets. DIRECT CELL/PACKET OVER FIBER DUAL STM-4/STS-12 OR QUAD STM-1/STS-3 TXB PT DS3 (SPE MPR) DE* OVERHEAD PROCESSOR MONITOR TXC TXD TRANSPORT OVERHEAD TERMINATION PACKET/CELL FIFOs POINTER PROCESSOR DUAL STM-4/STS-12 OR QUAD STM-1/STS-3 INTERFACE BLOCK TXCLK TXA OVERHEAD PROCESSOR INSERT UTOPIA INTERFACE RXA PT (PTR INTER) DS3 RXS RXB DE RXC RXD CONTROL MISCELLANEOUS DIRECT CELL/PACKET OVER FIBER TXTOAC RXTOAC MPU INTERFACE GPIO TOAC INTERFACE Note: PT = path terminator, RXS = receive sequencer, and DE = data engine. * In the transmit path the data engine performs packet/cell processing (encapsulation, scrambling). In the receive path the data engine performs packet/cell processing (delineation, descrambling, de-encapsulation). Figure 1. MARS1G2 P-LT Block Diagram 2 Agere Systems Inc. Product Brief April 2003 MARS1G2 P-LT (TDAT161G2) SONET/SDH 155/622 Mbits/s Data Interface Target Applications Supported MARS1G2 P-LT (792-Pin PBGA) This multirate/multiprotocol/multimode SONET/SDH data interface device targets the following applications see Figure 2 for device interface speed/rate information: Mixed ATM/POS-TDM. Access router and aggregation. Wireless, DSLAM, and gateway. LINE INTERFACE DUAL (1 x 622 Mbits/s LVPECL) or QUAD (1 x 155 Mbits/s LVPECL) PT DS3 (SPE MPR) OVERHEAD PROCESSOR MONITOR DUAL UL2+ DE TRANSPORT OVERHEAD TERMINATION PACKET/CELL FIFOs POINTER PROCESSOR TXCLK OVERHEAD PROCESSOR INSERT INTERFACE BLOCK DUAL (1 x 622 Mbits/s LVPECL) or QUAD (1 x 155 Mbits/s LVPECL) DIRECT CELL/PACKET OVER FIBER UTOPIA/DATA INTERFACE PT (PTR INTER) CONTROL DS3 RXS DE DUAL UL2+ MISCELLANEOUS DIRECT CELL/PACKET OVER FIBER TXTOAC RXTOAC MPU INTERFACE GPIO TOAC INTERFACE Figure 2. MARS1G2 P-LT Device Interface Speed/Rate Diagram Agere Systems Inc. 3 Telcordia Technologies is a trademark of Telcordia Technologies, Inc. ANSI is a registered trademark of American National Standards Institute, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. MARS is a trademark of Agere Systems Inc. Copyright (c) 2003 Agere Systems Inc. All Rights Reserved April 2003 PB03-089SONT