PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 1
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Based on DDR3-1066/1333 128Mx8 SDRAM C-Die
Features
•Performance:
Speed Sort
PC3-8500
PC3-10600
Unit
-BE
-CG
DIMM CAS Latency
7
9
fck – Clock Frequency
533
667
MHz
tck – Clock Cycle
1.875
1.5
ns
fDQ – DQ Burst Freqency
1066
1333
Mbps
• 240-Pin Dual In-Line Memory Module (UDIMM)
• 128Mx64 and 256Mx64 DDR3 Unbuffered DIMM based on
128Mx8 DDR3 SDRAM A-Die devices.
• Intended for 533MHz/667MHz applications
• Inputs and outputs are SSTL-15 compatible
• VDD = VDDQ = 1.5V ±0.075V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Nominal and Dynamic On-Die Termination support
• Halogen free product
• Programmable Operation:
- DIMM  Latency: 6,7,8,9
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
• Two different termination values (Rtt_Nom & Rtt_WR)
• 14/10/2 (row/column/rank) Addressing for 2GB
• Extended operating temperature rage
• Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
• SDRAMs are in 78-ball BGA Package
• RoHS compliance
Description
NT2GC64B8HC0NF is 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM),
organized as two ranks of 256Mx64 (2GB) high-speed memory array. Modules use sixteen 128Mx8 (2GB) 78-ball BGA packaged devices.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design
files minimizes electrical variation between suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte
interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of
1066Mbps/1333Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be programmed into the
DIMM by address inputs A0-A13 and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 2
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Ordering Information
Part Number
Speed
Power
Leads
Note
NT2GC64B8HC0NF-BE
DDR3-1066
PC3-8500
533MHz (1.875ns @ CL = 7)
1.5V
Gold
NT2GC64B8HC0NF-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
Pin Description
Pin Name
Description
Pin Name
Description
CK0, CK1
Clock Inputs, positive line
DQ0-DQ63
Data input/output
, 
Clock Inputs, negative line
DQS0-DQS8
Data strobes
CKE0, CKE1
Clock Enable
-
Data strobes complement

Row Address Strobe
DM0-DM8
Data Masks

Column Address Strobe

Temperature event pin

Write Enable

Reset pin
, 
Chip Selects
VREFDQ , VREFCA
Input/Output Reference
A0-A9, A11, A13
Address Inputs
VDDSPD
SPD and Temp sensor power
A10/AP
Address Input/Auto-Precharge
SA0, SA1
Serial Presence Detect Address Inputs
A12/
Address Input/Burst Chop
Vtt
Termination voltage
BA0-BA2
SDRAM Bank Address Inputs
VSS
Ground
ODT0, ODT1
Active termination control lines
VDD
Core and I/O power
SCL
Serial Presence Detect Clock Input
NC
No Connect
SDA
Serial Presence Detect Data input/output
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 3
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
DDR3 SDRAM Pin Assignment
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VREFDQ
121
VSS
31
DQ25
151
VSS
61
A2
181
A1
91
DQ41
211
VSS
2
VSS
122
DQ4
32
VSS
152
DM3
62
VDD
182
VDD
92
VSS
212
DM5
3
DQ0
123
DQ5
33

153
NC
63
CK1/NC
183
VDD
93

213
NC
4
DQ1
124
VSS
34
DQS3
154
VSS
64
/NC
184
CK0
94
DQS5
214
VSS
5
VSS
125
DM0
35
VSS
155
DQ30
65
VDD
185

95
VSS
215
DQ46
6

126
NC
36
DQ26
156
DQ31
66
VDD
186
VDD
96
DQ42
216
DQ47
7
DQS0
127
VSS
37
DQ27
157
VSS
67
VREFCA
187

97
DQ43
217
VSS
8
VSS
128
DQ6
38
VSS
158
NC
68
NC
188
A0
98
VSS
218
DQ52
9
DQ2
129
DQ7
39
NC
159
NC
69
VDD
189
VDD
99
DQ48
219
DQ53
10
DQ3
130
VSS
40
NC
160
VSS
70
A10/AP
190
BA1
100
DQ49
220
VSS
11
VSS
131
DQ12
41
VSS
161
DM8
71
BA0
191
VDD
101
VSS
221
DM6
12
DQ8
132
DQ13
42

162
NC
72
VDD
192

102

222
NC
13
DQ9
133
VSS
43
DQS8
163
VSS
73

193

103
DQS6
223
VSS
14
VSS
134
DM1
44
VSS
164
NC
74

194
VDD
104
VSS
224
DQ54
15

135
NC
45
NC
165
NC
75
VDD
195
ODT0
105
DQ50
225
DQ55
16
DQS1
136
VSS
46
NC
166
VSS
76

196
A13
106
DQ51
226
VSS
17
VSS
137
DQ14
47
VSS
167
NC
77
ODT1/NC
197
VDD
107
VSS
227
DQ60
18
DQ10
138
DQ15
48
NC
168

78
VDD
198
NC
108
DQ56
228
DQ61
19
DQ11
139
VSS
49
NC
169
CKE1/NC
79
NC
199
VSS
109
DQ57
229
VSS
20
VSS
140
DQ20
50
CKE0
170
VDD
80
VSS
200
DQ36
110
VSS
230
DM7
21
DQ16
141
DQ21
51
VDD
171
NC
81
DQ32
201
DQ37
111

231
NC
22
DQ17
142
VSS
52
BA2
172
NC
82
DQ33
202
VSS
112
DQS7
232
VSS
23
VSS
143
DM2
53
NC
173
VDD
83
VSS
203
DM4
113
VSS
233
DQ62
24

144
NC
54
VDD
174
A12/
84

204
NC
114
DQ58
234
DQ63
25
DQS2
145
VSS
55
A11
175
A9
85
DQS4
205
VSS
115
DQ59
235
VSS
26
VSS
146
DQ22
56
A7
176
VDD
86
VSS
206
DQ38
116
VSS
236
VDDSPD
27
DQ18
147
DQ23
57
VDD
177
A8
87
DQ34
207
DQ39
117
SA0
237
SA1
28
DQ19
148
VSS
58
A5
178
A6
88
DQ35
208
VSS
118
SCL
238
SDA
29
VSS
149
DQ28
59
A4
179
VDD
89
VSS
209
DQ44
119
SA2
239
VSS
30
DQ24
150
DQ29
60
VDD
180
A3
90
DQ40
210
DQ45
120
VTT
240
VTT
Note: CK1, , CKE1,  and ODT1 are for 2GB modules only.
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 4
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0, CK1
, 
Input
Cross
point
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
CKE0, CKE1
Input
Active
High
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
, 
Input
Active
Low
Enables the associated DDR3 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue, Rank 0 is selected by ; Rank 1 is selected by 
, , 
Input
Active
Low
When sampled at the positive rising edge of CK and falling edge of , signals , , 
define the operation to be executed by the SDRAM.
ODT0, ODT1
Input
Active
High
Asserts on-die termination for DQ, DM, DQS, and  signals if enabled via the DDR3 SDRAM
mode register.
DM0 – DM8
Input
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
DQS0 – DQS8
 – 
I/O
Cross
point
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.
 signals are complements, and timing is relative to the cross point of respective DQS and
. If the module is to be operated in single ended strobe mode, all  signals must be tied on
the system board to VSS and DDR3 SDRAM mode registers programmed appropriately.
BA0, BA1, BA2
Input
-
Selects which DDR3 SDRAM internal bank of four or eight is activated.
A0 – A9
A10/AP
A11
A12/
A13
Input
-
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
. In addition to the column address, AP is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
DQ0 – DQ63
Input
-
Data Input/Output pins.
VDD, VDDSPD, VSS
Supply
-
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
VREFDQ, VREFCA
Supply
-
Reference voltage for SSTL15 inputs
SDA
I/O
-
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull
up.
SCL
Input
-
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
SA0 – SA2
Input
-
Address pins used to select the Serial Presence Detect and Temp sensor base address.

Output
-
The  pin is reserved for use to flag critical module temperature.

Input
-
This signal resets the DDR3 SDRAM
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 5
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram
[2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]

DM1

DQ8
DQ9
DQ10
DQ15
DQ12
DQ14
DQ13
DQ11

DQ16
DQ17
DQ18
DQ23
DQ20
DQ22
DQ21
DQ19
DM2

DQ24
DQ25
DQ26
DQ31
DQ28
DQ30
DQ29
DQ27
DM3
DM0

DQ0
DQ1
DQ2
DQ7
DQ4
DQ6
DQ5
DQ3
DM5

DQS5
DQ40
DQ41
DQ42
DQ47
DQ44
DQ46
DQ45
DQ43 D5
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
DM6
DQS6
DQS6
DQ48
DQ49
DQ50
DQ55
DQ52
DQ54
DQ53
DQ51 D6
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
DM7

DQ56
DQ57
DQ58
DQ63
DQ60
DQ62
DQ61
DQ59 D7
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
DQS4
DQ32
DQ33
DQ34
DQ39
DQ36
DQ38
DQ37
DQ35 D4
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM

DM4
D1
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D2
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D3
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
CS DQSDQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D9
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D10
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D11
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D8
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D13
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D14
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D15
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D12
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM

DQS0
DQS1
DQS2
DQS3
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
DQS7
ZQ ZQ ZQ ZQ
ZQ ZQ ZQ ZQ
ZQ ZQ ZQ ZQ
ZQZQ
ZQ
ZQ
DDR3
SDRAM
VTT
CKE[1:0], A[13:0],
, , ,
ODT[1:0], BA[2:0],
[1:0]
DDR3
SDRAM
VDD
CK

VDDSPD
VSS
VREFDQ
VREFCA
VDD/VDDQ
SPD
D0-D15
D0-D15
D0-D15
BA0-BA2 D0-D15
BA0-BA2: SDRAMs D0-D15
A0-A13


CKE0

ODT0
A0-A13: SDRAMs D0-D15
: SDRAMs D0-D15
: SDRAMs D0-D15
ODT: SDRAMs D0-D7
: SDRAMs D0-D15
CKE: SDRAMs D0-D7
CK0 CK: SDRAMs D0-D7
 : SDRAMs D0-D7
 : SDRAMs D8-D15
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ
resistor is 240Ω±1%.
4. One SPD exists per module.
SPD
SCL
WP
SCL
SDA
SA0
SA1 A0
A1
A2
D0
CKE1 CKE: SDRAMs D8-D15
ODT1 ODT: SDRAMs D8-D15
CK1 CK: SDRAMs D8-D15
 : SDRAMs D8-D15
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 6
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Serial Presence Detect (Part 1 of 2) [2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data
Entry (Hex.)
-BE
-CG
-BE
-CG
0
CRC range, EEPROM bytes, bytes used
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
92
92
1
SPD revision
Revision 1.0
Revision 1.0
10
10
2
DRAM device type
DDR3 SDRAM
DDR3 SDRAM
0B
0B
3
Module type (form factor)
UDIMM
UDIMM
02
02
4
SDRAM Device density and banks
8 banks, 1Gb
8 banks, 1Gb
02
02
5
SDRAM device row and column count
14 rows, 10 columns
14 rows, 10 columns
11
11
6
Module minimum nominal voltage
1.5 V
1.5 V
00
00
7
Module ranks and device DQ count
2 ranks, 8 bits
2 ranks, 8 bits
09
09
8
ECC tag and module memory Bus width
Non ECC, 64bits
Non ECC, 64bits
03
03
9
Fine timebase dividend/divisor (in ps)
2.5ps
2.5ps
52
52
10
Medium timebase dividend
1ns
1ns
01
01
11
Medium timebase divisor
8ns
8ns
08
08
12
Minimum SDRAM cycle time (tCKmin)
1.875ns
1.5ns
0F
0C
13
Reserved
Undefined
Undefined
00
00
14
CAS latencies supported
6,7,8
6,7,8,9
1C
3C
15
CAS latencies supported
Undefined
Undefined
00
00
16
Minimum CAS latency time (tAAmin)
13.125ns
13.125ns
69
69
17
Minimum write recovery time (tWRmin)
15ns
15ns
78
78
18
Minimum -to- delay (tRCDmin)
13.125ns
13.125ns
69
69
19
Minimum Row Active to Row Active delay
(tRRDmin)
7.5ns
6ns
3C
30
20
Minimum row Precharge delay (tRPmin)
13.125ns
13.125ns
69
69
21
Upper nibble for tRAS and tRC
1,1
1,1
11
11
22
Minimum Active-to-Precharge delay (tRASmin)
37.5ns
36ns
2C
20
23
Minimum Active-to-Active/Refresh delay (tRCmin)
50.625ns
49.125ns
95
89
24
Minimum refresh recovery delay (tRFCmin) LSB
(Combo bytes 24,25)
(Combo bytes 24,25)
70
70
25
Minimum refresh recovery delay (tRFCmin) MSB
110ns
110ns
03
03
26
Minimum internal Write-to-Read command delay
(tWTRmin)
7.5ns
7.5ns
3C
3C
27
Minimum internal Read-to-Precharge command
delay (tRTPmin)
7.5ns
7.5ns
3C
3C
28
Minimum four active window delay (tFAWmin) LSB
(Combo byte 28, 29)
(Combo byte 28, 29)
01
00
29
Minimum four active window delay (tFAWmin)
MSB
37.5ns
30ns
2C
F0
30
SDRAM device output drivers suported
RZQ / 7,
DLL-Off Mode Support,
RZQ / 7,
DLL-Off Mode Support,
82
82
31
SDRAM device thermal and refresh options
Extended Temperature Range,
ASR,
Extended Temperature Range,
ASR,
05
05
32
Module thermal sensor
Non Thermal Sensor Support
Non Thermal Sensor Support
00
00
33
SDRAM device type
Standard Monolithic Device
Standard Monolithic Device
00
00
34-59
Reserved
Undefined
Undefined
--
--
60
Module height (nominal)
29 ＜ height ≦ 30 mm
29 ＜ height ≦ 30 mm
0F
0F
61
Module thickness (Max)
Back: 1 < thickness ≤ 2 mm,
Front: 1 < thickness ≤ 2 mm,
Back: 1 < thickness ≤ 2 mm,
Front: 1 < thickness ≤ 2 mm,
11
11
62
Raw Card ID reference
Raw Card B
Raw Card B
01
01
63
DRAM address mapping edge connector
Undefined
Undefined
01
01
64-116
Reserved
Undefined
Undefined
--
--
117-118
Module manufacture ID
Nanya Technology
Nanya Technology
830B
830B
119-125
Module information
Undefined
Undefined
--
--
126-127
CRC
Calculated Value
Calculated Value
4408
06A1
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 7
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Serial Presence Detect (Part 2 of 2) [2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
-BE
-CG
-BE
-CG
128-145
Module part number
ASCII values
ASCII values
--
--
146
Module die revision
Undefined
Undefined
00
00
147
Module PCB revision
Undefined
Undefined
00
00
148-149
DRAM device
manufacturer ID
Nanya Technology
Nanya Technology
830B
830B
150-175
Manufacturer reserved
Undefined
Undefined
--
--
176-255
Customer reserved
Undefined
Undefined
--
--
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 8
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Environmental Requirements
Symbol
Parameter
Rating
Units
Note
TOPR
Module Operating Temperature Range (ambient)
0 to 55
°C
3
HOPR
Operating Humidity (relative)
10 to 90
%
1
TSTG
Storage Temperature (Plastic)
-55 to 100
°C
1
HSTG
Storage Humidity (without condensation)
5 to 95
%
1
PBAR
Barometric Pressure (operating & storage)
105 to 69
K Pascal
1, 2
Note:
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. Up to 9850 ft.
3. The component maximum case temperature shall not exceed the value specified in the component spec.
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Note
VDD
Voltage on VDD pins relative to Vss
-0.4 V ~ 1.975 V
V
1, 3
VDDQ
Voltage on VDDQ pins relative to Vss
-0.4 V ~ 1.975 V
V
1, 3
VIN, VOUT
Voltage on I/O pins relative to Vss
-0.4 V ~ 1.975 V
V
1
TSTG
Storage Temperature
-55 to +100
°C
1, 2
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREF must be not greater
Operating temperature Conditions
Symbol
Parameter
Rating
Units
Note
TOPER
Normal Operating Temperature Range
0 to 85
°C
1, 2
Extended Temperature Range
85 to 95
°C
1, 3
Note:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions,
please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the
DRAM case temperature must be maintained between 0 to 85 °C under all operating conditions
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C case temperature. Full
specifications are supported in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 μs. It is also possible to specify
a component with 1X refresh (tREFI to 7.8μs) in the Extended Temperature Range. Please refer to supplier data sheet and/or the
DIMM SPD for option availability.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh
mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode
(MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option
availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range.
DC Electrical Characteristics and Operating Conditions
Symbol
Parameter
Min
Typ
Max
Units
Notes
VDD
Supply Voltage
1.425
1.5
1.575
V
1,2
VDDQ
Output Supply Voltage
1.425
1.5
1.575
V
1,2
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 9
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Single-Ended AC and DC Input Levels for Command and Address
Symbol
Parameter
DDR3-1066 (-BE)
DDR3-1333 (-CG)
Units
Note
Min.
Max.
Min.
Max.
VIH.CA(DC)
DC Input Logic High
Vref + 0.100
VDD
Vref + 0.100
VDD
V
1
VIL.CA(DC)
DC Input Logic Low
VSS
Vref - 0.100
VSS
Vref - 0.100
V
1
VIH.CA(AC)
AC Input Logic High
Vref + 0.175
Note 2
Vref + 0.175
Note 2
V
1, 2
VIL.CA(AC)
AC Input Logic Low
Note 2
Vref - 0.175
Note 2
Vref - 0.175
V
1, 2
VIH.CA(AC150)
AC Input Logic High
Vref + 0.150
Note 2
Vref + 0.150
Note 2
V
1, 2
VIL.CA(AC150)
AC Input Logic Low
Note 2
Vref - 0.150
Note 2
Vref - 0.150
V
1, 2
VRefCA(DC)
Reference Voltage for
ADD, CMD Inputs
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Note:
1. For input only pins except RESET#. Vref = VrefCA(DC).
2. See “Overshoot and Undershoot Specifications” in the device datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
Single-Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
DDR3-1066 (-BE)
DDR3-1333 (-CG)
Units
Note
Min.
Max.
Min.
Max.
VIH.DQ(DC)
DC Input Logic High
Vref + 0.100
VDD
Vref + 0.100
VDD
V
1
VIL.DQ(DC)
DC Input Logic Low
VSS
Vref - 0.100
VSS
Vref - 0.100
V
1
VIH.DQ(AC175)
AC Input Logic High
Vref + 0.175
Note 2
Vref + 0.15
Note 2
V
1, 2, 5
VIL.DQ(AC175)
AC Input Logic Low
Note 2
Vref - 0.175
Note 2
Vref - 0.150
V
1, 2, 5
VIH.DQ(AC150)
AC Input Logic High
Vref + 0.150
Note 2
Vref + 0.15
Note 2
V
1, 2, 5
VIL.DQ(AC150)
AC Input Logic Low
Note 2
Vref - 0.150
Note 2
Vref - 0.150
V
1, 2, 5
VRefDQ(DC)
Reference Voltage for
DQ, DM Inputs
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Note:
1. For input only pins except RESET#. Vref = VrefDQ(DC).
2. See “Overshoot and Undershoot Specifications” in the device datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. Single-ended swing requirement for DQS, DQS# is 350 mV (peak to peak). Differential swing requirement for DQS - DQS# is 700 mV
(peak to peak).
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 10
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
Symbol
Parameter/Condition
PC3-8500
(-BE)
PC3-10600
(-CG)
Unit
IDD0
Operating One Bank Active-Precharge Current
1364
1496
mA
IDD1
Operating One Bank Active-Read-Precharge Current
1540
1672
mA
IDD2P0
Precharge Power-Down Current Slow Exit
211
211
mA
IDD2P1
Precharge Power-Down Current Fast Exit
440
528
mA
IDD2Q
Precharge Quiet Standby Current
968
1056
mA
IDD2N
Precharge Standby Current
880
968
mA
IDD3P
Active Power-Down Current
528
616
mA
IDD3N
Active Standby Current
968
1056
mA
IDD4R
Operating Burst Read Current
1892
2288
mA
IDD4W
Operating Burst Write Current
1892
2200
mA
IDD5B
Burst Refresh Current
2420
2640
mA
IDD6
Self Refresh Current: Normal Temperature Range
176
176
mA
IDD7
Operating Bank Interleave Read Current
3916
4840
mA
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 11
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Standard Speed Bins
Symbol min max min max
tAA 13.125 20 13.5 20 ns
tRCD 13.125 -13.5 -ns
tRP 13.125 -13.5 -ns
tRC 50.625 -49.5 -ns
tRAS 37.5 9*tREFI 36 9*tREFI ns
CL CWL
6 5 tCK(avg) 2.5 3.3 2.5 3.3 ns
6 6 tCK(avg) ns
67,8 tCK(avg) ns
7 5 tCK(avg) ns
7 6 tCK(avg) 1.875 <2.5 ns
77,8 tCK(avg) ns
8 5 tCK(avg) ns
8 6 tCK(avg) 1.875 <2.5 1.875 <2.5 ns
8 7 tCK(avg) ns
95,6 tCK(avg) ns
9 7 tCK(avg) 1.5 <1.875 ns
9 8 tCK(avg) ns
nCK
nCK
Reserved
Reserved
Supported CWL settings
CL-nRCD-nRP
5,6
Supported CL settings
DDR3-1066 (-BE)
7-7-7
Reserved
DDR3-1333 (-CG)
9-9-9
6, 7, 8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6, 7, 8, 9
5,6,7
ACT to ACT or REF command period
ACT to PRE command period
Parameter
Internal read command to first data
ACT to internal read or write delay
PRE command period
Unit
Speed Bin
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 12
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Timing Specifications for DDR3 SDRAM Devices Used on Module
Unit
min max min max
Clock Timing
tCK(DLL_OF
Minimum Clock Cycle Time (DLL off mode) 8 - 8 - ns
tCK(avg)
Average Clock Period(Refer to "Standard Speed
tCH(avg) Average high pulse width 0.47 0.53 0.47 0.53 tCK(avg)
tCL(avg) Average low pulse width 0.47 0.53 0.47 0.53 tCK(avg)
tCK(abs) Absolute Clock Period
tCK(avg)min +
tJIT(per)min
tCK(avg)max +
tJIT(per)max
tCK(avg)min +
tJIT(per)min
tCK(avg)max +
tJIT(per)max
ps
tCH(abs) Absolute high pulse width 0.43 -0.43 -tCK(avg)
tCL(abs) Absolute low pulse width 0.43 -0.43 -tCK(avg)
JIT(per) Clock Period Jitter -90 90 -80 80 ps
tJIT(per,lck) Clock Period Jitter during DLL locking period -80 80 -70 70 ps
tJIT(cc) Cycle to Clcyle Period Jitter ps
tJIT(cc,lck) Cycle to Cycle Period Jitter ps
tERR(2per) Cumulative error accross 2 cycles -132 132 -118 118 ps
tERR(3per) Cumulative error accross 3 cycles -157 157 -140 140 ps
tERR(4per) Cumulative error accross 4cycles -175 175 -155 155 ps
tERR(5per) Cumulative error accross 5cycles -188 188 -168 168 ps
tERR(6per) Cumulative error accross 6 cycles -200 200 -177 177 ps
tERR(7per) Cumulative error accross 7 cycles -209 209 -186 186 ps
tERR(8per) Cumulative error accross 8 cycles -217 217 -193 193 ps
tERR(9per) Cumulative error accross 9 cycles -224 224 -200 200 ps
tERR(10per) Cumulative error accross 10 cycles -231 231 -205 205 ps
tERR(11per) Cumulative error accross 11 cycles -237 237 -210 210 ps
tERR(12per) Cumulative error accross 12 cycles -242 242 -215 215 ps
tERR(nper) Cumulative error accross n=13,14,..,49,50 cycles
tERR(npr)min =
(1+ 0.68In(n)) *
tJIT(per)min
tERR(npr)max =
(1+ 0.68In(n)) *
tJIT(per)max
tERR(npr)min
= (1+
0.68In(n)) *
tJIT(per)min
tERR(npr)max
= (1+
0.68In(n)) *
tJIT(per)max
ps
Data Timing
tDQSQ DQS, DQS to DQ skew per group, per access - 150 -125 ps
tQH DQ output hold time from DQS, DQS 0.38 -0.38 -tCK(avg)
tLZ(DQ) DQ low-impedence time from CK /  -600 300 -500 250 ps
tHZ(DQ) DQ high-impedence time from CK /  -300 -250 ps
tDS(base)
Data Setup time to DQS, DQS referenced to
Vih(ac)/ Vil(ac) levels
25 TBD ps
tDH(base)
Data Hold time to DQS, DQS referenced to Vih(dc)/
Vil(dc) levels
100 TBD ps
Data Strobe Timing
tRPRE DQS, DQS differential READ Preamble 0.9 Note 19 0.9 Note 19 tCK(avg)
tRPST DQS, DQS differential READ Postamble 0.3 Note 11 0.3 Note 11 tCK(avg)
tQSH DQS, DQS differential output high time 0.38 -0.4 -tCK(avg)
tQSL DQS, DQS differential output low time 0.38 -0.4 -tCK(avg)
tWPRE DQS, DQS differential WRITE Preamble 0.9 -0.9 -tCK(avg)
tWPST DQS, DQS differential WRITE Postamble 0.3 -0.3 -tCK(avg)
tDQSCK
DQS, DQS rising edge output access time from
rising CK, 
-300 300 -255 255 ps
tLZ(DQS)
DQS, DQS low-impedance time (Referenced from
-600 300 -500 250 ps
tHZ(DQS)
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
-300 -250 ps
tDQSL DQS, DQS differential input low pulse width 0.4 0.6 0.4 0.6 tCK(avg)
tDQSH DQS, DQS differential input high pulse width 0.4 0.6 0.4 0.6 tCK(avg)
tDQSS DQS, DQS rising edge to CK,  rising edge -0.25 0.25 -0.25 0.25 tCK(avg)
tDSS
DQS, DQS falling edge setup time to CK,  rising
edge
0.2 -0.2 - tCK(avg)
tDSH
DQS, DQS falling edge hold time to CK,  rising
0.2 -0.2 -tCK(avg)
Symbol
Parameter
140
DDR3-1066 (-BE)
DDR3-1333 (-CG)
180
160
160
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 13
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Unit
min max min max
Command and Address Timing
tDLLK DLL Locking time 512 -512 -nCK
tRTP
Internal READ command to PRECHARGE
Command delay
max(4nCK,
7.5ns)
-
max(4nCK,
7.5ns)
-
tWTR
Delay from start of internal write transaction to
internal read command
max(4nCK,
7.5ns)
-
max(4nCK,
7.5ns)
-
tWR WRITE recovery time 15 -15 -ns
tMRD Mode Register Set command cycle time 4 - 4 - nCK
tMOD Mode Register Set command update delay
max(12nCK,
15ns)
-
max(12nCK,
15ns)
-
tCCD CAS to CAS command delay 4 - 4 - nCK
tDAL Auto Precharge write recovery + precharge time nCK
tMPRR End of MPR Read burst to MSR for MPR (exit) 1 - nCK
tRAS
ACTIVE to PRECHARGE command period Refer to
"Standard Speed Bins"
tRRD
ACTIVE to ACTIVE command period (1k page size
-x4/x8)
max(4nCK,
7.5ns)
-
max(4nCK,
6ns)
-
tRRD
ACTIVE to ACTIVE command period (2k page size
-x16)
max(4nCK,
10ns)
-
max(4nCK,
7.5ns)
-
tFAW Four activate window (1k page size - x4/x8) 37.5 -30 0ns
tFAW Four activate window (2k page size - x16) 50 -45 0ns
tIS(base)
Command and Address setup time to CK, 
referenced Vih(ac) / Vil(ac) levels
125 65 ps
tIH(base)
Command and Address hold time from CK, 
referenced Vih(ac) / Vil(ac) levels
200 140 ps
tIS(base)
AC150
Commad and Address setup time to CK, 
referenced to Vih(ac) / Vil(ac) levels
- - 65+125 ps
Calibration Timing
tZQinit Power-up and RESET calibration time 512 -512 -nCK
tZQoper Normal operation Full calibration time 256 -256 -nCK
tZQCS normal operation Short calibration time 64 -64 -nCK
Reset Timing
tXPR Exit Reset from CKE HIGH to a valid command
max(5nCK,
tRFC(min)
+10ns)
-
max(5nCK,
tRFC(min)
+10ns)
-
Self RefreshTimings
tXS
Exit Self Refresh to Commands not requiring a
locked DLL
max(5nCK,
tRFC(min)
+10ns)
-
max(5nCK,
tRFC(min)
+10ns)
-
tXSDLL
Exit Self Refresh to Commands requiring a locked
tDLLK(min) - tDLLK(min) - nCK
tCKESR
Minimum CKE low width for Self Refresh entry to
exit timing
tCKE(min)+1nC
K
-
tCKE(min)+1n
CK
-
tCKSRE
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power Down Entry (PDE)
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
tCKSRX
Valid Clock Requirement before Self Refresh
Exit(SRX) or Power-Down Exit (PDX) or Reset Exit
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
Power Down Timings
tXP
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max(3nCK,
7.5ns)
-
max(3nCK,
6ns)
-
tXPDLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
max(10nCK,
24ns)
-
max(10nCK,
24ns)
-
tCKE CKE minimm pulse width
max(3nCK,
5.625ns)
-
max(3nCK,
5.625ns)
-
tCPDED Command Pass disable delay 1 - 1 - nCK
tPD Power Down Entry to Exit Timing tCKE(min) 9tREFI tCKE(min) 9tREFI
tACTPDEN Timing of ACT command to Power Down entry 1 - 1 - nCK
tPRPDEN
Timing of PRE or PREA command to Power Down
1 - 1 - nCK
tRDPDEN Timing of RD/RDA command to Power Down entry RL + 4 + 1 - RL + 4 + 1 - nCK
WR + roundup (tRP/tCK(avg))
WR + roundup (tRP/tCK(avg))
DDR3-1333 (-CG)
Symbol
Parameter
DDR3-1066 (-BE/-BF)
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 14
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Unit
min max min max
Command and Address Timing
tDLLK DLL Locking time 512 -512 -nCK
tRTP
Internal READ command to PRECHARGE
Command delay
max(4nCK,
7.5ns)
-
max(4nCK,
7.5ns)
-
tWTR
Delay from start of internal write transaction to
internal read command
max(4nCK,
7.5ns)
-
max(4nCK,
7.5ns)
-
tWR WRITE recovery time 15 -15 -ns
tMRD Mode Register Set command cycle time 4 - 4 - nCK
tMOD Mode Register Set command update delay
max(12nCK,
15ns)
-
max(12nCK,
15ns)
-
tCCD CAS to CAS command delay 4 - 4 - nCK
tDAL Auto Precharge write recovery + precharge time nCK
tMPRR End of MPR Read burst to MSR for MPR (exit) 1 - nCK
tRAS
ACTIVE to PRECHARGE command period Refer to
"Standard Speed Bins"
tRRD
ACTIVE to ACTIVE command period (1k page size
-x4/x8)
max(4nCK,
7.5ns)
-
max(4nCK,
6ns)
-
tRRD
ACTIVE to ACTIVE command period (2k page size
-x16)
max(4nCK,
10ns)
-
max(4nCK,
7.5ns)
-
tFAW Four activate window (1k page size - x4/x8) 37.5 -30 0ns
tFAW Four activate window (2k page size - x16) 50 -45 0ns
tIS(base)
Command and Address setup time to CK, 
referenced Vih(ac) / Vil(ac) levels
125 65 ps
tIH(base)
Command and Address hold time from CK, 
referenced Vih(ac) / Vil(ac) levels
200 140 ps
tIS(base)
AC150
Commad and Address setup time to CK, 
referenced to Vih(ac) / Vil(ac) levels
- - 65+125 ps
Calibration Timing
tZQinit Power-up and RESET calibration time 512 -512 -nCK
tZQoper Normal operation Full calibration time 256 -256 -nCK
tZQCS normal operation Short calibration time 64 -64 -nCK
Reset Timing
tXPR Exit Reset from CKE HIGH to a valid command
max(5nCK,
tRFC(min)
+10ns)
-
max(5nCK,
tRFC(min)
+10ns)
-
Self RefreshTimings
tXS
Exit Self Refresh to Commands not requiring a
locked DLL
max(5nCK,
tRFC(min)
+10ns)
-
max(5nCK,
tRFC(min)
+10ns)
-
tXSDLL
Exit Self Refresh to Commands requiring a locked
tDLLK(min) - tDLLK(min) - nCK
tCKESR
Minimum CKE low width for Self Refresh entry to
exit timing
tCKE(min)+1nC
K
-
tCKE(min)+1n
CK
-
tCKSRE
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power Down Entry (PDE)
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
tCKSRX
Valid Clock Requirement before Self Refresh
Exit(SRX) or Power-Down Exit (PDX) or Reset Exit
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
Power Down Timings
tXP
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max(3nCK,
7.5ns)
-
max(3nCK,
6ns)
-
tXPDLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
max(10nCK,
24ns)
-
max(10nCK,
24ns)
-
tCKE CKE minimm pulse width
max(3nCK,
5.625ns)
-
max(3nCK,
5.625ns)
-
tCPDED Command Pass disable delay 1 - 1 - nCK
tPD Power Down Entry to Exit Timing tCKE(min) 9tREFI tCKE(min) 9tREFI
tACTPDEN Timing of ACT command to Power Down entry 1 - 1 - nCK
tPRPDEN
Timing of PRE or PREA command to Power Down
1 - 1 - nCK
tRDPDEN Timing of RD/RDA command to Power Down entry RL + 4 + 1 - RL + 4 + 1 - nCK
WR + roundup (tRP/tCK(avg))
WR + roundup (tRP/tCK(avg))
DDR3-1333 (-CG)
Symbol
Parameter
DDR3-1066 (-BE)
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 15
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Package Dimensions
[NT2GC64B8HC0NF, 2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
FRONT
1.50 +/- 0.10
Detail A Detail B
0.80 +/- 0.05
BACK
3.80
4.00
1.00 Pitch
Detail A
9.50
133.35 +/- 0.15
Units: Millimeters
30.00 +0.5/-0.15
SIDE
4.00 Max.
1.27 +0.07/-0.10
17.30
5.175 47.00
Detail B
71.00
5.00
2.50
3.0 (x4)
Note: Device position and scale are only for reference.
Revision Log
PC3-8500 / PC3-10600
Un-buffered DDR3 SDRAM DIMM
NT2GC64B8HC0NF
REV 1.0 16
12/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Rev
Date
Modification
0.1
10/2009
Preliminary Release
1.0
12/2009
Official Release
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
Please visit our home page for more information: www.nanya.com
Printed in Taiwan
© 2009