[ /Title (CD74 HC123 , CD74 HCT12 3, CD74 HC423 , CD74 HCT42 3) /Subject (High Speed CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Data sheet acquired from Harris Semiconductor SCHS142B September 1997 - Revised March 2002 High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets Features Description * Overriding Reset Terminates Output Pulse The 'HC123, 'HCT123, CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the 423 types do not have this feature. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and CX provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses. * Triggering From the Leading or Trailing Edge * Q and Q Buffered Outputs * Separate Resets * Wide Range of Output-Pulse Widths * Schmitt Trigger on Both A and B Inputs * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Once triggered, the output pulse width may be extended by retriggering inputs A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A) and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A, B, and R) must be terminated high or low. * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V The minimum value of external resistance, Rx is typically 5k. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.45 RXCX at VCC = 5V. Ordering Information * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH PART NUMBER Pinout CD54HC123, CD54HCT123 (CERDIP) CD74HC123 (PDIP, SOIC, SOP) CD74HCT123, CD74HC423, CD74HCT423 (PDIP, SOIC) TOP VIEW TEMP. RANGE (oC) PACKAGE CD54HC123F -55 to 125 16 Ld CERDIP CD54HC123F3A -55 to 125 16 Ld CERDIP CD74HC123E -55 to 125 16 Ld PDIP CD74HC123M -55 to 125 16 Ld SOIC CD74HC123NSR -55 to 125 16 Ld SOP CD54HCT123F3A -55 to 125 16 Ld CERDIP CD74HCT123E -55 to 125 16 Ld PDIP CD74HCT123M -55 to 125 16 Ld SOIC 1A 1 16 VCC CD74HC423E -55 to 125 16 Ld PDIP 1B 2 15 1RXCX CD74HC423M -55 to 125 16 Ld SOIC 1R 3 14 1CX CD74HCT423E -55 to 125 16 Ld PDIP 1Q 4 13 1Q 2Q 5 12 2Q CD74HCT423M -55 to 125 16 Ld SOIC 2CX 6 11 2R 2RXCX 7 10 2B GND 8 9 2A NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) 2002, Texas Instruments Incorporated 1 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Functional Diagram 1Cx 14 1Rx VCC 15 1Cx 1RxCx 13 1A 1Q 1 MONO 1 4 1B 1Q 2 1R 2R 3 11 5 9 2Q 2A MONO 2 10 12 2B 2Q 2Cx 2RxCx 6 7 2Cx VCC 2Rx TRUTH TABLE INPUTS A OUTPUTS B R Q Q H X H L H X L H L H L H H H X X L L H L H H X H L H X L H L H L H H H X X L L H CD74HC/HCT123 CD74HC/HCT423 NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care. 2 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .50mA Package Thermal Impedance, JA (see Note 3): PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - 0.1 - 1 - 1 A ICC VCC or GND 0 6 - - 8 - 80 - 160 A 3 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 0.1 - 1 - 1 A HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 A ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 A NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS All 0.35 NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g. 360A max at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER SYMBOL -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 2 100 - - 125 - - 150 - - ns 4.5 20 - - 25 - - 30 - - ns 6 17 - - 21 - - 26 - - ns 2 100 - - 125 - - 150 - - ns 4.5 20 - - 25 - - 30 - - ns 6 17 - - 21 - - 26 - - ns HC TYPES Minimum Input, Pulse Width tWL A B tWH 4 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER R A and B Hold Time Reset Removal Time Retrigger Time Number -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS tWL 2 100 - - 125 - - 150 - 150 ns 4.5 20 - - 25 - - 30 - 30 ns 6 17 - - 21 - - 26 - 26 ns 2 50 - - 65 - - 75 - 75 ns 4.5 10 - - 13 - - 15 - 15 ns 6 9 - - 11 - - 13 - 13 ns 2 50 - - 65 - - 75 - 75 ns 4.5 10 - - 13 - - 15 - 15 ns 6 9 - - 11 - - 13 - 13 ns 5 - - - - - - - - - ns - 50 - - 63 - - 76 - ns 40 - 50 38.7 - 51.3 38.2 - 51.8 s tH tREM trT RX = 10K, CX = 0 Output Pulse Width -40oC TO 85oC tW 5 Q or Q RX = 10K, CX = 10nF HCT TYPES Minimum Input, Pulse Width tWL 5 A 20 - - 25 - - 30 - - ns B tWH 20 - - 25 - - 30 - - ns R tWL 20 - - 25 - - 30 - - ns - - ns - ns A and B Hold Time tH 5 10 - - 13 - - 15 tREM 5 10 - - 13 - - 15 RX = 10K, CX = 0 trT 5 - 50 - - 63 - - 76 - ns Output Pulse Width Q or Q tW 5 40 - 50 38.7 - 51.3 38.2 - 51.8 s Reset Removal Time Retrigger Time Number (Note 4) RX = 10K, CX = 10nF NOTE: 4. Time to trigger depends on the values of RX and CX. The output pulse width can only be extended when the time between the activegoing edges of the trigger input pulses meet the minimum retrigger time requirement. 5 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Switching Specifications CL = 50pF, Input tr, tf = 6ns, RX = 10K, CX = 0 -40oC TO 85oC 25oC PARAMETER SYMBOL TEST CONDITIONS tPHL CL = 50pF -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 300 - 375 - 450 ns 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - - - - ns CL = 50pF 6 - - 51 - 64 - 76 ns CL = 50pF 2 - - 320 - 400 - 480 ns 4.5 - - 64 - 80 - 96 ns CL = 15pF 5 - 26 - - - - - ns CL = 50pF 6 - - 54 - 68 - 82 ns CL = 50pF 2 - - 215 - 270 - 325 ns 4.5 - - 43 - 54 - 65 ns 6 - - 37 - 46 - 55 ns 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns - 45 - - - - - s - 2 - - - - - % HC TYPES Trigger Propagation Delay A, B, R to Q A, B, R to Q Reset Propagation Delay tPHL tPHL, tPLH R to Q or Q Output Transition Time Output Pulse Width tTHL, tTLH - CL = 50pF - 5 RX = 10K, CX = 10pF Pulse Width Match Between Circuits In the Same Package - - 5 RX = 10K, CX = 10pF Power Dissipation Capacitance (Notes 5, 6) CPD CL = 15pF 5 - - - - - - - pF Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF NOTES: 5. CPD is used to determine the dynamic power consumption, per multivibrator. 6. PD = (CPD + CX) VCC2 fi (CL VCC2 fO) where fi = input frequency, fO = Output Frequency, CL = Output Load Capacitance, I CX = External Capacitance VCC = Supply Voltage assuming fi -----tW 6 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Test Circuits and Waveforms A B = LOW A A = HIGH B = LOW A = HIGH B B R R VS VS tW tW tW VS Q VS Q tW tW tW FIGURE 1. OUTPUT PULSE CONTROL USING RESET INPUT (R) PULSE FOR 123 tW FIGURE 2. OUTPUT PULSE CONTROL USING RESET INPUT (R) FOR 423 A B tW B (R = HIGH) A trT Q VS tW tW tW NOTE: Output pulse control using retrigger pulse for 123 and 423. 8 6 4 2 0.9 EXTERNAL CAPACITANCE (CX) = 10nF 0.8 103 8 6 4 2 102 101 0k RX 0k 8 6 4 2 RX 8 6 4 2 103 = =1 4 68 2 4 68 2 4 68 2 105 104 106 EXTERNAL CAPACITANCE (CX) - pF 0.6 HCT 0.5 0.4 0.3 DC SUPPLY VOLTAGE (VCC) = 5V AMBIENT TEMPERATURE (TA) = 25oC 2 EXTERNAL RESISTANCE (RX) = 10k TO 100k AMBIENT TEMPERATURE (TA) = 25oC 0.7 10 "K" FACTOR OUTPUT PULSE WIDTH (s) FIGURE 3. TRIGGERING OF ONE SHOT BY INPUT A OR INPUT B FOR A PERIOD tW 0.2 0.1 4 68 107 FIGURE 4. TYPICAL OUTPUT PULSE WIDTH AS A FUNCTION OF CX FOR RX = 10k AND 100k 1 2 3 4 5 6 7 8 9 DC SUPPLY VOLTAGE (VCC) - VOLTS 10 11 FIGURE 5. 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